1 | /**************************************************************************//**
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2 | * @file irq_ctrl.h
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3 | * @brief Interrupt Controller API header file
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4 | * @version V1.0.0
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5 | * @date 23. June 2017
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6 | ******************************************************************************/
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7 | /*
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8 | * Copyright (c) 2017 ARM Limited. All rights reserved.
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9 | *
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10 | * SPDX-License-Identifier: Apache-2.0
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11 | *
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12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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13 | * not use this file except in compliance with the License.
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14 | * You may obtain a copy of the License at
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15 | *
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16 | * www.apache.org/licenses/LICENSE-2.0
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17 | *
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18 | * Unless required by applicable law or agreed to in writing, software
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19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 | * See the License for the specific language governing permissions and
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22 | * limitations under the License.
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23 | */
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24 |
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25 | #if defined ( __ICCARM__ )
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26 | #pragma system_include /* treat file as system include file for MISRA check */
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27 | #elif defined (__clang__)
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28 | #pragma clang system_header /* treat file as system include file */
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29 | #endif
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30 |
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31 | #ifndef IRQ_CTRL_H_
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32 | #define IRQ_CTRL_H_
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33 |
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34 | #include <stdint.h>
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35 |
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36 | #ifndef IRQHANDLER_T
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37 | #define IRQHANDLER_T
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38 | /// Interrupt handler data type
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39 | typedef void (*IRQHandler_t) (void);
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40 | #endif
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41 |
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42 | #ifndef IRQN_ID_T
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43 | #define IRQN_ID_T
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44 | /// Interrupt ID number data type
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45 | typedef int32_t IRQn_ID_t;
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46 | #endif
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47 |
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48 | /* Interrupt mode bit-masks */
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49 | #define IRQ_MODE_TRIG_Pos (0U)
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50 | #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
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51 | #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
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52 | #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
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53 | #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
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54 | #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
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55 | #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
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56 | #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
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57 | #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
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58 |
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59 | #define IRQ_MODE_TYPE_Pos (3U)
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60 | #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
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61 | #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
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62 | #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
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63 |
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64 | #define IRQ_MODE_DOMAIN_Pos (4U)
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65 | #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
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66 | #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
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67 | #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
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68 |
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69 | #define IRQ_MODE_CPU_Pos (5U)
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70 | #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
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71 | #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
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72 | #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
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73 | #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
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74 | #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
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75 | #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
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76 | #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
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77 | #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
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78 | #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
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79 | #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
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80 |
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81 | #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
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82 |
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83 | /* Interrupt priority bit-masks */
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84 | #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
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85 | #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
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86 |
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87 | /// Initialize interrupt controller.
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88 | /// \return 0 on success, -1 on error.
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89 | int32_t IRQ_Initialize (void);
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90 |
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91 | /// Register interrupt handler.
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92 | /// \param[in] irqn interrupt ID number
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93 | /// \param[in] handler interrupt handler function address
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94 | /// \return 0 on success, -1 on error.
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95 | int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
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96 |
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97 | /// Get the registered interrupt handler.
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98 | /// \param[in] irqn interrupt ID number
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99 | /// \return registered interrupt handler function address.
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100 | IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
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101 |
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102 | /// Enable interrupt.
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103 | /// \param[in] irqn interrupt ID number
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104 | /// \return 0 on success, -1 on error.
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105 | int32_t IRQ_Enable (IRQn_ID_t irqn);
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106 |
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107 | /// Disable interrupt.
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108 | /// \param[in] irqn interrupt ID number
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109 | /// \return 0 on success, -1 on error.
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110 | int32_t IRQ_Disable (IRQn_ID_t irqn);
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111 |
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112 | /// Get interrupt enable state.
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113 | /// \param[in] irqn interrupt ID number
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114 | /// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
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115 | uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
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116 |
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117 | /// Configure interrupt request mode.
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118 | /// \param[in] irqn interrupt ID number
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119 | /// \param[in] mode mode configuration
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120 | /// \return 0 on success, -1 on error.
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121 | int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
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122 |
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123 | /// Get interrupt mode configuration.
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124 | /// \param[in] irqn interrupt ID number
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125 | /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
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126 | uint32_t IRQ_GetMode (IRQn_ID_t irqn);
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127 |
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128 | /// Get ID number of current interrupt request (IRQ).
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129 | /// \return interrupt ID number.
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130 | IRQn_ID_t IRQ_GetActiveIRQ (void);
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131 |
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132 | /// Get ID number of current fast interrupt request (FIQ).
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133 | /// \return interrupt ID number.
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134 | IRQn_ID_t IRQ_GetActiveFIQ (void);
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135 |
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136 | /// Signal end of interrupt processing.
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137 | /// \param[in] irqn interrupt ID number
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138 | /// \return 0 on success, -1 on error.
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139 | int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
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140 |
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141 | /// Set interrupt pending flag.
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142 | /// \param[in] irqn interrupt ID number
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143 | /// \return 0 on success, -1 on error.
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144 | int32_t IRQ_SetPending (IRQn_ID_t irqn);
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145 |
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146 | /// Get interrupt pending flag.
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147 | /// \param[in] irqn interrupt ID number
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148 | /// \return 0 - interrupt is not pending, 1 - interrupt is pending.
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149 | uint32_t IRQ_GetPending (IRQn_ID_t irqn);
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150 |
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151 | /// Clear interrupt pending flag.
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152 | /// \param[in] irqn interrupt ID number
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153 | /// \return 0 on success, -1 on error.
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154 | int32_t IRQ_ClearPending (IRQn_ID_t irqn);
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155 |
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156 | /// Set interrupt priority value.
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157 | /// \param[in] irqn interrupt ID number
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158 | /// \param[in] priority interrupt priority value
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159 | /// \return 0 on success, -1 on error.
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160 | int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
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161 |
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162 | /// Get interrupt priority.
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163 | /// \param[in] irqn interrupt ID number
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164 | /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
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165 | uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
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166 |
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167 | /// Set priority masking threshold.
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168 | /// \param[in] priority priority masking threshold value
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169 | /// \return 0 on success, -1 on error.
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170 | int32_t IRQ_SetPriorityMask (uint32_t priority);
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171 |
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172 | /// Get priority masking threshold
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173 | /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
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174 | uint32_t IRQ_GetPriorityMask (void);
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175 |
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176 | /// Set priority grouping field split point
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177 | /// \param[in] bits number of MSB bits included in the group priority field comparison
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178 | /// \return 0 on success, -1 on error.
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179 | int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
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180 |
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181 | /// Get priority grouping field split point
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182 | /// \return current number of MSB bits included in the group priority field comparison with
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183 | /// optional IRQ_PRIORITY_ERROR bit set.
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184 | uint32_t IRQ_GetPriorityGroupBits (void);
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185 |
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186 | #endif // IRQ_CTRL_H_
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