[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000,2001 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2001 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | * Copyright (C) 2002-2004 by Hokkaido Industrial Research Institute, JAPAN
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| 11 | *
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| 12 | * ä¸è¨èä½æ¨©è
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| 13 | ã¯ï¼Free Software Foundation ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã
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| 15 | * GNU General Public License ã® Version 2 ã«è¨è¿°ããã¦ããæ¡ä»¶ãï¼ä»¥
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| 16 | * ä¸ã®æ¡ä»¶ã®ãããããæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§
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| 17 | * ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 18 | å¸ï¼ä»¥ä¸ï¼
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| 19 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 20 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 21 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 22 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 23 | * (2) æ¬ã½ããã¦ã§ã¢ãåå©ç¨å¯è½ãªãã¤ããªã³ã¼ãï¼ãªãã±ã¼ã¿ãã«ãªã
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| 24 | * ã¸ã§ã¯ããã¡ã¤ã«ãã©ã¤ãã©ãªãªã©ï¼ã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼å©ç¨
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| 25 | * ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 26 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼
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| 27 | * ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 28 | * (3) æ¬ã½ããã¦ã§ã¢ãåå©ç¨ä¸å¯è½ãªãã¤ããªã³ã¼ãã®å½¢ã¾ãã¯æ©å¨ã«çµ
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| 29 | * ã¿è¾¼ãã å½¢ã§å©ç¨ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºãããã¨ï¼
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| 30 | * (a) å©ç¨ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 31 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½
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| 32 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 33 | * (b) å©ç¨ã®å½¢æ
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| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼ä¸è¨èä½æ¨©è
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| 35 | ã«å ±åãã
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| 36 | * ãã¨ï¼
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| 37 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 38 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 39 | ãå
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| 40 | 責ãããã¨ï¼
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| 41 | *
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| 42 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 43 | ã¯ï¼
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| 44 | * æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ã
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| 45 | * ãªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çããã
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| 46 | * ããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 47 | *
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| 48 | * @(#) $Id: sh7615.h,v 1.5 2005/07/06 00:45:07 honda Exp $
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| 49 | */
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| 50 |
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| 51 | #ifndef _SH7615_H_
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| 52 | #define _SH7615_H_
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| 53 |
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| 54 | #include <sil.h>
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| 55 |
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| 56 | /*
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| 57 | * å²è¾¼ã¿ã®ãã¯ã¿çªå·å®ç¾©
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| 58 | */
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| 59 | #define GII 4 /* ä¸è¬ä¸å½å½ä»¤:General Illegal Instruction */
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| 60 | #define SII 6 /* ã¹ãããä¸å½å½ä»¤:Slot Illegal Instruction */
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| 61 | #define CAE 9 /* CPUã¢ãã¬ã¹ã¨ã©ã¼:CPU Address Error */
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| 62 | #define DAE 10 /* DMAã¢ãã¬ã¹ã¨ã©ã¼:DMA Address Error */
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| 63 |
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| 64 | #define NMI 11 /* NMI */
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| 65 | #define USBK 12 /* ã¦ã¼ã¶ã¼ãã¬ã¼ã¯ */
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| 66 | #define HUDI 13 /* ã¦ã¼ã¶ã¼ãããã°ã¤ã³ã¿ã¼ãã§ã¼ã¹ */
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| 67 | /* å¤é¨ãã¯ã¿çªå·ãæå®ããå ´åãåå®ç¾©ãå¥ã«å®ç¾©ãã */
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| 68 | #define IRQ0 64 /* å¤é¨å²è¾¼ã¿è¦æ± */
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| 69 | #define IRQ1 65
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| 70 | #define IRQ2 66
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| 71 | #define IRQ3 67
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| 72 | #define IRL1 64
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| 73 | #define IRL2 65
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| 74 | #define IRL3 65
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| 75 | #define IRL4 66
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| 76 | #define IRL5 66
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| 77 | #define IRL6 67
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| 78 | #define IRL7 67
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| 79 | #define IRL8 68
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| 80 | #define IRL9 68
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| 81 | #define IRL10 69
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| 82 | #define IRL11 69
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| 83 | #define IRL12 70
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| 84 | #define IRL13 70
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| 85 | #define IRL14 71
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| 86 | #define IRL15 71
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| 87 |
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| 88 | /* ãã¯ã¿çªå·ãèªç±ã«æå®ããå ´åãåå®ç¾©ãå¥ã«å®ç¾©ãã */
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| 89 | /* DMAC:ãã¤ã¬ã¯ãã¡ã¢ãªã¢ã¯ã»ã¹ã³ã³ããã¼ã© */
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| 90 | #define DMAC0 72 /* DMAC0 */
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| 91 | #define DMAC1 73 /* DMAC1 */
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| 92 |
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| 93 | #define ITI 74 /* WDT:ã¦ã©ããããã¯ã¿ã¤ã */
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| 94 | #define CMI 75 /* REF:DRAMãªãã¬ãã·ã¥å¶å¾¡ */
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| 95 | #define EINT 76 /* EINT:EtherCå²ã込㿠*/
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| 96 |
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| 97 | /* FRT:ããªã¼ã©ã³ãã³ã°ã¿ã¤ã */
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| 98 | #define ICI 77 /* FRT */
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| 99 | #define OCI 78
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| 100 | #define OVI 79
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| 101 |
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| 102 | /* TPU:ã¿ã¤ããã«ã¹ã¦ããã */
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| 103 | #define TGI0A 80 /* TPU0 */
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| 104 | #define TGI0B 81
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| 105 | #define TGI0C 82
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| 106 | #define TGI0D 83
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| 107 | #define TCI0V 84
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| 108 | #define TGI1A 85 /* TPU1 */
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| 109 | #define TGI1B 86
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| 110 | #define TCI1V 87
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| 111 | #define TCI1U 88
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| 112 | #define TGI2A 89 /* TPU2 */
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| 113 | #define TGI2B 90
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| 114 | #define TCI2V 91
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| 115 | #define TCI2U 92
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| 116 |
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| 117 | /* SCIF:ã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ã¼ãã§ã¼ã¹ */
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| 118 | #define ERI1 93 /* SCI1 */
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| 119 | #define RXI1 94
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| 120 | #define BRI1 95
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| 121 | #define TXI1 96
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| 122 | #define ERI2 97 /* SCI2 */
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| 123 | #define RXI2 98
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| 124 | #define BRI2 99
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| 125 | #define TXI2 100
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| 126 |
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| 127 | /* SIO:ã·ãªã¢ã«I/O */
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| 128 | #define EREI0 101 /* SCI0 */
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| 129 | #define TERI0 102
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| 130 | #define RDFI0 103
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| 131 | #define TDEI0 104
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| 132 | #define EREI1 105 /* SCI1 */
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| 133 | #define TERI1 106
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| 134 | #define RDFI1 107
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| 135 | #define TDEI1 108
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| 136 | #define EREI2 109 /* SCI2 */
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| 137 | #define TERI2 110
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| 138 | #define RDFI2 111
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| 139 | #define TDEI2 112
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| 140 |
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| 141 |
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| 142 |
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| 143 | #ifndef _MACRO_ONLY
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| 144 |
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| 145 | /*
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| 146 | * SH2ã®å
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| 147 | é¨ã¬ã¸ã¹ã¿å®ç¾©
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| 148 | */
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| 149 |
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| 150 | /* ã¬ã¸ã¹ã¿ã®ã¢ã¯ã»ã¹ã¯åå32bitå¹
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| 151 | */
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| 152 | /*
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| 153 | * ãã¹ã¹ãã¼ãã³ã³ããã¼ã©
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| 154 | */
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| 155 | /* ãã¹ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ */
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| 156 | #define BCR1 ((VW *)0xffffffe0)
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| 157 | #define BCR2 ((VW *)0xffffffe4)
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| 158 | #define BCR3 ((VW *)0xfffffffc)
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| 159 | /* ã¦ã§ã¤ãã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ */
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| 160 | #define WCR1 ((VW *)0xffffffe8)
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| 161 | #define WCR2 ((VW *)0xffffffc0)
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| 162 | #define WCR3 ((VW *)0xffffffc4)
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| 163 | /* åå¥ã¡ã¢ãªã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ */
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| 164 | #define MCR ((VW *)0xffffffec)
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| 165 | /* ãªãã¬ãã·ã¥ã¿ã¤ãã³ã³ããã¼ã«/ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ */
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| 166 | #define RTCSR ((VW *)0xfffffff0)
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| 167 | /* ãªãã¬ãã·ã¥ã¿ã¤ãã«ã¦ã³ã¿ */
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| 168 | #define RTCNT ((VW *)0xfffffff4)
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| 169 | /* ãªãã¬ãã·ã¥ã¿ã¤ã ã³ã³ã¹ã¿ã³ãã¬ã¸ã¹ã¿ */
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| 170 | #define RTCOR ((VW *)0xfffffff8)
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| 171 | /*-----å
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| 172 | é¨çºæ¯åè·¯-----*/
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| 173 | #define FMR ((VB *)0xfffffe90)
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| 174 |
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| 175 | /*
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| 176 | * ãã³ãã¡ã³ã¯ã·ã§ã³ã³ã³ããã¼ã©
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| 177 | */
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| 178 | #define PACR ((VH *)0xfffffc80) /* ãã¼ãA ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ */
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| 179 | #define PAIOR ((VH *)0xfffffc82) /* ãã¼ãA I/Oã¬ã¸ã¹ã¿ */
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| 180 | #define PBCR ((VH *)0xfffffc88) /* ãã¼ãB ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ */
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| 181 | #define PBIOR ((VH *)0xfffffc8a) /* ãã¼ãB I/Oã¬ã¸ã¹ã¿ */
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| 182 | #define PBCR2 ((VH *)0xfffffc8e) /* ãã¼ãB ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿2 */
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| 183 | #define PADR ((VH *)0xfffffc84) /* ãã¼ãA ãã¼ã¿ã¬ã¸ã¹ã¿ */
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| 184 | #define PBDR ((VH *)0xfffffc8c) /* ãã¼ãB ãã¼ã¿ã¬ã¸ã¹ã¿ */
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| 185 |
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| 186 | /* å²ãè¾¼ã¿åªå
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| 187 | 度ã¬ãã«è¨å®ã¬ã¸ã¹ã¿ */
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| 188 | #define IPRA ((VH *)0xfffffee2)
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| 189 | #define IPRB ((VH *)0xfffffe60)
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| 190 | #define IPRC ((VH *)0xfffffee6)
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| 191 | #define IPRD ((VH *)0xfffffe40)
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| 192 | #define IPRE ((VH *)0xfffffec0)
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| 193 | /* ãã¯ã¿çªå·è¨å®ã¬ã¸ã¹ã¿ */
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| 194 | #define VCRA ((VH *)0xfffffe62)
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| 195 | #define VCRB ((VH *)0xfffffe64)
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| 196 | #define VCRC ((VH *)0xfffffe66)
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| 197 | #define VCRD ((VH *)0xfffffe68)
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| 198 | #define VCRE ((VH *)0xfffffe42)
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| 199 | #define VCRF ((VH *)0xfffffe44)
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| 200 | #define VCRG ((VH *)0xfffffe46)
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| 201 | #define VCRH ((VH *)0xfffffe48)
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| 202 | #define VCRI ((VH *)0xfffffe4a)
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| 203 | #define VCRJ ((VH *)0xfffffe4c)
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| 204 | #define VCRK ((VH *)0xfffffe4e)
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| 205 | #define VCRL ((VH *)0xfffffe50)
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| 206 | #define VCRM ((VH *)0xfffffe52)
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| 207 | #define VCRN ((VH *)0xfffffe54)
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| 208 | #define VCRO ((VH *)0xfffffe56)
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| 209 | #define VCRP ((VH *)0xfffffec2)
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| 210 | #define VCRQ ((VH *)0xfffffec4)
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| 211 | #define VCRR ((VH *)0xfffffec6)
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| 212 | #define VCRS ((VH *)0xfffffec8)
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| 213 | #define VCRT ((VH *)0xfffffeca)
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| 214 | #define VCRU ((VH *)0xfffffecc)
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| 215 | #define VCRWDT ((VH *)0xfffffee4)
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| 216 | #define DMA_VCRDMA0 ((VW *)0xffffffa0)
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| 217 | #define DMA_VCRDMA1 ((VW *)0xffffffa8)
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| 218 | /* å²ãè¾¼ã¿ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ */
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| 219 | #define ICR ((VH *)0xfffffee0)
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| 220 | /* å²ãè¾¼ã¿ã³ã³ããã¼ã«/ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ */
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| 221 | #define IRQCSR ((VH *)0xfffffee8)
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| 222 |
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| 223 | /*
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| 224 | * å²ãè¾¼ã¿ã³ã³ããã¼ã©ã®åæå
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| 225 | */
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| 226 | Inline void
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| 227 | sh2_init_intcontorller (void)
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| 228 | {
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| 229 | sil_wrh_mem (IPRA, 0x0000);
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| 230 | sil_wrh_mem (IPRB, 0x0000);
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| 231 | sil_wrh_mem (IPRC, 0x0000);
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| 232 | sil_wrh_mem (IPRD, 0x0000);
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| 233 | sil_wrh_mem (IPRE, 0x0000);
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| 234 | }
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| 235 |
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| 236 | #endif /* _MACRO_ONLY */
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| 237 |
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| 238 | #endif /* _SH7615_H_ */
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