[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2001-2004 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | * Copyright (C) 2002-2004 by Hokkaido Industrial Research Institute, JAPAN
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| 11 | * Copyright (C) 2006 by GJ Business Division RICOH COMPANY,LTD. JAPAN
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| 12 | *
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| 13 | * ä¸è¨èä½æ¨©è
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| 14 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 15 | * ã«ãã£ã¦å
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| 16 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 17 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 18 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 19 | å¸ï¼ä»¥ä¸ï¼
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| 20 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 21 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 22 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 23 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 24 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼åé
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| 27 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 28 | * è
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| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 30 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 31 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 32 | * ç¨ã§ããªãå½¢ã§åé
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| 33 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 34 | * ã¨ï¼
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| 35 | * (a) åé
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| 36 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 37 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 38 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 39 | * (b) åé
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| 40 | å¸ã®å½¢æ
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| 41 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 42 | * å ±åãããã¨ï¼
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| 43 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 44 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 45 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 46 | 責ãããã¨ï¼
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| 47 | *
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| 48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 49 | ã
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| 50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 51 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 52 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 53 | *
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| 54 | * @(#) $Id$
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| 55 | */
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| 56 |
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| 57 |
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| 58 | #include "jsp_kernel.h"
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| 59 | #include "sh7047.h"
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| 60 | #include <sil.h>
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| 61 |
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| 62 | void hardware_init_hook(void)
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| 63 | {
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| 64 | unsigned long *p = (unsigned long *)SRAM_START;
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| 65 |
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| 66 | /* initial Module Standby register */
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| 67 | sil_wrh_mem((VP)(IOREG_MST_BASE+IOREG_CR1_OFFSET), 0xf023); /* sci4,sci3,sci2 */
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| 68 | sil_wrh_mem((VP)(IOREG_MST_BASE+IOREG_CR2_OFFSET), 0xe0f0); /* cmt */
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| 69 |
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| 70 | /* initial base state */
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| 71 | sil_wrh_mem((VP)(IOREG_BSC_BASE+IOREG_BCR1_OFFSET), 0x600e);/* CS0:8bit */
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| 72 | sil_wrh_mem((VP)(IOREG_BSC_BASE+IOREG_BCR2_OFFSET), 0xffff);/* CS0:idle cycle 3*/
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| 73 | sil_wrh_mem((VP)(IOREG_BSC_BASE+IOREG_WCR1_OFFSET), 0xfff2);/* CS0 2Wait */
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| 74 |
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| 75 | /* IOãã¼ãè¨å® */
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| 76 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PACRL1_OFFSET), 0x1115); /* 0001 0001 0001 0101 */
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| 77 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PACRL2_OFFSET), 0x4000); /* 0100 0000 0000 0000 */ /* PA6 */
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| 78 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PACRL3_OFFSET), 0x03bf); /* 0000 0011 1011 1111 */ /* PA6 */
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| 79 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PAIORL_OFFSET), 0x5ebf); /* 0101 1110 1011 1111 */
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| 80 |
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| 81 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PBCR1_OFFSET), 0x2c00); /* 0010 1100 0000 0000 */ /* TXD4,RXD4 */
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| 82 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PBCR2_OFFSET), 0x04f5); /* 0000 0100 1111 0101 */ /* TXD4,RXD4 */
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| 83 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PBIOR_OFFSET), 0x0023); /* 0000 0000 0010 0011 */ /* TXD4,RXD4 */
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| 84 |
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| 85 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PDCRL1_OFFSET), 0x00ff); /* 0000 0000 1111 1111 */
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| 86 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PDCRL2_OFFSET), 0x0000); /* 0000 0000 0000 0000 */
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| 87 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PDIORL_OFFSET), 0x0000); /* 0000 0000 0000 0000 */
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| 88 |
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| 89 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PECRH_OFFSET), 0x0fff); /* 0000 1111 1111 1111 */
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| 90 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PECRL1_OFFSET), 0x0000); /* 0000 0000 0000 0000 */
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| 91 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PECRL2_OFFSET), 0xff00); /* 1111 1111 0000 0000 */
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| 92 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PEIORH_OFFSET), 0x003f); /* 0000 0000 0011 1111 */
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| 93 | sil_wrh_mem((VP)(IOREG_PFC_BASE+IOREG_PEIORL_OFFSET), 0x00f0); /* 0000 0000 1111 0000 */
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| 94 |
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| 95 | /* SRAM clear */
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| 96 | while(p < (unsigned long *)SRAM_END){
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| 97 | *p++ = 0L;
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| 98 | }
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| 99 | }
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| 100 |
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| 101 | /*
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| 102 | * å²ãè¾¼ã¿ã³ã³ããã¼ã©ã®åæå
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| 103 | */
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| 104 | void sh2_init_intcontorller (void)
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| 105 | {
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| 106 | sil_wrh_mem((VP)(IOREG_INTC_BASE+IOREG_IPRA_OFFSET), 0x0000);
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| 107 | sil_wrh_mem((VP)(IOREG_INTC_BASE+IOREG_IPRD_OFFSET), 0x0000);
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| 108 | sil_wrh_mem((VP)(IOREG_INTC_BASE+IOREG_IPRE_OFFSET), 0x0000);
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| 109 | sil_wrh_mem((VP)(IOREG_INTC_BASE+IOREG_IPRF_OFFSET), 0x0000);
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| 110 | sil_wrh_mem((VP)(IOREG_INTC_BASE+IOREG_IPRG_OFFSET), 0x0000);
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| 111 | sil_wrh_mem((VP)(IOREG_INTC_BASE+IOREG_IPRH_OFFSET), 0x0000);
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| 112 | }
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| 113 |
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