[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | *
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| 9 | * Copyright (C) 2004 by SEIKO EPSON Corp, JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | */
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| 53 |
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| 54 | /*
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| 55 | * ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
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| 56 | */
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| 57 | #ifndef _S1C33_H_
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| 58 | #define _S1C33_H_
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| 59 |
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| 60 | /*
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| 61 | * æ±ç¨ã¬ã¸ã¹ã¿æ°
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| 62 | */
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| 63 | #define S1C33_GR_NUM 16
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| 64 |
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| 65 | /*
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| 66 | * PSR
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| 67 | */
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| 68 | #define S1C33_PSR_INITIAL 0x00000000
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| 69 | #define S1C33_PSR_MASK_IL 0x00000F00
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| 70 | #define S1C33_PSR_FLAG_IE 0x00000010
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| 71 |
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| 72 | /*
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| 73 | * åºæ¬ã¡ã¢ãªããã
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| 74 | */
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| 75 | #define S1C33_AREA00_BASE 0x00000000
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| 76 | #define S1C33_AREA01_BASE 0x00040000
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| 77 | #define S1C33_AREA02_BASE 0x00060000
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| 78 | #define S1C33_AREA03_BASE 0x00080000
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| 79 | #define S1C33_AREA04_BASE 0x00100000
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| 80 | #define S1C33_AREA05_BASE 0x00200000
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| 81 | #define S1C33_AREA06_BASE 0x00300000
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| 82 | #define S1C33_AREA07_BASE 0x00400000
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| 83 | #define S1C33_AREA08_BASE 0x00600000
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| 84 | #define S1C33_AREA09_BASE 0x00800000
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| 85 | #define S1C33_AREA10_BASE 0x00c00000
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| 86 | #define S1C33_AREA11_BASE 0x01000000
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| 87 | #define S1C33_AREA12_BASE 0x01800000
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| 88 | #define S1C33_AREA13_BASE 0x02000000
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| 89 | #define S1C33_AREA14_BASE 0x03000000
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| 90 | #define S1C33_AREA15_BASE 0x04000000
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| 91 | #define S1C33_AREA16_BASE 0x06000000
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| 92 | #define S1C33_AREA17_BASE 0x08000000
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| 93 | #define S1C33_AREA18_BASE 0x0c000000
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| 94 |
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| 95 | #define S1C33_INTERNAL_RAM_BASE S1C33_AREA00_BASE
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| 96 | #define S1C33_INT08_DEVICE_BASE (S1C33_AREA01_BASE + 0x0000000)
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| 97 | #define S1C33_INT16_DEVICE_BASE (S1C33_AREA01_BASE + 0x0008000)
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| 98 | #define S1C33_EXT08_DEVICE_BASE (S1C33_AREA06_BASE + 0x0000000)
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| 99 | #define S1C33_EXT16_DEVICE_BASE (S1C33_AREA06_BASE + 0x0080000)
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| 100 |
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| 101 | #define S1C33_TIMER_CONTROL_BASE (S1C33_INT08_DEVICE_BASE + 0x0000140)
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| 102 | #define S1C33_CLKTIMER_BASE (S1C33_INT08_DEVICE_BASE + 0x0000150)
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| 103 | #define S1C33_P8TIMER_BASE (S1C33_INT08_DEVICE_BASE + 0x0000160)
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| 104 | #define S1C33_WATCHDOG_BASE (S1C33_INT08_DEVICE_BASE + 0x0000170)
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| 105 | #define S1C33_POWER_BASE (S1C33_INT08_DEVICE_BASE + 0x0000180)
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| 106 | #define S1C33_SERIAL_BASE (S1C33_INT08_DEVICE_BASE + 0x00001e0)
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| 107 | #define S1C33_AD_BASE (S1C33_INT08_DEVICE_BASE + 0x0000240)
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| 108 | #define S1C33_INTC_BASE (S1C33_INT08_DEVICE_BASE + 0x0000260)
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| 109 | #define S1C33_DMAC_BASE (S1C33_INT08_DEVICE_BASE + 0x0000290)
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| 110 | #define S1C33_PORT_BASE (S1C33_INT08_DEVICE_BASE + 0x00002c0)
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| 111 |
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| 112 | #define S1C33_BCU_BASE (S1C33_INT16_DEVICE_BASE + 0x0000120)
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| 113 | #define S1C33_P16TIMER_BASE (S1C33_INT16_DEVICE_BASE + 0x0000180)
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| 114 | #define S1C33_IDMA_BASE (S1C33_INT16_DEVICE_BASE + 0x0000200)
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| 115 | #define S1C33_HSDMA_BASE (S1C33_INT16_DEVICE_BASE + 0x0000220)
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| 116 |
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| 117 | /*
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| 118 | * å²ãè¾¼ã¿ãã¯ã¿çªå·
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| 119 | */
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| 120 | #define S1C33_INHNO_RESET 0x00
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| 121 | #define S1C33_INHNO_ZERO 0x04
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| 122 | #define S1C33_INHNO_ADDRESS 0x06
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| 123 | #define S1C33_INHNO_DEBUG 0x07
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| 124 | #define S1C33_INHNO_NMI 0x08
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| 125 | #define S1C33_INHNO_INT0 0x0c
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| 126 | #define S1C33_INHNO_INT1 0x0d
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| 127 | #define S1C33_INHNO_INT2 0x0e
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| 128 | #define S1C33_INHNO_INT3 0x0f
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| 129 | #define S1C33_INHNO_PINT0 0x10
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| 130 | #define S1C33_INHNO_PINT1 0x11
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| 131 | #define S1C33_INHNO_PINT2 0x12
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| 132 | #define S1C33_INHNO_PINT3 0x13
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| 133 | #define S1C33_INHNO_KINT0 0x14
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| 134 | #define S1C33_INHNO_KINT1 0x15
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| 135 | #define S1C33_INHNO_HSDMA0 0x16
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| 136 | #define S1C33_INHNO_HSDMA1 0x17
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| 137 | #define S1C33_INHNO_HSDMA2 0x18
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| 138 | #define S1C33_INHNO_HSDMA3 0x19
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| 139 | #define S1C33_INHNO_IDMA 0x1a
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| 140 | #define S1C33_INHNO_P16TIMER0B 0x1e
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| 141 | #define S1C33_INHNO_P16TIMER0A 0x1f
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| 142 | #define S1C33_INHNO_P16TIMER1B 0x22
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| 143 | #define S1C33_INHNO_P16TIMER1A 0x23
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| 144 | #define S1C33_INHNO_P16TIMER2B 0x26
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| 145 | #define S1C33_INHNO_P16TIMER2A 0x27
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| 146 | #define S1C33_INHNO_P16TIMER3B 0x2a
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| 147 | #define S1C33_INHNO_P16TIMER3A 0x2b
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| 148 | #define S1C33_INHNO_P16TIMER4B 0x2e
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| 149 | #define S1C33_INHNO_P16TIMER4A 0x2f
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| 150 | #define S1C33_INHNO_P16TIMER5B 0x32
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| 151 | #define S1C33_INHNO_P16TIMER5A 0x33
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| 152 | #define S1C33_INHNO_P8TIMER0 0x34
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| 153 | #define S1C33_INHNO_P8TIMER1 0x35
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| 154 | #define S1C33_INHNO_P8TIMER2 0x36
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| 155 | #define S1C33_INHNO_P8TIMER3 0x37
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| 156 | #define S1C33_INHNO_SERIAL0ERR 0x38
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| 157 | #define S1C33_INHNO_SERIAL0RX 0x39
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| 158 | #define S1C33_INHNO_SERIAL0TX 0x3a
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| 159 | #define S1C33_INHNO_SERIAL1ERR 0x3c
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| 160 | #define S1C33_INHNO_SERIAL1RX 0x3d
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| 161 | #define S1C33_INHNO_SERIAL1TX 0x3e
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| 162 | #define S1C33_INHNO_AD 0x40
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| 163 | #define S1C33_INHNO_CLKTIMER 0x41
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| 164 | #define S1C33_INHNO_PINT4 0x44
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| 165 | #define S1C33_INHNO_PINT5 0x45
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| 166 | #define S1C33_INHNO_PINT6 0x46
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| 167 | #define S1C33_INHNO_PINT7 0x47
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| 168 | #define S1C33_INHNO_P8TIMER4 0x48
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| 169 | #define S1C33_INHNO_P8TIMER5 0x49
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| 170 | #define S1C33_INHNO_SERIAL2ERR 0x4c
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| 171 | #define S1C33_INHNO_SERIAL2RX 0x4d
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| 172 | #define S1C33_INHNO_SERIAL2TX 0x4e
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| 173 | #define S1C33_INHNO_SERIAL3ERR 0x50
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| 174 | #define S1C33_INHNO_SERIAL3RX 0x51
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| 175 | #define S1C33_INHNO_SERIAL3TX 0x52
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| 176 |
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| 177 | /*
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| 178 | * ã¢ããã³ã¹ããã¯ãåºæã®å²ãè¾¼ã¿ãã¯ã¿
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| 179 | */
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| 180 | #define S1C33_INHNO_PINT8 0x54
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| 181 | #define S1C33_INHNO_PINT9 0x55
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| 182 | #define S1C33_INHNO_PINT10 0x56
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| 183 | #define S1C33_INHNO_PINT11 0x57
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| 184 | #define S1C33_INHNO_PINT12 0x58
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| 185 | #define S1C33_INHNO_PINT13 0x59
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| 186 | #define S1C33_INHNO_PINT14 0x5a
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| 187 | #define S1C33_INHNO_PINT15 0x5b
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| 188 | #define S1C33_INHNO_P16TIMER6B 0x5e
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| 189 | #define S1C33_INHNO_P16TIMER6A 0x5f
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| 190 | #define S1C33_INHNO_P16TIMER7B 0x62
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| 191 | #define S1C33_INHNO_P16TIMER7A 0x63
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| 192 | #define S1C33_INHNO_P16TIMER8B 0x66
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| 193 | #define S1C33_INHNO_P16TIMER8A 0x67
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| 194 | #define S1C33_INHNO_P16TIMER9B 0x6a
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| 195 | #define S1C33_INHNO_P16TIMER9A 0x6b
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| 196 |
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| 197 |
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| 198 | #ifndef _MACRO_ONLY
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| 199 |
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| 200 | typedef unsigned char byte;
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| 201 | typedef unsigned short word;
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| 202 | typedef volatile byte IOREG;
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| 203 | typedef volatile word HIOREG;
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| 204 | typedef volatile int LIOREG;
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| 205 |
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| 206 | /*
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| 207 | * ã¬ã¸ã¹ã¿(TIMER_CONTROL 140)
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| 208 | */
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| 209 | typedef struct {
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| 210 | IOREG bP8ClkSelect45;
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| 211 | IOREG bDummy[4];
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| 212 | IOREG bP8ClkCtrl45;
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| 213 | IOREG bP8ClkSelect;
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| 214 | IOREG bP16ClkCtrl[6];
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| 215 | IOREG bP8ClkCtrl[2];
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| 216 | IOREG bADClkCtrl;
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| 217 | } s1c33TimerControl_t;
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| 218 |
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| 219 | /*
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| 220 | * ã¬ã¸ã¹ã¿(SERIAL 1e0)
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| 221 | */
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| 222 | typedef struct {
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| 223 | struct {
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| 224 | IOREG bTxd;
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| 225 | IOREG bRxd;
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| 226 | IOREG bStatus;
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| 227 | IOREG bControl;
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| 228 | IOREG bIrDA;
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| 229 | } stChannel01[2];
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| 230 |
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| 231 | IOREG Dummy0[6];
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| 232 |
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| 233 | struct {
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| 234 | IOREG bTxd;
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| 235 | IOREG bRxd;
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| 236 | IOREG bStatus;
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| 237 | IOREG bControl;
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| 238 | IOREG bIrDA;
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| 239 | } stChannel23[2];
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| 240 | #ifdef __c33adv
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| 241 | IOREG Dummy1[5];
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| 242 | IOREG bSioAdv;
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| 243 | #endif // __c33adv
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| 244 | } s1c33Serial_t;
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| 245 |
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| 246 | /*
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| 247 | * ã¬ã¸ã¹ã¿(INTC 260)
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| 248 | *
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| 249 | */
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| 250 | typedef struct {
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| 251 | IOREG bPriority[15]; /* C33209ã§ã®ã¢ãµã¤ã³ã¯bPriority[14] + */
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| 252 | IOREG bDummy0[1]; /* bDummy0[2]ã®æ§æã¨çãã */
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| 253 |
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| 254 | IOREG bIntEnable[10]; /* C33209ã§ã®ã¢ãµã¤ã³ã¯bIntEnable[8] + */
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| 255 | IOREG bDummy1[6]; /* bDummy1[8]ã®æ§æã¨çãã */
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| 256 |
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| 257 | IOREG bIntFactor[10]; /* C33209ã§ã®ã¢ãµã¤ã³ã¯bIntFactor[8] + */
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| 258 | IOREG bDummy2[6]; /* bDummy2[8]ã®æ§æã¨çãã */
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| 259 |
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| 260 | IOREG bIDMAReq[4];
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| 261 | IOREG bIDMAEnable[4];
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| 262 | IOREG bHSDMATriger[2];
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| 263 | IOREG bHSDMASoftTrg;
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| 264 |
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| 265 | IOREG bIDMAReqExt; /* C33209ã§ã®ã¢ãµã¤ã³ã¯bDummy3[4]ã® */
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| 266 | IOREG bIDMAEnableExt; /* æ§æã¨çãã*/
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| 267 | IOREG bDummy3[2];
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| 268 |
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| 269 | IOREG bReset;
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| 270 | } s1c33Intc_t;
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| 271 |
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| 272 | /*
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| 273 | * ã¬ã¸ã¹ã¿(PORT 2c0)
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| 274 | */
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| 275 | typedef struct {
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| 276 | struct {
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| 277 | IOREG bFuncSwitch;
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| 278 | IOREG bData;
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| 279 | } stK5Port;
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| 280 |
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| 281 | IOREG bDummy;
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| 282 |
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| 283 | struct {
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| 284 | IOREG bFuncSwitch;
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| 285 | IOREG bData;
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| 286 | } stK6Port;
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| 287 |
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| 288 | IOREG bIntFPSwitch; /* C33L11ã§ã¯æªä½¿ç¨ */
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| 289 |
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| 290 | struct {
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| 291 | IOREG bSpt[2];
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| 292 | IOREG bSppt;
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| 293 | IOREG bSept;
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| 294 | } stPINT;
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| 295 |
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| 296 | struct {
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| 297 | IOREG bSppk;
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| 298 | IOREG bTM16Switch; /* C33L11ã§ã¯æªä½¿ç¨ */
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| 299 | IOREG bScpk[2];
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| 300 | IOREG bSmpk[2];
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| 301 | } stKINT;
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| 302 |
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| 303 | struct {
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| 304 | IOREG bFuncSwitch;
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| 305 | IOREG bData;
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| 306 | IOREG bControl;
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| 307 | IOREG bFuncExt /* stPPort[0]ã®ã¿C33209,C33L11 */;
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| 308 | /* ã¨ãæªä½¿ç¨ */
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| 309 | } stPPort[4];
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| 310 | } s1c33Port_t;
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| 311 |
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| 312 | /*
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| 313 | * ã¬ã¸ã¹ã¿(BCU 120)
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| 314 | */
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| 315 | typedef struct {
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| 316 | HIOREG uwA18_15;
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| 317 | HIOREG uwA14_13;
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| 318 | HIOREG uwA12_11;
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| 319 | HIOREG uwA10_09;
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| 320 | HIOREG uwA08_07;
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| 321 | HIOREG uwA06_04;
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| 322 | IOREG bDummy;
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| 323 | IOREG bTtbrProt;
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| 324 | HIOREG uwBus;
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| 325 | HIOREG uwDram;
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| 326 | HIOREG uwAccess;
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| 327 | LIOREG ulTtbr;
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| 328 | HIOREG uwGACtrl;
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| 329 | IOREG bBClk;
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| 330 | } s1c33Bcu_t;
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| 331 |
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| 332 | /*
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| 333 | * ã¬ã¸ã¹ã¿(P16TIMER 180)
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| 334 | */
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| 335 | typedef struct {
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| 336 | struct {
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| 337 | HIOREG uwComp[2];
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| 338 | HIOREG uwCount;
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| 339 | IOREG bControl;
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| 340 | IOREG bDummy;
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| 341 | } stChannel[6];
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| 342 | } s1c33P16Timer_t;
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| 343 |
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| 344 | #endif /* _MACRO_ONLY */
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| 345 | #endif /* _S1C33_H_ */
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