[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2001-2004 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | * @(#) $Id: vea_oea.h,v 1.2 2004/10/07 17:10:56 honda Exp $
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| 53 | */
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| 54 |
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| 55 | /*
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| 56 | * PowerPCã¢ã¼ããã¯ãã£VEA,OEAä¾åã®å®ç¾©
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| 57 | * ããªãªã¸ãã«ã®PowerPCã¢ã¼ããã¯ãã£ã®å ´å
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| 58 | * ããã¢ããã¼ã©MPCã·ãªã¼ãºãIPM PowerPC6xx/7xxã·ãªã¼ãºã¯
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| 59 | * ãããã¡ãã«è©²å½ããã
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| 60 | * ã
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| 61 | * ãPowerPCã¢ã¼ããã¯ãã£ã®å®ç¾©ã¯ä»¥ä¸ã®ï¼ã¤ã®ã¬ãã«ããæã
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| 62 | * ãã»USIA:User Instruction Set Architecture
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| 63 | * ãã»VEA: Virtual Environment Architecture
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| 64 | * ãã»OEA: Operating Environment Architecture
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| 65 | * ã
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| 66 | * ãUSIAã«ã¤ãã¦ã¯å
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| 67 | ¨æ©ç¨®å
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| 68 | ±éã§ããããVEAã¨OEAã«ã¤ãã¦ã¯
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| 69 | * ããªãªã¸ãã«ã®PowerPCã¢ã¼ããã¯ãã£ã¨The IBM PowerPC
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| 70 | * ãEmbedded Environmentããããå¥ã«å®ç¾©ããã¦ããããã
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| 71 | * ãVEAã¨OEAã®å®ç¾©ã¯ãã¡ã¤ã«ãåãã¦ããããã¤ã³ã¯ã«ã¼ã
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| 72 | * ããã¦ããã
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| 73 | */
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| 74 |
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| 75 | #ifndef _VEA_OEA_H_
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| 76 | #define _VEA_OEA_H_
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| 77 |
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| 78 | /*
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| 79 | * ã¬ã¸ã¹ã¿çªå·ã®å®ç¾©
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| 80 | */
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| 81 |
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| 82 | /*
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| 83 | * Configuration Register
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| 84 | */
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| 85 | #define PVR 287 /* ããã»ããµã»ãã¼ã¸ã§ã³ã»ã¬ã¸ã¹ã¿ */
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| 86 |
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| 87 | /*
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| 88 | * Memory Management Registers
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| 89 | */
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| 90 | /* Instruction BAT Registers */
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| 91 | #define IBAT0U 528
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| 92 | #define IBAT0L 529
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| 93 | #define IBAT1U 530
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| 94 | #define IBAT1L 531
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| 95 | #define IBAT2U 532
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| 96 | #define IBAT2L 533
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| 97 | #define IBAT3U 534
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| 98 | #define IBAT3L 535
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| 99 |
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| 100 | /* Instruction BAT Registers */
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| 101 | #define DBAT0U 536
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| 102 | #define DBAT0L 537
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| 103 | #define DBAT1U 538
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| 104 | #define DBAT1L 539
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| 105 | #define DBAT2U 540
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| 106 | #define DBAT2L 541
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| 107 | #define DBAT3U 542
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| 108 | #define DBAT3L 543
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| 109 |
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| 110 | #define SDR1 25
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| 111 | #define ASR 280
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| 112 |
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| 113 | /*
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| 114 | * Exception Handling Registers
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| 115 | */
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| 116 | #define DAR 19 /* Data Address Register */
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| 117 |
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| 118 | #define SPRG0 272 /* ç¹æ®ã¬ã¸ã¹ã¿ï¼OSç¨ */
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| 119 | #define SPRG1 273 /* ç¹æ®ã¬ã¸ã¹ã¿ï¼OSç¨ */
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| 120 | #define SPRG2 274 /* ç¹æ®ã¬ã¸ã¹ã¿ï¼OSç¨ */
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| 121 | #define SPRG3 275 /* ç¹æ®ã¬ã¸ã¹ã¿ï¼OSç¨ */
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| 122 |
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| 123 | #define DSISR 18 /* DSIã¹ãã¼ã¿ã¹ã»ã¬ã¸ã¹ã¿(*) */
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| 124 | /* ãDSIï¼ãã¼ã¿ã»ã¹ãã¢å²è¾¼ã¿ */
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| 125 | #define SRR0 26 /* å¾
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| 126 | é¿ï¼å¾©å¸°ã¬ã¸ã¹ã¿0 */
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| 127 | #define SRR1 27 /* å¾
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| 128 | é¿ï¼å¾©å¸°ã¬ã¸ã¹ã¿1 */
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| 129 |
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| 130 | #define FPECR 1022 /* Floating-Point Exception Cause Register */
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| 131 |
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| 132 |
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| 133 | /*
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| 134 | * Miscellaneous Registers
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| 135 | */
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| 136 | /* Time Base Facility(OEA:for Writing) */
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| 137 | #define TBLw 284
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| 138 | #define TBUw 285
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| 139 |
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| 140 | /* Time Base Facility(VEA:for Reading) */
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| 141 | #define TBL 268
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| 142 | #define TBU 269
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| 143 |
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| 144 | #define DEC 22 /* ãã£ã¯ãªã¡ã³ãã»ã¬ã¸ã¹ã¿(*) */
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| 145 |
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| 146 | #define PIR 1023 /* Processor Identification Register */
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| 147 |
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| 148 | #define DABR 1013 /* DATA Address Breakpint Register(option) */
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| 149 | #define EAR 282 /* Exception Access Register(option) */
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| 150 |
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| 151 |
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| 152 |
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| 153 | /*
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| 154 | * ãããçªå·ã®å®ç¾©
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| 155 | * ã注æï¼PowerPCã®ãããçªå·ã¯é常ã¨éã«ãªã£ã¦ãã
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| 156 | * ããããã¾ãã32ãããã¬ã¸ã¹ã¿ã¨16ãããã¬ã¸ã¹ã¿ã§ã¯
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| 157 | * ããããæä¸ä½ãããã®ãããçªå·ãç°ãªãç¹ã«ã注æ
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| 158 | */
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| 159 |
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| 160 | /* ãã·ã³ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã®åãããã®å®ç¾© */
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| 161 | /* ã注æï¼32ãããã»ã¤ã³ããªã¡ã³ãå°ç¨ */
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| 162 | #define MSR_POW BIT13_32 /* ãã¯ã¼ããã¼ã¸ã¡ã³ãã»ã¤ãã¼ãã« */
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| 163 | #define MSR_ILE BIT15_32 /* ä¾å¤å¦çæã®ã¨ã³ãã£ã¢ã³ã¢ã¼ã */
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| 164 | /* ãä¾å¤åä»æã«MSR.LEâMSR.ILE */
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| 165 | #define MSR_EE BIT16_32 /* å¤é¨å²è¾¼ã¿ã¤ãã¼ãã« */
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| 166 | #define MSR_PR BIT17_32 /* ç¹æ¨©ã¬ãã« */
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| 167 | /* ã0ï¼ã¹ã¼ããã¤ã¶ã»ã¬ãã« */
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| 168 | /* ã1ï¼ã¦ã¼ã¶ã»ã¬ãã« */
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| 169 | #define MSR_FP BIT18_32 /* æµ®åå°æ°ç¹ã¤ãã¼ãã« */
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| 170 | #define MSR_ME BIT19_32 /* ãã·ã³ãã§ãã¯ã»ã¤ãã¼ãã« */
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| 171 | #define MSR_FE0 BIT20_32 /* æµ®åå°æ°ç¹ä¾å¤ã¢ã¼ã0 */
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| 172 | #define MSR_FE1 BIT23_32 /* æµ®åå°æ°ç¹ä¾å¤ã¢ã¼ã1 */
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| 173 | /* ã注æï¼çªå·ãä¸é£ç¶ */
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| 174 | #define MSR_SE BIT21_32 /* ã·ã³ã°ã«ã¹ããããã¬ã¼ã¹ã»ã¤ãã¼ãã« */
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| 175 | #define MSR_BE BIT22_32 /* åå²ãã¬ã¼ã¹ã»ã¤ãã¼ãã« */
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| 176 | #define MSR_IP BIT25_32 /* ä¾å¤ããªãã£ãã¯ã¹ */
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| 177 | /* ã0ï¼0x000n,nnnn */
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| 178 | /* ã1ï¼0xfffn,nnnn */
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| 179 | #define MSR_IR BIT26_32 /* å½ä»¤ã¢ãã¬ã¹å¤æã¤ãã¼ãã« */
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| 180 | #define MSR_DR BIT27_32 /* ãã¼ã¿ã¢ãã¬ã¹å¤æã¤ãã¼ãã« */
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| 181 | #define MSR_RI BIT30_32 /* å復å¯è½ãªä¾å¤ */
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| 182 | /* ã0:å復ä¸å¯è½ */
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| 183 | /* ã1:å復å¯è½ */
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| 184 | #define MSR_LE BIT31_32 /* ãªãã«ã¨ã³ãã£ã¢ã³ã»ã¢ã¼ã */
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| 185 | /* ã0ï¼ããã°ã¨ã³ãã£ã¢ã³ */
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| 186 | /* ã1ï¼ãªãã«ã¨ã³ãã£ã¢ã³ */
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| 187 | /* 0ã§äºç´ããã¦ãããããã®ããã®ãã¹ã¯ */
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| 188 | #define MSR_MASK ~(BIT0_32 | BIT1_32 | BIT2_32 | BIT3_32 | BIT4_32 \
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| 189 | | BIT5_32 | BIT6_32 | BIT7_32 | BIT8_32 | BIT9_32 \
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| 190 | | BIT10_32 | BIT11_32 | BIT12_32 | BIT24_32 \
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| 191 | | BIT28_32 | BIT29_32)
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| 192 |
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| 193 |
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| 194 | /*
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| 195 | * CPUä¾å¤è¦å ã®å®ç¾©
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| 196 | * ãçªå·ãä¸é£ç¶ãªã®ã§CPUä¾å¤æ¬ä¼¼ãã¯ã¿ãã¼ãã«ã«ä¸é¨ç¡é§ãå
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| 197 | ¥ããã
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| 198 | * ãPowerPCã¢ã¼ããã¯ãã£ã®å®ç¾©ã«åãããæ¹ãåªå
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| 199 | ããã
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| 200 | */
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| 201 | #define EXC_NO_SYSTEM_RESET 0x1 /* ã·ã¹ãã ãªã»ããä¾å¤ */
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| 202 | #define EXC_NO_MACHINE_CHECK 0x2 /* ãã·ã³ã»ãã§ãã¯ä¾å¤ */
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| 203 | #define EXC_NO_DSI 0x3 /* DSIä¾å¤ */
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| 204 | /* ï¼ãã¼ã¿ã»ã¡ã¢ãªã»ã¢ã¯ã»ã¹ï¼ */
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| 205 | #define EXC_NO_ISI 0x4 /* ISIä¾å¤ï¼å½ä»¤ãã§ããï¼ */
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| 206 | #define EXC_NO_EXTERNAL_INTERRUPT 0x5 /* å¤é¨å²è¾¼ã¿ */
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| 207 | #define EXC_NO_ALIGNMENT 0x6 /* ã¢ã©ã¤ã¡ã³ãä¾å¤ */
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| 208 | #define EXC_NO_PROGRAM 0x7 /* ããã°ã©ã ä¾å¤ */
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| 209 | #define EXC_NO_FLOATING_POINT_UNAVAILABLE 0x8 /* æµ®åå°æ°ç¹ä½¿ç¨ä¸å¯ */
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| 210 | #define EXC_NO_DECREMENTER 0x9 /* ãã¯ãªã¡ã³ã¿ä¾å¤ */
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| 211 | /* ã¤ã³ããªã¡ã³ãã¼ã·ã§ã³åºæã®ä¾å¤0x00a00 */
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| 212 | #define EXC_NO_IMPLEMENT_EXCEPTION_00A00 0xa
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| 213 | #define EXC_NO_SYSTEM_CALL 0xc /* ã·ã¹ãã ã³ã¼ã« */
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| 214 | #define EXC_NO_TRACE 0xd /* ãã¬ã¼ã¹ï¼ãªãã·ã§ã³ï¼ */
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| 215 | #define EXC_NO_FLOATING_POINT_ASSIST 0xe /* æµ®åå°æ°ç¹è£å© */
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| 216 | /* ã¤ã³ããªã¡ã³ãã¼ã·ã§ã³åºæã®ä¾å¤0x01000 */
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| 217 | #define EXC_NO_IMPLEMENT_EXCEPTION_01000 0x10
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| 218 |
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| 219 |
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| 220 | /*
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| 221 | * ä¾å¤ã®ç¨®å¥æ°
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| 222 | * ãå¤é¨å²è¾¼ã¿ãï¼ã¤ã¨æ°ãã
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| 223 | * ãã0çªã¯æªä½¿ç¨
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| 224 | * ãããã»ä¾å¤ãã¯ã¿ã®ãªãã»ããã¨å¯¾å¿
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| 225 | * ãããã»å¤é¨å²ãè¾¼ã¿ãï¼ã¤ã¨æ°ãã
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| 226 | * ãããã»é
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| 227 | å宣è¨ã®ããã+1ãã¦ãã
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| 228 | */
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| 229 |
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| 230 | #ifdef IMPLEMENT_EXCEPTION_01000 /* ä¾å¤ãã¯ã¿0x1000ã使ç¨ããå ´å */
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| 231 | #define TMAX_EXCNO ( 0x10 + 1 )
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| 232 |
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| 233 | #else /* IMPLEMENT_EXCEPTION_01000 */
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| 234 | #define TMAX_EXCNO ( 0xe + 1 )
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| 235 |
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| 236 | #endif /* IMPLEMENT_EXCEPTION_01000 */
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| 237 |
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| 238 |
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| 239 |
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| 240 |
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| 241 | #endif /* _VEA_OEA_H_ */
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| 242 | /* end of file */
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