[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 11 | * ã«ãã£ã¦å
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| 12 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 13 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 14 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 15 | å¸ï¼ä»¥ä¸ï¼
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| 16 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 17 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 18 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 19 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 20 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 21 | * ç¨ã§ããå½¢ã§åé
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| 22 | å¸ããå ´åã«ã¯ï¼åé
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| 23 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 24 | * è
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| 25 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 26 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 27 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 28 | * ç¨ã§ããªãå½¢ã§åé
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| 29 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 30 | * ã¨ï¼
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| 31 | * (a) åé
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| 32 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 33 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 34 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 35 | * (b) åé
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| 36 | å¸ã®å½¢æ
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| 37 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 38 | * å ±åãããã¨ï¼
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| 39 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 40 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 41 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 42 | 責ãããã¨ï¼
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| 43 | *
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| 44 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 45 | ã
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| 46 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 47 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 48 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 49 | *
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| 50 | * @(#) $Id: microblaze.h,v 1.6 2004/02/05 09:16:25 honda Exp $
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| 51 | */
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| 52 |
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| 53 | #ifndef _MICROBLAZE_H_
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| 54 | #define _MICROBLAZE_H_
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| 55 |
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| 56 |
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| 57 |
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| 58 | #ifndef _MACRO_ONLY
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| 59 | #include <itron.h>
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| 60 | #include <sil.h>
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| 61 | #endif /* _MACRO_ONLY */
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| 62 |
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| 63 |
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| 64 | /*
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| 65 | * MSRã®ããã
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| 66 | */
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| 67 | #define MSR_CC 0x80000000
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| 68 | #define MSR_DCE 0x80
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| 69 | #define MSR_DZ 0x40
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| 70 | #define MSR_ICE 0x20
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| 71 | #define MSR_FSL 0x10
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| 72 | #define MSR_BIP 0x08
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| 73 | #define MSR_C 0x04
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| 74 | #define MSR_IE 0x02
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| 75 | #define MSR_BE 0x01
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| 76 |
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| 77 |
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| 78 | /*
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| 79 | * INTC Registers
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| 80 | */
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| 81 | #define INTC_INT_STATUS_REG 0x00
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| 82 | #define INTC_INT_PENDING_REG 0x04
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| 83 | #define INTC_INT_ENABLE_REG 0x08
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| 84 | #define INTC_INT_ACK_REG 0x0c
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| 85 | #define INTC_SET_INT_ENABLE 0x10
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| 86 | #define INTC_CLEAR_INT_ENABLE 0x14
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| 87 | #define INTC_INT_VECTOR_REG 0x18
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| 88 | #define INTC_MASTER_ENABLE_REG 0x1c
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| 89 |
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| 90 | /*
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| 91 | * Masks for the INTC Registers
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| 92 | */
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| 93 | #define INTC_HIE_MASK 0x2
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| 94 | #define INTC_ME_MASK 0x1
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| 95 |
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| 96 |
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| 97 |
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| 98 | #define INTC_ISR (INTC_BASE + INTC_INT_STATUS_REG)
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| 99 | #define INTC_IPR (INTC_BASE + INTC_INT_PENDING_REG)
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| 100 | #define INTC_IER (INTC_BASE + INTC_INT_ENABLE_REG)
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| 101 | #define INTC_IAR (INTC_BASE + INTC_INT_ACK_REG)
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| 102 | #define INTC_SIE (INTC_BASE + INTC_SET_INT_ENABLE)
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| 103 | #define INTC_CIE (INTC_BASE + INTC_CLEAR_INT_ENABLE)
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| 104 | #define INTC_IVR (INTC_BASE + INTC_INT_VECTOR_REG)
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| 105 | #define INTC_MER (INTC_BASE + INTC_MASTER_ENABLE_REG)
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| 106 |
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| 107 | #ifndef _MACRO_ONLY
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| 108 | /*
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| 109 | * INTCæä½é¢æ°
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| 110 | */
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| 111 | Inline void
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| 112 | intc_start(void){
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| 113 | sil_wrw_mem((VP)INTC_MER, INTC_HIE_MASK | INTC_ME_MASK);
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| 114 | }
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| 115 |
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| 116 | Inline void
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| 117 | intc_disable_allinterrupt(){
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| 118 | sil_wrw_mem((VP)INTC_MER, 0);
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| 119 | }
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| 120 |
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| 121 | Inline void
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| 122 | intc_enable_interrupt(UW mask)
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| 123 | {
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| 124 | sil_wrw_mem((VP)INTC_SIE, mask);
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| 125 | }
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| 126 |
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| 127 | Inline void
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| 128 | intc_disable_interrupt(UW mask)
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| 129 | {
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| 130 | sil_wrw_mem((VP)INTC_CIE, mask);
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| 131 | }
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| 132 |
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| 133 | Inline void
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| 134 | intc_ack_interrupt(UW mask)
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| 135 | {
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| 136 | sil_wrw_mem((VP)INTC_IAR, mask);
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| 137 | }
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| 138 |
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| 139 | #endif /* _MACRO_ONLY */
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| 140 |
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| 141 |
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| 142 |
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| 143 | /*
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| 144 | * ã¿ã¤ããã©ã¤ãç¨ã®ãã¯ãå®ç¾©
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| 145 | */
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| 146 |
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| 147 |
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| 148 | /*
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| 149 | * Masks for the control/status register
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| 150 | */
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| 151 | #define TIMER_ENABLE_ALL 0x400
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| 152 | #define TIMER_PWM 0x200
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| 153 | #define TIMER_INTERRUPT 0x100
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| 154 | #define TIMER_ENABLE 0x080
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| 155 | #define TIMER_ENABLE_INTR 0x040
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| 156 | #define TIMER_RESET 0x020
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| 157 | #define TIMER_RELOAD 0x010
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| 158 | #define TIMER_EXT_CAPTURE 0x008
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| 159 | #define TIMER_EXT_COMPARE 0x004
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| 160 | #define TIMER_DOWN_COUNT 0x002
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| 161 | #define TIMER_CAPTURE_MODE 0x001
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| 162 |
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| 163 | #define TIMER_CONTROL_STATUS_0 0x0
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| 164 | #define TIMER_COMPARE_CAPTURE_0 0x4
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| 165 | #define TIMER_COUNTER_0 0x8
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| 166 | #define TIMER_CONTROL_STATUS_1 0x10
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| 167 | #define TIMER_COMPARE_CAPTURE_1 0x14
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| 168 | #define TIMER_COUNTER_1 0x18
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| 169 |
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| 170 |
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| 171 | #define TIMER_TCSR0 (TIMER_BASE + TIMER_CONTROL_STATUS_0)
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| 172 | #define TIMER_TCCR0 (TIMER_BASE + TIMER_COMPARE_CAPTURE_0)
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| 173 | #define TIMER_TCR0 (TIMER_BASE + TIMER_COUNTER_0)
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| 174 | #define TIMER_TCSR1 (TIMER_BASE + TIMER_CONTROL_STATUS_1)
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| 175 | #define TIMER_TCCR1 (TIMER_BASE + TIMER_COMPARE_CAPTURE_1)
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| 176 | #define TIMER_TCR1 (TIMER_BASE + TIMER_COUNTER_1)
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| 177 |
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| 178 |
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| 179 | /*
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| 180 | * UARTãã©ã¤ãç¨ã®ãã¯ãå®ç¾©
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| 181 | */
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| 182 |
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| 183 | /*
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| 184 | * Error condition masks
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| 185 | */
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| 186 | #define UARTLITE_PAR_ERROR 0x80
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| 187 | #define UARTLITE_FRAME_ERROR 0x40
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| 188 | #define UARTLITE_OVERRUN_ERROR 0x20
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| 189 |
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| 190 |
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| 191 | /*
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| 192 | * Other status bit masks
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| 193 | */
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| 194 | #define UARTLITE_INTR_ENABLED 0x10
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| 195 | #define UARTLITE_TX_FIFO_FULL 0x08
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| 196 | #define UARTLITE_TX_FIFO_EMPTY 0x04
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| 197 | #define UARTLITE_RX_FIFO_FULL 0x02
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| 198 | #define UARTLITE_RX_FIFO_VALID_DATA 0x01
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| 199 |
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| 200 | /*
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| 201 | * Control bit masks
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| 202 | */
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| 203 | #define UARTLITE_ENABLE_INTR 0x10
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| 204 | #define UARTLITE_RST_RX_FIFO 0x02
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| 205 | #define UARTLITE_RST_TX_FIFO 0x01
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| 206 |
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| 207 | /*
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| 208 | * UARTLITE Registers
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| 209 | */
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| 210 | #define UARTLITE_RECEIVE_REG 0x0
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| 211 | #define UARTLITE_TRANSMIT_REG 0x4
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| 212 | #define UARTLITE_STATUS_REG 0x8
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| 213 | #define UARTLITE_CONTROL_REG 0xc
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| 214 |
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| 215 |
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| 216 | #define UARTLITE_RXREG (UART_BASE + UARTLITE_RECEIVE_REG)
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| 217 | #define UARTLITE_TXREG (UART_BASE + UARTLITE_TRANSMIT_REG)
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| 218 | #define UARTLITE_SRREG (UART_BASE + UARTLITE_STATUS_REG)
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| 219 | #define UARTLITE_CTREG (UART_BASE + UARTLITE_CONTROL_REG)
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| 220 |
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| 221 |
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| 222 |
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| 223 | #ifndef _MACRO_ONLY
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| 224 | /*
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| 225 | * å
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| 226 | èµUARTç¨ ç°¡æSIOãã©ã¤ã
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| 227 | */
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| 228 |
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| 229 | /*
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| 230 | * ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯
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| 231 | */
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| 232 | typedef struct sio_port_initialization_block {
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| 233 |
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| 234 | } SIOPINIB;
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| 235 |
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| 236 | /*
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| 237 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯
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| 238 | */
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| 239 | typedef struct sio_port_control_block {
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| 240 | const SIOPINIB *siopinib; /* ã·ãªã¢ã«I/Oãã¼ãåæåããã㯠*/
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| 241 | VP_INT exinf; /* æ¡å¼µæ
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| 242 | å ± */
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| 243 | BOOL openflag; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
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| 244 | BOOL sendflag; /* éä¿¡å²è¾¼ã¿ã¤ãã¼ãã«ãã©ã° */
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| 245 | BOOL getready; /* æåãåä¿¡ããç¶æ
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| 246 | */
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| 247 | BOOL putready; /* æåãéä¿¡ã§ããç¶æ
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| 248 | */
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| 249 | } SIOPCB;
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| 250 |
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| 251 | extern SIOPCB siopcb_table[];
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| 252 |
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| 253 | #define uart_openflag (siopcb_table[0].openflag)
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| 254 |
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| 255 | Inline void
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| 256 | uart_putc(unsigned char c){
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| 257 | while(sil_rew_mem((VP)UARTLITE_SRREG) & UARTLITE_TX_FIFO_FULL);
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| 258 | sil_wrw_mem((VP)UARTLITE_TXREG, c);
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| 259 | }
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| 260 |
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| 261 | Inline unsigned char
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| 262 | uart_getc(void){
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| 263 | while(!(sil_rew_mem((VP)UARTLITE_SRREG) & UARTLITE_RX_FIFO_VALID_DATA));
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| 264 | return (char)(sil_rew_mem((VP)UARTLITE_RXREG));
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| 265 | }
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| 266 |
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| 267 | /*
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| 268 | * ã³ã¼ã«ããã¯ã«ã¼ãã³ã®èå¥çªå·
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| 269 | * OPB_UARTLITE ã¯ï¼éåä¿¡å²è¾¼ã¿ãåããã¦ããªãããï¼æå³ã¯ãªãï¼
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| 270 | */
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| 271 | #define SIO_ERDY_SND 1u /* éä¿¡å¯è½ã³ã¼ã«ãã㯠*/
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| 272 | #define SIO_ERDY_RCV 2u /* åä¿¡éç¥ã³ã¼ã«ãã㯠*/
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| 273 |
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| 274 |
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| 275 | /*
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| 276 | * SIOãã©ã¤ãã®åæåã«ã¼ãã³
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| 277 | */
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| 278 | extern void uart_initialize(void);
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| 279 |
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| 280 |
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| 281 | /*
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| 282 | * ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
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| 283 | */
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| 284 | extern SIOPCB *uart_opn_por(ID siopid, VP_INT exinf);
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| 285 |
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| 286 | /*
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| 287 | * ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
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| 288 | */
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| 289 | extern void uart_cls_por(SIOPCB *siopcb);
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| 290 |
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| 291 | /*
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| 292 | * ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
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| 293 | */
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| 294 | extern BOOL uart_snd_chr(SIOPCB *siopcb, INT chr);
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| 295 |
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| 296 | /*
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| 297 | * ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
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| 298 | */
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| 299 | extern INT uart_rcv_chr(SIOPCB *siopcb);
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| 300 |
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| 301 |
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| 302 | /*
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| 303 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
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| 304 | */
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| 305 | extern void uart_ena_cbr(SIOPCB *siopcb, UINT cbrtn);
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| 306 |
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| 307 |
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| 308 | /*
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| 309 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
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| 310 | */
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| 311 | extern void uart_dis_cbr(SIOPCB *siopcb, UINT cbrtn);
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| 312 |
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| 313 |
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| 314 | /*
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| 315 | * SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
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| 316 | */
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| 317 | extern void uart_isr(void);
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| 318 |
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| 319 |
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| 320 | /*
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| 321 | * ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
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| 322 | */
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| 323 | extern void uart_ierdy_snd(VP_INT exinf);
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| 324 |
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| 325 |
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| 326 | /*
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| 327 | * ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
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| 328 | */
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| 329 | extern void uart_ierdy_rcv(VP_INT exinf);
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| 330 |
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| 331 |
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| 332 |
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| 333 |
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| 334 | #endif /* _MACRO_ONLY */
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| 335 |
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| 336 | #endif /* _MICROBLAZE_H_*/
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| 337 |
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