[363] | 1 | /*
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| 2 | *
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| 3 | * TOPPERS/JSP Kernel
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| 4 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 5 | * Just Standard Profile Kernel
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| 6 | *
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| 7 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 8 | * Toyohashi Univ. of Technology, JAPAN
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| 9 | *
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| 10 | * ä¸è¨èä½æ¨©è
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| 11 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 12 | * ã«ãã£ã¦å
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| 13 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 14 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 15 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 16 | å¸ï¼ä»¥ä¸ï¼
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| 17 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 18 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 19 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 20 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 21 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 22 | * ç¨ã§ããå½¢ã§åé
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| 23 | å¸ããå ´åã«ã¯ï¼åé
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| 24 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 25 | * è
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| 26 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 27 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 28 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 29 | * ç¨ã§ããªãå½¢ã§åé
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| 30 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 31 | * ã¨ï¼
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| 32 | * (a) åé
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| 33 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 34 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 35 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 36 | * (b) åé
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| 37 | å¸ã®å½¢æ
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| 38 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 39 | * å ±åãããã¨ï¼
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| 40 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 41 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 43 | 責ãããã¨ï¼
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| 44 | *
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| 45 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 46 | ã
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| 47 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 48 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 49 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 50 | *
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| 51 | * @(#) $Id: cpu_support.S,v 1.15 2007/04/19 06:38:27 honda Exp $
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| 52 | */
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| 53 |
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| 54 | #define _MACRO_ONLY
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| 55 |
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| 56 | /*
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| 57 | * ã¢ããªã±ã¼ã·ã§ã³ã¨å
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| 58 | ±éã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«
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| 59 | */
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| 60 | #include <kernel.h>
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| 61 |
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| 62 | /*
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| 63 | * ã¿ã¼ã²ããä¾åæ
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| 64 | å ±ã®å®ç¾©
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| 65 | */
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| 66 | #include <t_config.h>
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| 67 |
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| 68 | #include "jsp_kernel.h"
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| 69 | #include "offset.h"
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| 70 | #include <microblaze_asm.inc>
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| 71 | #include <microblaze.h>
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| 72 |
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| 73 |
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| 74 | /*
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| 75 | * INTCã®è¨è¨ã«ã¤ãã¦ï¼
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| 76 | *
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| 77 | * ä¿åããã¬ã¸ã¹ã¿
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| 78 | * R3-R4 Return Valus (Volatile)
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| 79 | * R5-R10 Passing parameters (Volatile)
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| 80 | * R11-R12 Temporaries (Volatile)
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| 81 | * R14 Return address for interrupt
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| 82 | * R15 Return address for Sub-routine
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| 83 | * R16 Return address for Trap(Debugger)
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| 84 | * R17 Return address for Exeptions
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| 85 | * ?R18 Reserved for Assember
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| 86 | */
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| 87 |
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| 88 | #define STACK_TOP (STACKTOP - 0x4)
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| 89 |
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| 90 | #define INTC_ISR (INTC_BASE + INTC_INT_STATUS_REG)
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| 91 | #define INTC_IPR (INTC_BASE + INTC_INT_PENDING_REG)
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| 92 | #define INTC_IER (INTC_BASE + INTC_INT_ENABLE_REG)
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| 93 | #define INTC_IAR (INTC_BASE + INTC_INT_ACK_REG)
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| 94 | #define INTC_SIE (INTC_BASE + INTC_SET_INT_ENABLE)
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| 95 | #define INTC_CIE (INTC_BASE + INTC_CLEAR_INT_ENABLE)
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| 96 | #define INTC_IVR (INTC_BASE + INTC_INT_VECTOR_REG)
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| 97 | #define INTC_MER (INTC_BASE + INTC_MASTER_ENABLE_REG)
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| 98 |
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| 99 |
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| 100 | /*
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| 101 | * ä¾å¤ã¨ã³ããª
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| 102 | * Not Support!
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| 103 | */
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| 104 | .text
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| 105 | .globl exception_entry
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| 106 | .align 2
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| 107 | exception_entry:
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| 108 | nop
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| 109 |
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| 110 |
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| 111 |
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| 112 |
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| 113 | .text
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| 114 | .globl interrupt_entry
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| 115 | .align 2
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| 116 | interrupt_entry:
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| 117 | /*
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| 118 | * ã¹ã¿ãã¯ãã¤ã³ã¿ã®åãæ¿ããå¿
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| 119 | è¦
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| 120 | */
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| 121 | addik r1,r1,-64
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| 122 | swi r3, r1, 60
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| 123 | swi r4, r1, 56
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| 124 | swi r5, r1, 52
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| 125 | swi r6, r1, 48
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| 126 | swi r7, r1, 44
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| 127 | swi r8, r1, 40
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| 128 | swi r9, r1, 36
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| 129 | swi r10, r1, 32
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| 130 | swi r11, r1, 28
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| 131 | swi r12, r1, 24
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| 132 | swi r14, r1, 20
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| 133 | swi r15, r1, 16
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| 134 | swi r16, r1, 12
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| 135 | swi r17, r1, 8
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| 136 | swi r18, r1, 4
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| 137 | mfs r3, rmsr /* msrã®ä¿å */
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| 138 | swi r3, r1, 0
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| 139 |
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| 140 | lwi r5, r13, interrupt_count
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| 141 | bgti r5, nest_int /* ãã¹ãåæ°ã1以ä¸ãªãã¹ã¿ãã¯ãåãæ¿ããªã */
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| 142 |
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| 143 | /*
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| 144 | * ã¹ã¿ãã¯ãã¤ã³ã¿åãæ¿ã
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| 145 | */
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| 146 | la r4, r0, STACK_TOP /* ã¿ã¹ã¯ç¬ç«é¨ã®ã¹ã¿ãã¯ã®èªã¿è¾¼ã¿ */
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| 147 | sw r1, r0, r4 /* ã¿ã¹ã¯ã¹ã¿ãã¯ã®ä¿å */
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| 148 | Mov r1, r4 /* ã¹ã¿ãã¯ãã¤ã³ã¿åãæ¿ã */
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| 149 | nest_int:
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| 150 | /*
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| 151 | * å²è¾¼ã¿ãã¹ãåæ°ã®ã¤ã³ã¯ãªã¡ã³ã
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| 152 | */
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| 153 | addi r5, r5, 1
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| 154 | swi r5, r13, interrupt_count
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| 155 |
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| 156 | lwi r3, r0, INTC_IVR /* ãã¯ã¿ã®èªã¿è¾¼ã¿ */
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| 157 | add r3, r3, r3 /* ãã¯ã¿ã4å */
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| 158 | add r3, r3, r3
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| 159 | lwi r5, r3, int_handler_table /* ãã³ãã©ã¢ãã¬ã¹ã®èªã¿è¾¼ã¿ */
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| 160 | lwi r6, r3, int_bit_table /* ãã¹ã¯ãããã®èªã¿è¾¼ã¿ */
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| 161 | swi r6, r0, INTC_CIE /* çºçããå²è¾¼ã¿ããã¹ã¯ */
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| 162 | ori r4, r0, 0x02 | MSR_CACHE_SETTING /* r4 = 0x02 */
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| 163 | Push r6 /* ãã¹ã¯ããããã¹ã¿ãã¯ã« */
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| 164 |
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| 165 | mts rmsr,r4 /* å²è¾¼ã¿è¨±å¯(MSR(IE)ãã»ãã)*/
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| 166 |
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| 167 | brald r15, r5 /* ãã³ãã©å¼ã³åºã */
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| 168 | nop
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| 169 |
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| 170 | la r4, r0, MSR_CACHE_SETTING
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| 171 | mts rmsr,r4 /* å²è¾¼ã¿ç¦æ¢ */
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| 172 |
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| 173 | // ori r4, r0, 0x03 /* r4 = 0x03 */
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| 174 | // swi r4, r0, INTC_MER /* INTC_MER = 0x0 INTCã¹ã¿ã¼ã */
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| 175 |
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| 176 | Pop r6 /* ãã¹ã¯ãããã®åãåºã */
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| 177 | // swi r6, r0, INTC_IAR /* ACK */
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| 178 | swi r6, r0, INTC_SIE /* çºçå²è¾¼ã¿ã®è¨±å¯ */
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| 179 |
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| 180 | /*
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| 181 | * å²è¾¼ã¿ãã¹ãåæ°ã®ãã¯ãªã¡ã³ã
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| 182 | */
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| 183 | lwi r5, r13, interrupt_count
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| 184 | addi r5, r5, -1
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| 185 | swi r5, r13, interrupt_count
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| 186 |
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| 187 | bgti r5, ret_to_task_int /* ãã¹ãåæ°ã1以ä¸ãªãæ»ã */
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| 188 |
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| 189 | lw r1, r0, r1 /* ã¹ã¿ãã¯ãã¤ã³ã¿ãæ»ã */
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| 190 | lwi r4, r13, reqflg /* reqflg ã®ãã§ã㯠*/
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| 191 | beqi r4, ret_to_task_int /* FALSE ãªã ã¿ã¹ã¯ã«æ»ã */
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| 192 | bri ret_int /* TRUE ãªã ret_int ã« */
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| 193 | ret_to_task_int:
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| 194 | lwi r3, r1, 0
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| 195 | mts rmsr,r3
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| 196 | lwi r18, r1, 4
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| 197 | lwi r17, r1, 8
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| 198 | lwi r16, r1, 12
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| 199 | lwi r15, r1, 16
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| 200 | lwi r14, r1, 20
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| 201 | lwi r12, r1, 24
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| 202 | lwi r11, r1, 28
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| 203 | lwi r10, r1, 32
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| 204 | lwi r9, r1, 36
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| 205 | lwi r8, r1, 40
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| 206 | lwi r7, r1, 44
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| 207 | lwi r6, r1, 48
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| 208 | lwi r5, r1, 52
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| 209 | lwi r4, r1, 56
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| 210 | lwi r3, r1, 60
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| 211 | rtid r14,0
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| 212 | addik r1,r1,64
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| 213 |
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| 214 |
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| 215 |
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| 216 | /*
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| 217 | * æªç»é²ã®å²è¾¼ã¿ãçºçããã¨å¼ã³åºããã
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| 218 | * Not Yet!
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| 219 | */
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| 220 | .globl no_reg_interrupt
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| 221 | .align 2
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| 222 | no_reg_interrupt:
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| 223 | nop
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| 224 |
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| 225 |
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| 226 | /*
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| 227 | * ã¿ã¹ã¯ãã£ã¹ãããã£
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| 228 | *
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| 229 | * dispatch ã¯ï¼interrupt_count = 0
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| 230 | * MSRã® IE=0 ã®å²è¾¼ã¿ç¦æ¢ç¶æ
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| 231 | ã§å¼ã³åºããªããã°ãªããªãï¼
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| 232 | * exit_and_dispatch ãåæ§ã«ï¼interrupt_count = 0 å²è¾¼ã¿ç¦æ¢ç¶æ
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| 233 | ã§
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| 234 | * å¼ã³åºãã®ãååã§ãããï¼ã«ã¼ãã«èµ·åæã«å¯¾å¿ããããï¼
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| 235 | * interrupt_count = 1 ã§å¼ã³åºããå ´åã«ã対å¿ãã¦ããï¼
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| 236 | *
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| 237 | */
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| 238 |
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| 239 | .globl dispatch
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| 240 | .align 2
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| 241 | dispatch:
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| 242 | addi r1, r1, -64 /* ã¹ã¯ã©ããã¬ã¸ã¹ã¿ä»¥å¤ãä¿åãã */
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| 243 | swi r15, r1, 60
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| 244 | mfs r3, rmsr /* msrã®ä¿å(ãã£ãã·ã¥ã®è¨å®ã®ä¿å) */
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| 245 | swi r3, r1, 56
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| 246 | swi r18, r1, 52 /* å¿
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| 247 | è¦ã? */
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| 248 | swi r19, r1, 48
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| 249 | swi r20, r1, 44
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| 250 | swi r21, r1, 40
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| 251 | swi r22, r1, 36
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| 252 | swi r23, r1, 32
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| 253 | swi r24, r1, 28
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| 254 | swi r25, r1, 24
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| 255 | swi r26, r1, 20
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| 256 | swi r27, r1, 16
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| 257 | swi r28, r1, 12
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| 258 | swi r29, r1, 8
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| 259 | swi r30, r1, 4
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| 260 | swi r31, r1, 0
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| 261 | lwi r4 , r13, runtsk /* r4 <- runtsk */
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| 262 | swi r1 , r4, TCB_sp /* ã¿ã¹ã¯ã¹ã¿ãã¯ãTCBã«ä¿å */
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| 263 | la r5 , r0, dispatch_r /* å®è¡åéçªå°ãä¿å */
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| 264 | swi r5 , r4, TCB_pc /* å®è¡åéçªå°ãTCBã«ä¿å */
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| 265 | bri dispatcher
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| 266 |
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| 267 | dispatch_r:
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| 268 | lwi r31, r1, 0 /* ã¬ã¸ã¹ã¿ã復帰 */
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| 269 | lwi r30, r1, 4
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| 270 | lwi r29, r1, 8
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| 271 | lwi r28, r1, 12
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| 272 | lwi r27, r1, 16
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| 273 | lwi r26, r1, 20
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| 274 | lwi r25, r1, 24
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| 275 | lwi r24, r1, 28
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| 276 | lwi r23, r1, 32
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| 277 | lwi r22, r1, 36
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| 278 | lwi r21, r1, 40
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| 279 | lwi r20, r1, 44
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| 280 | lwi r19, r1, 48
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| 281 | lwi r18, r1, 52
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| 282 | lwi r3, r1, 56 /* MSRãæ»ã(ãã£ãã·ã¥ã®è¨å®ãæ»ã) */
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| 283 | mts rmsr,r3
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| 284 | addi r1, r1, 60 /* ã¹ã¿ãã¯ãã¤ã³ã¿ãæ»ã */
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| 285 | /*
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| 286 | * ã¿ã¹ã¯ä¾å¤å¦çã«ã¼ãã³ã®èµ·å
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| 287 | * dispatch_r 㯠dispatcher ããå¼ã³åºãããããï¼
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| 288 | * tcb ã®ã¢ãã¬ã¹ã¯ r4 ã«å
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| 289 | ¥ã£ã¦ãã
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| 290 | * Not Yet!
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| 291 | */
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| 292 | lwi r5, r4, TCB_enatex /* r5 <- enatex */
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| 293 | andi r6, r5, TCB_enatex_mask
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| 294 | beqi r6, dispatch_r_1 /* enatex ã FALSE ãªããªã¿ã¼ã³ */
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| 295 | lwi r7, r4, TCB_texptn /* r5 <- texptn */
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| 296 | beqi r7, dispatch_r_1 /* texptn ã 0 ã§ãªããã° */
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| 297 | brlid r15 call_texrtn /* ã¿ã¹ã¯ä¾å¤ã«ã¼ãã³ã®å¼ã³åºã */
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| 298 | nop
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| 299 | dispatch_r_1:
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| 300 | Pop r15
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| 301 | rtsd r15,8
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| 302 | nop
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| 303 |
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| 304 |
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| 305 |
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| 306 | .globl exit_and_dispatch
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| 307 | exit_and_dispatch:
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| 308 | /* interrupt_count ãã¯ãªã¢ */
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| 309 | swi r0, r13, interrupt_count
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| 310 | dispatcher:
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| 311 | /*
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| 312 | * ããã¯å²è¾¼ã¿ç¦æ¢ã§æ¥ããã¨
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| 313 | */
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| 314 | lwi r4, r13, schedtsk /* r4 <- schedtsk */
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| 315 | swi r4, r13, runtsk /* schedtsk ã runtsk ã« */
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| 316 | beqi r4, dispatcher_1 /* schedtsk ãããã */
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| 317 | lwi r1, r4, TCB_sp /* TCBããã¿ã¹ã¯ã¹ã¿ãã¯ã復帰 */
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| 318 | lwi r5, r4, TCB_pc /* TCBããå®è¡åéçªå°ã復帰 */
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| 319 | bra r5
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| 320 | dispatcher_1:
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| 321 | /*
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| 322 | * ããã§å²è¾¼ã¿ã¢ã¼ãã«åãæ¿ããã®ã¯ï¼ããã§çºçããå²è¾¼ã¿å¦ç
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| 323 | * ã«ã©ã®ã¹ã¿ãã¯ã使ããã¨ããåé¡ã®è§£æ±ºã¨ï¼å²è¾¼ã¿ãã³ãã©å
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| 324 | ã§
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| 325 | * ã®ã¿ã¹ã¯ãã£ã¹ãããã®é²æ¢ã¨ãã2ã¤ã®æå³ãããï¼
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| 326 | */
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| 327 | la r1, r0, STACKTOP /* å²è¾¼ã¿ã¹ã¿ãã¯ã«å¤æ´ */
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| 328 | la r6, r0, 1 /* interrupt_count ã1ã« */
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| 329 | swi r6, r13, interrupt_count
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| 330 | la r5, r0, 0x02 | MSR_CACHE_SETTING /* IE = '1' */
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| 331 | la r4, r0, MSR_CACHE_SETTING /* IE = '0' */
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| 332 | dispatcher_2:
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| 333 | mts rmsr, r5 /* å²è¾¼ã¿è¨±å¯(MSR(IE)ãã»ãã) */
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| 334 | nop
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| 335 | nop
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| 336 | mts rmsr, r4 /* å²è¾¼ã¿ç¦æ¢(MSR(IE)ãã¯ãªã¢) */
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| 337 | lwi r6, r13, reqflg /* r6 <- reqflg */
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| 338 | beqi r6, dispatcher_2 /* reqflg ã FALSE ãªã */
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| 339 | swi r0, r13, interrupt_count /* interrupt_count ãã¯ãªã¢ */
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| 340 | swi r0, r13, reqflg /* reqflg ã FALSE ã« */
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| 341 | bri dispatcher
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| 342 |
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| 343 | /*
|
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| 344 | * å²è¾¼ã¿ãã³ãã©/CPUä¾å¤ãã³ãã©åºå£å¦ç
|
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| 345 | *
|
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| 346 | * æ»ãå
|
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| 347 | ãã¿ã¹ã¯ã§ reqflg ãã»ããããã¦ããå ´åã®ã¿ããã«ããï¼
|
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| 348 | * interrupt_count = 0ï¼å²è¾¼ã¿ç¦æ¢ç¶æ
|
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| 349 | ï¼ã¹ã¯ã©ããã¬ã¸ã¹ã¿ãä¿åãã
|
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| 350 | * ç¶æ
|
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| 351 | ã§å¼ã³åºããã¨ï¼
|
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| 352 | */
|
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| 353 | .align 2
|
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| 354 | .globl ret_int
|
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| 355 | .globl ret_exc
|
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| 356 | ret_exc:
|
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| 357 | ret_int:
|
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| 358 | swi r0, r13, reqflg /* reqflg ã FALSE ã« */
|
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| 359 | lwi r4, r13, runtsk /* r4 <- runtsk */
|
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| 360 | lwi r6, r13, enadsp /* r6 <- enadsp */
|
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| 361 | beqi r6, ret_int_1 /* enadsp ã FALSE ãªã ret_int_1 㸠*/
|
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| 362 | lwi r5, r13, schedtsk /* r5 <- schedtsk */
|
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| 363 | sub r6, r5, r4 /* runtsk 㨠schedtsk ãåããªã */
|
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| 364 | beqi r6, ret_int_1 /* ret_int_1 㸠*/
|
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| 365 | addi r1, r1, -52 /* æ®ãã®ã¬ã¸ã¹ã¿ãä¿åãã */
|
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| 366 | swi r19, r1, 48
|
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| 367 | swi r20, r1, 44
|
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| 368 | swi r21, r1, 40
|
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| 369 | swi r22, r1, 36
|
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| 370 | swi r23, r1, 32
|
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| 371 | swi r24, r1, 28
|
---|
| 372 | swi r25, r1, 24
|
---|
| 373 | swi r26, r1, 20
|
---|
| 374 | swi r27, r1, 16
|
---|
| 375 | swi r28, r1, 12
|
---|
| 376 | swi r29, r1, 8
|
---|
| 377 | swi r30, r1, 4
|
---|
| 378 | swi r31, r1, 0
|
---|
| 379 | swi r1 , r4, TCB_sp /* ã¿ã¹ã¯ã¹ã¿ãã¯ãTCBã«ä¿å */
|
---|
| 380 | la r6 , r0, ret_int_r /* å®è¡åéçªå°ãä¿å */
|
---|
| 381 | swi r6 , r4, TCB_pc /* å®è¡åéçªå°ãTCBã«ä¿å */
|
---|
| 382 | bri dispatcher
|
---|
| 383 |
|
---|
| 384 | ret_int_r:
|
---|
| 385 | lwi r31, r1, 0 /* ã¬ã¸ã¹ã¿ã復帰 */
|
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| 386 | lwi r30, r1, 4
|
---|
| 387 | lwi r29, r1, 8
|
---|
| 388 | lwi r28, r1, 12
|
---|
| 389 | lwi r27, r1, 16
|
---|
| 390 | lwi r26, r1, 20
|
---|
| 391 | lwi r25, r1, 24
|
---|
| 392 | lwi r24, r1, 28
|
---|
| 393 | lwi r23, r1, 32
|
---|
| 394 | lwi r22, r1, 36
|
---|
| 395 | lwi r21, r1, 40
|
---|
| 396 | lwi r20, r1, 44
|
---|
| 397 | lwi r19, r1, 48
|
---|
| 398 | addi r1, r1, 52
|
---|
| 399 | lwi r3, r1, 0 /* MSR ãæ»ãï¼ãã£ãã·ã¥ã®è¨å®ãæ»ãï¼*/
|
---|
| 400 | mts rmsr, r3
|
---|
| 401 | ret_int_1:
|
---|
| 402 | /*
|
---|
| 403 | * ã¿ã¹ã¯ä¾å¤ã«ã¼ãã³ã®èµ·å
|
---|
| 404 | * ret_int_r 㯠dispatcher ããå¼ã³åºãããããï¼
|
---|
| 405 | * tcb ã®ã¢ãã¬ã¹ã¯ r4 ã«å
|
---|
| 406 | ¥ã£ã¦ãã
|
---|
| 407 | */
|
---|
| 408 | lwi r5, r4, TCB_enatex /* r5 <- enatex */
|
---|
| 409 | andi r6, r5, TCB_enatex_mask
|
---|
| 410 | beqi r6, ret_int_2 /* enatex ã FALSE ãªããªã¿ã¼ã³ */
|
---|
| 411 | lwi r7, r4, TCB_texptn /* r5 <- texptn */
|
---|
| 412 | beqi r7, ret_int_2 /* texptn ã 0 ã§ãªããã° */
|
---|
| 413 | brlid r15 call_texrtn /* ã¿ã¹ã¯ä¾å¤ã«ã¼ãã³ã®å¼ã³åºã */
|
---|
| 414 | nop
|
---|
| 415 | ret_int_2:
|
---|
| 416 | lwi r3, r1, 0 /* MSR ãæ»ãï¼å²è¾¼ã¿IE=0ã§å²è¾¼ã¿ç¦æ¢ã«ãªãï¼*/
|
---|
| 417 | mts rmsr,r3
|
---|
| 418 | lwi r18, r1, 4
|
---|
| 419 | lwi r17, r1, 8
|
---|
| 420 | lwi r16, r1, 12
|
---|
| 421 | lwi r15, r1, 16
|
---|
| 422 | lwi r14, r1, 20
|
---|
| 423 | lwi r12, r1, 24
|
---|
| 424 | lwi r11, r1, 28
|
---|
| 425 | lwi r10, r1, 32
|
---|
| 426 | lwi r9, r1, 36
|
---|
| 427 | lwi r8, r1, 40
|
---|
| 428 | lwi r7, r1, 44
|
---|
| 429 | lwi r6, r1, 48
|
---|
| 430 | lwi r5, r1, 52
|
---|
| 431 | lwi r4, r1, 56
|
---|
| 432 | lwi r3, r1, 60
|
---|
| 433 | rtid r14,0
|
---|
| 434 | addik r1,r1,64
|
---|
| 435 |
|
---|
| 436 |
|
---|
| 437 |
|
---|
| 438 | /*
|
---|
| 439 | * ã¿ã¹ã¯èµ·åå¦ç
|
---|
| 440 | *
|
---|
| 441 | * ã¹ã¿ãã¯ã®åãæ¹
|
---|
| 442 | * Microblaze Processor Reference Guide 52ã53ãã
|
---|
| 443 | * é¢æ°å¼åºãã®ããå¼æ°ã¯ï¼r5ãr10 ã«æ ¼ç´ããï¼
|
---|
| 444 | * ããã¨åæã«å¼åºãå
|
---|
| 445 | ã¯ã¹ã¿ãã¯ãã¬ã¼ã ã«å¼æ°ã®æ ¼ç´å ´æã確ä¿ããå¿
|
---|
| 446 | è¦
|
---|
| 447 | * ãããï¼ããã«ãã®ä¸ã«ã¯ãªã³ã¯ã¬ã¸ã¹ã¿(R15)ã®åã®é åãå¿
|
---|
| 448 | è¦ã¨ãªãï¼
|
---|
| 449 | * å¼åºãå
|
---|
| 450 | ã¯æ´ã«ä»ã®é¢æ°ãå¼ã³åºãå ´åçã« r5ãr10 ããã®é åã«ä¿åã
|
---|
| 451 | * ãï¼
|
---|
| 452 | * Low Address
|
---|
| 453 | * --------------------
|
---|
| 454 | * new_sp -> | Link Register(R15) |
|
---|
| 455 | * --------------------
|
---|
| 456 | * | Arg1ç¨ã®é å |
|
---|
| 457 | * --------------------
|
---|
| 458 | * | Arg2ç¨ã®é å |
|
---|
| 459 | * --------------------
|
---|
| 460 | * | .... |
|
---|
| 461 | * --------------------
|
---|
| 462 | * High Address
|
---|
| 463 | */
|
---|
| 464 |
|
---|
| 465 | .text
|
---|
| 466 | .globl activate_r
|
---|
| 467 | .align 2
|
---|
| 468 | activate_r:
|
---|
| 469 | ori r4, r0, 0x02 | MSR_CACHE_SETTING /* msrã®åæå¤ */
|
---|
| 470 | mts rmsr,r4 /* å²è¾¼ã¿è¨±å¯(MSR(IE)ãã»ãã) */
|
---|
| 471 | lw r11, r1, r0 /* ã¿ã¹ã¯ã®å®è¡çªå° */
|
---|
| 472 | lwi r5, r1, 4 /* å¼æ°ï¼exinfï¼ */
|
---|
| 473 | la r15, r0, ext_tsk -8 /* ã¿ã¹ã¯ããã®æ»ãå
|
---|
| 474 | */
|
---|
| 475 | bra r11 /* ã¿ã¹ã¯ã®å®è¡éå§ */
|
---|
| 476 |
|
---|
| 477 |
|
---|
| 478 |
|
---|
| 479 | /*
|
---|
| 480 | * å¾®å°æéå¾
|
---|
| 481 | ã¡
|
---|
| 482 | */
|
---|
| 483 | .globl _sil_dly_nse
|
---|
| 484 | _sil_dly_nse:
|
---|
| 485 | addi r5, r5, -SIL_DLY_TIM1
|
---|
| 486 | bgti r5, _sil_dly_nse_1
|
---|
| 487 | rtsd r15, 8
|
---|
| 488 | nop
|
---|
| 489 | _sil_dly_nse_1:
|
---|
| 490 | addi r5, r5, -SIL_DLY_TIM2
|
---|
| 491 | bgti r5, _sil_dly_nse_1
|
---|
| 492 | rtsd r15, 8
|
---|
| 493 | nop
|
---|