[363] | 1 | /*
|
---|
| 2 | * TOPPERS/JSP Kernel
|
---|
| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
|
---|
| 4 | * Just Standard Profile Kernel
|
---|
| 5 | *
|
---|
| 6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
|
---|
| 7 | * Toyohashi Univ. of Technology, JAPAN
|
---|
| 8 | * Copyright (C) 2001-2004 by Dep. of Computer Science and Engineering
|
---|
| 9 | * Tomakomai National College of Technology, JAPAN
|
---|
| 10 | * Copyright (C) 2001-2007 by Industrial Technology Institute,
|
---|
| 11 | * Miyagi Prefectural Government, JAPAN
|
---|
| 12 | *
|
---|
| 13 | * ä¸è¨èä½æ¨©è
|
---|
| 14 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
|
---|
| 15 | * ã«ãã£ã¦å
|
---|
| 16 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
|
---|
| 17 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
|
---|
| 18 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
|
---|
| 19 | å¸ï¼ä»¥ä¸ï¼
|
---|
| 20 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
|
---|
| 21 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
|
---|
| 22 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
|
---|
| 23 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
|
---|
| 24 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 25 | * ç¨ã§ããå½¢ã§åé
|
---|
| 26 | å¸ããå ´åã«ã¯ï¼åé
|
---|
| 27 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
|
---|
| 28 | * è
|
---|
| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
|
---|
| 30 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 31 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 32 | * ç¨ã§ããªãå½¢ã§åé
|
---|
| 33 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
|
---|
| 34 | * ã¨ï¼
|
---|
| 35 | * (a) åé
|
---|
| 36 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
|
---|
| 37 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
|
---|
| 38 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 39 | * (b) åé
|
---|
| 40 | å¸ã®å½¢æ
|
---|
| 41 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
|
---|
| 42 | * å ±åãããã¨ï¼
|
---|
| 43 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
|
---|
| 44 | * 害ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 45 | ããã³TOPPERSããã¸ã§ã¯ããå
|
---|
| 46 | 責ãããã¨ï¼
|
---|
| 47 | *
|
---|
| 48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
|
---|
| 49 | ã
|
---|
| 50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
|
---|
| 51 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
|
---|
| 52 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
|
---|
| 53 | */
|
---|
| 54 |
|
---|
| 55 | /*
|
---|
| 56 | * ããã»ããµä¾åã¢ã¸ã¥ã¼ã«(H8Sç¨)
|
---|
| 57 | */
|
---|
| 58 |
|
---|
| 59 | #include "jsp_kernel.h"
|
---|
| 60 | #include "check.h"
|
---|
| 61 | #include "task.h"
|
---|
| 62 |
|
---|
| 63 | /*
|
---|
| 64 | * ã¿ã¹ã¯ã³ã³ããã¹ãã§ã®å²è¾¼ã¿ãã¹ã¯
|
---|
| 65 | */
|
---|
| 66 | #ifdef SUPPORT_CHG_IPM
|
---|
| 67 | volatile IPM task_intmask = 0; /* IPM -> UBï¼ç¬¦å·ç¡ã8ããã */
|
---|
| 68 | #endif /* SUPPORT_CHG_IPM */
|
---|
| 69 |
|
---|
| 70 | /*
|
---|
| 71 | * éã¿ã¹ã¯ã³ã³ããã¹ãã§ã®å²è¾¼ã¿ãã¹ã¯
|
---|
| 72 | */
|
---|
| 73 | volatile IPM int_intmask = 0;
|
---|
| 74 |
|
---|
| 75 | /*
|
---|
| 76 | * å²è¾¼ã¿ãã¹ãã«ã¦ã³ã¿
|
---|
| 77 | */
|
---|
| 78 | volatile UB intnest = 1;
|
---|
| 79 |
|
---|
| 80 | /*
|
---|
| 81 | * CPUããã¯ç¶æ
|
---|
| 82 | ã表ããã©ã°
|
---|
| 83 | * ãã»å²è¾¼ã¿ç¦æ¢ï¼ã«ã¼ãã«ç®¡çä¸ã®å²è¾¼ã¿ã®ã¿ï¼
|
---|
| 84 | * ããããã¤
|
---|
| 85 | * ãã»iscpulocked == TRUE
|
---|
| 86 | * ãããã®ã¨ãCPUããã¯ç¶æ
|
---|
| 87 | ã¨ããã
|
---|
| 88 | */
|
---|
| 89 | volatile BOOL iscpulocked = TRUE;
|
---|
| 90 |
|
---|
| 91 | /*
|
---|
| 92 | * ããã»ããµä¾åã®åæå
|
---|
| 93 | */
|
---|
| 94 | void cpu_initialize(void) {
|
---|
| 95 |
|
---|
| 96 | /*
|
---|
| 97 | * 以ä¸ã®4ã¤ã¯ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§åæåãæ¸ãã§ããã
|
---|
| 98 | * ããã»å²è¾¼ã¿ãã¹ãã«ã¦ã³ã¿ intnest = 1;
|
---|
| 99 | * ããã»éã¿ã¹ã¯ã³ã³ããã¹ãã®å²è¾¼ã¿ãã¹ã¯ int_intmask = 0;
|
---|
| 100 | * ããã»ã¿ã¹ã¯ã³ã³ããã¹ãã®å²è¾¼ã¿ãã¹ã¯ task_intmask = 0;
|
---|
| 101 | * ããããï¼chg_ipmããµãã¼ãããå ´åï¼
|
---|
| 102 | * ããã»CPUããã¯ãã©ã° iscpulocked = TRUE;
|
---|
| 103 | */
|
---|
| 104 |
|
---|
| 105 | /* å²è¾¼ã¿å¶å¾¡ã¢ã¼ãã®è¨å® */
|
---|
| 106 | h8s_wrb_reg(SYSCR, SYS_SYSCR);
|
---|
| 107 |
|
---|
| 108 | /* å²è¾¼ã¿ã¬ãã«ã®åæå */
|
---|
| 109 | h8s_wrb_reg(IPRA, 0);
|
---|
| 110 | h8s_wrb_reg(IPRB, 0);
|
---|
| 111 | h8s_wrb_reg(IPRC, 0);
|
---|
| 112 | h8s_wrb_reg(IPRD, 0);
|
---|
| 113 | h8s_wrb_reg(IPRE, 0);
|
---|
| 114 | h8s_wrb_reg(IPRF, 0);
|
---|
| 115 | h8s_wrb_reg(IPRG, 0);
|
---|
| 116 | h8s_wrb_reg(IPRH, 0);
|
---|
| 117 | h8s_wrb_reg(IPRI, 0);
|
---|
| 118 | h8s_wrb_reg(IPRJ, 0);
|
---|
| 119 | h8s_wrb_reg(IPRK, 0);
|
---|
| 120 | }
|
---|
| 121 |
|
---|
| 122 | /*
|
---|
| 123 | * ããã»ããµä¾åã®çµäºå¦ç
|
---|
| 124 | */
|
---|
| 125 | void cpu_terminate(void) {
|
---|
| 126 | }
|
---|
| 127 |
|
---|
| 128 | /*
|
---|
| 129 | * å¾®å°æéå¾
|
---|
| 130 | ã¡
|
---|
| 131 | * ãã注æäºé
|
---|
| 132 | ï¼
|
---|
| 133 | * ãããæ¨æºã§ã¯dlytimã¯UINTåã ã16ããããããªãã®ã§ã
|
---|
| 134 | * ãããUWåã«å¤æ´ãã¦ããã
|
---|
| 135 | * ãããsil_dly_nse()ã¯å
|
---|
| 136 | é¨ã§sil_dly_nse_long()ãå¼ã³åºãã
|
---|
| 137 | */
|
---|
| 138 | void sil_dly_nse(UINT dlytim) {
|
---|
| 139 | sil_dly_nse_long((UW)dlytim);
|
---|
| 140 | }
|
---|
| 141 |
|
---|
| 142 | #ifdef SUPPORT_CHG_IPM
|
---|
| 143 |
|
---|
| 144 | /*
|
---|
| 145 | * å²è¾¼ã¿ãã¹ã¯ã®å¤æ´
|
---|
| 146 | *
|
---|
| 147 | *ãIPMã«è¨å®ã§ããå¤ã¯0ãMAX_IPMã§ããã
|
---|
| 148 | *ãå²è¾¼ã¿ãã©ã¤ãªãªãã£ã¬ãã«ã(MAX_IPM+1)以ä¸ã®å²è¾¼ã¿ã¯ã«ã¼ãã«ç®¡çå¤
|
---|
| 149 | *ãæ±ãã§ããã
|
---|
| 150 | *
|
---|
| 151 | * IPM ã 0 以å¤ã®æã«ãï¼ã¿ã¹ã¯ãã£ã¹ãããã¯ä¿çãããªãï¼
|
---|
| 152 | * ãã£ã¹ããããç¦æ¢ãããå ´åã«ã¯ï¼loc_cpu ã«ããCPUããã¯ç¶æ
|
---|
| 153 | ã«
|
---|
| 154 | * ããã°ããï¼IPM ã¯ï¼
|
---|
| 155 | * ã¿ã¹ã¯ãã£ã¹ãããã«ãã£ã¦ï¼æ°ããå®è¡ç¶æ
|
---|
| 156 | ã«ãªã£ãã¿ã¹ã¯ã¸å¼ãç¶ã
|
---|
| 157 | * ããï¼ãã®ããï¼ã¿ã¹ã¯ãå®è¡ä¸ã«ï¼å¥ã®ã¿ã¹ã¯ã«ãã£ã¦ IPM ãå¤æ´ã
|
---|
| 158 | * ããå ´åãããï¼JSPã«ã¼ãã«ã§ã¯ï¼IPM ã®å¤æ´ã¯ã¿ã¹ã¯ä¾å¤å¦çã«ã¼ã
|
---|
| 159 | * ã³ã«ãã£ã¦ãèµ·ããã®ãï¼ããã«ãã£ã¦æ±ããé£ãããªãç¶æ³ã¯å°ãªãã¨
|
---|
| 160 | * æãããï¼
|
---|
| 161 | *ãIPM ã®å¤ã«ãã£ã¦ã¿ã¹ã¯ãã£ã¹ããããç¦æ¢ãããå ´åã«ã¯ï¼dis_dspã
|
---|
| 162 | * ä½µç¨ããã°ããï¼
|
---|
| 163 | */
|
---|
| 164 | SYSCALL ER
|
---|
| 165 | chg_ipm(IPM ipm)
|
---|
| 166 | {
|
---|
| 167 | ER ercd = E_OK;
|
---|
| 168 |
|
---|
| 169 | LOG_CHG_IPM_ENTER(ipm);
|
---|
| 170 | CHECK_TSKCTX_UNL();
|
---|
| 171 | CHECK_PAR(ipm <= MAX_IPM);
|
---|
| 172 |
|
---|
| 173 | t_lock_cpu();
|
---|
| 174 | task_intmask = ipm;
|
---|
| 175 | t_unlock_cpu();
|
---|
| 176 |
|
---|
| 177 | exit:
|
---|
| 178 | LOG_CHG_IPM_LEAVE(ercd)
|
---|
| 179 | return(ercd);
|
---|
| 180 | }
|
---|
| 181 |
|
---|
| 182 | /*
|
---|
| 183 | * å²è¾¼ã¿ãã¹ã¯ã®åç
|
---|
| 184 | §
|
---|
| 185 | */
|
---|
| 186 | SYSCALL ER
|
---|
| 187 | get_ipm(IPM *p_ipm)
|
---|
| 188 | {
|
---|
| 189 | ER ercd = E_OK;
|
---|
| 190 |
|
---|
| 191 | LOG_GET_IPM_ENTER(p_ipm);
|
---|
| 192 | CHECK_TSKCTX_UNL();
|
---|
| 193 |
|
---|
| 194 | t_lock_cpu();
|
---|
| 195 | *p_ipm = task_intmask;
|
---|
| 196 | t_unlock_cpu();
|
---|
| 197 |
|
---|
| 198 | exit:
|
---|
| 199 | LOG_GET_IPM_LEAVE(ercd, *p_ipm);
|
---|
| 200 | return(ercd);
|
---|
| 201 | }
|
---|
| 202 |
|
---|
| 203 |
|
---|
| 204 | #endif /* SUPPORT_CHG_IPM */
|
---|
| 205 |
|
---|
| 206 | /*============================================================================*/
|
---|
| 207 | /* å
|
---|
| 208 | ±éããã¥ã¡ã³ãã«ã¯ãªããç¬èªã®é¨å */
|
---|
| 209 |
|
---|
| 210 | /*
|
---|
| 211 | * ç»é²ããã¦ããªãå²ãè¾¼ã¿ãçºçããã¨å¼ã³åºããã
|
---|
| 212 | */
|
---|
| 213 | void
|
---|
| 214 | cpu_experr(EXCSTACK *sp)
|
---|
| 215 | {
|
---|
| 216 | UW sp2, pc, ccr, tmp;
|
---|
| 217 |
|
---|
| 218 | sp2 = (UW)sp + OFFSET_SP;
|
---|
| 219 | tmp = sp->pc;
|
---|
| 220 | ccr = (tmp >> 24U) & 0xff; /* ä¸ä½1ãã¤ã */
|
---|
| 221 | pc = tmp & 0x00ffffffUL; /* ä¸ä½3ãã¤ã */
|
---|
| 222 |
|
---|
| 223 | syslog(LOG_EMERG, "Unexpected interrupt.");
|
---|
| 224 | syslog(LOG_EMERG, "PC = 0x%08lx SP = 0x%08lx CCR = 0x%02x",
|
---|
| 225 | (VP)pc, (VP)sp2, (INT)ccr);
|
---|
| 226 | syslog(LOG_EMERG, "EXR = 0x%02x", (INT)(sp->exr));
|
---|
| 227 | syslog(LOG_EMERG, "ER0 = 0x%08lx ER1 = 0x%08lx ER2 = 0x%08lx ER3 = 0x%08lx",
|
---|
| 228 | (VP)(sp->er0), (VP)(sp->er1), (VP)(sp->er2), (VP)(sp->er3));
|
---|
| 229 | syslog(LOG_EMERG, "ER4 = 0x%08lx ER5 = 0x%08lx ER6 = 0x%08lx",
|
---|
| 230 | (VP)(sp->er4), (VP)(sp->er5), (VP)(sp->er6));
|
---|
| 231 | while(1)
|
---|
| 232 | ;
|
---|
| 233 | }
|
---|
| 234 |
|
---|
| 235 |
|
---|
| 236 | /*============================================================================*/
|
---|
| 237 | /* ãããã°ç¨ã³ã¼ã */
|
---|
| 238 |
|
---|
| 239 | #ifdef TEST_CPU_INSN
|
---|
| 240 |
|
---|
| 241 | volatile UB ccr, exr;
|
---|
| 242 | volatile IPM intmask;
|
---|
| 243 |
|
---|
| 244 | void test_cpu_insn(void)
|
---|
| 245 | {
|
---|
| 246 | ccr = current_ccr();
|
---|
| 247 | set_ccr(0xf);
|
---|
| 248 | ccr = current_ccr();
|
---|
| 249 |
|
---|
| 250 | exr = current_exr();
|
---|
| 251 | set_exr(0x7);
|
---|
| 252 | exr = current_exr();
|
---|
| 253 |
|
---|
| 254 | intmask = current_intmask();
|
---|
| 255 | set_intmask(0x3);
|
---|
| 256 | intmask = current_intmask();
|
---|
| 257 |
|
---|
| 258 | disint();
|
---|
| 259 | enaint();
|
---|
| 260 |
|
---|
| 261 | _disint_();
|
---|
| 262 | }
|
---|
| 263 |
|
---|
| 264 | #endif /* TEST_CPU_INSN */
|
---|
| 265 |
|
---|
| 266 |
|
---|
| 267 | #ifdef TEST_CPU_CONFIG
|
---|
| 268 |
|
---|
| 269 | volatile BOOL b;
|
---|
| 270 | volatile ER err;
|
---|
| 271 | volatile IPM ipm;
|
---|
| 272 |
|
---|
| 273 | void dummy(void)
|
---|
| 274 | {
|
---|
| 275 | }
|
---|
| 276 |
|
---|
| 277 | void test_cpu_config(void)
|
---|
| 278 | {
|
---|
| 279 | b = sense_context();
|
---|
| 280 | dummy();
|
---|
| 281 | intnest = 1;
|
---|
| 282 | dummy();
|
---|
| 283 | b = sense_context();
|
---|
| 284 | dummy();
|
---|
| 285 | intnest = 0;
|
---|
| 286 | dummy();
|
---|
| 287 | b = sense_context();
|
---|
| 288 | dummy();
|
---|
| 289 |
|
---|
| 290 | b = t_sense_lock();
|
---|
| 291 | dummy();
|
---|
| 292 | t_lock_cpu();
|
---|
| 293 | dummy();
|
---|
| 294 | b = t_sense_lock();
|
---|
| 295 | dummy();
|
---|
| 296 | t_unlock_cpu();
|
---|
| 297 | dummy();
|
---|
| 298 | b = t_sense_lock();
|
---|
| 299 | dummy();
|
---|
| 300 |
|
---|
| 301 | i_lock_cpu();
|
---|
| 302 | dummy();
|
---|
| 303 | b = i_sense_lock();
|
---|
| 304 | dummy();
|
---|
| 305 | i_unlock_cpu();
|
---|
| 306 | dummy();
|
---|
| 307 | b = i_sense_lock();
|
---|
| 308 | dummy();
|
---|
| 309 |
|
---|
| 310 | err = chg_ipm(6);
|
---|
| 311 | dummy();
|
---|
| 312 | err = get_ipm(&ipm);
|
---|
| 313 | dummy();
|
---|
| 314 | err = chg_ipm(3);
|
---|
| 315 | dummy();
|
---|
| 316 | err = get_ipm(&ipm);
|
---|
| 317 | dummy();
|
---|
| 318 | err = chg_ipm(8);
|
---|
| 319 | dummy();
|
---|
| 320 | }
|
---|
| 321 |
|
---|
| 322 | #endif /* TEST_CPU_CONFIG */
|
---|
| 323 |
|
---|
| 324 | #ifdef TEST_H8S_SIL
|
---|
| 325 |
|
---|
| 326 | volatile UB ddr;
|
---|
| 327 |
|
---|
| 328 | void test_h8s_sil(void)
|
---|
| 329 | {
|
---|
| 330 | ddr = sil_reb_ddr(IO_PORT7);
|
---|
| 331 | sil_wrb_ddr(IO_PORT7, 0xff);
|
---|
| 332 | ddr = sil_reb_ddr(IO_PORT7);
|
---|
| 333 | sil_anb_ddr(IO_PORT7, 0xf);
|
---|
| 334 | ddr = sil_reb_ddr(IO_PORT7);
|
---|
| 335 | sil_orb_ddr(IO_PORT7, 0x80);
|
---|
| 336 | ddr = sil_reb_ddr(IO_PORT7);
|
---|
| 337 | }
|
---|
| 338 |
|
---|
| 339 | #endif /* TEST_H8S_SIL */
|
---|
| 340 |
|
---|
| 341 |
|
---|
| 342 |
|
---|