[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2001-2010 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | * Copyright (C) 2001-2004 by Dep. of Computer Science and Engineering
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| 11 | * Tomakomai National College of Technology, JAPAN
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| 12 | * Copyright (C) 2001-2004 by Kunihiko Ohnaka
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| 13 | *
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| 14 | * ä¸è¨èä½æ¨©è
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| 15 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 16 | * ã«ãã£ã¦å
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| 17 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 18 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 19 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 20 | å¸ï¼ä»¥ä¸ï¼
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| 21 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 26 | * ç¨ã§ããå½¢ã§åé
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| 27 | å¸ããå ´åã«ã¯ï¼åé
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| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 29 | * è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 33 | * ç¨ã§ããªãå½¢ã§åé
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| 34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 35 | * ã¨ï¼
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| 36 | * (a) åé
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| 37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 40 | * (b) åé
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| 41 | å¸ã®å½¢æ
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| 42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 43 | * å ±åãããã¨ï¼
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| 44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 45 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 46 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 47 | 責ãããã¨ï¼
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| 48 | *
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| 49 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 50 | ã
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| 51 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 52 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 53 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 54 | *
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| 55 | * @(#) $Id: h8_3069f.h,v 1.4 2007/03/23 07:22:15 honda Exp $
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| 56 | */
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| 57 |
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| 58 | #ifndef _H8_3069F_H_
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| 59 | #define _H8_3069F_H_
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| 60 |
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| 61 | /*
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| 62 | * H8/3069F ç¨å®ç¾©
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| 63 | */
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| 64 |
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| 65 | /* Interrupt numbers */
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| 66 |
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| 67 | #define IRQ_NMI 7 /* NMI */
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| 68 |
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| 69 | #define TRAP8 8
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| 70 |
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| 71 | #define IRQ_EXT0 12 /* IRQ0 */
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| 72 | #define IRQ_EXT1 13 /* IRQ1 */
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| 73 | #define IRQ_EXT2 14 /* IRQ2 */
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| 74 | #define IRQ_EXT3 15 /* IRQ3 */
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| 75 | #define IRQ_EXT4 16 /* IRQ4 */
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| 76 | #define IRQ_EXT5 17 /* IRQ5 */
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| 77 |
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| 78 | #define IRQ_WOVI 20 /* Watch Doc Timer */
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| 79 |
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| 80 | #define IRQ_CMI 21 /* Compare Match */
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| 81 |
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| 82 | #define IRQ_ADI 23 /* A/D */
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| 83 |
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| 84 | #define IRQ_IMIA0 24 /* 16 bit timer 0 IMIA0 */
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| 85 | #define IRQ_IMIB0 25 /* 16 bit timer 0 IMIB0 */
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| 86 | #define IRQ_OVI0 26 /* 16 bit timer 0 OVI0 */
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| 87 |
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| 88 | #define IRQ_IMIA1 28 /* 16 bit timer 1 IMIA1 */
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| 89 | #define IRQ_IMIB1 29 /* 16 bit timer 1 IMIB1 */
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| 90 | #define IRQ_OVI1 30 /* 16 bit timer 1 OVI1 */
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| 91 |
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| 92 | #define IRQ_IMIA2 32 /* 16 bit timer 2 IMIA2 */
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| 93 | #define IRQ_IMIB2 33 /* 16 bit timer 2 IMIB2 */
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| 94 | #define IRQ_OVI2 34 /* 16 bit timer 2 OVI2 */
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| 95 |
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| 96 | #define IRQ_CIMIA0 36 /* 8 bit timer 0 CIMIA0 */
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| 97 | #define IRQ_CIMIB0 37 /* 8 bit timer 0 CIMIB0 */
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| 98 | #define IRQ_CIMIA1 38 /* 8 bit timer 1 CIMIA1 */
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| 99 | #define IRQ_CIMIB1 38 /* 8 bit timer 1 CIMIB1 */
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| 100 | #define IRQ_TOVI0 39 /* 8 bit timer 0 TOVI0 */
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| 101 | #define IRQ_TOVI1 39 /* 8 bit timer 1 TOVI1 */
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| 102 |
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| 103 | #define IRQ_CIMIA2 40 /* 8 bit timer 2 CIMIA2 */
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| 104 | #define IRQ_CIMIB2 41 /* 8 bit timer 2 CIMIB2 */
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| 105 | #define IRQ_CIMIA3 42 /* 8 bit timer 3 CIMIA3 */
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| 106 | #define IRQ_CIMIB3 42 /* 8 bit timer 3 CIMIB3 */
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| 107 | #define IRQ_TOVI2 43 /* 8 bit timer 2 TOVI2 */
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| 108 | #define IRQ_TOVI3 43 /* 8 bit timer 3 TOVI3 */
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| 109 |
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| 110 | #define IRQ_DEND0A 44 /* DMAC */
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| 111 | #define IRQ_DEND0B 45 /* DMAC */
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| 112 | #define IRQ_DEND1A 46 /* DMAC */
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| 113 | #define IRQ_DEND1B 47 /* DMAC */
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| 114 |
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| 115 | #define IRQ_ERI0 52 /* SCI0 ERI */
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| 116 | #define IRQ_RXI0 53 /* SCI0 RXI */
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| 117 | #define IRQ_TXI0 54 /* SCI0 TXI */
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| 118 | #define IRQ_TEI0 55 /* SCI0 TEI */
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| 119 |
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| 120 | #define IRQ_ERI1 56 /* SCI1 ERI */
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| 121 | #define IRQ_RXI1 57 /* SCI1 RXI */
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| 122 | #define IRQ_TXI1 58 /* SCI1 TXI */
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| 123 | #define IRQ_TEI1 59 /* SCI1 TEI */
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| 124 |
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| 125 | #define IRQ_ERI2 60 /* SCI2 ERI */
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| 126 | #define IRQ_RXI2 61 /* SCI2 RXI */
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| 127 | #define IRQ_TXI2 62 /* SCI2 TXI */
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| 128 | #define IRQ_TEI2 63 /* SCI2 TEI */
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| 129 |
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| 130 | /*
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| 131 | * register address
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| 132 | *ããå
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| 133 | é¨I/Oã¬ã¸ã¹ã¿(1) 0xfe,e000ã0xfe,e0ff
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| 134 | *ããå
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| 135 | é¨I/Oã¬ã¸ã¹ã¿(2) 0xff,ff20ã0xff,ffe9
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| 136 | *ããããããã¥ã¢ã«ã«ã¯ä¸ä½20ãããããè¨è¼ããã¦ããªãã®ã§
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| 137 | *ããããä¸ä½4ãããï¼0xf0,0000ï¼ãè£ãã
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| 138 | */
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| 139 |
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| 140 | /* I/O ports */
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| 141 |
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| 142 | /* port1: A0 - A7 */
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| 143 |
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| 144 | #define H8P1DDR 0xfee000
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| 145 | #define H8P1DR 0xffffd0
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| 146 |
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| 147 | /* port2: A8 - A15 */
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| 148 |
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| 149 | #define H8P2DDR 0xfee001
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| 150 | #define H8P2DR 0xffffd1
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| 151 | #define H8P2PCR 0xfee03c
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| 152 |
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| 153 | /* port3: D8 - D15 */
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| 154 |
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| 155 | #define H8P3DDR 0xfee002
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| 156 | #define H8P3DR 0xffffd2
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| 157 |
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| 158 | /* port4: D0 - D7 */
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| 159 |
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| 160 | #define H8P4DDR 0xfee003
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| 161 | #define H8P4DR 0xffffd3
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| 162 | #define H8P4PCR 0xfee03e
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| 163 |
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| 164 | /* port5: A16 - A19 */
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| 165 |
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| 166 | #define H8P5DDR 0xfee004
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| 167 | #define H8P5DR 0xffffd4
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| 168 | #define H8P5PCR 0xfee03f
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| 169 |
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| 170 | #define H8P5DDR_A19_BIT 3
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| 171 | #define H8P5DDR_A18_BIT 2
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| 172 | #define H8P5DDR_A17_BIT 1
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| 173 | #define H8P5DDR_A16_BIT 0
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| 174 |
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| 175 | #define H8P5DDR_A19 (1<<H8P5DDR_A19_BIT)
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| 176 | #define H8P5DDR_A18 (1<<H8P5DDR_A18_BIT)
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| 177 | #define H8P5DDR_A17 (1<<H8P5DDR_A17_BIT)
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| 178 | #define H8P5DDR_A16 (1<<H8P5DDR_A16_BIT)
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| 179 |
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| 180 | /* port6 */
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| 181 |
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| 182 | #define H8P6DDR 0xfee005
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| 183 | #define H8P6DR 0xffffd5
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| 184 |
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| 185 | #define H8P6DDR_CLOCK_BIT 7
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| 186 | #define H8P6DDR_HWR_BIT 6
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| 187 | #define H8P6DDR_LWR_BIT 5
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| 188 | #define H8P6DDR_RD_BIT 4
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| 189 | #define H8P6DDR_AS_BIT 3
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| 190 | #define H8P6DDR_BACK_BIT 2
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| 191 | #define H8P6DDR_BREQ_BIT 1
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| 192 | #define H8P6DDR_WAIT_BIT 0
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| 193 |
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| 194 | #define H8P6DDR_CLOCK (1<<H8P6DDR_CLOCK_BIT)
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| 195 | #define H8P6DDR_HWR (1<<H8P6DDR_HWR_BIT)
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| 196 | #define H8P6DDR_LWR (1<<H8P6DDR_LWR_BIT)
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| 197 | #define H8P6DDR_RD (1<<H8P6DDR_RD_BIT)
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| 198 | #define H8P6DDR_AS (1<<H8P6DDR_AS_BIT)
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| 199 | #define H8P6DDR_BACK (1<<H8P6DDR_BACK_BIT)
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| 200 | #define H8P6DDR_BREQ (1<<H8P6DDR_BREQ_BIT)
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| 201 | #define H8P6DDR_WAIT (1<<H8P6DDR_WAIT_BIT)
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| 202 |
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| 203 | /* port7 */
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| 204 |
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| 205 | #define H8P7DR 0xffffd6
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| 206 |
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| 207 | /* port8 */
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| 208 |
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| 209 | #define H8P8DDR 0xfee007
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| 210 | #define H8P8DR 0xffffd7
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| 211 |
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| 212 | #define H8P8DDR_CS0_BIT 4
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| 213 | #define H8P8DDR_CS1_BIT 3
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| 214 | #define H8P8DDR_CS2_BIT 2
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| 215 | #define H8P8DDR_CS3_BIT 1
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| 216 | #define H8P8DDR_RFSH_BIT 0
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| 217 |
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| 218 | #define H8P8DDR_CS0 (1<<H8P8DDR_CS0_BIT)
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| 219 | #define H8P8DDR_CS1 (1<<H8P8DDR_CS1_BIT)
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| 220 | #define H8P8DDR_CS2 (1<<H8P8DDR_CS2_BIT)
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| 221 | #define H8P8DDR_CS3 (1<<H8P8DDR_CS3_BIT)
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| 222 | #define H8P8DDR_RFSH (1<<H8P8DDR_RFSH_BIT)
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| 223 |
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| 224 | #define H8P8DDR_IRQ3_BIT 3
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| 225 | #define H8P8DDR_IRQ2_BIT 2
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| 226 | #define H8P8DDR_IRQ1_BIT 1
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| 227 | #define H8P8DDR_IRQ0_BIT 0
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| 228 |
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| 229 | #define H8P8DDR_IRQ3 (1<<H8P8DDR_IRQ3_BIT)
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| 230 | #define H8P8DDR_IRQ2 (1<<H8P8DDR_IRQ2_BIT)
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| 231 | #define H8P8DDR_IRQ1 (1<<H8P8DDR_IRQ1_BIT)
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| 232 | #define H8P8DDR_IRQ0 (1<<H8P8DDR_IRQ0_BIT)
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| 233 |
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| 234 | #define H8P8DDR_ADTRG_BIT 3
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| 235 |
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| 236 | #define H8P8DDR_ADTRG (1<<H8PBDDR_ADTRG_BIT)
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| 237 |
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| 238 | /* port9 (SCI) */
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| 239 |
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| 240 | #define H8P9DDR 0xfee008
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| 241 | #define H8P9DR 0xffffd8
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| 242 |
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| 243 | #define H8P9DDR_SCK1_BIT 5
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| 244 | #define H8P9DDR_SCK0_BIT 4
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| 245 | #define H8P9DDR_RXD1_BIT 3
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| 246 | #define H8P9DDR_RXD0_BIT 2
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| 247 | #define H8P9DDR_TXD1_BIT 1
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| 248 | #define H8P9DDR_TXD0_BIT 0
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| 249 |
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| 250 | #define H8P9DDR_SCK1 (1<<H8P9DDR_SCK1_BIT)
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| 251 | #define H8P9DDR_SCK0 (1<<H8P9DDR_SCK0_BIT)
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| 252 | #define H8P9DDR_RXD1 (1<<H8P9DDR_RXD1_BIT)
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| 253 | #define H8P9DDR_RXD0 (1<<H8P9DDR_RXD0_BIT)
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| 254 | #define H8P9DDR_TXD1 (1<<H8P9DDR_TXD1_BIT)
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| 255 | #define H8P9DDR_TXD0 (1<<H8P9DDR_TXD0_BIT)
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| 256 |
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| 257 | #define H8P9DDR_IRQ5_BIT 5
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| 258 | #define H8P9DDR_IRQ4_BIT 4
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| 259 |
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| 260 | #define H8P9DDR_IRQ5 (1<<H8P9DDR_IRQ5_BIT)
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| 261 | #define H8P9DDR_IRQ4 (1<<H8P9DDR_IRQ4_BIT)
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| 262 |
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| 263 | /* portA (TPC/ITU/DMA) */
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| 264 |
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| 265 | #define H8PADDR 0xfee009
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| 266 | #define H8PADR 0xffffd9
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| 267 |
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| 268 | #define H8PADDR_TP7_BIT 7
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| 269 | #define H8PADDR_TP6_BIT 6
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| 270 | #define H8PADDR_TP5_BIT 5
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| 271 | #define H8PADDR_TP4_BIT 4
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| 272 | #define H8PADDR_TP3_BIT 3
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| 273 | #define H8PADDR_TP2_BIT 2
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| 274 | #define H8PADDR_TP1_BIT 1
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| 275 | #define H8PADDR_TP0_BIT 0
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| 276 |
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| 277 | #define H8PADDR_TP7 (1<<H8PADDR_TP7_BIT)
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| 278 | #define H8PADDR_TP6 (1<<H8PADDR_TP6_BIT)
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| 279 | #define H8PADDR_TP5 (1<<H8PADDR_TP5_BIT)
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| 280 | #define H8PADDR_TP4 (1<<H8PADDR_TP4_BIT)
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| 281 | #define H8PADDR_TP3 (1<<H8PADDR_TP3_BIT)
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| 282 | #define H8PADDR_TP2 (1<<H8PADDR_TP2_BIT)
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| 283 | #define H8PADDR_TP1 (1<<H8PADDR_TP1_BIT)
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| 284 | #define H8PADDR_TP0 (1<<H8PADDR_TP0_BIT)
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| 285 |
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| 286 | #define H8PADDR_TIOCB2_BIT 7
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| 287 | #define H8PADDR_TIOCA2_BIT 6
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| 288 | #define H8PADDR_TIOCB1_BIT 5
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| 289 | #define H8PADDR_TIOCA1_BIT 4
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| 290 | #define H8PADDR_TIOCB0_BIT 3
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| 291 | #define H8PADDR_TIOCA0_BIT 2
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| 292 |
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| 293 | #define H8PADDR_TIOCB2 (1<<H8PADDR_TIOCB2_BIT)
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| 294 | #define H8PADDR_TIOCA2 (1<<H8PADDR_TIOCA2_BIT)
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| 295 | #define H8PADDR_TIOCB1 (1<<H8PADDR_TIOCB1_BIT)
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| 296 | #define H8PADDR_TIOCA1 (1<<H8PADDR_TIOCA1_BIT)
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| 297 | #define H8PADDR_TIOCB0 (1<<H8PADDR_TIOCB0_BIT)
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| 298 | #define H8PADDR_TIOCA0 (1<<H8PADDR_TIOCA0_BIT)
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| 299 |
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| 300 | #define H8PADDR_TEND1_BIT 1
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| 301 | #define H8PADDR_TEND0_BIT 0
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| 302 |
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| 303 | #define H8PADDR_TEND1 (1<<H8PADDR_TEND1_BIT)
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| 304 | #define H8PADDR_TEND0 (1<<H8PADDR_TEND0_BIT)
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| 305 |
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| 306 | #define H8PADDR_A20_BIT 7
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| 307 | #define H8PADDR_A21_BIT 6
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| 308 | #define H8PADDR_A22_BIT 5
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| 309 | #define H8PADDR_A23_BIT 4
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| 310 |
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| 311 | #define H8PADDR_A20 (1<<H8PADDR_A20_BIT)
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| 312 | #define H8PADDR_A21 (1<<H8PADDR_A21_BIT)
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| 313 | #define H8PADDR_A22 (1<<H8PADDR_A22_BIT)
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| 314 | #define H8PADDR_A23 (1<<H8PADDR_A23_BIT)
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| 315 |
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| 316 | #define H8PADDR_TCLKD_BIT 3
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| 317 | #define H8PADDR_TCLKC_BIT 2
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| 318 | #define H8PADDR_TCLKB_BIT 1
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| 319 | #define H8PADDR_TCLKA_BIT 0
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| 320 |
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| 321 | #define H8PADDR_TCLKD (1<<H8PADDR_TCLKD_BIT)
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| 322 | #define H8PADDR_TCLKC (1<<H8PADDR_TCLKC_BIT)
|
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| 323 | #define H8PADDR_TCLKB (1<<H8PADDR_TCLKB_BIT)
|
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| 324 | #define H8PADDR_TCLKA (1<<H8PADDR_TCLKA_BIT)
|
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| 325 |
|
---|
| 326 | /* portB (TP/ITU/DMA/AD) */
|
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| 327 |
|
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| 328 | #define H8PBDDR 0xfee00a
|
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| 329 | #define H8PBDR 0xffffda
|
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| 330 |
|
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| 331 | #define H8PBDDR_TP15_BIT 7
|
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| 332 | #define H8PBDDR_TP14_BIT 6
|
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| 333 | #define H8PBDDR_TP13_BIT 5
|
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| 334 | #define H8PBDDR_TP12_BIT 4
|
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| 335 | #define H8PBDDR_TP11_BIT 3
|
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| 336 | #define H8PBDDR_TP10_BIT 2
|
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| 337 | #define H8PBDDR_TP9_BIT 1
|
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| 338 | #define H8PBDDR_TP8_BIT 0
|
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| 339 |
|
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| 340 | #define H8PBDDR_TP15 (1<<H8PBDDR_TP15_BIT)
|
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| 341 | #define H8PBDDR_TP14 (1<<H8PBDDR_TP14_BIT)
|
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| 342 | #define H8PBDDR_TP13 (1<<H8PBDDR_TP13_BIT)
|
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| 343 | #define H8PBDDR_TP12 (1<<H8PBDDR_TP12_BIT)
|
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| 344 | #define H8PBDDR_TP11 (1<<H8PBDDR_TP11_BIT)
|
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| 345 | #define H8PBDDR_TP10 (1<<H8PBDDR_TP10_BIT)
|
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| 346 | #define H8PBDDR_TP9 (1<<H8PBDDR_TP9_BIT)
|
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| 347 | #define H8PBDDR_TP8 (1<<H8PBDDR_TP8_BIT)
|
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| 348 |
|
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| 349 | #define H8PBDDR_LCAS_BIT 5
|
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| 350 | #define H8PBDDR_UCAS_BIT 4
|
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| 351 | #define H8PBDDR_DREQ1_BIT 3
|
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| 352 | #define H8PBDDR_DREQ0_BIT 1
|
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| 353 |
|
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| 354 | #define H8PBDDR_LCAS (1<<H8PBDDR_LCAS_BIT)
|
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| 355 | #define H8PBDDR_UCAS (1<<H8PBDDR_UCAS_BIT)
|
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| 356 | #define H8PBDDR_DREQ1 (1<<H8PBDDR_DREQ1_BIT)
|
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| 357 | #define H8PBDDR_DREQ0 (1<<H8PBDDR_DREQ0_BIT)
|
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| 358 |
|
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| 359 | #define H8PBDDR_TMIO3_BIT 3
|
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| 360 | #define H8PBDDR_TMIO2_BIT 2
|
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| 361 | #define H8PBDDR_TMIO1_BIT 1
|
---|
| 362 | #define H8PBDDR_TMIO0_BIT 0
|
---|
| 363 |
|
---|
| 364 | #define H8PBDDR_TMIO4 (1<<H8PBDDR_TMIO3_BIT)
|
---|
| 365 | #define H8PBDDR_TMIO3 (1<<H8PBDDR_TMIO2_BIT)
|
---|
| 366 | #define H8PBDDR_TMIO2 (1<<H8PBDDR_TMIO1_BIT)
|
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| 367 | #define H8PBDDR_TMIO1 (1<<H8PBDDR_TMIO0_BIT)
|
---|
| 368 |
|
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| 369 | #define H8PBDDR_RXD2_BIT 7
|
---|
| 370 | #define H8PBDDR_TXD2_BIT 6
|
---|
| 371 | #define H8PBDDR_SCK2_BIT 5
|
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| 372 |
|
---|
| 373 | #define H8PBDDR_RXD2 (1<<H8PBDDR_RXD2_BIT)
|
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| 374 | #define H8PBDDR_TXD2 (1<<H8PBDDR_TXD2_BIT)
|
---|
| 375 | #define H8PBDDR_SCK2 (1<<H8PBDDR_SCK2_BIT)
|
---|
| 376 |
|
---|
| 377 | #define H8PBDDR_CS4_BIT 3
|
---|
| 378 | #define H8PBDDR_CS5_BIT 2
|
---|
| 379 | #define H8PBDDR_CS6_BIT 1
|
---|
| 380 | #define H8PBDDR_CS7_BIT 0
|
---|
| 381 |
|
---|
| 382 | #define H8PBDDR_CS4 (1<<H8PBDDR_CS4_BIT)
|
---|
| 383 | #define H8PBDDR_CS5 (1<<H8PBDDR_CS5_BIT)
|
---|
| 384 | #define H8PBDDR_CS6 (1<<H8PBDDR_CS6_BIT)
|
---|
| 385 | #define H8PBDDR_CS7 (1<<H8PBDDR_CS7_BIT)
|
---|
| 386 |
|
---|
| 387 | /* Interrupt Contolller */
|
---|
| 388 |
|
---|
| 389 | #define H8INTC 0xfee014 /* interrupt controller base address */
|
---|
| 390 | #define H8ISCR 0xfee014
|
---|
| 391 | #define H8IER 0xfee015
|
---|
| 392 | #define H8ISR 0xfee016
|
---|
| 393 | #define H8IPRA 0xfee018
|
---|
| 394 | #define H8IPRB 0xfee019
|
---|
| 395 |
|
---|
| 396 | /* System Control Register */
|
---|
| 397 |
|
---|
| 398 | #define H8SYSCR 0xfee012 /* SYSCR */
|
---|
| 399 |
|
---|
| 400 | #define H8SYSCR_SSBY_BIT 7
|
---|
| 401 | #define H8SYSCR_STS2_BIT 6
|
---|
| 402 | #define H8SYSCR_STS1_BIT 5
|
---|
| 403 | #define H8SYSCR_STS0_BIT 4
|
---|
| 404 | #define H8SYSCR_UE_BIT 3
|
---|
| 405 | #define H8SYSCR_NMIEG_BIT 2
|
---|
| 406 | #define H8SYSCR_SSOE_BIT 1
|
---|
| 407 | #define H8SYSCR_RAME_BIT 0
|
---|
| 408 |
|
---|
| 409 | #define H8SYSCR_SSBY (1<<(H8SYSCR_SSBY_BIT))
|
---|
| 410 | #define H8SYSCR_STS2 (1<<(H8SYSCR_STS2_BIT))
|
---|
| 411 | #define H8SYSCR_STS1 (1<<(H8SYSCR_STS1_BIT))
|
---|
| 412 | #define H8SYSCR_STS0 (1<<(H8SYSCR_STS0_BIT))
|
---|
| 413 | #define H8SYSCR_UE (1<<(H8SYSCR_UE_BIT))
|
---|
| 414 | #define H8SYSCR_NMIEG (1<<(H8SYSCR_NMIEG_BIT))
|
---|
| 415 | #define H8SYSCR_SSOE (1<<(H8SYSCR_SSOE_BIT))
|
---|
| 416 | #define H8SYSCR_RAME (1<<(H8SYSCR_RAME_BIT))
|
---|
| 417 |
|
---|
| 418 | /* Interrupt Enable Register */
|
---|
| 419 |
|
---|
| 420 | #define H8IER_IRQ5E_BIT 5 /* IRQ5 */
|
---|
| 421 | #define H8IER_IRQ4E_BIT 4 /* IRQ4 */
|
---|
| 422 | #define H8IER_IRQ3E_BIT 3 /* IRQ3 */
|
---|
| 423 | #define H8IER_IRQ2E_BIT 2 /* IRQ2 */
|
---|
| 424 | #define H8IER_IRQ1E_BIT 1 /* IRQ1 */
|
---|
| 425 | #define H8IER_IRQ0E_BIT 0 /* IRQ0 */
|
---|
| 426 |
|
---|
| 427 | #define H8IER_IRQ5E (1<<(H8IER_IRQ5E_BIT))
|
---|
| 428 | #define H8IER_IRQ4E (1<<(H8IER_IRQ4E_BIT))
|
---|
| 429 | #define H8IER_IRQ3E (1<<(H8IER_IRQ3E_BIT))
|
---|
| 430 | #define H8IER_IRQ2E (1<<(H8IER_IRQ2E_BIT))
|
---|
| 431 | #define H8IER_IRQ1E (1<<(H8IER_IRQ1E_BIT))
|
---|
| 432 | #define H8IER_IRQ0E (1<<(H8IER_IRQ0E_BIT))
|
---|
| 433 |
|
---|
| 434 | /* IRQ Sense Control Register */
|
---|
| 435 | #define H8ISCR_IRQ0SC 0x01
|
---|
| 436 | #define H8ISCR_IRQ1SC 0x02
|
---|
| 437 | #define H8ISCR_IRQ2SC 0x04
|
---|
| 438 | #define H8ISCR_IRQ3SC 0x08
|
---|
| 439 | #define H8ISCR_IRQ4SC 0x10
|
---|
| 440 | #define H8ISCR_IRQ5SC 0x20
|
---|
| 441 |
|
---|
| 442 | /* IRQ Status Register */
|
---|
| 443 | #define H8ISR_IRQ0F 0x01
|
---|
| 444 | #define H8ISR_IRQ1F 0x02
|
---|
| 445 | #define H8ISR_IRQ2F 0x04
|
---|
| 446 | #define H8ISR_IRQ3F 0x08
|
---|
| 447 | #define H8ISR_IRQ4F 0x10
|
---|
| 448 | #define H8ISR_IRQ5F 0x20
|
---|
| 449 |
|
---|
| 450 |
|
---|
| 451 | /* Interrupt Priority Register A */
|
---|
| 452 |
|
---|
| 453 | #define H8IPR_IRQ0_BIT 7 /* IRQ0 */
|
---|
| 454 | #define H8IPR_IRQ1_BIT 6 /* IRQ1 */
|
---|
| 455 | #define H8IPR_IRQ2_BIT 5 /* IRQ2 */
|
---|
| 456 | #define H8IPR_IRQ3_BIT 5 /* IRQ3 */
|
---|
| 457 | #define H8IPR_IRQ4_BIT 4 /* IRQ4 */
|
---|
| 458 | #define H8IPR_IRQ5_BIT 4 /* IRQ5 */
|
---|
| 459 | #define H8IPR_WDT_BIT 3 /* WDT */
|
---|
| 460 | #define H8IPR_AD_BIT 3 /* A/D */
|
---|
| 461 | #define H8IPR_CMI_BIT 3 /* CMI */
|
---|
| 462 | #define H8IPR_ITU0_BIT 2 /* 16 bit timer 0 */
|
---|
| 463 | #define H8IPR_ITU1_BIT 1 /* 16 bit timer 1 */
|
---|
| 464 | #define H8IPR_ITU2_BIT 0 /* 16 bit timer 2 */
|
---|
| 465 |
|
---|
| 466 | #define H8IPR_IRQ0 (1<<(H8IPR_IRQ0_BIT))
|
---|
| 467 | #define H8IPR_IRQ1 (1<<(H8IPR_IRQ1_BIT))
|
---|
| 468 | #define H8IPR_IRQ2 (1<<(H8IPR_IRQ2_BIT))
|
---|
| 469 | #define H8IPR_IRQ3 (1<<(H8IPR_IRQ3_BIT))
|
---|
| 470 | #define H8IPR_IRQ4 (1<<(H8IPR_IRQ4_BIT))
|
---|
| 471 | #define H8IPR_IRQ5 (1<<(H8IPR_IRQ5_BIT))
|
---|
| 472 | #define H8IPR_WDT (1<<(H8IPR_WDT_BIT))
|
---|
| 473 | #define H8IPR_AD (1<<(H8IPR_AD_BIT))
|
---|
| 474 | #define H8IPR_CMI (1<<(H8IPR_CMI_BIT))
|
---|
| 475 | #define H8IPR_ITU0 (1<<(H8IPR_ITU0_BIT))
|
---|
| 476 | #define H8IPR_ITU1 (1<<(H8IPR_ITU1_BIT))
|
---|
| 477 | #define H8IPR_ITU2 (1<<(H8IPR_ITU2_BIT))
|
---|
| 478 |
|
---|
| 479 | /* Interrupt Priority Register B */
|
---|
| 480 |
|
---|
| 481 | #define H8IPR_TU80_BIT 7 /* 8 bit timer 0 */
|
---|
| 482 | #define H8IPR_TU81_BIT 6 /* 8 bit timer 1 */
|
---|
| 483 | #define H8IPR_DMAC_BIT 5 /* DMAC (CH0,1) */
|
---|
| 484 | #define H8IPR_SCI0_BIT 3 /* SCI0 */
|
---|
| 485 | #define H8IPR_SCI1_BIT 2 /* SCI1 */
|
---|
| 486 | #define H8IPR_SCI2_BIT 1 /* SCI2 */
|
---|
| 487 |
|
---|
| 488 | #define H8IPR_TU80 (1<<(H8IPR_TU80_BIT))
|
---|
| 489 | #define H8IPR_TU81 (1<<(H8IPR_TU81_BIT))
|
---|
| 490 | #define H8IPR_DMAC (1<<(H8IPR_DMAC_BIT))
|
---|
| 491 | #define H8IPR_SCI0 (1<<(H8IPR_SCI0_BIT))
|
---|
| 492 | #define H8IPR_SCI1 (1<<(H8IPR_SCI1_BIT))
|
---|
| 493 | #define H8IPR_SCI2 (1<<(H8IPR_SCI2_BIT))
|
---|
| 494 |
|
---|
| 495 | /* 16 bit Timer */
|
---|
| 496 |
|
---|
| 497 | #define H816TU 0xffff60 /* base address */
|
---|
| 498 | #define H816TU_TSTR 0xffff60
|
---|
| 499 | #define H816TU_TSNC 0xffff61
|
---|
| 500 | #define H816TU_TMDR 0xffff62
|
---|
| 501 | #define H816TU_TOLR 0xffff63
|
---|
| 502 | #define H816TU_TISRA 0xffff64
|
---|
| 503 | #define H816TU_TISRB 0xffff65
|
---|
| 504 | #define H816TU_TISRC 0xffff66
|
---|
| 505 |
|
---|
| 506 | #define H816TU0 0xffff68 /* base address */
|
---|
| 507 | #define H816TU1 0xffff70 /* base address */
|
---|
| 508 | #define H816TU2 0xffff78 /* base address */
|
---|
| 509 |
|
---|
| 510 | /* address offset */
|
---|
| 511 |
|
---|
| 512 | #define H8TCR 0
|
---|
| 513 | #define H8TIOR 1
|
---|
| 514 | #define H8TCNT 2
|
---|
| 515 | #define H8TCNTH 2
|
---|
| 516 | #define H8TCNTL 3
|
---|
| 517 | #define H8GRA 4
|
---|
| 518 | #define H8GRAH 4
|
---|
| 519 | #define H8GRAL 5
|
---|
| 520 | #define H8GRB 6
|
---|
| 521 | #define H8GRBH 6
|
---|
| 522 | #define H8GRBL 7
|
---|
| 523 |
|
---|
| 524 | /* Timer Start Register (TSTR) */
|
---|
| 525 |
|
---|
| 526 | #define H8TSTR_STR2_BIT 2
|
---|
| 527 | #define H8TSTR_STR1_BIT 1
|
---|
| 528 | #define H8TSTR_STR0_BIT 0
|
---|
| 529 |
|
---|
| 530 | #define H8TSTR_STR2 (1<<H8TSTR_STR2_BIT)
|
---|
| 531 | #define H8TSTR_STR1 (1<<H8TSTR_STR1_BIT)
|
---|
| 532 | #define H8TSTR_STR0 (1<<H8TSTR_STR0_BIT)
|
---|
| 533 |
|
---|
| 534 | /* Timer Synchronous Register (TSNC) */
|
---|
| 535 |
|
---|
| 536 | #define H8TSNC_SYNC2_BIT 2
|
---|
| 537 | #define H8TSNC_SYNC1_BIT 1
|
---|
| 538 | #define H8TSNC_SYNC0_BIT 0
|
---|
| 539 |
|
---|
| 540 | #define H8TSNC_SYNC2 (1<<H8TSNC_SYNC2_BIT)
|
---|
| 541 | #define H8TSNC_SYNC1 (1<<H8TSNC_SYNC1_BIT)
|
---|
| 542 | #define H8TSNC_SYNC0 (1<<H8TSNC_SYNC0_BIT)
|
---|
| 543 |
|
---|
| 544 | /* Timer Mode Register (TMDR) */
|
---|
| 545 |
|
---|
| 546 | #define H8TMDR_MDF_BIT 6
|
---|
| 547 | #define H8TMDR_FDIR_BIT 5
|
---|
| 548 | #define H8TMDR_PWM2_BIT 2
|
---|
| 549 | #define H8TMDR_PWM1_BIT 1
|
---|
| 550 | #define H8TMDR_PWM0_BIT 0
|
---|
| 551 |
|
---|
| 552 | #define H8TMDR_MDF (1<<H8TMDR_MDF_BIT)
|
---|
| 553 | #define H8TMDR_FDIR (1<<H8TMDR_FDIR_BIT)
|
---|
| 554 | #define H8TMDR_PWM2 (1<<H8TMDR_PWM2_BIT)
|
---|
| 555 | #define H8TMDR_PWM1 (1<<H8TMDR_PWM1_BIT)
|
---|
| 556 | #define H8TMDR_PWM0 (1<<H8TMDR_PWM0_BIT)
|
---|
| 557 |
|
---|
| 558 | /* Timer Interrupt Status Register A (TISRA) */
|
---|
| 559 |
|
---|
| 560 | #define H8TISRA_IMIEA2_BIT 6
|
---|
| 561 | #define H8TISRA_IMIEA1_BIT 5
|
---|
| 562 | #define H8TISRA_IMIEA0_BIT 4
|
---|
| 563 | #define H8TISRA_IMFA2_BIT 2
|
---|
| 564 | #define H8TISRA_IMFA1_BIT 1
|
---|
| 565 | #define H8TISRA_IMFA0_BIT 0
|
---|
| 566 |
|
---|
| 567 | #define H8TISRA_IMIEA2 (1<<H8TISRA_IMIEA2_BIT)
|
---|
| 568 | #define H8TISRA_IMIEA1 (1<<H8TISRA_IMIEA1_BIT)
|
---|
| 569 | #define H8TISRA_IMIEA0 (1<<H8TISRA_IMIEA0_BIT)
|
---|
| 570 | #define H8TISRA_IMFA2 (1<<H8TISRA_IMFA2_BIT)
|
---|
| 571 | #define H8TISRA_IMFA1 (1<<H8TISRA_IMFA1_BIT)
|
---|
| 572 | #define H8TISRA_IMFA0 (1<<H8TISRA_IMFA0_BIT)
|
---|
| 573 |
|
---|
| 574 | /* Timer Interrupt Status Register B (TISRB) */
|
---|
| 575 |
|
---|
| 576 | #define H8TISRB_IMIEB2_BIT 6
|
---|
| 577 | #define H8TISRB_IMIEB1_BIT 5
|
---|
| 578 | #define H8TISRB_IMIEB0_BIT 4
|
---|
| 579 | #define H8TISRB_IMFB2_BIT 2
|
---|
| 580 | #define H8TISRB_IMFB1_BIT 1
|
---|
| 581 | #define H8TISRB_IMFB0_BIT 0
|
---|
| 582 |
|
---|
| 583 | #define H8TISRB_IMIEB2 (1<<H8TISRB_IMIEB2_BIT)
|
---|
| 584 | #define H8TISRB_IMIEB1 (1<<H8TISRB_IMIEB1_BIT)
|
---|
| 585 | #define H8TISRB_IMIEB0 (1<<H8TISRB_IMIEB0_BIT)
|
---|
| 586 | #define H8TISRB_IMFB2 (1<<H8TISRB_IMFB2_BIT)
|
---|
| 587 | #define H8TISRB_IMFB1 (1<<H8TISRB_IMFB1_BIT)
|
---|
| 588 | #define H8TISRB_IMFB0 (1<<H8TISRB_IMFB0_BIT)
|
---|
| 589 |
|
---|
| 590 | /* Timer Interrupt Status Register C (TISRC) */
|
---|
| 591 |
|
---|
| 592 | #define H8TISRC_OVIEA2_BIT 6
|
---|
| 593 | #define H8TISRC_OVIEA1_BIT 5
|
---|
| 594 | #define H8TISRC_OVIEA0_BIT 4
|
---|
| 595 | #define H8TISRC_OVFA2_BIT 2
|
---|
| 596 | #define H8TISRC_OVFA1_BIT 1
|
---|
| 597 | #define H8TISRC_OVFA0_BIT 0
|
---|
| 598 |
|
---|
| 599 | #define H8TISRC_OVIEA2 (1<<H8TISRC_OVIEA2_BIT)
|
---|
| 600 | #define H8TISRC_OVIEA1 (1<<H8TISRC_OVIEA1_BIT)
|
---|
| 601 | #define H8TISRC_OVIEA0 (1<<H8TISRC_OVIEA0_BIT)
|
---|
| 602 | #define H8TISRC_OVFA2 (1<<H8TISRC_OVFA2_BIT)
|
---|
| 603 | #define H8TISRC_OVFA1 (1<<H8TISRC_OVFA1_BIT)
|
---|
| 604 | #define H8TISRC_OVFA0 (1<<H8TISRC_OVFA0_BIT)
|
---|
| 605 |
|
---|
| 606 | /* Timer Control Register (TCR) */
|
---|
| 607 |
|
---|
| 608 | #define H8TCR_CCLR1_BIT 6
|
---|
| 609 | #define H8TCR_CCLR0_BIT 5
|
---|
| 610 | #define H8TCR_CKEG1_BIT 4
|
---|
| 611 | #define H8TCR_CKEG0_BIT 3
|
---|
| 612 | #define H8TCR_TPSC2_BIT 2
|
---|
| 613 | #define H8TCR_TPSC1_BIT 1
|
---|
| 614 | #define H8TCR_TPSC0_BIT 0
|
---|
| 615 |
|
---|
| 616 | #define H8TCR_CCLR1 (1<<H8TCR_CCLR1_BIT)
|
---|
| 617 | #define H8TCR_CCLR0 (1<<H8TCR_CCLR0_BIT)
|
---|
| 618 | #define H8TCR_CKEG1 (1<<H8TCR_CKEG1_BIT)
|
---|
| 619 | #define H8TCR_CKEG0 (1<<H8TCR_CKEG0_BIT)
|
---|
| 620 | #define H8TCR_TPSC2 (1<<H8TCR_TPSC2_BIT)
|
---|
| 621 | #define H8TCR_TPSC1 (1<<H8TCR_TPSC1_BIT)
|
---|
| 622 | #define H8TCR_TPSC0 (1<<H8TCR_TPSC0_BIT)
|
---|
| 623 |
|
---|
| 624 | /* Timer I/O Control Register (TIOR) */
|
---|
| 625 |
|
---|
| 626 | #define H8TIOR_IOB2_BIT 6
|
---|
| 627 | #define H8TIOR_IOB1_BIT 5
|
---|
| 628 | #define H8TIOR_IOB0_BIT 4
|
---|
| 629 | #define H8TIOR_IOA2_BIT 2
|
---|
| 630 | #define H8TIOR_IOA1_BIT 1
|
---|
| 631 | #define H8TIOR_IOA0_BIT 0
|
---|
| 632 |
|
---|
| 633 | #define H8TIOR_IOB2 (1<<H8TIOR_IOB2_BIT)
|
---|
| 634 | #define H8TIOR_IOB1 (1<<H8TIOR_IOB1_BIT)
|
---|
| 635 | #define H8TIOR_IOB0 (1<<H8TIOR_IOB0_BIT)
|
---|
| 636 | #define H8TIOR_IOA2 (1<<H8TIOR_IOA2_BIT)
|
---|
| 637 | #define H8TIOR_IOA1 (1<<H8TIOR_IOA1_BIT)
|
---|
| 638 | #define H8TIOR_IOA0 (1<<H8TIOR_IOA0_BIT)
|
---|
| 639 |
|
---|
| 640 | /* 8 bit Timer */
|
---|
| 641 |
|
---|
| 642 | #define H88TU0 0xffff80 /* base address */
|
---|
| 643 | #define H88TU1 0xffff81
|
---|
| 644 | #define H88TU2 0xffff90
|
---|
| 645 | #define H88TU3 0xffff91
|
---|
| 646 |
|
---|
| 647 | /* address offset */
|
---|
| 648 |
|
---|
| 649 | #define H88TCR 0
|
---|
| 650 | #define H88TCSR 2
|
---|
| 651 | #define H88TCORA 4
|
---|
| 652 | #define H88TCORB 6
|
---|
| 653 | #define H88TCNT 8
|
---|
| 654 |
|
---|
| 655 | /* 8 Bit Timer Control Register (8TCR) */
|
---|
| 656 |
|
---|
| 657 | #define H88TCR_CMIEB_BIT 7
|
---|
| 658 | #define H88TCR_CMIEA_BIT 6
|
---|
| 659 | #define H88TCR_OVIE_BIT 5
|
---|
| 660 | #define H88TCR_CCLR1_BIT 4
|
---|
| 661 | #define H88TCR_CCLR0_BIT 3
|
---|
| 662 | #define H88TCR_CKS2_BIT 2
|
---|
| 663 | #define H88TCR_CKS1_BIT 1
|
---|
| 664 | #define H88TCR_CKS0_BIT 0
|
---|
| 665 |
|
---|
| 666 | #define H88TCR_CMIEB (1<<H88TCR_CMIEB_BIT)
|
---|
| 667 | #define H88TCR_CMIEA (1<<H88TCR_CMIEA_BIT)
|
---|
| 668 | #define H88TCR_OVIE (1<<H88TCR_OVIE_BIT)
|
---|
| 669 | #define H88TCR_CCLR1 (1<<H88TCR_CCLR1_BIT)
|
---|
| 670 | #define H88TCR_CCLR0 (1<<H88TCR_CCLR0_BIT)
|
---|
| 671 | #define H88TCR_CKS2 (1<<H88TCR_CKS2_BIT)
|
---|
| 672 | #define H88TCR_CKS1 (1<<H88TCR_CKS1_BIT)
|
---|
| 673 | #define H88TCR_CKS0 (1<<H88TCR_CKS0_BIT)
|
---|
| 674 |
|
---|
| 675 | /* 8 Bit Timer Control/Status Register (8TCSR) */
|
---|
| 676 |
|
---|
| 677 | #define H88TCSR_CMFB_BIT 7
|
---|
| 678 | #define H88TCSR_CMFA_BIT 6
|
---|
| 679 | #define H88TCSR_OVF_BIT 5
|
---|
| 680 | #define H88TCSR_ADTE_BIT 4
|
---|
| 681 | #define H88TCSR_ICE_BIT 4
|
---|
| 682 | #define H88TCSR_OIS3_BIT 3
|
---|
| 683 | #define H88TCSR_OIS2_BIT 2
|
---|
| 684 | #define H88TCSR_OS1_BIT 1
|
---|
| 685 | #define H88TCSR_OS0_BIT 0
|
---|
| 686 |
|
---|
| 687 | #define H88TCSR_CMFB (1<<H88TCSR_CMFB_BIT)
|
---|
| 688 | #define H88TCSR_CMFA (1<<H88TCSR_CMFA_BIT)
|
---|
| 689 | #define H88TCSR_OVF (1<<H88TCSR_OVF_BIT)
|
---|
| 690 | #define H88TCSR_ADTE (1<<H88TCSR_ADTE_BIT)
|
---|
| 691 | #define H88TCSR_ICE (1<<H88TCSR_ICE_BIT)
|
---|
| 692 | #define H88TCSR_OIS3 (1<<H88TCSR_OIS3_BIT)
|
---|
| 693 | #define H88TCSR_OIS2 (1<<H88TCSR_OIS2_BIT)
|
---|
| 694 | #define H88TCSR_OS1 (1<<H88TCSR_OS1_BIT)
|
---|
| 695 | #define H88TCSR_OS0 (1<<H88TCSR_OS0_BIT)
|
---|
| 696 |
|
---|
| 697 | /* Serial Communication Interface (SCI) */
|
---|
| 698 |
|
---|
| 699 | #define H8SCI0 0xffffb0 /* base address */
|
---|
| 700 | #define H8SCI1 0xffffb8
|
---|
| 701 | #define H8SCI2 0xffffc0
|
---|
| 702 |
|
---|
| 703 | /* address offset */
|
---|
| 704 |
|
---|
| 705 | #define H8SMR 0
|
---|
| 706 | #define H8BRR 1
|
---|
| 707 | #define H8SCR 2
|
---|
| 708 | #define H8TDR 3
|
---|
| 709 | #define H8SSR 4
|
---|
| 710 | #define H8RDR 5
|
---|
| 711 | #define H8SCMR 6
|
---|
| 712 |
|
---|
| 713 | /* SCI Serial Mode Register (SMR) */
|
---|
| 714 |
|
---|
| 715 | #define H8SMR_GM_BIT 7
|
---|
| 716 | #define H8SMR_CHR_BIT 6
|
---|
| 717 | #define H8SMR_PE_BIT 5
|
---|
| 718 | #define H8SMR_OE_BIT 4
|
---|
| 719 | #define H8SMR_STOP_BIT 3
|
---|
| 720 | #define H8SMR_MP_BIT 2
|
---|
| 721 | #define H8SMR_CKS1_BIT 1
|
---|
| 722 | #define H8SMR_CKS0_BIT 0
|
---|
| 723 |
|
---|
| 724 | #define H8SMR_GM (1<<H8SMR_GM_BIT)
|
---|
| 725 | #define H8SMR_CHR (1<<H8SMR_CHR_BIT)
|
---|
| 726 | #define H8SMR_PE (1<<H8SMR_PE_BIT)
|
---|
| 727 | #define H8SMR_OE (1<<H8SMR_OE_BIT)
|
---|
| 728 | #define H8SMR_STOP (1<<H8SMR_STOP_BIT)
|
---|
| 729 | #define H8SMR_MP (1<<H8SMR_MP_BIT)
|
---|
| 730 | #define H8SMR_CKS1 (1<<H8SMR_CKS1_BIT)
|
---|
| 731 | #define H8SMR_CKS0 (1<<H8SMR_CKS0_BIT)
|
---|
| 732 | #define H8SMR_CKS_MASK (H8SMR_CKS1|H8SMR_CKS0)
|
---|
| 733 |
|
---|
| 734 | /* SCI Serial Control Register (SCR) */
|
---|
| 735 |
|
---|
| 736 | #define H8SCR_TIE_BIT 7
|
---|
| 737 | #define H8SCR_RIE_BIT 6
|
---|
| 738 | #define H8SCR_TE_BIT 5
|
---|
| 739 | #define H8SCR_RE_BIT 4
|
---|
| 740 | #define H8SCR_MPIE_BIT 3
|
---|
| 741 | #define H8SCR_TEIE_BIT 2
|
---|
| 742 | #define H8SCR_CKE1_BIT 1
|
---|
| 743 | #define H8SCR_CKE0_BIT 0
|
---|
| 744 |
|
---|
| 745 | #define H8SCR_TIE (1<<H8SCR_TIE_BIT)
|
---|
| 746 | #define H8SCR_RIE (1<<H8SCR_RIE_BIT)
|
---|
| 747 | #define H8SCR_TE (1<<H8SCR_TE_BIT)
|
---|
| 748 | #define H8SCR_RE (1<<H8SCR_RE_BIT)
|
---|
| 749 | #define H8SCR_MPIE (1<<H8SCR_MPIE_BIT)
|
---|
| 750 | #define H8SCR_TEIE (1<<H8SCR_TEIE_BIT)
|
---|
| 751 | #define H8SCR_CKE1 (1<<H8SCR_CKE1_BIT)
|
---|
| 752 | #define H8SCR_CKE0 (1<<H8SCR_CKE0_BIT)
|
---|
| 753 | #define H8SCR_CKE_MASK (H8SCR_CKE1|H8SCR_CKE0)
|
---|
| 754 | #define H8SCR_IE (H8SCR_TIE|H8SCR_RIE|H8SCR_MPIE|H8SCR_TEIE)
|
---|
| 755 |
|
---|
| 756 | /* SCI Serial Status Register (SSR) */
|
---|
| 757 |
|
---|
| 758 | #define H8SSR_TDRE_BIT 7
|
---|
| 759 | #define H8SSR_RDRF_BIT 6
|
---|
| 760 | #define H8SSR_ORER_BIT 5
|
---|
| 761 | #define H8SSR_FER_BIT 4
|
---|
| 762 | #define H8SSR_PER_BIT 3
|
---|
| 763 | #define H8SSR_TEND_BIT 2
|
---|
| 764 | #define H8SSR_MPB_BIT 1
|
---|
| 765 | #define H8SSR_MPBT_BIT 0
|
---|
| 766 |
|
---|
| 767 | #define H8SSR_TDRE (1<<H8SSR_TDRE_BIT)
|
---|
| 768 | #define H8SSR_RDRF (1<<H8SSR_RDRF_BIT)
|
---|
| 769 | #define H8SSR_ORER (1<<H8SSR_ORER_BIT)
|
---|
| 770 | #define H8SSR_FER (1<<H8SSR_FER_BIT)
|
---|
| 771 | #define H8SSR_PER (1<<H8SSR_PER_BIT)
|
---|
| 772 | #define H8SSR_TEND (1<<H8SSR_TEND_BIT)
|
---|
| 773 | #define H8SSR_MPB (1<<H8SSR_MPB_BIT)
|
---|
| 774 | #define H8SSR_MPBT (1<<H8SSR_MPBT_BIT)
|
---|
| 775 |
|
---|
| 776 |
|
---|
| 777 | /* Bus Release Control Regisger */
|
---|
| 778 |
|
---|
| 779 | #define H8BRCR 0xfee013
|
---|
| 780 |
|
---|
| 781 | /* Control bit in BRCR */
|
---|
| 782 |
|
---|
| 783 | #define H8BRCR_A23E_BIT 7
|
---|
| 784 | #define H8BRCR_A22E_BIT 6
|
---|
| 785 | #define H8BRCR_A21E_BIT 5
|
---|
| 786 | #define H8BRCR_BRLE_BIT 1
|
---|
| 787 |
|
---|
| 788 | #define H8BRCR_A23E (1<<(H8BRCR_A23E_BIT))
|
---|
| 789 | #define H8BRCR_A22E (1<<(H8BRCR_A22E_BIT))
|
---|
| 790 | #define H8BRCR_A21E (1<<(H8BRCR_A21E_BIT))
|
---|
| 791 | #define H8BRCR_BRLE (1<<(H8BRCR_BRLE_BIT))
|
---|
| 792 |
|
---|
| 793 | /* DRAM Control Registers */
|
---|
| 794 |
|
---|
| 795 | #define H8DRCRA 0xfee026 /* Control Register A */
|
---|
| 796 | #define H8DRCRB 0xfee027 /* Control Register B */
|
---|
| 797 | #define H8RTMCSR 0xfee028 /* Timer Control / Status Register */
|
---|
| 798 | #define H8RTCNT 0xfee029 /* Reflesh Timer Counter */
|
---|
| 799 | #define H8RTCOR 0xfee02a /* Reflesh Time Constant Register */
|
---|
| 800 |
|
---|
| 801 | /* DRAM Control Register A */
|
---|
| 802 |
|
---|
| 803 | #define H8DRCRA_DRAS2_BIT 7
|
---|
| 804 | #define H8DRCRA_DRAS1_BIT 6
|
---|
| 805 | #define H8DRCRA_DRAS0_BIT 5
|
---|
| 806 | #define H8DRCRA_BE_BIT 3
|
---|
| 807 | #define H8DRCRA_RDM_BIT 2
|
---|
| 808 | #define H8DRCRA_SRFMD_BIT 1
|
---|
| 809 | #define H8DRCRA_RFSHE_BIT 0
|
---|
| 810 |
|
---|
| 811 | #define H8DRCRA_DRAS2 (1<<H8DRCRA_DRAS2_BIT)
|
---|
| 812 | #define H8DRCRA_DRAS1 (1<<H8DRCRA_DRAS1_BIT)
|
---|
| 813 | #define H8DRCRA_DRAS0 (1<<H8DRCRA_DRAS0_BIT)
|
---|
| 814 | #define H8DRCRA_BE (1<<H8DRCRA_BE_BIT)
|
---|
| 815 | #define H8DRCRA_RDM (1<<H8DRCRA_RDM_BIT)
|
---|
| 816 | #define H8DRCRA_SRFMD (1<<H8DRCRA_SRFMD_BIT)
|
---|
| 817 | #define H8DRCRA_RFSHE (1<<H8DRCRA_RFSHE_BIT)
|
---|
| 818 |
|
---|
| 819 | /* DRAM Control Register B */
|
---|
| 820 |
|
---|
| 821 | #define H8DRCRB_MXC1_BIT 7
|
---|
| 822 | #define H8DRCRB_MXC0_BIT 6
|
---|
| 823 | #define H8DRCRB_CSEL_BIT 5
|
---|
| 824 | #define H8DRCRB_RCYCE_BIT 4
|
---|
| 825 | #define H8DRCRB_TPC_BIT 2
|
---|
| 826 | #define H8DRCRB_RCW_BIT 1
|
---|
| 827 | #define H8DRCRB_RLW_BIT 0
|
---|
| 828 |
|
---|
| 829 | #define H8DRCRB_MXC1 (1<<H8DRCRB_MXC1_BIT)
|
---|
| 830 | #define H8DRCRB_MXC0 (1<<H8DRCRB_MXC0_BIT)
|
---|
| 831 | #define H8DRCRB_CSEL (1<<H8DRCRB_CSEL_BIT)
|
---|
| 832 | #define H8DRCRB_RCYCE (1<<H8DRCRB_RCYCE_BIT)
|
---|
| 833 | #define H8DRCRB_TPC (1<<H8DRCRB_TPC_BIT)
|
---|
| 834 | #define H8DRCRB_RCW (1<<H8DRCRB_RCW_BIT)
|
---|
| 835 | #define H8DRCRB_RLW (1<<H8DRCRB_RLW_BIT)
|
---|
| 836 |
|
---|
| 837 | /* Reflesh Timer Control / Status Register */
|
---|
| 838 |
|
---|
| 839 | #define H8RTMCSR_CMF_BIT 7
|
---|
| 840 | #define H8RTMCSR_CMIE_BIT 6
|
---|
| 841 | #define H8RTMCSR_CKS2_BIT 5
|
---|
| 842 | #define H8RTMCSR_CKS1_BIT 4
|
---|
| 843 | #define H8RTMCSR_CKS0_BIT 3
|
---|
| 844 |
|
---|
| 845 | #define H8RTMCSR_CMF (1<<H8RTMCSR_CMF_BIT)
|
---|
| 846 | #define H8RTMCSR_CMIE (1<<H8RTMCSR_CMIE_BIT)
|
---|
| 847 | #define H8RTMCSR_CKS2 (1<<H8RTMCSR_CKS2_BIT)
|
---|
| 848 | #define H8RTMCSR_CKS1 (1<<H8RTMCSR_CKS1_BIT)
|
---|
| 849 | #define H8RTMCSR_CKS0 (1<<H8RTMCSR_CKS0_BIT)
|
---|
| 850 |
|
---|
| 851 | /* BUS Wait Control Registers */
|
---|
| 852 | #define H8WCRH 0xfee022 /* Control Register H */
|
---|
| 853 | #define H8WCRL 0xfee023 /* Control Register L */
|
---|
| 854 |
|
---|
| 855 | #define H8WCRH_W71_BIT 6
|
---|
| 856 | #define H8WCRH_W70_BIT 6
|
---|
| 857 | #define H8WCRH_W61_BIT 5
|
---|
| 858 | #define H8WCRH_W60_BIT 4
|
---|
| 859 | #define H8WCRH_W51_BIT 3
|
---|
| 860 | #define H8WCRH_W50_BIT 2
|
---|
| 861 | #define H8WCRH_W41_BIT 1
|
---|
| 862 | #define H8WCRH_W40_BIT 0
|
---|
| 863 |
|
---|
| 864 | #define H8WCRL_W31_BIT 7
|
---|
| 865 | #define H8WCRL_W30_BIT 6
|
---|
| 866 | #define H8WCRL_W21_BIT 5
|
---|
| 867 | #define H8WCRL_W20_BIT 4
|
---|
| 868 | #define H8WCRL_W11_BIT 3
|
---|
| 869 | #define H8WCRL_W10_BIT 2
|
---|
| 870 | #define H8WCRL_W01_BIT 1
|
---|
| 871 | #define H8WCRL_W00_BIT 0
|
---|
| 872 |
|
---|
| 873 | #define H8WCRH_W7_NOWAIT (0<<H8WCRH_W70_BIT)
|
---|
| 874 | #define H8WCRH_W7_1WAIT (1<<H8WCRH_W70_BIT)
|
---|
| 875 | #define H8WCRH_W7_2WAIT (2<<H8WCRH_W70_BIT)
|
---|
| 876 | #define H8WCRH_W7_3WAIT (3<<H8WCRH_W70_BIT)
|
---|
| 877 | #define H8WCRH_W6_NOWAIT (0<<H8WCRH_W60_BIT)
|
---|
| 878 | #define H8WCRH_W6_1WAIT (1<<H8WCRH_W60_BIT)
|
---|
| 879 | #define H8WCRH_W6_2WAIT (2<<H8WCRH_W60_BIT)
|
---|
| 880 | #define H8WCRH_W6_3WAIT (3<<H8WCRH_W60_BIT)
|
---|
| 881 | #define H8WCRH_W5_NOWAIT (0<<H8WCRH_W50_BIT)
|
---|
| 882 | #define H8WCRH_W5_1WAIT (1<<H8WCRH_W50_BIT)
|
---|
| 883 | #define H8WCRH_W5_2WAIT (2<<H8WCRH_W50_BIT)
|
---|
| 884 | #define H8WCRH_W5_3WAIT (3<<H8WCRH_W50_BIT)
|
---|
| 885 | #define H8WCRH_W4_NOWAIT (0<<H8WCRH_W40_BIT)
|
---|
| 886 | #define H8WCRH_W4_1WAIT (1<<H8WCRH_W40_BIT)
|
---|
| 887 | #define H8WCRH_W4_2WAIT (2<<H8WCRH_W40_BIT)
|
---|
| 888 | #define H8WCRH_W4_3WAIT (3<<H8WCRH_W40_BIT)
|
---|
| 889 | #define H8WCRL_W3_NOWAIT (0<<H8WCRL_W30_BIT)
|
---|
| 890 | #define H8WCRL_W3_1WAIT (1<<H8WCRL_W30_BIT)
|
---|
| 891 | #define H8WCRL_W3_2WAIT (2<<H8WCRL_W30_BIT)
|
---|
| 892 | #define H8WCRL_W3_3WAIT (3<<H8WCRL_W30_BIT)
|
---|
| 893 | #define H8WCRL_W2_NOWAIT (0<<H8WCRL_W20_BIT)
|
---|
| 894 | #define H8WCRL_W2_1WAIT (1<<H8WCRL_W20_BIT)
|
---|
| 895 | #define H8WCRL_W2_2WAIT (2<<H8WCRL_W20_BIT)
|
---|
| 896 | #define H8WCRL_W2_3WAIT (3<<H8WCRL_W20_BIT)
|
---|
| 897 | #define H8WCRL_W1_NOWAIT (0<<H8WCRL_W10_BIT)
|
---|
| 898 | #define H8WCRL_W1_1WAIT (1<<H8WCRL_W10_BIT)
|
---|
| 899 | #define H8WCRL_W1_2WAIT (2<<H8WCRL_W10_BIT)
|
---|
| 900 | #define H8WCRL_W1_3WAIT (3<<H8WCRL_W10_BIT)
|
---|
| 901 | #define H8WCRL_W0_NOWAIT (0<<H8WCRL_W00_BIT)
|
---|
| 902 | #define H8WCRL_W0_1WAIT (1<<H8WCRL_W00_BIT)
|
---|
| 903 | #define H8WCRL_W0_2WAIT (2<<H8WCRL_W00_BIT)
|
---|
| 904 | #define H8WCRL_W0_3WAIT (3<<H8WCRL_W00_BIT)
|
---|
| 905 |
|
---|
| 906 | /* BUS Access State Control Register */
|
---|
| 907 |
|
---|
| 908 | #define H8ASTCR 0xfee021
|
---|
| 909 |
|
---|
| 910 | #define H8ASTCR_AST7_BIT 7
|
---|
| 911 | #define H8ASTCR_AST6_BIT 6
|
---|
| 912 | #define H8ASTCR_AST5_BIT 5
|
---|
| 913 | #define H8ASTCR_AST4_BIT 4
|
---|
| 914 | #define H8ASTCR_AST3_BIT 3
|
---|
| 915 | #define H8ASTCR_AST2_BIT 2
|
---|
| 916 | #define H8ASTCR_AST1_BIT 1
|
---|
| 917 | #define H8ASTCR_AST0_BIT 0
|
---|
| 918 |
|
---|
| 919 | #define H8ASTCR_AST7 (1<<H8ASTCR_AST7_BIT)
|
---|
| 920 | #define H8ASTCR_AST6 (1<<H8ASTCR_AST6_BIT)
|
---|
| 921 | #define H8ASTCR_AST5 (1<<H8ASTCR_AST5_BIT)
|
---|
| 922 | #define H8ASTCR_AST4 (1<<H8ASTCR_AST4_BIT)
|
---|
| 923 | #define H8ASTCR_AST3 (1<<H8ASTCR_AST3_BIT)
|
---|
| 924 | #define H8ASTCR_AST2 (1<<H8ASTCR_AST2_BIT)
|
---|
| 925 | #define H8ASTCR_AST1 (1<<H8ASTCR_AST1_BIT)
|
---|
| 926 | #define H8ASTCR_AST0 (1<<H8ASTCR_AST0_BIT)
|
---|
| 927 |
|
---|
| 928 | /*
|
---|
| 929 | * å
|
---|
| 930 | èµã¡ã¢ãªã®å®ç¾©
|
---|
| 931 | */
|
---|
| 932 | #define H8IN_ROM_BASE 0x000000
|
---|
| 933 | #define H8IN_ROM_SIZE 0x080000
|
---|
| 934 | #define H8IN_RAM_BASE 0xffbf20
|
---|
| 935 | #define H8IN_RAM_SIZE 0x004000
|
---|
| 936 |
|
---|
| 937 |
|
---|
| 938 | /*
|
---|
| 939 | * I/Oãã¼ã
|
---|
| 940 | */
|
---|
| 941 | #define H8PORT_NUM 12 /* ãã¼ã1ããã¼ãB (DDRå¤ä¸æä¿åç¨) */
|
---|
| 942 |
|
---|
| 943 | /* ãã¼ã1 */
|
---|
| 944 | #define H8P10DDR 0x01
|
---|
| 945 | #define H8P11DDR 0x02
|
---|
| 946 | #define H8P12DDR 0x04
|
---|
| 947 | #define H8P13DDR 0x08
|
---|
| 948 | #define H8P14DDR 0x10
|
---|
| 949 | #define H8P15DDR 0x20
|
---|
| 950 | #define H8P16DDR 0x40
|
---|
| 951 | #define H8P17DDR 0x80
|
---|
| 952 |
|
---|
| 953 | #define H8P10DR 0x01
|
---|
| 954 | #define H8P11DR 0x02
|
---|
| 955 | #define H8P12DR 0x04
|
---|
| 956 | #define H8P13DR 0x08
|
---|
| 957 | #define H8P14DR 0x10
|
---|
| 958 | #define H8P15DR 0x20
|
---|
| 959 | #define H8P16DR 0x40
|
---|
| 960 | #define H8P17DR 0x80
|
---|
| 961 |
|
---|
| 962 | /* ãã¼ã2 */
|
---|
| 963 | #define H8P20DDR 0x01
|
---|
| 964 | #define H8P21DDR 0x02
|
---|
| 965 | #define H8P22DDR 0x04
|
---|
| 966 | #define H8P23DDR 0x08
|
---|
| 967 | #define H8P24DDR 0x10
|
---|
| 968 | #define H8P25DDR 0x20
|
---|
| 969 | #define H8P26DDR 0x40
|
---|
| 970 | #define H8P27DDR 0x80
|
---|
| 971 |
|
---|
| 972 | #define H8P20DR 0x01
|
---|
| 973 | #define H8P21DR 0x02
|
---|
| 974 | #define H8P22DR 0x04
|
---|
| 975 | #define H8P23DR 0x08
|
---|
| 976 | #define H8P24DR 0x10
|
---|
| 977 | #define H8P25DR 0x20
|
---|
| 978 | #define H8P26DR 0x40
|
---|
| 979 | #define H8P27DR 0x80
|
---|
| 980 |
|
---|
| 981 | #define H8P20PCR 0x01
|
---|
| 982 | #define H8P21PCR 0x02
|
---|
| 983 | #define H8P22PCR 0x04
|
---|
| 984 | #define H8P23PCR 0x08
|
---|
| 985 | #define H8P24PCR 0x10
|
---|
| 986 | #define H8P25PCR 0x20
|
---|
| 987 | #define H8P26PCR 0x40
|
---|
| 988 | #define H8P27PCR 0x80
|
---|
| 989 |
|
---|
| 990 | /* ãã¼ã3 */
|
---|
| 991 | #define H8P30DDR 0x01
|
---|
| 992 | #define H8P31DDR 0x02
|
---|
| 993 | #define H8P32DDR 0x04
|
---|
| 994 | #define H8P33DDR 0x08
|
---|
| 995 | #define H8P34DDR 0x10
|
---|
| 996 | #define H8P35DDR 0x20
|
---|
| 997 | #define H8P36DDR 0x40
|
---|
| 998 | #define H8P37DDR 0x80
|
---|
| 999 |
|
---|
| 1000 | #define H8P30DR 0x01
|
---|
| 1001 | #define H8P31DR 0x02
|
---|
| 1002 | #define H8P32DR 0x04
|
---|
| 1003 | #define H8P33DR 0x08
|
---|
| 1004 | #define H8P34DR 0x10
|
---|
| 1005 | #define H8P35DR 0x20
|
---|
| 1006 | #define H8P36DR 0x40
|
---|
| 1007 | #define H8P37DR 0x80
|
---|
| 1008 |
|
---|
| 1009 | /* ãã¼ã4 */
|
---|
| 1010 | #define H8P40DDR 0x01
|
---|
| 1011 | #define H8P41DDR 0x02
|
---|
| 1012 | #define H8P42DDR 0x04
|
---|
| 1013 | #define H8P43DDR 0x08
|
---|
| 1014 | #define H8P44DDR 0x10
|
---|
| 1015 | #define H8P45DDR 0x20
|
---|
| 1016 | #define H8P46DDR 0x40
|
---|
| 1017 | #define H8P47DDR 0x80
|
---|
| 1018 |
|
---|
| 1019 | #define H8P40DR 0x01
|
---|
| 1020 | #define H8P41DR 0x02
|
---|
| 1021 | #define H8P42DR 0x04
|
---|
| 1022 | #define H8P43DR 0x08
|
---|
| 1023 | #define H8P44DR 0x10
|
---|
| 1024 | #define H8P45DR 0x20
|
---|
| 1025 | #define H8P46DR 0x40
|
---|
| 1026 | #define H8P47DR 0x80
|
---|
| 1027 |
|
---|
| 1028 | #define H8P40PCR 0x01
|
---|
| 1029 | #define H8P41PCR 0x02
|
---|
| 1030 | #define H8P42PCR 0x04
|
---|
| 1031 | #define H8P43PCR 0x08
|
---|
| 1032 | #define H8P44PCR 0x10
|
---|
| 1033 | #define H8P45PCR 0x20
|
---|
| 1034 | #define H8P46PCR 0x40
|
---|
| 1035 | #define H8P47PCR 0x80
|
---|
| 1036 |
|
---|
| 1037 | /* ãã¼ã5 */
|
---|
| 1038 | #define H8P50DDR 0x01
|
---|
| 1039 | #define H8P51DDR 0x02
|
---|
| 1040 | #define H8P52DDR 0x04
|
---|
| 1041 | #define H8P53DDR 0x08
|
---|
| 1042 |
|
---|
| 1043 | #define H8P50DR 0x01
|
---|
| 1044 | #define H8P51DR 0x02
|
---|
| 1045 | #define H8P52DR 0x04
|
---|
| 1046 | #define H8P53DR 0x08
|
---|
| 1047 |
|
---|
| 1048 | #define H8P50PCR 0x01
|
---|
| 1049 | #define H8P51PCR 0x02
|
---|
| 1050 | #define H8P52PCR 0x04
|
---|
| 1051 | #define H8P53PCR 0x08
|
---|
| 1052 |
|
---|
| 1053 | /* ãã¼ã6 */
|
---|
| 1054 | #define H8P60DDR 0x01
|
---|
| 1055 | #define H8P61DDR 0x02
|
---|
| 1056 | #define H8P62DDR 0x04
|
---|
| 1057 | #define H8P63DDR 0x08
|
---|
| 1058 | #define H8P64DDR 0x10
|
---|
| 1059 | #define H8P65DDR 0x20
|
---|
| 1060 | #define H8P66DDR 0x40
|
---|
| 1061 | #define H8P67DDR 0x80
|
---|
| 1062 |
|
---|
| 1063 | #define H8P60DR 0x01
|
---|
| 1064 | #define H8P61DR 0x02
|
---|
| 1065 | #define H8P62DR 0x04
|
---|
| 1066 | #define H8P63DR 0x08
|
---|
| 1067 | #define H8P64DR 0x10
|
---|
| 1068 | #define H8P65DR 0x20
|
---|
| 1069 | #define H8P66DR 0x40
|
---|
| 1070 | #define H8P67DR 0x80
|
---|
| 1071 |
|
---|
| 1072 | /* ãã¼ã7 */
|
---|
| 1073 | #define H8P70DDR 0x01
|
---|
| 1074 | #define H8P71DDR 0x02
|
---|
| 1075 | #define H8P72DDR 0x04
|
---|
| 1076 | #define H8P73DDR 0x08
|
---|
| 1077 | #define H8P74DDR 0x10
|
---|
| 1078 | #define H8P75DDR 0x20
|
---|
| 1079 | #define H8P76DDR 0x40
|
---|
| 1080 | #define H8P77DDR 0x80
|
---|
| 1081 |
|
---|
| 1082 | /* ãã¼ã8 */
|
---|
| 1083 | #define H8P80DDR 0x01
|
---|
| 1084 | #define H8P81DDR 0x02
|
---|
| 1085 | #define H8P82DDR 0x04
|
---|
| 1086 | #define H8P83DDR 0x08
|
---|
| 1087 | #define H8P84DDR 0x10
|
---|
| 1088 |
|
---|
| 1089 | #define H8P80DR 0x01
|
---|
| 1090 | #define H8P81DR 0x02
|
---|
| 1091 | #define H8P82DR 0x04
|
---|
| 1092 | #define H8P83DR 0x08
|
---|
| 1093 | #define H8P84DR 0x10
|
---|
| 1094 |
|
---|
| 1095 | /* ãã¼ã9 */
|
---|
| 1096 | #define H8P90DDR 0x01
|
---|
| 1097 | #define H8P91DDR 0x02
|
---|
| 1098 | #define H8P92DDR 0x04
|
---|
| 1099 | #define H8P93DDR 0x08
|
---|
| 1100 | #define H8P94DDR 0x10
|
---|
| 1101 | #define H8P95DDR 0x20
|
---|
| 1102 |
|
---|
| 1103 | #define H8P90DR 0x01
|
---|
| 1104 | #define H8P91DR 0x02
|
---|
| 1105 | #define H8P92DR 0x04
|
---|
| 1106 | #define H8P93DR 0x08
|
---|
| 1107 | #define H8P94DR 0x10
|
---|
| 1108 | #define H8P95DR 0x20
|
---|
| 1109 |
|
---|
| 1110 | /* ãã¼ãA */
|
---|
| 1111 | #define H8PA0DDR 0x01
|
---|
| 1112 | #define H8PA1DDR 0x02
|
---|
| 1113 | #define H8PA2DDR 0x04
|
---|
| 1114 | #define H8PA3DDR 0x08
|
---|
| 1115 | #define H8PA4DDR 0x10
|
---|
| 1116 | #define H8PA5DDR 0x20
|
---|
| 1117 | #define H8PA6DDR 0x40
|
---|
| 1118 | #define H8PA7DDR 0x80
|
---|
| 1119 |
|
---|
| 1120 | #define H8PA0DR 0x01
|
---|
| 1121 | #define H8PA1DR 0x02
|
---|
| 1122 | #define H8PA2DR 0x04
|
---|
| 1123 | #define H8PA3DR 0x08
|
---|
| 1124 | #define H8PA4DR 0x10
|
---|
| 1125 | #define H8PA5DR 0x20
|
---|
| 1126 | #define H8PA6DR 0x40
|
---|
| 1127 | #define H8PA7DR 0x80
|
---|
| 1128 |
|
---|
| 1129 | /* ãã¼ãB */
|
---|
| 1130 | #define H8PB0DDR 0x01
|
---|
| 1131 | #define H8PB1DDR 0x02
|
---|
| 1132 | #define H8PB2DDR 0x04
|
---|
| 1133 | #define H8PB3DDR 0x08
|
---|
| 1134 | #define H8PB4DDR 0x10
|
---|
| 1135 | #define H8PB5DDR 0x20
|
---|
| 1136 | #define H8PB6DDR 0x40
|
---|
| 1137 | #define H8PB7DDR 0x80
|
---|
| 1138 |
|
---|
| 1139 | #define H8PB0DR 0x01
|
---|
| 1140 | #define H8PB1DR 0x02
|
---|
| 1141 | #define H8PB2DR 0x04
|
---|
| 1142 | #define H8PB3DR 0x08
|
---|
| 1143 | #define H8PB4DR 0x10
|
---|
| 1144 | #define H8PB5DR 0x20
|
---|
| 1145 | #define H8PB6DR 0x40
|
---|
| 1146 | #define H8PB7DR 0x80
|
---|
| 1147 |
|
---|
| 1148 | /* Dï¼ï¼¡å¤æ */
|
---|
| 1149 | #define H8DADR0 0xFFFF9C
|
---|
| 1150 | #define H8DADR1 0xFFFF9D
|
---|
| 1151 | #define H8DACR 0xFFFF9E
|
---|
| 1152 | #define H8DASTCR 0xFEE01A
|
---|
| 1153 |
|
---|
| 1154 | #define H8DACR_DAOE1 0x80
|
---|
| 1155 | #define H8DACR_DAOE0 0x40
|
---|
| 1156 | #define H8DACR_DAE 0x20
|
---|
| 1157 | #define H8DASTCR_DASTE 0x01
|
---|
| 1158 |
|
---|
| 1159 | /* Aï¼ï¼¤å¤æ */
|
---|
| 1160 | #define H8ADDRA 0xFFFFE0
|
---|
| 1161 | #define H8ADDRB 0xFFFFE2
|
---|
| 1162 | #define H8ADDRC 0xFFFFE4
|
---|
| 1163 | #define H8ADDRD 0xFFFFE6
|
---|
| 1164 |
|
---|
| 1165 | #define H8ADDRAH H8ADDRA
|
---|
| 1166 | #define H8ADDRAL (H8ADDRA + 1)
|
---|
| 1167 | #define H8ADDRBH H8ADDRB
|
---|
| 1168 | #define H8ADDRBL (H8ADDRB + 1)
|
---|
| 1169 | #define H8ADDRCH H8ADDRC
|
---|
| 1170 | #define H8ADDRCL (H8ADDRC + 1)
|
---|
| 1171 | #define H8ADDRDH H8ADDRD
|
---|
| 1172 | #define H8ADDRDL (H8ADDRD + 1)
|
---|
| 1173 |
|
---|
| 1174 | #define H8ADCSR 0xFFFFE8
|
---|
| 1175 | #define H8ADCR 0xFFFFE9
|
---|
| 1176 |
|
---|
| 1177 | #define H8ADCSR_ADF 0x80
|
---|
| 1178 | #define H8ADCSR_ADIE 0x40
|
---|
| 1179 | #define H8ADCSR_ADST 0x20
|
---|
| 1180 | #define H8ADCSR_SCAN 0x10
|
---|
| 1181 | #define H8ADCSR_CKS 0x08
|
---|
| 1182 | #define H8ADCSR_CH2 0x04
|
---|
| 1183 | #define H8ADCSR_CH1 0x02
|
---|
| 1184 | #define H8ADCSR_CH0 0x01
|
---|
| 1185 |
|
---|
| 1186 | #define H8ADCR_TRGE 0x80
|
---|
| 1187 |
|
---|
| 1188 |
|
---|
| 1189 | /* DMA */
|
---|
| 1190 |
|
---|
| 1191 | /* DMAC ãã£ãã«0A */
|
---|
| 1192 | #define H8DMA_MAR0AR 0xffff20
|
---|
| 1193 | #define H8DMA_MAR0AE 0xffff21
|
---|
| 1194 | #define H8DMA_MAR0AH 0xffff22
|
---|
| 1195 | #define H8DMA_MAR0AL 0xffff23
|
---|
| 1196 | #define H8DMA_IOAR0A 0xffff26
|
---|
| 1197 | #define H8DMA_ETCR0AH 0xffff24
|
---|
| 1198 | #define H8DMA_ETCR0AL 0xffff25
|
---|
| 1199 | #define H8DMA_DTCR0A 0xffff27
|
---|
| 1200 |
|
---|
| 1201 | /* DMAC ãã£ãã«0B */
|
---|
| 1202 | #define H8DMA_MAR0BR 0xffff28
|
---|
| 1203 | #define H8DMA_MAR0BE 0xffff29
|
---|
| 1204 | #define H8DMA_MAR0BH 0xffff2A
|
---|
| 1205 | #define H8DMA_MAR0BL 0xffff2B
|
---|
| 1206 | #define H8DMA_IOAR0B 0xffff2E
|
---|
| 1207 | #define H8DMA_ETCR0BH 0xffff2C
|
---|
| 1208 | #define H8DMA_ETCR0BL 0xffff2D
|
---|
| 1209 | #define H8DMA_DTCR0B 0xffff2F
|
---|
| 1210 |
|
---|
| 1211 | /* DMAC ãã£ãã«1A */
|
---|
| 1212 | #define H8DMA_MAR1AR 0xffff30
|
---|
| 1213 | #define H8DMA_MAR1AE 0xffff31
|
---|
| 1214 | #define H8DMA_MAR1AH 0xffff32
|
---|
| 1215 | #define H8DMA_MAR1AL 0xffff33
|
---|
| 1216 | #define H8DMA_IOAR1A 0xffff36
|
---|
| 1217 | #define H8DMA_ETCR1AH 0xffff34
|
---|
| 1218 | #define H8DMA_ETCR1AL 0xffff35
|
---|
| 1219 | #define H8DMA_DTCR1A 0xffff37
|
---|
| 1220 |
|
---|
| 1221 | /* DMAC ãã£ãã«1B */
|
---|
| 1222 | #define H8DMA_MAR1BR 0xffff38
|
---|
| 1223 | #define H8DMA_MAR1BE 0xffff39
|
---|
| 1224 | #define H8DMA_MAR1BH 0xffff3A
|
---|
| 1225 | #define H8DMA_MAR1BL 0xffff3B
|
---|
| 1226 | #define H8DMA_IOAR1B 0xffff3E
|
---|
| 1227 | #define H8DMA_ETCR1BH 0xffff3C
|
---|
| 1228 | #define H8DMA_ETCR1BL 0xffff3D
|
---|
| 1229 | #define H8DMA_DTCR1B 0xffff3F
|
---|
| 1230 |
|
---|
| 1231 | /* ãã¼ã¿ãã©ã³ã¹ãã¡ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ (DTCR) */
|
---|
| 1232 | #define H8DMA_DTCR_DTE 0x80
|
---|
| 1233 | #define H8DMA_DTCR_DTSZ 0x40
|
---|
| 1234 | #define H8DMA_DTCR_DTID 0x20
|
---|
| 1235 | #define H8DMA_DTCR_RPE 0x10
|
---|
| 1236 | #define H8DMA_DTCR_DTIE 0x08
|
---|
| 1237 | #define H8DMA_DTCR_DTS2 0x04
|
---|
| 1238 | #define H8DMA_DTCR_DTS1 0x02
|
---|
| 1239 | #define H8DMA_DTCR_DTS0 0x01
|
---|
| 1240 |
|
---|
| 1241 | #endif /* _H8_3069F_H_ */
|
---|