[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2006 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2005-2006 by Logic Research Co., Ltd.
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| 9 | *
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| 10 | * ä¸è¨èä½æ¨©è
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| 11 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 12 | * ã«ãã£ã¦å
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| 13 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 14 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 15 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 16 | å¸ï¼ä»¥ä¸ï¼
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| 17 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 18 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 19 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 20 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 21 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 22 | * ç¨ã§ããå½¢ã§åé
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| 23 | å¸ããå ´åã«ã¯ï¼åé
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| 24 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 25 | * è
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| 26 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 27 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 28 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 29 | * ç¨ã§ããªãå½¢ã§åé
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| 30 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 31 | * ã¨ï¼
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| 32 | * (a) åé
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| 33 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 34 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 35 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 36 | * (b) åé
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| 37 | å¸ã®å½¢æ
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| 38 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 39 | * å ±åãããã¨ï¼
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| 40 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 41 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 43 | 責ãããã¨ï¼
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| 44 | *
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| 45 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 46 | ã
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| 47 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 48 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 49 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 50 | *
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| 51 | */
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| 52 |
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| 53 | #ifndef _FRK_ADUC_H_
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| 54 | #define _FRK_ADUC_H_
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| 55 |
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| 56 | #ifndef _MACRO_ONLY
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| 57 | #include <itron.h>
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| 58 | #include <sil.h>
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| 59 | #endif /* _MACRO_ONLY */
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| 60 |
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| 61 | #include <armv4.h>
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| 62 | #include "sys_config.h"
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| 63 | #include "cpu_config.h"
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| 64 |
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| 65 |
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| 66 |
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| 67 | /*
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| 68 | * GPIO
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| 69 | */
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| 70 | /* GPIO Register address */
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| 71 | #define GPIO_BASE 0xFFFFF400 /* GPIO base-address */
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| 72 | #define GP0CON (GPIO_BASE | 0x00) /* GPIO port0 condition register */
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| 73 | #define GP1CON (GPIO_BASE | 0x04) /* GPIO port1 condition register */
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| 74 | #define GP2CON (GPIO_BASE | 0x08) /* GPIO port2 condition register */
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| 75 | #define GP4CON (GPIO_BASE | 0x10) /* GPIO port4 condition register */
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| 76 | #define GP4DAT (GPIO_BASE | 0x60) /* GPIO data register */
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| 77 | #define GP4SET (GPIO_BASE | 0x64) /* GPIO SET feild */
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| 78 | #define GP4CLR (GPIO_BASE | 0x68) /* GPIO CLEAR feild */
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| 79 |
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| 80 | /* Port4 data */
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| 81 | #define P47_DIR 0x80000000 /* Port4 pin7 Direction - Output */
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| 82 | #define LED 0x00800000 /* Port4 pin7 data */
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| 83 |
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| 84 | /* Serial mode */
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| 85 | #define GP07_SIN 0x20000000
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| 86 | #define GP10_SIN 0x00000001
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| 87 | #define GP11_SOUT 0x00000010
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| 88 | #define GP12_RTS 0x00000100
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| 89 | #define GP13_CTS 0x00001000
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| 90 | #define GP14_RI 0x00010000
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| 91 | #define GP15_DCD 0x00100000
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| 92 | #define GP16_DSR 0x01000000
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| 93 | #define GP17_DTR 0x10000000
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| 94 | #define GP20_SOUT 0x00000002
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| 95 |
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| 96 |
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| 97 |
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| 98 |
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| 99 | /*
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| 100 | * PLL
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| 101 | */
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| 102 | /* PLL Registers */
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| 103 | #define PLL_BASE 0xFFFF0400 /* PLL base-address */
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| 104 | #define POWKEY1_VCT 0x04
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| 105 | #define POWCON_VCT 0x08
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| 106 | #define POWKEY2_VCT 0x0C
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| 107 | #define PLLKEY1_VCT 0x10
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| 108 | #define PLLCON_VCT 0x14
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| 109 | #define PLLKEY2_VCT 0x18
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| 110 |
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| 111 | #define POWKEY1 (PLL_BASE|POWKEY1_VCT) /* POWKEY1 address */
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| 112 | #define POWCON (PLL_BASE|POWCON_VCT) /* POWCOM address */
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| 113 | #define POWKEY2 (PLL_BASE|POWKEY2_VCT) /* POWKEY2 address */
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| 114 | #define PLLKEY1 (PLL_BASE|PLLKEY1_VCT) /* PLLKEY1 address */
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| 115 | #define PLLCON (PLL_BASE|PLLCON_VCT) /* PLLCON address */
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| 116 | #define PLLKEY2 (PLL_BASE|PLLKEY2_VCT) /* PLLKEY2 address */
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| 117 |
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| 118 |
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| 119 |
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| 120 | /* KEY's offset */
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| 121 | #define POWKEY1_DATA 0x01 /* POWKEY1 data */
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| 122 | #define POWKEY2_DATA 0xF4 /* POWKEY2 data */
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| 123 | #define PLLKEY1_DATA 0xAA /* PLLKEY1 data */
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| 124 | #define PLLKEY2_DATA 0x55 /* PLLKEY2 data */
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| 125 |
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| 126 | /* POWCON bits */
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| 127 | #define POWCON_PC_STP 0x40 /* Stop mode */
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| 128 | #define POWCON_PC_SLP 0x30 /* Sleep mode */
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| 129 | #define POWCON_PC_NAP 0x20 /* Nap. */
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| 130 | #define POWCON_PC_PAU 0x10 /* Pause mode */
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| 131 | #define POWCON_PC_ACT 0x00 /* Active mode */
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| 132 |
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| 133 | #define POWCON_CD_326K 0x07 /* Core Clock = 326KHz */
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| 134 | #define POWCON_CD_653K 0x06 /* Core Clock = 653KHz */
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| 135 | #define POWCON_CD_1M 0x05 /* Core Clock = 1.31MHz */
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| 136 | #define POWCON_CD_2M 0x04 /* Core Clock = 2.61MHz */
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| 137 | #define POWCON_CD_5M 0x03 /* Core Clock = 5.22MHz */
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| 138 | #define POWCON_CD_10M 0x02 /* Core Clock = 10.44MHz */
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| 139 | #define POWCON_CD_20M 0x01 /* Core Clock = 20.89MHz */
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| 140 | #define POWCON_CD_41M 0x00 /* Core Clock = 41.78MHz */
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| 141 |
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| 142 | /* PLLCON bits */
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| 143 | #define PLLCON_OSEL 0x20 /* 1:internal oscillator, 0:external crystal */
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| 144 |
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| 145 | #define PLLCON_MDCLK_EXT 0x03 /* External Clock on P0.7 pin */
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| 146 | #define PLLCON_MDCLK_PLL 0x01 /* PLL */
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| 147 |
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| 148 |
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| 149 |
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| 150 | /*
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| 151 | * FRK_ADuC Peripheral Base Address
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| 152 | */
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| 153 | #define IRQ_BASE 0xFFFF0000 /* IRQ base-address */
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| 154 | #define TIMER_BASE 0xFFFF0300 /* Timer base-address */
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| 155 | #define UART_BASE 0xFFFF0700
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| 156 |
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| 157 |
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| 158 |
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| 159 | /*
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| 160 | * Remap Register
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| 161 | */
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| 162 | #define REMAP 0xFFFF0220
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| 163 |
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| 164 | #define REMAP_SRAM 0x01 /* remap the sram to address to 0 */
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| 165 |
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| 166 |
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| 167 |
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| 168 | /*
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| 169 | * IRQ
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| 170 | */
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| 171 | /* IRQ Registers */
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| 172 | #define IRQSTA (IRQ_BASE | 0x00) /* IRQ Status Register */
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| 173 | #define IRQSIG (IRQ_BASE | 0x04) /* IRQ Signal Register */
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| 174 | #define IRQEN (IRQ_BASE | 0x08) /* IRQ enable Register */
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| 175 | #define IRQCLR (IRQ_BASE | 0x0C) /* IRQ Clear Register */
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| 176 | #define SWICFG (IRQ_BASE | 0x10)
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| 177 |
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| 178 | #define IRQ_PWMTRIP_BIT 23
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| 179 | #define IRQ_EXT3_BIT 22
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| 180 | #define IRQ_EXT2_BIT 21
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| 181 | #define IRQ_PLA1_BIT 20
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| 182 | #define IRQ_PLA0_BIT 19
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| 183 | #define IRQ_EXT1_BIT 18
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| 184 | #define IRQ_PSM_BIT 17
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| 185 | #define IRQ_COMP_BIT 16
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| 186 | #define IRQ_EXT0_BIT 15
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| 187 | #define IRQ_UART_BIT 14
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| 188 | #define IRQ_SPIM_BIT 13
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| 189 | #define IRQ_SPIS_BIT 12
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| 190 | #define IRQ_I2C1M_BIT 11
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| 191 | #define IRQ_I2C0M_BIT 10
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| 192 | #define IRQ_I2C0S_BIT 9
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| 193 | #define IRQ_PLLL_BIT 8
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| 194 | #define IRQ_ADCC_BIT 7
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| 195 | #define IRQ_FLAC_BIT 6
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| 196 | #define IRQ_TIM3_BIT 5
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| 197 | #define IRQ_TIM2_BIT 4
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| 198 | #define IRQ_TIM1_BIT 3
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| 199 | #define IRQ_TIM0_BIT 2
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| 200 | #define IRQ_SWI_BIT 1
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| 201 | #define ALL_INT_OR 0
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| 202 |
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| 203 | #define IRQ_PWM_TRIP (1 << IRQ_PWMT_BIT)
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| 204 | #define IRQ_EXT_IRQ3 (1 << IRQ_EXT3_BIT)
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| 205 | #define IRQ_EXT_IRQ2 (1 << IRQ_EXT2_BIT)
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| 206 | #define IRQ_PLA_IRQ1 (1 << IRQ_PLA1_BIT)
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| 207 | #define IRQ_PLA_IRQ0 (1 << IRQ_PLA0_BIT)
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| 208 | #define IRQ_EXT_IRQ1 (1 << IRQ_EXT1_BIT)
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| 209 | #define IRQ_PSM (1 << IRQ_PSM_BIT)
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| 210 | #define IRQ_COMP (1 << IRQ_COMP_BIT)
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| 211 | #define IRQ_EXT_IRQ0 (1 << IRQ_EXT0_BIT)
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| 212 | #define IRQ_UART (1 << IRQ_UART_BIT)
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| 213 | #define IRQ_SPI_MST (1 << IRQ_SPIM_BIT)
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| 214 | #define IRQ_SPI_SLV (1 << IRQ_SPIS_BIT)
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| 215 | #define IRQ_I2C1_MST (1 << IRQ_I2C1M_BIT)
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| 216 | #define IRQ_I2C0_MST (1 << IRQ_I2C0M_BIT)
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| 217 | #define IRQ_I2C0_SLV (1 << IRQ_I2C0S_BIT)
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| 218 | #define IRQ_PLL_LOCK (1 << IRQ_PLLL_BIT)
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| 219 | #define IRQ_ADC_CH (1 << IRQ_ADCC_BIT)
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| 220 | #define IRQ_FLA_CTRL (1 << IRQ_FLAC_BIT)
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| 221 | #define IRQ_TIMER3 (1 << IRQ_TIM3_BIT)
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| 222 | #define IRQ_TIMER2 (1 << IRQ_TIM2_BIT)
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| 223 | #define IRQ_TIMER1 (1 << IRQ_TIM1_BIT)
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| 224 | #define IRQ_TIMER0 (1 << IRQ_TIM0_BIT)
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| 225 | #define IRQ_SWI (1 << IRQ_SWI_BIT)
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| 226 | #define ALL_INT (1 << ALL_INT_OR)
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| 227 |
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| 228 | #define MASK_IRQ_TIMER3 0xFFFFFF
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| 229 | #define MASK_IRQ_TIMER2 0xFFFFDF
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| 230 | #define MASK_IRQ_TIMER1 0xFFFFCF
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| 231 | #define MASK_IRQ_TIMER0 0xFFFFC7
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| 232 | #define MASK_IRQ_UART 0xFFFFC3
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| 233 | #define MASK_IRQ_SWI 0xFFBFC3
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| 234 |
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| 235 | #define MASK_IRQ_PWM_TRIP 0xFFBFC1
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| 236 | #define MASK_IRQ_EXT_IRQ3 0x7FBFC1
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| 237 | #define MASK_IRQ_EXT_IRQ2 0x3FBFC1
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| 238 | #define MASK_IRQ_PLA_IRQ1 0x1FBFC1
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| 239 | #define MASK_IRQ_PLA_IRQ0 0x0FBFC1
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| 240 | #define MASK_IRQ_EXT_IRQ1 0x07BFC1
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| 241 | #define MASK_IRQ_PSM 0x03BFC1
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| 242 | #define MASK_IRQ_COMP 0x01BFC1
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| 243 | #define MASK_IRQ_EXT_IRQ0 0x00BFC1
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| 244 | #define MASK_IRQ_SPI_MST 0x003FC1
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| 245 | #define MASK_IRQ_SPI_SLV 0x001FC1
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| 246 | #define MASK_IRQ_I2C1_MST 0x000FC1
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| 247 | #define MASK_IRQ_I2C0_MST 0x0007C1
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| 248 | #define MASK_IRQ_I2C0_SLV 0x0003C1
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| 249 | #define MASK_IRQ_PLL_LOCK 0x0001C1
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| 250 | #define MASK_IRQ_ADC_CH 0x0000C1
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| 251 | #define MASK_IRQ_FLA_CTRL 0x000041
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| 252 | #define MASK_ALL_INT 0x000001
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| 253 |
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| 254 | #define INT_DISABLE_ALL 0xFFFFFF
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| 255 |
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| 256 | /*
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| 257 | * Timer0
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| 258 | */
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| 259 | /* Timer0 Register address */
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| 260 | #define T0LD (TIMER_BASE | 0x00) /* Timer0 Load Register */
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| 261 | #define T0VAL (TIMER_BASE | 0x04) /* Timer0 Value Register */
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| 262 | #define T0CON (TIMER_BASE | 0x08) /* Timer0 Control Register */
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| 263 | #define T0CLRI (TIMER_BASE | 0x0C) /* Timer0 Clear Register */
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| 264 |
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| 265 | /* Timer0 Control Register bits */
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| 266 | #define T0CON_ENA 0x80 /* Timer0 enable */
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| 267 | #define T0CON_MOD 0x40 /* 1:periodic mode, 0:free-running mode */
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| 268 | #define T0CON_PSC_UDF 0x0C /* Prescale: undefined, equal 0x00 */
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| 269 | #define T0CON_PSC_256 0x08 /* Prescale: 1/256 */
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| 270 | #define T0CON_PSC_16 0x04 /* Prescale: 1/16 */
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| 271 | #define T0CON_PSC_1 0x00 /* Prescale: 1/1 */
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| 272 |
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| 273 | /* Timer0 count number */
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| 274 | #define TIM0_COUNT_MAX 0xFFFF /* 16 bit */
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| 275 | #define TIM0_COUNT 0x55FF /* 16 bit */
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| 276 |
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| 277 |
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| 278 |
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| 279 | /*
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| 280 | * Timer1
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| 281 | */
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| 282 | /* Timer1 Register address */
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| 283 | #define T1LD (TIMER_BASE | 0x20) /* Timer1 Load Register */
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| 284 | #define T1VAL (TIMER_BASE | 0x24) /* Timer1 Value Register */
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| 285 | #define T1CON (TIMER_BASE | 0x28) /* Timer1 Control Register */
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| 286 | #define T1CLRI (TIMER_BASE | 0x2C) /* Timer1 Clear Register */
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| 287 | #define T1CAP (TIMER_BASE | 0x30) /* Timer1 Capture Register */
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| 288 |
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| 289 | /* Timer1 Control Register bits */
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| 290 | #define T1CON_CAP 0x20000 /* capture */
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| 291 |
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| 292 | #define T1CON_CLS_P0_6 0x0600 /* Clock source from Port0 pin6 */
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| 293 | #define T1CON_CLS_P1_0 0x0400 /* Clock source from Port1 pin0 */
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| 294 | #define T1CON_CLS_OSCI 0x0200 /* Clock source from oscillator */
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| 295 | #define T1CON_CLS_CORE 0x0000 /* Clock source from core clock */
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| 296 |
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| 297 | #define T1CON_CUP 0x0100 /* 1:count up, 0:count down */
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| 298 | #define T1CON_ENA 0x0080 /* Timer1 enable */
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| 299 | #define T1CON_MOD 0x0040 /* 1:periodic mode, 0:free-running mode */
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| 300 |
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| 301 | #define T1CON_FMT_BIN 0x0000 /* Format: binary */
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| 302 | #define T1CON_FMT_23H 0x0020 /* Format: hr:min:sec:hundredths -23h to 0h */
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| 303 | #define T1CON_FMT_255H 0x0030 /* Format: hr:min:sec:hundredths -255h to 0h */
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| 304 |
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| 305 | #define T1CON_PSC_32768 0x000F /* Prescale: 1/32768 */
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| 306 | #define T1CON_PSC_256 0x0008 /* Prescale: 1/256 */
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| 307 | #define T1CON_PSC_16 0x0004 /* Prescale: 1/16 */
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| 308 | #define T1CON_PSC_1 0x0000 /* Prescale: 1/1 */
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| 309 |
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| 310 |
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| 311 | /* Timer1 count number */
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| 312 | //#define TIM1_CNT_1S 41780000 /* 1s (41.78MHz) */
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| 313 | //#define TIM1_CNT_1mS 41780 /* 1ms (41.78MHz) */
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| 314 | //#define TIM1_CNT_OSC 32768 /* 1s (32.768kHz) */
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| 315 |
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| 316 |
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| 317 |
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| 318 | /*
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| 319 | * UART
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| 320 | */
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| 321 | /* UART Registers */
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| 322 | #define COMTX (UART_BASE | 0x00) /* Transmit */
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| 323 | #define COMRX (UART_BASE | 0x00) /* Receive */
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| 324 | #define COMDIV0 (UART_BASE | 0x00) /* Low-byte divisor latch */
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| 325 | #define COMIEN0 (UART_BASE | 0x04) /* Interrupt Enable */
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| 326 | #define COMDIV1 (UART_BASE | 0x04) /* High-byte divisor latch */
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| 327 | #define COMIID0 (UART_BASE | 0x08) /* Interrupt identification */
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| 328 | #define COMCON0 (UART_BASE | 0x0C) /* Line control */
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| 329 | #define COMSTA0 (UART_BASE | 0x14) /* Line status */
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| 330 | #define COMSCR (UART_BASE | 0x1C) /* Scratch register */
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| 331 |
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| 332 |
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| 333 | /* COMIEN0 bits */
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| 334 | #define COMIEN0_EDSSI 0x08 /* Modem status interrupt-enable */
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| 335 | #define COMIEN0_ELSI 0x04 /* RX status interrupt-enable */
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| 336 | #define COMIEN0_ETBEI 0x02 /* Enable Transmit buffer empty interrupt */
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| 337 | #define COMIEN0_ERBFI 0x01 /* Enable Receive buffer full interrupt */
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| 338 |
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| 339 | /* COMIID0 bits */
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| 340 | #define COMIID0_NOINT 0x01 /* No Interrutp */
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| 341 | #define COMIID0_RXLINT 0x06 /* Recieve line status Interrupt */
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| 342 | #define COMIID0_RXFINT 0x06 /* Recieve buffer full Interrupt */
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| 343 | #define COMIID0_TXEINT 0x02 /* Transmit buffer empty Interrupt */
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| 344 | #define COMIID0_MODINT 0x00 /* Modem status Interrupt */
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| 345 |
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| 346 | /* COMCON0 bits */
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| 347 | #define COMCON0_DLAB 0x80 /* Set: Enable access COMDIV0 and COMDIV1 */
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| 348 | /* Clear: Enable access COMRX and COMTX */
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| 349 | #define COMCON0_BRK 0x40 /* Force SOUT to 0 */
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| 350 | #define COMCON0_SP 0x20 /* Stick Parity (?) */
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| 351 | #define COMCON0_EPS 0x10 /* Even Parity Select bit */
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| 352 | #define COMCON0_PEN 0x08 /* Parity Enable bit */
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| 353 | #define COMCON0_STOP 0x04 /* Stop bit */
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| 354 |
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| 355 | #define COMCON0_WLS_8b 0x03 /* Word length is 8 bits */
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| 356 | #define COMCON0_WLS_7b 0x02 /* Word length is 7 bits */
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| 357 | #define COMCON0_WLS_6b 0x01 /* Word length is 6 bits */
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| 358 | #define COMCON0_WLS_5b 0x00 /* Word length is 5 bits */
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| 359 |
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| 360 | /* COMSTA0 bits */
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| 361 | #define COMSTA0_TEMT 0x40 /* COMTX empty */
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| 362 | #define COMSTA0_THRE 0x20 /* COMTX and COMRX empty */
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| 363 | #define COMSTA0_BI 0x10 /* Break error */
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| 364 | #define COMSTA0_FE 0x08 /* Framing error */
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| 365 | #define COMSTA0_PE 0x04 /* parity error */
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| 366 | #define COMSTA0_OE 0x02 /* Overrun error */
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| 367 | #define COMSTA0_DR 0x01 /* Data ready (COMRX is full) */
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| 368 |
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| 369 | /* COMDIVx bits : Baud Rate = 9600 */
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| 370 | #define COMDIV0_BR9600 0x88 /* Low byte */
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| 371 | #define COMDIV1_BR9600 0x00 /* High byte */
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| 372 |
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| 373 | /*
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| 374 | * SRAM
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| 375 | */
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| 376 | #define VCT_TB_SRAM 0x10000
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| 377 | #define VCT_TB 0x00000
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| 378 |
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| 379 |
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| 380 | #ifndef _MACRO_ONLY
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| 381 |
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| 382 | /*
|
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| 383 | * å
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| 384 | èµUARTç¨ ç°¡æSIOãã©ã¤ã
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| 385 | */
|
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| 386 | /*
|
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| 387 | * ã«ã¼ãã«èµ·åæç¨ã®åæå(sys_putcã使ç¨ãããã)
|
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| 388 | */
|
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| 389 | extern void init_uart(void);
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| 390 |
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| 391 |
|
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| 392 | /*
|
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| 393 | * ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯
|
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| 394 | */
|
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| 395 | typedef struct sio_port_initialization_block
|
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| 396 | {
|
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| 397 | VP uart_data;
|
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| 398 | VP divisor_lo;
|
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| 399 | VP divisor_hi;
|
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| 400 | VP int_enable;
|
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| 401 | VP int_identifier;
|
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| 402 | VP line_control;
|
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| 403 | VP line_status;
|
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| 404 | VW irq_bit;
|
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| 405 | }
|
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| 406 | SIOPINIB;
|
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| 407 |
|
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| 408 | /*
|
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| 409 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®å®ç¾©
|
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| 410 | */
|
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| 411 | typedef struct sio_port_control_block
|
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| 412 | {
|
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| 413 | const SIOPINIB *siopinib; /* ã·ãªã¢ã«I/Oãã¼ãåæåããã㯠*/
|
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| 414 | VP_INT exinf; /* æ¡å¼µæ
|
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| 415 | å ± */
|
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| 416 | BOOL openflag; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
|
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| 417 | BOOL sendflag; /* éä¿¡å²è¾¼ã¿ã¤ãã¼ãã«ãã©ã° */
|
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| 418 | BOOL getready; /* æåãåä¿¡ããç¶æ
|
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| 419 | */
|
---|
| 420 | BOOL putready; /* æåãéä¿¡ã§ããç¶æ
|
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| 421 | */
|
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| 422 |
|
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| 423 | }SIOPCB;
|
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| 424 |
|
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| 425 |
|
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| 426 | /*
|
---|
| 427 | * ã³ã¼ã«ããã¯ã«ã¼ãã³ã®èå¥çªå·
|
---|
| 428 | */
|
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| 429 | #define SIO_ERDY_SND 1u /* éä¿¡å¯è½ã³ã¼ã«ãã㯠*/
|
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| 430 | #define SIO_ERDY_RCV 2u /* åä¿¡éç¥ã³ã¼ã«ãã㯠*/
|
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| 431 |
|
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| 432 | /*
|
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| 433 | * ãªã³ãããã®UARTããã®ãã¼ãªã³ã°åºå
|
---|
| 434 | */
|
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| 435 | extern void uart_putc(char c);
|
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| 436 |
|
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| 437 | /*
|
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| 438 | * SIOãã©ã¤ãã®åæåã«ã¼ãã³
|
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| 439 | */
|
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| 440 | extern void uart_initialize(void);
|
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| 441 |
|
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| 442 | /*
|
---|
| 443 | * ãªã¼ãã³ãã¦ãããã¼ãããããï¼
|
---|
| 444 | */
|
---|
| 445 | extern BOOL uart_openflag(void);
|
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| 446 |
|
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| 447 | /*
|
---|
| 448 | * ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
|
---|
| 449 | */
|
---|
| 450 | extern SIOPCB *uart_opn_por(ID siopid, VP_INT exinf);
|
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| 451 |
|
---|
| 452 | /*
|
---|
| 453 | * ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
|
---|
| 454 | */
|
---|
| 455 | extern void uart_cls_por(SIOPCB *siopcb);
|
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| 456 |
|
---|
| 457 | /*
|
---|
| 458 | * ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
|
---|
| 459 | */
|
---|
| 460 | extern BOOL uart_snd_chr(SIOPCB *siopcb, char c);
|
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| 461 |
|
---|
| 462 | /*
|
---|
| 463 | * ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
|
---|
| 464 | */
|
---|
| 465 | extern INT uart_rcv_chr(SIOPCB *siopcb);
|
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| 466 |
|
---|
| 467 | /*
|
---|
| 468 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
|
---|
| 469 | */
|
---|
| 470 | extern void uart_ena_cbr(SIOPCB *siopcb, UINT cbrtn);
|
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| 471 |
|
---|
| 472 | /*
|
---|
| 473 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
|
---|
| 474 | */
|
---|
| 475 | extern void uart_dis_cbr(SIOPCB *siopcb, UINT cbrtn);
|
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| 476 |
|
---|
| 477 | /*
|
---|
| 478 | * SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
|
---|
| 479 | */
|
---|
| 480 | extern void uart_in_isr(void);
|
---|
| 481 | extern void uart_out_isr(void);
|
---|
| 482 |
|
---|
| 483 | /*
|
---|
| 484 | * ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
|
---|
| 485 | */
|
---|
| 486 | extern void uart_ierdy_snd(VP_INT exinf);
|
---|
| 487 |
|
---|
| 488 | /*
|
---|
| 489 | * ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
|
---|
| 490 | */
|
---|
| 491 | extern void uart_ierdy_rcv(VP_INT exinf);
|
---|
| 492 |
|
---|
| 493 |
|
---|
| 494 |
|
---|
| 495 | #endif /* _MACRO_ONLY */
|
---|
| 496 | #endif /* _FRK_ADUC_H_ */
|
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