[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 11 | * ã«ãã£ã¦å
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| 12 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 13 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 14 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 15 | å¸ï¼ä»¥ä¸ï¼
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| 16 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 17 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 18 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 19 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 20 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 21 | * ç¨ã§ããå½¢ã§åé
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| 22 | å¸ããå ´åã«ã¯ï¼åé
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| 23 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 24 | * è
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| 25 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 26 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 27 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 28 | * ç¨ã§ããªãå½¢ã§åé
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| 29 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 30 | * ã¨ï¼
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| 31 | * (a) åé
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| 32 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 33 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 34 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 35 | * (b) åé
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| 36 | å¸ã®å½¢æ
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| 37 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 38 | * å ±åãããã¨ï¼
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| 39 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 40 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 41 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 42 | 責ãããã¨ï¼
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| 43 | *
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| 44 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 45 | ã
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| 46 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 47 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 48 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 49 | *
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| 50 | * @(#) $Id: cpu_config.h,v 1.19 2004/09/17 13:45:55 honda Exp $
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| 51 | */
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| 52 |
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| 53 | /*
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| 54 | * ããã»ããµä¾åã¢ã¸ã¥ã¼ã«ï¼ARM4vTç¨ï¼
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| 55 | *
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| 56 | * ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼t_config.h ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼
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| 57 | * ä»ã®ãã¡ã¤ã«ããç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
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| 58 | */
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| 59 |
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| 60 | #ifndef _CPU_CONFIG_H_
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| 61 | #define _CPU_CONFIG_H_
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| 62 |
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| 63 | /*
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| 64 | * ã«ã¼ãã«å
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| 65 | é¨èå¥åã®ãªãã¼ã
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| 66 | */
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| 67 | #include "cpu_rename.h"
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| 68 |
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| 69 | /*
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| 70 | * ããã»ããµã®ç¹æ®å½ä»¤ã®ã¤ã³ã©ã¤ã³é¢æ°å®ç¾©
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| 71 | */
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| 72 | #ifndef _MACRO_ONLY
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| 73 | #include <cpu_insn.h>
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| 74 | #endif /* _MACRO_ONLY */
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| 75 |
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| 76 | /*
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| 77 | * TCB é¢é£ã®å®ç¾©
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| 78 | *
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| 79 | * cpu_context.h ã«å
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| 80 | ¥ããæ¹ãã¨ã¬ã¬ã³ãã ãï¼åç
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| 81 | §ã®ä¾åæ§ã®é¢ä¿ã§ï¼
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| 82 | * cpu_context.h ã«ã¯å
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| 83 | ¥ããããªãï¼
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| 84 | */
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| 85 |
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| 86 | /*
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| 87 | * TCB ä¸ã®ãã£ã¼ã«ãã®ãããå¹
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| 88 | ã®å®ç¾©
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| 89 | */
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| 90 | #define TBIT_TCB_TSTAT 8 /* tstat ãã£ã¼ã«ãã®ãããå¹
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| 91 | */
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| 92 | #define TBIT_TCB_PRIORITY 8 /* priority ãã£ã¼ã«ãã®ãããå¹
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| 93 | */
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| 94 |
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| 95 | #ifndef _MACRO_ONLY
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| 96 | /*
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| 97 | * ã¿ã¹ã¯ã³ã³ããã¹ããããã¯ã®å®ç¾©
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| 98 | */
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| 99 | typedef struct task_context_block {
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| 100 | VP sp; /* ã¹ã¿ãã¯ãã¤ã³ã¿ */
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| 101 | FP pc; /* ããã°ã©ã ã«ã¦ã³ã¿ */
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| 102 | } CTXB;
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| 103 |
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| 104 | /*
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| 105 | * å²ãè¾¼ã¿ã®ãã¹ãåæ°ã®ã«ã¦ã³ã
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| 106 | */
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| 107 | extern UW interrupt_count;
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| 108 |
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| 109 |
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| 110 | /*
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| 111 | * ã·ã¹ãã ç¶æ
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| 112 | åç
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| 113 | §
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| 114 | */
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| 115 | Inline UB
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| 116 | current_mode()
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| 117 | {
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| 118 | return(current_sr() & CPSR_MODE_MASK);
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| 119 | }
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| 120 |
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| 121 | Inline BOOL
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| 122 | sense_context()
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| 123 | {
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| 124 | return(interrupt_count > 0);
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| 125 | }
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| 126 |
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| 127 | Inline BOOL
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| 128 | sense_lock()
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| 129 | {
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| 130 | return(current_sr() & CPSR_IRQ_BIT);
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| 131 | }
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| 132 |
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| 133 | #define t_sense_lock sense_lock
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| 134 | #define i_sense_lock sense_lock
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| 135 |
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| 136 |
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| 137 | /*
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| 138 | * CPUããã¯ã¨ãã®è§£é¤
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| 139 | *
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| 140 | */
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| 141 |
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| 142 | #define t_lock_cpu lock_cpu
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| 143 | #define i_lock_cpu lock_cpu
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| 144 | #define t_unlock_cpu unlock_cpu
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| 145 | #define i_unlock_cpu unlock_cpu
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| 146 |
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| 147 |
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| 148 | Inline void
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| 149 | lock_cpu()
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| 150 | {
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| 151 | disint();
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| 152 | }
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| 153 |
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| 154 | Inline void
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| 155 | unlock_cpu()
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| 156 | {
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| 157 | enaint();
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| 158 | }
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| 159 |
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| 160 |
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| 161 | /*
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| 162 | * ã¿ã¹ã¯ãã£ã¹ãããã£
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| 163 | */
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| 164 |
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| 165 | /*
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| 166 | * æé«åªå
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| 167 | é ä½ã¿ã¹ã¯ã¸ã®ãã£ã¹ãããï¼cpu_support.Sï¼
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| 168 | *
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| 169 | * dispatch ã¯ï¼ã¿ã¹ã¯ã³ã³ããã¹ãããå¼ã³åºããããµã¼ãã¹ã³ã¼ã«å¦ç
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| 170 | * å
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| 171 | ã§ï¼CPUããã¯ç¶æ
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| 172 | ã§å¼ã³åºããªããã°ãªããªãï¼
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| 173 | */
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| 174 | extern void dispatch(void);
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| 175 |
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| 176 |
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| 177 | /*
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| 178 | * ç¾å¨ã®ã³ã³ããã¹ããæ¨ã¦ã¦ãã£ã¹ãããï¼cpu_support.Sï¼
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| 179 | *
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| 180 | * exit_and_dispatch ã¯ï¼CPUããã¯ç¶æ
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| 181 | ã§å¼ã³åºããªããã°ãªããªãï¼
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| 182 | */
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| 183 | extern void exit_and_dispatch(void);
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| 184 |
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| 185 |
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| 186 | /*
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| 187 | * ä¾å¤ãã¯ã¿ã«æ¸ãè¾¼ã¾ããã¸ã£ã³ãå½ä»¤ãåç
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| 188 | §ããã¢ãã¬ã¹
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| 189 | */
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| 190 | extern UW * arm_vector_add[8];
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| 191 |
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| 192 |
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| 193 | /*
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| 194 | * ä¾å¤ã«å¿ãããã³ãã©ã®èµ·åçªå°
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| 195 | */
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| 196 | extern UW arm_handler_add[8];
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| 197 |
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| 198 |
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| 199 | /*
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| 200 | * CPUä¾å¤ãã³ãã©ã®è¨å®
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| 201 | */
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| 202 | extern void define_exc(EXCNO excno, FP exchdr);
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| 203 |
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| 204 |
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| 205 | Inline void
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| 206 | arm_install_handler(EXCNO excno, FP exchdr)
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| 207 | {
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| 208 | *arm_vector_add[excno] = (UW)exchdr;
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| 209 | }
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| 210 |
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| 211 |
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| 212 | /*
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| 213 | * CPUä¾å¤ãã³ãã©ã®åºå
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| 214 | ¥å£å¦ç
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| 215 | */
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| 216 |
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| 217 |
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| 218 | /*
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| 219 | * CPUä¾å¤ãã³ãã©ã®åºå
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| 220 | ¥å£å¦çã®çæãã¯ã
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| 221 | *
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| 222 | */
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| 223 | #define __EXCHDR_ENTRY(exchdr, stacktop) \
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| 224 | extern void exchdr##_entry(VP sp); \
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| 225 | asm(".text \n" \
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| 226 | #exchdr "_entry: \n" \
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| 227 | " ldr sp,.int_stack_"#exchdr" \n" /* ã¹ã¿ãã¯ã®åãæ¿ã */\
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| 228 | " sub lr,lr,#4 \n" /* undefã§ãããã§ããã? */\
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| 229 | " stmfd sp!, {r0 - r2,lr} \n" /* ä¸æçã«int_stackã«å¾
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| 230 | é¿ */ \
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| 231 | " mrs r1, spsr \n" /* SVCã¢ã¼ãã«åãæ¿ãããã */ \
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| 232 | " mov r0, sp \n" /* ä¿åãã */ \
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| 233 | " mov r2,#0xd3 \n" /* CPSRã®æ¸ãæã(SVCã¢ã¼ãã¸)*/ \
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| 234 | " msr cpsr,r2 \n" \
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| 235 | " ldr r2,[r0,#0x0C] \n" /* load PC */\
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| 236 | " stmfd sp!,{r2} \n" /* Store PC */\
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| 237 | " stmfd sp!,{r3,ip,lr} \n" /* Store r3,ip,lr */\
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| 238 | " ldmfd r0!,{r2,ip,lr} \n" /* load r0,r1,r2 */\
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| 239 | " stmfd sp!,{r1,r2,ip,lr} \n" /* SPSR,Store r0,r1,r2 */\
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| 240 | " ldr r2, .interrupt_count_"#exchdr"\n" /* å¤éå²ãè¾¼ã¿ãå¤å® */\
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| 241 | " ldr r3, [r2] \n" \
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| 242 | " add r0,r3,#1 \n" \
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| 243 | " str r0, [r2] \n" \
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| 244 | " mov r0,sp \n" /* ä¾å¤ãã³ãã©ã¸ã®å¼æ° */\
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| 245 | " cmp r3, #0x00 \n" \
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| 246 | " ldreq sp,stack_"#exchdr" \n" /* ã¹ã¿ãã¯ã®å¤æ´ */\
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| 247 | " stmeqfd sp!,{r0} \n" /* ã¿ã¹ã¯ã¹ã¿ãã¯ã®ä¿å */\
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| 248 | " and r2, r1, #0xc0 \n" /* ä¾å¤çºçæã®CPUããã¯ç¶æ
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| 249 | (IRQ) */\
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| 250 | " orr r2, r2, #0x13 \n" /* ã¨FIQãç¶æ¿. SVCã¢ã¼ã */\
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| 251 | " msr cpsr,r2 \n" \
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| 252 | " bl "#exchdr" \n" /* ãã³ãã©å¼ã³åºã */\
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| 253 | " mrs r2, cpsr \n" /* FIQãç¶æ¿ */\
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| 254 | " and r2, r2, #0x40 \n" /* */\
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| 255 | " orr r2, r2, #0x93 \n" /* å²ãè¾¼ã¿ç¦æ¢ */\
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| 256 | " msr cpsr,r2 \n" \
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| 257 | " ldr r2,.interrupt_count_"#exchdr" \n"/* å²ãè¾¼ã¿åæ°ã */\
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| 258 | " ldr r1, [r2] \n" /* ãã¯ãªã¡ã³ã */\
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| 259 | " sub r3,r1,#1 \n"\
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| 260 | " str r3, [r2] \n"\
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| 261 | " cmp r3,#0x00 \n" /* å²ãè¾¼ã¿ãã¹ãæ°? */\
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| 262 | " bne return_to_task_"#exchdr" \n" \
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| 263 | " ldmfd sp!,{r0} \n" /* ã¿ã¹ã¯ã¹ã¿ãã¯ã®å¾©å¸° */\
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| 264 | " mov sp, r0 \n"\
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| 265 | " ldr r1, reqflg_"#exchdr" \n" /* Check reqflg */\
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| 266 | " ldr r0,[r1] \n"\
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| 267 | " cmp r0,#0 \n"\
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| 268 | " beq return_to_task_"#exchdr" \n"\
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| 269 | " mov r0,#0 \n"\
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| 270 | " str r0,[r1] \n" /* Clear reqflg */\
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| 271 | " b _kernel_ret_exc \n" /* ret_int㸠*/\
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| 272 | "return_to_task_"#exchdr": \n" \
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| 273 | " ldmfd sp!,{r1} \n" /* CPSRã®å¾©å¸°å¦ç r1 <- cpsr*/\
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| 274 | " mrs r2, cpsr \n" /* FIQãç¶æ¿ */\
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| 275 | " and r2, r2, #0x40 \n" /* */\
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| 276 | " and r1, r1, #~0x40 \n" /* */\
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| 277 | " orr r1, r1, r2 \n" /* */\
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| 278 | " msr spsr, r1 \n" /* å²ãè¾¼ã¿è¨±å¯ */\
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| 279 | " ldmfd sp!,{r0-r3,ip,lr,pc}^ \n"\
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| 280 | " .align 4 \n"\
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| 281 | ".int_stack_"#exchdr": \n"\
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| 282 | " .long _kernel_int_stack + 6 * 4 \n"\
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| 283 | "reqflg_"#exchdr": \n"\
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| 284 | " .long _kernel_reqflg \n"\
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| 285 | "stack_"#exchdr": \n"\
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| 286 | " .long " #stacktop " \n"\
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| 287 | ".interrupt_count_"#exchdr": \n"\
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| 288 | " .long _kernel_interrupt_count \n")
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| 289 |
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| 290 |
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| 291 | #define _EXCHDR_ENTRY(exchdr, stacktop) __EXCHDR_ENTRY(exchdr, stacktop)
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| 292 |
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| 293 | #define EXCHDR_ENTRY(exchdr) _EXCHDR_ENTRY(exchdr, STACKTOP)
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| 294 |
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| 295 | #define EXC_ENTRY(exchdr) exchdr##_entry
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| 296 |
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| 297 |
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| 298 | /*
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| 299 | * CPUä¾å¤ã®çºçããæã®ã·ã¹ãã ç¶æ
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| 300 | ã®åç
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| 301 | §
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| 302 | */
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| 303 |
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| 304 | /*
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| 305 | * CPUä¾å¤ã®çºçããæã®ãã£ã¹ããã
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| 306 | */
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| 307 | Inline BOOL
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| 308 | exc_sense_context(VP p_excinf)
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| 309 | {
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| 310 | return(interrupt_count > 1);
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| 311 | }
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| 312 |
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| 313 |
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| 314 | /*
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| 315 | * CPUä¾å¤ã®çºçããæã®CPUããã¯ç¶æ
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| 316 | ã®åç
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| 317 | §
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| 318 | */
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| 319 | Inline BOOL
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| 320 | exc_sense_lock(VP p_excinf)
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| 321 | {
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| 322 | return((*((UW *)p_excinf) & CPSR_IRQ_BIT) == CPSR_IRQ_BIT );
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| 323 | }
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| 324 |
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| 325 |
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| 326 | /*
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| 327 | * æªå®ç¾©ã®ä¾å¤ãå
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| 328 | ¥ã£ãå ´å
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| 329 | */
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| 330 | extern void undef_exception();
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| 331 | extern void swi_exception();
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| 332 | extern void prefetch_exception();
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| 333 | extern void data_abort_exception();
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| 334 | extern void irq_abort_exception();
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| 335 | extern void fiq_abort_exception();
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| 336 |
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| 337 |
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| 338 | /*
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| 339 | * ããã»ããµä¾åã®åæå
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| 340 | */
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| 341 | extern void cpu_initialize(void);
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| 342 |
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| 343 |
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| 344 | /*
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| 345 | * ããã»ããµä¾åã®çµäºæå¦ç
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| 346 | */
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| 347 | extern void cpu_terminate(void);
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| 348 |
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| 349 |
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| 350 | /*
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| 351 | * CPU/å²è¾¼ã¿ãã³ãã©ã®åºå
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| 352 | ¥ãå£å¦çã§ä¸æçã«ä½¿ç¨ããã¹ã¿ãã¯
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| 353 | */
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| 354 | #define INT_STACK_SIZE 6
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| 355 | extern UW int_stack[INT_STACK_SIZE];
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| 356 |
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| 357 |
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| 358 | #endif /* _MACRO_ONLY */
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| 359 | #endif /* _CPU_CONFIG_H_ */
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