[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | *
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| 9 | * Copyright (C) 2005-2007 by Y.D.K.Co.,LTD Technologies company
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | * @(#) $Id: sys_support.S,v 1.2 2007/05/21 01:33:50 honda Exp $
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| 53 | */
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| 54 |
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| 55 | #define _MACRO_ONLY
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| 56 | #include "jsp_kernel.h"
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| 57 | #include <ns9360.h>
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| 58 |
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| 59 | /* ããã»ããµã¢ã¼ã */
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| 60 | Mode_SVC = 0x13
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| 61 |
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| 62 | /* ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿å²ãè¾¼ã¿bit */
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| 63 | I_Bit = 0x80
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| 64 | F_Bit = 0x40
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| 65 |
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| 66 | /* BBUS reset register */
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| 67 | BBUS_RESET_BASE = 0x90600000
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| 68 |
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| 69 |
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| 70 | /*
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| 71 | * ä½ã¬ãã«ã®ã¿ã¼ã²ããã·ã¹ãã ä¾åã®åæå
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| 72 | *
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| 73 | * ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã®ä¸ã§ï¼ã¡ã¢ãªåæåã®åã«å¼ã³åºãããï¼
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| 74 | */
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| 75 |
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| 76 | .text
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| 77 | .align 2
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| 78 | .global hardware_init_hook
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| 79 | hardware_init_hook:
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| 80 |
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| 81 | /*
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| 82 | * NS9360ä¾åã®åæå
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| 83 | */
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| 84 | /*
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| 85 | * bbus_reset
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| 86 | */
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| 87 | mov r0, #0x0
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| 88 | ldr r0, =BBUS_RESET_BASE
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| 89 | mov r1, #0x0
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| 90 | str r1, [r0, #0]
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| 91 |
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| 92 | /*
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| 93 | * CSãGPIO Initial
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| 94 | */
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| 95 | stmfd sp!, {r4 - r11,lr} /* ã¬ã¸ã¹ã¿ã®ä¿å */
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| 96 | bl cpu_CsGpioInit
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| 97 | ldmfd sp!,{r4 - r11,lr}
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| 98 |
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| 99 | /*----*/
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| 100 | init_done:
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| 101 | mov pc, lr
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| 102 |
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| 103 |
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| 104 | /*
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| 105 | *
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| 106 | * å²è¾¼ã¿ã®åºå
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| 107 | ¥ãå£å¦ç
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| 108 | *
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| 109 | */
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| 110 | .text
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| 111 | .align 4
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| 112 | .global IRQ_Handler
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| 113 | IRQ_Handler:
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| 114 |
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| 115 | /*
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| 116 | * å²è¾¼ã¿ã¢ã¼ã
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| 117 | *
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| 118 | * cpsrãspsr_irqã«å¾©å¸°å
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| 119 | ãr14_irq(lp)ã«å
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| 120 | ¥ãï¼
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| 121 | * spsr_irqã¨r14_irqã¨r13(sp)_irqã r14,r13ã¨ãªãï¼
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| 122 | */
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| 123 |
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| 124 | /*
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| 125 | * ã¿ã¹ã¯ã®åä½æã¢ã¼ã(ã¹ã¼ãã¼ãã¤ã¶ã¼ã¢ã¼ã)ã¸
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| 126 | */
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| 127 | mov sp,#(CPSR_SVC | CPSR_FIQ_BIT | CPSR_IRQ_BIT)
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| 128 | msr cpsr_all, sp
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| 129 | stmfd sp!, {r0-r3,ip,lr,pc} /* pcã¯ããã¼ */
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| 130 |
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| 131 |
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| 132 | /*
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| 133 | * spsrã¨æ»ãçªå°ãåå¾ããããã«IRQã¢ã¼ãã¸
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| 134 | */
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| 135 | mov r0,#(CPSR_IRQ | CPSR_FIQ_BIT | CPSR_IRQ_BIT)
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| 136 | msr cpsr,r0
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| 137 | sub r0,lr,#4
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| 138 | mrs r1,spsr
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| 139 |
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| 140 |
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| 141 | /*
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| 142 | * ã¹ã¼ãã¼ãã¤ã¶ã¼ã¢ã¼ãã«
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| 143 | */
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| 144 | and r2, r1, #CPSR_FIQ_BIT /* FIQãããã®ç¶æ¿ */
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| 145 | orr r2, r2, #(CPSR_SVC|CPSR_IRQ_BIT)
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| 146 | msr cpsr, r2
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| 147 | str r0, [sp,#0x18] /* Store pc */
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| 148 | stmfd sp!,{r1} /* spsr */
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| 149 |
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| 150 |
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| 151 | /*
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| 152 | * å¤éå²ãè¾¼ã¿ãå¤å®
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| 153 | */
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| 154 | ldr r2, =interrupt_count
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| 155 | ldr r3, [r2]
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| 156 | add r0,r3,#1
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| 157 | str r0, [r2]
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| 158 | cmp r3, #0x00
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| 159 |
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| 160 | moveq r2,sp /* ãã¹ãå²ãè¾¼ã¿ã§ãªãå ´å */
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| 161 | ldreq sp,=STACKTOP /* ã¹ã¿ãã¯ã®å¤æ´ */
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| 162 | stmeqfd sp!,{r2} /* ã¿ã¹ã¯ã¹ã¿ãã¯ã®ä¿å */
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| 163 |
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| 164 | /*
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| 165 | * å²ãè¾¼ã¿è¦å ã®å¤å®ï¼
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| 166 | * INT_IDã®èªã¿è¾¼ã¿ï¼(ããã«ããå¿
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| 167 | è¦ã¯ãªãï¼)
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| 168 | */
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| 169 |
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| 170 | ldr r3, =ISRADDR_REG
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| 171 | ldr r0, [r3] /* å²ãè¾¼ã¿ãã¯ã¿ã®èªã¿åºã */
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| 172 |
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| 173 | /*
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| 174 | * æªå®ç¾©ã®å²è¾¼ã¿ããã§ãã¯
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| 175 | */
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| 176 | cmp r0, #0x00
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| 177 | beq undefined_interrupt
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| 178 |
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| 179 | /*
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| 180 | * å²ãè¾¼ã¿è¨±å¯
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| 181 | */
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| 182 | mrs r2, cpsr
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| 183 | and r2, r2, #~CPSR_IRQ_BIT /* å²è¾¼ã¿è¨±å¯ */
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| 184 | msr cpsr,r2
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| 185 |
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| 186 | /*
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| 187 | * Call Handler
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| 188 | */
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| 189 | mov lr, pc
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| 190 | mov pc, r0
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| 191 |
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| 192 | /*
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| 193 | * å²ãè¾¼ã¿ç¦æ¢
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| 194 | */
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| 195 | mrs r2, cpsr
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| 196 | and r2, r2, #CPSR_FIQ_BIT /* FIQãããã®ç¶æ¿ */
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| 197 | orr r2, r2, #(CPSR_SVC|CPSR_IRQ_BIT)
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| 198 | msr cpsr,r2
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| 199 |
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| 200 | /*
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| 201 | * å²è¾¼ã¿ãã¹ãåæ°(interrupt_count) ãã¯ãªã¡ã³ã
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| 202 | */
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| 203 | ldr r2, =interrupt_count
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| 204 | ldr r1, [r2]
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| 205 | sub r3, r1, #1
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| 206 | str r3, [r2]
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| 207 | cmp r3, #0x00
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| 208 | bne return_to_task_irq
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| 209 |
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| 210 | /*
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| 211 | * å²è¾¼ã¿ãã¹ããç¡ãã®ã§ãå
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| 212 | ¨ã¦ã®ãã¹ã¯ãã¯ãªã¢
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| 213 | */
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| 214 | ldr r2, =ISRADDR_REG
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| 215 | str r0, [r2] /* å²è¾¼ã¿ãã¹ã¯ã¯ãªã¢ */
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| 216 | /*
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| 217 | * ã¿ã¹ã¯ã¹ã¿ãã¯ã®å¾©å¸°
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| 218 | */
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| 219 | ldmfd sp!,{r0}
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| 220 | mov sp, r0
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| 221 |
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| 222 | ldr r1, =reqflg /* Check reqflg */
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| 223 | ldr r0, [r1]
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| 224 | cmp r0, #0
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| 225 | beq return_to_task_irq
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| 226 | mov r0, #0
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| 227 | str r0, [r1] /* Clear reqflg */
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| 228 | b ret_int
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| 229 |
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| 230 | return_to_task_irq:
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| 231 | /*
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| 232 | * 復帰å¦ç
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| 233 | * å²ãè¾¼ã¿è¨±å¯ã¨ãªããã¿ã¹ã¯ã³ã³ããã¹ãä¸ã«ä¿åãã¦ããããï¼
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| 234 | * åé¡ã¯ãªã
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| 235 | */
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| 236 | ldmfd sp!,{r1} /* CPSRã®å¾©å¸°å¦ç */
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| 237 | mrs r2, cpsr /* FIQãç¶æ¿ */
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| 238 | and r2, r2, #CPSR_FIQ_BIT
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| 239 | and r1, r1, #~CPSR_FIQ_BIT
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| 240 | orr r1, r1, r2
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| 241 | msr spsr, r1
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| 242 | ldmfd sp!,{r0-r3,ip,lr,pc}^ /*ã¿ã¹ã¯å¾©å¸° + å²è¾¼ã¿è¨±å¯ */
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| 243 |
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| 244 | /*
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| 245 | * æªå®ç¾©ã®å²è¾¼ã¿ãå
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| 246 | ¥ã£ãã¨ãã«å¼ã³åºã
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| 247 | */
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| 248 | undefined_interrupt:
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| 249 | b undef_interrupt
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| 250 |
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| 251 |
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| 252 | /*
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| 253 | * ãã£ãã·ã¥å¶å¾¡é¢ä¿
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| 254 | * UW cpuEnableICache( void );
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| 255 | * UW cpuEnableDCache( void );
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| 256 | * UW cpuEnableMMU( UW tlbaddr );
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| 257 | * UW cpuDCache_Line_Invalid( UW mva );
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| 258 | * UW cpuDCache_Line_Flush( UW mva );
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| 259 | * UW cpuDCache_Line_FlushInalid( UW mva );
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| 260 | * UW cpuDCache_DrainWriteBuffer( void );
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| 261 | */
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| 262 |
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| 263 |
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| 264 | .global cpuEnableICache, cpuEnableDCache
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| 265 | .global cpuEnableMMU
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| 266 | .global cpuDCache_Line_Invalid, cpuDCache_Line_Flush
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| 267 | .global cpuDCache_Line_FlushInvalid, cpuDCache_DrainWriteBuffer
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| 268 |
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| 269 |
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| 270 | #define CP15_ICACHE 0x1000
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| 271 | #define CP15_DCACHE 0x0004
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| 272 | #define CP15_MMU 0x0001
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| 273 |
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| 274 |
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| 275 | /*
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| 276 | * CP15-R1ã®I-cache bit(b12)=1 ã«ããã
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| 277 | * å¼æ°ãªã
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| 278 | */
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| 279 | cpuEnableICache:
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| 280 | mcr p15, 0, r0, c7, c5, 0 /* ICache invalidate */
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| 281 | nop
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| 282 | nop
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| 283 | nop
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| 284 | nop
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| 285 | nop
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| 286 | nop
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| 287 | nop
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| 288 | nop
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| 289 | mrc p15, 0, r0, c1, c0, 0 /* CP15 R1 */
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| 290 | orr r0, r0, #CP15_ICACHE /* I-Cache enable */
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| 291 | mcr p15, 0, r0, c1, c0, 0 /* Set CP15 R1 I-cache */
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| 292 | mov pc, lr
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| 293 |
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| 294 |
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| 295 | /*
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| 296 | * CP15-R7ã§Dcache invalidate å®æ½å¾ã«CP15-R1ã®D-cache bit(b2)=1ã«ããã
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| 297 | * å¼æ°ãªãã
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| 298 | */
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| 299 | cpuEnableDCache:
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| 300 | mcr p15, 0, r0, c7, c6, 0 /* DC all invalidate */
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| 301 | mrc p15, 0, r0, c1, c0, 0 /* CP15 R1 */
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| 302 | orr r0, r0, #CP15_DCACHE /* D-Cache enable */
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| 303 | mcr p15, 0, r0, c1, c0, 0 /* Set CP15 R1 D-cache */
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| 304 | mov pc,lr
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| 305 |
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| 306 |
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| 307 | /*
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| 308 | * CP15-R1ã®MMU bit(bit0)=1ã«ãããTLBè¨å®å¾ã«TBLã¢ãã¬ã¹ãå¼æ°ã«ã³ã¼ã«ããã
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| 309 | * r0:TLB address
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| 310 | */
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| 311 | cpuEnableMMU:
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| 312 | mcr p15, 0, r0, c2, c0, 0 /* Set CP15 R2 TLB pointer */
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| 313 | mov r0, #0 /* */
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| 314 | mvn r0, r0 /* all domain is manager */
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| 315 | mcr p15, 0, r0, c3, c0, 0 /* set Domain access (CP15 R3) */
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| 316 |
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| 317 | mrc p15, 0, r0, c1, c0, 0 /* CP15 R1 */
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| 318 | orr r0, r0, #CP15_MMU /* MMU enable */
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| 319 | mcr p15, 0, r0, c1, c0, 0 /* Set CP15 R1 MMU enable */
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| 320 | mov pc,lr
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| 321 |
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| 322 |
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| 323 | /*
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| 324 | * CP15-R7ã®Invalidate DCache single entry(MVA)ãå®è¡ããã
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| 325 | * r0:MVA
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| 326 | */
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| 327 | cpuDCache_Line_Invalid:
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| 328 | mcr p15, 0, r0, c7, c6, 1 /* DC invalidate single entry(MVA) */
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| 329 | mov pc,lr
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| 330 |
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| 331 |
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| 332 | /*
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| 333 | * CP15-R7ã®Clean DCache single entry(MVA)ãå®è¡ããã
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| 334 | * r0:MVA
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| 335 | */
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| 336 | cpuDCache_Line_Flush:
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| 337 | mcr p15, 0, r0, c7, c10, 1 /* DC clean single entry(MVA) */
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| 338 | mov pc,lr
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| 339 |
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| 340 |
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| 341 | /*
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| 342 | * CP15-R7ã®Clean & Invalidate DCache single entry(MVA)ãå®è¡ããã
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| 343 | * r0:MVA
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| 344 | */
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| 345 | cpuDCache_Line_FlushInvalid:
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| 346 | mcr p15, 0, r0, c7, c14, 1 /* DC clean single entry(MVA) */
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| 347 | mov pc,lr
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| 348 |
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| 349 |
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| 350 | /*
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| 351 | * CP15-R7ã®Drain write bufferãå®è¡ããã
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| 352 | */
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| 353 | cpuDCache_DrainWriteBuffer:
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| 354 | mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
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| 355 | mov pc,lr
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| 356 |
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