1 | /* mbed Microcontroller Library
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2 | * Copyright (c) 2006-2013 ARM Limited
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 | #include <string.h>
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17 | #include "ethernet_api.h"
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18 | #include "cmsis.h"
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19 | #include "mbed_interface.h"
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20 | #include "toolchain.h"
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21 | #include "mbed_error.h"
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22 | #include "ether_iodefine.h"
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23 | #include "ethernetext_api.h"
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24 |
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25 | /* Descriptor info */
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26 | #define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
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27 | #define MAX_SEND_SIZE (1514)
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28 | /* Ethernet Descriptor Value Define */
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29 | #define TD0_TFP_TOP_BOTTOM (0x30000000)
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30 | #define TD0_TACT (0x80000000)
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31 | #define TD0_TDLE (0x40000000)
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32 | #define RD0_RACT (0x80000000)
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33 | #define RD0_RDLE (0x40000000)
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34 | #define RD0_RFE (0x08000000)
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35 | #define RD0_RCSE (0x04000000)
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36 | #define RD0_RFS (0x03FF0000)
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37 | #define RD0_RCS (0x0000FFFF)
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38 | #define RD0_RFS_RFOF (0x02000000)
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39 | #define RD0_RFS_RUAF (0x00400000)
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40 | #define RD0_RFS_RRF (0x00100000)
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41 | #define RD0_RFS_RTLF (0x00080000)
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42 | #define RD0_RFS_RTSF (0x00040000)
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43 | #define RD0_RFS_PRE (0x00020000)
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44 | #define RD0_RFS_CERF (0x00010000)
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45 | #define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
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46 | RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
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47 | #define RD1_RDL_MSK (0x0000FFFF)
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48 | /* PHY Register */
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49 | #define BASIC_MODE_CONTROL_REG (0)
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50 | #define BASIC_MODE_STATUS_REG (1)
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51 | #define PHY_IDENTIFIER1_REG (2)
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52 | #define PHY_IDENTIFIER2_REG (3)
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53 | #define PHY_SP_CTL_STS_REG (31)
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54 | /* MII management interface access */
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55 | #define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
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56 | #define PHY_ST (1)
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57 | #define PHY_WRITE (1)
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58 | #define PHY_READ (2)
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59 | #define MDC_WAIT (6) /* 400ns/4 */
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60 | #define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
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61 | #define BASIC_STS_MSK_AUTO_CMP (0x0010) /* Auto-Negotiate Complete */
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62 | #define M_PHY_ID (0xFFFFFFF0)
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63 | #define PHY_ID_LAN8710A (0x0007C0F0)
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64 | /* ETHERPIR0 */
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65 | #define PIR0_MDI (0x00000008)
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66 | #define PIR0_MDO (0x00000004)
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67 | #define PIR0_MMD (0x00000002)
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68 | #define PIR0_MDC (0x00000001)
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69 | #define PIR0_MDC_HIGH (0x00000001)
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70 | #define PIR0_MDC_LOW (0x00000000)
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71 | /* ETHEREDRRR0 */
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72 | #define EDRRR0_RR (0x00000001)
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73 | /* ETHEREDTRR0 */
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74 | #define EDTRR0_TR (0x00000003)
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75 | /* software wait */
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76 | #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
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77 |
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78 | #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
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79 | /* 0x00040000 : Detect frame reception */
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80 | /* 0x00010000 : Receive FIFO overflow */
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81 | /* 0x00000010 : Residual bit frame reception */
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82 | /* 0x00000008 : Long frame reception */
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83 | /* 0x00000004 : Short frame reception */
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84 | /* 0x00000002 : PHY-LSI reception error */
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85 | /* 0x00000001 : Receive frame CRC error */
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86 | #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
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87 |
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88 | /* Send descriptor */
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89 | typedef struct tag_edmac_send_desc {
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90 | uint32_t td0;
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91 | uint32_t td1;
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92 | uint8_t *td2;
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93 | uint32_t padding4;
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94 | } edmac_send_desc_t;
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95 |
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96 | /* Receive descriptor */
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97 | typedef struct tag_edmac_recv_desc {
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98 | uint32_t rd0;
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99 | uint32_t rd1;
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100 | uint8_t *rd2;
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101 | uint32_t padding4;
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102 | } edmac_recv_desc_t;
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103 |
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104 | /* memory */
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105 | /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
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106 | /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
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107 | static uint8_t ehernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
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108 | (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
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109 | (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
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110 | (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
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111 | __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
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112 | static int32_t rx_read_offset; /* read offset */
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113 | static int32_t tx_wite_offset; /* write offset */
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114 | static uint32_t send_top_index;
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115 | static uint32_t recv_top_index;
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116 | static int32_t Interrupt_priority;
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117 | static edmac_send_desc_t *p_eth_desc_dsend = NULL;
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118 | static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
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119 | static edmac_recv_desc_t *p_recv_end_desc = NULL;
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120 | static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
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121 | static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
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122 | static uint32_t phy_id = 0;
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123 | static uint32_t start_stop = 1; /* 0:stop 1:start */
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124 |
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125 | /* function */
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126 | static void lan_reg_reset(void);
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127 | static void lan_desc_create(void);
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128 | static void lan_reg_set(int32_t link);
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129 | static uint16_t phy_reg_read(uint16_t reg_addr);
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130 | static void phy_reg_write(uint16_t reg_addr, uint16_t data);
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131 | static void mii_preamble(void);
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132 | static void mii_cmd(uint16_t reg_addr, uint32_t option);
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133 | static void mii_reg_read(uint16_t *data);
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134 | static void mii_reg_write(uint16_t data);
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135 | static void mii_z(void);
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136 | static void mii_write_1(void);
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137 | static void mii_write_0(void);
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138 | static void set_ether_pir(uint32_t set_data);
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139 | static void wait_100us(int32_t wait_cnt);
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140 |
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141 |
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142 | int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
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143 | int32_t i;
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144 | uint16_t val;
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145 |
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146 | CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
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147 |
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148 | /* P4_2(PHY Reset) */
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149 | GPIOP4 &= ~0x0004; /* Outputs low level */
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150 | GPIOPMC4 &= ~0x0004; /* Port mode */
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151 | GPIOPM4 &= ~0x0004; /* Output mode */
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152 |
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153 | /* GPIO P1 P1_14(ET_COL) */
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154 | GPIOPMC1 |= 0x4000;
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155 | GPIOPFCAE1 &= ~0x4000;
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156 | GPIOPFCE1 |= 0x4000;
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157 | GPIOPFC1 |= 0x4000;
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158 |
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159 | /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
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160 | GPIOPMC3 |= 0x0079;
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161 | GPIOPFCAE3 &= ~0x0079;
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162 | GPIOPFCE3 &= ~0x0079;
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163 | GPIOPFC3 |= 0x0079;
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164 | GPIOPIPC3 |= 0x0079;
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165 |
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166 | /* P5_9(ET_MDC) */
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167 | GPIOPMC5 |= 0x0200;
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168 | GPIOPFCAE5 &= ~0x0200;
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169 | GPIOPFCE5 &= ~0x0200;
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170 | GPIOPFC5 |= 0x0200;
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171 | GPIOPIPC5 |= 0x0200;
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172 |
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173 | /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
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174 | /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
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175 | GPIOPMC10 |= 0x0FFE;
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176 | GPIOPFCAE10 &= ~0x0FFE;
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177 | GPIOPFCE10 |= 0x0FFE;
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178 | GPIOPFC10 |= 0x0FFE;
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179 | GPIOPIPC10 |= 0x0FFE;
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180 |
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181 | /* Resets the E-MAC,E-DMAC */
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182 | lan_reg_reset();
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183 |
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184 | /* PHY Reset */
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185 | GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */
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186 | wait_100us(250); /* 25msec */
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187 | GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
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188 | wait_100us(100); /* 10msec */
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189 |
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190 | /* Resets the PHY-LSI */
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191 | phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
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192 | for (i = 10000; i > 0; i--) {
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193 | val = phy_reg_read(BASIC_MODE_CONTROL_REG);
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194 | if (((uint32_t)val & 0x8000uL) == 0) {
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195 | break; /* Reset complete */
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196 | }
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197 | }
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198 |
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199 | phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
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200 | | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
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201 |
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202 | Interrupt_priority = p_ethcfg->int_priority;
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203 | p_recv_cb_fnc = p_ethcfg->recv_cb;
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204 | start_stop = 1;
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205 |
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206 | if (p_ethcfg->ether_mac != NULL) {
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207 | (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
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208 | } else {
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209 | ethernet_address(mac_addr); /* Get MAC Address */
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210 | }
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211 |
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212 | return 0;
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213 | }
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214 |
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215 | void ethernetext_start_stop(int32_t mode) {
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216 | if (mode == 1) {
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217 | /* start */
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218 | ETHEREDTRR0 |= EDTRR0_TR;
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219 | ETHEREDRRR0 |= EDRRR0_RR;
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220 | start_stop = 1;
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221 | } else {
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222 | /* stop */
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223 | ETHEREDTRR0 &= ~EDTRR0_TR;
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224 | ETHEREDRRR0 &= ~EDRRR0_RR;
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225 | start_stop = 0;
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226 | }
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227 | }
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228 |
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229 | int ethernetext_chk_link_mode(void) {
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230 | int32_t link;
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231 | uint16_t data;
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232 |
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233 | if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
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234 | data = phy_reg_read(PHY_SP_CTL_STS_REG);
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235 | switch (((uint32_t)data >> 2) & 0x00000007) {
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236 | case 0x0001:
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237 | link = HALF_10M;
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238 | break;
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239 | case 0x0005:
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240 | link = FULL_10M;
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241 | break;
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242 | case 0x0002:
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243 | link = HALF_TX;
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244 | break;
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245 | case 0x0006:
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246 | link = FULL_TX;
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247 | break;
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248 | default:
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249 | link = NEGO_FAIL;
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250 | break;
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251 | }
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252 | } else {
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253 | link = NEGO_FAIL;
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254 | }
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255 |
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256 | return link;
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257 | }
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258 |
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259 | void ethernetext_set_link_mode(int32_t link) {
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260 | lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
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261 | lan_desc_create(); /* Initialize of buffer memory */
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262 | lan_reg_set(link); /* E-DMAC, E-MAC initialization */
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263 | }
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264 |
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265 | int ethernet_init() {
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266 | ethernet_cfg_t ethcfg;
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267 |
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268 | ethcfg.int_priority = 5;
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269 | ethcfg.recv_cb = NULL;
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270 | ethcfg.ether_mac = NULL;
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271 | ethernetext_init(ðcfg);
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272 | ethernet_set_link(-1, 0); /* Auto-Negotiation */
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273 |
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274 | return 0;
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275 | }
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276 |
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277 | void ethernet_free() {
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278 | ETHERARSTR |= 0x00000001; /* ETHER software reset */
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279 | CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
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280 | }
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281 |
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282 | int ethernet_write(const char *data, int slen) {
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283 | edmac_send_desc_t *p_send_desc;
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284 | int32_t copy_size;
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285 |
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286 | if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
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287 | || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
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288 | copy_size = 0;
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289 | } else {
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290 | p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
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291 | if ((p_send_desc->td0 & TD0_TACT) != 0) {
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292 | copy_size = 0;
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293 | } else {
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294 | copy_size = MAX_SEND_SIZE - tx_wite_offset;
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295 | if (copy_size > slen) {
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296 | copy_size = slen;
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297 | }
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298 | (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
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299 | tx_wite_offset += copy_size;
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300 | }
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301 | }
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302 |
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303 | return copy_size;
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304 | }
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305 |
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306 | int ethernet_send() {
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307 | edmac_send_desc_t *p_send_desc;
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308 | int32_t ret;
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309 |
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310 | if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
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311 | ret = 0;
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312 | } else {
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313 | /* Transfer 1 frame */
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314 | p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
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315 |
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316 | /* Sets the frame length */
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317 | p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
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318 | tx_wite_offset = 0;
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319 |
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320 | /* Sets the transmit descriptor to transmit again */
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321 | p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
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322 | p_send_desc->td0 |= TD0_TACT;
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323 | if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
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324 | ETHEREDTRR0 |= EDTRR0_TR;
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325 | }
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326 |
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327 | /* Update the current descriptor */
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328 | send_top_index++;
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329 | if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
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330 | send_top_index = 0;
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331 | }
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332 | ret = 1;
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333 | }
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334 |
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335 | return ret;
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336 | }
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337 |
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338 | int ethernet_receive() {
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339 | edmac_recv_desc_t *p_recv_desc;
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340 | int32_t receive_size = 0;
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341 |
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342 | if (p_eth_desc_drecv != NULL) {
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343 | if (p_recv_end_desc != NULL) {
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344 | /* Sets the receive descriptor to receive again */
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345 | p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
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346 | p_recv_end_desc->rd0 |= RD0_RACT;
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347 | if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
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348 | ETHEREDRRR0 |= EDRRR0_RR;
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349 | }
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350 | p_recv_end_desc = NULL;
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351 | }
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352 |
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353 | p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
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354 | if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
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355 | /* Receives 1 frame */
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356 | if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
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357 | /* Receive frame error */
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358 | /* Sets the receive descriptor to receive again */
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359 | p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
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360 | p_recv_desc->rd0 |= RD0_RACT;
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361 | if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
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362 | ETHEREDRRR0 |= EDRRR0_RR;
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363 | }
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364 | } else {
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365 | /* Copies the received frame */
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366 | rx_read_offset = 0;
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367 | p_recv_end_desc = p_recv_desc;
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368 | receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
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369 | }
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370 |
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371 | /* Update the current descriptor */
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372 | recv_top_index++;
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373 | if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
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374 | recv_top_index = 0;
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375 | }
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376 | }
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377 | }
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378 |
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379 | return receive_size;
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380 | }
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381 |
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382 | int ethernet_read(char *data, int dlen) {
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383 | edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
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384 | int32_t copy_size;
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385 |
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386 | if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
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387 | copy_size = 0;
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388 | } else {
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389 | copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
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390 | if (copy_size > dlen) {
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391 | copy_size = dlen;
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392 | }
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393 | (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
|
---|
394 | rx_read_offset += copy_size;
|
---|
395 | }
|
---|
396 |
|
---|
397 | return copy_size;
|
---|
398 | }
|
---|
399 |
|
---|
400 | void ethernet_address(char *mac) {
|
---|
401 | if (mac != NULL) {
|
---|
402 | mbed_mac_address(mac); /* Get MAC Address */
|
---|
403 | }
|
---|
404 | }
|
---|
405 |
|
---|
406 | int ethernet_link(void) {
|
---|
407 | int32_t ret;
|
---|
408 | uint16_t data;
|
---|
409 |
|
---|
410 | data = phy_reg_read(BASIC_MODE_STATUS_REG);
|
---|
411 | if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
|
---|
412 | ret = 1;
|
---|
413 | } else {
|
---|
414 | ret = 0;
|
---|
415 | }
|
---|
416 |
|
---|
417 | return ret;
|
---|
418 | }
|
---|
419 |
|
---|
420 | void ethernet_set_link(int speed, int duplex) {
|
---|
421 | uint16_t data;
|
---|
422 | int32_t i;
|
---|
423 | int32_t link;
|
---|
424 |
|
---|
425 | if ((speed < 0) || (speed > 1)) {
|
---|
426 | data = 0x1000; /* Auto-Negotiation Enable */
|
---|
427 | phy_reg_write(BASIC_MODE_CONTROL_REG, data);
|
---|
428 | data = phy_reg_read(BASIC_MODE_STATUS_REG);
|
---|
429 | for (i = 0; i < 1000; i++) {
|
---|
430 | if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
|
---|
431 | break;
|
---|
432 | }
|
---|
433 | wait_100us(10);
|
---|
434 | }
|
---|
435 | } else {
|
---|
436 | data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
|
---|
437 | phy_reg_write(BASIC_MODE_CONTROL_REG, data);
|
---|
438 | wait_100us(1);
|
---|
439 | }
|
---|
440 |
|
---|
441 | link = ethernetext_chk_link_mode();
|
---|
442 | ethernetext_set_link_mode(link);
|
---|
443 | }
|
---|
444 |
|
---|
445 | void INT_Ether(void) {
|
---|
446 | uint32_t stat_edmac;
|
---|
447 | uint32_t stat_etherc;
|
---|
448 |
|
---|
449 | /* Clear the interrupt request flag */
|
---|
450 | stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
|
---|
451 | ETHEREESR0 = stat_edmac;
|
---|
452 | /* Reception-related */
|
---|
453 | if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
|
---|
454 | if (p_recv_cb_fnc != NULL) {
|
---|
455 | p_recv_cb_fnc();
|
---|
456 | }
|
---|
457 | }
|
---|
458 | /* E-MAC-related */
|
---|
459 | if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
|
---|
460 | /* Clear the interrupt request flag */
|
---|
461 | stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
|
---|
462 | ETHERECSR0 = stat_etherc;
|
---|
463 | }
|
---|
464 | }
|
---|
465 |
|
---|
466 | static void lan_reg_reset(void) {
|
---|
467 | volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
|
---|
468 |
|
---|
469 | ETHERARSTR |= 0x00000001; /* ETHER software reset */
|
---|
470 | while (j--) {
|
---|
471 | /* Do Nothing */
|
---|
472 | }
|
---|
473 |
|
---|
474 | ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
|
---|
475 | ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
|
---|
476 |
|
---|
477 | /* Check clear software reset */
|
---|
478 | while ((ETHEREDMR0 & 0x00000003) != 0) {
|
---|
479 | /* Do Nothing */
|
---|
480 | }
|
---|
481 | }
|
---|
482 |
|
---|
483 | static void lan_desc_create(void) {
|
---|
484 | int32_t i;
|
---|
485 | uint8_t *p_memory_top;
|
---|
486 |
|
---|
487 | (void)memset((void *)ehernet_nc_memory, 0, sizeof(ehernet_nc_memory));
|
---|
488 | p_memory_top = ehernet_nc_memory;
|
---|
489 |
|
---|
490 | /* Descriptor area configuration */
|
---|
491 | p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
|
---|
492 | p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
|
---|
493 | p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
|
---|
494 | p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
|
---|
495 |
|
---|
496 | /* Transmit descriptor */
|
---|
497 | for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
|
---|
498 | p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
|
---|
499 | p_memory_top += SIZE_OF_BUFFER;
|
---|
500 | p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
|
---|
501 | p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
|
---|
502 | }
|
---|
503 | p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
|
---|
504 |
|
---|
505 | /* Receive descriptor */
|
---|
506 | for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
|
---|
507 | p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
|
---|
508 | p_memory_top += SIZE_OF_BUFFER;
|
---|
509 | p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
|
---|
510 | p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
|
---|
511 | }
|
---|
512 | p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
|
---|
513 |
|
---|
514 | /* Initialize descriptor management information */
|
---|
515 | send_top_index = 0;
|
---|
516 | recv_top_index = 0;
|
---|
517 | rx_read_offset = 0;
|
---|
518 | tx_wite_offset = 0;
|
---|
519 | p_recv_end_desc = NULL;
|
---|
520 | }
|
---|
521 |
|
---|
522 | static void lan_reg_set(int32_t link) {
|
---|
523 | /* MAC address setting */
|
---|
524 | ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
|
---|
525 | | ((uint32_t)mac_addr[1] << 16)
|
---|
526 | | ((uint32_t)mac_addr[2] << 8)
|
---|
527 | | (uint32_t)mac_addr[3];
|
---|
528 | ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
|
---|
529 | | (uint32_t)mac_addr[5];
|
---|
530 |
|
---|
531 | /* E-DMAC */
|
---|
532 | ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
|
---|
533 | ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
|
---|
534 | ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
|
---|
535 | ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
|
---|
536 | ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
|
---|
537 | ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
|
---|
538 | ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
|
---|
539 | ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
|
---|
540 | ETHEREDMR0 |= 0x00000040; /* Little endian */
|
---|
541 | ETHERTRSCER0 &= ~0x0003009F; /* All clear */
|
---|
542 | ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
|
---|
543 | ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
|
---|
544 | ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
|
---|
545 | ETHERFCFTR0 &= ~0x001F00FF;
|
---|
546 | ETHERFCFTR0 |= 0x00070007;
|
---|
547 | ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
|
---|
548 |
|
---|
549 | /* E-MAC */
|
---|
550 | ETHERECMR0 &= ~0x04BF2063; /* All clear */
|
---|
551 | ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
|
---|
552 | ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
|
---|
553 | ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
|
---|
554 | ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
|
---|
555 | ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
|
---|
556 | if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
|
---|
557 | ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
|
---|
558 | } else {
|
---|
559 | ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
|
---|
560 | }
|
---|
561 |
|
---|
562 | /* Interrupt-related */
|
---|
563 | if (p_recv_cb_fnc != NULL) {
|
---|
564 | ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
|
---|
565 | ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
|
---|
566 | ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
|
---|
567 | ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
|
---|
568 | /*InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
|
---|
569 | GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
|
---|
570 | GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
|
---|
571 | }
|
---|
572 |
|
---|
573 | ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
|
---|
574 |
|
---|
575 | /* Enable transmission/reception */
|
---|
576 | if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
|
---|
577 | ETHEREDRRR0 |= 0x00000001; /* RR */
|
---|
578 | }
|
---|
579 | }
|
---|
580 |
|
---|
581 | static uint16_t phy_reg_read(uint16_t reg_addr) {
|
---|
582 | uint16_t data;
|
---|
583 |
|
---|
584 | mii_preamble();
|
---|
585 | mii_cmd(reg_addr, PHY_READ);
|
---|
586 | mii_z();
|
---|
587 | mii_reg_read(&data);
|
---|
588 | mii_z();
|
---|
589 |
|
---|
590 | return data;
|
---|
591 | }
|
---|
592 |
|
---|
593 | static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
|
---|
594 | mii_preamble();
|
---|
595 | mii_cmd(reg_addr, PHY_WRITE);
|
---|
596 | mii_write_1();
|
---|
597 | mii_write_0();
|
---|
598 | mii_reg_write(data);
|
---|
599 | mii_z();
|
---|
600 | }
|
---|
601 |
|
---|
602 | static void mii_preamble(void) {
|
---|
603 | int32_t i = 32;
|
---|
604 |
|
---|
605 | for (i = 32; i > 0; i--) {
|
---|
606 | /* 1 is output via the MII (Media Independent Interface) block. */
|
---|
607 | mii_write_1();
|
---|
608 | }
|
---|
609 | }
|
---|
610 |
|
---|
611 | static void mii_cmd(uint16_t reg_addr, uint32_t option) {
|
---|
612 | int32_t i;
|
---|
613 | uint16_t data = 0;
|
---|
614 |
|
---|
615 | data |= (PHY_ST << 14); /* ST code */
|
---|
616 | data |= (option << 12); /* OP code */
|
---|
617 | data |= (PHY_ADDR << 7); /* PHY Address */
|
---|
618 | data |= (uint16_t)(reg_addr << 2); /* Reg Address */
|
---|
619 | for (i = 14; i > 0; i--) {
|
---|
620 | if ((data & 0x8000) == 0) {
|
---|
621 | mii_write_0();
|
---|
622 | } else {
|
---|
623 | mii_write_1();
|
---|
624 | }
|
---|
625 | data <<= 1;
|
---|
626 | }
|
---|
627 | }
|
---|
628 |
|
---|
629 | static void mii_reg_read(uint16_t *data) {
|
---|
630 | int32_t i;
|
---|
631 | uint16_t reg_data = 0;
|
---|
632 |
|
---|
633 | /* Data are read in one bit at a time */
|
---|
634 | for (i = 16; i > 0; i--) {
|
---|
635 | set_ether_pir(PIR0_MDC_LOW);
|
---|
636 | set_ether_pir(PIR0_MDC_HIGH);
|
---|
637 | reg_data <<= 1;
|
---|
638 | reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
|
---|
639 | set_ether_pir(PIR0_MDC_HIGH);
|
---|
640 | set_ether_pir(PIR0_MDC_LOW);
|
---|
641 | }
|
---|
642 | *data = reg_data;
|
---|
643 | }
|
---|
644 |
|
---|
645 | static void mii_reg_write(uint16_t data) {
|
---|
646 | int32_t i;
|
---|
647 |
|
---|
648 | /* Data are written one bit at a time */
|
---|
649 | for (i = 16; i > 0; i--) {
|
---|
650 | if ((data & 0x8000) == 0) {
|
---|
651 | mii_write_0();
|
---|
652 | } else {
|
---|
653 | mii_write_1();
|
---|
654 | }
|
---|
655 | data <<= 1;
|
---|
656 | }
|
---|
657 | }
|
---|
658 |
|
---|
659 | static void mii_z(void) {
|
---|
660 | set_ether_pir(PIR0_MDC_LOW);
|
---|
661 | set_ether_pir(PIR0_MDC_HIGH);
|
---|
662 | set_ether_pir(PIR0_MDC_HIGH);
|
---|
663 | set_ether_pir(PIR0_MDC_LOW);
|
---|
664 | }
|
---|
665 |
|
---|
666 | static void mii_write_1(void) {
|
---|
667 | set_ether_pir(PIR0_MDO | PIR0_MMD);
|
---|
668 | set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
|
---|
669 | set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
|
---|
670 | set_ether_pir(PIR0_MDO | PIR0_MMD);
|
---|
671 | }
|
---|
672 |
|
---|
673 | static void mii_write_0(void) {
|
---|
674 | set_ether_pir(PIR0_MMD);
|
---|
675 | set_ether_pir(PIR0_MMD | PIR0_MDC);
|
---|
676 | set_ether_pir(PIR0_MMD | PIR0_MDC);
|
---|
677 | set_ether_pir(PIR0_MMD);
|
---|
678 | }
|
---|
679 |
|
---|
680 | static void set_ether_pir(uint32_t set_data) {
|
---|
681 | int32_t i;
|
---|
682 |
|
---|
683 | for (i = MDC_WAIT; i > 0; i--) {
|
---|
684 | ETHERPIR0 = set_data;
|
---|
685 | }
|
---|
686 | }
|
---|
687 |
|
---|
688 | static void wait_100us(int32_t wait_cnt) {
|
---|
689 | volatile int32_t j = LOOP_100us * wait_cnt;
|
---|
690 |
|
---|
691 | while (--j) {
|
---|
692 | /* Do Nothing */
|
---|
693 | }
|
---|
694 | }
|
---|