1 | /**************************************************************************//**
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2 | * @file core_cmSimd.h
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3 | * @brief CMSIS Cortex-M SIMD Header File
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4 | * @version V4.10
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5 | * @date 18. March 2015
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /* Copyright (c) 2009 - 2014 ARM LIMITED
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11 |
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12 | All rights reserved.
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13 | Redistribution and use in source and binary forms, with or without
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14 | modification, are permitted provided that the following conditions are met:
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15 | - Redistributions of source code must retain the above copyright
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16 | notice, this list of conditions and the following disclaimer.
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17 | - Redistributions in binary form must reproduce the above copyright
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18 | notice, this list of conditions and the following disclaimer in the
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19 | documentation and/or other materials provided with the distribution.
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20 | - Neither the name of ARM nor the names of its contributors may be used
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21 | to endorse or promote products derived from this software without
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22 | specific prior written permission.
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23 | *
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24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 | POSSIBILITY OF SUCH DAMAGE.
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35 | ---------------------------------------------------------------------------*/
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36 |
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37 |
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38 | #if defined ( __ICCARM__ )
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39 | #pragma system_include /* treat file as system include file for MISRA check */
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40 | #endif
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41 |
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42 | #ifndef __CORE_CMSIMD_H
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43 | #define __CORE_CMSIMD_H
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44 |
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45 | #ifdef __cplusplus
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46 | extern "C" {
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47 | #endif
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48 |
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49 |
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50 | /*******************************************************************************
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51 | * Hardware Abstraction Layer
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52 | ******************************************************************************/
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53 |
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54 |
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55 | /* ################### Compiler specific Intrinsics ########################### */
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56 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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57 | Access to dedicated SIMD instructions
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58 | @{
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59 | */
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60 |
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61 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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62 | /* ARM armcc specific functions */
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63 | #define __SADD8 __sadd8
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64 | #define __QADD8 __qadd8
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65 | #define __SHADD8 __shadd8
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66 | #define __UADD8 __uadd8
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67 | #define __UQADD8 __uqadd8
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68 | #define __UHADD8 __uhadd8
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69 | #define __SSUB8 __ssub8
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70 | #define __QSUB8 __qsub8
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71 | #define __SHSUB8 __shsub8
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72 | #define __USUB8 __usub8
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73 | #define __UQSUB8 __uqsub8
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74 | #define __UHSUB8 __uhsub8
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75 | #define __SADD16 __sadd16
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76 | #define __QADD16 __qadd16
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77 | #define __SHADD16 __shadd16
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78 | #define __UADD16 __uadd16
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79 | #define __UQADD16 __uqadd16
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80 | #define __UHADD16 __uhadd16
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81 | #define __SSUB16 __ssub16
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82 | #define __QSUB16 __qsub16
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83 | #define __SHSUB16 __shsub16
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84 | #define __USUB16 __usub16
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85 | #define __UQSUB16 __uqsub16
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86 | #define __UHSUB16 __uhsub16
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87 | #define __SASX __sasx
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88 | #define __QASX __qasx
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89 | #define __SHASX __shasx
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90 | #define __UASX __uasx
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91 | #define __UQASX __uqasx
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92 | #define __UHASX __uhasx
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93 | #define __SSAX __ssax
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94 | #define __QSAX __qsax
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95 | #define __SHSAX __shsax
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96 | #define __USAX __usax
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97 | #define __UQSAX __uqsax
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98 | #define __UHSAX __uhsax
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99 | #define __USAD8 __usad8
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100 | #define __USADA8 __usada8
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101 | #define __SSAT16 __ssat16
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102 | #define __USAT16 __usat16
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103 | #define __UXTB16 __uxtb16
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104 | #define __UXTAB16 __uxtab16
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105 | #define __SXTB16 __sxtb16
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106 | #define __SXTAB16 __sxtab16
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107 | #define __SMUAD __smuad
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108 | #define __SMUADX __smuadx
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109 | #define __SMLAD __smlad
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110 | #define __SMLADX __smladx
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111 | #define __SMLALD __smlald
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112 | #define __SMLALDX __smlaldx
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113 | #define __SMUSD __smusd
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114 | #define __SMUSDX __smusdx
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115 | #define __SMLSD __smlsd
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116 | #define __SMLSDX __smlsdx
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117 | #define __SMLSLD __smlsld
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118 | #define __SMLSLDX __smlsldx
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119 | #define __SEL __sel
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120 | #define __QADD __qadd
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121 | #define __QSUB __qsub
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122 |
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123 | #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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124 | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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125 |
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126 | #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
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127 | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
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128 |
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129 | #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
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130 | ((int64_t)(ARG3) << 32) ) >> 32))
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131 |
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132 |
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133 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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134 | /* GNU gcc specific functions */
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135 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
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136 | {
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137 | uint32_t result;
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138 |
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139 | __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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140 | return(result);
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141 | }
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142 |
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143 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
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144 | {
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145 | uint32_t result;
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146 |
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147 | __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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148 | return(result);
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149 | }
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150 |
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151 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
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152 | {
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153 | uint32_t result;
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154 |
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155 | __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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156 | return(result);
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157 | }
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158 |
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159 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
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160 | {
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161 | uint32_t result;
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162 |
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163 | __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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164 | return(result);
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165 | }
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166 |
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167 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
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168 | {
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169 | uint32_t result;
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170 |
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171 | __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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172 | return(result);
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173 | }
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174 |
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175 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
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176 | {
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177 | uint32_t result;
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178 |
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179 | __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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180 | return(result);
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181 | }
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182 |
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183 |
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184 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
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185 | {
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186 | uint32_t result;
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187 |
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188 | __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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189 | return(result);
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190 | }
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191 |
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192 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
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193 | {
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194 | uint32_t result;
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195 |
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196 | __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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197 | return(result);
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198 | }
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199 |
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200 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
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201 | {
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202 | uint32_t result;
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203 |
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204 | __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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205 | return(result);
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206 | }
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207 |
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208 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
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209 | {
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210 | uint32_t result;
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211 |
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212 | __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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213 | return(result);
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214 | }
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215 |
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216 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
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217 | {
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218 | uint32_t result;
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219 |
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220 | __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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221 | return(result);
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222 | }
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223 |
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224 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
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225 | {
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226 | uint32_t result;
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227 |
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228 | __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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229 | return(result);
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230 | }
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231 |
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232 |
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233 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
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234 | {
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235 | uint32_t result;
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236 |
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237 | __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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238 | return(result);
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239 | }
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240 |
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241 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
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242 | {
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243 | uint32_t result;
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244 |
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245 | __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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246 | return(result);
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247 | }
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248 |
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249 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
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250 | {
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251 | uint32_t result;
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252 |
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253 | __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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254 | return(result);
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255 | }
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256 |
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257 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
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258 | {
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259 | uint32_t result;
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260 |
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261 | __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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262 | return(result);
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263 | }
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264 |
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265 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
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266 | {
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267 | uint32_t result;
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268 |
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269 | __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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270 | return(result);
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271 | }
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272 |
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273 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
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274 | {
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275 | uint32_t result;
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276 |
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277 | __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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278 | return(result);
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279 | }
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280 |
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281 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
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282 | {
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283 | uint32_t result;
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284 |
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285 | __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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286 | return(result);
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287 | }
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288 |
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289 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
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290 | {
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291 | uint32_t result;
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292 |
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293 | __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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294 | return(result);
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295 | }
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296 |
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297 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
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298 | {
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299 | uint32_t result;
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300 |
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301 | __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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302 | return(result);
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303 | }
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304 |
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305 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
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306 | {
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307 | uint32_t result;
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308 |
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309 | __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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310 | return(result);
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311 | }
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312 |
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313 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
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314 | {
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315 | uint32_t result;
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316 |
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317 | __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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318 | return(result);
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319 | }
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320 |
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321 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
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322 | {
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323 | uint32_t result;
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324 |
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325 | __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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326 | return(result);
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327 | }
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328 |
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329 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
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330 | {
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331 | uint32_t result;
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332 |
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333 | __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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334 | return(result);
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335 | }
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336 |
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337 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
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338 | {
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339 | uint32_t result;
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340 |
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341 | __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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342 | return(result);
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343 | }
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344 |
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345 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
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346 | {
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347 | uint32_t result;
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348 |
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349 | __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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350 | return(result);
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351 | }
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352 |
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353 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
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354 | {
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355 | uint32_t result;
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356 |
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357 | __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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358 | return(result);
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359 | }
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360 |
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361 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
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362 | {
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363 | uint32_t result;
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364 |
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365 | __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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366 | return(result);
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367 | }
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368 |
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369 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
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370 | {
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371 | uint32_t result;
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372 |
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373 | __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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374 | return(result);
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375 | }
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376 |
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377 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
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378 | {
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379 | uint32_t result;
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380 |
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381 | __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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382 | return(result);
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383 | }
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384 |
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385 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
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386 | {
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387 | uint32_t result;
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388 |
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389 | __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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390 | return(result);
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391 | }
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392 |
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393 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
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394 | {
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395 | uint32_t result;
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396 |
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397 | __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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398 | return(result);
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399 | }
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400 |
|
---|
401 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
---|
402 | {
|
---|
403 | uint32_t result;
|
---|
404 |
|
---|
405 | __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
406 | return(result);
|
---|
407 | }
|
---|
408 |
|
---|
409 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
---|
410 | {
|
---|
411 | uint32_t result;
|
---|
412 |
|
---|
413 | __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
414 | return(result);
|
---|
415 | }
|
---|
416 |
|
---|
417 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
---|
418 | {
|
---|
419 | uint32_t result;
|
---|
420 |
|
---|
421 | __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
422 | return(result);
|
---|
423 | }
|
---|
424 |
|
---|
425 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
---|
426 | {
|
---|
427 | uint32_t result;
|
---|
428 |
|
---|
429 | __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
430 | return(result);
|
---|
431 | }
|
---|
432 |
|
---|
433 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
434 | {
|
---|
435 | uint32_t result;
|
---|
436 |
|
---|
437 | __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
438 | return(result);
|
---|
439 | }
|
---|
440 |
|
---|
441 | #define __SSAT16(ARG1,ARG2) \
|
---|
442 | ({ \
|
---|
443 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
444 | __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
445 | __RES; \
|
---|
446 | })
|
---|
447 |
|
---|
448 | #define __USAT16(ARG1,ARG2) \
|
---|
449 | ({ \
|
---|
450 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
451 | __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
452 | __RES; \
|
---|
453 | })
|
---|
454 |
|
---|
455 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
---|
456 | {
|
---|
457 | uint32_t result;
|
---|
458 |
|
---|
459 | __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
---|
460 | return(result);
|
---|
461 | }
|
---|
462 |
|
---|
463 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
---|
464 | {
|
---|
465 | uint32_t result;
|
---|
466 |
|
---|
467 | __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
468 | return(result);
|
---|
469 | }
|
---|
470 |
|
---|
471 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
---|
472 | {
|
---|
473 | uint32_t result;
|
---|
474 |
|
---|
475 | __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
---|
476 | return(result);
|
---|
477 | }
|
---|
478 |
|
---|
479 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
---|
480 | {
|
---|
481 | uint32_t result;
|
---|
482 |
|
---|
483 | __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
484 | return(result);
|
---|
485 | }
|
---|
486 |
|
---|
487 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
---|
488 | {
|
---|
489 | uint32_t result;
|
---|
490 |
|
---|
491 | __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
492 | return(result);
|
---|
493 | }
|
---|
494 |
|
---|
495 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
---|
496 | {
|
---|
497 | uint32_t result;
|
---|
498 |
|
---|
499 | __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
500 | return(result);
|
---|
501 | }
|
---|
502 |
|
---|
503 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
504 | {
|
---|
505 | uint32_t result;
|
---|
506 |
|
---|
507 | __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
508 | return(result);
|
---|
509 | }
|
---|
510 |
|
---|
511 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
512 | {
|
---|
513 | uint32_t result;
|
---|
514 |
|
---|
515 | __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
516 | return(result);
|
---|
517 | }
|
---|
518 |
|
---|
519 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
520 | {
|
---|
521 | union llreg_u{
|
---|
522 | uint32_t w32[2];
|
---|
523 | uint64_t w64;
|
---|
524 | } llr;
|
---|
525 | llr.w64 = acc;
|
---|
526 |
|
---|
527 | #ifndef __ARMEB__ // Little endian
|
---|
528 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
529 | #else // Big endian
|
---|
530 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
531 | #endif
|
---|
532 |
|
---|
533 | return(llr.w64);
|
---|
534 | }
|
---|
535 |
|
---|
536 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
537 | {
|
---|
538 | union llreg_u{
|
---|
539 | uint32_t w32[2];
|
---|
540 | uint64_t w64;
|
---|
541 | } llr;
|
---|
542 | llr.w64 = acc;
|
---|
543 |
|
---|
544 | #ifndef __ARMEB__ // Little endian
|
---|
545 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
546 | #else // Big endian
|
---|
547 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
548 | #endif
|
---|
549 |
|
---|
550 | return(llr.w64);
|
---|
551 | }
|
---|
552 |
|
---|
553 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
---|
554 | {
|
---|
555 | uint32_t result;
|
---|
556 |
|
---|
557 | __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
558 | return(result);
|
---|
559 | }
|
---|
560 |
|
---|
561 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
---|
562 | {
|
---|
563 | uint32_t result;
|
---|
564 |
|
---|
565 | __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
566 | return(result);
|
---|
567 | }
|
---|
568 |
|
---|
569 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
570 | {
|
---|
571 | uint32_t result;
|
---|
572 |
|
---|
573 | __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
574 | return(result);
|
---|
575 | }
|
---|
576 |
|
---|
577 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
578 | {
|
---|
579 | uint32_t result;
|
---|
580 |
|
---|
581 | __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
582 | return(result);
|
---|
583 | }
|
---|
584 |
|
---|
585 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
586 | {
|
---|
587 | union llreg_u{
|
---|
588 | uint32_t w32[2];
|
---|
589 | uint64_t w64;
|
---|
590 | } llr;
|
---|
591 | llr.w64 = acc;
|
---|
592 |
|
---|
593 | #ifndef __ARMEB__ // Little endian
|
---|
594 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
595 | #else // Big endian
|
---|
596 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
597 | #endif
|
---|
598 |
|
---|
599 | return(llr.w64);
|
---|
600 | }
|
---|
601 |
|
---|
602 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
603 | {
|
---|
604 | union llreg_u{
|
---|
605 | uint32_t w32[2];
|
---|
606 | uint64_t w64;
|
---|
607 | } llr;
|
---|
608 | llr.w64 = acc;
|
---|
609 |
|
---|
610 | #ifndef __ARMEB__ // Little endian
|
---|
611 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
612 | #else // Big endian
|
---|
613 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
614 | #endif
|
---|
615 |
|
---|
616 | return(llr.w64);
|
---|
617 | }
|
---|
618 |
|
---|
619 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
---|
620 | {
|
---|
621 | uint32_t result;
|
---|
622 |
|
---|
623 | __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
624 | return(result);
|
---|
625 | }
|
---|
626 |
|
---|
627 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
---|
628 | {
|
---|
629 | uint32_t result;
|
---|
630 |
|
---|
631 | __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
632 | return(result);
|
---|
633 | }
|
---|
634 |
|
---|
635 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
---|
636 | {
|
---|
637 | uint32_t result;
|
---|
638 |
|
---|
639 | __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
640 | return(result);
|
---|
641 | }
|
---|
642 |
|
---|
643 | #define __PKHBT(ARG1,ARG2,ARG3) \
|
---|
644 | ({ \
|
---|
645 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
---|
646 | __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
---|
647 | __RES; \
|
---|
648 | })
|
---|
649 |
|
---|
650 | #define __PKHTB(ARG1,ARG2,ARG3) \
|
---|
651 | ({ \
|
---|
652 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
---|
653 | if (ARG3 == 0) \
|
---|
654 | __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
---|
655 | else \
|
---|
656 | __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
---|
657 | __RES; \
|
---|
658 | })
|
---|
659 |
|
---|
660 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
---|
661 | {
|
---|
662 | int32_t result;
|
---|
663 |
|
---|
664 | __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
---|
665 | return(result);
|
---|
666 | }
|
---|
667 |
|
---|
668 |
|
---|
669 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
---|
670 | /* IAR iccarm specific functions */
|
---|
671 | #include <cmsis_iar.h>
|
---|
672 |
|
---|
673 |
|
---|
674 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
---|
675 | /* TI CCS specific functions */
|
---|
676 | #include <cmsis_ccs.h>
|
---|
677 |
|
---|
678 |
|
---|
679 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
---|
680 | /* TASKING carm specific functions */
|
---|
681 | /* not yet supported */
|
---|
682 |
|
---|
683 |
|
---|
684 | #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
---|
685 | /* Cosmic specific functions */
|
---|
686 | #include <cmsis_csm.h>
|
---|
687 |
|
---|
688 | #endif
|
---|
689 |
|
---|
690 | /*@} end of group CMSIS_SIMD_intrinsics */
|
---|
691 |
|
---|
692 |
|
---|
693 | #ifdef __cplusplus
|
---|
694 | }
|
---|
695 | #endif
|
---|
696 |
|
---|
697 | #endif /* __CORE_CMSIMD_H */
|
---|