[270] | 1 | /**************************************************************************//**
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| 2 | * @file core_cmFunc.h
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| 3 | * @brief CMSIS Cortex-M Core Function Access Header File
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| 4 | * @version V3.20
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| 5 | * @date 25. February 2013
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| 6 | *
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| 7 | * @note
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| 8 | *
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| 9 | ******************************************************************************/
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| 10 | /* Copyright (c) 2009 - 2013 ARM LIMITED
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| 11 |
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| 12 | All rights reserved.
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| 13 | Redistribution and use in source and binary forms, with or without
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| 14 | modification, are permitted provided that the following conditions are met:
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| 15 | - Redistributions of source code must retain the above copyright
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| 16 | notice, this list of conditions and the following disclaimer.
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| 17 | - Redistributions in binary form must reproduce the above copyright
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| 18 | notice, this list of conditions and the following disclaimer in the
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| 19 | documentation and/or other materials provided with the distribution.
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| 20 | - Neither the name of ARM nor the names of its contributors may be used
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| 21 | to endorse or promote products derived from this software without
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| 22 | specific prior written permission.
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| 23 | *
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| 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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| 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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| 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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| 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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| 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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| 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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| 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 34 | POSSIBILITY OF SUCH DAMAGE.
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| 35 | ---------------------------------------------------------------------------*/
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| 36 |
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| 37 |
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| 38 | #ifndef __CORE_CMFUNC_H
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| 39 | #define __CORE_CMFUNC_H
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| 40 |
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| 41 |
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| 42 | /* ########################### Core Function Access ########################### */
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| 43 | /** \ingroup CMSIS_Core_FunctionInterface
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| 44 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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| 45 | @{
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| 46 | */
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| 47 |
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| 48 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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| 49 | /* ARM armcc specific functions */
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| 50 |
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| 51 | #if (__ARMCC_VERSION < 400677)
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| 52 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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| 53 | #endif
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| 54 |
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| 55 | /* intrinsic void __enable_irq(); */
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| 56 | /* intrinsic void __disable_irq(); */
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| 57 |
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| 58 | /** \brief Get Control Register
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| 59 |
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| 60 | This function returns the content of the Control Register.
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| 61 |
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| 62 | \return Control Register value
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| 63 | */
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| 64 | __STATIC_INLINE uint32_t __get_CONTROL(void)
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| 65 | {
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| 66 | register uint32_t __regControl __ASM("control");
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| 67 | return(__regControl);
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| 68 | }
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| 69 |
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| 70 |
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| 71 | /** \brief Set Control Register
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| 72 |
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| 73 | This function writes the given value to the Control Register.
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| 74 |
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| 75 | \param [in] control Control Register value to set
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| 76 | */
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| 77 | __STATIC_INLINE void __set_CONTROL(uint32_t control)
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| 78 | {
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| 79 | register uint32_t __regControl __ASM("control");
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| 80 | __regControl = control;
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| 81 | }
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| 82 |
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| 83 |
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| 84 | /** \brief Get IPSR Register
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| 85 |
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| 86 | This function returns the content of the IPSR Register.
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| 87 |
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| 88 | \return IPSR Register value
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| 89 | */
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| 90 | __STATIC_INLINE uint32_t __get_IPSR(void)
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| 91 | {
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| 92 | register uint32_t __regIPSR __ASM("ipsr");
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| 93 | return(__regIPSR);
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| 94 | }
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| 95 |
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| 96 |
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| 97 | /** \brief Get APSR Register
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| 98 |
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| 99 | This function returns the content of the APSR Register.
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| 100 |
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| 101 | \return APSR Register value
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| 102 | */
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| 103 | __STATIC_INLINE uint32_t __get_APSR(void)
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| 104 | {
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| 105 | register uint32_t __regAPSR __ASM("apsr");
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| 106 | return(__regAPSR);
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| 107 | }
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| 108 |
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| 109 |
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| 110 | /** \brief Get xPSR Register
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| 111 |
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| 112 | This function returns the content of the xPSR Register.
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| 113 |
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| 114 | \return xPSR Register value
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| 115 | */
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| 116 | __STATIC_INLINE uint32_t __get_xPSR(void)
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| 117 | {
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| 118 | register uint32_t __regXPSR __ASM("xpsr");
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| 119 | return(__regXPSR);
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| 120 | }
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| 121 |
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| 122 |
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| 123 | /** \brief Get Process Stack Pointer
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| 124 |
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| 125 | This function returns the current value of the Process Stack Pointer (PSP).
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| 126 |
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| 127 | \return PSP Register value
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| 128 | */
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| 129 | __STATIC_INLINE uint32_t __get_PSP(void)
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| 130 | {
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| 131 | register uint32_t __regProcessStackPointer __ASM("psp");
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| 132 | return(__regProcessStackPointer);
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| 133 | }
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| 134 |
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| 135 |
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| 136 | /** \brief Set Process Stack Pointer
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| 137 |
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| 138 | This function assigns the given value to the Process Stack Pointer (PSP).
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| 139 |
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| 140 | \param [in] topOfProcStack Process Stack Pointer value to set
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| 141 | */
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| 142 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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| 143 | {
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| 144 | register uint32_t __regProcessStackPointer __ASM("psp");
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| 145 | __regProcessStackPointer = topOfProcStack;
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| 146 | }
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| 147 |
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| 148 |
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| 149 | /** \brief Get Main Stack Pointer
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| 150 |
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| 151 | This function returns the current value of the Main Stack Pointer (MSP).
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| 152 |
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| 153 | \return MSP Register value
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| 154 | */
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| 155 | __STATIC_INLINE uint32_t __get_MSP(void)
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| 156 | {
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| 157 | register uint32_t __regMainStackPointer __ASM("msp");
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| 158 | return(__regMainStackPointer);
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| 159 | }
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| 160 |
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| 161 |
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| 162 | /** \brief Set Main Stack Pointer
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| 163 |
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| 164 | This function assigns the given value to the Main Stack Pointer (MSP).
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| 165 |
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| 166 | \param [in] topOfMainStack Main Stack Pointer value to set
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| 167 | */
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| 168 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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| 169 | {
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| 170 | register uint32_t __regMainStackPointer __ASM("msp");
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| 171 | __regMainStackPointer = topOfMainStack;
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| 172 | }
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| 173 |
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| 174 |
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| 175 | /** \brief Get Priority Mask
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| 176 |
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| 177 | This function returns the current state of the priority mask bit from the Priority Mask Register.
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| 178 |
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| 179 | \return Priority Mask value
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| 180 | */
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| 181 | __STATIC_INLINE uint32_t __get_PRIMASK(void)
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| 182 | {
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| 183 | register uint32_t __regPriMask __ASM("primask");
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| 184 | return(__regPriMask);
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| 185 | }
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| 186 |
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| 187 |
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| 188 | /** \brief Set Priority Mask
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| 189 |
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| 190 | This function assigns the given value to the Priority Mask Register.
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| 191 |
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| 192 | \param [in] priMask Priority Mask
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| 193 | */
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| 194 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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| 195 | {
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| 196 | register uint32_t __regPriMask __ASM("primask");
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| 197 | __regPriMask = (priMask);
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| 198 | }
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| 199 |
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| 200 |
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| 201 | #if (__CORTEX_M >= 0x03)
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| 202 |
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| 203 | /** \brief Enable FIQ
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| 204 |
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| 205 | This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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| 206 | Can only be executed in Privileged modes.
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| 207 | */
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| 208 | #define __enable_fault_irq __enable_fiq
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| 209 |
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| 210 |
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| 211 | /** \brief Disable FIQ
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| 212 |
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| 213 | This function disables FIQ interrupts by setting the F-bit in the CPSR.
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| 214 | Can only be executed in Privileged modes.
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| 215 | */
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| 216 | #define __disable_fault_irq __disable_fiq
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| 217 |
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| 218 |
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| 219 | /** \brief Get Base Priority
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| 220 |
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| 221 | This function returns the current value of the Base Priority register.
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| 222 |
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| 223 | \return Base Priority register value
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| 224 | */
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| 225 | __STATIC_INLINE uint32_t __get_BASEPRI(void)
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| 226 | {
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| 227 | register uint32_t __regBasePri __ASM("basepri");
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| 228 | return(__regBasePri);
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| 229 | }
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| 230 |
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| 231 |
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| 232 | /** \brief Set Base Priority
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| 233 |
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| 234 | This function assigns the given value to the Base Priority register.
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| 235 |
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| 236 | \param [in] basePri Base Priority value to set
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| 237 | */
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| 238 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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| 239 | {
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| 240 | register uint32_t __regBasePri __ASM("basepri");
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| 241 | __regBasePri = (basePri & 0xff);
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| 242 | }
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| 243 |
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| 244 |
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| 245 | /** \brief Get Fault Mask
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| 246 |
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| 247 | This function returns the current value of the Fault Mask register.
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| 248 |
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| 249 | \return Fault Mask register value
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| 250 | */
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| 251 | __STATIC_INLINE uint32_t __get_FAULTMASK(void)
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| 252 | {
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| 253 | register uint32_t __regFaultMask __ASM("faultmask");
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| 254 | return(__regFaultMask);
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| 255 | }
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| 256 |
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| 257 |
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| 258 | /** \brief Set Fault Mask
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| 259 |
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| 260 | This function assigns the given value to the Fault Mask register.
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| 261 |
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| 262 | \param [in] faultMask Fault Mask value to set
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| 263 | */
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| 264 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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| 265 | {
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| 266 | register uint32_t __regFaultMask __ASM("faultmask");
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| 267 | __regFaultMask = (faultMask & (uint32_t)1);
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| 268 | }
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| 269 |
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| 270 | #endif /* (__CORTEX_M >= 0x03) */
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| 271 |
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| 272 |
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| 273 | #if (__CORTEX_M == 0x04)
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| 274 |
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| 275 | /** \brief Get FPSCR
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| 276 |
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| 277 | This function returns the current value of the Floating Point Status/Control register.
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| 278 |
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| 279 | \return Floating Point Status/Control register value
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| 280 | */
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| 281 | __STATIC_INLINE uint32_t __get_FPSCR(void)
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| 282 | {
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| 283 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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| 284 | register uint32_t __regfpscr __ASM("fpscr");
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| 285 | return(__regfpscr);
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| 286 | #else
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| 287 | return(0);
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| 288 | #endif
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| 289 | }
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| 290 |
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| 291 |
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| 292 | /** \brief Set FPSCR
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| 293 |
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| 294 | This function assigns the given value to the Floating Point Status/Control register.
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| 295 |
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| 296 | \param [in] fpscr Floating Point Status/Control value to set
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| 297 | */
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| 298 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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| 299 | {
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| 300 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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| 301 | register uint32_t __regfpscr __ASM("fpscr");
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| 302 | __regfpscr = (fpscr);
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| 303 | #endif
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| 304 | }
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| 305 |
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| 306 | #endif /* (__CORTEX_M == 0x04) */
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| 307 |
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| 308 |
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| 309 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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| 310 | /* IAR iccarm specific functions */
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| 311 |
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| 312 | #include <cmsis_iar.h>
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| 313 |
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| 314 |
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| 315 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
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| 316 | /* TI CCS specific functions */
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| 317 |
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| 318 | #include <cmsis_ccs.h>
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| 319 |
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| 320 |
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| 321 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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| 322 | /* GNU gcc specific functions */
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| 323 |
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| 324 | /** \brief Enable IRQ Interrupts
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| 325 |
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| 326 | This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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| 327 | Can only be executed in Privileged modes.
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| 328 | */
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| 329 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
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| 330 | {
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| 331 | __ASM volatile ("cpsie i" : : : "memory");
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| 332 | }
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| 333 |
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| 334 |
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| 335 | /** \brief Disable IRQ Interrupts
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| 336 |
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| 337 | This function disables IRQ interrupts by setting the I-bit in the CPSR.
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| 338 | Can only be executed in Privileged modes.
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| 339 | */
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| 340 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
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| 341 | {
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| 342 | __ASM volatile ("cpsid i" : : : "memory");
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| 343 | }
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| 344 |
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| 345 |
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| 346 | /** \brief Get Control Register
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| 347 |
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| 348 | This function returns the content of the Control Register.
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| 349 |
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| 350 | \return Control Register value
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| 351 | */
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| 352 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
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| 353 | {
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| 354 | uint32_t result;
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| 355 |
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| 356 | __ASM volatile ("MRS %0, control" : "=r" (result) );
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| 357 | return(result);
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| 358 | }
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| 359 |
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| 360 |
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| 361 | /** \brief Set Control Register
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| 362 |
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| 363 | This function writes the given value to the Control Register.
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| 364 |
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| 365 | \param [in] control Control Register value to set
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| 366 | */
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| 367 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
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| 368 | {
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| 369 | __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
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| 370 | }
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| 371 |
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| 372 |
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| 373 | /** \brief Get IPSR Register
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| 374 |
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| 375 | This function returns the content of the IPSR Register.
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| 376 |
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| 377 | \return IPSR Register value
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| 378 | */
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| 379 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
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| 380 | {
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| 381 | uint32_t result;
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| 382 |
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| 383 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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| 384 | return(result);
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| 385 | }
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| 386 |
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| 387 |
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| 388 | /** \brief Get APSR Register
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| 389 |
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| 390 | This function returns the content of the APSR Register.
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| 391 |
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| 392 | \return APSR Register value
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| 393 | */
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| 394 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
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| 395 | {
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| 396 | uint32_t result;
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| 397 |
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| 398 | __ASM volatile ("MRS %0, apsr" : "=r" (result) );
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| 399 | return(result);
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| 400 | }
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| 401 |
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| 402 |
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| 403 | /** \brief Get xPSR Register
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| 404 |
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| 405 | This function returns the content of the xPSR Register.
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| 406 |
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| 407 | \return xPSR Register value
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| 408 | */
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| 409 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
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| 410 | {
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| 411 | uint32_t result;
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| 412 |
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| 413 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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| 414 | return(result);
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| 415 | }
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| 416 |
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| 417 |
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| 418 | /** \brief Get Process Stack Pointer
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| 419 |
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| 420 | This function returns the current value of the Process Stack Pointer (PSP).
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| 421 |
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| 422 | \return PSP Register value
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| 423 | */
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| 424 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
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| 425 | {
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| 426 | register uint32_t result;
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| 427 |
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| 428 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
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| 429 | return(result);
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| 430 | }
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| 431 |
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| 432 |
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| 433 | /** \brief Set Process Stack Pointer
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| 434 |
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| 435 | This function assigns the given value to the Process Stack Pointer (PSP).
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| 436 |
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| 437 | \param [in] topOfProcStack Process Stack Pointer value to set
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| 438 | */
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| 439 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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| 440 | {
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| 441 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
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| 442 | }
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| 443 |
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| 444 |
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| 445 | /** \brief Get Main Stack Pointer
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| 446 |
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| 447 | This function returns the current value of the Main Stack Pointer (MSP).
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| 448 |
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| 449 | \return MSP Register value
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| 450 | */
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| 451 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
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| 452 | {
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| 453 | register uint32_t result;
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| 454 |
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| 455 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
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| 456 | return(result);
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| 457 | }
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| 458 |
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| 459 |
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| 460 | /** \brief Set Main Stack Pointer
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| 461 |
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| 462 | This function assigns the given value to the Main Stack Pointer (MSP).
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| 463 |
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| 464 | \param [in] topOfMainStack Main Stack Pointer value to set
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| 465 | */
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| 466 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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| 467 | {
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| 468 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
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| 469 | }
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| 470 |
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| 471 |
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| 472 | /** \brief Get Priority Mask
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| 473 |
|
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| 474 | This function returns the current state of the priority mask bit from the Priority Mask Register.
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| 475 |
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| 476 | \return Priority Mask value
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| 477 | */
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| 478 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
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| 479 | {
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| 480 | uint32_t result;
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| 481 |
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| 482 | __ASM volatile ("MRS %0, primask" : "=r" (result) );
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| 483 | return(result);
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| 484 | }
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| 485 |
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| 486 |
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| 487 | /** \brief Set Priority Mask
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| 488 |
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| 489 | This function assigns the given value to the Priority Mask Register.
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| 490 |
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| 491 | \param [in] priMask Priority Mask
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| 492 | */
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| 493 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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| 494 | {
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| 495 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
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| 496 | }
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| 497 |
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| 498 |
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| 499 | #if (__CORTEX_M >= 0x03)
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| 500 |
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| 501 | /** \brief Enable FIQ
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| 502 |
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| 503 | This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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| 504 | Can only be executed in Privileged modes.
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| 505 | */
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| 506 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
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| 507 | {
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| 508 | __ASM volatile ("cpsie f" : : : "memory");
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| 509 | }
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| 510 |
|
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| 511 |
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| 512 | /** \brief Disable FIQ
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| 513 |
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| 514 | This function disables FIQ interrupts by setting the F-bit in the CPSR.
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| 515 | Can only be executed in Privileged modes.
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| 516 | */
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| 517 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
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| 518 | {
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| 519 | __ASM volatile ("cpsid f" : : : "memory");
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| 520 | }
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---|
| 521 |
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| 522 |
|
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| 523 | /** \brief Get Base Priority
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| 524 |
|
---|
| 525 | This function returns the current value of the Base Priority register.
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| 526 |
|
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| 527 | \return Base Priority register value
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---|
| 528 | */
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| 529 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
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| 530 | {
|
---|
| 531 | uint32_t result;
|
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| 532 |
|
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| 533 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
---|
| 534 | return(result);
|
---|
| 535 | }
|
---|
| 536 |
|
---|
| 537 |
|
---|
| 538 | /** \brief Set Base Priority
|
---|
| 539 |
|
---|
| 540 | This function assigns the given value to the Base Priority register.
|
---|
| 541 |
|
---|
| 542 | \param [in] basePri Base Priority value to set
|
---|
| 543 | */
|
---|
| 544 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
---|
| 545 | {
|
---|
| 546 | __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
---|
| 547 | }
|
---|
| 548 |
|
---|
| 549 |
|
---|
| 550 | /** \brief Get Fault Mask
|
---|
| 551 |
|
---|
| 552 | This function returns the current value of the Fault Mask register.
|
---|
| 553 |
|
---|
| 554 | \return Fault Mask register value
|
---|
| 555 | */
|
---|
| 556 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
---|
| 557 | {
|
---|
| 558 | uint32_t result;
|
---|
| 559 |
|
---|
| 560 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
---|
| 561 | return(result);
|
---|
| 562 | }
|
---|
| 563 |
|
---|
| 564 |
|
---|
| 565 | /** \brief Set Fault Mask
|
---|
| 566 |
|
---|
| 567 | This function assigns the given value to the Fault Mask register.
|
---|
| 568 |
|
---|
| 569 | \param [in] faultMask Fault Mask value to set
|
---|
| 570 | */
|
---|
| 571 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
---|
| 572 | {
|
---|
| 573 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
---|
| 574 | }
|
---|
| 575 |
|
---|
| 576 | #endif /* (__CORTEX_M >= 0x03) */
|
---|
| 577 |
|
---|
| 578 |
|
---|
| 579 | #if (__CORTEX_M == 0x04)
|
---|
| 580 |
|
---|
| 581 | /** \brief Get FPSCR
|
---|
| 582 |
|
---|
| 583 | This function returns the current value of the Floating Point Status/Control register.
|
---|
| 584 |
|
---|
| 585 | \return Floating Point Status/Control register value
|
---|
| 586 | */
|
---|
| 587 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
---|
| 588 | {
|
---|
| 589 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
---|
| 590 | uint32_t result;
|
---|
| 591 |
|
---|
| 592 | /* Empty asm statement works as a scheduling barrier */
|
---|
| 593 | __ASM volatile ("");
|
---|
| 594 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
---|
| 595 | __ASM volatile ("");
|
---|
| 596 | return(result);
|
---|
| 597 | #else
|
---|
| 598 | return(0);
|
---|
| 599 | #endif
|
---|
| 600 | }
|
---|
| 601 |
|
---|
| 602 |
|
---|
| 603 | /** \brief Set FPSCR
|
---|
| 604 |
|
---|
| 605 | This function assigns the given value to the Floating Point Status/Control register.
|
---|
| 606 |
|
---|
| 607 | \param [in] fpscr Floating Point Status/Control value to set
|
---|
| 608 | */
|
---|
| 609 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
---|
| 610 | {
|
---|
| 611 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
---|
| 612 | /* Empty asm statement works as a scheduling barrier */
|
---|
| 613 | __ASM volatile ("");
|
---|
| 614 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
---|
| 615 | __ASM volatile ("");
|
---|
| 616 | #endif
|
---|
| 617 | }
|
---|
| 618 |
|
---|
| 619 | #endif /* (__CORTEX_M == 0x04) */
|
---|
| 620 |
|
---|
| 621 |
|
---|
| 622 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
---|
| 623 | /* TASKING carm specific functions */
|
---|
| 624 |
|
---|
| 625 | /*
|
---|
| 626 | * The CMSIS functions have been implemented as intrinsics in the compiler.
|
---|
| 627 | * Please use "carm -?i" to get an up to date list of all instrinsics,
|
---|
| 628 | * Including the CMSIS ones.
|
---|
| 629 | */
|
---|
| 630 |
|
---|
| 631 | #endif
|
---|
| 632 |
|
---|
| 633 | /*@} end of CMSIS_Core_RegAccFunctions */
|
---|
| 634 |
|
---|
| 635 |
|
---|
| 636 | #endif /* __CORE_CMFUNC_H */
|
---|