[270] | 1 | /**************************************************************************//**
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| 2 | * @file core_ca9.h
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| 3 | * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
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| 4 | * @version
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| 5 | * @date 25 March 2013
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| 6 | *
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| 7 | * @note
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| 8 | *
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| 9 | ******************************************************************************/
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| 10 | /* Copyright (c) 2009 - 2012 ARM LIMITED
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| 11 |
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| 12 | All rights reserved.
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| 13 | Redistribution and use in source and binary forms, with or without
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| 14 | modification, are permitted provided that the following conditions are met:
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| 15 | - Redistributions of source code must retain the above copyright
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| 16 | notice, this list of conditions and the following disclaimer.
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| 17 | - Redistributions in binary form must reproduce the above copyright
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| 18 | notice, this list of conditions and the following disclaimer in the
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| 19 | documentation and/or other materials provided with the distribution.
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| 20 | - Neither the name of ARM nor the names of its contributors may be used
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| 21 | to endorse or promote products derived from this software without
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| 22 | specific prior written permission.
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| 23 | *
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| 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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| 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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| 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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| 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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| 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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| 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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| 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 34 | POSSIBILITY OF SUCH DAMAGE.
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| 35 | ---------------------------------------------------------------------------*/
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| 36 |
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| 37 |
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| 38 | #if defined ( __ICCARM__ )
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| 39 | #pragma system_include /* treat file as system include file for MISRA check */
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| 40 | #endif
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| 41 |
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| 42 | #ifdef __cplusplus
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| 43 | extern "C" {
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| 44 | #endif
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| 45 |
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| 46 | #ifndef __CORE_CA9_H_GENERIC
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| 47 | #define __CORE_CA9_H_GENERIC
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| 48 |
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| 49 |
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| 50 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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| 51 | CMSIS violates the following MISRA-C:2004 rules:
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| 52 |
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| 53 | \li Required Rule 8.5, object/function definition in header file.<br>
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| 54 | Function definitions in header files are used to allow 'inlining'.
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| 55 |
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| 56 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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| 57 | Unions are used for effective representation of core registers.
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| 58 |
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| 59 | \li Advisory Rule 19.7, Function-like macro defined.<br>
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| 60 | Function-like macros are used to allow more efficient code.
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| 61 | */
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| 62 |
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| 63 |
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| 64 | /*******************************************************************************
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| 65 | * CMSIS definitions
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| 66 | ******************************************************************************/
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| 67 | /** \ingroup Cortex_A9
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| 68 | @{
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| 69 | */
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| 70 |
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| 71 | /* CMSIS CA9 definitions */
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| 72 | #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
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| 73 | #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
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| 74 | #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
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| 75 | __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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| 76 |
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| 77 | #define __CORTEX_A (0x09) /*!< Cortex-A Core */
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| 78 |
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| 79 |
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| 80 | #if defined ( __CC_ARM )
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| 81 | #define __ASM __asm /*!< asm keyword for ARM Compiler */
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| 82 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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| 83 | #define __STATIC_INLINE static __inline
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| 84 | #define __STATIC_ASM static __asm
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| 85 |
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| 86 | #elif defined ( __ICCARM__ )
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| 87 | #define __ASM __asm /*!< asm keyword for IAR Compiler */
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| 88 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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| 89 | #define __STATIC_INLINE static inline
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| 90 | #define __STATIC_ASM static __asm
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| 91 |
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| 92 | #elif defined ( __TMS470__ )
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| 93 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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| 94 | #define __STATIC_INLINE static inline
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| 95 | #define __STATIC_ASM static __asm
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| 96 |
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| 97 | #elif defined ( __GNUC__ )
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| 98 | #define __ASM __asm /*!< asm keyword for GNU Compiler */
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| 99 | #define __INLINE inline /*!< inline keyword for GNU Compiler */
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| 100 | #define __STATIC_INLINE static inline
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| 101 | #define __STATIC_ASM static __asm
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| 102 |
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| 103 | #elif defined ( __TASKING__ )
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| 104 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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| 105 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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| 106 | #define __STATIC_INLINE static inline
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| 107 | #define __STATIC_ASM static __asm
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| 108 |
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| 109 | #endif
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| 110 |
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| 111 | /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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| 112 | */
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| 113 | #if defined ( __CC_ARM )
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| 114 | #if defined __TARGET_FPU_VFP
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| 115 | #if (__FPU_PRESENT == 1)
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| 116 | #define __FPU_USED 1
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| 117 | #else
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| 118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 119 | #define __FPU_USED 0
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| 120 | #endif
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| 121 | #else
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| 122 | #define __FPU_USED 0
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| 123 | #endif
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| 124 |
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| 125 | #elif defined ( __ICCARM__ )
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| 126 | #if defined __ARMVFP__
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| 127 | #if (__FPU_PRESENT == 1)
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| 128 | #define __FPU_USED 1
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| 129 | #else
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| 130 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 131 | #define __FPU_USED 0
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| 132 | #endif
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| 133 | #else
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| 134 | #define __FPU_USED 0
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| 135 | #endif
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| 136 |
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| 137 | #elif defined ( __TMS470__ )
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| 138 | #if defined __TI_VFP_SUPPORT__
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| 139 | #if (__FPU_PRESENT == 1)
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| 140 | #define __FPU_USED 1
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| 141 | #else
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| 142 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 143 | #define __FPU_USED 0
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| 144 | #endif
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| 145 | #else
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| 146 | #define __FPU_USED 0
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| 147 | #endif
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| 148 |
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| 149 | #elif defined ( __GNUC__ )
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| 150 | #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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| 151 | #if (__FPU_PRESENT == 1)
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| 152 | #define __FPU_USED 1
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| 153 | #else
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| 154 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 155 | #define __FPU_USED 0
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| 156 | #endif
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| 157 | #else
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| 158 | #define __FPU_USED 0
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| 159 | #endif
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| 160 |
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| 161 | #elif defined ( __TASKING__ )
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| 162 | #if defined __FPU_VFP__
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| 163 | #if (__FPU_PRESENT == 1)
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| 164 | #define __FPU_USED 1
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| 165 | #else
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| 166 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 167 | #define __FPU_USED 0
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| 168 | #endif
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| 169 | #else
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| 170 | #define __FPU_USED 0
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| 171 | #endif
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| 172 | #endif
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| 173 |
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| 174 | #include <stdint.h> /*!< standard types definitions */
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| 175 | #include "core_caInstr.h" /*!< Core Instruction Access */
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| 176 | #include "core_caFunc.h" /*!< Core Function Access */
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| 177 | #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
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| 178 |
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| 179 | #endif /* __CORE_CA9_H_GENERIC */
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| 180 |
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| 181 | #ifndef __CMSIS_GENERIC
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| 182 |
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| 183 | #ifndef __CORE_CA9_H_DEPENDANT
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| 184 | #define __CORE_CA9_H_DEPENDANT
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| 185 |
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| 186 | /* check device defines and use defaults */
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| 187 | #if defined __CHECK_DEVICE_DEFINES
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| 188 | #ifndef __CA9_REV
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| 189 | #define __CA9_REV 0x0000
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| 190 | #warning "__CA9_REV not defined in device header file; using default!"
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| 191 | #endif
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| 192 |
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| 193 | #ifndef __FPU_PRESENT
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| 194 | #define __FPU_PRESENT 1
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| 195 | #warning "__FPU_PRESENT not defined in device header file; using default!"
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| 196 | #endif
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| 197 |
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| 198 | #ifndef __Vendor_SysTickConfig
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| 199 | #define __Vendor_SysTickConfig 1
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| 200 | #endif
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| 201 |
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| 202 | #if __Vendor_SysTickConfig == 0
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| 203 | #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
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| 204 | #endif
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| 205 | #endif
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| 206 |
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| 207 | /* IO definitions (access restrictions to peripheral registers) */
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| 208 | /**
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| 209 | \defgroup CMSIS_glob_defs CMSIS Global Defines
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| 210 |
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| 211 | <strong>IO Type Qualifiers</strong> are used
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| 212 | \li to specify the access to peripheral variables.
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| 213 | \li for automatic generation of peripheral register debug information.
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| 214 | */
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| 215 | #ifdef __cplusplus
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| 216 | #define __I volatile /*!< Defines 'read only' permissions */
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| 217 | #else
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| 218 | #define __I volatile const /*!< Defines 'read only' permissions */
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| 219 | #endif
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| 220 | #define __O volatile /*!< Defines 'write only' permissions */
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| 221 | #define __IO volatile /*!< Defines 'read / write' permissions */
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| 222 |
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| 223 | /*@} end of group Cortex_A9 */
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| 224 |
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| 225 |
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| 226 | /*******************************************************************************
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| 227 | * Register Abstraction
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| 228 | ******************************************************************************/
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| 229 | /** \defgroup CMSIS_core_register Defines and Type Definitions
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| 230 | \brief Type definitions and defines for Cortex-A processor based devices.
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| 231 | */
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| 232 |
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| 233 | /** \ingroup CMSIS_core_register
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| 234 | \defgroup CMSIS_CORE Status and Control Registers
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| 235 | \brief Core Register type definitions.
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| 236 | @{
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| 237 | */
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| 238 |
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| 239 | /** \brief Union type to access the Application Program Status Register (APSR).
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| 240 | */
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| 241 | typedef union
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| 242 | {
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| 243 | struct
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| 244 | {
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| 245 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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| 246 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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| 247 | uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
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| 248 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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| 249 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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| 250 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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| 251 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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| 252 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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| 253 | } b; /*!< Structure used for bit access */
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| 254 | uint32_t w; /*!< Type used for word access */
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| 255 | } APSR_Type;
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| 256 |
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| 257 |
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| 258 | /*@} end of group CMSIS_CORE */
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| 259 |
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| 260 | /*@} end of CMSIS_Core_FPUFunctions */
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| 261 |
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| 262 |
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| 263 | #endif /* __CORE_CA9_H_GENERIC */
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| 264 |
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| 265 | #endif /* __CMSIS_GENERIC */
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| 266 |
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| 267 | #ifdef __cplusplus
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| 268 | }
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| 269 |
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| 270 |
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| 271 | #endif
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