SYSTEM std_2s180
{
System_Wizard_Version = "6.10";
System_Wizard_Build = "201";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "STRATIXII";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "0";
hdl_language = "vhdl";
view_master_columns = "1";
view_master_priorities = "0";
board_class = "altera_dsp_dev_board_stratix_2s180";
name_column_width = "253";
desc_column_width = "254";
bustype_column_width = "0";
base_column_width = "75";
end_column_width = "75";
view_frame_window = "140:131:1120:787";
do_log_history = "0";
device_family_id = "STRATIXII";
CLOCKS
{
CLOCK clk
{
frequency = "50000000";
source = "External";
Is_Clock_Source = "0";
display_name = "clk";
pipeline = "0";
}
}
clock_column_width = "75";
hardcopy_compatible = "0";
BOARD_INFO
{
CONFIGURATION factory
{
length = "";
menu_position = "1";
offset = "0x00200000";
reference_designator = "U17";
}
CONFIGURATION page0
{
length = "";
menu_position = "2";
offset = "0x00900000";
reference_designator = "U17";
}
JTAG_device_index = "1";
REFDES U17
{
base = "0x01000000";
}
altera_avalon_cfi_flash
{
reference_designators = "U17";
}
class = "altera_dsp_dev_board_stratix_2s180";
class_version = "1.0";
device_family = "STRATIXII";
quartus_pgm_file = "system/altera_dsp_dev_board_stratix_2s180.sof";
quartus_project_file = "system/altera_dsp_dev_board_stratix_2s180.qpf";
reference_designators = "U17";
sopc_system_file = "system/altera_dsp_dev_board_stratix_2s180.ptf";
}
}
MODULE cpu
{
class = "altera_nios2";
class_version = "6.05";
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.vhd, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu.vhd";
Synthesis_Only_Files = "";
}
MASTER instruction_master
{
PORT_WIRING
{
PORT i_address
{
direction = "output";
type = "address";
width = "28";
Is_Enabled = "1";
}
PORT i_read
{
direction = "output";
type = "read";
width = "1";
Is_Enabled = "1";
}
PORT i_readdata
{
direction = "input";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT i_readdatavalid
{
direction = "input";
type = "readdatavalid";
width = "1";
Is_Enabled = "1";
}
PORT i_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
Is_Readable = "1";
Is_Writeable = "0";
Address_Group = "0";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Linewrap_Bursts = "";
Interleave_Bursts = "";
Is_Big_Endian = "0";
}
}
MASTER data_master
{
PORT_WIRING
{
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "0";
}
PORT d_address
{
direction = "output";
type = "address";
width = "28";
Is_Enabled = "1";
}
PORT d_byteenable
{
direction = "output";
type = "byteenable";
width = "4";
Is_Enabled = "1";
}
PORT d_irq
{
direction = "input";
type = "irq";
width = "32";
Is_Enabled = "1";
}
PORT d_read
{
direction = "output";
type = "read";
width = "1";
Is_Enabled = "1";
}
PORT d_readdata
{
direction = "input";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT d_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
Is_Enabled = "1";
}
PORT d_write
{
direction = "output";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT d_writedata
{
direction = "output";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess_to_roms
{
direction = "output";
type = "debugaccess";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Is_Big_Endian = "0";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
PORT jtag_debug_module_address
{
direction = "input";
type = "address";
width = "9";
Is_Enabled = "1";
}
PORT jtag_debug_module_begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess
{
direction = "input";
type = "debugaccess";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT jtag_debug_module_reset
{
direction = "input";
type = "reset";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_resetrequest
{
direction = "output";
type = "resetrequest";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_select
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_write
{
direction = "input";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_writedata
{
direction = "input";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "0";
}
PORT jtag_debug_module_byteenable
{
direction = "input";
type = "byteenable";
width = "4";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "0x08010000";
Is_Memory_Device = "1";
Is_Printable_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "1118278";
JTAG_Hub_Instance_Id = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "1";
Is_Writeable = "1";
Is_Big_Endian = "0";
Address_Group = "0";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
CPU_Architecture = "nios2";
do_generate = "1";
cpu_selection = "s";
CPU_Implementation = "small";
cache_has_dcache = "0";
cache_has_icache = "1";
cache_dcache_size = "2048";
cache_icache_size = "4096";
include_debug = "0";
include_trace = "0";
include_oci = "1";
debug_level = "2";
oci_offchip_trace = "0";
oci_onchip_trace = "0";
oci_data_trace = "0";
oci_trace_addr_width = "7";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_num_pm = "0";
oci_pm_width = "40";
oci_debugreq_signals = "0";
oci_instance_number = "1";
hardware_multiply_present = "1";
hardware_divide_present = "0";
bht_ptr_sz = "8";
reset_slave = "ext_flash/s1";
reset_offset = "0x00000000";
exc_slave = "sdram/s1";
exc_offset = "0x00000020";
break_slave = "cpu/jtag_debug_module";
break_offset = "0x00000020";
altera_internal_test = "0";
full_waveform_signals = "0";
activate_model_checker = "0";
activate_monitors_and_trace = "0";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
always_encrypt = "1";
consistent_synthesis = "0";
ibuf_ptr_sz = "4";
jtb_ptr_sz = "5";
performance_counters_present = "0";
performance_counters_width = "32";
ras_ptr_sz = "4";
inst_decode_in_submodule = "0";
register_dependency_in_submodule = "0";
source_operands_in_submodule = "0";
alu_in_submodule = "0";
stdata_in_submodule = "0";
shift_rot_2N_in_submodule = "0";
control_regs_in_submodule = "0";
mult_cell_in_submodule = "0";
M_inst_result_mux_in_submodule = "0";
dcache_load_aligner_in_submodule = "0";
hardware_divide_in_submodule = "0";
mult_result_mux_in_submodule = "0";
shift_rotate_in_submodule = "0";
register_file_write_data_mux_in_submodule = "0";
avalon_imaster_in_submodule = "0";
avalon_dmaster_in_submodule = "0";
avalon_load_aligner_in_submodule = "0";
hbreak_test = "0";
iss_trace_on = "0";
iss_trace_warning = "1";
iss_trace_info = "1";
iss_trace_disassembly = "0";
iss_trace_registers = "0";
iss_trace_instr_count = "0";
iss_software_debug = "0";
iss_software_debug_port = "9996";
iss_memory_dump_start = "";
iss_memory_dump_end = "";
Boot_Copier = "boot_loader_cfi.srec";
Boot_Copier_EPCS = "boot_loader_epcs.srec";
CONSTANTS
{
CONSTANT __nios_catch_irqs__
{
value = "1";
comment = "Include panic handler for all irqs (needs uart)";
}
CONSTANT __nios_use_constructors__
{
value = "1";
comment = "Call c++ static constructors";
}
CONSTANT __nios_use_small_printf__
{
value = "1";
comment = "Smaller non-ANSI printf, with no floating point";
}
CONSTANT nasys_has_icache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_icache_size
{
value = "4096";
comment = "Size in bytes of instruction cache";
}
CONSTANT nasys_icache_line_size
{
value = "32";
comment = "Size in bytes of each icache line";
}
CONSTANT nasys_icache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each icache line";
}
CONSTANT nasys_has_dcache
{
value = "0";
comment = "True if instruction cache present";
}
CONSTANT nasys_dcache_size
{
value = "2048";
comment = "Size in bytes of data cache";
}
CONSTANT nasys_dcache_line_size
{
value = "4";
comment = "Size in bytes of each dcache line";
}
CONSTANT nasys_dcache_line_size_log2
{
value = "2";
comment = "Log2 size in bytes of each dcache line";
}
}
mainmem_slave = "sdram/s1";
datamem_slave = "sdram/s1";
maincomm_slave = "uart1/s1";
debugcomm_slave = "uart1/s1";
germs_monitor_id = "";
asp_debug = "0";
asp_core_debug = "0";
legacy_sdk_support = "0";
hdl_sim_caches_cleared = "1";
allow_full_address_range = "0";
break_slave_override = "";
break_offset_override = "0x20";
remove_hardware_multiplier = "0";
activate_trace = "1";
activate_monitors = "1";
activate_test_end_checker = "0";
clear_x_bits_ld_non_bypass = "1";
oci_trigger_arming = "1";
illegal_instructions_trap = "0";
include_third_party_debug_port = "0";
hardware_multiply_uses_les = "0";
hardware_multiply_omits_msw = "0";
hardware_multiply_implementation = "0";
hardware_multiply_implementation_dsp_blocks = "0";
hardware_multiply_implementation_embedded_mults = "1";
hardware_multiply_implementation_les = "2";
altera_show_unreleased_features = "0";
cache_omit_dcache = "0";
cache_omit_icache = "0";
omit_instruction_master = "0";
omit_data_master = "0";
num_data_channel_masters = "0";
num_instruction_channel_masters = "0";
gui_branch_prediction_type = "Automatic";
branch_prediction_type = "Static";
bht_index_pc_only = "0";
cpuid_sz = "1";
cpuid_value = "0";
gui_hardware_multiply_setting = "dsp_mul_dsp_shift";
hardware_multiply_impl = "dsp_mul";
num_tightly_coupled_data_masters = "0";
num_tightly_coupled_instruction_masters = "0";
shift_rot_impl = "dsp_shift";
gui_include_tightly_coupled_instruction_masters = "0";
gui_num_tightly_coupled_instruction_masters = "1";
gui_omit_avalon_data_master = "0";
gui_include_tightly_coupled_data_masters = "0";
gui_num_tightly_coupled_data_masters = "1";
cache_dcache_line_size = "4";
cache_icache_line_size = "32";
cache_dcache_bursts = "0";
cache_icache_burst_type = "none";
cache_dcache_ram_block_type = "AUTO";
cache_icache_ram_block_type = "AUTO";
oci_embedded_pll = "1";
gui_hardware_divide_setting = "0";
mmu_present = "0";
process_id_num_bits = "10";
dtlb_ptr_sz = "7";
dtlb_num_ways = "4";
udtlb_num_entries = "6";
itlb_ptr_sz = "7";
itlb_num_ways = "4";
uitlb_num_entries = "4";
fast_tlb_miss_exc_slave = "";
fast_tlb_miss_exc_offset = "0x0";
license_status = "encrypted";
cpu_reset = "0";
export_pcb = "0";
big_endian = "0";
altera_show_unpublished_features = "0";
alt_log_port_base = "";
alt_log_port_type = "";
gui_illegal_instructions_trap = "0";
gui_illegal_memory_access_detection = "0";
illegal_memory_access_detection = "0";
gui_mmu_present = "0";
debug_simgen = "0";
allow_legacy_sdk = "0";
Boot_Copier_EPCS_Stratix_II = "boot_loader_epcs_stratix_ii.srec";
Boot_Copier_BE = "boot_loader_cfi_be.srec";
Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
Boot_Copier_EPCS_Stratix_II_BE = "boot_loader_epcs_stratix_ii_be.srec";
dont_overwrite_cpuid = "0";
}
SYSTEM_BUILDER_INFO
{
Parameters_Signature = "";
Is_CPU = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Default_Module_Name = "cpu";
View
{
MESSAGES
{
}
Is_Collapsed = "0";
Settings_Summary = "Nios II/s
4-Kbyte Instruction Cache
JTAG Debug Module
";
}
Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIII,CYCLONE,CYCLONEII";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SOFTWARE_COMPONENT altera_hal
{
class = "altera_hal";
class_version = "1.0";
WIZARD_SCRIPT_ARGUMENTS
{
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
SOFTWARE_COMPONENT altera_nios2_test
{
class = "altera_nios2_test";
class_version = "2.0";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT debug_on
{
value = "0";
comment = "Enable debug features";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "0";
}
}
SOFTWARE_COMPONENT altera_plugs_library
{
class = "altera_plugs_library";
class_version = "2.1";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT PLUGS_PLUG_COUNT
{
value = "5";
comment = "Maximum number of plugs";
}
CONSTANT PLUGS_ADAPTER_COUNT
{
value = "2";
comment = "Maximum number of adapters";
}
CONSTANT PLUGS_DNS
{
value = "1";
comment = "Have routines for DNS lookups";
}
CONSTANT PLUGS_PING
{
value = "1";
comment = "Respond to icmp echo (ping) messages";
}
CONSTANT PLUGS_TCP
{
value = "1";
comment = "Support tcp in/out connections";
}
CONSTANT PLUGS_IRQ
{
value = "1";
comment = "Run at interrupte level";
}
CONSTANT PLUGS_DEBUG
{
value = "1";
comment = "Support debug routines";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
PORT_WIRING
{
PORT jtag_debug_trigout
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_clk
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_data
{
width = "18";
direction = "output";
Is_Enabled = "0";
}
PORT clkx2
{
width = "1";
direction = "input";
Is_Enabled = "0";
visible = "0";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL aaa
{
format = "Logic";
name = "i_readdata";
radix = "hexadecimal";
}
SIGNAL aab
{
format = "Logic";
name = "i_readdatavalid";
radix = "hexadecimal";
}
SIGNAL aac
{
format = "Logic";
name = "i_waitrequest";
radix = "hexadecimal";
}
SIGNAL aad
{
format = "Logic";
name = "i_address";
radix = "hexadecimal";
}
SIGNAL aae
{
format = "Logic";
name = "i_read";
radix = "hexadecimal";
}
SIGNAL aaf
{
format = "Logic";
name = "E_ci_combo_dataa";
radix = "hexadecimal";
}
SIGNAL aag
{
format = "Logic";
name = "E_ci_combo_datab";
radix = "hexadecimal";
}
SIGNAL aah
{
format = "Logic";
name = "E_ci_combo_ipending";
radix = "hexadecimal";
}
SIGNAL aai
{
format = "Logic";
name = "E_ci_combo_status";
radix = "hexadecimal";
}
SIGNAL aaj
{
format = "Logic";
name = "E_ci_combo_estatus";
radix = "hexadecimal";
}
SIGNAL aak
{
format = "Logic";
name = "E_ci_combo_n";
radix = "hexadecimal";
}
SIGNAL aal
{
format = "Logic";
name = "E_ci_combo_a";
radix = "hexadecimal";
}
SIGNAL aam
{
format = "Logic";
name = "E_ci_combo_b";
radix = "hexadecimal";
}
SIGNAL aan
{
format = "Logic";
name = "E_ci_combo_c";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Logic";
name = "E_ci_combo_readra";
radix = "hexadecimal";
}
SIGNAL aap
{
format = "Logic";
name = "E_ci_combo_readrb";
radix = "hexadecimal";
}
SIGNAL aaq
{
format = "Logic";
name = "E_ci_combo_writerc";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "E_ci_combo_result";
radix = "hexadecimal";
}
SIGNAL aas
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aat
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aau
{
format = "Logic";
name = "d_readdata";
radix = "hexadecimal";
}
SIGNAL aav
{
format = "Logic";
name = "d_waitrequest";
radix = "hexadecimal";
}
SIGNAL aaw
{
format = "Logic";
name = "d_irq";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "d_address";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "d_byteenable";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "d_read";
radix = "hexadecimal";
}
SIGNAL aba
{
format = "Logic";
name = "d_write";
radix = "hexadecimal";
}
SIGNAL abb
{
format = "Logic";
name = "d_writedata";
radix = "hexadecimal";
}
SIGNAL abc
{
format = "Divider";
name = "base pipeline";
radix = "";
}
SIGNAL abd
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL abe
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "M_stall";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Logic";
name = "F_pcb_nxt";
radix = "hexadecimal";
}
SIGNAL abh
{
format = "Logic";
name = "F_pcb";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "D_pcb";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "E_pcb";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "M_pcb";
radix = "hexadecimal";
}
SIGNAL abl
{
format = "Logic";
name = "W_pcb";
radix = "hexadecimal";
}
SIGNAL abm
{
format = "Logic";
name = "F_vinst";
radix = "ascii";
}
SIGNAL abn
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL abo
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL abp
{
format = "Logic";
name = "M_vinst";
radix = "ascii";
}
SIGNAL abq
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL abr
{
format = "Logic";
name = "F_inst_ram_hit";
radix = "hexadecimal";
}
SIGNAL abs
{
format = "Logic";
name = "F_issue";
radix = "hexadecimal";
}
SIGNAL abt
{
format = "Logic";
name = "F_kill";
radix = "hexadecimal";
}
SIGNAL abu
{
format = "Logic";
name = "D_kill";
radix = "hexadecimal";
}
SIGNAL abv
{
format = "Logic";
name = "D_refetch";
radix = "hexadecimal";
}
SIGNAL abw
{
format = "Logic";
name = "D_issue";
radix = "hexadecimal";
}
SIGNAL abx
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL aby
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL abz
{
format = "Logic";
name = "M_valid";
radix = "hexadecimal";
}
SIGNAL aca
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL acb
{
format = "Logic";
name = "W_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL acc
{
format = "Logic";
name = "W_dst_regnum";
radix = "hexadecimal";
}
SIGNAL acd
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL ace
{
format = "Logic";
name = "F_en";
radix = "hexadecimal";
}
SIGNAL acf
{
format = "Logic";
name = "D_en";
radix = "hexadecimal";
}
SIGNAL acg
{
format = "Logic";
name = "E_en";
radix = "hexadecimal";
}
SIGNAL ach
{
format = "Logic";
name = "M_en";
radix = "hexadecimal";
}
SIGNAL aci
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL acj
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL ack
{
format = "Logic";
name = "E_iw";
radix = "hexadecimal";
}
SIGNAL acl
{
format = "Logic";
name = "E_valid_prior_to_hbreak";
radix = "hexadecimal";
}
SIGNAL acm
{
format = "Logic";
name = "M_pipe_flush_nxt";
radix = "hexadecimal";
}
SIGNAL acn
{
format = "Logic";
name = "M_pipe_flush_baddr_nxt";
radix = "hexadecimal";
}
SIGNAL aco
{
format = "Logic";
name = "M_status_reg_pie";
radix = "hexadecimal";
}
SIGNAL acp
{
format = "Logic";
name = "M_ienable_reg";
radix = "hexadecimal";
}
SIGNAL acq
{
format = "Logic";
name = "intr_req";
radix = "hexadecimal";
}
SIGNAL acr
{
format = "Divider";
name = "combinatorial_custom_instruction";
radix = "";
}
SIGNAL acs
{
format = "Logic";
name = "E_ctrl_custom_combo";
radix = "hexadecimal";
}
SIGNAL act
{
format = "Logic";
name = "E_ci_combo_dataa";
radix = "hexadecimal";
}
SIGNAL acu
{
format = "Logic";
name = "E_ci_combo_datab";
radix = "hexadecimal";
}
SIGNAL acv
{
format = "Logic";
name = "E_ci_combo_ipending";
radix = "hexadecimal";
}
SIGNAL acw
{
format = "Logic";
name = "E_ci_combo_status";
radix = "hexadecimal";
}
SIGNAL acx
{
format = "Logic";
name = "E_ci_combo_estatus";
radix = "hexadecimal";
}
SIGNAL acy
{
format = "Logic";
name = "E_ci_combo_n";
radix = "hexadecimal";
}
SIGNAL acz
{
format = "Logic";
name = "E_ci_combo_readra";
radix = "hexadecimal";
}
SIGNAL ada
{
format = "Logic";
name = "E_ci_combo_readrb";
radix = "hexadecimal";
}
SIGNAL adb
{
format = "Logic";
name = "E_ci_combo_writerc";
radix = "hexadecimal";
}
SIGNAL adc
{
format = "Logic";
name = "E_ci_combo_result";
radix = "hexadecimal";
}
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
PORT E_ci_combo_a
{
Is_Enabled = "1";
direction = "output";
type = "combo_a";
width = "5";
}
PORT E_ci_combo_b
{
Is_Enabled = "1";
direction = "output";
type = "combo_b";
width = "5";
}
PORT E_ci_combo_c
{
Is_Enabled = "1";
direction = "output";
type = "combo_c";
width = "5";
}
PORT E_ci_combo_dataa
{
Is_Enabled = "1";
direction = "output";
type = "combo_dataa";
width = "32";
}
PORT E_ci_combo_datab
{
Is_Enabled = "1";
direction = "output";
type = "combo_datab";
width = "32";
}
PORT E_ci_combo_estatus
{
Is_Enabled = "1";
direction = "output";
type = "combo_estatus";
width = "1";
}
PORT E_ci_combo_ipending
{
Is_Enabled = "1";
direction = "output";
type = "combo_ipending";
width = "32";
}
PORT E_ci_combo_n
{
Is_Enabled = "1";
direction = "output";
type = "combo_n";
width = "8";
}
PORT E_ci_combo_readra
{
Is_Enabled = "1";
direction = "output";
type = "combo_readra";
width = "1";
}
PORT E_ci_combo_readrb
{
Is_Enabled = "1";
direction = "output";
type = "combo_readrb";
width = "1";
}
PORT E_ci_combo_result
{
Is_Enabled = "1";
direction = "input";
type = "combo_result";
width = "32";
}
PORT E_ci_combo_status
{
Is_Enabled = "1";
direction = "output";
type = "combo_status";
width = "1";
}
PORT E_ci_combo_writerc
{
Is_Enabled = "1";
direction = "output";
type = "combo_writerc";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "1";
}
}
MASTER data_master2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Is_Big_Endian = "0";
}
}
MASTER data_channel_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER data_channel_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER data_channel_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER data_channel_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER instruction_channel_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_data_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_data_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Is_Big_Endian = "0";
}
}
}
MODULE button_pio
{
class = "altera_avalon_pio";
class_version = "6.05";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
width = "4";
test_bench_value = "15";
Is_Enabled = "1";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "4";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "4";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "4";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "4";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "1";
Address_Width = "2";
Data_Width = "4";
Base_Address = "0x08010830";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "5";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Settings_Summary = " 4-bit PIO using
input pins with edge type ANY and interrupt source EDGE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "1";
edge_type = "ANY";
irq_type = "EDGE";
Do_Test_Bench_Wiring = "1";
Driven_Sim_Value = "0x000F";
}
}
MODULE ext_flash
{
class = "altera_avalon_cfi_flash";
class_version = "6.05";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "24";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
flash_reference_designator = "U17";
Supports_Flash_File_System = "1";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "24";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "45ns";
Hold_Time = "35ns";
Is_Base_Locked = "1";
Simulation_Num_Lanes = "1";
Is_Nonvolatile_Storage = "1";
Address_Span = "16777216";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Convert_Xs_To_0 = "1";
MASTERED_BY ext_flash_bus/tristate_master
{
priority = "1";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Make_Memory_Model = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "45";
Wait_Value = "160";
Hold_Value = "35";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "16777216";
MAKE
{
TARGET flashfiles
{
ext_flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Dependency = "$(ELF)";
Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Command2 = "elf2flash --input=$(ELF) --flash=U17 --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0xFFFFFF --reset=$(CPU_RESET_ADDRESS) ";
}
}
MACRO
{
EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET delete_placeholder_warning
{
ext_flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
ext_flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "";
}
}
MODULE ext_flash_bus
{
class = "altera_avalon_tri_state_bridge";
class_version = "6.05";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "0";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
}
}
MODULE ext_ram
{
class = "altera_nios_dev_kit_stratix_edition_sram2";
class_version = "6.05";
iss_model_name = "altera_memory";
HDL_INFO
{
}
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "1024";
sram_memory_units = "1024";
sram_data_width = "32";
MAKE
{
TARGET delete_placeholder_warning
{
ext_ram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
ext_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "";
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "32";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "18";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT be_n
{
width = "4";
is_shared = "0";
direction = "input";
type = "byteenable_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "32";
Address_Width = "18";
Has_IRQ = "0";
Read_Wait_States = "0ns";
Write_Wait_States = "0ns";
Hold_Time = "half";
Base_Address = "0x09000000";
Address_Span = "1048576";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
Setup_Time = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "0";
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "1";
Default_Module_Name = "sram";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
}
MODULE ext_ram_bus
{
class = "altera_avalon_tri_state_bridge";
class_version = "6.05";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
MASTERED_BY vga_16_bit/image_dma_master
{
priority = "1";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "0";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
}
}
MODULE high_res_timer
{
class = "altera_avalon_timer";
class_version = "6.05";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
Base_Address = "0x08010860";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "4";
}
Address_Group = "0";
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
Is_Enabled = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
View
{
Settings_Summary = "Timer with 1 ms timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "1";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/high_res_timer.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE jtag_uart
{
class = "altera_avalon_jtag_uart";
class_version = "6.05";
iss_model_name = "altera_avalon_jtag_uart";
SLAVE avalon_jtag_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "1";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
JTAG_Hub_Base_Id = "0x04006E";
JTAG_Hub_Instance_Id = "1";
Base_Address = "0x08010820";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "2";
}
Connection_Limit = "1";
Address_Group = "0";
}
PORT_WIRING
{
PORT clk
{
type = "clk";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
direction = "input";
width = "32";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT av_irq
{
type = "irq";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
Is_Enabled = "1";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
Is_Enabled = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
View
{
Settings_Summary = "
Write Depth: 64; Write IRQ Threshold: 8
Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "0";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
radix = "hexadecimal";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
radix = "hexadecimal";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
radix = "hexadecimal";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
radix = "hexadecimal";
}
SIGNAL av_irq
{
name = "av_irq";
radix = "hexadecimal";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE lan91c111
{
class = "altera_avalon_lan91c111";
class_version = "6.05";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT LAN91C111_REGISTERS_OFFSET
{
value = "0x0300";
comment = "offset 0 or 0x300, depending on address bus wiring";
}
CONSTANT LAN91C111_DATA_BUS_WIDTH
{
value = "32";
comment = "width 16 or 32, depending on data bus wiring";
}
}
Is_Ethernet_Mac = "1";
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Wire_Test_Bench_Values = "1";
Is_Enabled = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Is_Enabled = "1";
Is_Bus_Master = "0";
Bus_Type = "avalon_tristate";
Uses_Tri_State_Data_Bus = "1";
Address_Alignment = "native";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "20ns";
Write_Wait_States = "20ns";
Setup_Time = "20ns";
Hold_Time = "20ns";
Is_Memory_Device = "0";
Date_Modified = "2002.03.19.10:51:51";
Base_Address = "0x08000000";
Tri_State_Data_Bus = "--unknown--";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "0";
}
Address_Group = "0";
}
PORT_WIRING
{
PORT irq
{
direction = "output";
width = "1";
type = "irq";
test_bench_value = "0";
}
PORT byteenablen
{
is_shared = "1";
direction = "input";
width = "4";
type = "byteenable_n";
}
PORT address
{
is_shared = "1";
direction = "input";
width = "14";
type = "address";
}
PORT data
{
is_shared = "1";
direction = "inout";
width = "32";
type = "data";
}
PORT iow_n
{
direction = "input";
width = "1";
type = "write_n";
}
PORT ior_n
{
direction = "input";
width = "1";
type = "read_n";
}
PORT reset_n
{
direction = "input";
width = "1";
type = "reset_n";
Is_Enabled = "0";
}
PORT reset
{
direction = "input";
width = "1";
type = "reset";
}
PORT ardy
{
direction = "output";
width = "1";
type = "inhibitrequest_n";
Is_Enabled = "0";
}
}
}
}
MODULE lcd_display
{
class = "altera_avalon_lcd_16207";
class_version = "6.05";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd_display.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT LCD_E
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT LCD_RS
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT LCD_RW
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT LCD_data
{
direction = "inout";
width = "8";
Is_Enabled = "1";
}
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
Is_Enabled = "1";
}
PORT begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT read
{
direction = "input";
type = "read";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "8";
Is_Enabled = "1";
}
PORT write
{
direction = "input";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "8";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Is_Printable_Device = "1";
Address_Width = "2";
Data_Width = "8";
Base_Address = "0x080108B0";
Address_Alignment = "native";
Read_Wait_States = "250ns";
Write_Wait_States = "250ns";
Setup_Time = "250ns";
Hold_Time = "250ns";
Read_Latency = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
}
}
MODULE led_pio
{
class = "altera_avalon_pio";
class_version = "6.05";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT out_port
{
direction = "output";
width = "8";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "4";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "4";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "8";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "8";
Base_Address = "0x08010880";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Settings_Summary = " 8-bit PIO using
output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
}
}
MODULE onchip_ram_64_kbytes
{
class = "altera_avalon_onchip_memory2";
class_version = "6.05";
iss_model_name = "altera_memory";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_ram_64_kbytes.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
gui_ram_block_type = "M4K";
Writeable = "1";
dual_port = "0";
Size_Value = "64";
Size_Multiple = "1024";
contents_info = "QUARTUS_PROJECT_DIR/onchip_ram_64_kbytes.hex 1194955072 ";
MAKE
{
TARGET delete_placeholder_warning
{
onchip_ram_64_kbytes
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
onchip_ram_64_kbytes
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x02100000 0x210FFFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_ram_64_kbytes.hex --create-lanes=0 ";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_ram_64_kbytes.hex";
}
}
TARGET sim
{
onchip_ram_64_kbytes
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
init_contents_file = "onchip_ram_64_kbytes";
non_default_init_file_enabled = "0";
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "14";
Is_Enabled = "1";
}
PORT byteenable
{
direction = "input";
type = "byteenable";
width = "4";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT write
{
direction = "input";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT clken
{
default_value = "1'b1";
direction = "input";
type = "clken";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "65536";
Read_Latency = "1";
Base_Address = "0x02100000";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
Is_Channel = "1";
Is_Writable = "1";
Address_Group = "0";
}
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "65536";
Read_Latency = "1";
Is_Enabled = "0";
Is_Channel = "1";
Is_Writable = "1";
Address_Group = "0";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
PORT_WIRING
{
}
}
MODULE reconfig_request_pio
{
class = "altera_avalon_pio";
class_version = "6.05";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/reconfig_request_pio.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT bidir_port
{
direction = "inout";
width = "1";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "4";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "4";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "1";
Base_Address = "0x080108A0";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Settings_Summary = " 1-bit PIO using
tri-state pins with edge type NONE and interrupt source NONE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
has_tri = "1";
has_out = "0";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
}
}
MODULE sdram
{
class = "altera_avalon_new_sdram_controller";
class_version = "6.05";
iss_model_name = "altera_memory";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Maximum_Pending_Read_Transactions = "6";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Is_Memory_Device = "1";
Address_Width = "22";
Data_Width = "64";
Simulation_Num_Lanes = "1";
Base_Address = "0x0A000000";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "0";
Address_Group = "0";
MASTERED_BY vga_16_bit/image_dma_master
{
priority = "1";
}
}
PORT_WIRING
{
PORT az_addr
{
direction = "input";
type = "address";
width = "22";
Is_Enabled = "1";
}
PORT az_be_n
{
direction = "input";
type = "byteenable_n";
width = "8";
Is_Enabled = "1";
}
PORT az_cs
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT az_data
{
direction = "input";
type = "writedata";
width = "64";
Is_Enabled = "1";
}
PORT az_rd_n
{
direction = "input";
type = "read_n";
width = "1";
Is_Enabled = "1";
}
PORT az_wr_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT za_data
{
direction = "output";
type = "readdata";
width = "64";
Is_Enabled = "1";
}
PORT za_valid
{
direction = "output";
type = "readdatavalid";
width = "1";
Is_Enabled = "1";
}
PORT za_waitrequest
{
direction = "output";
type = "waitrequest";
width = "1";
Is_Enabled = "1";
}
PORT zs_addr
{
direction = "output";
width = "12";
Is_Enabled = "1";
}
PORT zs_ba
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_cas_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cke
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cs_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_dq
{
direction = "inout";
width = "64";
Is_Enabled = "1";
}
PORT zs_dqm
{
direction = "output";
width = "8";
Is_Enabled = "1";
}
PORT zs_ras_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_we_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Disable_Simulation_Port_Wiring = "0";
View
{
Settings_Summary = "4194304 x 64
Memory size: 32 MBytes
256 MBits
";
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
register_data_in = "1";
sim_model_base = "1";
sdram_data_width = "64";
sdram_addr_width = "12";
sdram_row_width = "12";
sdram_col_width = "8";
sdram_num_chipselects = "1";
sdram_num_banks = "4";
refresh_period = "15.625";
powerup_delay = "100";
cas_latency = "2";
t_rfc = "70";
t_rp = "20";
t_mrd = "3";
t_rcd = "20";
t_ac = "5.5";
t_wr = "14";
init_refresh_commands = "2";
init_nop_delay = "0";
shared_data = "0";
starvation_indicator = "0";
tristate_bridge_slave = "";
is_initialized = "1";
sdram_bank_width = "2";
MAKE
{
TARGET delete_placeholder_warning
{
sdram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
sdram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL a
{
name = "az_addr";
radix = "hexadecimal";
}
SIGNAL b
{
name = "az_be_n";
radix = "hexadecimal";
}
SIGNAL c
{
name = "az_cs";
}
SIGNAL d
{
name = "az_data";
radix = "hexadecimal";
}
SIGNAL e
{
name = "az_rd_n";
}
SIGNAL f
{
name = "az_wr_n";
}
SIGNAL g
{
name = "clk";
}
SIGNAL h
{
name = "za_data";
radix = "hexadecimal";
}
SIGNAL i
{
name = "za_valid";
}
SIGNAL j
{
name = "za_waitrequest";
}
SIGNAL k
{
name = "za_cannotrefresh";
suppress = "1";
}
SIGNAL l
{
name = "CODE";
radix = "ascii";
}
SIGNAL m
{
name = "zs_addr";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL n
{
name = "zs_ba";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL o
{
name = "zs_cs_n";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL p
{
name = "zs_ras_n";
suppress = "0";
}
SIGNAL q
{
name = "zs_cas_n";
suppress = "0";
}
SIGNAL r
{
name = "zs_we_n";
suppress = "0";
}
SIGNAL s
{
name = "zs_dq";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL t
{
name = "zs_dqm";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL u
{
name = "zt_addr";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL v
{
name = "zt_ba";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL w
{
name = "zt_oe";
suppress = "1";
}
SIGNAL x
{
name = "zt_cke";
suppress = "1";
}
SIGNAL y
{
name = "zt_chipselect";
suppress = "1";
}
SIGNAL z0
{
name = "zt_lock_n";
suppress = "1";
}
SIGNAL z1
{
name = "zt_ras_n";
suppress = "1";
}
SIGNAL z2
{
name = "zt_cas_n";
suppress = "1";
}
SIGNAL z3
{
name = "zt_we_n";
suppress = "1";
}
SIGNAL z4
{
name = "zt_cs_n";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z5
{
name = "zt_dqm";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z6
{
name = "zt_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z7
{
name = "tz_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z8
{
name = "tz_waitrequest";
suppress = "1";
}
}
PORT_WIRING
{
PORT clk
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT zs_addr
{
direction = "input";
width = "12";
Is_Enabled = "1";
}
PORT zs_ba
{
direction = "input";
width = "2";
Is_Enabled = "1";
}
PORT zs_cas_n
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT zs_cke
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT zs_cs_n
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT zs_dq
{
direction = "inout";
width = "64";
Is_Enabled = "1";
}
PORT zs_dqm
{
direction = "input";
width = "8";
Is_Enabled = "1";
}
PORT zs_ras_n
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT zs_we_n
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
}
}
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd, __PROJECT_DIRECTORY__/sdram_test_component.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE seven_seg_pio
{
class = "altera_avalon_pio";
class_version = "6.05";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/seven_seg_pio.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT out_port
{
direction = "output";
width = "16";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "4";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "4";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "16";
Base_Address = "0x08010890";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Settings_Summary = " 16-bit PIO using
output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
}
}
MODULE sys_clk_timer
{
class = "altera_avalon_timer";
class_version = "6.05";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
Base_Address = "0x08010800";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "1";
}
Address_Group = "0";
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
Is_Enabled = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
View
{
Settings_Summary = "Timer with 1 ms timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "1";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE sysid
{
class = "altera_avalon_sysid";
class_version = "6.05";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "1";
Data_Width = "32";
Base_Address = "0x08010828";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Read_Latency = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
View
{
Settings_Summary = "System ID (at last Generate):
A957D3F3 (unique ID tag)
4739914A (timestamp: Tue Nov 13, 2007 @8:58 PM)";
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
value0 = "3165772932u";
value1 = "1077149968u";
MAKE
{
TARGET verifysysid
{
verifysysid
{
All_Depends_On = "0";
Command = "nios2-download $(JTAG_CABLE) --sidp=0x08010828 --id=2841105395 --timestamp=1194955082";
Target_File = "dummy_verifysysid_file";
Is_Phony = "1";
}
}
}
id = "2841105395u";
timestamp = "1194955082u";
}
}
MODULE uart1
{
class = "altera_avalon_uart";
class_version = "6.05";
iss_model_name = "altera_avalon_uart";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
Base_Address = "0x08010840";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "3";
}
Address_Group = "0";
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
Is_Enabled = "1";
}
PORT begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT read_n
{
direction = "input";
type = "read_n";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
Is_Enabled = "1";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
Is_Enabled = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
View
{
Settings_Summary = "8-bit UART with 115200 baud,
1 stop bits and N parity";
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = " Bus Interface";
format = "Divider";
}
SIGNAL b
{
name = "chipselect";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "writedata";
radix = "hexadecimal";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = " Internals";
format = "Divider";
}
SIGNAL g
{
name = "tx_ready";
}
SIGNAL h
{
name = "tx_data";
radix = "ascii";
}
SIGNAL i
{
name = "rx_char_ready";
}
SIGNAL j
{
name = "rx_data";
radix = "ascii";
}
}
INTERACTIVE_OUT log
{
enable = "0";
file = "_log_module.txt";
radix = "ascii";
signals = "temp,list";
exe = "perl -- tail-f.pl";
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "perl -- uart.pl";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
baud = "115200";
data_bits = "8";
fixed_baud = "1";
parity = "N";
stop_bits = "1";
use_cts_rts = "0";
use_eop_register = "0";
sim_true_baud = "0";
sim_char_stream = "";
}
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart1.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT rxd
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT txd
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT cts_n
{
direction = "input";
width = "1";
Is_Enabled = "0";
}
PORT rts_n
{
direction = "output";
width = "1";
Is_Enabled = "0";
}
}
}
MODULE vga_16_bit
{
class = "altera_avalon_16_bit_vga";
class_version = "2.0";
HDL_INFO
{
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/image_package.vhd,__PROJECT_DIRECTORY__/vga_register_bank.vhd,__PROJECT_DIRECTORY__/line_buffer.vhd,__PROJECT_DIRECTORY__/image_dma.vhd,__PROJECT_DIRECTORY__/vga_driver.vhd,__PROJECT_DIRECTORY__/altera_avalon_16_bit_vga.vhd,__PROJECT_DIRECTORY__/vga_16_bit.vhd";
Simulation_HDL_Files = "";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
vhdl_Sim_Model_Files = "";
}
MASTER image_dma_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "32";
Data_Width = "32";
Is_Enabled = "1";
Interrupts_Enabled = "0";
}
PORT_WIRING
{
PORT read_to_sram
{
type = "read";
direction = "output";
width = "1";
}
PORT address_to_sram
{
type = "address";
direction = "output";
width = "32";
}
PORT data_from_sram
{
type = "readdata";
direction = "input";
width = "32";
}
PORT waitrequest
{
type = "waitrequest";
direction = "input";
width = "1";
}
PORT readdatavalid
{
type = "readdatavalid";
direction = "input";
width = "1";
}
}
}
SLAVE config_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "3";
Data_Width = "32";
Has_IRQ = "1";
Address_Alignment = "dynamic";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "6";
}
Base_Address = "0x080108C0";
Address_Group = "0";
}
PORT_WIRING
{
PORT clk
{
width = "1";
direction = "input";
type = "clk";
}
PORT chipselect_config
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT address_config
{
direction = "input";
is_shared = "1";
type = "address";
width = "3";
}
PORT read_config
{
type = "read";
direction = "input";
width = "1";
}
PORT readdata_config
{
type = "readdata";
direction = "output";
width = "32";
}
PORT write_config
{
type = "write";
direction = "input";
width = "1";
}
PORT writedata_config
{
type = "writedata";
direction = "input";
width = "32";
}
PORT irq
{
type = "irq";
direction = "output";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
View
{
Is_Collapsed = "0";
MESSAGES
{
}
}
Clock_Source = "clk";
}
SIMULATION
{
}
PORT_WIRING
{
PORT vga_clk
{
direction = "input";
width = "1";
}
PORT clock25
{
direction = "input";
width = "1";
}
PORT resetn
{
direction = "input";
width = "1";
}
PORT vga_clock_external
{
direction = "output";
width = "1";
}
PORT hsync
{
direction = "output";
width = "1";
}
PORT vsync
{
direction = "output";
width = "1";
}
PORT M1
{
direction = "output";
width = "1";
}
PORT M2
{
direction = "output";
width = "1";
}
PORT sync_n
{
direction = "output";
width = "1";
}
PORT sync_t
{
direction = "output";
width = "1";
}
PORT blank_n
{
direction = "output";
width = "1";
}
PORT R
{
direction = "output";
width = "8";
}
PORT G
{
direction = "output";
width = "8";
}
PORT B
{
direction = "output";
width = "8";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
}
}
MODULE interruptvector_cpu
{
class = "altera_nios_custom_instr_interrupt_vector";
class_version = "6.05";
iss_model_name = "nios2_custom_instruction";
HDL_INFO
{
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/interruptvector_cpu.vhd";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_Only_Files = "";
}
SLAVE interrupt_vector
{
PORT_WIRING
{
PORT estatus
{
Is_Enabled = "1";
direction = "input";
type = "estatus";
width = "1";
}
PORT ipending
{
Is_Enabled = "1";
direction = "input";
type = "ipending";
width = "32";
}
PORT result
{
Is_Enabled = "1";
direction = "output";
type = "result";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "0";
Is_Custom_Instruction = "1";
Is_Visible = "0";
Is_Enabled = "1";
ci_macro_name = "interrupt_vector";
required_ci_macro_name = "interrupt_vector";
ci_inst_type = "combinatorial";
ci_operands = "0";
MASTERED_BY cpu/custom_instruction_master
{
priority = "1";
}
Base_Address = "0x00000000";
Address_Group = "0";
IRQ_MASTER cpu/custom_instruction_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Is_Visible = "0";
Instantiate_In_System_Module = "1";
Is_Custom_Instruction = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Module_Name = "interrupt_vector";
Synthesize_Imported_HDL = "1";
}
PORT_WIRING
{
}
}
}