Index: azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/Makefile
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/Makefile	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/Makefile	(revision 458)
@@ -215,9 +215,4 @@
 SYSSVC_LIBS := $(SYSSVC_LIBS)
 INCLUDES := $(INCLUDES) -I$(SRCDIR)/pdic/k210
-#LDFLAGS := $(LDFLAGS) \
-#	-Wl,--wrap=_malloc_r \
-#	-Wl,--wrap=_calloc_r \
-#	-Wl,--wrap=_free_r \
-#	-Wl,--wrap=_realloc_r
 
 #
@@ -489,7 +484,7 @@
   #
   ifdef GCC_TARGET
-    GCC_TARGET_PREFIX = $(GCC_TARGET)-
+	GCC_TARGET_PREFIX = $(GCC_TARGET)-
   else
-    GCC_TARGET_PREFIX =
+	GCC_TARGET_PREFIX =
   endif
   CC = $(GCC_TARGET_PREFIX)gcc
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.c	(revision 458)
@@ -275,7 +275,6 @@
 	OV2640_t        *hcmr;
 	DVP_Handle_t    *hdvp;
-	uint16_t        *lcd_buffer;
 	ER_UINT	ercd;
-	uint32_t i, count;
+	uint32_t i;
 	struct tm2 time;
 	unsigned long atmp;
@@ -465,10 +464,5 @@
 	lcd_init(hlcd);
 	syslog_2(LOG_NOTICE, "width(%d) height(%d)", hlcd->_width, hlcd->_height);
-	count = hcmr->_width * hcmr->_height;
-	lcd_buffer = (uint16_t *)malloc(count * 2);
-	if(lcd_buffer == NULL){
-		syslog_0(LOG_ERROR, "no lcd buffer !");
-		slp_tsk();
-	}
+
 	DrawProp.BackColor = ST7789_WHITE;
 	DrawProp.TextColor = ST7789_BLACK;
@@ -588,11 +582,5 @@
 			ercd = ov2640_snapshot(hcmr);
 			if(ercd == E_OK){
-				uint32_t *p = (uint32_t *)hcmr->_dataBuffer;
-				uint32_t *q = (uint32_t *)lcd_buffer;
-				uint32_t *e = (uint32_t *)&lcd_buffer[count];
-				for (; q < e ; p++, q++){
-					*q = SWAP_32(*p);
-				}
-				lcd_drawPicture(hlcd, 0, 0, hcmr->_width, hcmr->_height, lcd_buffer);
+				lcd_drawPicture(hlcd, 0, 0, hcmr->_width, hcmr->_height, (uint16_t *)hcmr->_dataBuffer);
 			}
 		}
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.cfg
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.cfg	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/OBJ/K210_GCC/DEMO/demo.cfg	(revision 458)
@@ -11,4 +11,5 @@
 INCLUDE("syssvc/serial.cfg");
 INCLUDE("syssvc/logtask.cfg");
+INCLUDE("syssvc/malloc.cfg");
 INCLUDE("pdic/k210/device.cfg");
 INCLUDE("pdic/k210/dvp.cfg");
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv32elf.ld
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv32elf.ld	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv32elf.ld	(revision 458)
@@ -2,18 +2,4 @@
  *  @(#) $Id$
  */
-
-MEMORY
-{
-  /*
-   * Memory with CPU cache.
-   *6M CPU SRAM
-   */
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = (6 * 1024 * 1024)
-  /*
-   * Memory without CPU cache
-   * 6M CPU SRAM
-  */
-  ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024)
-}
 
 OUTPUT_ARCH(riscv)
@@ -22,6 +8,4 @@
 PROVIDE(software_init_hook = 0);
 PROVIDE(software_term_hook = 0);
-PROVIDE(__idata_start = 0);
-PROVIDE(__idata_end = 0);
 STARTUP(start.o)
 
@@ -33,5 +17,5 @@
     {
         KEEP (*(.init))
-    }>ram
+    }
     .text :
     {
@@ -39,9 +23,9 @@
         *(.text .stub .text.* .gnu.linkonce.t.*)
 
-    }>ram
+    }
     .fini :
     {
         KEEP (*(.fini))
-    }>ram
+    }
     _etext = . ;
     PROVIDE (etext = .) ;
@@ -49,17 +33,17 @@
     {
         *(.rodata .rodata.* .gnu.linkonce.r.*)
-    }>ram
+    }
     . = ALIGN(4) ;
-    .data : 
+    __idata_start = . ;
+    .data : AT(__idata_start)
     {
         __data_start = . ;
-        /* Writable data segment (.data segment) */
         *(.data .data.*)
-        *(.sdata .sdata.* .sdata2 .sdata2.*)
+        *(.sdata .sdata.* .sdata2.*)
         . = ALIGN(8);
-        PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800);
-    }>ram
-    .eh_frame : { KEEP (*(.eh_frame)) }>ram
-    .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) }>ram
+        PROVIDE( __global_pointer$ = . + 0x800 );
+    }
+    .eh_frame : { KEEP (*(.eh_frame)) }
+    .gcc_except_table : { *(.gcc_except_table) }
     .ctors :
     {
@@ -68,5 +52,5 @@
         KEEP (*(SORT(.ctors.*)))
         KEEP (*(.ctors))
-    }>ram
+    }
     .dtors :
     {
@@ -75,29 +59,22 @@
         KEEP (*(SORT(.dtors.*)))
         KEEP (*(.dtors))
-    }>ram
+    }
+    __idata_end = __idata_start + SIZEOF(.data) ;
     _edata  = . ;
     PROVIDE (edata = .) ;
     . = ALIGN(4) ;
     __bss_start = . ;
-    _bss = .;
     .bss :
     {
         *(.bss .bss.*)
-        *(.sbss .sbss.* .sbss2 .sbss2.*)
+        *(.sbss .sbss.* .sbss2.*)
         *(COMMON)
-    }>ram
+    }
     _end = . ;
     __bss_end = . ;
-    _ebss = . ;
-    .stack (NOLOAD) :
+    .stack :
     {
     	*(.stack)
-    }>ram
-    .heap (NOLOAD) :
-    {
-        PROVIDE (_heap_start = .) ;
-        *(.heap)
-    }>ram
-    PROVIDE (_heap_end = .) ;
+    }
     PROVIDE (end = .) ;
     .comment        0 : { *(.comment) }
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv64elf.ld
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv64elf.ld	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/arch/riscv_gcc/riscv64elf.ld	(revision 458)
@@ -2,18 +2,4 @@
  *  @(#) $Id$
  */
-
-MEMORY
-{
-  /*
-   * Memory with CPU cache.
-   *6M CPU SRAM
-   */
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = (6 * 1024 * 1024)
-  /*
-   * Memory without CPU cache
-   * 6M CPU SRAM
-  */
-  ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024)
-}
 
 OUTPUT_ARCH(riscv)
@@ -22,6 +8,4 @@
 PROVIDE(software_init_hook = 0);
 PROVIDE(software_term_hook = 0);
-PROVIDE(__idata_start = 0);
-PROVIDE(__idata_end = 0);
 STARTUP(start.o)
 
@@ -33,5 +17,5 @@
     {
         KEEP (*(.init))
-    }>ram
+    }
     .text :
     {
@@ -39,9 +23,9 @@
         *(.text .stub .text.* .gnu.linkonce.t.*)
 
-    }>ram
+    }
     .fini :
     {
         KEEP (*(.fini))
-    }>ram
+    }
     _etext = . ;
     PROVIDE (etext = .) ;
@@ -49,17 +33,18 @@
     {
         *(.rodata .rodata.* .gnu.linkonce.r.*)
-    }>ram
+    }
     . = ALIGN(8);
-    .data : 
+    __idata_start = . ;
+    .data :
     {
         __data_start = . ;
         /* Writable data segment (.data segment) */
         *(.data .data.*)
-        *(.sdata .sdata.* .sdata2 .sdata2.*)
+        *(.sdata .sdata.* .sdata2.*)
         . = ALIGN(8);
         PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800);
-    }>ram
-    .eh_frame : { KEEP (*(.eh_frame)) }>ram
-    .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) }>ram
+    }
+    .eh_frame : { KEEP (*(.eh_frame)) }
+    .gcc_except_table : { *(.gcc_except_table) }
     .ctors :
     {
@@ -68,5 +53,5 @@
         KEEP (*(SORT(.ctors.*)))
         KEEP (*(.ctors))
-    }>ram
+    }
     .dtors :
     {
@@ -75,29 +60,22 @@
         KEEP (*(SORT(.dtors.*)))
         KEEP (*(.dtors))
-    }>ram
+    }
+    __idata_end = __idata_start + SIZEOF(.data) ;
     _edata  = . ;
     PROVIDE (edata = .) ;
     . = ALIGN(8) ;
     __bss_start = . ;
-    _bss = .;
     .bss :
     {
         *(.bss .bss.*)
-        *(.sbss .sbss.* .sbss2 .sbss2.*)
+        *(.sbss .sbss.* .sbss2.*)
         *(COMMON)
-    }>ram
+    }
     _end = . ;
     __bss_end = . ;
-    _ebss = . ;
-    .stack (NOLOAD) :
+    .stack :
     {
     	*(.stack)
-    }>ram
-    .heap (NOLOAD) :
-    {
-        PROVIDE (_heap_start = .) ;
-        *(.heap)
-    }>ram
-    PROVIDE (_heap_end = .) ;
+    }
     PROVIDE (end = .) ;
     .comment        0 : { *(.comment) }
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_ov2640/sipeed_ov2640.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_ov2640/sipeed_ov2640.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_ov2640/sipeed_ov2640.c	(revision 458)
@@ -750,5 +750,5 @@
 			dly_tsk(1);
 	}
-	reverse_u32pixel((uint32_t*)hcmr->_dataBuffer, hcmr->_width * hcmr->_height/2);
+	//reverse_u32pixel((uint32_t*)hcmr->_dataBuffer, hcmr->_width * hcmr->_height/2);
 	return E_OK;
 }
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_st7789/sipeed_st7789.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_st7789/sipeed_st7789.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/gdic/sipeed_st7789/sipeed_st7789.c	(revision 458)
@@ -83,10 +83,10 @@
 static void set_dcx_control(LCD_Handler_t *hlcd)
 {
-    gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_LOW);
+	gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_LOW);
 }
 
 static void set_dcx_data(LCD_Handler_t *hlcd)
 {
-    gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_HIGH);
+	gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_HIGH);
 }
 
@@ -101,9 +101,9 @@
 
 	aTxBuffer[0] = c;
-    set_dcx_control(hlcd);
+	set_dcx_control(hlcd);
 	hspi->Init.DataSize = 8;
 	hspi->Init.InstLength = 8;
 	hspi->Init.AddrLength = 0;
-    ercd = spi_core_transmit(hspi, hlcd->cs_sel, (uint8_t *)(aTxBuffer), 1);
+	ercd = spi_core_transmit(hspi, hlcd->cs_sel, (uint8_t *)(aTxBuffer), 1);
 #if SPI_WAIT_TIME == 0
 	if(ercd == E_OK)
@@ -128,5 +128,5 @@
 		aTxBuffer[i] = buf[i];
 
-    set_dcx_data(hlcd);
+	set_dcx_data(hlcd);
 	hspi->Init.DataSize = 8;
 	hspi->Init.InstLength = 8;
@@ -146,5 +146,5 @@
 	ER ercd = E_OK;
 
-    set_dcx_data(hlcd);
+	set_dcx_data(hlcd);
 	hspi->Init.DataSize = 8;
 	hspi->Init.InstLength = 8;
@@ -167,5 +167,5 @@
 	ER ercd = E_OK;
 
-    set_dcx_data(hlcd);
+	set_dcx_data(hlcd);
 	hspi->Init.DataSize = 16;
 	hspi->Init.InstLength = 16;
@@ -188,5 +188,5 @@
 	ER ercd = E_OK;
 
-    set_dcx_data(hlcd);
+	set_dcx_data(hlcd);
 	hspi->Init.DataSize = 32;
 	hspi->Init.InstLength = 0;
@@ -206,5 +206,5 @@
 {
 	GPIO_Init_t init = {0};
-    uint8_t data = 0;
+	uint8_t data[2] = {0};
 
 	/*
@@ -214,6 +214,6 @@
 	init.mode = GPIO_MODE_OUTPUT;
 	init.pull = GPIO_PULLDOWN;
-    gpio_setup(TADR_GPIO_BASE, &init, hlcd->dcx_no);
-    gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_HIGH);
+	gpio_setup(TADR_GPIO_BASE, &init, hlcd->dcx_no);
+	gpio_set_pin(TADR_GPIO_BASE, hlcd->dcx_no, PORT_HIGH);
 
 	/*
@@ -227,6 +227,6 @@
 		gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, PORT_HIGH);
 
-	    gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, 0);
-	    gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, 1);
+		gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, 0);
+		gpio_set_pin(TADR_GPIO_BASE, hlcd->rst_no, 1);
 	}
 
@@ -245,6 +245,6 @@
 	 */
 	lcd_writecommand(hlcd, PIXEL_FORMAT_SET);
-	data = 0x55;
-    lcd_writebyte(hlcd, &data, 1);
+	data[0] = 0x55;
+	lcd_writebyte(hlcd, &data, 1);
 	if(hlcd->dir & DIR_XY_MASK){
 		hlcd->_width = ST7789_TFTHEIGHT;
@@ -259,5 +259,10 @@
 
 	lcd_writecommand(hlcd, MEMORY_ACCESS_CTL);
-    lcd_writebyte(hlcd, (uint8_t *)&hlcd->dir, 1);
+	lcd_writebyte(hlcd, (uint8_t *)&hlcd->dir, 1);
+
+	//lcd_writecommand(hlcd, RGB_IF_SIGNAL_CTL);
+	//data[0] = 0x00;
+	//data[1] = 0xF8;
+	//lcd_writebyte(hlcd, &data, 2);
 
 	/*
@@ -274,19 +279,19 @@
 lcd_setAddrWindow(LCD_Handler_t *hlcd,  uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
 {
-    uint8_t data[4] = {0};
-
-    data[0] = (uint8_t)(x0 >> 8);
-    data[1] = (uint8_t)(x0);
-    data[2] = (uint8_t)(x1 >> 8);
-    data[3] = (uint8_t)(x1);
+	uint8_t data[4] = {0};
+
+	data[0] = (uint8_t)(x0 >> 8);
+	data[1] = (uint8_t)(x0);
+	data[2] = (uint8_t)(x1 >> 8);
+	data[3] = (uint8_t)(x1);
 	lcd_writecommand(hlcd, HORIZONTAL_ADDRESS_SET);
-    lcd_writebyte(hlcd, data, 4);
-
-    data[0] = (uint8_t)(y0 >> 8);
-    data[1] = (uint8_t)(y0);
-    data[2] = (uint8_t)(y1 >> 8);
-    data[3] = (uint8_t)(y1);
+	lcd_writebyte(hlcd, data, 4);
+
+	data[0] = (uint8_t)(y0 >> 8);
+	data[1] = (uint8_t)(y0);
+	data[2] = (uint8_t)(y1 >> 8);
+	data[3] = (uint8_t)(y1);
 	lcd_writecommand(hlcd, VERTICAL_ADDRESS_SET);
-    lcd_writebyte(hlcd, data, 4);
+	lcd_writebyte(hlcd, data, 4);
 
 	SVC_PERROR(lcd_writecommand(hlcd, MEMORY_WRITE));
@@ -305,5 +310,5 @@
 lcd_fillRect(LCD_Handler_t *hlcd, int16_t x, int16_t y, int16_t w, int16_t h, color_t color)
 {
-    uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
+	uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
 	// rudimentary clipping (drawChar w/big text requires this)
 	if((x >= hlcd->_width) || (y >= hlcd->_height)) return;
@@ -312,5 +317,5 @@
 
 	lcd_setAddrWindow(hlcd, x, y, x+w-1, y+h-1);
-    SVC_PERROR(lcd_filldata(hlcd, &data, (h*w+1)/2));
+	SVC_PERROR(lcd_filldata(hlcd, &data, (h*w+1)/2));
 }
 
@@ -326,5 +331,5 @@
 {
 	uint32_t data = color;
-    lcd_setAddrWindow(hlcd, x, y, x, y);
+	lcd_setAddrWindow(hlcd, x, y, x, y);
 	SVC_PERROR(lcd_writehalf(hlcd, &data, 1));
 }
@@ -341,5 +346,5 @@
 lcd_drawFastVLine(LCD_Handler_t *hlcd, int16_t x, int16_t y, int16_t h, color_t color)
 {
-    uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
+	uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
 	// Rudimentary clipping
 	if(h == 0) return;
@@ -347,5 +352,5 @@
 	if((y+h-1) >= hlcd->_height) h = hlcd->_height-y;
 	lcd_setAddrWindow(hlcd, x, y, x, y+h-1);
-    SVC_PERROR(lcd_filldata(hlcd, &data, (h+1)/2));
+	SVC_PERROR(lcd_filldata(hlcd, &data, (h+1)/2));
 }
 
@@ -360,5 +365,5 @@
 void lcd_drawFastHLine(LCD_Handler_t *hlcd, int16_t x, int16_t y, int16_t w, color_t color)
 {
-    uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
+	uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
 	// Rudimentary clipping
 	if(w == 0) return;
@@ -366,5 +371,5 @@
 	if((x+w-1) >= hlcd->_width)  w = hlcd->_width-x;
 	lcd_setAddrWindow(hlcd, x, y, x+w-1, y);
-    SVC_PERROR(lcd_filldata(hlcd, &data, (w+1)/2));
+	SVC_PERROR(lcd_filldata(hlcd, &data, (w+1)/2));
 }
 
@@ -462,5 +467,5 @@
 
 	lcd_setAddrWindow(hlcd, x, y, x+width-1, y+height-1);
-    set_dcx_data(hlcd);
+	set_dcx_data(hlcd);
 	hspi->Init.DataSize = 32;
 	hspi->Init.InstLength = 0;
@@ -533,5 +538,5 @@
 {
 	LCD_Handler_t *hlcd = pDrawProp->hlcd;
- 	int32_t   decision;    /* Decision Variable */ 
+	int32_t   decision;    /* Decision Variable */ 
 	uint32_t  current_x;   /* Current X Value */
 	uint32_t  current_y;   /* Current Y Value */
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/dvp.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/dvp.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/dvp.c	(revision 458)
@@ -66,5 +66,5 @@
 
 #define DEAFULT_CLEAR_INT       (DVP_STS_FRAME_START  | DVP_STS_FRAME_START_WE | \
-                                 DVP_STS_FRAME_FINISH | DVP_STS_FRAME_FINISH_WE)
+								 DVP_STS_FRAME_FINISH | DVP_STS_FRAME_FINISH_WE)
 
 
@@ -75,6 +75,6 @@
 {
 	uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0));
-    uint32_t source = 0;
-    uint32_t result = 0;
+	uint32_t source = 0;
+	uint32_t result = 0;
 	uint32_t threshold = 0;
 
@@ -97,5 +97,5 @@
 	result = source / (threshold + 1);
 	syslog_2(LOG_NOTICE, "## dvp_clock_get_freq req(%d) result(%d) ##", clock, result);
-    return result;
+	return result;
 }
 
@@ -104,8 +104,8 @@
 {
 	while(sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS)) & DVP_STS_SCCB_EN)
-        ;
+		;
 	sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS), (DVP_STS_SCCB_EN | DVP_STS_SCCB_EN_WE));
-    while (sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS)) & DVP_STS_SCCB_EN)
-        ;
+	while (sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS)) & DVP_STS_SCCB_EN)
+		;
 }
 
@@ -150,5 +150,5 @@
 	tmp = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG)) & (~DVP_SCCB_BYTE_NUM_MASK);
 
-    if (hdvp->Init.num_sccb_reg == 8)
+	if (hdvp->Init.num_sccb_reg == 8)
 		tmp |= DVP_SCCB_BYTE_NUM_2;
 	else
@@ -164,9 +164,9 @@
 	sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CTL), tmp);
 
-    dvp_sccb_start_transfer(hdvp);
+	dvp_sccb_start_transfer(hdvp);
 
 	sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CTL), addr);
 
-    dvp_sccb_start_transfer(hdvp);
+	dvp_sccb_start_transfer(hdvp);
 
 	tmp = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG));
@@ -182,5 +182,5 @@
 dvp_init(DVP_Handle_t *hdvp)
 {
-    uint32_t v_apb1_clk, v_period;
+	uint32_t v_apb1_clk, v_period;
 
 	if(hdvp == NULL)
@@ -201,10 +201,10 @@
 	fpioa_set_function(hdvp->Init.SccbSdaPin, FUNC_SCCB_SDA);
 
-    /* Do a power cycle */
-    dvp_dcmi_powerdown(hdvp, false);
-    dly_tsk(10);
-
-    dvp_dcmi_powerdown(hdvp, true);
-    dly_tsk(100);
+	/* Do a power cycle */
+	dvp_dcmi_powerdown(hdvp, false);
+	dly_tsk(10);
+
+	dvp_dcmi_powerdown(hdvp, true);
+	dly_tsk(100);
 
 	/*
@@ -372,12 +372,12 @@
 	cfg  = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_CFG));
 	cfg &= ~(DVP_CFG_HREF_BURST_NUM_MASK | DVP_CFG_LINE_NUM_MASK);
-    cfg |= hdvp->Init.Height << 20;
-
-    if((cfg & DVP_CFG_BURST_SIZE_4BEATS) != 0)
+	cfg |= hdvp->Init.Height << 20;
+
+	if((cfg & DVP_CFG_BURST_SIZE_4BEATS) != 0)
 		divw = 4;
 	else
 		divw = 1;
 	cfg |= (hdvp->Init.Width / 8 / divw) << 12;
-    sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_CFG), cfg);
+	sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_CFG), cfg);
 	return E_OK;
 }
@@ -403,6 +403,6 @@
 
 	sccb_cfg  = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG));
-    sccb_cfg &= ~(DVP_SCCB_SCL_LCNT_MASK | DVP_SCCB_SCL_HCNT_MASK);
-    sccb_cfg |= (v_period_clk_cnt << 8) | (v_period_clk_cnt << 16);
+	sccb_cfg &= ~(DVP_SCCB_SCL_LCNT_MASK | DVP_SCCB_SCL_HCNT_MASK);
+	sccb_cfg |= (v_period_clk_cnt << 8) | (v_period_clk_cnt << 16);
 	sil_wrw_mem((uint32_t *)(hdvp->base+TOFF_DVP_SCCB_CFG), sccb_cfg);
 	return dvp_clock_get_freq(DVP_CLOCK_REQ) / (v_period_clk_cnt * 2);
@@ -454,11 +454,15 @@
 	uint32_t istatus, estatus;
 
-	if(hdvp == NULL)
+	if (hdvp == NULL) {
+		syslog_0(LOG_NOTICE, "dvp_handler hdvp == NULL");
 		return;
+	}
 	istatus = sil_rew_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS));
-	if(istatus == 0)
+	if (istatus == 0) {
+		syslog_0(LOG_DEBUG, "dvp_handler istatus == 0");
 		return;
+	}
 	estatus = istatus;
-	syslog_2(LOG_DEBUG, "sensor_irq istatus[%08x] hdvp->state(%d)", istatus, hdvp->state);
+	syslog_2(LOG_DEBUG, "dvp_handler istatus[%08x] hdvp->state(%d)", istatus, hdvp->state);
 	if((istatus & DVP_STS_FRAME_FINISH) != 0){	//frame end
 		estatus |= DVP_STS_FRAME_FINISH_WE;
@@ -469,5 +473,5 @@
 	if((istatus & DVP_STS_FRAME_START) != 0){	//frame start
 		estatus |= DVP_STS_FRAME_START_WE;
-        if(hdvp->state == DVP_STATE_ACTIVATE){  //only we finish the convert, do transmit again
+		if(hdvp->state == DVP_STATE_ACTIVATE){  //only we finish the convert, do transmit again
 			/*
 			 *  コンバートスタート
@@ -479,4 +483,2 @@
 	sil_orw_mem((uint32_t *)(hdvp->base+TOFF_DVP_STS), estatus);
 }
-
-
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.c	(revision 458)
@@ -56,26 +56,26 @@
 sil_rel_mem(const uint64_t *mem)
 {
-	uint64_t	data;
-
-	data = *((const volatile uint64_t *) mem);
-	return(data);
-}
-
-#define sil_orw_mem(a, b)		sil_wrw_mem((a), sil_rew_mem(a) | (b))
-#define sil_andw_mem(a, b)		sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
-#define sil_modw_mem(a, b, c)	sil_wrw_mem((a), (sil_rew_mem(a) & (~b)) | (c))
+	uint64_t data;
+
+	data = *((const volatile uint64_t *)mem);
+	return (data);
+}
+
+#define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b))
+#define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
+#define sil_modw_mem(a, b, c) sil_wrw_mem((a), (sil_rew_mem(a) & (~b)) | (c))
 
 /*
  *  SPIOポートIDから管理ブロックを取り出すためのマクロ
  */
-#define INDEX_SPI(spiid)        ((uint_t)((spiid) - 1))
-
-#define get_framewidth(l)       (((l)+7)/8)
-
-#define SPI_SSIENR_DISABLE      0x00000000
-#define SPI_SSIENR_ENABLE       0x00000001
-
-#define SPI_DMACR_RXENABLE      0x00000001
-#define SPI_DMACR_TXENABLE      0x00000002
+#define INDEX_SPI(spiid) ((uint_t)((spiid)-1))
+
+#define get_framewidth(l) (((l) + 7) / 8)
+
+#define SPI_SSIENR_DISABLE 0x00000000
+#define SPI_SSIENR_ENABLE 0x00000001
+
+#define SPI_DMACR_RXENABLE 0x00000001
+#define SPI_DMACR_TXENABLE 0x00000002
 
 /*
@@ -83,17 +83,17 @@
  */
 
-typedef struct _SPI_PortControlBlock{
-	unsigned long         base;
-	int16_t               func_data;
-	int16_t               func_ss;
-	int16_t               func_arb;
-	int16_t               func_sclk;
+typedef struct _SPI_PortControlBlock {
+	unsigned long base;
+	int16_t func_data;
+	int16_t func_ss;
+	int16_t func_arb;
+	int16_t func_sclk;
 } SPI_PortControlBlock;
 
 static const SPI_PortControlBlock spi_pcb[NUM_SPIPORT] = {
-	{TADR_SPI0_BASE, FUNC_SPI0_D0,      FUNC_SPI0_SS0,     FUNC_SPI0_ARB, FUNC_SPI0_SCLK     },
-	{TADR_SPI1_BASE, FUNC_SPI1_D0,      FUNC_SPI1_SS0,     FUNC_SPI1_ARB, FUNC_SPI1_SCLK     },
+	{TADR_SPI0_BASE, FUNC_SPI0_D0,      FUNC_SPI0_SS0,     FUNC_SPI0_ARB, FUNC_SPI0_SCLK},
+	{TADR_SPI1_BASE, FUNC_SPI1_D0,      FUNC_SPI1_SS0,     FUNC_SPI1_ARB, FUNC_SPI1_SCLK},
 	{TADR_SPIS_BASE, FUNC_SPI_SLAVE_D0, FUNC_SPI_SLAVE_SS, -1,            FUNC_SPI_SLAVE_SCLK},
-	{TADR_SPI2_BASE, -1,                -1,                -1,            -1                 }
+	{TADR_SPI2_BASE, -1,                -1,                -1,            -1}
 };
 
@@ -109,9 +109,9 @@
 {
 	SPI_Init_t *init;
-    uint32_t inst_l = 4;
-    uint32_t addr_l;
+	uint32_t inst_l = 4;
+	uint32_t addr_l;
 
 	init = &hspi->Init;
-    switch (init->InstLength){
+	switch (init->InstLength) {
 	case 0:
 		inst_l = 0;
@@ -128,14 +128,14 @@
 	default:
 		break;
-    }
-	if(inst_l == 4)
+	}
+	if (inst_l == 4)
 		return E_PAR;
 
 	addr_l = init->AddrLength / 4;
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_CTRLR0), (init->WorkMode << hspi->work_mode_offset) | \
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR0), (init->WorkMode << hspi->work_mode_offset) |
 		(init->FrameFormat << hspi->frf_offset) | ((init->DataSize - 1) << hspi->dfs_offset));
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SPI_CTRLR0),
-		((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode));
-	sil_modw_mem((uint32_t *)(hspi->base+TOFF_SPI_CTRLR0), (3 << hspi->tmod_offset), (tmod << hspi->tmod_offset));
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SPI_CTRLR0),
+				((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode));
+	sil_modw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR0), (3 << hspi->tmod_offset), (tmod << hspi->tmod_offset));
 	return E_OK;
 }
@@ -148,5 +148,5 @@
 {
 	SPI_Handle_t *hspi = (SPI_Handle_t *)hdma->localdata;
-	if(hspi != NULL && hspi->Init.semdmaid != 0){
+	if (hspi != NULL && hspi->Init.semdmaid != 0) {
 		isig_sem(hspi->Init.semdmaid);
 	}
@@ -158,39 +158,39 @@
 DMA_Handle_t *
 spi_dmac_set_single_mode(SPI_Handle_t *hspi, uint8_t rtx,
-						  int8_t  ss_no, const void *src, void *dest,
-						  uint8_t src_inc, uint8_t dest_inc,
-                          uint8_t dmac_burst_size, uint8_t dmac_trans_width,
-                          size_t block_size)
+						 int8_t ss_no, const void *src, void *dest,
+						 uint8_t src_inc, uint8_t dest_inc,
+						 uint8_t dmac_burst_size, uint8_t dmac_trans_width,
+						 size_t block_size)
 {
 	DMA_Handle_t *hdma;
-    int mem_type_src, mem_type_dest;
-    uint8_t flow_control;
-
-	if(rtx == 0){
+	int mem_type_src, mem_type_dest;
+	uint8_t flow_control;
+
+	if (rtx == 0) {
 		hdma = hspi->hdmatx;
-        flow_control = DMA_MEMORY_TO_PERIPH;
+		flow_control = DMA_MEMORY_TO_PERIPH;
 		mem_type_src = 1;
 		mem_type_dest = 0;
 	}
-	else{
+	else {
 		hdma = hspi->hdmarx;
-        flow_control = DMA_PERIPH_TO_MEMORY;
+		flow_control = DMA_PERIPH_TO_MEMORY;
 		mem_type_src = 0;
 		mem_type_dest = 1;
 	}
-	if(ss_no < 0)
+	if (ss_no < 0)
 		ss_no = 0;
 
-	hdma->Init.Direction    = flow_control;	/* DMA転送方向 */
-	hdma->Init.SrcHandShake = (mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE);	/* ソースハンドシェイク */
-	hdma->Init.DrcHandShake = (mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE);	/* デスティネーションハンドシェイク */
-	hdma->Init.SrcInc       = src_inc;	/* ソースインクリメント設定 */
-	hdma->Init.DstInc       = dest_inc;	/* デスティネーションインクリメント設定 */
-	hdma->Init.SrcTransWidth = dmac_trans_width;	/* ソース転送幅 */
-	hdma->Init.DstTransWidth = dmac_trans_width;	/* デスティネーション転送幅 */
-	hdma->Init.SrcBurstSize = dmac_burst_size;	/* ソースバーストサイズ */
-	hdma->Init.DstBurstSize = dmac_burst_size;	/* デスティネーションバーストサイズ */
+	hdma->Init.Direction = flow_control;											 /* DMA転送方向 */
+	hdma->Init.SrcHandShake = (mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE);	 /* ソースハンドシェイク */
+	hdma->Init.DrcHandShake = (mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE); /* デスティネーションハンドシェイク */
+	hdma->Init.SrcInc = src_inc;													 /* ソースインクリメント設定 */
+	hdma->Init.DstInc = dest_inc;													 /* デスティネーションインクリメント設定 */
+	hdma->Init.SrcTransWidth = dmac_trans_width;									 /* ソース転送幅 */
+	hdma->Init.DstTransWidth = dmac_trans_width;									 /* デスティネーション転送幅 */
+	hdma->Init.SrcBurstSize = dmac_burst_size;										 /* ソースバーストサイズ */
+	hdma->Init.DstBurstSize = dmac_burst_size;										 /* デスティネーションバーストサイズ */
 	dma_reset(hdma);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), (1 << ss_no));
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no));
 	dma_start(hdma, (uintptr_t)src, (uintptr_t)dest, block_size);
 	return hdma;
@@ -201,5 +201,5 @@
  */
 ER
-spi_dmac_wait_done(DMA_Handle_t * hdma)
+spi_dmac_wait_done(DMA_Handle_t *hdma)
 {
 	SPI_Handle_t *hspi = (SPI_Handle_t *)hdma->localdata;
@@ -207,7 +207,7 @@
 	int tick = DMA_TRS_TIMEOUT;
 
-	while((hdma->status == DMA_STATUS_BUSY) && tick > 0){
-		if(hspi != NULL && hspi->Init.semdmaid != 0){
-	 		ercd = twai_sem(hspi->Init.semdmaid, 5);
+	while ((hdma->status == DMA_STATUS_BUSY) && tick > 0) {
+		if (hspi != NULL && hspi->Init.semdmaid != 0) {
+			ercd = twai_sem(hspi->Init.semdmaid, 5);
 		}
 		else
@@ -216,7 +216,7 @@
 	}
 	dma_end(hdma);
-	if(hdma->ErrorCode != 0)
+	if (hdma->ErrorCode != 0)
 		ercd = E_OBJ;
-	else if(tick == 0)
+	else if (tick == 0)
 		ercd = E_TMOUT;
 	return ercd;
@@ -232,18 +232,20 @@
 	int tick = timeout;
 
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011);
-    while((sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0){
-		if(hspi->Init.semid != 0)
-			twai_sem(hspi->Init.semid, 5);
-		else
-			dly_tsk(1);
-		tick--;
-	}
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), 0x00000000);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
-
-	if(hspi->ErrorCode != 0)
+	if (hspi->hdmatx != NULL) {
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_IMR), 0x0011);
+		while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) {
+			if (hspi->Init.semid != 0)
+				twai_sem(hspi->Init.semid, 5);
+			else
+				dly_tsk(1);
+			tick--;
+		}
+	}
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
+
+	if (hspi->ErrorCode != 0)
 		ercd = E_OBJ;
-	else if(tick == 0)
+	else if (tick == 0)
 		ercd = E_TMOUT;
 	hspi->TxXferCount = 0;
@@ -266,19 +268,19 @@
 	const SPI_PortControlBlock *spcb;
 	unsigned long base;
-	uint8_t  spi_num;
+	uint8_t spi_num;
 	uint32_t spi_baudr, clk_th1, threshold;
-    uint8_t  dfs_offset, frf_offset, work_mode_offset, tmod_offset;
+	uint8_t dfs_offset, frf_offset, work_mode_offset, tmod_offset;
 	uint32_t dsize_err = 0;
-    uint32_t inst_l = 4;
-    uint32_t addr_l;
-
-	if(port < SPI1_PORTID || port > NUM_SPIPORT)
+	uint32_t inst_l = 4;
+	uint32_t addr_l;
+
+	if (port < SPI1_PORTID || port > NUM_SPIPORT)
 		return NULL;
 	spi_num = INDEX_SPI(port);
-	if(init == NULL)
+	if (init == NULL)
 		return NULL;
-	if(init->DataSize < 4 && init->DataSize > 32)
+	if (init->DataSize < 4 && init->DataSize > 32)
 		return NULL;
-	if(init->AddrLength % 4 != 0 && init->AddrLength > 60)
+	if (init->AddrLength % 4 != 0 && init->AddrLength > 60)
 		return NULL;
 
@@ -286,13 +288,13 @@
 	 *  クロック設定
 	 */
-    if(spi_num == 3){
-		sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_SPI3_CLK_SEL);
-	}
-	if(spi_num < 2)
-		sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB2_CLK_EN);
-	else if(spi_num == 2)
-		sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB0_CLK_EN);
-	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), (SYSCTL_CLK_EN_PERI_SPI0_CLK_EN<<spi_num));
-	sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_TH1), 0xFF << (spi_num*8));
+	if (spi_num == 3) {
+		sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0), SYSCTL_CLK_SEL0_SPI3_CLK_SEL);
+	}
+	if (spi_num < 2)
+		sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB2_CLK_EN);
+	else if (spi_num == 2)
+		sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_CENT), SYSCTL_CLK_EN_CENT_APB0_CLK_EN);
+	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), (SYSCTL_CLK_EN_PERI_SPI0_CLK_EN << spi_num));
+	sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_TH1), 0xFF << (spi_num * 8));
 
 	/*
@@ -300,19 +302,18 @@
 	 */
 	spcb = &spi_pcb[spi_num];
-	if(spcb->func_ss >= 0 && init->SsPin >= 0)
+	if (spcb->func_ss >= 0 && init->SsPin >= 0)
 		fpioa_set_function(init->SsPin, (uint8_t)(spcb->func_ss + init->SsNo));
-	if(spcb->func_sclk >= 0 && init->SclkPin >= 0)
+	if (spcb->func_sclk >= 0 && init->SclkPin >= 0)
 		fpioa_set_function(init->SclkPin, (uint8_t)(spcb->func_sclk));
-	if(spcb->func_data >= 0){
-		if(init->MosiPin >= 0)
+	if (spcb->func_data >= 0) {
+		if (init->MosiPin >= 0)
 			fpioa_set_function(init->MosiPin, (uint8_t)(spcb->func_data));
-		if(init->MisoPin >= 0)
-			fpioa_set_function(init->MisoPin, (uint8_t)(spcb->func_data+1));
-
+		if (init->MisoPin >= 0)
+			fpioa_set_function(init->MisoPin, (uint8_t)(spcb->func_data + 1));
 	}
 	hspi = &SpiHandle[spi_num];
 	base = spcb->base;
 
-    switch(spi_num){
+	switch (spi_num) {
 	case 0:
 	case 1:
@@ -331,15 +332,15 @@
 	}
 
-	switch(init->FrameFormat){
+	switch (init->FrameFormat) {
 	case SPI_FF_DUAL:
-		if(init->DataSize % 2 != 0)
+		if (init->DataSize % 2 != 0)
 			dsize_err = 1;
 		break;
 	case SPI_FF_QUAD:
-		if(init->DataSize % 4 != 0)
+		if (init->DataSize % 4 != 0)
 			dsize_err = 1;
 		break;
 	case SPI_FF_OCTAL:
-		if(init->DataSize % 8 != 0)
+		if (init->DataSize % 8 != 0)
 			dsize_err = 1;
 		break;
@@ -348,5 +349,5 @@
 	}
 
-	switch(init->InstLength){
+	switch (init->InstLength) {
 	case 0:
 		inst_l = 0;
@@ -364,5 +365,5 @@
 		break;
 	}
-	if(inst_l == 4 || dsize_err){
+	if (inst_l == 4 || dsize_err) {
 		syslog_0(LOG_ERROR, "Invalid instruction length");
 		return NULL;
@@ -372,37 +373,36 @@
 	memcpy(&hspi->Init, init, sizeof(SPI_Init_t));
 
-    if(sil_rew_mem((uint32_t *)(base+TOFF_SPI_BAUDR)) == 0)
-		sil_wrw_mem((uint32_t *)(base+TOFF_SPI_BAUDR), 0x14);
+	if (sil_rew_mem((uint32_t *)(base + TOFF_SPI_BAUDR)) == 0)
+		sil_wrw_mem((uint32_t *)(base + TOFF_SPI_BAUDR), 0x14);
 	/*
 	 *  割込み不許可
 	 */
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_IMR), 0x00000000);
-
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_DMACR), 0x00000000);
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_DMATDLR), 0x00000010);
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_DMARDLR), 0x00000000);
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_SER), 0x00000000);
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_CTRLR0), (init->WorkMode << work_mode_offset) | \
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_IMR), 0x00000000);
+
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMACR), 0x00000000);
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMATDLR), 0x00000010);
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_DMARDLR), 0x00000000);
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SER), 0x00000000);
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_CTRLR0), (init->WorkMode << work_mode_offset) |
 		(init->FrameFormat << frf_offset) | ((init->DataSize - 1) << dfs_offset));
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_SPI_CTRLR0),
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_SPI_CTRLR0),
 		((init->WaitCycles << 11) | (inst_l << 8) | (addr_l << 2) | init->IATransMode));
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_ENDIAN), init->SignBit);
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_ENDIAN), init->SignBit);
 
 	/*
 	 *  転送クロック設定
 	 */
-	clk_th1 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_TH1));
+	clk_th1 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_TH1));
 	threshold = (clk_th1 >> (spi_num * 8)) & 0xff;
 	spi_baudr = (get_pll_clock(0) / ((threshold + 1) * 2)) / init->Prescaler;
 
-
-	if(spi_baudr < 2 ){
+	if (spi_baudr < 2) {
 		spi_baudr = 2;
 	}
-	else if(spi_baudr > 65534){
+	else if (spi_baudr > 65534) {
 		spi_baudr = 65534;
 	}
-	sil_wrw_mem((uint32_t *)(base+TOFF_SPI_BAUDR), spi_baudr);
+	sil_wrw_mem((uint32_t *)(base + TOFF_SPI_BAUDR), spi_baudr);
 
 	/*
@@ -411,69 +411,69 @@
 	hspi->base = base;
 	hspi->spi_num = spi_num;
-	hspi->dfs_offset  = dfs_offset;
-	hspi->frf_offset  = frf_offset;
+	hspi->dfs_offset = dfs_offset;
+	hspi->frf_offset = frf_offset;
 	hspi->work_mode_offset = work_mode_offset;
 	hspi->tmod_offset = tmod_offset;
 	hspi->hdmatx = NULL;
 	hspi->hdmarx = NULL;
-	if(init->TxDMAChannel >= 0){
+	if (init->TxDMAChannel >= 0) {
 		hdma = &spi_dma_handle[init->TxDMAChannel][0];
 		hdma->chnum = init->TxDMAChannel;
-		if(init->RxDMAChannel >= 0)
-			hdma->xfercallback      = NULL;
+		if (init->RxDMAChannel >= 0)
+			hdma->xfercallback = NULL;
 		else
-			hdma->xfercallback      = spi_dma_comp;
-		hdma->errorcallback     = NULL;
-		hdma->Init.Request      = DMA_SELECT_SSI0_TX_REQ + spi_num * 2;	/* DMA選択 */
-		hdma->Init.Direction    = DMA_MEMORY_TO_PERIPH;	/* DMA転送方向 */
-		hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT;	/* ソースマルチブロックタイプ */
-		hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT;	/* デスティネーションマルチブロックタイプ */
-		hdma->Init.SrcHandShake = DMAC_HS_SOFTWARE;	/* ソースハンドシェイク */
-		hdma->Init.DrcHandShake = DMAC_HS_HARDWARE;	/* デスティネーションハンドシェイク */
-		hdma->Init.SrcHwhsPol   = DMAC_HWHS_POLARITY_LOW;	/* ソースハードウェアハンドシェイク極性 */
-		hdma->Init.DrcHwhsPol   = DMAC_HWHS_POLARITY_LOW;	/* デスティネーションハードウェアハンドシェイク極性 */
-		hdma->Init.Priority     = 4;	/* 優先度 */
-		hdma->Init.SrcMaster    = DMAC_MASTER1;	/* ソースマスター設定 */
-		hdma->Init.DstMaster    = DMAC_MASTER2;	/* デスティネーションマスター設定 */
-		hdma->Init.SrcInc       = DMAC_ADDR_INCREMENT;	/* ソースインクリメント設定 */
-		hdma->Init.DstInc       = DMAC_ADDR_NOCHANGE;	/* デスティネーションインクリメント設定 */
-		hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32;	/* ソース転送幅 */
-		hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32;	/* デスティネーション転送幅 */
-		hdma->Init.SrcBurstSize = DMAC_MSIZE_4;	/* ソースバーストサイズ */
-		hdma->Init.DstBurstSize = DMAC_MSIZE_4;	/* デスティネーションバーストサイズ */
-		hdma->Init.IocBlkTrans  = 0;	/* IOCブロック転送 */
-		hdma->localdata         = (void *)hspi;
+			hdma->xfercallback = spi_dma_comp;
+		hdma->errorcallback = NULL;
+		hdma->Init.Request = DMA_SELECT_SSI0_TX_REQ + spi_num * 2; /* DMA選択 */
+		hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;			   /* DMA転送方向 */
+		hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT;			   /* ソースマルチブロックタイプ */
+		hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT;			   /* デスティネーションマルチブロックタイプ */
+		hdma->Init.SrcHandShake = DMAC_HS_SOFTWARE;				   /* ソースハンドシェイク */
+		hdma->Init.DrcHandShake = DMAC_HS_HARDWARE;				   /* デスティネーションハンドシェイク */
+		hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW;			   /* ソースハードウェアハンドシェイク極性 */
+		hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW;			   /* デスティネーションハードウェアハンドシェイク極性 */
+		hdma->Init.Priority = 4;								   /* 優先度 */
+		hdma->Init.SrcMaster = DMAC_MASTER1;					   /* ソースマスター設定 */
+		hdma->Init.DstMaster = DMAC_MASTER2;					   /* デスティネーションマスター設定 */
+		hdma->Init.SrcInc = DMAC_ADDR_INCREMENT;				   /* ソースインクリメント設定 */
+		hdma->Init.DstInc = DMAC_ADDR_NOCHANGE;					   /* デスティネーションインクリメント設定 */
+		hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32;			   /* ソース転送幅 */
+		hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32;			   /* デスティネーション転送幅 */
+		hdma->Init.SrcBurstSize = DMAC_MSIZE_4;					   /* ソースバーストサイズ */
+		hdma->Init.DstBurstSize = DMAC_MSIZE_4;					   /* デスティネーションバーストサイズ */
+		hdma->Init.IocBlkTrans = 0;								   /* IOCブロック転送 */
+		hdma->localdata = (void *)hspi;
 		dma_init(hdma);
 		hspi->hdmatx = hdma;
 	}
-	if(init->RxDMAChannel >= 0){
+	if (init->RxDMAChannel >= 0) {
 		hdma = &spi_dma_handle[init->RxDMAChannel][1];
 		hdma->chnum = init->RxDMAChannel;
-		hdma->xfercallback      = spi_dma_comp;
-		hdma->errorcallback     = NULL;
-		hdma->Init.Request      = DMA_SELECT_SSI0_RX_REQ + spi_num * 2;	/* DMA選択 */
-		hdma->Init.Direction    = DMA_PERIPH_TO_MEMORY;	/* DMA転送方向 */
-		hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT;	/* ソースマルチブロックタイプ */
-		hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT;	/* デスティネーションマルチブロックタイプ */
-		hdma->Init.SrcHandShake = DMAC_HS_HARDWARE;	/* ソースハンドシェイク */
-		hdma->Init.DrcHandShake = DMAC_HS_SOFTWARE;	/* デスティネーションハンドシェイク */
-		hdma->Init.SrcHwhsPol   = DMAC_HWHS_POLARITY_LOW;	/* ソースハードウェアハンドシェイク極性 */
-		hdma->Init.DrcHwhsPol   = DMAC_HWHS_POLARITY_LOW;	/* デスティネーションハードウェアハンドシェイク極性 */
-		hdma->Init.Priority     = 4;	/* 優先度 */
-		hdma->Init.SrcMaster    = DMAC_MASTER1;	/* ソースマスター設定 */
-		hdma->Init.DstMaster    = DMAC_MASTER2;	/* デスティネーションマスター設定 */
-		hdma->Init.SrcInc       = DMAC_ADDR_NOCHANGE;	/* ソースインクリメント設定 */
-		hdma->Init.DstInc       = DMAC_ADDR_INCREMENT;	/* デスティネーションインクリメント設定 */
-		hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32;	/* ソース転送幅 */
-		hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32;	/* デスティネーション転送幅 */
-		hdma->Init.SrcBurstSize = DMAC_MSIZE_4;	/* ソースバーストサイズ */
-		hdma->Init.DstBurstSize = DMAC_MSIZE_4;	/* デスティネーションバーストサイズ */
-		hdma->Init.IocBlkTrans  = 0;	/* IOCブロック転送 */
-		hdma->localdata         = (void *)hspi;
+		hdma->xfercallback = spi_dma_comp;
+		hdma->errorcallback = NULL;
+		hdma->Init.Request = DMA_SELECT_SSI0_RX_REQ + spi_num * 2; /* DMA選択 */
+		hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;			   /* DMA転送方向 */
+		hdma->Init.SrcMultBlock = DMAC_MULTBLOCK_CONT;			   /* ソースマルチブロックタイプ */
+		hdma->Init.DrcMultBlock = DMAC_MULTBLOCK_CONT;			   /* デスティネーションマルチブロックタイプ */
+		hdma->Init.SrcHandShake = DMAC_HS_HARDWARE;				   /* ソースハンドシェイク */
+		hdma->Init.DrcHandShake = DMAC_HS_SOFTWARE;				   /* デスティネーションハンドシェイク */
+		hdma->Init.SrcHwhsPol = DMAC_HWHS_POLARITY_LOW;			   /* ソースハードウェアハンドシェイク極性 */
+		hdma->Init.DrcHwhsPol = DMAC_HWHS_POLARITY_LOW;			   /* デスティネーションハードウェアハンドシェイク極性 */
+		hdma->Init.Priority = 4;								   /* 優先度 */
+		hdma->Init.SrcMaster = DMAC_MASTER1;					   /* ソースマスター設定 */
+		hdma->Init.DstMaster = DMAC_MASTER2;					   /* デスティネーションマスター設定 */
+		hdma->Init.SrcInc = DMAC_ADDR_NOCHANGE;					   /* ソースインクリメント設定 */
+		hdma->Init.DstInc = DMAC_ADDR_INCREMENT;				   /* デスティネーションインクリメント設定 */
+		hdma->Init.SrcTransWidth = DMAC_TRANS_WIDTH_32;			   /* ソース転送幅 */
+		hdma->Init.DstTransWidth = DMAC_TRANS_WIDTH_32;			   /* デスティネーション転送幅 */
+		hdma->Init.SrcBurstSize = DMAC_MSIZE_4;					   /* ソースバーストサイズ */
+		hdma->Init.DstBurstSize = DMAC_MSIZE_4;					   /* デスティネーションバーストサイズ */
+		hdma->Init.IocBlkTrans = 0;								   /* IOCブロック転送 */
+		hdma->localdata = (void *)hspi;
 		dma_init(hdma);
 		hspi->hdmarx = hdma;
 	}
 	hspi->status = SPI_STATUS_READY;
-	hspi->xmode  = 0;
+	hspi->xmode = 0;
 	return hspi;
 }
@@ -487,16 +487,16 @@
 spi_deinit(SPI_Handle_t *hspi)
 {
-	if(hspi == NULL)
+	if (hspi == NULL)
 		return E_PAR;
 
-	if(hspi->hdmatx != NULL){
+	if (hspi->hdmatx != NULL) {
 		dma_deinit(hspi->hdmatx);
 		hspi->hdmatx = NULL;
 	}
-	if(hspi->hdmarx != NULL){
+	if (hspi->hdmarx != NULL) {
 		dma_deinit(hspi->hdmarx);
 		hspi->hdmarx = NULL;
 	}
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
 
 	hspi->ErrorCode = SPI_ERROR_NONE;
@@ -509,58 +509,79 @@
  */
 static void
-spi_send_data_normal2(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buff, size_t tx_len)
-{
-	size_t index, fifo_len;
+spi_send_data_normal(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buff, size_t tx_len)
+{
+	size_t fifo_len;
+	const uint32_t *src = (const uint32_t *)tx_buff;
+
+	if (ss_no < 0)
+		ss_no = 0;
+
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no));
+	while (tx_len > 0) {
+		fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_TXFLR));
+		fifo_len = fifo_len < tx_len ? fifo_len : tx_len;
+		uint32_t *dst = (uint32_t *)(hspi->base + TOFF_SPI_DR);
+		uint32_t *end = &dst[fifo_len];
+		for (; dst < end; src++, dst++) {
+			sil_wrw_mem(dst, *src);
+		}
+		tx_len -= fifo_len;
+
+		int tick = 200;
+		//sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011);
+		while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) {
+			//if(hspi->Init.semid != 0)
+			//	twai_sem(hspi->Init.semid, 1);
+			//else
+			//	dly_tsk(1);
+			tick--;
+		}
+	}
+}
+
+/*
+ *  ポーリングデータ送信
+ */
+static void
+spi_send_data_normal2(SPI_Handle_t *hspi, int8_t ss_no, uint32_t tx_data, size_t tx_len)
+{
+	size_t fifo_len;
 	uint8_t frame_width = get_framewidth(hspi->Init.DataSize);
-	uint8_t v_misalign_flag = 0;
-	uint32_t v_send_data;
-	uint32_t i = 0;
-
-	if((uintptr_t)tx_buff % frame_width){
-		v_misalign_flag = 1;
-	}
-	if(ss_no < 0)
+
+	switch (frame_width)
+	{
+	case 2:
+		tx_data = (tx_data << 16) | (tx_data & 0xFFFF);
+		break;
+	case 1:
+		tx_data = (tx_data << 24) | ((tx_data << 16) & 0xFF0000) | ((tx_data << 8) & 0xFF00) | (tx_data & 0xFF);
+		break;
+	}
+
+	if (ss_no < 0)
 		ss_no = 0;
 
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), (1 << ss_no));
-	while(tx_len > 0){
-		fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_TXFLR));
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), (1 << ss_no));
+	while (tx_len > 0) {
+		fifo_len = 32 - sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_TXFLR));
 		fifo_len = fifo_len < tx_len ? fifo_len : tx_len;
-		switch(frame_width){
-		case SPI_TRANS_INT:
-			fifo_len = fifo_len / 4 * 4;
-			if(v_misalign_flag){
-				for(index = 0; index < fifo_len; index +=4){
-					memcpy(&v_send_data, tx_buff + i , 4);
-					sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), v_send_data);
-					i += 4;
-				}
-			}
-			else{
-				for(index = 0; index < fifo_len / 4; index++)
-					sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), ((uint32_t *)tx_buff)[i++]);
-			}
-			break;
-		case SPI_TRANS_SHORT:
-			fifo_len = fifo_len / 2 * 2;
-			if(v_misalign_flag){
-				for(index = 0; index < fifo_len; index +=2){
-					memcpy(&v_send_data, tx_buff + i, 2);
-					sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), v_send_data);
-					i += 2;
-				}
-			}
-			else{
-				for(index = 0; index < fifo_len / 2; index++)
-					sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), ((uint16_t *)tx_buff)[i++]);
-			}
-			break;
-		default:
-			for(index = 0; index < fifo_len; index++)
-				sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), tx_buff[i++]);
-			break;
- 		}
+		uint32_t *dst = (uint32_t *)(hspi->base + TOFF_SPI_DR);
+		uint32_t *end = &dst[fifo_len];
+		for (; dst < end; dst++) {
+			sil_wrw_mem(dst, tx_data);
+		}
 		tx_len -= fifo_len;
+
+		int tick = 200;
+		//sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0x0011);
+		while ((sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_SR)) & 0x05) != 0x04 && tick > 0) {
+			//if(hspi->Init.semid != 0)
+			//	twai_sem(hspi->Init.semid, 1);
+			//else
+			//	dly_tsk(1);
+			tick--;
+		}
 	}
 }
@@ -580,21 +601,22 @@
 	ER ercd = E_OK;
 
-	if(hspi == NULL)
+	if (hspi == NULL)
 		return E_PAR;
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		wai_sem(hspi->Init.semlock);
+
 	hspi->xmode = SPI_XMODE_TX;
-    spi_set_tmod(hspi, SPI_TMOD_TRANS);
-	if(hspi->hdmatx != NULL){
-		sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_TXENABLE);
-		sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
-		hdma = spi_dmac_set_single_mode(hspi, 0, ss_no, (const void *)pdata, 
-							(void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
-							DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length);
+	spi_set_tmod(hspi, SPI_TMOD_TRANS);
+	if (hspi->hdmatx != NULL) {
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_TXENABLE);
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
+		hdma = spi_dmac_set_single_mode(hspi, 0, ss_no, (const void *)pdata,
+										(void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
+										DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, length);
 		spi_dmac_wait_done(hdma);
 	}
-	else{
-		spi_send_data_normal2(hspi, ss_no, (const void *)pdata, length);
+	else {
+		spi_send_data_normal(hspi, ss_no, (const void *)pdata, length);
 	}
 
@@ -602,5 +624,5 @@
 	ercd = spi_inwait(hspi, SPI_WAIT_TIME * length);
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		sig_sem(hspi->Init.semlock);
 #endif
@@ -622,23 +644,28 @@
 	ER ercd = E_OK;
 
-	if(hspi == NULL)
+	if (hspi == NULL)
 		return E_PAR;
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		wai_sem(hspi->Init.semlock);
 
 	hspi->xmode = SPI_XMODE_TX;
 	spi_set_tmod(hspi, SPI_TMOD_TRANS);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_TXENABLE);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
-
-    hdmatx = spi_dmac_set_single_mode(hspi, 0, ss_no, tx_buff, (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
-                                DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len);
-    spi_dmac_wait_done(hdmatx);
-
+	if (hspi->hdmatx != NULL) {
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_TXENABLE);
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
+
+		hdmatx = spi_dmac_set_single_mode(hspi, 0, ss_no, tx_buff,
+			(void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
+			DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, tx_len);
+		spi_dmac_wait_done(hdmatx);
+	}
+	else {
+		spi_send_data_normal2(hspi, ss_no, *tx_buff, tx_len);
+	}
 #if SPI_WAIT_TIME != 0
 	ercd = spi_inwait(hspi, SPI_WAIT_TIME * tx_len);
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		sig_sem(hspi->Init.semlock);
 #endif
@@ -657,11 +684,11 @@
 spi_core_receive(SPI_Handle_t *hspi, int8_t ss_no, void *rx_buff, size_t rx_len)
 {
-	DMA_Handle_t * hdmarx;
+	DMA_Handle_t *hdmarx;
 	ER ercd = E_OK;
 
-	if(hspi == NULL || hspi->spi_num == 2)
+	if (hspi == NULL || hspi->spi_num == 2)
 		return E_PAR;
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		wai_sem(hspi->Init.semlock);
 
@@ -669,21 +696,22 @@
 	spi_set_tmod(hspi, SPI_TMOD_RECV);
 
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_CTRLR1), (rx_len - 1));
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_RXENABLE);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
-
-    hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
-                           DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len);
-    if(hspi->Init.FrameFormat == SPI_FF_STANDARD)
-		sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DR), 0xFFFFFFFF);
-    spi_dmac_wait_done(hdmarx);
-
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), 0x00000000);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_CTRLR1), (rx_len - 1));
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_RXENABLE);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
+
+	hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no,
+		(void *)(hspi->base + TOFF_SPI_DR), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
+		DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len);
+	if (hspi->Init.FrameFormat == SPI_FF_STANDARD)
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DR), 0xFFFFFFFF);
+	spi_dmac_wait_done(hdmarx);
+
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
 
 #if SPI_WAIT_TIME != 0
 	ercd = spi_inwait(hspi, SPI_WAIT_TIME * rx_len);
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		sig_sem(hspi->Init.semlock);
 #endif
@@ -703,47 +731,47 @@
 spi_core_transrecv(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buf, uint8_t *rx_buf, size_t len)
 {
-	DMA_Handle_t * hdmarx, *hdmatx;
-    uint8_t frame_width = get_framewidth(hspi->Init.DataSize);
-    size_t v_len = len / frame_width;
+	DMA_Handle_t *hdmarx, *hdmatx;
+	uint8_t frame_width = get_framewidth(hspi->Init.DataSize);
+	size_t v_len = len / frame_width;
 	ER ercd = E_OK;
 
-	if(hspi == NULL)
+	if (hspi == NULL)
 		return E_PAR;
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		wai_sem(hspi->Init.semlock);
 
 	hspi->xmode = SPI_XMODE_TXRX;
-    spi_set_tmod(hspi, SPI_TMOD_TRANS_RECV);
-
-
-	if(hspi->hdmatx != NULL){
-		sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), (SPI_DMACR_TXENABLE | SPI_DMACR_RXENABLE));
-		sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
-
-	    hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
-                           DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len);
-	    hdmatx = spi_dmac_set_single_mode(hspi, 0, -1, tx_buf, (void *)(hspi->base+TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
-                           DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_len);
-
-	    spi_dmac_wait_done(hdmatx);
-	}
-	else{
-		sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_DMACR), SPI_DMACR_RXENABLE);
-		sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
-
-	    hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base+TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
-                           DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len);
-		spi_send_data_normal2(hspi, -1, (const void *)tx_buf, len);
+	spi_set_tmod(hspi, SPI_TMOD_TRANS_RECV);
+
+	if (hspi->hdmatx != NULL) {
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), (SPI_DMACR_TXENABLE | SPI_DMACR_RXENABLE));
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
+
+		hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no, (void *)(hspi->base + TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
+										  DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len);
+		hdmatx = spi_dmac_set_single_mode(hspi, 0, -1, tx_buf, (void *)(hspi->base + TOFF_SPI_DR), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
+										  DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_len);
+
+		spi_dmac_wait_done(hdmatx);
+	}
+	else {
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_DMACR), SPI_DMACR_RXENABLE);
+		sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_ENABLE);
+
+		hdmarx = spi_dmac_set_single_mode(hspi, 1, ss_no,
+			(void *)(hspi->base + TOFF_SPI_DR), rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
+			DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_len);
+		spi_send_data_normal(hspi, -1, (const void *)tx_buf, len);
 	}
 	spi_dmac_wait_done(hdmarx);
 
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SER), 0x00000000);
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SER), 0x00000000);
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_SSIENR), SPI_SSIENR_DISABLE);
 
 #if SPI_WAIT_TIME != 0
 	ercd = spi_inwait(hspi, SPI_WAIT_TIME * len);
 
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		sig_sem(hspi->Init.semlock);
 #endif
@@ -760,8 +788,8 @@
 
 #if SPI_WAIT_TIME == 0
-	if(hspi == NULL)
+	if (hspi == NULL)
 		return E_PAR;
 	ercd = spi_inwait(hspi, timeout);
-	if(hspi->Init.semlock != 0)
+	if (hspi->Init.semlock != 0)
 		sig_sem(hspi->Init.semlock);
 #endif
@@ -769,5 +797,4 @@
 }
 
-
 /*
  *  SPI割込みサービスルーチン
@@ -776,13 +803,14 @@
 spi_handler(SPI_Handle_t *hspi)
 {
-	volatile uint32_t imr, isr, tmp;
-
-	imr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR));
-	isr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ISR));
-	sil_wrw_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR), 0);
-
-	syslog_2(LOG_DEBUG, "spi_handler imr[%08x] isr[%08x]", imr, isr);
-	tmp = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ICR));
-	if(hspi->Init.semid != 0)
+	//volatile uint32_t imr, isr;
+	volatile uint32_t tmp;
+
+	//imr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_IMR));
+	//isr = sil_rew_mem((uint32_t *)(hspi->base+TOFF_SPI_ISR));
+	sil_wrw_mem((uint32_t *)(hspi->base + TOFF_SPI_IMR), 0);
+
+	//syslog_2(LOG_DEBUG, "spi_handler imr[%08x] isr[%08x]", imr, isr);
+	tmp = sil_rew_mem((uint32_t *)(hspi->base + TOFF_SPI_ICR));
+	if (hspi->Init.semid != 0)
 		isig_sem(hspi->Init.semid);
 	(void)(tmp);
@@ -794,6 +822,4 @@
 void spi_isr(intptr_t exinf)
 {
-  spi_handler(&SpiHandle[INDEX_SPI((uint32_t)exinf)]);
-}
-
-
+	spi_handler(&SpiHandle[INDEX_SPI((uint32_t)exinf)]);
+}
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.h
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.h	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi.h	(revision 458)
@@ -49,5 +49,5 @@
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
@@ -55,160 +55,156 @@
  *  SPIポート定義
  */
-#define SPI1_PORTID             1
-#define SPI2_PORTID             2
-#define SPI3_PORTID             3
-#define SPI4_PORTID             3
-#define NUM_SPIPORT             4
-
+#define SPI1_PORTID 1
+#define SPI2_PORTID 2
+#define SPI3_PORTID 3
+#define SPI4_PORTID 3
+#define NUM_SPIPORT 4
 
 /*
  *  SPI状態定義
  */
-#define SPI_STATUS_RESET        0x0000	/* SPI未使用状態 */
-#define SPI_STATUS_READY        0x0001	/* SPIレディ状態 */
-#define SPI_STATUS_ERROR        0x0002	/* SPIエラー状態 */
-#define SPI_STATUS_BUSY         0x0004	/* SPI処理中 */
+#define SPI_STATUS_RESET 0x0000 /* SPI未使用状態 */
+#define SPI_STATUS_READY 0x0001 /* SPIレディ状態 */
+#define SPI_STATUS_ERROR 0x0002 /* SPIエラー状態 */
+#define SPI_STATUS_BUSY 0x0004	/* SPI処理中 */
 
 /*
  *  SPI転送モード
  */
-#define SPI_XMODE_TX            0x0000	/* 送信モード */
-#define SPI_XMODE_RX            0x0001	/* 受信モード */
-#define SPI_XMODE_TXRX          0x0002	/* 送受信モード */
+#define SPI_XMODE_TX 0x0000	  /* 送信モード */
+#define SPI_XMODE_RX 0x0001	  /* 受信モード */
+#define SPI_XMODE_TXRX 0x0002 /* 送受信モード */
 
 /*
  *  SPIエラー定義
  */
-#define SPI_ERROR_NONE          0x00000000	/* No error */
-#define SPI_ERROR_MODF          0x00000001	/* MODF error */
-#define SPI_ERROR_CRC           0x00000002	/* CRC error */
-#define SPI_ERROR_OVR           0x00000004	/* OVR error */
-#define SPI_ERROR_FRE           0x00000008	/* FRE error */
-#define SPI_ERROR_DMA           0x00000010	/* DMA transfer error */
-#define SPI_ERROR_TIMEOUT       0x00000020
+#define SPI_ERROR_NONE 0x00000000 /* No error */
+#define SPI_ERROR_MODF 0x00000001 /* MODF error */
+#define SPI_ERROR_CRC 0x00000002  /* CRC error */
+#define SPI_ERROR_OVR 0x00000004  /* OVR error */
+#define SPI_ERROR_FRE 0x00000008  /* FRE error */
+#define SPI_ERROR_DMA 0x00000010  /* DMA transfer error */
+#define SPI_ERROR_TIMEOUT 0x00000020
 
 /*
  *  SPIワークモード定義
  */
-#define SPI_WORK_MODE_0         0x00000000
-#define SPI_WORK_MODE_1         0x00000001
-#define SPI_WORK_MODE_2         0x00000002
-#define SPI_WORK_MODE_3         0x00000003
+#define SPI_WORK_MODE_0 0x00000000
+#define SPI_WORK_MODE_1 0x00000001
+#define SPI_WORK_MODE_2 0x00000002
+#define SPI_WORK_MODE_3 0x00000003
 
 /*
  *  SPIフレームフォーマット定義
  */
-#define SPI_FF_STANDARD         0x00000000
-#define SPI_FF_DUAL             0x00000001
-#define SPI_FF_QUAD             0x00000002
-#define SPI_FF_OCTAL            0x00000003
+#define SPI_FF_STANDARD 0x00000000
+#define SPI_FF_DUAL 0x00000001
+#define SPI_FF_QUAD 0x00000002
+#define SPI_FF_OCTAL 0x00000003
 
 /*
  *  SPIインストラクションアドレスモード
  */
-#define SPI_AITM_STANDARD        0x00000000
-#define SPI_AITM_ADDR_STANDARD   0x00000001
+#define SPI_AITM_STANDARD 0x00000000
+#define SPI_AITM_ADDR_STANDARD 0x00000001
 #define SPI_AITM_AS_FRAME_FORMAT 0x00000002
 
-
 /*
  *  SPI転送モード定義
  */
-#define SPI_TMOD_TRANS_RECV     0x00000000
-#define SPI_TMOD_TRANS          0x00000001
-#define SPI_TMOD_RECV           0x00000002
-#define SPI_TMOD_EEROM          0x00000003
+#define SPI_TMOD_TRANS_RECV 0x00000000
+#define SPI_TMOD_TRANS 0x00000001
+#define SPI_TMOD_RECV 0x00000002
+#define SPI_TMOD_EEROM 0x00000003
 
 /*
  *  SPI転送データ長定義
  */
-#define SPI_TRANS_CHAR          0x01
-#define SPI_TRANS_SHORT         0x02
-#define SPI_TRANS_INT           0x04
+#define SPI_TRANS_CHAR 0x01
+#define SPI_TRANS_SHORT 0x02
+#define SPI_TRANS_INT 0x04
 
 /*
  *  SPI CS選択定義
  */
-#define SPI_CHIP_SELECT_0       0x00
-#define SPI_CHIP_SELECT_1       0x01
-#define SPI_CHIP_SELECT_2       0x02
-#define SPI_CHIP_SELECT_3       0x03
-#define SPI_CHIP_SELECT_MAX     4
-
-/*
+#define SPI_CHIP_SELECT_0 0x00
+#define SPI_CHIP_SELECT_1 0x01
+#define SPI_CHIP_SELECT_2 0x02
+#define SPI_CHIP_SELECT_3 0x03
+#define SPI_CHIP_SELECT_MAX 4
+
+	/*
  *  SPI 設定初期設定構造体
  */
-typedef struct
-{
-	uint32_t              WorkMode;
-	uint32_t              FrameFormat;
-    uint32_t              DataSize;			/* SPI転送データサイズ */
-	uint32_t              Prescaler;		/* SPIクロック分周設定 */
-	uint32_t              SignBit;			/* SPI MSB/LSB設定 */
-	uint32_t              InstLength;		/* SPI Instraction Length */
-	uint32_t              AddrLength;		/* SPI Address Length */
-	uint32_t              WaitCycles;		/* SPI WaitCycles */
-	uint32_t              IATransMode;		/* SPI 転送モード */
-	int32_t               SclkPin;			/* SPI SCLK-PIN */
-	int32_t               MosiPin;			/* SPI MOSI-PIN */
-	int32_t               MisoPin;			/* SPI MISO-PIN */
-	int32_t               SsPin;			/* SPI Slave Select-PIN */
-	int32_t               SsNo;				/* SPI Slave Select-Number */
-	int32_t               TxDMAChannel;		/* SPI TxDMAチャンネル */
-	int32_t               RxDMAChannel;		/* SPI RxDMAチャンネル */
-	int                   semid;			/* SPI 通信用セマフォ値 */
-	int                   semlock;			/* SPI ロックセマフォ値 */
-	int                   semdmaid;			/* SPI DMA通信用セマフォ値 */
-}SPI_Init_t;
-
-/*
+	typedef struct
+	{
+		uint32_t WorkMode;
+		uint32_t FrameFormat;
+		uint32_t DataSize;	  /* SPI転送データサイズ */
+		uint32_t Prescaler;	  /* SPIクロック分周設定 */
+		uint32_t SignBit;	  /* SPI MSB/LSB設定 */
+		uint32_t InstLength;  /* SPI Instraction Length */
+		uint32_t AddrLength;  /* SPI Address Length */
+		uint32_t WaitCycles;  /* SPI WaitCycles */
+		uint32_t IATransMode; /* SPI 転送モード */
+		int32_t SclkPin;	  /* SPI SCLK-PIN */
+		int32_t MosiPin;	  /* SPI MOSI-PIN */
+		int32_t MisoPin;	  /* SPI MISO-PIN */
+		int32_t SsPin;		  /* SPI Slave Select-PIN */
+		int32_t SsNo;		  /* SPI Slave Select-Number */
+		int32_t TxDMAChannel; /* SPI TxDMAチャンネル */
+		int32_t RxDMAChannel; /* SPI RxDMAチャンネル */
+		int semid;			  /* SPI 通信用セマフォ値 */
+		int semlock;		  /* SPI ロックセマフォ値 */
+		int semdmaid;		  /* SPI DMA通信用セマフォ値 */
+	} SPI_Init_t;
+
+	/*
  *  SPIハンドラ
  */
-typedef struct _SPI_Handle_t
-{
-	unsigned long         base;				/* SPI registers base address */
-	SPI_Init_t            Init;				/* SPI communication parameters */
-	uint8_t               spi_num;
-	uint8_t               dfs_offset;
-	uint8_t               frf_offset;
-	uint8_t               work_mode_offset;
-	uint8_t               tmod_offset;
-	uint8_t               dummy[3];
-	uint8_t               *pTxBuffPtr;		/* Pointer to SPI Tx transfer Buffer */
-	uint32_t              TxXferSize;		/* SPI Tx transfer size */
-	uint32_t              TxXferCount;		/* SPI Tx Transfer Counter */
-	uint8_t               *pRxBuffPtr;		/* Pointer to SPI Rx transfer Buffer */
-	uint32_t              RxXferSize;		/* SPI Rx transfer size */
-	uint32_t              RxXferCount;		/* SPI Rx Transfer Counter */
-	DMA_Handle_t          *hdmatx;			/* SPI Tx DMA handle parameters */
-	DMA_Handle_t          *hdmarx;			/* SPI Rx DMA handle parameters */
-	uint16_t              xmode;			/* SPI Transfar mode */
-	volatile uint16_t     status;			/* SPI communication state */
-	volatile uint32_t     ErrorCode;		/* SPI Error code */
-}SPI_Handle_t;
-
-
-extern SPI_Handle_t *spi_init(ID port, const SPI_Init_t *init);
-extern ER spi_deinit(SPI_Handle_t *hspi);
-extern ER spi_core_transmit(SPI_Handle_t *hspi, int8_t ss_no, uint8_t *pdata, uint16_t length);
-extern ER spi_core_transmit_fill(SPI_Handle_t *hspi, int8_t ss_no, const uint32_t *tx_buff, size_t tx_len);
-extern ER spi_core_receive(SPI_Handle_t *hspi, int8_t ss_no, void *rx_buff, size_t rx_len);
-extern ER spi_core_transrecv(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buf, uint8_t *rx_buf, size_t len);
-extern ER spi_transmit(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length);
-extern ER spi_receive(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length);
-extern ER spi_transrecv(SPI_Handle_t *hspi, uint8_t *ptxData, uint8_t *prxData, uint16_t length);
-extern ER spi_wait(SPI_Handle_t *hspi, uint32_t timeout);
-extern void spi_handler(SPI_Handle_t *hspi);
-extern void spi_isr(intptr_t exinf);
-extern DMA_Handle_t *spi_dmac_set_single_mode(SPI_Handle_t *hspi, 
-                          uint8_t rtx,
-						  int8_t  ss_no,
-                          const void *src, void *dest, uint8_t src_inc,
-                          uint8_t dest_inc,
-                          uint8_t dmac_burst_size,
-                          uint8_t dmac_trans_width,
-                          size_t block_size);
-extern ER spi_dmac_wait_done(DMA_Handle_t * hdma);
-
+	typedef struct _SPI_Handle_t
+	{
+		unsigned long base; /* SPI registers base address */
+		SPI_Init_t Init;	/* SPI communication parameters */
+		uint8_t spi_num;
+		uint8_t dfs_offset;
+		uint8_t frf_offset;
+		uint8_t work_mode_offset;
+		uint8_t tmod_offset;
+		uint8_t dummy[3];
+		uint8_t *pTxBuffPtr;		 /* Pointer to SPI Tx transfer Buffer */
+		uint32_t TxXferSize;		 /* SPI Tx transfer size */
+		uint32_t TxXferCount;		 /* SPI Tx Transfer Counter */
+		uint8_t *pRxBuffPtr;		 /* Pointer to SPI Rx transfer Buffer */
+		uint32_t RxXferSize;		 /* SPI Rx transfer size */
+		uint32_t RxXferCount;		 /* SPI Rx Transfer Counter */
+		DMA_Handle_t *hdmatx;		 /* SPI Tx DMA handle parameters */
+		DMA_Handle_t *hdmarx;		 /* SPI Rx DMA handle parameters */
+		uint16_t xmode;				 /* SPI Transfar mode */
+		volatile uint16_t status;	 /* SPI communication state */
+		volatile uint32_t ErrorCode; /* SPI Error code */
+	} SPI_Handle_t;
+
+	extern SPI_Handle_t *spi_init(ID port, const SPI_Init_t *init);
+	extern ER spi_deinit(SPI_Handle_t *hspi);
+	extern ER spi_core_transmit(SPI_Handle_t *hspi, int8_t ss_no, uint8_t *pdata, uint16_t length);
+	extern ER spi_core_transmit_fill(SPI_Handle_t *hspi, int8_t ss_no, const uint32_t *tx_buff, size_t tx_len);
+	extern ER spi_core_receive(SPI_Handle_t *hspi, int8_t ss_no, void *rx_buff, size_t rx_len);
+	extern ER spi_core_transrecv(SPI_Handle_t *hspi, int8_t ss_no, const uint8_t *tx_buf, uint8_t *rx_buf, size_t len);
+	extern ER spi_transmit(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length);
+	extern ER spi_receive(SPI_Handle_t *hspi, uint8_t *pdata, uint16_t length);
+	extern ER spi_transrecv(SPI_Handle_t *hspi, uint8_t *ptxData, uint8_t *prxData, uint16_t length);
+	extern ER spi_wait(SPI_Handle_t *hspi, uint32_t timeout);
+	extern void spi_handler(SPI_Handle_t *hspi);
+	extern void spi_isr(intptr_t exinf);
+	extern DMA_Handle_t *spi_dmac_set_single_mode(SPI_Handle_t *hspi,
+												  uint8_t rtx,
+												  int8_t ss_no,
+												  const void *src, void *dest, uint8_t src_inc,
+												  uint8_t dest_inc,
+												  uint8_t dmac_burst_size,
+												  uint8_t dmac_trans_width,
+												  size_t block_size);
+	extern ER spi_dmac_wait_done(DMA_Handle_t *hdma);
 
 #ifdef __cplusplus
@@ -216,4 +212,3 @@
 #endif
 
-#endif	/* _SPI_H_ */
-
+#endif /* _SPI_H_ */
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi_reg.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi_reg.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/pdic/k210/spi_reg.c	(revision 458)
@@ -169,3 +169,2 @@
 	return ercd;
 }
-
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/logtask.h
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/logtask.h	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/logtask.h	(revision 458)
@@ -62,5 +62,5 @@
 
 #ifndef LOGTASK_STACK_SIZE
-#define LOGTASK_STACK_SIZE	1024	/* スタック領域のサイズ */
+#define LOGTASK_STACK_SIZE	2048	/* スタック領域のサイズ */
 #endif /* LOGTASK_STACK_SIZE */
 
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/malloc.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/malloc.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/malloc.c	(revision 458)
@@ -307,7 +307,8 @@
 		ER ret;
 		if (sense_context())
-			ret = iloc_cpu();
+			//ret = iloc_cpu();
+			ret = E_CTX;
 		else
-			ret = loc_cpu();
+			ret = wai_sem(MALLOC_SEM);
 		if (ret != E_OK)
 			syslog_1(LOG_ERROR, "__malloc_unlock: count[%d] loc_cpu", malloc_lock_count);
@@ -322,7 +323,8 @@
 		ER ret;
 		if (sense_context())
-			ret = iunl_cpu();
+			//ret = iunl_cpu();
+			ret = E_CTX;
 		else
-			ret = unl_cpu();
+			ret = sig_sem(MALLOC_SEM);
 		if (ret != E_OK)
 			syslog_1(LOG_ERROR, "__malloc_unlock: count[%d] unl_cpu error !", malloc_lock_count);
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/malloc.cfg
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/malloc.cfg	(revision 458)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/malloc.cfg	(revision 458)
@@ -0,0 +1,5 @@
+/*
+ *  $Id$
+ */
+CRE_SEM(MALLOC_SEM, { TA_NULL, 1, 1 });
+
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/serial.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/serial.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/syssvc/serial.c	(revision 458)
@@ -56,56 +56,56 @@
  */
 #ifndef SERIAL_RCV_BUFSZ1
-#define	SERIAL_RCV_BUFSZ1	256			/* ポート1の受信バッファサイズ */
-#endif /* SERIAL_RCV_BUFSZ1 */
+#define SERIAL_RCV_BUFSZ1 256 /* ポート1の受信バッファサイズ */
+#endif						  /* SERIAL_RCV_BUFSZ1 */
 
 #ifndef SERIAL_SND_BUFSZ1
-#define	SERIAL_SND_BUFSZ1	256			/* ポート1の送信バッファサイズ */
-#endif /* SERIAL_SND_BUFSZ1 */
-
-static char	rcv_buffer1[SERIAL_RCV_BUFSZ1];
-static char	snd_buffer1[SERIAL_SND_BUFSZ1];
-
-#if TNUM_PORT >= 2						/* ポート2に関する定義 */
+#define SERIAL_SND_BUFSZ1 256 /* ポート1の送信バッファサイズ */
+#endif						  /* SERIAL_SND_BUFSZ1 */
+
+static char rcv_buffer1[SERIAL_RCV_BUFSZ1];
+static char snd_buffer1[SERIAL_SND_BUFSZ1];
+
+#if TNUM_PORT >= 2 /* ポート2に関する定義 */
 
 #ifndef SERIAL_RCV_BUFSZ2
-#define	SERIAL_RCV_BUFSZ2	256			/* ポート2の受信バッファサイズ */
-#endif /* SERIAL_RCV_BUFSZ2 */
+#define SERIAL_RCV_BUFSZ2 256 /* ポート2の受信バッファサイズ */
+#endif						  /* SERIAL_RCV_BUFSZ2 */
 
 #ifndef SERIAL_SND_BUFSZ2
-#define	SERIAL_SND_BUFSZ2	256			/* ポート2の送信バッファサイズ */
-#endif /* SERIAL_SND_BUFSZ2 */
-
-static char	rcv_buffer2[SERIAL_RCV_BUFSZ2];
-static char	snd_buffer2[SERIAL_SND_BUFSZ2];
+#define SERIAL_SND_BUFSZ2 256 /* ポート2の送信バッファサイズ */
+#endif						  /* SERIAL_SND_BUFSZ2 */
+
+static char rcv_buffer2[SERIAL_RCV_BUFSZ2];
+static char snd_buffer2[SERIAL_SND_BUFSZ2];
 
 #endif /* TNUM_PORT >= 2 */
 
-#if TNUM_PORT >= 3						/* ポート3に関する定義 */
+#if TNUM_PORT >= 3 /* ポート3に関する定義 */
 
 #ifndef SERIAL_RCV_BUFSZ3
-#define	SERIAL_RCV_BUFSZ3	256			/* ポート3の受信バッファサイズ */
-#endif /* SERIAL_RCV_BUFSZ3 */
+#define SERIAL_RCV_BUFSZ3 256 /* ポート3の受信バッファサイズ */
+#endif						  /* SERIAL_RCV_BUFSZ3 */
 
 #ifndef SERIAL_SND_BUFSZ3
-#define	SERIAL_SND_BUFSZ3	256			/* ポート3の送信バッファサイズ */
-#endif /* SERIAL_SND_BUFSZ3 */
-
-static char	rcv_buffer3[SERIAL_RCV_BUFSZ3];
-static char	snd_buffer3[SERIAL_SND_BUFSZ3];
+#define SERIAL_SND_BUFSZ3 256 /* ポート3の送信バッファサイズ */
+#endif						  /* SERIAL_SND_BUFSZ3 */
+
+static char rcv_buffer3[SERIAL_RCV_BUFSZ3];
+static char snd_buffer3[SERIAL_SND_BUFSZ3];
 
 #endif /* TNUM_PORT >= 3 */
 
-#if TNUM_PORT >= 4						/* ポート4に関する定義 */
+#if TNUM_PORT >= 4 /* ポート4に関する定義 */
 
 #ifndef SERIAL_RCV_BUFSZ4
-#define	SERIAL_RCV_BUFSZ4	256			/* ポート4の受信バッファサイズ */
-#endif /* SERIAL_RCV_BUFSZ4 */
+#define SERIAL_RCV_BUFSZ4 256 /* ポート4の受信バッファサイズ */
+#endif						  /* SERIAL_RCV_BUFSZ4 */
 
 #ifndef SERIAL_SND_BUFSZ4
-#define	SERIAL_SND_BUFSZ4	256			/* ポート4の送信バッファサイズ */
-#endif /* SERIAL_SND_BUFSZ4 */
-
-static char	rcv_buffer4[SERIAL_RCV_BUFSZ4];
-static char	snd_buffer4[SERIAL_SND_BUFSZ4];
+#define SERIAL_SND_BUFSZ4 256 /* ポート4の送信バッファサイズ */
+#endif						  /* SERIAL_SND_BUFSZ4 */
+
+static char rcv_buffer4[SERIAL_RCV_BUFSZ4];
+static char snd_buffer4[SERIAL_SND_BUFSZ4];
 
 #endif /* TNUM_PORT >= 4 */
@@ -118,9 +118,9 @@
  *  フロー制御に関連する定数とマクロ
  */
-#define	FC_STOP			'\023'		/* コントロール-S */
-#define	FC_START		'\021'		/* コントロール-Q */
-
-#define BUFCNT_STOP(bufsz)		((bufsz) * 3 / 4)	/* STOPを送る基準文字数 */
-#define BUFCNT_START(bufsz)		((bufsz) / 2)		/* STARTを送る基準文字数 */
+#define FC_STOP '\023'	/* コントロール-S */
+#define FC_START '\021' /* コントロール-Q */
+
+#define BUFCNT_STOP(bufsz) ((bufsz)*3 / 4) /* STOPを送る基準文字数 */
+#define BUFCNT_START(bufsz) ((bufsz) / 2)  /* STARTを送る基準文字数 */
 
 /*
@@ -128,30 +128,30 @@
  */
 typedef struct serial_port_initialization_block {
-	ID		rcv_semid;		/* 受信バッファ管理用セマフォのID */
-	ID		snd_semid;		/* 送信バッファ管理用セマフォのID */
-	uint_t	rcv_bufsz;		/* 受信バッファサイズ */
-	char	*rcv_buffer;	/* 受信バッファ */
-	uint_t	snd_bufsz;		/* 送信バッファサイズ */
-	char	*snd_buffer;	/* 送信バッファ */
+	ID rcv_semid;	  /* 受信バッファ管理用セマフォのID */
+	ID snd_semid;	  /* 送信バッファ管理用セマフォのID */
+	uint_t rcv_bufsz; /* 受信バッファサイズ */
+	char *rcv_buffer; /* 受信バッファ */
+	uint_t snd_bufsz; /* 送信バッファサイズ */
+	char *snd_buffer; /* 送信バッファ */
 } SPINIB;
 
 static const SPINIB spinib_table[TNUM_PORT] = {
-	{ SERIAL_RCV_SEM1, SERIAL_SND_SEM1,
-	  SERIAL_RCV_BUFSZ1, rcv_buffer1,
-	  SERIAL_SND_BUFSZ1, snd_buffer1 },
+	{SERIAL_RCV_SEM1, SERIAL_SND_SEM1,
+	 SERIAL_RCV_BUFSZ1, rcv_buffer1,
+	 SERIAL_SND_BUFSZ1, snd_buffer1},
 #if TNUM_PORT >= 2
-	{ SERIAL_RCV_SEM2, SERIAL_SND_SEM2,
-	  SERIAL_RCV_BUFSZ2, rcv_buffer2,
-	  SERIAL_SND_BUFSZ2, snd_buffer2 },
+	{SERIAL_RCV_SEM2, SERIAL_SND_SEM2,
+	 SERIAL_RCV_BUFSZ2, rcv_buffer2,
+	 SERIAL_SND_BUFSZ2, snd_buffer2},
 #endif /* TNUM_PORT >= 2 */
 #if TNUM_PORT >= 3
-	{ SERIAL_RCV_SEM3, SERIAL_SND_SEM3,
-	  SERIAL_RCV_BUFSZ3, rcv_buffer3,
-	  SERIAL_SND_BUFSZ3, snd_buffer3 },
+	{SERIAL_RCV_SEM3, SERIAL_SND_SEM3,
+	 SERIAL_RCV_BUFSZ3, rcv_buffer3,
+	 SERIAL_SND_BUFSZ3, snd_buffer3},
 #endif /* TNUM_PORT >= 3 */
 #if TNUM_PORT >= 4
-	{ SERIAL_RCV_SEM4, SERIAL_SND_SEM4,
-	  SERIAL_RCV_BUFSZ4, rcv_buffer4,
-	  SERIAL_SND_BUFSZ4, snd_buffer4 },
+	{SERIAL_RCV_SEM4, SERIAL_SND_SEM4,
+	 SERIAL_RCV_BUFSZ4, rcv_buffer4,
+	 SERIAL_SND_BUFSZ4, snd_buffer4},
 #endif /* TNUM_PORT >= 4 */
 };
@@ -161,38 +161,38 @@
  */
 typedef struct serial_port_control_block {
-	const SPINIB *p_spinib;		/* シリアルポート初期化ブロック */
-	SIOPCB	*p_siopcb;			/* シリアルI/Oポート管理ブロック */
-	bool_t	openflag;			/* オープン済みフラグ */
-	bool_t	errorflag;			/* エラーフラグ */
-	uint_t	ioctl;				/* 動作制御の設定値 */
-
-	uint_t	rcv_read_ptr;		/* 受信バッファ読出しポインタ */
-	uint_t	rcv_write_ptr;		/* 受信バッファ書込みポインタ */
-	uint_t	rcv_count;			/* 受信バッファ中の文字数 */
-	char	rcv_fc_chr;			/* 送るべきSTART/STOP */
-	bool_t	rcv_stopped;		/* STOPを送った状態か？ */
-
-	uint_t	snd_read_ptr;		/* 送信バッファ読出しポインタ */
-	uint_t	snd_write_ptr;		/* 送信バッファ書込みポインタ */
-	uint_t	snd_count;			/* 送信バッファ中の文字数 */
-	bool_t	snd_stopped;		/* STOPを受け取った状態か？ */
+	const SPINIB *p_spinib; /* シリアルポート初期化ブロック */
+	SIOPCB *p_siopcb;		/* シリアルI/Oポート管理ブロック */
+	bool_t openflag;		/* オープン済みフラグ */
+	bool_t errorflag;		/* エラーフラグ */
+	uint_t ioctl;			/* 動作制御の設定値 */
+
+	uint_t rcv_read_ptr;  /* 受信バッファ読出しポインタ */
+	uint_t rcv_write_ptr; /* 受信バッファ書込みポインタ */
+	uint_t rcv_count;	  /* 受信バッファ中の文字数 */
+	char rcv_fc_chr;	  /* 送るべきSTART/STOP */
+	bool_t rcv_stopped;	  /* STOPを送った状態か？ */
+
+	uint_t snd_read_ptr;  /* 送信バッファ読出しポインタ */
+	uint_t snd_write_ptr; /* 送信バッファ書込みポインタ */
+	uint_t snd_count;	  /* 送信バッファ中の文字数 */
+	bool_t snd_stopped;	  /* STOPを受け取った状態か？ */
 } SPCB;
 
-static SPCB	spcb_table[TNUM_PORT];
+static SPCB spcb_table[TNUM_PORT];
 
 /*
  *  シリアルポートIDからシリアルポート管理ブロックを取り出すためのマクロ
  */
-#define INDEX_PORT(portid)	((uint_t)((portid) - 1))
-#define get_spcb(portid)	(&(spcb_table[INDEX_PORT(portid)]))
+#define INDEX_PORT(portid) ((uint_t)((portid)-1))
+#define get_spcb(portid) (&(spcb_table[INDEX_PORT(portid)]))
 
 /*
  *  ポインタのインクリメント
  */
-#define INC_PTR(ptr, bufsz) do {	\
-	if (++(ptr) == (bufsz)) {		\
-		(ptr) = 0;					\
-	 }								\
-} while (false)
+#define INC_PTR(ptr, bufsz) do {   \
+		if (++(ptr) == (bufsz)) {  \
+			(ptr) = 0;             \
+		}                          \
+	} while (false)
 
 /*
@@ -202,10 +202,10 @@
  *  合には，ercにercd_expを評価した値を代入し，error_exitにgotoする．
  */
-#define SVC(exp, ercd_exp) do {		\
-	if ((exp) < 0) {				\
-		ercd = (ercd_exp);			\
-		goto error_exit;			\
-	}								\
-} while (false)
+#define SVC(exp, ercd_exp) do {    \
+		if ((exp) < 0) {           \
+			ercd = (ercd_exp);     \
+			goto error_exit;       \
+		}                          \
+	} while (false)
 
 /*
@@ -216,5 +216,5 @@
 {
 	p_spcb->errorflag = true;
-	return(E_SYS);
+	return (E_SYS);
 }
 
@@ -228,8 +228,8 @@
 	case E_RLWAI:
 	case E_DLT:
-		return(rercd);
+		return (rercd);
 	default:
 		p_spcb->errorflag = true;
-		return(E_SYS);
+		return (E_SYS);
 	}
 }
@@ -241,6 +241,6 @@
 serial_initialize(intptr_t exinf)
 {
-	uint_t	i;
-	SPCB	*p_spcb;
+	uint_t i;
+	SPCB *p_spcb;
 
 	for (i = 0; i < TNUM_PORT; i++) {
@@ -257,17 +257,17 @@
 serial_opn_por(ID portid)
 {
-	SPCB	*p_spcb;
-	ER		ercd;
-
-	if (sns_dpn()) {				/* コンテキストのチェック */
-		return(E_CTX);
+	SPCB *p_spcb;
+	ER ercd;
+
+	if (sns_dpn()) { /* コンテキストのチェック */
+		return (E_CTX);
 	}
 	if (!(1 <= portid && portid <= TNUM_PORT)) {
-		return(E_ID);				/* ポート番号のチェック */
+		return (E_ID); /* ポート番号のチェック */
 	}
 	p_spcb = get_spcb(portid);
 
 	SVC(dis_dsp(), gen_ercd_sys(p_spcb));
-	if (p_spcb->openflag) {			/* オープン済みかのチェック */
+	if (p_spcb->openflag) { /* オープン済みかのチェック */
 		ercd = E_OBJ;
 	}
@@ -292,5 +292,5 @@
 		 *  これ以降，割込みを禁止する．
 		 */
-		if (loc_cpu() < 0) {
+		if (loc_cpu() < 0) 	{
 			ercd = E_SYS;
 			goto error_exit_enadsp;
@@ -300,5 +300,5 @@
 		 *  ハードウェア依存のオープン処理
 		 */
-		p_spcb->p_siopcb = sio_opn_por(portid, (intptr_t) p_spcb);
+		p_spcb->p_siopcb = sio_opn_por(portid, (intptr_t)p_spcb);
 
 		/*
@@ -317,9 +317,9 @@
 	}
 
-  error_exit_enadsp:
+error_exit_enadsp:
 	SVC(ena_dsp(), gen_ercd_sys(p_spcb));
 
-  error_exit:
-	return(ercd);
+error_exit:
+	return (ercd);
 }
 
@@ -330,18 +330,18 @@
 serial_cls_por(ID portid)
 {
-	SPCB	*p_spcb;
-	ER		ercd;
-	bool_t	eflag = false;
-
-	if (sns_dpn()) {				/* コンテキストのチェック */
-		return(E_CTX);
+	SPCB *p_spcb;
+	ER ercd;
+	bool_t eflag = false;
+
+	if (sns_dpn()) { /* コンテキストのチェック */
+		return (E_CTX);
 	}
 	if (!(1 <= portid && portid <= TNUM_PORT)) {
-		return(E_ID);				/* ポート番号のチェック */
+		return (E_ID); /* ポート番号のチェック */
 	}
 	p_spcb = get_spcb(portid);
 
 	SVC(dis_dsp(), gen_ercd_sys(p_spcb));
-	if (!(p_spcb->openflag)) {		/* オープン済みかのチェック */
+	if (!(p_spcb->openflag)) { /* オープン済みかのチェック */
 		ercd = E_OBJ;
 	}
@@ -381,6 +381,6 @@
 	SVC(ena_dsp(), gen_ercd_sys(p_spcb));
 
-  error_exit:
-	return(ercd);
+error_exit:
+	return (ercd);
 }
 
@@ -397,9 +397,9 @@
 {
 	if (sio_snd_chr(p_spcb->p_siopcb, c)) {
-		return(true);
+		return (true);
 	}
 	else {
 		sio_ena_cbr(p_spcb->p_siopcb, SIO_RDY_SND);
-		return(false);
+		return (false);
 	}
 }
@@ -411,6 +411,6 @@
 serial_wri_chr(SPCB *p_spcb, char c)
 {
-	bool_t	buffer_full;
-	ER		ercd, rercd;
+	bool_t buffer_full;
+	ER ercd, rercd;
 
 	/*
@@ -424,7 +424,7 @@
 		 */
 		SVC(rercd = serial_wri_chr(p_spcb, '\r'), rercd);
-		if ((bool_t) rercd) {
+		if ((bool_t)rercd) {
 			SVC(rercd = wai_sem(p_spcb->p_spinib->snd_semid),
-										gen_ercd_wait(rercd, p_spcb));
+				gen_ercd_wait(rercd, p_spcb));
 		}
 	}
@@ -432,5 +432,5 @@
 	SVC(loc_cpu(), gen_ercd_sys(p_spcb));
 	if (p_spcb->snd_count == 0U && !(p_spcb->snd_stopped)
-								&& serial_snd_chr(p_spcb, c)) {
+		&& serial_snd_chr(p_spcb, c)) {
 		/*
 		 *  シリアルI/Oデバイスの送信レジスタに文字を入れることに成功し
@@ -450,8 +450,8 @@
 
 	SVC(unl_cpu(), gen_ercd_sys(p_spcb));
-	ercd = (ER_BOOL) buffer_full;
-
-  error_exit:
-	return(ercd);
+	ercd = (ER_BOOL)buffer_full;
+
+error_exit:
+	return (ercd);
 }
 
@@ -462,33 +462,33 @@
 serial_wri_dat(ID portid, const char *buf, uint_t len)
 {
-	SPCB	*p_spcb;
-	bool_t	buffer_full;
-	uint_t	wricnt = 0U;
-	ER		ercd, rercd;
-
-	if (sns_dpn()) {				/* コンテキストのチェック */
-		return(E_CTX);
+	SPCB *p_spcb;
+	bool_t buffer_full;
+	uint_t wricnt = 0U;
+	ER ercd, rercd;
+
+	if (sns_dpn()) { /* コンテキストのチェック */
+		return (E_CTX);
 	}
 	if (!(1 <= portid && portid <= TNUM_PORT)) {
-		return(E_ID);				/* ポート番号のチェック */
+		return (E_ID); /* ポート番号のチェック */
 	}
 
 	p_spcb = get_spcb(portid);
-	if (!(p_spcb->openflag)) {		/* オープン済みかのチェック */
-		return(E_OBJ);
-	}
-	if (p_spcb->errorflag) {		/* エラー状態かのチェック */
-		return(E_SYS);
-	}
-
-	buffer_full = true;				/* ループの1回めはwai_semする */
+	if (!(p_spcb->openflag)) { /* オープン済みかのチェック */
+		return (E_OBJ);
+	}
+	if (p_spcb->errorflag) { /* エラー状態かのチェック */
+		return (E_SYS);
+	}
+
+	buffer_full = true; /* ループの1回めはwai_semする */
 	while (wricnt < len) {
 		if (buffer_full) {
 			SVC(rercd = wai_sem(p_spcb->p_spinib->snd_semid),
-										gen_ercd_wait(rercd, p_spcb));
+				gen_ercd_wait(rercd, p_spcb));
 		}
 		SVC(rercd = serial_wri_chr(p_spcb, *buf++), rercd);
 		wricnt++;
-		buffer_full = (bool_t) rercd;
+		buffer_full = (bool_t)rercd;
 	}
 	if (!buffer_full) {
@@ -497,6 +497,6 @@
 	ercd = E_OK;
 
-  error_exit:
-	return(wricnt > 0U ? (ER_UINT) wricnt : ercd);
+error_exit:
+	return (wricnt > 0U ? (ER_UINT)wricnt : ercd);
 }
 
@@ -507,6 +507,6 @@
 serial_rea_chr(SPCB *p_spcb, char *p_c)
 {
-	bool_t	buffer_empty;
-	ER		ercd;
+	bool_t buffer_empty;
+	ER ercd;
 
 	SVC(loc_cpu(), gen_ercd_sys(p_spcb));
@@ -523,6 +523,6 @@
 	 *  STARTを送信する．
 	 */
-	if (p_spcb->rcv_stopped && p_spcb->rcv_count
-								<= BUFCNT_START(p_spcb->p_spinib->rcv_bufsz)) {
+	if (p_spcb->rcv_stopped
+		&& p_spcb->rcv_count <= BUFCNT_START(p_spcb->p_spinib->rcv_bufsz)) {
 		if (!serial_snd_chr(p_spcb, FC_START)) {
 			p_spcb->rcv_fc_chr = FC_START;
@@ -532,8 +532,8 @@
 
 	SVC(unl_cpu(), gen_ercd_sys(p_spcb));
-	ercd = (ER_BOOL) buffer_empty;
-
-  error_exit:
-	return(ercd);
+	ercd = (ER_BOOL)buffer_empty;
+
+error_exit:
+	return (ercd);
 }
 
@@ -544,35 +544,35 @@
 serial_rea_dat(ID portid, char *buf, uint_t len)
 {
-	SPCB	*p_spcb;
-	bool_t	buffer_empty;
-	uint_t	reacnt = 0U;
-	char	c = '\0';		/* コンパイラの警告を抑止するために初期化する */
-	ER		ercd, rercd;
-
-	if (sns_dpn()) {				/* コンテキストのチェック */
-		return(E_CTX);
+	SPCB *p_spcb;
+	bool_t buffer_empty;
+	uint_t reacnt = 0U;
+	char c = '\0'; /* コンパイラの警告を抑止するために初期化する */
+	ER ercd, rercd;
+
+	if (sns_dpn()) { /* コンテキストのチェック */
+		return (E_CTX);
 	}
 	if (!(1 <= portid && portid <= TNUM_PORT)) {
-		return(E_ID);				/* ポート番号のチェック */
+		return (E_ID); /* ポート番号のチェック */
 	}
 
 	p_spcb = get_spcb(portid);
-	if (!(p_spcb->openflag)) {		/* オープン済みかのチェック */
-		return(E_OBJ);
-	}
-	if (p_spcb->errorflag) {		/* エラー状態かのチェック */
-		return(E_SYS);
-	}
-
-	buffer_empty = true;			/* ループの1回めはwai_semする */
+	if (!(p_spcb->openflag)) { /* オープン済みかのチェック */
+		return (E_OBJ);
+	}
+	if (p_spcb->errorflag) { /* エラー状態かのチェック */
+		return (E_SYS);
+	}
+
+	buffer_empty = true; /* ループの1回めはwai_semする */
 	while (reacnt < len) {
 		if (buffer_empty) {
 			SVC(rercd = wai_sem(p_spcb->p_spinib->rcv_semid),
-										gen_ercd_wait(rercd, p_spcb));
+				gen_ercd_wait(rercd, p_spcb));
 		}
 		SVC(rercd = serial_rea_chr(p_spcb, &c), rercd);
 		*buf++ = c;
 		reacnt++;
-		buffer_empty = (bool_t) rercd;
+		buffer_empty = (bool_t)rercd;
 
 		/*
@@ -581,9 +581,9 @@
 		if ((p_spcb->ioctl & IOCTL_ECHO) != 0U) {
 			SVC(rercd = wai_sem(p_spcb->p_spinib->snd_semid),
-										gen_ercd_wait(rercd, p_spcb));
+				gen_ercd_wait(rercd, p_spcb));
 			SVC(rercd = serial_wri_chr(p_spcb, c), rercd);
-			if (!((bool_t) rercd)) {
+			if (!((bool_t)rercd)) {
 				SVC(sig_sem(p_spcb->p_spinib->snd_semid),
-										gen_ercd_sys(p_spcb));
+					gen_ercd_sys(p_spcb));
 			}
 		}
@@ -594,6 +594,6 @@
 	ercd = E_OK;
 
-  error_exit:
-	return(reacnt > 0U ? (ER_UINT) reacnt : ercd);
+error_exit:
+	return (reacnt > 0U ? (ER_UINT)reacnt : ercd);
 }
 
@@ -604,23 +604,23 @@
 serial_ctl_por(ID portid, uint_t ioctl)
 {
-	SPCB	*p_spcb;
-
-	if (sns_dpn()) {				/* コンテキストのチェック */
-		return(E_CTX);
+	SPCB *p_spcb;
+
+	if (sns_dpn()) { /* コンテキストのチェック */
+		return (E_CTX);
 	}
 	if (!(1 <= portid && portid <= TNUM_PORT)) {
-		return(E_ID);				/* ポート番号のチェック */
+		return (E_ID); /* ポート番号のチェック */
 	}
 
 	p_spcb = get_spcb(portid);
-	if (!(p_spcb->openflag)) {		/* オープン済みかのチェック */
-		return(E_OBJ);
-	}
-	if (p_spcb->errorflag) {		/* エラー状態かのチェック */
-		return(E_SYS);
+	if (!(p_spcb->openflag)) { /* オープン済みかのチェック */
+		return (E_OBJ);
+	}
+	if (p_spcb->errorflag) { /* エラー状態かのチェック */
+		return (E_SYS);
 	}
 
 	p_spcb->ioctl = ioctl;
-	return(E_OK);
+	return (E_OK);
 }
 
@@ -631,24 +631,24 @@
 serial_ref_por(ID portid, T_SERIAL_RPOR *pk_rpor)
 {
-	SPCB	*p_spcb;
-
-	if (sns_dpn()) {				/* コンテキストのチェック */
-		return(E_CTX);
+	SPCB *p_spcb;
+
+	if (sns_dpn()) { /* コンテキストのチェック */
+		return (E_CTX);
 	}
 	if (!(1 <= portid && portid <= TNUM_PORT)) {
-		return(E_ID);				/* ポート番号のチェック */
+		return (E_ID); /* ポート番号のチェック */
 	}
 
 	p_spcb = get_spcb(portid);
-	if (!(p_spcb->openflag)) {		/* オープン済みかのチェック */
-		return(E_OBJ);
-	}
-	if (p_spcb->errorflag) {		/* エラー状態かのチェック */
-		return(E_SYS);
+	if (!(p_spcb->openflag)) { /* オープン済みかのチェック */
+		return (E_OBJ);
+	}
+	if (p_spcb->errorflag) { /* エラー状態かのチェック */
+		return (E_SYS);
 	}
 
 	pk_rpor->reacnt = p_spcb->rcv_count;
 	pk_rpor->wricnt = p_spcb->snd_count;
-	return(E_OK);
+	return (E_OK);
 }
 
@@ -659,33 +659,38 @@
 sio_irdy_snd(intptr_t exinf)
 {
-	SPCB	*p_spcb;
-
-	p_spcb = (SPCB *) exinf;
-	if (p_spcb->rcv_fc_chr != '\0') {
-		/*
-		 *  START/STOP を送信する．
-		 */
-		(void) sio_snd_chr(p_spcb->p_siopcb, p_spcb->rcv_fc_chr);
-		p_spcb->rcv_fc_chr = '\0';
-	}
-	else if (!(p_spcb->snd_stopped) && p_spcb->snd_count > 0U) {
-		/*
-		 *  送信バッファ中から文字を取り出して送信する．
-		 */
-		(void) sio_snd_chr(p_spcb->p_siopcb,
-					p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr]);
-		INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz);
-		if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) {
-			if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) {
-				p_spcb->errorflag = true;
+	SPCB *p_spcb;
+
+	p_spcb = (SPCB *)exinf;
+	for (;;) {
+		if (p_spcb->rcv_fc_chr != '\0') {
+			/*
+			*  START/STOP を送信する．
+			*/
+			if (!sio_snd_chr(p_spcb->p_siopcb, p_spcb->rcv_fc_chr))
+				break;
+			p_spcb->rcv_fc_chr = '\0';
+		}
+		else if (!(p_spcb->snd_stopped) && p_spcb->snd_count > 0U) {
+			/*
+			*  送信バッファ中から文字を取り出して送信する．
+			*/
+			if (!sio_snd_chr(p_spcb->p_siopcb,
+							 p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr]))
+				break;
+			INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz);
+			if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) {
+				if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) {
+					p_spcb->errorflag = true;
+				}
 			}
-		}
-		p_spcb->snd_count--;
-	}
-	else {
-		/*
-		 *  送信すべき文字がない場合は，送信可能コールバックを禁止する．
-		 */
-		sio_dis_cbr(p_spcb->p_siopcb, SIO_RDY_SND);
+			p_spcb->snd_count--;
+		}
+		else {
+			/*
+			*  送信すべき文字がない場合は，送信可能コールバックを禁止する．
+			*/
+			sio_dis_cbr(p_spcb->p_siopcb, SIO_RDY_SND);
+			break;
+		}
 	}
 }
@@ -697,67 +702,70 @@
 sio_irdy_rcv(intptr_t exinf)
 {
-	SPCB	*p_spcb;
-	char	c;
-
-	p_spcb = (SPCB *) exinf;
-	c = (char) sio_rcv_chr(p_spcb->p_siopcb);
-	if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_STOP) {
-		/*
-		 *  送信を一時停止する．送信中の文字はそのまま送信する．
-		 */
-		p_spcb->snd_stopped = true;
-	}
-	else if (p_spcb->snd_stopped && (c == FC_START
-				|| (p_spcb->ioctl & IOCTL_FCANY) != 0U)) {
-		/*
-		 *  送信を再開する．
-		 */
-		p_spcb->snd_stopped = false;
-		if (p_spcb->snd_count > 0U) {
-			c = p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr];
-			if (serial_snd_chr(p_spcb, c)) {
-				INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz);
-				if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) {
-					if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) {
-						p_spcb->errorflag = true;
+	SPCB *p_spcb;
+	int_t c;
+
+	p_spcb = (SPCB *)exinf;
+	for (;;) {
+		c = sio_rcv_chr(p_spcb->p_siopcb);
+		if (c < 0)
+			break;
+		if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_STOP) {
+			/*
+			*  送信を一時停止する．送信中の文字はそのまま送信する．
+			*/
+			p_spcb->snd_stopped = true;
+		}
+		else if (p_spcb->snd_stopped && (c == FC_START
+			|| (p_spcb->ioctl & IOCTL_FCANY) != 0U)) {
+			/*
+			*  送信を再開する．
+			*/
+			p_spcb->snd_stopped = false;
+			if (p_spcb->snd_count > 0U) {
+				c = p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr];
+				if (serial_snd_chr(p_spcb, c)) {
+					INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz);
+					if (p_spcb->snd_count == p_spcb->p_spinib->snd_bufsz) {
+						if (isig_sem(p_spcb->p_spinib->snd_semid) < 0) {
+							p_spcb->errorflag = true;
+						}
 					}
+					p_spcb->snd_count--;
 				}
-				p_spcb->snd_count--;
 			}
 		}
-	}
-	else if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_START) {
-		/*
-		 *  送信に対してフロー制御している場合，START は捨てる．
-		 */
-	}
-	else if (p_spcb->rcv_count == p_spcb->p_spinib->rcv_bufsz) {
-		/*
-		 *  バッファフルの場合，受信した文字を捨てる．
-		 */
-	}
-	else {
-		/*
-		 *  受信した文字を受信バッファに入れる．
-		 */
-		p_spcb->p_spinib->rcv_buffer[p_spcb->rcv_write_ptr] = c;
-		INC_PTR(p_spcb->rcv_write_ptr, p_spcb->p_spinib->rcv_bufsz);
-		if (p_spcb->rcv_count == 0U) {
-			if (isig_sem(p_spcb->p_spinib->rcv_semid) < 0) {
-				p_spcb->errorflag = true;
+		else if ((p_spcb->ioctl & IOCTL_FCSND) != 0U && c == FC_START) {
+			/*
+			*  送信に対してフロー制御している場合，START は捨てる．
+			*/
+		}
+		else if (p_spcb->rcv_count == p_spcb->p_spinib->rcv_bufsz) {
+			/*
+			*  バッファフルの場合，受信した文字を捨てる．
+			*/
+		}
+		else {
+			/*
+			*  受信した文字を受信バッファに入れる．
+			*/
+			p_spcb->p_spinib->rcv_buffer[p_spcb->rcv_write_ptr] = c;
+			INC_PTR(p_spcb->rcv_write_ptr, p_spcb->p_spinib->rcv_bufsz);
+			if (p_spcb->rcv_count == 0U) {
+				if (isig_sem(p_spcb->p_spinib->rcv_semid) < 0) {
+					p_spcb->errorflag = true;
+				}
 			}
-		}
-		p_spcb->rcv_count++;
-
-		/*
-		 *  STOPを送信する．
-		 */
-		if ((p_spcb->ioctl & IOCTL_FCRCV) != 0U && !(p_spcb->rcv_stopped)
-						&& p_spcb->rcv_count
-							>= BUFCNT_STOP(p_spcb->p_spinib->rcv_bufsz)) {
-			if (!serial_snd_chr(p_spcb, FC_STOP)) {
-				p_spcb->rcv_fc_chr = FC_STOP;
+			p_spcb->rcv_count++;
+
+			/*
+			*  STOPを送信する．
+			*/
+			if ((p_spcb->ioctl & IOCTL_FCRCV) != 0U && !(p_spcb->rcv_stopped)
+				&& p_spcb->rcv_count >= BUFCNT_STOP(p_spcb->p_spinib->rcv_bufsz)) {
+				if (!serial_snd_chr(p_spcb, FC_STOP)) {
+					p_spcb->rcv_fc_chr = FC_STOP;
+				}
+				p_spcb->rcv_stopped = true;
 			}
-			p_spcb->rcv_stopped = true;
 		}
 	}
@@ -770,17 +778,17 @@
 serial_get_chr(ID portid, char *p_c)
 {
-	SPCB	*p_spcb;
-
-	if (1 <= portid && portid <= TNUM_PORT) {	/* ポート番号のチェック */
+	SPCB *p_spcb;
+
+	if (1 <= portid && portid <= TNUM_PORT) { /* ポート番号のチェック */
 		p_spcb = get_spcb(portid);
-		if (p_spcb->openflag) {					/* オープン済みかのチェック */
+		if (p_spcb->openflag) { /* オープン済みかのチェック */
 			if (p_spcb->snd_count > 0U) {
 				*p_c = p_spcb->p_spinib->snd_buffer[p_spcb->snd_read_ptr];
 				INC_PTR(p_spcb->snd_read_ptr, p_spcb->p_spinib->snd_bufsz);
 				p_spcb->snd_count--;
-				return(true);
+				return (true);
 			}
 		}
 	}
-	return(false);
-}
+	return (false);
+}
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/Makefile.target
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/Makefile.target	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/Makefile.target	(revision 458)
@@ -56,5 +56,5 @@
 #  リンカスクリプトの定義
 #
-LDSCRIPT = $(SRCDIR)/arch/$(PRC)_$(TOOL)/riscv64elf.ld
+LDSCRIPT = $(TARGETDIR)/kendryte-k210.ld
 
 #
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/kendryte-k210.ld
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/kendryte-k210.ld	(revision 458)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/kendryte-k210.ld	(revision 458)
@@ -0,0 +1,110 @@
+/*
+ *  @(#) $Id$
+ */
+
+MEMORY
+{
+  /*
+   * Memory with CPU cache.
+   *6M CPU SRAM
+   */
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = (6 * 1024 * 1024)
+  /*
+   * Memory without CPU cache
+   * 6M CPU SRAM
+  */
+  ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024)
+}
+
+OUTPUT_ARCH(riscv)
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+PROVIDE(__idata_start = 0);
+PROVIDE(__idata_end = 0);
+STARTUP(start.o)
+
+SECTIONS
+{
+    __stack_size = DEFINED(__stack_size) ? __stack_size : 8K;
+
+    .init :
+    {
+        KEEP (*(.init))
+    }>ram
+    .text :
+    {
+        __text = . ;
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+
+    }>ram
+    .fini :
+    {
+        KEEP (*(.fini))
+    }>ram
+    _etext = . ;
+    PROVIDE (etext = .) ;
+    .rodata :
+    {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+    }>ram
+    . = ALIGN(8);
+    .data : 
+    {
+        __data_start = . ;
+        /* Writable data segment (.data segment) */
+        *(.data .data.*)
+        *(.sdata .sdata.* .sdata2 .sdata2.*)
+        . = ALIGN(8);
+        PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800);
+    }>ram
+    .eh_frame : { KEEP (*(.eh_frame)) }>ram
+    .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) }>ram
+    .ctors :
+    {
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+    }>ram
+    .dtors :
+    {
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+    }>ram
+    _edata  = . ;
+    PROVIDE (edata = .) ;
+    . = ALIGN(8) ;
+    __bss_start = . ;
+    _bss = .;
+    .bss :
+    {
+        *(.bss .bss.*)
+        *(.sbss .sbss.* .sbss2 .sbss2.*)
+        *(COMMON)
+    }>ram
+    _end = . ;
+    __bss_end = . ;
+    _ebss = . ;
+    .stack (NOLOAD) :
+    {
+    	*(.stack)
+    }>ram
+    .heap (NOLOAD) :
+    {
+        PROVIDE (_heap_start = .) ;
+        *(.heap)
+    }>ram
+    PROVIDE (_heap_end = .) ;
+    PROVIDE (end = .) ;
+    .comment        0 : { *(.comment) }
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+}
Index: azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c	(revision 454)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c	(revision 458)
@@ -55,17 +55,17 @@
  *  SIL関数のマクロ定義
  */
-#define sil_orw_mem(a, b)		sil_wrw_mem((a), sil_rew_mem(a) | (b))
-#define sil_andw_mem(a, b)		sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
+#define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b))
+#define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
 
 /*
  * レジスタ設定値
  */
-#define INDEX_PORT(x)	((x) - 1)
-#define GET_SIOPCB(x)	(&siopcb_table[INDEX_PORT(x)])
-
-#define __UART_BRATE_CONST  16
+#define INDEX_PORT(x) ((x)-1)
+#define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)])
+
+#define __UART_BRATE_CONST 16
 
 #ifndef COM0
-#define COM0                0
+#define COM0 0
 #endif
 
@@ -73,36 +73,36 @@
  *  ビット長パラメータ
  */
-#define UART_WordLength_5B  0x00000000
-#define UART_WordLength_6B  0x00000001
-#define UART_WordLength_7B  0x00000002
-#define UART_WordLength_8b  0x00000003
+#define UART_WordLength_5B 0x00000000
+#define UART_WordLength_6B 0x00000001
+#define UART_WordLength_7B 0x00000002
+#define UART_WordLength_8b 0x00000003
 
 /*
  *  ストップビットパラメータ
- */ 
-#define UART_StopBits_1     0x00000000
-#define UART_StopBits_1_5   UART_LCR_STB
+ */
+#define UART_StopBits_1 0x00000000
+#define UART_StopBits_1_5 UART_LCR_STB
 
 /*
  *  パリティパラメータ
  */
-#define UART_Parity_No      0x00000000
-#define UART_Parity_Odd     UART_LCR_PARITY
-#define UART_Parity_Even    (UART_LCR_PARITY | UART_LCR_PEVEN)
+#define UART_Parity_No 0x00000000
+#define UART_Parity_Odd UART_LCR_PARITY
+#define UART_Parity_Even (UART_LCR_PARITY | UART_LCR_PEVEN)
 
 /*
  *  送信FIFO
  */
-#define UART_SEND_FIFO0     0
-#define UART_SEND_FIFO2     1
-#define UART_SEND_FIFO4     2
-#define UART_SEND_FIFO8     3
+#define UART_SEND_FIFO0 0
+#define UART_SEND_FIFO2 1
+#define UART_SEND_FIFO4 2
+#define UART_SEND_FIFO8 3
 
 /*
  *  受信FIFO
  */
-#define UART_RECEIVE_FIFO1  0
-#define UART_RECEIVE_FIFO4  1
-#define UART_RECEIVE_FIFO8  2
+#define UART_RECEIVE_FIFO1 0
+#define UART_RECEIVE_FIFO4 1
+#define UART_RECEIVE_FIFO8 2
 #define UART_RECEIVE_FIFO14 3
 
@@ -112,9 +112,9 @@
 typedef struct sio_port_initialization_block {
 	uint64_t base;
-	INTNO    intno_usart;
+	INTNO intno_usart;
 	uint32_t clk;
-	uint8_t  txfunc;
-	uint8_t  rxfunc;
-	uint8_t  com;
+	uint8_t txfunc;
+	uint8_t rxfunc;
+	uint8_t com;
 } SIOPINIB;
 
@@ -123,7 +123,7 @@
  */
 struct sio_port_control_block {
-	const SIOPINIB  *p_siopinib;  /* シリアルI/Oポート初期化ブロック */
-	intptr_t        exinf;        /* 拡張情報 */
-	bool_t          opnflg;       /* オープン済みフラグ */
+	const SIOPINIB *p_siopinib; /* シリアルI/Oポート初期化ブロック */
+	intptr_t exinf;				/* 拡張情報 */
+	bool_t opnflg;				/* オープン済みフラグ */
 };
 
@@ -134,5 +134,5 @@
 	{(uint32_t)TADR_UART1_BASE, (INTNO)IRQ_VECTOR_UART1, SYSCTL_CLK_EN_PERI_UART1_CLK_EN, FUNC_UART1_TX, FUNC_UART1_RX, COM0},
 #if TNUM_SIOP >= 2
-	{(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0^1}
+	{(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0 ^ 1}
 #endif
 };
@@ -142,6 +142,6 @@
  */
 static uint8_t uartpin[2][2] = {
-	{5, 4},		/* com0 tx, rx */
-	{6, 7},		/* com1 tx, rx */
+	{5, 4}, /* com0 tx, rx */
+	{6, 7}, /* com1 tx, rx */
 };
 
@@ -149,11 +149,11 @@
  *  シリアルI/Oポート管理ブロックのエリア
  */
-SIOPCB	siopcb_table[TNUM_SIOP];
+SIOPCB siopcb_table[TNUM_SIOP];
 
 /*
  *  シリアルI/OポートIDから管理ブロックを取り出すためのマクロ
  */
-#define INDEX_SIOP(siopid)	((uint_t)((siopid) - 1))
-#define get_siopcb(siopid)	(&(siopcb_table[INDEX_SIOP(siopid)]))
+#define INDEX_SIOP(siopid) ((uint_t)((siopid)-1))
+#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
 
 extern uint32_t get_pll_clock(uint8_t no);
@@ -166,15 +166,14 @@
 get_clock_aclk(void)
 {
-	uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0));
+	uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0));
 	uint32_t select = clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SEL;
 	uint32_t source = 0;
 
-	if(select == 0)
+	if (select == 0)
 		source = SYSCTRL_CLOCK_FREQ_IN0;
-	else if(select == 1)
-		source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER)>>1));
+	else if (select == 1)
+		source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER) >> 1));
 	return source;
 }
-
 
 void put_hex(char a, int val)
@@ -183,8 +182,8 @@
 	target_fput_log(a);
 	target_fput_log(' ');
-	for(i = 28 ; i >= 0 ; i-= 4){
-		j = (val >> i) & 0xf;;
-		if(j > 9)
-			j += ('A'-10);
+	for (i = 28; i >= 0; i -= 4) {
+		j = (val >> i) & 0xf;
+		if (j > 9)
+			j += ('A' - 10);
 		else
 			j += '0';
@@ -200,6 +199,6 @@
 sio_initialize(intptr_t exinf)
 {
-	SIOPCB	*p_siopcb;
-	uint_t	i;
+	SIOPCB *p_siopcb;
+	uint_t i;
 
 	/*
@@ -212,5 +211,4 @@
 }
 
-
 /*
  *  シリアルI/Oポートのオープン
@@ -219,11 +217,11 @@
 sio_opn_por(ID siopid, intptr_t exinf)
 {
-	SIOPCB          *p_siopcb;
-	const SIOPINIB  *p_siopinib;
-	bool_t   opnflg;
-	ER       ercd;
+	SIOPCB *p_siopcb;
+	const SIOPINIB *p_siopinib;
+	bool_t opnflg;
+	ER ercd;
 	unsigned long base;
 	uint32_t divisor, threshold, tmp;
-	uint8_t  dlh, dll, dlf;
+	uint8_t dlh, dll, dlf;
 
 	p_siopcb = get_siopcb(siopid);
@@ -237,5 +235,5 @@
 	p_siopcb->exinf = exinf;
 	base = p_siopinib->base;
-	if(base == 0)				/* no uart port */
+	if (base == 0) /* no uart port */
 		goto sio_opn_exit;
 
@@ -243,31 +241,33 @@
 	 *  ハードウェアの初期化
 	 */
-	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
-
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_IER), 0x00000000);
+	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
+
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_IER), 0x00000000);
 	sil_dly_nse(10000);
 
-	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
-    divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING;
-    dlh = divisor >> 12;
-    dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
-    dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
-
-    /* Set UART registers */
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
-	sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR),
-			(UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1));
+	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
+	divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING;
+	dlh = divisor >> 12;
+	dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
+	dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
+
+	/* Set UART registers */
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR),
+				(UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00);
 
 	fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc);
 	fpioa_set_function(uartpin[p_siopinib->com][0], p_siopinib->txfunc);
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_RIE);
-	tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_RBR));
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_RIE);
+	tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR));
 	p_siopcb->opnflg = true;
 	(void)(tmp);
@@ -283,5 +283,5 @@
 
 sio_opn_exit:;
-	return(p_siopcb);
+	return (p_siopcb);
 }
 
@@ -292,5 +292,5 @@
 sio_cls_por(SIOPCB *p_siopcb)
 {
-	const SIOPINIB  *p_siopinib;
+	const SIOPINIB *p_siopinib;
 
 	p_siopinib = p_siopcb->p_siopinib;
@@ -305,6 +305,6 @@
 	 *  シリアル停止
 	 */
-	sil_wrw_mem((uint32_t *)(p_siopinib->base+TOFF_UART_IER), 0x00000000);
-	sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
+	sil_wrw_mem((uint32_t *)(p_siopinib->base + TOFF_UART_IER), 0x00000000);
+	sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
 	p_siopcb->opnflg = false;
 }
@@ -318,19 +318,25 @@
 	SIOPCB *p_siopcb = get_siopcb(exinf);
 	unsigned long base = p_siopcb->p_siopinib->base;
-	uint32_t ip = sil_rew_mem((uint32_t *)(base+TOFF_UART_IIR)) & 0x0F;
 	uint32_t tmp;
 
-	if(ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT){
-		sio_irdy_rcv(p_siopcb->exinf);
-	}
-	else if(ip == UART_IIR_SEND){
-		sio_irdy_snd(p_siopcb->exinf);
-	}
-	else{
-		tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR));
-		tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_USR));
-		tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_MSR));
-	}
-	(void)(tmp);
+	for (;;) {
+		uint32_t ip = sil_rew_mem((uint32_t *)(base + TOFF_UART_IIR)) & 0x0F;
+
+		if (ip == 1) {
+			break;
+		}
+		else if (ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT) {
+			sio_irdy_rcv(p_siopcb->exinf);
+		}
+		else if (ip == UART_IIR_SEND) {
+			sio_irdy_snd(p_siopcb->exinf);
+		}
+		else {
+			tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR));
+			tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_USR));
+			tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_MSR));
+		}
+		(void)(tmp);
+	}
 }
 
@@ -339,9 +345,9 @@
  */
 Inline bool_t
-sio_putready(SIOPCB* p_siopcb)
-{
-	uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_LSR));
-
-	if((lsr & UART_LSR_TFL) == 0){
+sio_putready(SIOPCB *p_siopcb)
+{
+	uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR));
+
+	if ((lsr & UART_LSR_TFL) == 0) {
 		return 1;
 	}
@@ -352,6 +358,6 @@
 sio_snd_chr(SIOPCB *p_siopcb, char c)
 {
-	if(sio_putready(p_siopcb)){
-		sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_THR), (uint32_t)c);
+	if (sio_putready(p_siopcb)) {
+		sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_THR), (uint32_t)c);
 		return true;
 	}
@@ -367,6 +373,6 @@
 	int_t c = -1;
 
-	if((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_LSR)) & UART_LSR_RFL) != 0){
-		c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_RBR)) & 0xFF;
+	if ((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR)) & UART_LSR_RFL) != 0) {
+		c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR)) & 0xFF;
 	}
 	return c;
@@ -381,8 +387,8 @@
 	switch (cbrtn) {
 	case SIO_RDY_SND:
-		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_TIE);
+		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE);
 		break;
 	case SIO_RDY_RCV:
-		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_RIE);
+		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE);
 		break;
 	}
@@ -397,8 +403,8 @@
 	switch (cbrtn) {
 	case SIO_RDY_SND:
-		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_TIE);
+		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE);
 		break;
 	case SIO_RDY_RCV:
-		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_RIE);
+		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE);
 		break;
 	}
@@ -412,12 +418,14 @@
 	unsigned long base = siopinib_table[INDEX_PORT(siopid)].base;
 
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_THR), (uint32_t)c);
-	while(0 != (sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR)) & UART_LSR_TFL));
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_THR), (uint32_t)c);
+	while (0 != (sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR)) & UART_LSR_TFL))
+		;
 
 	/*
 	 *  出力が完全に終わるまで待つ
 	 */
-	volatile int n = SYS_CLOCK/BPS_SETTING;
-	while(n--);
+	volatile int n = SYS_CLOCK / BPS_SETTING;
+	while (n--)
+		;
 }
 
@@ -427,8 +435,8 @@
 void target_uart_init(ID siopid)
 {
-	const SIOPINIB  *p_siopinib;
+	const SIOPINIB *p_siopinib;
 	unsigned long base;
 	uint32_t divisor, threshold;
-	uint8_t  dlh, dll, dlf;
+	uint8_t dlh, dll, dlf;
 
 	p_siopinib = &siopinib_table[INDEX_PORT(siopid)];
@@ -438,23 +446,25 @@
 	 *  ハードウェアの初期化
 	 */
-	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
-
-	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
-    divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING;
-    dlh = divisor >> 12;
-    dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
-    dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
-
-    /* Set UART registers */
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
-	sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR),
-			(UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1));
+	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
+
+	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
+	divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING;
+	dlh = divisor >> 12;
+	dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
+	dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
+
+	/* Set UART registers */
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR),
+				(UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00);
 
 	fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc);
