Index: azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c
===================================================================
--- azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c	(revision 453)
+++ azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c	(revision 458)
@@ -55,17 +55,17 @@
  *  SIL関数のマクロ定義
  */
-#define sil_orw_mem(a, b)		sil_wrw_mem((a), sil_rew_mem(a) | (b))
-#define sil_andw_mem(a, b)		sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
+#define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b))
+#define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
 
 /*
  * レジスタ設定値
  */
-#define INDEX_PORT(x)	((x) - 1)
-#define GET_SIOPCB(x)	(&siopcb_table[INDEX_PORT(x)])
-
-#define __UART_BRATE_CONST  16
+#define INDEX_PORT(x) ((x)-1)
+#define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)])
+
+#define __UART_BRATE_CONST 16
 
 #ifndef COM0
-#define COM0                0
+#define COM0 0
 #endif
 
@@ -73,36 +73,36 @@
  *  ビット長パラメータ
  */
-#define UART_WordLength_5B  0x00000000
-#define UART_WordLength_6B  0x00000001
-#define UART_WordLength_7B  0x00000002
-#define UART_WordLength_8b  0x00000003
+#define UART_WordLength_5B 0x00000000
+#define UART_WordLength_6B 0x00000001
+#define UART_WordLength_7B 0x00000002
+#define UART_WordLength_8b 0x00000003
 
 /*
  *  ストップビットパラメータ
- */ 
-#define UART_StopBits_1     0x00000000
-#define UART_StopBits_1_5   UART_LCR_STB
+ */
+#define UART_StopBits_1 0x00000000
+#define UART_StopBits_1_5 UART_LCR_STB
 
 /*
  *  パリティパラメータ
  */
-#define UART_Parity_No      0x00000000
-#define UART_Parity_Odd     UART_LCR_PARITY
-#define UART_Parity_Even    (UART_LCR_PARITY | UART_LCR_PEVEN)
+#define UART_Parity_No 0x00000000
+#define UART_Parity_Odd UART_LCR_PARITY
+#define UART_Parity_Even (UART_LCR_PARITY | UART_LCR_PEVEN)
 
 /*
  *  送信FIFO
  */
-#define UART_SEND_FIFO0     0
-#define UART_SEND_FIFO2     1
-#define UART_SEND_FIFO4     2
-#define UART_SEND_FIFO8     3
+#define UART_SEND_FIFO0 0
+#define UART_SEND_FIFO2 1
+#define UART_SEND_FIFO4 2
+#define UART_SEND_FIFO8 3
 
 /*
  *  受信FIFO
  */
-#define UART_RECEIVE_FIFO1  0
-#define UART_RECEIVE_FIFO4  1
-#define UART_RECEIVE_FIFO8  2
+#define UART_RECEIVE_FIFO1 0
+#define UART_RECEIVE_FIFO4 1
+#define UART_RECEIVE_FIFO8 2
 #define UART_RECEIVE_FIFO14 3
 
@@ -112,9 +112,9 @@
 typedef struct sio_port_initialization_block {
 	uint64_t base;
-	INTNO    intno_usart;
+	INTNO intno_usart;
 	uint32_t clk;
-	uint8_t  txfunc;
-	uint8_t  rxfunc;
-	uint8_t  com;
+	uint8_t txfunc;
+	uint8_t rxfunc;
+	uint8_t com;
 } SIOPINIB;
 
@@ -123,7 +123,7 @@
  */
 struct sio_port_control_block {
-	const SIOPINIB  *p_siopinib;  /* シリアルI/Oポート初期化ブロック */
-	intptr_t        exinf;        /* 拡張情報 */
-	bool_t          opnflg;       /* オープン済みフラグ */
+	const SIOPINIB *p_siopinib; /* シリアルI/Oポート初期化ブロック */
+	intptr_t exinf;				/* 拡張情報 */
+	bool_t opnflg;				/* オープン済みフラグ */
 };
 
@@ -134,5 +134,5 @@
 	{(uint32_t)TADR_UART1_BASE, (INTNO)IRQ_VECTOR_UART1, SYSCTL_CLK_EN_PERI_UART1_CLK_EN, FUNC_UART1_TX, FUNC_UART1_RX, COM0},
 #if TNUM_SIOP >= 2
-	{(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0^1}
+	{(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0 ^ 1}
 #endif
 };
@@ -142,6 +142,6 @@
  */
 static uint8_t uartpin[2][2] = {
-	{5, 4},		/* com0 tx, rx */
-	{6, 7},		/* com1 tx, rx */
+	{5, 4}, /* com0 tx, rx */
+	{6, 7}, /* com1 tx, rx */
 };
 
@@ -149,11 +149,11 @@
  *  シリアルI/Oポート管理ブロックのエリア
  */
-SIOPCB	siopcb_table[TNUM_SIOP];
+SIOPCB siopcb_table[TNUM_SIOP];
 
 /*
  *  シリアルI/OポートIDから管理ブロックを取り出すためのマクロ
  */
-#define INDEX_SIOP(siopid)	((uint_t)((siopid) - 1))
-#define get_siopcb(siopid)	(&(siopcb_table[INDEX_SIOP(siopid)]))
+#define INDEX_SIOP(siopid) ((uint_t)((siopid)-1))
+#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
 
 extern uint32_t get_pll_clock(uint8_t no);
@@ -166,15 +166,14 @@
 get_clock_aclk(void)
 {
-	uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0));
+	uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0));
 	uint32_t select = clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SEL;
 	uint32_t source = 0;
 
-	if(select == 0)
+	if (select == 0)
 		source = SYSCTRL_CLOCK_FREQ_IN0;
-	else if(select == 1)
-		source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER)>>1));
+	else if (select == 1)
+		source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER) >> 1));
 	return source;
 }
-
 
 void put_hex(char a, int val)
@@ -183,8 +182,8 @@
 	target_fput_log(a);
 	target_fput_log(' ');
-	for(i = 28 ; i >= 0 ; i-= 4){
-		j = (val >> i) & 0xf;;
-		if(j > 9)
-			j += ('A'-10);
+	for (i = 28; i >= 0; i -= 4) {
+		j = (val >> i) & 0xf;
+		if (j > 9)
+			j += ('A' - 10);
 		else
 			j += '0';
@@ -200,6 +199,6 @@
 sio_initialize(intptr_t exinf)
 {
-	SIOPCB	*p_siopcb;
-	uint_t	i;
+	SIOPCB *p_siopcb;
+	uint_t i;
 
 	/*
@@ -212,5 +211,4 @@
 }
 
-
 /*
  *  シリアルI/Oポートのオープン
@@ -219,11 +217,11 @@
 sio_opn_por(ID siopid, intptr_t exinf)
 {
-	SIOPCB          *p_siopcb;
-	const SIOPINIB  *p_siopinib;
-	bool_t   opnflg;
-	ER       ercd;
+	SIOPCB *p_siopcb;
+	const SIOPINIB *p_siopinib;
+	bool_t opnflg;
+	ER ercd;
 	unsigned long base;
 	uint32_t divisor, threshold, tmp;
-	uint8_t  dlh, dll, dlf;
+	uint8_t dlh, dll, dlf;
 
 	p_siopcb = get_siopcb(siopid);
@@ -237,5 +235,5 @@
 	p_siopcb->exinf = exinf;
 	base = p_siopinib->base;
-	if(base == 0)				/* no uart port */
+	if (base == 0) /* no uart port */
 		goto sio_opn_exit;
 
@@ -243,31 +241,33 @@
 	 *  ハードウェアの初期化
 	 */
-	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
-
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_IER), 0x00000000);
+	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
+
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_IER), 0x00000000);
 	sil_dly_nse(10000);
 
-	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
-    divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING;
-    dlh = divisor >> 12;
-    dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
-    dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
-
-    /* Set UART registers */
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
-	sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR),
-			(UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1));
+	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
+	divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING;
+	dlh = divisor >> 12;
+	dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
+	dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
+
+	/* Set UART registers */
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR),
+				(UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00);
 
 	fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc);
 	fpioa_set_function(uartpin[p_siopinib->com][0], p_siopinib->txfunc);
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_RIE);
-	tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_RBR));
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_RIE);
+	tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR));
 	p_siopcb->opnflg = true;
 	(void)(tmp);
@@ -283,5 +283,5 @@
 
 sio_opn_exit:;
-	return(p_siopcb);
+	return (p_siopcb);
 }
 
@@ -292,5 +292,5 @@
 sio_cls_por(SIOPCB *p_siopcb)
 {
-	const SIOPINIB  *p_siopinib;
+	const SIOPINIB *p_siopinib;
 
 	p_siopinib = p_siopcb->p_siopinib;
@@ -305,6 +305,6 @@
 	 *  シリアル停止
 	 */
-	sil_wrw_mem((uint32_t *)(p_siopinib->base+TOFF_UART_IER), 0x00000000);
-	sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
+	sil_wrw_mem((uint32_t *)(p_siopinib->base + TOFF_UART_IER), 0x00000000);
+	sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
 	p_siopcb->opnflg = false;
 }
@@ -318,19 +318,25 @@
 	SIOPCB *p_siopcb = get_siopcb(exinf);
 	unsigned long base = p_siopcb->p_siopinib->base;
-	uint32_t ip = sil_rew_mem((uint32_t *)(base+TOFF_UART_IIR)) & 0x0F;
 	uint32_t tmp;
 
-	if(ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT){
-		sio_irdy_rcv(p_siopcb->exinf);
-	}
-	else if(ip == UART_IIR_SEND){
-		sio_irdy_snd(p_siopcb->exinf);
-	}
-	else{
-		tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR));
-		tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_USR));
-		tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_MSR));
-	}
-	(void)(tmp);
+	for (;;) {
+		uint32_t ip = sil_rew_mem((uint32_t *)(base + TOFF_UART_IIR)) & 0x0F;
+
+		if (ip == 1) {
+			break;
+		}
+		else if (ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT) {
+			sio_irdy_rcv(p_siopcb->exinf);
+		}
+		else if (ip == UART_IIR_SEND) {
+			sio_irdy_snd(p_siopcb->exinf);
+		}
+		else {
+			tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR));
+			tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_USR));
+			tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_MSR));
+		}
+		(void)(tmp);
+	}
 }
 
@@ -339,9 +345,9 @@
  */
 Inline bool_t
-sio_putready(SIOPCB* p_siopcb)
-{
-	uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_LSR));
-
-	if((lsr & UART_LSR_TFL) == 0){
+sio_putready(SIOPCB *p_siopcb)
+{
+	uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR));
+
+	if ((lsr & UART_LSR_TFL) == 0) {
 		return 1;
 	}
@@ -352,6 +358,6 @@
 sio_snd_chr(SIOPCB *p_siopcb, char c)
 {
-	if(sio_putready(p_siopcb)){
-		sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_THR), (uint32_t)c);
+	if (sio_putready(p_siopcb)) {
+		sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_THR), (uint32_t)c);
 		return true;
 	}
@@ -367,6 +373,6 @@
 	int_t c = -1;
 
-	if((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_LSR)) & UART_LSR_RFL) != 0){
-		c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_RBR)) & 0xFF;
+	if ((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR)) & UART_LSR_RFL) != 0) {
+		c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR)) & 0xFF;
 	}
 	return c;
@@ -381,8 +387,8 @@
 	switch (cbrtn) {
 	case SIO_RDY_SND:
-		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_TIE);
+		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE);
 		break;
 	case SIO_RDY_RCV:
-		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_RIE);
+		sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE);
 		break;
 	}
@@ -397,8 +403,8 @@
 	switch (cbrtn) {
 	case SIO_RDY_SND:
-		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_TIE);
+		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE);
 		break;
 	case SIO_RDY_RCV:
-		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_IER), UART_IER_RIE);
+		sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE);
 		break;
 	}
@@ -412,12 +418,14 @@
 	unsigned long base = siopinib_table[INDEX_PORT(siopid)].base;
 
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_THR), (uint32_t)c);
-	while(0 != (sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR)) & UART_LSR_TFL));
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_THR), (uint32_t)c);
+	while (0 != (sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR)) & UART_LSR_TFL))
+		;
 
 	/*
 	 *  出力が完全に終わるまで待つ
 	 */
-	volatile int n = SYS_CLOCK/BPS_SETTING;
-	while(n--);
+	volatile int n = SYS_CLOCK / BPS_SETTING;
+	while (n--)
+		;
 }
 
@@ -427,8 +435,8 @@
 void target_uart_init(ID siopid)
 {
-	const SIOPINIB  *p_siopinib;
+	const SIOPINIB *p_siopinib;
 	unsigned long base;
 	uint32_t divisor, threshold;
-	uint8_t  dlh, dll, dlf;
+	uint8_t dlh, dll, dlf;
 
 	p_siopinib = &siopinib_table[INDEX_PORT(siopid)];
@@ -438,23 +446,25 @@
 	 *  ハードウェアの初期化
 	 */
-	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
-
-	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
-    divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING;
-    dlh = divisor >> 12;
-    dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
-    dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
-
-    /* Set UART registers */
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
-	sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD);
-	sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE);
-	sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR),
-			(UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1));
+	sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);
+
+	threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3;
+	divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING;
+	dlh = divisor >> 12;
+	dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
+	dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
+
+	/* Set UART registers */
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD);
+	sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR),
+				(UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/));
+	sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3);
+	sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00);
 
 	fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc);
