Changeset 458 for azure_iot_hub_riscv/trunk/asp_baseplatform/target
- Timestamp:
- Sep 14, 2020, 6:36:03 PM (4 years ago)
- Location:
- azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc
- Files:
-
- 1 added
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/Makefile.target
r453 r458 56 56 # リンカスクリプトの定義 57 57 # 58 LDSCRIPT = $( SRCDIR)/arch/$(PRC)_$(TOOL)/riscv64elf.ld58 LDSCRIPT = $(TARGETDIR)/kendryte-k210.ld 59 59 60 60 # -
azure_iot_hub_riscv/trunk/asp_baseplatform/target/k210_gcc/target_serial.c
r453 r458 55 55 * SIL関数のマクロ定義 56 56 */ 57 #define sil_orw_mem(a, b) 58 #define sil_andw_mem(a, b) 57 #define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b)) 58 #define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b)) 59 59 60 60 /* 61 61 * レジスタ設定値 62 62 */ 63 #define INDEX_PORT(x) ((x) -1)64 #define GET_SIOPCB(x) 65 66 #define __UART_BRATE_CONST 63 #define INDEX_PORT(x) ((x)-1) 64 #define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)]) 65 66 #define __UART_BRATE_CONST 16 67 67 68 68 #ifndef COM0 69 #define COM0 69 #define COM0 0 70 70 #endif 71 71 … … 73 73 * ビット長パラメータ 74 74 */ 75 #define UART_WordLength_5B 76 #define UART_WordLength_6B 77 #define UART_WordLength_7B 78 #define UART_WordLength_8b 75 #define UART_WordLength_5B 0x00000000 76 #define UART_WordLength_6B 0x00000001 77 #define UART_WordLength_7B 0x00000002 78 #define UART_WordLength_8b 0x00000003 79 79 80 80 /* 81 81 * ストップビットパラメータ 82 */ 83 #define UART_StopBits_1 84 #define UART_StopBits_1_5 82 */ 83 #define UART_StopBits_1 0x00000000 84 #define UART_StopBits_1_5 UART_LCR_STB 85 85 86 86 /* 87 87 * パリティパラメータ 88 88 */ 89 #define UART_Parity_No 90 #define UART_Parity_Odd 91 #define UART_Parity_Even 89 #define UART_Parity_No 0x00000000 90 #define UART_Parity_Odd UART_LCR_PARITY 91 #define UART_Parity_Even (UART_LCR_PARITY | UART_LCR_PEVEN) 92 92 93 93 /* 94 94 * 送信FIFO 95 95 */ 96 #define UART_SEND_FIFO0 97 #define UART_SEND_FIFO2 98 #define UART_SEND_FIFO4 99 #define UART_SEND_FIFO8 96 #define UART_SEND_FIFO0 0 97 #define UART_SEND_FIFO2 1 98 #define UART_SEND_FIFO4 2 99 #define UART_SEND_FIFO8 3 100 100 101 101 /* 102 102 * 受信FIFO 103 103 */ 104 #define UART_RECEIVE_FIFO1 105 #define UART_RECEIVE_FIFO4 106 #define UART_RECEIVE_FIFO8 104 #define UART_RECEIVE_FIFO1 0 105 #define UART_RECEIVE_FIFO4 1 106 #define UART_RECEIVE_FIFO8 2 107 107 #define UART_RECEIVE_FIFO14 3 108 108 … … 112 112 typedef struct sio_port_initialization_block { 113 113 uint64_t base; 114 INTNO 114 INTNO intno_usart; 115 115 uint32_t clk; 116 uint8_t 117 uint8_t 118 uint8_t 116 uint8_t txfunc; 117 uint8_t rxfunc; 118 uint8_t com; 119 119 } SIOPINIB; 120 120 … … 123 123 */ 124 124 struct sio_port_control_block { 125 const SIOPINIB *p_siopinib;/* シリアルI/Oポート初期化ブロック */126 intptr_t exinf;/* 拡張情報 */127 bool_t opnflg;/* オープン済みフラグ */125 const SIOPINIB *p_siopinib; /* シリアルI/Oポート初期化ブロック */ 126 intptr_t exinf; /* 拡張情報 */ 127 bool_t opnflg; /* オープン済みフラグ */ 128 128 }; 129 129 … … 134 134 {(uint32_t)TADR_UART1_BASE, (INTNO)IRQ_VECTOR_UART1, SYSCTL_CLK_EN_PERI_UART1_CLK_EN, FUNC_UART1_TX, FUNC_UART1_RX, COM0}, 135 135 #if TNUM_SIOP >= 2 136 {(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0 ^1}136 {(uint32_t)TADR_UART3_BASE, (INTNO)IRQ_VECTOR_UART3, SYSCTL_CLK_EN_PERI_UART3_CLK_EN, FUNC_UART3_TX, FUNC_UART3_RX, COM0 ^ 1} 137 137 #endif 138 138 }; … … 142 142 */ 143 143 static uint8_t uartpin[2][2] = { 144 {5, 4}, 145 {6, 7}, 144 {5, 4}, /* com0 tx, rx */ 145 {6, 7}, /* com1 tx, rx */ 146 146 }; 147 147 … … 149 149 * シリアルI/Oポート管理ブロックのエリア 150 150 */ 151 SIOPCB 151 SIOPCB siopcb_table[TNUM_SIOP]; 152 152 153 153 /* 154 154 * シリアルI/OポートIDから管理ブロックを取り出すためのマクロ 155 155 */ 156 #define INDEX_SIOP(siopid) ((uint_t)((siopid) -1))157 #define get_siopcb(siopid) 156 #define INDEX_SIOP(siopid) ((uint_t)((siopid)-1)) 157 #define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)])) 158 158 159 159 extern uint32_t get_pll_clock(uint8_t no); … … 166 166 get_clock_aclk(void) 167 167 { 168 uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_CLK_SEL0));168 uint32_t clk_sel0 = sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)); 169 169 uint32_t select = clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SEL; 170 170 uint32_t source = 0; 171 171 172 if (select == 0)172 if (select == 0) 173 173 source = SYSCTRL_CLOCK_FREQ_IN0; 174 else if (select == 1)175 source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER) >>1));174 else if (select == 1) 175 source = get_pll_clock(0) / (2UL << ((clk_sel0 & SYSCTL_CLK_SEL0_ACLK_SDIVISER) >> 1)); 176 176 return source; 177 177 } 178 179 178 180 179 void put_hex(char a, int val) … … 183 182 target_fput_log(a); 184 183 target_fput_log(' '); 185 for (i = 28 ; i >= 0 ; i-= 4){186 j = (val >> i) & 0xf; ;187 if (j > 9)188 j += ('A' -10);184 for (i = 28; i >= 0; i -= 4) { 185 j = (val >> i) & 0xf; 186 if (j > 9) 187 j += ('A' - 10); 189 188 else 190 189 j += '0'; … … 200 199 sio_initialize(intptr_t exinf) 201 200 { 202 SIOPCB 203 uint_t 201 SIOPCB *p_siopcb; 202 uint_t i; 204 203 205 204 /* … … 212 211 } 213 212 214 215 213 /* 216 214 * シリアルI/Oポートのオープン … … 219 217 sio_opn_por(ID siopid, intptr_t exinf) 220 218 { 221 SIOPCB 222 const SIOPINIB 223 bool_t 224 ER 219 SIOPCB *p_siopcb; 220 const SIOPINIB *p_siopinib; 221 bool_t opnflg; 222 ER ercd; 225 223 unsigned long base; 226 224 uint32_t divisor, threshold, tmp; 227 uint8_t 225 uint8_t dlh, dll, dlf; 228 226 229 227 p_siopcb = get_siopcb(siopid); … … 237 235 p_siopcb->exinf = exinf; 238 236 base = p_siopinib->base; 239 if (base == 0)/* no uart port */237 if (base == 0) /* no uart port */ 240 238 goto sio_opn_exit; 241 239 … … 243 241 * ハードウェアの初期化 244 242 */ 245 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);246 247 sil_wrw_mem((uint32_t *)(base +TOFF_UART_IER), 0x00000000);243 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 244 245 sil_wrw_mem((uint32_t *)(base + TOFF_UART_IER), 0x00000000); 248 246 sil_dly_nse(10000); 249 247 250 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 251 divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING; 252 dlh = divisor >> 12; 253 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 254 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 255 256 /* Set UART registers */ 257 sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 258 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh); 259 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll); 260 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf); 261 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00); 262 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 263 sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 264 sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE); 265 sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR), 266 (UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1)); 248 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 249 divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING; 250 dlh = divisor >> 12; 251 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 252 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 253 254 /* Set UART registers */ 255 sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 256 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh); 257 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll); 258 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf); 259 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00); 260 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 261 sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 262 sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE); 263 sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR), 264 (UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/)); 265 sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3); 266 sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00); 267 267 268 268 fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc); 269 269 fpioa_set_function(uartpin[p_siopinib->com][0], p_siopinib->txfunc); 270 sil_orw_mem((uint32_t *)(base +TOFF_UART_IER), UART_IER_RIE);271 tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_RBR));270 sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_RIE); 271 tmp = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR)); 272 272 p_siopcb->opnflg = true; 273 273 (void)(tmp); … … 283 283 284 284 sio_opn_exit:; 285 return (p_siopcb);285 return (p_siopcb); 286 286 } 287 287 … … 292 292 sio_cls_por(SIOPCB *p_siopcb) 293 293 { 294 const SIOPINIB 294 const SIOPINIB *p_siopinib; 295 295 296 296 p_siopinib = p_siopcb->p_siopinib; … … 305 305 * シリアル停止 306 306 */ 307 sil_wrw_mem((uint32_t *)(p_siopinib->base +TOFF_UART_IER), 0x00000000);308 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE +TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk);307 sil_wrw_mem((uint32_t *)(p_siopinib->base + TOFF_UART_IER), 0x00000000); 308 sil_andw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 309 309 p_siopcb->opnflg = false; 310 310 } … … 318 318 SIOPCB *p_siopcb = get_siopcb(exinf); 319 319 unsigned long base = p_siopcb->p_siopinib->base; 320 uint32_t ip = sil_rew_mem((uint32_t *)(base+TOFF_UART_IIR)) & 0x0F;321 320 uint32_t tmp; 322 321 323 if(ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT){ 324 sio_irdy_rcv(p_siopcb->exinf); 325 } 326 else if(ip == UART_IIR_SEND){ 327 sio_irdy_snd(p_siopcb->exinf); 328 } 329 else{ 330 tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR)); 331 tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_USR)); 332 tmp = sil_rew_mem((uint32_t *)(base+TOFF_UART_MSR)); 333 } 334 (void)(tmp); 322 for (;;) { 323 uint32_t ip = sil_rew_mem((uint32_t *)(base + TOFF_UART_IIR)) & 0x0F; 324 325 if (ip == 1) { 326 break; 327 } 328 else if (ip == UART_IIR_RECEIVE || ip == UART_IIR_CTIMEOUT) { 329 sio_irdy_rcv(p_siopcb->exinf); 330 } 331 else if (ip == UART_IIR_SEND) { 332 sio_irdy_snd(p_siopcb->exinf); 333 } 334 else { 335 tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR)); 336 tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_USR)); 337 tmp = sil_rew_mem((uint32_t *)(base + TOFF_UART_MSR)); 338 } 339 (void)(tmp); 340 } 335 341 } 336 342 … … 339 345 */ 340 346 Inline bool_t 341 sio_putready(SIOPCB *p_siopcb)342 { 343 uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_LSR));344 345 if ((lsr & UART_LSR_TFL) == 0){347 sio_putready(SIOPCB *p_siopcb) 348 { 349 uint32_t lsr = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR)); 350 351 if ((lsr & UART_LSR_TFL) == 0) { 346 352 return 1; 347 353 } … … 352 358 sio_snd_chr(SIOPCB *p_siopcb, char c) 353 359 { 354 if (sio_putready(p_siopcb)){355 sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_THR), (uint32_t)c);360 if (sio_putready(p_siopcb)) { 361 sil_wrw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_THR), (uint32_t)c); 356 362 return true; 357 363 } … … 367 373 int_t c = -1; 368 374 369 if ((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base+TOFF_UART_LSR)) & UART_LSR_RFL) != 0){370 c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_RBR)) & 0xFF;375 if ((sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_LSR)) & UART_LSR_RFL) != 0) { 376 c = sil_rew_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_RBR)) & 0xFF; 371 377 } 372 378 return c; … … 381 387 switch (cbrtn) { 382 388 case SIO_RDY_SND: 383 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_TIE);389 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE); 384 390 break; 385 391 case SIO_RDY_RCV: 386 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_RIE);392 sil_orw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE); 387 393 break; 388 394 } … … 397 403 switch (cbrtn) { 398 404 case SIO_RDY_SND: 399 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_TIE);405 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_TIE); 400 406 break; 401 407 case SIO_RDY_RCV: 402 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base +TOFF_UART_IER), UART_IER_RIE);408 sil_andw_mem((uint32_t *)(p_siopcb->p_siopinib->base + TOFF_UART_IER), UART_IER_RIE); 403 409 break; 404 410 } … … 412 418 unsigned long base = siopinib_table[INDEX_PORT(siopid)].base; 413 419 414 sil_wrw_mem((uint32_t *)(base+TOFF_UART_THR), (uint32_t)c); 415 while(0 != (sil_rew_mem((uint32_t *)(base+TOFF_UART_LSR)) & UART_LSR_TFL)); 420 sil_wrw_mem((uint32_t *)(base + TOFF_UART_THR), (uint32_t)c); 421 while (0 != (sil_rew_mem((uint32_t *)(base + TOFF_UART_LSR)) & UART_LSR_TFL)) 422 ; 416 423 417 424 /* 418 425 * 出力が完全に終わるまで待つ 419 426 */ 420 volatile int n = SYS_CLOCK/BPS_SETTING; 421 while(n--); 427 volatile int n = SYS_CLOCK / BPS_SETTING; 428 while (n--) 429 ; 422 430 } 423 431 … … 427 435 void target_uart_init(ID siopid) 428 436 { 429 const SIOPINIB 437 const SIOPINIB *p_siopinib; 430 438 unsigned long base; 431 439 uint32_t divisor, threshold; 432 uint8_t 440 uint8_t dlh, dll, dlf; 433 441 434 442 p_siopinib = &siopinib_table[INDEX_PORT(siopid)]; … … 438 446 * ハードウェアの初期化 439 447 */ 440 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 441 442 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE+TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 443 divisor = (get_clock_aclk() / (threshold+1)) / BPS_SETTING; 444 dlh = divisor >> 12; 445 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 446 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 447 448 /* Set UART registers */ 449 sil_orw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 450 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLH), dlh); 451 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLL), dll); 452 sil_wrw_mem((uint32_t *)(base+TOFF_UART_DLF), dlf); 453 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), 0x00); 454 sil_wrw_mem((uint32_t *)(base+TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 455 sil_andw_mem((uint32_t *)(base+TOFF_UART_LCR), UART_LCR_DMD); 456 sil_orw_mem((uint32_t *)(base+TOFF_UART_IER), UART_IER_THRE); 457 sil_wrw_mem((uint32_t *)(base+TOFF_UART_FCR), 458 (UART_RECEIVE_FIFO1 << 6 | UART_SEND_FIFO8 << 4 | 0x1 << 3 | 0x1)); 448 sil_orw_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_SYSCTL_CLK_EN_PERI), p_siopinib->clk); 449 450 threshold = (sil_rew_mem((uint32_t *)(TADR_SYSCTL_BASE + TOFF_CLK_SEL0)) & SYSCTL_CLK_SEL0_APB0_CLK_SEL) >> 3; 451 divisor = (get_clock_aclk() / (threshold + 1)) / BPS_SETTING; 452 dlh = divisor >> 12; 453 dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST; 454 dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST; 455 456 /* Set UART registers */ 457 sil_orw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 458 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLH), dlh); 459 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLL), dll); 460 sil_wrw_mem((uint32_t *)(base + TOFF_UART_DLF), dlf); 461 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), 0x00); 462 sil_wrw_mem((uint32_t *)(base + TOFF_UART_LCR), (UART_WordLength_8b | UART_StopBits_1 | UART_Parity_No)); 463 sil_andw_mem((uint32_t *)(base + TOFF_UART_LCR), UART_LCR_DMD); 464 sil_orw_mem((uint32_t *)(base + TOFF_UART_IER), UART_IER_THRE); 465 sil_wrw_mem((uint32_t *)(base + TOFF_UART_FCR), 466 (UART_RECEIVE_FIFO14 << 6 | UART_SEND_FIFO8 << 4 /*| 0x1 << 3 DMA mode?*/ | 0x1 /*FIFO enable?*/)); 467 sil_andw_mem((uint32_t *)(base + TOFF_UART_MCR), (1 << 6) | 3); 468 sil_wrw_mem((uint32_t *)(base + TOFF_UART_TCR), 0x00); 459 469 460 470 fpioa_set_function(uartpin[p_siopinib->com][1], p_siopinib->rxfunc);
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