Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/Debug/Makefile	(revision 374)
@@ -172,5 +172,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -226,5 +226,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o client.o jsonsl.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/DebugEnbt/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/DebugEnbt/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/DebugEnbt/Makefile	(revision 374)
@@ -172,5 +172,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -226,5 +226,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o client.o jsonsl.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/DebugEther/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/DebugEther/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/DebugEther/Makefile	(revision 374)
@@ -172,5 +172,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -226,5 +226,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o client.o jsonsl.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/client.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/client.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/client.c	(revision 374)
@@ -33,5 +33,5 @@
  *  の責任を負わない．
  *
- *  @(#) $Id: client.c 1729 2019-01-09 14:44:36Z coas-nagasima $
+ *  @(#) $Id$
  */
 #include <lib/curl_config.h>
@@ -47,5 +47,5 @@
 #include "kernel_cfg.h"
 #include "ff.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "client.h"
 #include "jsonsl.h"
Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/client.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/client.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/client.h	(revision 374)
@@ -33,5 +33,5 @@
  *  の責任を負わない．
  * 
- *  @(#) $Id: client.h 1784 2019-02-06 01:11:25Z coas-nagasima $
+ *  @(#) $Id$
  */
 
Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/echonet_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/echonet_main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/echonet_main.c	(revision 374)
@@ -905,18 +905,18 @@
 static uint8_t main_read_button(analogin_t *obj)
 {
-	float a = analogin_read(obj);
-
-	a *= 5.0;
+	int a = analogin_read_u16(obj);
+
+	a *= 5;
 
 	//printf("Button read analog = %f\r\n",a);
-	if (a < 0.2)
+	if (a < (int)(0.2 * 65536))
 		return BUTTON_DOWN;
-	if (a < 1.0)
+	if (a < (int)(1.0 * 65536))
 		return BUTTON_RIGHT;
-	if (a < 1.7)
+	if (a < (int)(1.7 * 65536))
 		return BUTTON_SELECT;
-	if (a < 2.6)
+	if (a < (int)(2.6 * 65536))
 		return BUTTON_UP;
-	if (a < 4.6)
+	if (a < (int)(4.6 * 65536))
 		return BUTTON_LEFT;
 	else
Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/main.c	(revision 374)
@@ -68,5 +68,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -192,19 +192,14 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
 	//wolfSSL_Debugging_ON();
 
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app1_usb_watt_meter/src/main.cfg	(revision 374)
@@ -51,4 +51,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 INCLUDE("tinet/tinet_asp.cfg");
Index: asp3_tinet_ecnl_arm/trunk/app2_light/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app2_light/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app2_light/Debug/Makefile	(revision 374)
@@ -163,5 +163,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -208,5 +208,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app2_light/DebugEther/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app2_light/DebugEther/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app2_light/DebugEther/Makefile	(revision 374)
@@ -161,5 +161,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -206,5 +206,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app2_light/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app2_light/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app2_light/src/main.c	(revision 374)
@@ -67,5 +67,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -183,17 +183,12 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/app2_light/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app2_light/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app2_light/src/main.cfg	(revision 374)
@@ -51,4 +51,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 INCLUDE("tinet/tinet_asp.cfg");
Index: asp3_tinet_ecnl_arm/trunk/app3_human_detec/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app3_human_detec/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app3_human_detec/Debug/Makefile	(revision 374)
@@ -163,5 +163,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -208,5 +208,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app3_human_detec/DebugEther/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app3_human_detec/DebugEther/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app3_human_detec/DebugEther/Makefile	(revision 374)
@@ -161,5 +161,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -206,5 +206,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app3_human_detec/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app3_human_detec/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app3_human_detec/src/main.c	(revision 374)
@@ -67,5 +67,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -183,17 +183,12 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/app3_human_detec/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app3_human_detec/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app3_human_detec/src/main.cfg	(revision 374)
@@ -51,4 +51,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 INCLUDE("tinet/tinet_asp.cfg");
Index: asp3_tinet_ecnl_arm/trunk/app4_aircon/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app4_aircon/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app4_aircon/Debug/Makefile	(revision 374)
@@ -169,5 +169,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -217,5 +217,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app4_aircon/DebugEther/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app4_aircon/DebugEther/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app4_aircon/DebugEther/Makefile	(revision 374)
@@ -167,5 +167,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -215,5 +215,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app4_aircon/src/echonet_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app4_aircon/src/echonet_main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app4_aircon/src/echonet_main.c	(revision 374)
@@ -1091,18 +1091,18 @@
 static uint8_t main_read_button(analogin_t *obj)
 {
-	float a = analogin_read(obj);
-
-	a *= 5.0;
+	int a = analogin_read_u16(obj);
+
+	a *= 5;
 
 	//printf("Button read analog = %f\r\n",a);
-	if (a < 0.2)
+	if (a < (int)(0.2 * 65536))
 		return BUTTON_DOWN;
-	if (a < 1.0)
+	if (a < (int)(1.0 * 65536))
 		return BUTTON_RIGHT;
-	if (a < 1.7)
+	if (a < (int)(1.7 * 65536))
 		return BUTTON_SELECT;
-	if (a < 2.6)
+	if (a < (int)(2.6 * 65536))
 		return BUTTON_UP;
-	if (a < 4.6)
+	if (a < (int)(4.6 * 65536))
 		return BUTTON_LEFT;
 	else
Index: asp3_tinet_ecnl_arm/trunk/app4_aircon/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app4_aircon/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app4_aircon/src/main.c	(revision 374)
@@ -67,5 +67,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -183,17 +183,12 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/app4_aircon/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app4_aircon/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app4_aircon/src/main.cfg	(revision 374)
@@ -51,4 +51,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 INCLUDE("tinet/tinet_asp.cfg");
Index: asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/Debug/Makefile	(revision 374)
@@ -169,5 +169,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -217,5 +217,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/DebugEther/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/DebugEther/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/DebugEther/Makefile	(revision 374)
@@ -167,5 +167,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -215,5 +215,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/src/main.c	(revision 374)
@@ -67,5 +67,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -183,17 +183,12 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app5_temp_sensor/src/main.cfg	(revision 374)
@@ -51,4 +51,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 INCLUDE("tinet/tinet_asp.cfg");
Index: asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/Debug/Makefile	(revision 374)
@@ -163,5 +163,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -208,5 +208,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/DebugEther/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/DebugEther/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/DebugEther/Makefile	(revision 374)
@@ -161,5 +161,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -206,5 +206,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/src/main.c	(revision 374)
@@ -67,5 +67,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -183,17 +183,12 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app6_hot_water_pot/src/main.cfg	(revision 374)
@@ -51,4 +51,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 INCLUDE("tinet/tinet_asp.cfg");
Index: asp3_tinet_ecnl_arm/trunk/app7_buzzer/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app7_buzzer/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app7_buzzer/Debug/Makefile	(revision 374)
@@ -163,5 +163,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -208,5 +208,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app7_buzzer/DebugEther/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app7_buzzer/DebugEther/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app7_buzzer/DebugEther/Makefile	(revision 374)
@@ -161,5 +161,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -206,5 +206,5 @@
 	APPL_COBJS := $(APPL_COBJS) main.o ntshell_main.o echonet_main.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/app7_buzzer/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app7_buzzer/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app7_buzzer/src/main.c	(revision 374)
@@ -67,5 +67,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -183,17 +183,12 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/app7_buzzer/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/app7_buzzer/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/app7_buzzer/src/main.cfg	(revision 374)
@@ -51,4 +51,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 INCLUDE("tinet/tinet_asp.cfg");
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/Debug/Makefile	(revision 374)
@@ -81,4 +81,10 @@
 
 #
+#  システムサービスコールライブラリ（libsyssvc.a）のディレクトリ名
+#  （システムサービスコールライブラリもmake対象にする時は，空に定義する）
+#
+SYSSVC_LIB = 
+
+#
 #  カーネルを関数単位でコンパイルするかどうかの定義
 #
@@ -161,5 +167,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -193,5 +199,5 @@
 	APPL_COBJS := sample1.o
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o time.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o time.o mbed_stub.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
 ifdef APPLDIRS
@@ -234,4 +240,7 @@
 #  システムサービスに関する定義
 #
+MALLOC_LIB = "${TCINSTALL}arm-none-eabi/lib/thumb/v7-ar/fpv3/hard/libc.a"
+MALLOC_OBJS = lib_a-reent.o lib_a-impure.o lib_a-malloc.o lib_a-mallocr.o lib_a-calloc.o lib_a-callocr.o lib_a-realloc.o lib_a-reallocr.o lib_a-sbrkr.o lib_a-freer.o
+
 SYSSVC_DIRS := $(TECSGENDIR) $(SRCDIR)/tecs_kernel \
 				$(SYSSVC_DIRS) $(SRCDIR)/syssvc
@@ -341,5 +350,5 @@
 #  コンパイルのための変数の定義
 #
-KERNEL_LIB_OBJS = $(KERNEL_ASMOBJS) $(KERNEL_COBJS) $(KERNEL_LCOBJS)
+KERNEL_LIB_OBJS = $(KERNEL_ASMOBJS) $(KERNEL_COBJS) $(KERNEL_LCOBJS) $(MALLOC_OBJS)
 SYSSVC_OBJS = $(SYSSVC_ASMOBJS) $(SYSSVC_COBJS) $(HIDDEN_OBJS)
 APPL_OBJS = $(APPL_ASMOBJS) $(APPL_COBJS) $(APPL_CXXOBJS) $(APPL_BINOBJS)
@@ -355,4 +364,12 @@
 	OBJ_LDFLAGS := $(OBJ_LDFLAGS) -L.
 endif
+ifdef SYSSVC_LIB
+	LIBS_DEP := $(LIBS_DEP) $(SYSSVC_LIB)/libsyssvc.a
+	OBJ_LDFLAGS := $(OBJ_LDFLAGS) -L$(SYSSVC_LIB)
+	REALCLEAN_FILES := $(REALCLEAN_FILES) libsyssvc.a
+else
+	LIBS_DEP := $(LIBS_DEP) libsyssvc.a
+	OBJ_LDFLAGS := $(OBJ_LDFLAGS) -L.
+endif
 
 ifdef TEXT_START_ADDRESS
@@ -418,4 +435,12 @@
 
 #
+#  システムサービスコールライブラリファイルの生成
+#
+libsyssvc.a: $(filter-out tBannerMain.o, $(SYSSVC_OBJS))
+	rm -f libsyssvc.a
+	$(AR) -rcs libsyssvc.a $(filter-out tBannerMain.o, $(SYSSVC_OBJS))
+	$(RANLIB) libsyssvc.a
+
+#
 #  並列makeのための依存関係の定義
 #
@@ -427,5 +452,5 @@
 #  特別な依存関係の定義
 #
-tBannerMain.o: $(filter-out tBannerMain.o,$(ALL_OBJS)) $(LIBS_DEP)
+tBannerMain.o: $(filter-out tBannerMain.o, $(ALL_OBJS)) $(LIBS_DEP)
 
 #
@@ -488,4 +513,7 @@
 	rm -f libkernel.a
 endif
+ifndef SYSSVC_LIB
+	rm -f libsyssvc.a
+endif
 
 .PHONY: cleankernel
@@ -493,4 +521,9 @@
 	rm -f $(OFFSET_H) $(KERNEL_LIB_OBJS)
 	rm -f $(KERNEL_LIB_OBJS:%.o=$(DEPDIR)/%.d)
+
+.PHONY: cleansyssvc
+cleansyssvc:
+	rm -f $(SYSSVC_OBJS)
+	rm -f $(SYSSVC_OBJS:%.o=$(DEPDIR)/%.d)
 
 .PHONY: realclean
@@ -609,4 +642,7 @@
 	$(OBJCOPY) -B arm -I binary -O elf32-littlearm --rename-section .data=.rodata $< $*.o
 
+$(MALLOC_OBJS):
+	$(AR) x $(MALLOC_LIB) "$@"
+
 #
 #  デフォルトコンパイルルールを上書き
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/Makefile.core
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/Makefile.core	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/Makefile.core	(revision 374)
@@ -55,3 +55,3 @@
 	$(CC) -c $(CFLAGS) $(KERNEL_CFLAGS) $<
 
-LDFLAGS := -nostdlib $(LDFLAGS)
+LDFLAGS := -nodefaultlibs $(LDFLAGS)
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/arm.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/arm.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/arm.h	(revision 374)
@@ -5,5 +5,5 @@
  *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
  *                              Toyohashi Univ. of Technology, JAPAN
- *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *  Copyright (C) 2006-2018 by Embedded and Real-Time Systems Laboratory
  *              Graduate School of Information Science, Nagoya Univ., JAPAN
  * 
@@ -119,4 +119,12 @@
 
 /*
+ *  CP15のコプロセッサアクセス制御レジスタ（CPACR）の設定値
+ */
+#define CP15_CPACR_ASEDIS			UINT_C(0x80000000)
+#define CP15_CPACR_D32DIS			UINT_C(0x40000000)
+#define CP15_CPACR_CP11_FULLACCESS	UINT_C(0x00c00000)
+#define CP15_CPACR_CP10_FULLACCESS	UINT_C(0x00300000)
+
+/*
  *  CP15のフォールト状態レジスタの参照値
  */
@@ -444,3 +452,9 @@
 
 #endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  浮動小数点例外制御レジスタ（FPEXC）の設定値
+ */
+#define FPEXC_ENABLE		UINT_C(0x40000000)
+
 #endif /* TOPPERS_ARM_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/arm_insn.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/arm_insn.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/arm_insn.h	(revision 374)
@@ -5,5 +5,5 @@
  *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
  *                              Toyohashi Univ. of Technology, JAPAN
- *  Copyright (C) 2006-2017 by Embedded and Real-Time Systems Laboratory
+ *  Copyright (C) 2006-2018 by Embedded and Real-Time Systems Laboratory
  *              Graduate School of Information Science, Nagoya Univ., JAPAN
  * 
@@ -227,4 +227,8 @@
 #define CP15_WRITE_ACTLR(reg)	Asm("mcr p15, 0, %0, c1, c0, 1"::"r"(reg))
 
+/* コプロセッサアクセス制御レジスタ */
+#define CP15_READ_CPACR(reg)	Asm("mrc p15, 0, %0, c1, c0, 2":"=r"(reg))
+#define CP15_WRITE_CPACR(reg)	Asm("mcr p15, 0, %0, c1, c0, 2"::"r"(reg))
+
 /*
  *  CP15によるキャッシュ操作マクロ
@@ -421,3 +425,25 @@
 
 #endif /* __TARGET_ARCH_ARM == 7 */
+
+/*
+ *  浮動小数点例外制御レジスタ（FPEXC）の現在値の読出し
+ */
+Inline uint32_t
+current_fpexc(void)
+{
+	uint32_t	fpexc;
+
+	Asm("vmrs %0, fpexc" : "=r"(fpexc));
+	return(fpexc);
+}
+
+/*
+ *  浮動小数点例外制御レジスタ（FPEXC）の現在値の変更
+ */
+Inline void
+set_fpexc(uint32_t fpexc)
+{
+	Asm("vmsr fpexc, %0" : : "r"(fpexc));
+}
+
 #endif /* TOPPERS_ARM_INSN_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_check.trb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_check.trb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_check.trb	(revision 374)
@@ -19,6 +19,7 @@
 #
 inhTable = SYMBOL("_kernel_inh_table")
+offset = SYMBOL("__etext") - SYMBOL("__data_start__")
 $cfgData[:DEF_INH].each do |key, params|
-  inthdr = PEEK(inhTable + params[:inhno] * $sizeof_FP, $sizeof_FP)
+  inthdr = PEEK(inhTable + offset + params[:inhno] * $sizeof_FP, $sizeof_FP)
 
   #	割込みハンドラの先頭番地のチェック［NGKI3056］
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel.h	(revision 374)
@@ -6,5 +6,5 @@
  *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
  *                              Toyohashi Univ. of Technology, JAPAN
- *  Copyright (C) 2004-2016 by Embedded and Real-Time Systems Laboratory
+ *  Copyright (C) 2004-2018 by Embedded and Real-Time Systems Laboratory
  *              Graduate School of Information Science, Nagoya Univ., JAPAN
  * 
@@ -51,4 +51,9 @@
 #ifndef TOPPERS_CORE_KERNEL_H
 #define TOPPERS_CORE_KERNEL_H
+
+/*
+ *  ターゲット定義のタスク属性
+ */
+#define TA_FPU		UINT_C(0x08)	/* FPUレジスタをコンテキストに含める */
 
 /*
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel.trb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel.trb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel.trb	(revision 374)
@@ -65,5 +65,5 @@
 $kernelCfgC.comment_header("Interrupt Handler Table")
 
-$kernelCfgC.add("const FP _kernel_inh_table[TNUM_INHNO] = {")
+$kernelCfgC.add("FP _kernel_inh_table[TNUM_INHNO] = {")
 $INHNO_VALID.each_with_index do |inhnoVal, index|
   $kernelCfgC.add(",") if index > 0
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel_impl.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel_impl.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel_impl.c	(revision 374)
@@ -170,4 +170,29 @@
 
 /*
+ *  FPUの初期化
+ */
+#ifdef USE_ARM_FPU
+
+void
+arm_fpu_initialize(void)
+{
+	uint32_t	reg;
+
+	/*
+	 *  CP10とCP11をアクセス可能に設定する．
+	 */
+	CP15_READ_CPACR(reg);
+	reg |= (CP15_CPACR_CP10_FULLACCESS | CP15_CPACR_CP11_FULLACCESS);
+	CP15_WRITE_CPACR(reg);
+
+	/*
+	 *  FPUをディスエーブルする．
+	 */
+	set_fpexc(current_fpexc() & ~FPEXC_ENABLE);
+}
+
+#endif /* USE_ARM_FPU */
+
+/*
  *  コア依存の初期化
  */
@@ -187,4 +212,11 @@
 	arm_mmu_initialize();
 #endif /* USE_ARM_MMU */
+
+	/*
+	 *  FPUの初期化
+	 */
+#ifdef USE_ARM_FPU
+	arm_fpu_initialize();
+#endif /* USE_ARM_FPU */
 
 	/*
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel_impl.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel_impl.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_kernel_impl.h	(revision 374)
@@ -55,4 +55,11 @@
 
 /*
+ *  ターゲット依存のタスク属性（エラーチェック用）
+ */
+#ifdef USE_ARM_FPU
+#define TARGET_TSKATR		(TA_FPU)
+#endif /* USE_ARM_FPU */
+
+/*
  *  エラーチェック方法の指定
  */
@@ -324,5 +331,5 @@
  *  割込みハンドラテーブル（kernel_cfg.c）
  */
-extern const FP inh_table[TNUM_INHNO];
+extern FP inh_table[TNUM_INHNO];
 
 /*
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_offset.trb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_offset.trb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_offset.trb	(revision 374)
@@ -17,4 +17,5 @@
 GenerateDefine("TCB_sp", $offsetof_TCB_sp)
 GenerateDefine("TCB_pc", $offsetof_TCB_pc)
+GenerateDefine("TINIB_tskatr", $offsetof_TINIB_tskatr)
 GenerateDefine("TINIB_exinf", $offsetof_TINIB_exinf)
 GenerateDefine("TINIB_task", $offsetof_TINIB_task)
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_support.S
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_support.S	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/core_support.S	(revision 374)
@@ -6,8 +6,8 @@
  *  Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
  *                              Toyohashi Univ. of Technology, JAPAN
- *  Copyright (C) 2006-2017 by Embedded and Real-Time Systems Laboratory
+ *  Copyright (C) 2006-2018 by Embedded and Real-Time Systems Laboratory
  *              Graduate School of Information Science, Nagoya Univ., JAPAN
  * 
- *  上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
  *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
  *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
@@ -55,4 +55,11 @@
 
 /*
+ *  使用する命令セットの定義
+ */
+#ifdef USE_ARM_FPU
+	.fpu	vfpv3
+#endif /* USE_ARM_FPU */
+
+/*
  *  例外ベクタ
  */
@@ -101,11 +108,20 @@
 	 *  マスク全解除状態・ディスパッチ許可状態で呼び出される．
 	 */
-	push	{r12,lr}				/* 戻り番地を保存，r12はダミー */
+	push	{r12,lr}				/* 戻り番地（lr）を保存 */
+									/* r12はアラインメントのため */
 #ifdef TOPPERS_SUPPORT_OVRHDR
 	bl		ovrtimer_stop
 #endif /* TOPPERS_SUPPORT_OVRHDR */
-	stmfd	sp!, {r4-r11}			/* 非スクラッチレジスタの保存 */
+	push	{r4-r11}				/* 非スクラッチレジスタの保存 */
 	ldr		r0, =p_runtsk			/* p_runtsk → r0 */
 	ldr		r0, [r0]
+#ifdef USE_ARM_FPU
+	ldr		r2, [r0,#TCB_p_tinib]	/* p_runtsk->p_tinib → r2 */
+	ldr		r1, [r2,#TINIB_tskatr]	/* p_runtsk->p_tinib->tskatr → r1 */
+	tst		r1, #TA_FPU
+	beq		1f
+	vpush	{d8-d15}				/* 非スクラッチFPUレジスタの保存 */
+1:
+#endif /* USE_ARM_FPU */
 	str		sp, [r0,#TCB_sp]		/* スタックポインタを保存 */
 	adr		r1, dispatch_r
@@ -114,5 +130,21 @@
 
 ALABEL(dispatch_r)
-	ldmfd	sp!, {r4-r11}			/* 非スクラッチレジスタの復帰 */
+	/*
+	 * 【この時点のレジスタ状態】
+	 *  r4：p_runtsk（タスク切換え後）
+	 */
+#ifdef USE_ARM_FPU
+	ldr		r2, [r4,#TCB_p_tinib]	/* p_runtsk->p_tinib → r2 */
+	ldr		r1, [r2,#TINIB_tskatr]	/* p_runtsk->p_tinib->tskatr → r1 */
+	tst		r1, #TA_FPU
+	vmrs	r0, fpexc
+	biceq	r0, r0, #FPEXC_ENABLE
+	orrne	r0, r0, #FPEXC_ENABLE
+	vmsr	fpexc, r0				/* FPEXCを設定 */
+	beq		1f
+	vpop	{d8-d15}				/* 非スクラッチFPUレジスタの復帰 */
+1:
+#endif /* USE_ARM_FPU */
+	pop		{r4-r11}				/* 非スクラッチレジスタの復帰 */
 #ifdef TOPPERS_SUPPORT_OVRHDR
 	bl		ovrtimer_start
@@ -136,4 +168,9 @@
 	 */
 
+	/*
+	 *  各種のデバイス（特に割込みコントローラ）の設定が完了するのを待つ．
+	 */
+	asm_data_sync_barrier r0
+	
 	/*
 	 *	タスクコンテキストに切り換える．
@@ -232,6 +269,9 @@
 ALABEL(call_exit_kernel)
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_INTLOCK)
-	ldr		r0, =istkpt				/* 非タスクコンテキストのスタックへ */
+	ldr		r0, =istkpt				/* 非タスクコンテキスト用のスタックに */
 	ldr		sp, [r0]
+	ldr		r0, =excpt_nest_count	/* 例外ネストカウントを1に */
+	mov		r1, #1
+	str		r1, [r0]
 	b		exit_kernel
 
@@ -243,5 +283,6 @@
 	AGLOBAL(start_r)
 	/*
-	 *  ディスパッチャ本体から呼び出されるため，p_runtskはr4に入っている．
+	 * 【この時点のレジスタ状態】
+	 *  r4：p_runtsk（タスク切換え後）
 	 */
 ALABEL(start_r)
@@ -253,4 +294,12 @@
 	ldr		lr, =ext_tsk			/* タスク本体からの戻り番地を設定 */
 	ldr		r2, [r4,#TCB_p_tinib]	/* p_runtsk->p_tinib → r2 */
+#ifdef USE_ARM_FPU
+	ldr		r1, [r2,#TINIB_tskatr]	/* p_runtsk->p_tinib->tskatr → r1 */
+	tst		r1, #TA_FPU
+	vmrs	r0, fpexc
+	biceq	r0, r0, #FPEXC_ENABLE
+	orrne	r0, r0, #FPEXC_ENABLE
+	vmsr	fpexc, r0				/* FPEXCを設定 */
+#endif /* USE_ARM_FPU */
 	ldr		r0, [r2,#TINIB_exinf]	/* exinfをパラメータに */
 	ldr		r1, [r2,#TINIB_task]	/* タスク起動番地にジャンプ */
@@ -270,11 +319,12 @@
 #if __TARGET_ARCH_ARM < 6
 	/*
-	 *  スーパバイザモードに切り換え，スクラッチレジスタを保存する．
+	 *  スーパバイザモードに切り換え，スクラッチレジスタ＋αを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT)
-	stmfd	sp!, {r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
-
-	/*
-	 *  IRQモードに戻して，戻り番地とspsr（戻り先のcpsr）を取得する．
+	push	{r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
+
+	/*
+	 *  IRQモードに戻して，戻り番地（lr−4）と戻り先のcpsr（spsr）を取
+	 *  得する．
 	 */
 	msr		cpsr_c, #(CPSR_IRQ_MODE AOR CPSR_IRQ_BIT)
@@ -283,13 +333,13 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，戻り番地とspsrを保存する．
+	 *  スーパバイザモードに切り換え，戻り番地と戻り先のcpsrを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_IRQ_BIT)
-	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存 */
-	push	{r1}					/* spsrをスタックに保存 */
+	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存（pcの場所）*/
+	push	{r1}					/* 戻り先のcpsrをスタックに保存 */
 #else /* __TARGET_ARCH_ARM < 6 */
 	/*
-	 *  戻り先（lr）とspsr（cpsr_svc）をスーパバイザモードのスタックに
-	 *  保存する．
+	 *  戻り番地（lr）と戻り先のcpsr（spsr）をスーパバイザモードのスタッ
+	 *  クに保存する．
 	 */
 	sub		lr, lr, #4				/* 戻り番地の算出 */
@@ -297,8 +347,8 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，スクラッチレジスタを保存する．
+	 *  スーパバイザモードに切り換え，スクラッチレジスタ＋αを保存する．
 	 */
 	cps		#CPSR_SVC_MODE
-	stmfd	sp!, {r0-r5,r12,lr}
+	push	{r0-r5,r12,lr}
 #endif /* __TARGET_ARCH_ARM < 6 */
 
@@ -308,6 +358,6 @@
 	and		r1, sp, #4
 	sub		sp, sp, r1
-	push	{r0,r1}					/* r0はスペース確保のため */
-
+	push	{r0,r1}					/* スタックポインタの調整値を保存 */
+									/* r0はスペース確保のため */
 	/*
 	 *  例外ネストカウントをインクリメントする．割込みが非タスクコンテキ
@@ -328,4 +378,14 @@
 #endif /* TOPPERS_SUPPORT_OVRHDR */
 
+#ifdef USE_ARM_FPU
+	/*
+	 *  FPUをディスエーブルする．
+	 */
+	vmrs	r0, fpexc
+	str		r0, [sp]				/* FPEXCを保存（r0の場所）*/
+	bic		r0, r0, #FPEXC_ENABLE
+	vmsr	fpexc, r0				/* FPEXCを設定 */
+#endif /* USE_ARM_FPU */
+	
 	/*
 	 *  非タスクコンテキスト用のスタックに切り換える．
@@ -339,4 +399,7 @@
 	/*
 	 *  割込みコントローラを操作し，割込み番号を取得する．
+	 *
+	 *  irc_begin_intは，スタックトップ（r0の場所）に，irc_end_intで用
+	 *  いる情報を保存する．
 	 */
 	bl		irc_begin_int
@@ -420,4 +483,12 @@
 	mov   	sp, r3
 
+#ifdef USE_ARM_FPU
+	/*
+	 *  FPUを元に戻す．
+	 */
+	ldr		r0, [sp]				/* FPEXCを復帰 */
+	vmsr	fpexc, r0
+#endif /* USE_ARM_FPU */
+	
 	/*
 	 *  p_runtskがNULLか判定する．
@@ -433,5 +504,5 @@
 	pop		{r0,r1}					/* スタックポインタの調整を元に戻す */
 	add		sp, sp, r1
-	add		sp, sp, #40				/* スクラッチレジスタを捨てる */
+	add		sp, sp, #40				/* スクラッチレジスタ等を捨てる */
 	b		dispatcher_0
 
@@ -440,4 +511,8 @@
 	 */
 ALABEL(irq_handler_3)
+	/*
+	 * 【この時点のレジスタ状態】
+	 *  r0：p_runtsk
+	 */
 	ldr		r1, =p_schedtsk			/* p_schedtsk → r1 */
 	ldr		r1, [r1]
@@ -448,5 +523,18 @@
 	 *  コンテキストを保存する．
 	 */
-	stmfd	sp!, {r6-r11}			/* 非スクラッチレジスタの保存 */
+	push	{r6-r11}				/* 残りのレジスタの保存 */
+#ifdef USE_ARM_FPU
+	ldr		r2, [r0,#TCB_p_tinib]	/* p_runtsk->p_tinib → r2 */
+	ldr		r1, [r2,#TINIB_tskatr]	/* p_runtsk->p_tinib->tskatr → r1 */
+	tst		r1, #TA_FPU
+	beq		1f						/* TA_FPU属性でない場合は分岐 */
+#ifdef USE_ARM_FPU_D32
+	vpush	{d16-d31}
+#endif /* USE_ARM_FPU_D32 */
+	vpush	{d0-d15}				/* 全FPUレジスタの保存 */
+	vmrs	r1, fpscr
+	push	{r1,r2}					/* FPSCRの保存 */
+1:									/* r2はアラインメントのため */
+#endif /* USE_ARM_FPU */
 	str		sp, [r0,#TCB_sp]		/* スタックポインタを保存 */
 	adr		r1, ret_int_r			/* 実行再開番地を保存 */
@@ -457,6 +545,26 @@
 	/*
 	 *  コンテキストを復帰する．
-	 */
-	ldmfd	sp!, {r6-r11}			/* 非スクラッチレジスタの復帰 */
+	 *
+	 * 【この時点のレジスタ状態】
+	 *  r4：p_runtsk（タスク切換え後）
+	 */
+#ifdef USE_ARM_FPU
+	ldr		r2, [r4,#TCB_p_tinib]	/* p_runtsk->p_tinib → r2 */
+	ldr		r1, [r2,#TINIB_tskatr]	/* p_runtsk->p_tinib->tskatr → r1 */
+	tst		r1, #TA_FPU
+	vmrs	r0, fpexc
+	biceq	r0, r0, #FPEXC_ENABLE
+	orrne	r0, r0, #FPEXC_ENABLE
+	vmsr	fpexc, r0				/* FPEXCを設定 */
+	beq		1f						/* TA_FPU属性でない場合は分岐 */
+	pop		{r1,r2}					/* FPSCRの復帰 */
+	vmsr	fpscr, r1
+	vpop	{d0-d15}				/* 全FPUレジスタの復帰 */
+#ifdef USE_ARM_FPU_D32
+	vpop	{d16-d31}
+#endif /* USE_ARM_FPU_D32 */
+1:
+#endif /* USE_ARM_FPU */
+	pop		{r6-r11}				/* 残りのレジスタの復帰 */
 
 ALABEL(irq_handler_4)
@@ -469,9 +577,9 @@
 
 	/*
-	 *  割込み／CPU例外処理からのリターン
+	 *  割込み処理からのリターン
 	 *
-	 *  割込み／CPU例外処理からのリターンにより，CPUロック解除状態に遷
-	 *  移するようにする必要があるが，ARMはCPSRのビットによってCPUロッ
-	 *  ク状態を表しているため，CPSRを元に戻してリターンすればよい．
+	 *  割込み処理からのリターンにより，CPUロック解除状態に遷移するよ
+	 *  うにする必要があるが，ARMはCPSRのビットによってCPUロック状態を
+	 *  表しているため，CPSRを元に戻してリターンすればよい．
 	 */
 ALABEL(irq_handler_5)
@@ -480,10 +588,10 @@
 
 #if __TARGET_ARCH_ARM < 6
-	ldmfd	sp!, {r0}				/* 戻り先のcpsrをspsrに設定 */
+	pop		{r0}					/* 戻り先のcpsrをspsrに設定 */
 	msr		spsr_cxsf, r0
 	ldmfd	sp!, {r0-r5,r12,lr,pc}^	/* コンテキストの復帰 */
 									/* ^付きなので，spsr → cpsr */
 #else /* __TARGET_ARCH_ARM < 6 */
-	ldmfd	sp!, {r0-r5,r12,lr}
+	pop		{r0-r5,r12,lr}			/* スクラッチレジスタ＋αの復帰 */
 	rfefd	sp!
 #endif /* __TARGET_ARCH_ARM < 6 */
@@ -509,11 +617,12 @@
 	/*
 	 *  IビットとFビットをセットし，スーパバイザモードに切り換え，スク
-	 *  ラッチレジスタを保存する．
+	 *  ラッチレジスタ＋αを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	stmfd	sp!, {r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
-
-	/*
-	 *  未定義モードに戻して，戻り番地とspsrを取得する．
+	push	{r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
+
+	/*
+	 *  未定義モードに戻して，戻り番地（lr）と戻り先のcpsr（spsr）を取
+	 *  得する．
 	 */
 	msr		cpsr_c, #(CPSR_UND_MODE AOR CPSR_FIQ_IRQ_BIT)
@@ -522,21 +631,21 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，戻り番地とspsrを保存する．
+	 *  スーパバイザモードに切り換え，戻り番地と戻り先のcpsrを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存 */
-	push	{r1}					/* spsrをスタックに保存 */
+	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存（pcの場所）*/
+	push	{r1}					/* 戻り先のcpsrをスタックに保存 */
 #else /* __TARGET_ARCH_ARM < 6 */
 	/*
-	 *  戻り先（lr）とspsr（cpsr_svc）をスーパバイザモードのスタックに
-	 *  保存する．
+	 *  戻り番地（lr）と戻り先のcpsr（spsr）をスーパバイザモードのスタッ
+	 *  クに保存する．
 	 */
 	srsfd	#CPSR_SVC_MODE!
 
 	/*
-	 *  スーパバイザモードに切り換え，スクラッチレジスタを保存する．
+	 *  スーパバイザモードに切り換え，スクラッチレジスタ＋αを保存する．
 	 */
 	cps		#CPSR_SVC_MODE
-	stmfd	sp!, {r0-r5,r12,lr}
+	push	{r0-r5,r12,lr}
 #endif /* __TARGET_ARCH_ARM < 6 */
 	mov		r4, #EXCNO_UNDEF
@@ -550,5 +659,4 @@
 	ATEXT
 	AALIGN(2)
-	AWEAK(svc_handler)
 	AGLOBAL(svc_handler)
 ALABEL(svc_handler)
@@ -558,32 +666,23 @@
 #if __TARGET_ARCH_ARM < 6
 	/*
-	 *  IビットとFビットをセットし，スクラッチレジスタを保存する．
+	 *  IビットとFビットをセットし，戻り番地（lr），スクラッチレジスタ
+	 *  ＋α，戻り先のcpsr（spsr）を保存する（lrは二重に保存される）．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	stmfd	sp!, {r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
-
-	/*
-	 *  戻り番地とspsrを取得する．
-	 */
-	mov		r2, lr
+	push	{lr}
+	push	{r0-r5,r12,lr}
 	mrs		r1, spsr
-
-	/*
-	 *  戻り番地とspsrを保存する．
-	 */
-	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存 */
-	push	{r1}					/* spsrをスタックに保存 */
+	push	{r1}
 #else /* __TARGET_ARCH_ARM < 6 */
 	/*
-	 *  戻り先（lr）とspsr（cpsr_svc）をスーパバイザモードのスタックに
-	 *  保存する．
+	 *  戻り番地（lr）と戻り先のcpsr（spsr）をスーパバイザモードのスタッ
+	 *  クに保存する．
 	 */
 	srsfd	#CPSR_SVC_MODE!
 
 	/*
-	 *  スーパバイザモードで，スクラッチレジスタを保存する．
-	 */
-	cps		#CPSR_SVC_MODE			/* 不要と思われる */
-	stmfd	sp!, {r0-r5,r12,lr}
+	 *  スーパバイザモードで，スクラッチレジスタ＋αを保存する．
+	 */
+	push	{r0-r5,r12,lr}
 #endif /* __TARGET_ARCH_ARM < 6 */
 	mov		r4, #EXCNO_SVC
@@ -605,11 +704,12 @@
 	/*
 	 *  IビットとFビットをセットし，スーパバイザモードに切り換え，スク
-	 *  ラッチレジスタを保存する．
+	 *  ラッチレジスタ＋αを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	stmfd	sp!, {r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
-
-	/*
-	 *  アボートモードに戻して，戻り番地とspsrを取得する．
+	push	{r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
+
+	/*
+	 *  アボートモードに戻して，戻り番地（lr）と戻り先のcpsr（spsr）を
+	 *  取得する．
 	 */
 	msr		cpsr_c, #(CPSR_ABT_MODE AOR CPSR_FIQ_IRQ_BIT)
@@ -618,21 +718,21 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，戻り番地とspsrを保存する．
+	 *  スーパバイザモードに切り換え，戻り番地と戻り先のcpsrを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存 */
-	push	{r1}					/* spsrをスタックに保存 */
+	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存（pcの場所）*/
+	push	{r1}					/* 戻り先のcpsrをスタックに保存 */
 #else /* __TARGET_ARCH_ARM < 6 */
 	/*
-	 *  戻り先（lr）とspsr（cpsr_svc）をスーパバイザモードのスタックに
-	 *  保存する．
+	 *  戻り番地（lr）と戻り先のcpsr（spsr）をスーパバイザモードのスタッ
+	 *  クに保存する．
 	 */
 	srsfd	#CPSR_SVC_MODE!
 
 	/*
-	 *  スーパバイザモードに切り換え，スクラッチレジスタを保存する．
+	 *  スーパバイザモードに切り換え，スクラッチレジスタ＋αを保存する．
 	 */
 	cps		#CPSR_SVC_MODE
-	stmfd	sp!, {r0-r5,r12,lr}
+	push	{r0-r5,r12,lr}
 #endif /* __TARGET_ARCH_ARM < 6 */
 	mov		r4, #EXCNO_PABORT
@@ -666,11 +766,12 @@
 	/*
 	 *  IビットとFビットをセットし，スーパバイザモードに切り換え，スク
-	 *  ラッチレジスタを保存する．
+	 *  ラッチレジスタ＋αを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	stmfd	sp!, {r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
-
-	/*
-	 *  アボートモードに戻して，戻り番地とspsrを取得する．
+	push	{r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
+
+	/*
+	 *  アボートモードに戻して，戻り番地（lr）と戻り先のcpsr（spsr）を
+	 *  取得する．
 	 */
 	msr		cpsr_c, #(CPSR_ABT_MODE AOR CPSR_FIQ_IRQ_BIT)
@@ -679,21 +780,21 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，戻り番地とspsrを保存する．
+	 *  スーパバイザモードに切り換え，戻り番地と戻り先のcpsrを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存 */
-	push	{r1}					/* spsrをスタックに保存 */
+	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存（pcの場所）*/
+	push	{r1}					/* 戻り先のcpsrをスタックに保存 */
 #else /* __TARGET_ARCH_ARM < 6 */
 	/*
-	 *  戻り先（lr）とspsr（cpsr_svc）をスーパバイザモードのスタックに
-	 *  保存する．
+	 *  戻り番地（lr）と戻り先のcpsr（spsr）をスーパバイザモードのスタッ
+	 *  クに保存する．
 	 */
 	srsfd	#CPSR_SVC_MODE!
 
 	/*
-	 *  スーパバイザモードに切り換え，スクラッチレジスタを保存する．
+	 *  スーパバイザモードに切り換え，スクラッチレジスタ＋αを保存する．
 	 */
 	cps		#CPSR_SVC_MODE
-	stmfd	sp!, {r0-r5,r12,lr}
+	push	{r0-r5,r12,lr}
 #endif /* __TARGET_ARCH_ARM < 6 */
 	mov		r4, #EXCNO_DABORT
@@ -708,13 +809,14 @@
 	/*
 	 *  IビットとFビットをセットし，スーパバイザモードに切り換え，スタッ
-	 *  クポインタを初期化し，スクラッチレジスタを保存する．
+	 *  クポインタを初期化し，スクラッチレジスタ＋αを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
 	ldr		sp, =istkpt
 	ldr		sp, [sp]
-	stmfd	sp!, {r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
-
-	/*
-	 *  アボートモードに戻して，戻り番地とspsrを取得する．
+	push	{r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
+
+	/*
+	 *  アボートモードに戻して，戻り番地（lr）と戻り先のcpsr（spsr）を
+	 *  取得する．
 	 */
 	msr		cpsr_c, #(CPSR_ABT_MODE AOR CPSR_FIQ_IRQ_BIT)
@@ -723,9 +825,9 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，戻り番地とspsrを保存する．
+	 *  スーパバイザモードに切り換え，戻り番地と戻り先のcpsrを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存 */
-	push	{r1}					/* spsrをスタックに保存 */
+	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存（pcの場所）*/
+	push	{r1}					/* 戻り先のcpsrをスタックに保存 */
 #else /* __TARGET_ARCH_ARM < 6 */
 	/*
@@ -738,6 +840,6 @@
 
 	/*
-	 *  アボートモードに戻して，戻り先（lr）とspsr（cpsr_svc）をスーパ
-	 *  バイザモードのスタックに保存する．
+	 *  アボートモードに戻して，戻り番地（lr）と戻り先のcpsr（spsr）を
+	 *  スーパバイザモードのスタックに保存する．
 	 */
 	cps		#CPSR_ABT_MODE
@@ -745,8 +847,8 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，スクラッチレジスタを保存する．
+	 *  スーパバイザモードに切り換え，スクラッチレジスタ＋αを保存する．
 	 */
 	cps		#CPSR_SVC_MODE
-	stmfd	sp!, {r0-r5,r12,lr}
+	push	{r0-r5,r12,lr}
 #endif /* __TARGET_ARCH_ARM < 6 */
 
@@ -776,11 +878,12 @@
 	/*
 	 *  IビットとFビットをセットし，スーパバイザモードに切り換え，スク
-	 *  ラッチレジスタを保存する．
+	 *  ラッチレジスタ＋αを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	stmfd	sp!, {r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
-
-	/*
-	 *  FIQモードに戻して，戻り番地とspsrを取得する．
+	push	{r0-r5,r12,lr,pc}		/* pcはスペース確保のため */
+
+	/*
+	 *  FIQモードに戻して，戻り番地（lr）と戻り先のcpsr（spsr）を取得
+	 *  する．
 	 */
 	msr		cpsr_c, #(CPSR_FIQ_MODE AOR CPSR_FIQ_IRQ_BIT)
@@ -789,21 +892,21 @@
 
 	/*
-	 *  スーパバイザモードに切り換え，戻り番地とspsrを保存する．
+	 *  スーパバイザモードに切り換え，戻り番地と戻り先のcpsrを保存する．
 	 */
 	msr		cpsr_c, #(CPSR_SVC_MODE AOR CPSR_FIQ_IRQ_BIT)
-	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存 */
-	push	{r1}					/* spsrをスタックに保存 */
+	str		r2, [sp,#0x20]			/* 戻り番地をスタックに保存（pcの場所）*/
+	push	{r1}					/* 戻り先のcpsrをスタックに保存 */
 #else /* __TARGET_ARCH_ARM < 6 */
 	/*
-	 *  戻り先（lr）とspsr（cpsr_svc）をスーパバイザモードのスタックに
-	 *  保存する．
+	 *  戻り番地（lr）と戻り先のcpsr（spsr）をスーパバイザモードのスタッ
+	 *  クに保存する．
 	 */
 	srsfd	#CPSR_SVC_MODE!
 
 	/*
-	 *  スーパバイザモードに切り換え，スクラッチレジスタを保存する．
+	 *  スーパバイザモードに切り換え，スクラッチレジスタ＋αを保存する．
 	 */
 	cps		#CPSR_SVC_MODE
-	stmfd	sp!, {r0-r5,r12,lr}
+	push	{r0-r5,r12,lr}
 #endif /* __TARGET_ARCH_ARM < 6 */
 	mov		r4, #EXCNO_FIQ
@@ -815,10 +918,10 @@
 /*
  *  CPU例外ハンドラ出入口処理の共通部分
- *
- * 【この時点のレジスタ状態】
- *  r4：CPU例外ハンドラ番号
  */
 ALABEL(exc_handler_1)
 	/*
+	 * 【この時点のレジスタ状態】
+	 *  r4：CPU例外ハンドラ番号
+	 *
 	 *  CPU例外が発生した状況の判断に用いるために，CPU例外発生前の割
 	 *  込み優先度マスクと例外ネストカウントをスタックに保存する．
@@ -836,6 +939,6 @@
 	and		r1, sp, #4
 	sub		sp, sp, r1
-	push	{r0,r1}					/* r0はスペース確保のため */
-
+	push	{r0,r1}					/* スタックポインタの調整値を保存 */
+									/* r0はスペース確保のため */
 	/*
 	 *  カーネル管理外のCPU例外か判定する
@@ -873,4 +976,14 @@
 #endif /* TOPPERS_SUPPORT_OVRHDR */
 
+#ifdef USE_ARM_FPU
+	/*
+	 *  FPUをディスエーブルする．
+	 */
+	vmrs	r0, fpexc
+	str		r0, [sp]				/* FPEXCを保存（r0の場所）*/
+	bic		r0, r0, #FPEXC_ENABLE
+	vmsr	fpexc, r0				/* FPEXCを設定 */
+#endif /* USE_ARM_FPU */
+	
 	/*
 	 *  非タスクコンテキスト用のスタックに切り換える．
@@ -890,4 +1003,7 @@
 	/*
 	 *  （必要なら）割込みコントローラを操作する．
+	 *
+	 *  irc_begin_excは，スタックトップ（r0の場所）に，irc_end_excで用
+	 *  いる情報を保存する．
 	 */
 	bl		irc_begin_exc
@@ -970,4 +1086,12 @@
 	mov		sp, r3
 
+#ifdef USE_ARM_FPU
+	/*
+	 *  FPUを元に戻す．
+	 */
+	ldr		r0, [sp]				/* FPEXCを復帰 */
+	vmsr	fpexc, r0
+#endif /* USE_ARM_FPU */
+	
 	/*
 	 *  p_runtskがNULLか判定する．
@@ -990,4 +1114,8 @@
 	 */
 ALABEL(exc_handler_3)
+	/*
+	 * 【この時点のレジスタ状態】
+	 *  r0：p_runtsk
+	 */
 	ldr		r1, =p_schedtsk			/* p_schedtsk → r1 */
 	ldr		r1, [r1]
@@ -998,5 +1126,18 @@
 	 *  コンテキストを保存する．
 	 */
-	stmfd	sp!, {r6-r11}			/* 非スクラッチレジスタの保存 */
+	push	{r6-r11}				/* 残りのレジスタの保存 */
+#ifdef USE_ARM_FPU
+	ldr		r2, [r0,#TCB_p_tinib]	/* p_runtsk->p_tinib → r2 */
+	ldr		r1, [r2,#TINIB_tskatr]	/* p_runtsk->p_tinib->tskatr → r1 */
+	tst		r1, #TA_FPU
+	beq		1f						/* TA_FPU属性でない場合は分岐 */
+#ifdef USE_ARM_FPU_D32
+	vpush	{d16-d31}
+#endif /* USE_ARM_FPU_D32 */
+	vpush	{d0-d15}				/* 全FPUレジスタの保存 */
+	vmrs	r1, fpscr
+	push	{r1,r2}					/* FPSCRの保存 */
+1:									/* r2はアラインメントのため */
+#endif /* USE_ARM_FPU */
 	str		sp, [r0,#TCB_sp]		/* スタックポインタを保存 */
 	adr		r1, ret_exc_r			/* 実行再開番地を保存 */
@@ -1007,6 +1148,26 @@
 	/*
 	 *  コンテキストを復帰する．
-	 */
-	ldmfd	sp!, {r6-r11}			/* 非スクラッチレジスタの復帰 */
+	 *
+	 * 【この時点のレジスタ状態】
+	 *  r4：p_runtsk（タスク切換え後）
+	 */
+#ifdef USE_ARM_FPU
+	ldr		r2, [r4,#TCB_p_tinib]	/* p_runtsk->p_tinib → r2 */
+	ldr		r1, [r2,#TINIB_tskatr]	/* p_runtsk->p_tinib->tskatr → r1 */
+	tst		r1, #TA_FPU
+	vmrs	r0, fpexc
+	biceq	r0, r0, #FPEXC_ENABLE
+	orrne	r0, r0, #FPEXC_ENABLE
+	vmsr	fpexc, r0				/* FPEXCを設定 */
+	beq		1f						/* TA_FPU属性でない場合は分岐 */
+	pop		{r1,r2}					/* FPSCRの復帰 */
+	vmsr	fpscr, r1
+	vpop	{d0-d15}				/* 全FPUレジスタの復帰 */
+#ifdef USE_ARM_FPU_D32
+	vpop	{d16-d31}
+#endif /* USE_ARM_FPU_D32 */
+1:
+#endif /* USE_ARM_FPU */
+	pop		{r6-r11}				/* 残りのレジスタの復帰 */
 
 ALABEL(exc_handler_4)
@@ -1031,10 +1192,10 @@
 
 #if __TARGET_ARCH_ARM < 6
-	ldmfd	sp!, {r0}				/* 戻り先のcpsrをspsrに設定 */
+	pop		{r0}					/* 戻り先のcpsrをspsrに設定 */
 	msr		spsr_cxsf, r0
 	ldmfd	sp!, {r0-r5,r12,lr,pc}^	/* コンテキストの復帰 */
 									/* ^付きなので，spsr → cpsr */
 #else /* __TARGET_ARCH_ARM < 6 */
-	ldmfd	sp!, {r0-r5,r12,lr}
+	pop		{r0-r5,r12,lr}			/* スクラッチレジスタ＋αの復帰 */
 	rfefd	sp!
 #endif /* __TARGET_ARCH_ARM < 6 */
@@ -1061,4 +1222,14 @@
 	bne		nk_exc_handler_2		/*		 	ならnk_exc_handler_2に分岐 */
 
+#ifdef USE_ARM_FPU
+	/*
+	 *  FPUをディスエーブルする．
+	 */
+	vmrs	r0, fpexc
+	str		r0, [sp]				/* FPEXCを保存（r0の場所）*/
+	bic		r0, r0, #FPEXC_ENABLE
+	vmsr	fpexc, r0				/* FPEXCを設定 */
+#endif /* USE_ARM_FPU */
+	
 	/*
 	 *  非タスクコンテキスト用のスタックに切り換える．
@@ -1068,5 +1239,5 @@
 	ldr		sp, [r2]
 	push	{r0,r3}					/* 切換え前のスタックポインタを保存 */
-									/* r0はスペース確保のため */
+									/* r0はアラインメントのため */
 ALABEL(nk_exc_handler_2)
 	/*
@@ -1101,6 +1272,14 @@
 	pop		{r0,r3}
 	mov		sp, r3
+
+#ifdef USE_ARM_FPU
+	/*
+	 *  FPUを元に戻す．
+	 */
+	ldr		r0, [sp]				/* FPEXCを復帰 */
+	vmsr	fpexc, r0
+#endif /* USE_ARM_FPU */
 	b		exc_handler_5
-
+	
 /*
  *  ステータスレジスタの操作関数
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/cfg/pass1.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/cfg/pass1.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/cfg/pass1.rb	(revision 374)
@@ -727,5 +727,5 @@
   #
   def self.OutLineNumber(cfgInfo)
-    @cfg1Out.add("#line #{cfgInfo[:_LINE_]} \"#{cfgInfo[:_FILE_]}\"")
+    @cfg1Out.add("#line #{cfgInfo[:_LINE_]} \"#{cfgInfo[:_FILE_].gsub('\\', '/')}\"")
   end
 
@@ -734,5 +734,5 @@
   #
   def self.OutClassLineNumber(cfgInfo)
-    @cfg1Out.add("#line #{cfgInfo[:CLASS_LINE_]} \"#{cfgInfo[:CLASS_FILE_]}\"")
+    @cfg1Out.add("#line #{cfgInfo[:CLASS_LINE_]} \"#{cfgInfo[:CLASS_FILE_].gsub('\\', '/')}\"")
   end
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/gdic/adafruit_ssd1306/Makefile.config
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/gdic/adafruit_ssd1306/Makefile.config	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/gdic/adafruit_ssd1306/Makefile.config	(revision 374)
@@ -41,5 +41,5 @@
  
 #
-#  Makefile のプロセッサ依存 (adafruit st7735:LCD用)
+#  Makefile のプロセッサ依存 (adafruit ssd1306:OLED用)
 #
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/library/vasyslog.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/library/vasyslog.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/library/vasyslog.c	(revision 374)
@@ -129,10 +129,3 @@
 }
 
-void
-mbed_error_vfprintf(const char * format, va_list arg)
-{
-	vsyslog(LOG_ERROR, format, arg);
-	ext_ker();
-}
-
 #endif /* TOPPERS_OMIT_SYSLOG */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/Makefile.mbed
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/Makefile.mbed	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/Makefile.mbed	(revision 374)
@@ -16,11 +16,17 @@
 	-I$(MBEDDIR)\
 	-I$(MBEDDIR)/cmsis\
+	-I$(MBEDDIR)/cmsis/TARGET_CORTEX_A\
 	-I$(MBEDDIR)/hal\
 	-I$(MBEDDIR)/platform\
 	-I$(MBEDDIR)/targets/TARGET_RENESAS\
-	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZ_A1H/device\
-	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc\
-	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines\
-	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZ_A1H
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX\
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H\
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H\
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device\
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc\
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks\
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines\
+	-I$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/common\
+	-I$(MBEDDIR)/rtos/TARGET_CORTEX
 COPTS := $(COPTS)\
   -mthumb\
@@ -40,26 +46,55 @@
   -mno-unaligned-access
 CDEFS := $(CDEFS)\
-	-D__FPU_PRESENT\
-	-D__CORTEX_A9\
-	-DDEVICE_ANALOGIN\
-	-DDEVICE_CAN\
-	-DDEVICE_ERROR_PATTERN\
-	-DDEVICE_ETHERNET\
-	-DDEVICE_I2C\
-	-DDEVICE_I2CSLAVE\
-	-DDEVICE_I2C_ASYNCH\
-	-DDEVICE_INTERRUPTIN\
-	-DDEVICE_PORTIN\
-	-DDEVICE_PORTINOUT\
-	-DDEVICE_PORTOUT\
-	-DDEVICE_PWMOUT\
-	-DDEVICE_RTC\
-	-DDEVICE_SERIAL\
-	-DDEVICE_SERIAL_ASYNCH\
-	-DDEVICE_SERIAL_FC\
-	-DDEVICE_SPI\
-	-DDEVICE_SPISLAVE\
-	-DDEVICE_SPI_ASYNCH
-	#-DDEVICE_STDIO_MESSAGES
+	-DARM_MATH_CA9 \
+	-DDEVICE_ANALOGIN=1 \
+	-DDEVICE_CAN=1 \
+	-DDEVICE_EMAC=1 \
+	-DDEVICE_ETHERNET=1 \
+	-DDEVICE_FLASH=1 \
+	-DDEVICE_I2C=1 \
+	-DDEVICE_I2CSLAVE=1 \
+	-DDEVICE_I2C_ASYNCH=1 \
+	-DDEVICE_INTERRUPTIN=1 \
+	-DDEVICE_LPTICKER=1 \
+	-DDEVICE_PORTIN=1 \
+	-DDEVICE_PORTINOUT=1 \
+	-DDEVICE_PORTOUT=1 \
+	-DDEVICE_PWMOUT=1 \
+	-DDEVICE_RTC=1 \
+	-DDEVICE_SEMIHOST=1 \
+	-DDEVICE_SERIAL=1 \
+	-DDEVICE_SERIAL_ASYNCH=1 \
+	-DDEVICE_SERIAL_FC=1 \
+	-DDEVICE_SLEEP=1 \
+	-DDEVICE_SPI=1 \
+	-DDEVICE_SPISLAVE=1 \
+	-DDEVICE_SPI_ASYNCH=1 \
+	-DDEVICE_STDIO_MESSAGES=1 \
+	-DDEVICE_USTICKER=1 \
+	-DMBED_BUILD_TIMESTAMP=1550103323.92 \
+	-DTARGET_A9 \
+	-DTARGET_CORTEX \
+	-DTARGET_CORTEX_A \
+	-DTARGET_FF_ARDUINO \
+	-DTARGET_LIKE_CORTEX_A9 \
+	-DTARGET_LIKE_MBED \
+	-DTARGET_MBRZA1H \
+	-DTARGET_RELEASE \
+	-DTARGET_RENESAS \
+	-DTARGET_RZA1H \
+	-DTARGET_RZ_A1H \
+	-DTARGET_RZ_A1XX \
+	-DTARGET_RZ_A1_EMAC \
+	-DTOOLCHAIN_GCC \
+	-DTOOLCHAIN_GCC_ARM \
+	-DTOOLCHAIN_object \
+	-D__CMSIS_RTOS \
+	-D__CORTEX_A9 \
+	-D__EVAL \
+	-D__FPU_PRESENT=1 \
+	-D__MBED_CMSIS_RTOS_CA9 \
+	-D__MBED__=1 \
+	-DIRQ_GIC_LINE_COUNT=587 \
+	#-DDEVICE_STDIO_MESSAGES=1
 
 #
@@ -67,21 +102,29 @@
 #
 SYSSVC_DIRS := $(SYSSVC_DIRS)\
+	$(MBEDDIR)\
 	$(MBEDDIR)/hal\
 	$(MBEDDIR)/platform\
-	$(MBEDDIR)/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A\
-	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZ_A1H\
-	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZ_A1H/device\
-	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM
-SYSSVC_ASMOBJS := $(SYSSVC_ASMOBJS)\
-	cache.o
+	$(MBEDDIR)/cmsis/TARGET_CORTEX_A\
+	$(MBEDDIR)/targets/TARGET_RENESAS\
+	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX\
+	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H\
+	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H\
+	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device\
+	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM\
+	$(MBEDDIR)/targets/TARGET_RENESAS/TARGET_RZA1XX/common
+SYSSVC_ASMOBJS := $(SYSSVC_ASMOBJS)
 START_OBJS = startup_RZ1AH.o
 SYSSVC_COBJS := $(SYSSVC_COBJS)\
-	mbed_assert.o mbed_board.o mbed_gpio.o mbed_lp_ticker_api.o mbed_interface.o\
-	mbed_pinmap_common.o mbed_rtc_time.o mbed_semihost_api.o mbed_ticker_api.o mbed_us_ticker_api.o\
-	mbed_critical.o RZ_A1_Init.o cmsis_nvic.o gic.o mbed_sf_boot.o mmu_Renesas_RZ_A1.o\
-	nvic_wrapper.o pl310.o rza_io_regrw.o system_MBRZA1H.o\
-	analogin_api.o can_api.o ethernet_api.o gpio_api.o gpio_irq_api.o i2c_api.o\
-	pinmap.o port_api.o pwmout_api.o rtc_api.o serial_api.o spi_api.o
-	#mbed_wait_api_no_rtos.o us_ticker.o
-CFG_DMY := cfg_dmy.o mmu_Renesas_RZ_A1.o mbed_sf_boot.o RZ_A1_Init.o system_MBRZA1H.o cache.o pl310.o gic.o
+	mbed_critical_section_api.o mbed_flash_api.o mbed_gpio.o mbed_lp_ticker_api.o\
+	mbed_lp_ticker_wrapper.o mbed_pinmap_common.o mbed_sleep_manager.o mbed_mktime.o\
+	mbed_ticker_api.o mbed_us_ticker_api.o mbed_assert.o mbed_board.o\
+	mbed_critical.o mbed_error.o mbed_error_hist.o mbed_interface.o\
+	mbed_rtc_time.o mbed_semihost_api.o mbed_stats.o\
+	PeripheralPins.o RZ_A1_Init.o mbed_sf_boot.o mmu_RZ_A1H.o\
+	system_RZ_A1H.o trng_api_esp32.o analogin_api.o can_api.o cmsis_nvic.o\
+	irq_ctrl_gic.o nvic_wrapper.o rza_io_regrw.o ethernet_api.o flash_api.o\
+	gpio_api.o gpio_irq_api.o i2c_api.o lp_ticker.o mtu2.o pinmap.o port_api.o\
+	pwmout_api.o rtc_api.o serial_api.o sleep.o spi_api.o trng_api.o us_ticker.o
+	#mbed_wait_api_no_rtos.o
+CFG_DMY := cfg_dmy.o mmu_RZ_A1H.o mbed_sf_boot.o RZ_A1_Init.o system_RZ_A1H.o irq_ctrl_gic.o
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/RTE_Components.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/RTE_Components.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/RTE_Components.h	(revision 374)
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define CMSIS_device_header <cmsis.h>
+
+#if defined(MBED_CONF_RTOS_PRESENT)
+#include "mbed_rtx_conf.h"
+#endif
+#include "mbed_cmsis_conf.h"
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_compiler.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_compiler.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_compiler.h	(revision 374)
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include "cmsis_iccarm.h"
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __attribute__((aligned(x)))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __attribute__((packed))
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __packed__
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                     _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
+    #define CMSIS_DEPRECATED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __weak
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  @packed
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_cp15.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_cp15.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_cp15.h	(revision 374)
@@ -0,0 +1,514 @@
+/**************************************************************************//**
+ * @file     cmsis_cp15.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.1
+ * @date     07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
+/** \brief  Get ACTLR
+    \return               Auxiliary Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return(result);
+}
+
+/** \brief  Set ACTLR
+    \param [in]    actlr  Auxiliary Control value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
+{
+  __set_CP(15, 0, actlr, 1, 0, 1);
+}
+
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 2);
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Access Control value to set
+ */
+__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
+{
+  __set_CP(15, 0, cpacr, 1, 0, 2);
+}
+
+/** \brief  Get DFSR
+    \return               Data Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 0);
+  return result;
+}
+
+/** \brief  Set DFSR
+    \param [in]    dfsr  Data Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
+{
+  __set_CP(15, 0, dfsr, 5, 0, 0);
+}
+
+/** \brief  Get IFSR
+    \return               Instruction Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 1);
+  return result;
+}
+
+/** \brief  Set IFSR
+    \param [in]    ifsr  Instruction Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
+{
+  __set_CP(15, 0, ifsr, 5, 0, 1);
+}
+
+/** \brief  Get ISR
+    \return               Interrupt Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ISR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 1, 0);
+  return result;
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 4, result, 15, 0, 0);
+  return result;
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 2, 0, 0);
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
+{
+  __set_CP(15, 0, ttbr0, 2, 0, 0);
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 3, 0, 0);
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
+{
+  __set_CP(15, 0, dacr, 3, 0, 0);
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
+{
+  __set_CP(15, 0, sctlr, 1, 0, 0);
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 0);
+  return result;
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
+{
+  __set_CP(15, 0, actrl, 1, 0, 1);
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 0, 0, 5);
+  return result;
+}
+
+/** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 0);
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
+{
+  __set_CP(15, 0, vbar, 12, 0, 0);
+}
+
+/** \brief  Get MVBAR
+
+    This function returns the value of the Monitor Vector Base Address Register.
+
+    \return               Monitor Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 1);
+  return result;
+}
+
+/** \brief  Set MVBAR
+
+    This function assigns the given value to the Monitor Vector Base Address Register.
+
+    \param [in]    mvbar  Monitor Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
+{
+  __set_CP(15, 0, mvbar, 12, 0, 1);
+}
+
+#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
+    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+    defined(DOXYGEN)
+
+/** \brief  Set CNTFRQ
+
+  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 0, 0);
+}
+
+/** \brief  Get CNTFRQ
+
+    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+    \return               CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 0 , 0);
+  return result;
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 0);
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 0);
+  return result;
+}
+
+/** \brief  Get CNTPCT
+
+    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
+
+    \return               CNTPCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
+{
+  uint64_t result;
+  __get_CP64(15, 0, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CVAL
+
+  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+  \param [in]    value  CNTP_CVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
+{
+  __set_CP64(15, 2, value, 14);
+}
+
+/** \brief  Get CNTP_CVAL
+
+    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+    \return               CNTP_CVAL Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
+{
+  uint64_t result;
+  __get_CP64(15, 2, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 1);
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 1);
+  return result;
+}
+
+#endif
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 8, 7, 0);
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 6);
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 0);
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 14, 1);
+}
+
+/** \brief  Set CSSELR
+ */
+__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+  __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief  Get CSSELR
+    \return CSSELR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 2, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Set CCSIDR
+    \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
+ */
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
+{
+  __set_CSSELR(value);
+}
+
+/** \brief  Get CCSIDR
+    \return CCSIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Get CLIDR
+    \return CLIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 1);
+  return result;
+}
+
+/** \brief  Set DCISW
+ */
+__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 6, 2);
+}
+
+/** \brief  Set DCCSW
+ */
+__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 10, 2);
+}
+
+/** \brief  Set DCCISW
+ */
+__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 14, 2);
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_gcc.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_gcc.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/cmsis_gcc.h	(revision 374)
@@ -0,0 +1,679 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   CMSIS_DEPRECATED
+ #define  CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+/**
+  \brief   Send Event
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE  uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U) {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             (uint8_t)__builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE  void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE  void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return Floating Point Status/Control register value
+*/
+__STATIC_FORCEINLINE  uint32_t __get_FPSCR(void)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_get_fpscr) 
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    return __builtin_arm_get_fpscr();
+  #else
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+  #endif
+  #else
+    return(0U);
+  #endif
+}
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in] fpscr  Floating Point Status/Control value to set
+*/
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_set_fpscr)
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    __builtin_arm_set_fpscr(fpscr);
+  #else
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+  #endif
+  #else
+    (void)fpscr;
+  #endif
+}
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+    return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr = __get_CPSR();
+  uint32_t result;
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     %0, sp   " : "=r"(result) : : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr = __get_CPSR();
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     sp, %0   " : : "r" (topOfProcStack) : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/core_ca.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/core_ca.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/core_ca.h	(revision 374)
@@ -0,0 +1,2614 @@
+/**************************************************************************//**
+ * @file     core_ca.h
+ * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
+ * @version  V1.0.1
+ * @date     07. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA_H_GENERIC
+#define __CORE_CA_H_GENERIC
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+
+/*  CMSIS CA definitions */
+#define __CA_CMSIS_VERSION_MAIN  (1U)                                      /*!< \brief [31:16] CMSIS-Core(A) main version   */
+#define __CA_CMSIS_VERSION_SUB   (1U)                                      /*!< \brief [15:0]  CMSIS-Core(A) sub version    */
+#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CA_CMSIS_VERSION_SUB          )       /*!< \brief CMSIS-Core(A) version number         */
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA_H_DEPENDANT
+#define __CORE_CA_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ /* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CA_REV
+    #define __CA_REV              0x0000U
+    #warning "__CA_REV not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+    
+  #ifndef __GIC_PRESENT
+    #define __GIC_PRESENT             1U
+    #warning "__GIC_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __TIM_PRESENT
+    #define __TIM_PRESENT             1U
+    #warning "__TIM_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __L2C_PRESENT
+    #define __L2C_PRESENT             0U
+    #warning "__L2C_PRESENT not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< \brief Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< \brief Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< \brief Defines 'write only' permissions */
+#define     __IO    volatile             /*!< \brief Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*!< \brief Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*!< \brief Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
+#define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
+
+ /*******************************************************************************
+  *                 Register Abstraction
+   Core Register contain:
+   - CPSR
+   - CP15 Registers
+   - L2C-310 Cache Controller
+   - Generic Interrupt Controller Distributor
+   - Generic Interrupt Controller Interface
+  ******************************************************************************/
+
+/* Core Register CPSR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:5;                        /*!< \brief bit:  0.. 4  Mode field */
+    uint32_t T:1;                        /*!< \brief bit:      5  Thumb execution state bit */
+    uint32_t F:1;                        /*!< \brief bit:      6  FIQ mask bit */
+    uint32_t I:1;                        /*!< \brief bit:      7  IRQ mask bit */
+    uint32_t A:1;                        /*!< \brief bit:      8  Asynchronous abort mask bit */
+    uint32_t E:1;                        /*!< \brief bit:      9  Endianness execution state bit */
+    uint32_t IT1:6;                      /*!< \brief bit: 10..15  If-Then execution state bits 2-7 */
+    uint32_t GE:4;                       /*!< \brief bit: 16..19  Greater than or Equal flags */
+    RESERVED(0:4, uint32_t)              
+    uint32_t J:1;                        /*!< \brief bit:     24  Jazelle bit */
+    uint32_t IT0:2;                      /*!< \brief bit: 25..26  If-Then execution state bits 0-1 */
+    uint32_t Q:1;                        /*!< \brief bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< \brief bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< \brief bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< \brief bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< \brief bit:     31  Negative condition code flag */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPSR_Type;
+
+
+
+/* CPSR Register Definitions */
+#define CPSR_N_Pos                       31U                                    /*!< \brief CPSR: N Position */
+#define CPSR_N_Msk                       (1UL << CPSR_N_Pos)                    /*!< \brief CPSR: N Mask */
+
+#define CPSR_Z_Pos                       30U                                    /*!< \brief CPSR: Z Position */
+#define CPSR_Z_Msk                       (1UL << CPSR_Z_Pos)                    /*!< \brief CPSR: Z Mask */
+
+#define CPSR_C_Pos                       29U                                    /*!< \brief CPSR: C Position */
+#define CPSR_C_Msk                       (1UL << CPSR_C_Pos)                    /*!< \brief CPSR: C Mask */
+
+#define CPSR_V_Pos                       28U                                    /*!< \brief CPSR: V Position */
+#define CPSR_V_Msk                       (1UL << CPSR_V_Pos)                    /*!< \brief CPSR: V Mask */
+
+#define CPSR_Q_Pos                       27U                                    /*!< \brief CPSR: Q Position */
+#define CPSR_Q_Msk                       (1UL << CPSR_Q_Pos)                    /*!< \brief CPSR: Q Mask */
+
+#define CPSR_IT0_Pos                     25U                                    /*!< \brief CPSR: IT0 Position */
+#define CPSR_IT0_Msk                     (3UL << CPSR_IT0_Pos)                  /*!< \brief CPSR: IT0 Mask */
+
+#define CPSR_J_Pos                       24U                                    /*!< \brief CPSR: J Position */
+#define CPSR_J_Msk                       (1UL << CPSR_J_Pos)                    /*!< \brief CPSR: J Mask */
+
+#define CPSR_GE_Pos                      16U                                    /*!< \brief CPSR: GE Position */
+#define CPSR_GE_Msk                      (0xFUL << CPSR_GE_Pos)                 /*!< \brief CPSR: GE Mask */
+
+#define CPSR_IT1_Pos                     10U                                    /*!< \brief CPSR: IT1 Position */
+#define CPSR_IT1_Msk                     (0x3FUL << CPSR_IT1_Pos)               /*!< \brief CPSR: IT1 Mask */
+
+#define CPSR_E_Pos                       9U                                     /*!< \brief CPSR: E Position */
+#define CPSR_E_Msk                       (1UL << CPSR_E_Pos)                    /*!< \brief CPSR: E Mask */
+
+#define CPSR_A_Pos                       8U                                     /*!< \brief CPSR: A Position */
+#define CPSR_A_Msk                       (1UL << CPSR_A_Pos)                    /*!< \brief CPSR: A Mask */
+
+#define CPSR_I_Pos                       7U                                     /*!< \brief CPSR: I Position */
+#define CPSR_I_Msk                       (1UL << CPSR_I_Pos)                    /*!< \brief CPSR: I Mask */
+
+#define CPSR_F_Pos                       6U                                     /*!< \brief CPSR: F Position */
+#define CPSR_F_Msk                       (1UL << CPSR_F_Pos)                    /*!< \brief CPSR: F Mask */
+
+#define CPSR_T_Pos                       5U                                     /*!< \brief CPSR: T Position */
+#define CPSR_T_Msk                       (1UL << CPSR_T_Pos)                    /*!< \brief CPSR: T Mask */
+
+#define CPSR_M_Pos                       0U                                     /*!< \brief CPSR: M Position */
+#define CPSR_M_Msk                       (0x1FUL << CPSR_M_Pos)                 /*!< \brief CPSR: M Mask */
+
+#define CPSR_M_USR                       0x10U                                  /*!< \brief CPSR: M User mode (PL0) */
+#define CPSR_M_FIQ                       0x11U                                  /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
+#define CPSR_M_IRQ                       0x12U                                  /*!< \brief CPSR: M Interrupt mode (PL1) */
+#define CPSR_M_SVC                       0x13U                                  /*!< \brief CPSR: M Supervisor mode (PL1) */
+#define CPSR_M_MON                       0x16U                                  /*!< \brief CPSR: M Monitor mode (PL1) */
+#define CPSR_M_ABT                       0x17U                                  /*!< \brief CPSR: M Abort mode (PL1) */
+#define CPSR_M_HYP                       0x1AU                                  /*!< \brief CPSR: M Hypervisor mode (PL2) */
+#define CPSR_M_UND                       0x1BU                                  /*!< \brief CPSR: M Undefined mode (PL1) */
+#define CPSR_M_SYS                       0x1FU                                  /*!< \brief CPSR: M System mode (PL1) */
+
+/* CP15 Register SCTLR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:1;                        /*!< \brief bit:     0  MMU enable */
+    uint32_t A:1;                        /*!< \brief bit:     1  Alignment check enable */
+    uint32_t C:1;                        /*!< \brief bit:     2  Cache enable */
+    RESERVED(0:2, uint32_t)              
+    uint32_t CP15BEN:1;                  /*!< \brief bit:     5  CP15 barrier enable */
+    RESERVED(1:1, uint32_t)              
+    uint32_t B:1;                        /*!< \brief bit:     7  Endianness model */
+    RESERVED(2:2, uint32_t)              
+    uint32_t SW:1;                       /*!< \brief bit:    10  SWP and SWPB enable */
+    uint32_t Z:1;                        /*!< \brief bit:    11  Branch prediction enable */
+    uint32_t I:1;                        /*!< \brief bit:    12  Instruction cache enable */
+    uint32_t V:1;                        /*!< \brief bit:    13  Vectors bit */
+    uint32_t RR:1;                       /*!< \brief bit:    14  Round Robin select */
+    RESERVED(3:2, uint32_t)              
+    uint32_t HA:1;                       /*!< \brief bit:    17  Hardware Access flag enable */
+    RESERVED(4:1, uint32_t)              
+    uint32_t WXN:1;                      /*!< \brief bit:    19  Write permission implies XN */
+    uint32_t UWXN:1;                     /*!< \brief bit:    20  Unprivileged write permission implies PL1 XN */
+    uint32_t FI:1;                       /*!< \brief bit:    21  Fast interrupts configuration enable */
+    uint32_t U:1;                        /*!< \brief bit:    22  Alignment model */
+    RESERVED(5:1, uint32_t)              
+    uint32_t VE:1;                       /*!< \brief bit:    24  Interrupt Vectors Enable */
+    uint32_t EE:1;                       /*!< \brief bit:    25  Exception Endianness */
+    RESERVED(6:1, uint32_t)              
+    uint32_t NMFI:1;                     /*!< \brief bit:    27  Non-maskable FIQ (NMFI) support */
+    uint32_t TRE:1;                      /*!< \brief bit:    28  TEX remap enable. */
+    uint32_t AFE:1;                      /*!< \brief bit:    29  Access flag enable */
+    uint32_t TE:1;                       /*!< \brief bit:    30  Thumb Exception enable */
+    RESERVED(7:1, uint32_t)              
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} SCTLR_Type;
+
+#define SCTLR_TE_Pos                     30U                                    /*!< \brief SCTLR: TE Position */
+#define SCTLR_TE_Msk                     (1UL << SCTLR_TE_Pos)                  /*!< \brief SCTLR: TE Mask */
+
+#define SCTLR_AFE_Pos                    29U                                    /*!< \brief SCTLR: AFE Position */
+#define SCTLR_AFE_Msk                    (1UL << SCTLR_AFE_Pos)                 /*!< \brief SCTLR: AFE Mask */
+
+#define SCTLR_TRE_Pos                    28U                                    /*!< \brief SCTLR: TRE Position */
+#define SCTLR_TRE_Msk                    (1UL << SCTLR_TRE_Pos)                 /*!< \brief SCTLR: TRE Mask */
+
+#define SCTLR_NMFI_Pos                   27U                                    /*!< \brief SCTLR: NMFI Position */
+#define SCTLR_NMFI_Msk                   (1UL << SCTLR_NMFI_Pos)                /*!< \brief SCTLR: NMFI Mask */
+
+#define SCTLR_EE_Pos                     25U                                    /*!< \brief SCTLR: EE Position */
+#define SCTLR_EE_Msk                     (1UL << SCTLR_EE_Pos)                  /*!< \brief SCTLR: EE Mask */
+
+#define SCTLR_VE_Pos                     24U                                    /*!< \brief SCTLR: VE Position */
+#define SCTLR_VE_Msk                     (1UL << SCTLR_VE_Pos)                  /*!< \brief SCTLR: VE Mask */
+
+#define SCTLR_U_Pos                      22U                                    /*!< \brief SCTLR: U Position */
+#define SCTLR_U_Msk                      (1UL << SCTLR_U_Pos)                   /*!< \brief SCTLR: U Mask */
+
+#define SCTLR_FI_Pos                     21U                                    /*!< \brief SCTLR: FI Position */
+#define SCTLR_FI_Msk                     (1UL << SCTLR_FI_Pos)                  /*!< \brief SCTLR: FI Mask */
+
+#define SCTLR_UWXN_Pos                   20U                                    /*!< \brief SCTLR: UWXN Position */
+#define SCTLR_UWXN_Msk                   (1UL << SCTLR_UWXN_Pos)                /*!< \brief SCTLR: UWXN Mask */
+
+#define SCTLR_WXN_Pos                    19U                                    /*!< \brief SCTLR: WXN Position */
+#define SCTLR_WXN_Msk                    (1UL << SCTLR_WXN_Pos)                 /*!< \brief SCTLR: WXN Mask */
+
+#define SCTLR_HA_Pos                     17U                                    /*!< \brief SCTLR: HA Position */
+#define SCTLR_HA_Msk                     (1UL << SCTLR_HA_Pos)                  /*!< \brief SCTLR: HA Mask */
+
+#define SCTLR_RR_Pos                     14U                                    /*!< \brief SCTLR: RR Position */
+#define SCTLR_RR_Msk                     (1UL << SCTLR_RR_Pos)                  /*!< \brief SCTLR: RR Mask */
+
+#define SCTLR_V_Pos                      13U                                    /*!< \brief SCTLR: V Position */
+#define SCTLR_V_Msk                      (1UL << SCTLR_V_Pos)                   /*!< \brief SCTLR: V Mask */
+
+#define SCTLR_I_Pos                      12U                                    /*!< \brief SCTLR: I Position */
+#define SCTLR_I_Msk                      (1UL << SCTLR_I_Pos)                   /*!< \brief SCTLR: I Mask */
+
+#define SCTLR_Z_Pos                      11U                                    /*!< \brief SCTLR: Z Position */
+#define SCTLR_Z_Msk                      (1UL << SCTLR_Z_Pos)                   /*!< \brief SCTLR: Z Mask */
+
+#define SCTLR_SW_Pos                     10U                                    /*!< \brief SCTLR: SW Position */
+#define SCTLR_SW_Msk                     (1UL << SCTLR_SW_Pos)                  /*!< \brief SCTLR: SW Mask */
+
+#define SCTLR_B_Pos                      7U                                     /*!< \brief SCTLR: B Position */
+#define SCTLR_B_Msk                      (1UL << SCTLR_B_Pos)                   /*!< \brief SCTLR: B Mask */
+
+#define SCTLR_CP15BEN_Pos                5U                                     /*!< \brief SCTLR: CP15BEN Position */
+#define SCTLR_CP15BEN_Msk                (1UL << SCTLR_CP15BEN_Pos)             /*!< \brief SCTLR: CP15BEN Mask */
+
+#define SCTLR_C_Pos                      2U                                     /*!< \brief SCTLR: C Position */
+#define SCTLR_C_Msk                      (1UL << SCTLR_C_Pos)                   /*!< \brief SCTLR: C Mask */
+
+#define SCTLR_A_Pos                      1U                                     /*!< \brief SCTLR: A Position */
+#define SCTLR_A_Msk                      (1UL << SCTLR_A_Pos)                   /*!< \brief SCTLR: A Mask */
+
+#define SCTLR_M_Pos                      0U                                     /*!< \brief SCTLR: M Position */
+#define SCTLR_M_Msk                      (1UL << SCTLR_M_Pos)                   /*!< \brief SCTLR: M Mask */
+
+/* CP15 Register ACTLR */
+typedef union
+{
+#if __CORTEX_A == 5 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A5 */
+  struct
+  {
+    uint32_t FW:1;                      /*!< \brief bit:      0  Cache and TLB maintenance broadcast */
+    RESERVED(0:5, uint32_t)              
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    uint32_t EXCL:1;                     /*!< \brief bit:     7  Exclusive L1/L2 cache control */
+    RESERVED(1:2, uint32_t)
+    uint32_t DODMBS:1;                   /*!< \brief bit:    10  Disable optimized data memory barrier behavior */
+    uint32_t DWBST:1;                    /*!< \brief bit:    11  AXI data write bursts to Normal memory */
+    uint32_t RADIS:1;                    /*!< \brief bit:    12  L1 Data Cache read-allocate mode disable */
+    uint32_t L1PCTL:2;                   /*!< \brief bit:13..14  L1 Data prefetch control */    
+    uint32_t BP:2;                       /*!< \brief bit:16..15  Branch prediction policy */
+    uint32_t RSDIS:1;                    /*!< \brief bit:    17  Disable return stack operation */
+    uint32_t BTDIS:1;                    /*!< \brief bit:    18  Disable indirect Branch Target Address Cache (BTAC) */
+    RESERVED(3:9, uint32_t)             
+    uint32_t DBDI:1;                     /*!< \brief bit:    28  Disable branch dual issue */
+    RESERVED(7:3, uint32_t)              
+ } b;
+#endif  
+#if __CORTEX_A == 7 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A7 */
+  struct
+  {
+    RESERVED(0:6, uint32_t)              
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    RESERVED(1:3, uint32_t)              
+    uint32_t DODMBS:1;                   /*!< \brief bit:    10  Disable optimized data memory barrier behavior */
+    uint32_t L2RADIS:1;                  /*!< \brief bit:    11  L2 Data Cache read-allocate mode disable */
+    uint32_t L1RADIS:1;                  /*!< \brief bit:    12  L1 Data Cache read-allocate mode disable */
+    uint32_t L1PCTL:2;                   /*!< \brief bit:13..14  L1 Data prefetch control */
+    uint32_t DDVM:1;                     /*!< \brief bit:    15  Disable Distributed Virtual Memory (DVM) transactions */
+    RESERVED(3:12, uint32_t)             
+    uint32_t DDI:1;                      /*!< \brief bit:    28  Disable dual issue */
+    RESERVED(7:3, uint32_t)              
+  } b;
+#endif  
+#if __CORTEX_A == 9 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A9 */
+  struct
+  {
+    uint32_t FW:1;                       /*!< \brief bit:     0  Cache and TLB maintenance broadcast */
+    RESERVED(0:1, uint32_t)
+    uint32_t L1PE:1;                     /*!< \brief bit:     2  Dside prefetch */
+    uint32_t WFLZM:1;                    /*!< \brief bit:     3  Cache and TLB maintenance broadcast */
+    RESERVED(1:2, uint32_t)
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    uint32_t EXCL:1;                     /*!< \brief bit:     7  Exclusive L1/L2 cache control */
+    uint32_t AOW:1;                      /*!< \brief bit:     8  Enable allocation in one cache way only */
+    uint32_t PARITY:1;                   /*!< \brief bit:     9  Support for parity checking, if implemented */
+    RESERVED(7:22, uint32_t)              
+  } b;
+#endif  
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} ACTLR_Type;
+
+#define ACTLR_DDI_Pos                    28U                                     /*!< \brief ACTLR: DDI Position */
+#define ACTLR_DDI_Msk                    (1UL << ACTLR_DDI_Pos)                  /*!< \brief ACTLR: DDI Mask */
+
+#define ACTLR_DBDI_Pos                   28U                                     /*!< \brief ACTLR: DBDI Position */
+#define ACTLR_DBDI_Msk                   (1UL << ACTLR_DBDI_Pos)                 /*!< \brief ACTLR: DBDI Mask */
+
+#define ACTLR_BTDIS_Pos                  18U                                     /*!< \brief ACTLR: BTDIS Position */
+#define ACTLR_BTDIS_Msk                  (1UL << ACTLR_BTDIS_Pos)                /*!< \brief ACTLR: BTDIS Mask */
+
+#define ACTLR_RSDIS_Pos                  17U                                     /*!< \brief ACTLR: RSDIS Position */
+#define ACTLR_RSDIS_Msk                  (1UL << ACTLR_RSDIS_Pos)                /*!< \brief ACTLR: RSDIS Mask */
+
+#define ACTLR_BP_Pos                     15U                                     /*!< \brief ACTLR: BP Position */
+#define ACTLR_BP_Msk                     (3UL << ACTLR_BP_Pos)                   /*!< \brief ACTLR: BP Mask */
+
+#define ACTLR_DDVM_Pos                   15U                                     /*!< \brief ACTLR: DDVM Position */
+#define ACTLR_DDVM_Msk                   (1UL << ACTLR_DDVM_Pos)                 /*!< \brief ACTLR: DDVM Mask */
+
+#define ACTLR_L1PCTL_Pos                 13U                                     /*!< \brief ACTLR: L1PCTL Position */
+#define ACTLR_L1PCTL_Msk                 (3UL << ACTLR_L1PCTL_Pos)               /*!< \brief ACTLR: L1PCTL Mask */
+
+#define ACTLR_RADIS_Pos                  12U                                     /*!< \brief ACTLR: RADIS Position */
+#define ACTLR_RADIS_Msk                  (1UL << ACTLR_RADIS_Pos)                /*!< \brief ACTLR: RADIS Mask */
+
+#define ACTLR_L1RADIS_Pos                12U                                     /*!< \brief ACTLR: L1RADIS Position */
+#define ACTLR_L1RADIS_Msk                (1UL << ACTLR_L1RADIS_Pos)              /*!< \brief ACTLR: L1RADIS Mask */
+
+#define ACTLR_DWBST_Pos                  11U                                     /*!< \brief ACTLR: DWBST Position */
+#define ACTLR_DWBST_Msk                  (1UL << ACTLR_DWBST_Pos)                /*!< \brief ACTLR: DWBST Mask */
+
+#define ACTLR_L2RADIS_Pos                11U                                     /*!< \brief ACTLR: L2RADIS Position */
+#define ACTLR_L2RADIS_Msk                (1UL << ACTLR_L2RADIS_Pos)              /*!< \brief ACTLR: L2RADIS Mask */
+
+#define ACTLR_DODMBS_Pos                 10U                                     /*!< \brief ACTLR: DODMBS Position */
+#define ACTLR_DODMBS_Msk                 (1UL << ACTLR_DODMBS_Pos)               /*!< \brief ACTLR: DODMBS Mask */
+
+#define ACTLR_PARITY_Pos                 9U                                      /*!< \brief ACTLR: PARITY Position */
+#define ACTLR_PARITY_Msk                 (1UL << ACTLR_PARITY_Pos)               /*!< \brief ACTLR: PARITY Mask */
+
+#define ACTLR_AOW_Pos                    8U                                      /*!< \brief ACTLR: AOW Position */
+#define ACTLR_AOW_Msk                    (1UL << ACTLR_AOW_Pos)                  /*!< \brief ACTLR: AOW Mask */
+
+#define ACTLR_EXCL_Pos                   7U                                      /*!< \brief ACTLR: EXCL Position */
+#define ACTLR_EXCL_Msk                   (1UL << ACTLR_EXCL_Pos)                 /*!< \brief ACTLR: EXCL Mask */
+
+#define ACTLR_SMP_Pos                    6U                                      /*!< \brief ACTLR: SMP Position */
+#define ACTLR_SMP_Msk                    (1UL << ACTLR_SMP_Pos)                  /*!< \brief ACTLR: SMP Mask */
+
+#define ACTLR_WFLZM_Pos                  3U                                      /*!< \brief ACTLR: WFLZM Position */
+#define ACTLR_WFLZM_Msk                  (1UL << ACTLR_WFLZM_Pos)                /*!< \brief ACTLR: WFLZM Mask */
+
+#define ACTLR_L1PE_Pos                   2U                                      /*!< \brief ACTLR: L1PE Position */
+#define ACTLR_L1PE_Msk                   (1UL << ACTLR_L1PE_Pos)                 /*!< \brief ACTLR: L1PE Mask */
+
+#define ACTLR_FW_Pos                     0U                                      /*!< \brief ACTLR: FW Position */
+#define ACTLR_FW_Msk                     (1UL << ACTLR_FW_Pos)                   /*!< \brief ACTLR: FW Mask */
+
+/* CP15 Register CPACR */
+typedef union
+{
+  struct
+  {
+    uint32_t CP0:2;                      /*!< \brief bit:  0..1  Access rights for coprocessor 0 */
+    uint32_t CP1:2;                      /*!< \brief bit:  2..3  Access rights for coprocessor 1 */
+    uint32_t CP2:2;                      /*!< \brief bit:  4..5  Access rights for coprocessor 2 */
+    uint32_t CP3:2;                      /*!< \brief bit:  6..7  Access rights for coprocessor 3 */
+    uint32_t CP4:2;                      /*!< \brief bit:  8..9  Access rights for coprocessor 4 */
+    uint32_t CP5:2;                      /*!< \brief bit:10..11  Access rights for coprocessor 5 */
+    uint32_t CP6:2;                      /*!< \brief bit:12..13  Access rights for coprocessor 6 */
+    uint32_t CP7:2;                      /*!< \brief bit:14..15  Access rights for coprocessor 7 */
+    uint32_t CP8:2;                      /*!< \brief bit:16..17  Access rights for coprocessor 8 */
+    uint32_t CP9:2;                      /*!< \brief bit:18..19  Access rights for coprocessor 9 */
+    uint32_t CP10:2;                     /*!< \brief bit:20..21  Access rights for coprocessor 10 */
+    uint32_t CP11:2;                     /*!< \brief bit:22..23  Access rights for coprocessor 11 */
+    uint32_t CP12:2;                     /*!< \brief bit:24..25  Access rights for coprocessor 11 */
+    uint32_t CP13:2;                     /*!< \brief bit:26..27  Access rights for coprocessor 11 */
+    uint32_t TRCDIS:1;                   /*!< \brief bit:    28  Disable CP14 access to trace registers */
+    RESERVED(0:1, uint32_t)              
+    uint32_t D32DIS:1;                   /*!< \brief bit:    30  Disable use of registers D16-D31 of the VFP register file */
+    uint32_t ASEDIS:1;                   /*!< \brief bit:    31  Disable Advanced SIMD Functionality */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPACR_Type;
+
+#define CPACR_ASEDIS_Pos                 31U                                    /*!< \brief CPACR: ASEDIS Position */
+#define CPACR_ASEDIS_Msk                 (1UL << CPACR_ASEDIS_Pos)              /*!< \brief CPACR: ASEDIS Mask */
+
+#define CPACR_D32DIS_Pos                 30U                                    /*!< \brief CPACR: D32DIS Position */
+#define CPACR_D32DIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_TRCDIS_Pos                 28U                                    /*!< \brief CPACR: D32DIS Position */
+#define CPACR_TRCDIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_CP_Pos_(n)                 (n*2U)                                 /*!< \brief CPACR: CPn Position */
+#define CPACR_CP_Msk_(n)                 (3UL << CPACR_CP_Pos_(n))              /*!< \brief CPACR: CPn Mask */
+
+#define CPACR_CP_NA                      0U                                     /*!< \brief CPACR CPn field: Access denied. */
+#define CPACR_CP_PL1                     1U                                     /*!< \brief CPACR CPn field: Accessible from PL1 only. */
+#define CPACR_CP_FA                      3U                                     /*!< \brief CPACR CPn field: Full access. */
+
+/* CP15 Register DFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    uint32_t Domain:4;                   /*!< \brief bit: 4.. 7  Fault on which domain */
+    RESERVED(0:1, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
+    RESERVED(1:18, uint32_t)             
+  } s;                                   /*!< \brief Structure used for bit  access in short format */
+  struct
+  {
+    uint32_t STATUS:5;                   /*!< \brief bit: 0.. 5  Fault Status bits */
+    RESERVED(0:3, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    RESERVED(1:1, uint32_t)              
+    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
+    RESERVED(2:18, uint32_t)             
+  } l;                                   /*!< \brief Structure used for bit  access in long format */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} DFSR_Type;
+
+#define DFSR_CM_Pos                      13U                                    /*!< \brief DFSR: CM Position */
+#define DFSR_CM_Msk                      (1UL << DFSR_CM_Pos)                   /*!< \brief DFSR: CM Mask */
+
+#define DFSR_Ext_Pos                     12U                                    /*!< \brief DFSR: Ext Position */
+#define DFSR_Ext_Msk                     (1UL << DFSR_Ext_Pos)                  /*!< \brief DFSR: Ext Mask */
+
+#define DFSR_WnR_Pos                     11U                                    /*!< \brief DFSR: WnR Position */
+#define DFSR_WnR_Msk                     (1UL << DFSR_WnR_Pos)                  /*!< \brief DFSR: WnR Mask */
+
+#define DFSR_FS1_Pos                     10U                                    /*!< \brief DFSR: FS1 Position */
+#define DFSR_FS1_Msk                     (1UL << DFSR_FS1_Pos)                  /*!< \brief DFSR: FS1 Mask */
+
+#define DFSR_LPAE_Pos                    9U                                    /*!< \brief DFSR: LPAE Position */
+#define DFSR_LPAE_Msk                    (1UL << DFSR_LPAE_Pos)                /*!< \brief DFSR: LPAE Mask */
+
+#define DFSR_Domain_Pos                  4U                                     /*!< \brief DFSR: Domain Position */
+#define DFSR_Domain_Msk                  (0xFUL << DFSR_Domain_Pos)             /*!< \brief DFSR: Domain Mask */
+
+#define DFSR_FS0_Pos                     0U                                     /*!< \brief DFSR: FS0 Position */
+#define DFSR_FS0_Msk                     (0xFUL << DFSR_FS0_Pos)                /*!< \brief DFSR: FS0 Mask */
+
+#define DFSR_STATUS_Pos                  0U                                     /*!< \brief DFSR: STATUS Position */
+#define DFSR_STATUS_Msk                  (0x3FUL << DFSR_STATUS_Pos)            /*!< \brief DFSR: STATUS Mask */
+
+/* CP15 Register IFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    RESERVED(0:5, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    RESERVED(1:1, uint32_t)              
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    RESERVED(2:19, uint32_t)             
+  } s;                                   /*!< \brief Structure used for bit access in short format */
+  struct
+  {
+    uint32_t STATUS:6;                   /*!< \brief bit: 0.. 5  Fault Status bits */
+    RESERVED(0:3, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    RESERVED(1:2, uint32_t)              
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    RESERVED(2:19, uint32_t)             
+  } l;                                   /*!< \brief Structure used for bit access in long format */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} IFSR_Type;
+
+#define IFSR_ExT_Pos                     12U                                    /*!< \brief IFSR: ExT Position */
+#define IFSR_ExT_Msk                     (1UL << IFSR_ExT_Pos)                  /*!< \brief IFSR: ExT Mask */
+
+#define IFSR_FS1_Pos                     10U                                    /*!< \brief IFSR: FS1 Position */
+#define IFSR_FS1_Msk                     (1UL << IFSR_FS1_Pos)                  /*!< \brief IFSR: FS1 Mask */
+
+#define IFSR_LPAE_Pos                    9U                                     /*!< \brief IFSR: LPAE Position */
+#define IFSR_LPAE_Msk                    (0x1UL << IFSR_LPAE_Pos)               /*!< \brief IFSR: LPAE Mask */
+
+#define IFSR_FS0_Pos                     0U                                     /*!< \brief IFSR: FS0 Position */
+#define IFSR_FS0_Msk                     (0xFUL << IFSR_FS0_Pos)                /*!< \brief IFSR: FS0 Mask */
+
+#define IFSR_STATUS_Pos                  0U                                     /*!< \brief IFSR: STATUS Position */
+#define IFSR_STATUS_Msk                  (0x3FUL << IFSR_STATUS_Pos)            /*!< \brief IFSR: STATUS Mask */
+
+/* CP15 Register ISR */
+typedef union
+{
+  struct
+  {
+    RESERVED(0:6, uint32_t)              
+    uint32_t F:1;                        /*!< \brief bit:     6  FIQ pending bit */
+    uint32_t I:1;                        /*!< \brief bit:     7  IRQ pending bit */
+    uint32_t A:1;                        /*!< \brief bit:     8  External abort pending bit */
+    RESERVED(1:23, uint32_t)             
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} ISR_Type;
+
+#define ISR_A_Pos                        13U                                    /*!< \brief ISR: A Position */
+#define ISR_A_Msk                        (1UL << ISR_A_Pos)                     /*!< \brief ISR: A Mask */
+
+#define ISR_I_Pos                        12U                                    /*!< \brief ISR: I Position */
+#define ISR_I_Msk                        (1UL << ISR_I_Pos)                     /*!< \brief ISR: I Mask */
+
+#define ISR_F_Pos                        11U                                    /*!< \brief ISR: F Position */
+#define ISR_F_Msk                        (1UL << ISR_F_Pos)                     /*!< \brief ISR: F Mask */
+
+/* DACR Register */
+#define DACR_D_Pos_(n)                   (2U*n)                                 /*!< \brief DACR: Dn Position */
+#define DACR_D_Msk_(n)                   (3UL << DACR_D_Pos_(n))                /*!< \brief DACR: Dn Mask */
+#define DACR_Dn_NOACCESS                 0U                                     /*!< \brief DACR Dn field: No access */
+#define DACR_Dn_CLIENT                   1U                                     /*!< \brief DACR Dn field: Client */
+#define DACR_Dn_MANAGER                  3U                                     /*!< \brief DACR Dn field: Manager */
+
+/**
+  \brief     Mask and shift a bit field value for use in a register bit range.
+  \param [in] field  Name of the register bit field.
+  \param [in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param [in] field  Name of the register bit field.
+  \param [in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+
+/**
+ \brief  Union type to access the L2C_310 Cache Controller.
+*/
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+typedef struct
+{
+  __IM  uint32_t CACHE_ID;                   /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register               */
+  __IM  uint32_t CACHE_TYPE;                 /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register             */
+        RESERVED(0[0x3e], uint32_t)
+  __IOM uint32_t CONTROL;                    /*!< \brief Offset: 0x0100 (R/W) Control Register                */
+  __IOM uint32_t AUX_CNT;                    /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control               */
+        RESERVED(1[0x3e], uint32_t)
+  __IOM uint32_t EVENT_CONTROL;              /*!< \brief Offset: 0x0200 (R/W) Event Counter Control           */
+  __IOM uint32_t EVENT_COUNTER1_CONF;        /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration   */
+  __IOM uint32_t EVENT_COUNTER0_CONF;        /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration   */
+        RESERVED(2[0x2], uint32_t)
+  __IOM uint32_t INTERRUPT_MASK;             /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask                  */
+  __IM  uint32_t MASKED_INT_STATUS;          /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status         */
+  __IM  uint32_t RAW_INT_STATUS;             /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status            */
+  __OM  uint32_t INTERRUPT_CLEAR;            /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear                 */
+        RESERVED(3[0x143], uint32_t)
+  __IOM uint32_t CACHE_SYNC;                 /*!< \brief Offset: 0x0730 (R/W) Cache Sync                      */
+        RESERVED(4[0xf], uint32_t)
+  __IOM uint32_t INV_LINE_PA;                /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA           */
+        RESERVED(6[2], uint32_t)
+  __IOM uint32_t INV_WAY;                    /*!< \brief Offset: 0x077c (R/W) Invalidate by Way               */
+        RESERVED(5[0xc], uint32_t)
+  __IOM uint32_t CLEAN_LINE_PA;              /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA                */
+        RESERVED(7[1], uint32_t)
+  __IOM uint32_t CLEAN_LINE_INDEX_WAY;       /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way         */
+  __IOM uint32_t CLEAN_WAY;                  /*!< \brief Offset: 0x07bc (R/W) Clean by Way                    */
+        RESERVED(8[0xc], uint32_t)
+  __IOM uint32_t CLEAN_INV_LINE_PA;          /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA  */
+        RESERVED(9[1], uint32_t)
+  __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way  */
+  __IOM uint32_t CLEAN_INV_WAY;              /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way     */
+        RESERVED(10[0x40], uint32_t)
+  __IOM uint32_t DATA_LOCK_0_WAY;            /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way          */
+  __IOM uint32_t INST_LOCK_0_WAY;            /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way   */
+  __IOM uint32_t DATA_LOCK_1_WAY;            /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way          */
+  __IOM uint32_t INST_LOCK_1_WAY;            /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way   */
+  __IOM uint32_t DATA_LOCK_2_WAY;            /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way          */
+  __IOM uint32_t INST_LOCK_2_WAY;            /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way   */
+  __IOM uint32_t DATA_LOCK_3_WAY;            /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way          */
+  __IOM uint32_t INST_LOCK_3_WAY;            /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way   */
+  __IOM uint32_t DATA_LOCK_4_WAY;            /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way          */
+  __IOM uint32_t INST_LOCK_4_WAY;            /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way   */
+  __IOM uint32_t DATA_LOCK_5_WAY;            /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way          */
+  __IOM uint32_t INST_LOCK_5_WAY;            /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way   */
+  __IOM uint32_t DATA_LOCK_6_WAY;            /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way          */
+  __IOM uint32_t INST_LOCK_6_WAY;            /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way   */
+  __IOM uint32_t DATA_LOCK_7_WAY;            /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way          */
+  __IOM uint32_t INST_LOCK_7_WAY;            /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way   */
+        RESERVED(11[0x4], uint32_t)
+  __IOM uint32_t LOCK_LINE_EN;               /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable         */
+  __IOM uint32_t UNLOCK_ALL_BY_WAY;          /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way         */
+        RESERVED(12[0xaa], uint32_t)
+  __IOM uint32_t ADDRESS_FILTER_START;       /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start         */
+  __IOM uint32_t ADDRESS_FILTER_END;         /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End           */
+        RESERVED(13[0xce], uint32_t)
+  __IOM uint32_t DEBUG_CONTROL;              /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register          */
+} L2C_310_TypeDef;
+
+#define L2C_310           ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
+#endif
+
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+    
+/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
+*/
+typedef struct
+{
+  __IOM uint32_t CTLR;                 /*!< \brief  Offset: 0x000 (R/W) Distributor Control Register */
+  __IM  uint32_t TYPER;                /*!< \brief  Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+  __IM  uint32_t IIDR;                 /*!< \brief  Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
+        RESERVED(0, uint32_t)
+  __IOM uint32_t STATUSR;              /*!< \brief  Offset: 0x010 (R/W) Error Reporting Status Register, optional */
+        RESERVED(1[11], uint32_t)
+  __OM  uint32_t SETSPI_NSR;           /*!< \brief  Offset: 0x040 ( /W) Set SPI Register */
+        RESERVED(2, uint32_t)
+  __OM  uint32_t CLRSPI_NSR;           /*!< \brief  Offset: 0x048 ( /W) Clear SPI Register */
+        RESERVED(3, uint32_t)
+  __OM  uint32_t SETSPI_SR;            /*!< \brief  Offset: 0x050 ( /W) Set SPI, Secure Register */
+        RESERVED(4, uint32_t)
+  __OM  uint32_t CLRSPI_SR;            /*!< \brief  Offset: 0x058 ( /W) Clear SPI, Secure Register */
+        RESERVED(5[9], uint32_t)
+  __IOM uint32_t IGROUPR[32];          /*!< \brief  Offset: 0x080 (R/W) Interrupt Group Registers */
+  __IOM uint32_t ISENABLER[32];        /*!< \brief  Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
+  __IOM uint32_t ICENABLER[32];        /*!< \brief  Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
+  __IOM uint32_t ISPENDR[32];          /*!< \brief  Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
+  __IOM uint32_t ICPENDR[32];          /*!< \brief  Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
+  __IOM uint32_t ISACTIVER[32];        /*!< \brief  Offset: 0x300 (R/W) Interrupt Set-Active Registers */
+  __IOM uint32_t ICACTIVER[32];        /*!< \brief  Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
+  __IOM uint32_t IPRIORITYR[255];      /*!< \brief  Offset: 0x400 (R/W) Interrupt Priority Registers */
+        RESERVED(6, uint32_t)
+  __IOM uint32_t  ITARGETSR[255];      /*!< \brief  Offset: 0x800 (R/W) Interrupt Targets Registers */
+        RESERVED(7, uint32_t)
+  __IOM uint32_t ICFGR[64];            /*!< \brief  Offset: 0xC00 (R/W) Interrupt Configuration Registers */
+  __IOM uint32_t IGRPMODR[32];         /*!< \brief  Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
+        RESERVED(8[32], uint32_t)
+  __IOM uint32_t NSACR[64];            /*!< \brief  Offset: 0xE00 (R/W) Non-secure Access Control Registers */
+  __OM  uint32_t SGIR;                 /*!< \brief  Offset: 0xF00 ( /W) Software Generated Interrupt Register */
+        RESERVED(9[3], uint32_t)
+  __IOM uint32_t CPENDSGIR[4];         /*!< \brief  Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
+  __IOM uint32_t SPENDSGIR[4];         /*!< \brief  Offset: 0xF20 (R/W) SGI Set-Pending Registers */
+        RESERVED(10[5236], uint32_t)
+  __IOM uint64_t IROUTER[988];         /*!< \brief  Offset: 0x6100(R/W) Interrupt Routing Registers */
+}  GICDistributor_Type;
+
+#define GICDistributor      ((GICDistributor_Type      *)     GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
+
+/** \brief  Structure type to access the Generic Interrupt Controller Interface (GICC)
+*/
+typedef struct
+{
+  __IOM uint32_t CTLR;                 /*!< \brief  Offset: 0x000 (R/W) CPU Interface Control Register */
+  __IOM uint32_t PMR;                  /*!< \brief  Offset: 0x004 (R/W) Interrupt Priority Mask Register */
+  __IOM uint32_t BPR;                  /*!< \brief  Offset: 0x008 (R/W) Binary Point Register */
+  __IM  uint32_t IAR;                  /*!< \brief  Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
+  __OM  uint32_t EOIR;                 /*!< \brief  Offset: 0x010 ( /W) End Of Interrupt Register */
+  __IM  uint32_t RPR;                  /*!< \brief  Offset: 0x014 (R/ ) Running Priority Register */
+  __IM  uint32_t HPPIR;                /*!< \brief  Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
+  __IOM uint32_t ABPR;                 /*!< \brief  Offset: 0x01C (R/W) Aliased Binary Point Register */
+  __IM  uint32_t AIAR;                 /*!< \brief  Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
+  __OM  uint32_t AEOIR;                /*!< \brief  Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
+  __IM  uint32_t AHPPIR;               /*!< \brief  Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
+  __IOM uint32_t STATUSR;              /*!< \brief  Offset: 0x02C (R/W) Error Reporting Status Register, optional */
+        RESERVED(1[40], uint32_t)
+  __IOM uint32_t APR[4];               /*!< \brief  Offset: 0x0D0 (R/W) Active Priority Register */
+  __IOM uint32_t NSAPR[4];             /*!< \brief  Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
+        RESERVED(2[3], uint32_t)
+  __IM  uint32_t IIDR;                 /*!< \brief  Offset: 0x0FC (R/ ) CPU Interface Identification Register */
+        RESERVED(3[960], uint32_t)
+  __OM  uint32_t DIR;                  /*!< \brief  Offset: 0x1000( /W) Deactivate Interrupt Register */
+}  GICInterface_Type;
+
+#define GICInterface        ((GICInterface_Type        *)     GIC_INTERFACE_BASE )   /*!< \brief GIC Interface register set access pointer */
+#endif
+
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Structure type to access the Private Timer
+*/
+typedef struct
+{
+  __IOM uint32_t LOAD;            //!< \brief  Offset: 0x000 (R/W) Private Timer Load Register
+  __IOM uint32_t COUNTER;         //!< \brief  Offset: 0x004 (R/W) Private Timer Counter Register
+  __IOM uint32_t CONTROL;         //!< \brief  Offset: 0x008 (R/W) Private Timer Control Register
+  __IOM uint32_t ISR;             //!< \brief  Offset: 0x00C (R/W) Private Timer Interrupt Status Register
+        RESERVED(0[4], uint32_t)
+  __IOM uint32_t WLOAD;           //!< \brief  Offset: 0x020 (R/W) Watchdog Load Register
+  __IOM uint32_t WCOUNTER;        //!< \brief  Offset: 0x024 (R/W) Watchdog Counter Register
+  __IOM uint32_t WCONTROL;        //!< \brief  Offset: 0x028 (R/W) Watchdog Control Register
+  __IOM uint32_t WISR;            //!< \brief  Offset: 0x02C (R/W) Watchdog Interrupt Status Register
+  __IOM uint32_t WRESET;          //!< \brief  Offset: 0x030 (R/W) Watchdog Reset Status Register
+  __OM  uint32_t WDISABLE;        //!< \brief  Offset: 0x034 ( /W) Watchdog Disable Register
+} Timer_Type;
+#define PTIM ((Timer_Type *) TIMER_BASE )   /*!< \brief Timer register struct */
+#endif
+#endif
+
+ /*******************************************************************************
+  *                Hardware Abstraction Layer
+   Core Function Interface contains:
+   - L1 Cache Functions
+   - L2C-310 Cache Controller Functions 
+   - PL1 Timer Functions
+   - GIC Functions
+   - MMU Functions
+  ******************************************************************************/
+ 
+/* ##########################  L1 Cache functions  ################################# */
+
+/** \brief Enable Caches by setting I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableCaches(void) {
+  __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
+  __ISB();
+}
+
+/** \brief Disable Caches by clearing I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableCaches(void) {
+  __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
+  __ISB();
+}
+
+/** \brief  Enable Branch Prediction by setting Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
+  __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
+  __ISB();
+}
+
+/** \brief  Disable Branch Prediction by clearing Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
+  __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
+  __ISB();
+}
+
+/** \brief  Invalidate entire branch predictor array
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
+  __set_BPIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+/** \brief  Invalidate the whole instruction cache
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
+  __set_ICIALLU(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean data cache line by address.
+* \param [in] va Pointer to data to clear the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
+  __set_DCCMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate data cache line by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
+  __set_DCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate data cache by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
+  __set_DCCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Calculate log2 rounded up
+*  - log(0)  => 0
+*  - log(1)  => 0
+*  - log(2)  => 1
+*  - log(3)  => 2
+*  - log(4)  => 2
+*  - log(5)  => 3
+*        :      :
+*  - log(16) => 4
+*  - log(32) => 5
+*        :      :
+* \param [in] n input value parameter 
+* \return log2(n)
+*/
+__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
+{
+  if (n < 2U) {
+    return 0U;
+  }
+  uint8_t log = 0U;
+  uint32_t t = n;
+  while(t > 1U)
+  {
+    log++;
+    t >>= 1U;
+  }
+  if (n & 1U) { log++; }
+  return log;
+}
+
+/** \brief  Apply cache maintenance to given cache level.
+* \param [in] level cache level to be maintained
+* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
+{
+  uint32_t Dummy;
+  uint32_t ccsidr;
+  uint32_t num_sets;
+  uint32_t num_ways;
+  uint32_t shift_way;
+  uint32_t log2_linesize;
+   int32_t log2_num_ways;
+
+  Dummy = level << 1U;
+  /* set csselr, select ccsidr register */
+  __set_CSSELR(Dummy);
+  /* get current ccsidr register */
+  ccsidr = __get_CCSIDR();
+  num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
+  num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
+  log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
+  log2_num_ways = __log2_up(num_ways);
+  if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
+    return; // FATAL ERROR
+  }
+  shift_way = 32U - (uint32_t)log2_num_ways;
+  for(int32_t way = num_ways-1; way >= 0; way--)
+  {
+    for(int32_t set = num_sets-1; set >= 0; set--)
+    {
+      Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
+      switch (maint)
+      {
+        case 0U: __set_DCISW(Dummy);  break;
+        case 1U: __set_DCCSW(Dummy);  break;
+        default: __set_DCCISW(Dummy); break;
+      }
+    }
+  }
+  __DMB();
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
+  uint32_t clidr;
+  uint32_t cache_type;
+  clidr =  __get_CLIDR();
+  for(uint32_t i = 0U; i<7U; i++)
+  {
+    cache_type = (clidr >> i*3U) & 0x7UL;
+    if ((cache_type >= 2U) && (cache_type <= 4U))
+    {
+      __L1C_MaintainDCacheSetWay(i, op);
+    }
+  }
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+* \deprecated Use generic L1C_CleanInvalidateCache instead.
+*/
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
+  L1C_CleanInvalidateCache(op);
+}
+
+/** \brief  Invalidate the whole data cache.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(0);
+}
+
+/** \brief  Clean the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
+  L1C_CleanInvalidateCache(1);
+}
+
+/** \brief  Clean and invalidate the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(2);
+}
+
+/* ##########################  L2 Cache functions  ################################# */
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+/** \brief Cache Sync operation by writing CACHE_SYNC register.
+*/
+__STATIC_INLINE void L2C_Sync(void)
+{
+  L2C_310->CACHE_SYNC = 0x0;
+}
+
+/** \brief Read cache controller cache ID from CACHE_ID register.
+ * \return L2C_310_TypeDef::CACHE_ID
+ */
+__STATIC_INLINE int L2C_GetID (void)
+{
+  return L2C_310->CACHE_ID;
+}
+
+/** \brief Read cache controller cache type from CACHE_TYPE register.
+*  \return L2C_310_TypeDef::CACHE_TYPE
+*/
+__STATIC_INLINE int L2C_GetType (void)
+{
+  return L2C_310->CACHE_TYPE;
+}
+
+/** \brief Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_InvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1U << 16U)) {
+    assoc = 16U;
+  } else {
+    assoc =  8U;
+  }
+  
+  L2C_310->INV_WAY = (1U << assoc) - 1U;
+  while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+  L2C_Sync();
+}
+
+/** \brief Clean and Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_CleanInvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1U << 16U)) {
+    assoc = 16U;
+  } else {
+    assoc =  8U;
+  }
+
+  L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
+  while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+  L2C_Sync();
+}
+
+/** \brief Enable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Enable(void)
+{
+  L2C_310->CONTROL = 0;
+  L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
+  L2C_310->DEBUG_CONTROL = 0;
+  L2C_310->DATA_LOCK_0_WAY = 0;
+  L2C_310->CACHE_SYNC = 0;
+  L2C_310->CONTROL = 0x01;
+  L2C_Sync();
+}
+
+/** \brief Disable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Disable(void)
+{
+  L2C_310->CONTROL = 0x00;
+  L2C_Sync();
+}
+
+/** \brief Invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_InvPa (void *pa)
+{
+  L2C_310->INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+/** \brief Clean cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanPa (void *pa)
+{
+  L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+/** \brief Clean and invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanInvPa (void *pa)
+{
+  L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+#endif
+
+/* ##########################  GIC functions  ###################################### */
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+  
+/** \brief  Enable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_EnableDistributor(void)
+{
+  GICDistributor->CTLR |= 1U;
+}
+
+/** \brief Disable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_DisableDistributor(void)
+{
+  GICDistributor->CTLR &=~1U;
+}
+
+/** \brief Read the GIC's TYPER register.
+* \return GICDistributor_Type::TYPER
+*/
+__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
+{
+  return (GICDistributor->TYPER);
+}
+
+/** \brief Reads the GIC's IIDR register.
+* \return GICDistributor_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
+{
+  return (GICDistributor->IIDR);
+}
+
+/** \brief Sets the GIC's ITARGETSR register for the given interrupt.
+* \param [in] IRQn Interrupt to be configured.
+* \param [in] cpu_target CPU interfaces to assign this interrupt to.
+*/
+__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+  uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+  GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the GIC's ITARGETSR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return GICDistributor_Type::ITARGETSR
+*/
+__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+  return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Enable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_EnableInterface(void)
+{
+  GICInterface->CTLR |= 1U; //enable interface
+}
+
+/** \brief Disable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_DisableInterface(void)
+{
+  GICInterface->CTLR &=~1U; //disable distributor
+}
+
+/** \brief Read the CPU's IAR register.
+* \return GICInterface_Type::IAR
+*/
+__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
+{
+  return (IRQn_Type)(GICInterface->IAR);
+}
+
+/** \brief Writes the given interrupt number to the CPU's EOIR register.
+* \param [in] IRQn The interrupt to be signaled as finished.
+*/
+__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+  GICInterface->EOIR = IRQn;
+}
+
+/** \brief Enables the given interrupt using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt enable status using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
+*/
+__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+
+/** \brief Disables the given interrupt using GIC's ICENABLER register.
+* \param [in] IRQn The interrupt to be disabled.
+*/
+__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt pending status from GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not pending, 1 - interrupt is pendig.
+*/
+__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  uint32_t pend;
+
+  if (IRQn >= 16U) {
+    pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+    // No CPU identification offered
+    if (pend != 0U) {
+      pend = 1U;
+    } else {
+      pend = 0U;
+    }
+  }
+
+  return (pend);
+}
+
+/** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if (IRQn >= 16U) {
+    GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+  }
+}
+
+/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if (IRQn >= 16U) {
+    GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+  }
+}
+
+/** \brief Sets the interrupt configuration using GIC's ICFGR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+*                                           Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
+{
+  uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
+  uint32_t shift = (IRQn % 16U) << 1U;
+
+  icfgr &= (~(3U         << shift));
+  icfgr |= (  int_config << shift);
+
+  GICDistributor->ICFGR[IRQn / 16U] = icfgr;
+}
+
+/** \brief Get the interrupt configuration from the GIC's ICFGR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+*                                 Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
+{
+  return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
+}
+
+/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] priority The priority for the interrupt, lower values denote higher priorities.
+*/
+__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+  GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be queried.
+*/
+__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+  return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Set the interrupt priority mask using CPU's PMR register.
+* \param [in] priority Priority mask to be set.
+*/
+__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
+{
+  GICInterface->PMR = priority & 0xFFUL; //set priority mask
+}
+
+/** \brief Read the current interrupt priority mask from CPU's PMR register.
+* \result GICInterface_Type::PMR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
+{
+  return GICInterface->PMR;
+}
+
+/** \brief Configures the group priority and subpriority split point using CPU's BPR register.
+* \param [in] binary_point Amount of bits used as subpriority.
+*/
+__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+  GICInterface->BPR = binary_point & 7U; //set binary point
+}
+
+/** \brief Read the current group priority and subpriority split point from CPU's BPR register.
+* \return GICInterface_Type::BPR
+*/
+__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
+{
+  return GICInterface->BPR;
+}
+
+/** \brief Get the status for a given interrupt.
+* \param [in] IRQn The interrupt to get status for.
+* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
+*/
+__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+  uint32_t pending, active;
+
+  active = ((GICDistributor->ISACTIVER[IRQn / 32U])  >> (IRQn % 32U)) & 1UL;
+  pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
+
+  return ((active<<1U) | pending);
+}
+
+/** \brief Generate a software interrupt using GIC's SGIR register.
+* \param [in] IRQn Software interrupt to be generated.
+* \param [in] target_list List of CPUs the software interrupt should be forwarded to.
+* \param [in] filter_list Filter to be applied to determine interrupt receivers.
+*/
+__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+  GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
+}
+
+/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
+* \return GICInterface_Type::HPPIR
+*/
+__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) 
+{ 
+  return GICInterface->HPPIR; 
+}
+
+/** \brief Provides information about the implementer and revision of the CPU interface.
+* \return GICInterface_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
+{ 
+  return GICInterface->IIDR; 
+}
+
+/** \brief Set the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
+{
+  uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
+  uint32_t shift   = (IRQn % 32U);
+
+  igroupr &= (~(1U          << shift));
+  igroupr |= ( (group & 1U) << shift);
+
+  GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
+}
+#define GIC_SetSecurity         GIC_SetGroup
+
+/** \brief Get the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
+{
+  return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+#define GIC_GetSecurity         GIC_GetGroup
+
+/** \brief Initialize the interrupt distributor.
+*/
+__STATIC_INLINE void GIC_DistInit(void)
+{
+  uint32_t i;
+  uint32_t num_irq = 0U;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableDistributor();
+  //Get the maximum number of interrupts that the GIC supports
+  num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+  priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+  for (i = 32U; i < num_irq; i++)
+  {
+      //Disable the SPI interrupt
+      GIC_DisableIRQ((IRQn_Type)i);
+      //Set level-sensitive (and N-N model)
+      GIC_SetConfiguration((IRQn_Type)i, 0U);
+      //Set priority
+      GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+      //Set target list to CPU0
+      GIC_SetTarget((IRQn_Type)i, 1U);
+  }
+  //Enable distributor
+  GIC_EnableDistributor();
+}
+
+/** \brief Initialize the CPU's interrupt interface
+*/
+__STATIC_INLINE void GIC_CPUInterfaceInit(void)
+{
+  uint32_t i;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableInterface();
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+  priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+  //SGI and PPI
+  for (i = 0U; i < 32U; i++)
+  {
+    if(i > 15U) {
+      //Set level-sensitive (and N-N model) for PPI
+      GIC_SetConfiguration((IRQn_Type)i, 0U);
+    }
+    //Disable SGI and PPI interrupts
+    GIC_DisableIRQ((IRQn_Type)i);
+    //Set priority
+    GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+  }
+  //Enable interface
+  GIC_EnableInterface();
+  //Set binary point to 0
+  GIC_SetBinaryPoint(0U);
+  //Set priority mask
+  GIC_SetInterfacePriorityMask(0xFFU);
+}
+
+/** \brief Initialize and enable the GIC
+*/
+__STATIC_INLINE void GIC_Enable(void)
+{
+  GIC_DistInit();
+  GIC_CPUInterfaceInit(); //per CPU
+}
+#endif
+
+/* ##########################  Generic Timer functions  ############################ */
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+  
+/* PL1 Physical Timer */
+#if (__CORTEX_A == 7U) || defined(DOXYGEN)
+  
+/** \brief Physical Timer Control register */
+typedef union
+{
+  struct
+  {
+    uint32_t ENABLE:1;      /*!< \brief bit: 0      Enables the timer. */
+    uint32_t IMASK:1;       /*!< \brief bit: 1      Timer output signal mask bit. */
+    uint32_t ISTATUS:1;     /*!< \brief bit: 2      The status of the timer. */
+    RESERVED(0:29, uint32_t)
+  } b;                      /*!< \brief Structure used for bit  access */
+  uint32_t w;               /*!< \brief Type      used for word access */
+} CNTP_CTL_Type;
+
+/** \brief Configures the frequency the timer shall run at.
+* \param [in] value The timer frequency in Hz.
+*/
+__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
+{
+  __set_CNTFRQ(value);
+  __ISB();
+}
+
+/** \brief Sets the reset value of the timer.
+* \param [in] value The value the timer is loaded with.
+*/
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
+{
+  __set_CNTP_TVAL(value);
+  __ISB();
+}
+
+/** \brief Get the current counter value.
+* \return Current counter value.
+*/
+__STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
+{
+  return(__get_CNTP_TVAL());
+}
+
+/** \brief Get the current physical counter value.
+* \return Current physical counter value.
+*/
+__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
+{
+  return(__get_CNTPCT());
+}
+
+/** \brief Set the physical compare value.
+* \param [in] value New physical timer compare value.
+*/
+__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
+{
+  __set_CNTP_CVAL(value);
+  __ISB();
+}
+
+/** \brief Get the physical compare value.
+* \return Physical compare value.
+*/
+__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
+{
+  return(__get_CNTP_CVAL());
+}
+
+/** \brief Configure the timer by setting the control value.
+* \param [in] value New timer control value.
+*/
+__STATIC_INLINE void PL1_SetControl(uint32_t value)
+{
+  __set_CNTP_CTL(value);
+  __ISB();
+}
+
+/** \brief Get the control value.
+* \return Control value.
+*/
+__STATIC_INLINE uint32_t PL1_GetControl(void)
+{
+  return(__get_CNTP_CTL());
+}
+#endif
+
+/* Private Timer */
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Set the load value to timers LOAD register.
+* \param [in] value The load value to be set.
+*/
+__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
+{
+  PTIM->LOAD = value;
+}
+
+/** \brief Get the load value from timers LOAD register.
+* \return Timer_Type::LOAD
+*/
+__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
+{
+  return(PTIM->LOAD);
+}
+
+/** \brief Set current counter value from its COUNTER register.
+*/
+__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
+{
+  PTIM->COUNTER = value;
+}
+
+/** \brief Get current counter value from timers COUNTER register.
+* \result Timer_Type::COUNTER
+*/
+__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
+{
+  return(PTIM->COUNTER);
+}
+
+/** \brief Configure the timer using its CONTROL register.
+* \param [in] value The new configuration value to be set.
+*/
+__STATIC_INLINE void PTIM_SetControl(uint32_t value)
+{
+  PTIM->CONTROL = value;
+}
+
+/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
+* \return Timer_Type::CONTROL
+*/
+__STATIC_INLINE uint32_t PTIM_GetControl(void)
+{
+  return(PTIM->CONTROL);
+}
+
+/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
+* \return 0 - flag is not set, 1- flag is set
+*/
+__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
+{
+  return (PTIM->ISR & 1UL);
+}
+
+/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
+*/
+__STATIC_INLINE void PTIM_ClearEventFlag(void)
+{
+  PTIM->ISR = 1;
+}
+#endif
+#endif
+
+/* ##########################  MMU functions  ###################################### */
+
+#define SECTION_DESCRIPTOR      (0x2)
+#define SECTION_MASK            (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
+#define SECTION_B_SHIFT         (2)
+#define SECTION_C_SHIFT         (3)
+#define SECTION_TEX0_SHIFT      (12)
+#define SECTION_TEX1_SHIFT      (13)
+#define SECTION_TEX2_SHIFT      (14)
+
+#define SECTION_XN_MASK         (0xFFFFFFEF)
+#define SECTION_XN_SHIFT        (4)
+
+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT    (5)
+
+#define SECTION_P_MASK          (0xFFFFFDFF)
+#define SECTION_P_SHIFT         (9)
+
+#define SECTION_AP_MASK         (0xFFFF73FF)
+#define SECTION_AP_SHIFT        (10)
+#define SECTION_AP2_SHIFT       (15)
+
+#define SECTION_S_MASK          (0xFFFEFFFF)
+#define SECTION_S_SHIFT         (16)
+
+#define SECTION_NG_MASK         (0xFFFDFFFF)
+#define SECTION_NG_SHIFT        (17)
+
+#define SECTION_NS_MASK         (0xFFF7FFFF)
+#define SECTION_NS_SHIFT        (19)
+
+#define PAGE_L1_DESCRIPTOR      (0x1)
+#define PAGE_L1_MASK            (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC         (0x2)
+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC        (0x1)
+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT         (2)
+#define PAGE_4K_C_SHIFT         (3)
+#define PAGE_4K_TEX0_SHIFT      (6)
+#define PAGE_4K_TEX1_SHIFT      (7)
+#define PAGE_4K_TEX2_SHIFT      (8)
+
+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT        (2)
+#define PAGE_64K_C_SHIFT        (3)
+#define PAGE_64K_TEX0_SHIFT     (12)
+#define PAGE_64K_TEX1_SHIFT     (13)
+#define PAGE_64K_TEX2_SHIFT     (14)
+
+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
+#define PAGE_B_SHIFT            (2)
+#define PAGE_C_SHIFT            (3)
+#define PAGE_TEX_SHIFT          (12)
+
+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT        (0)
+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT       (15)
+
+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT       (5)
+
+#define PAGE_P_MASK             (0xFFFFFDFF)
+#define PAGE_P_SHIFT            (9)
+
+#define PAGE_AP_MASK            (0xFFFFFDCF)
+#define PAGE_AP_SHIFT           (4)
+#define PAGE_AP2_SHIFT          (9)
+
+#define PAGE_S_MASK             (0xFFFFFBFF)
+#define PAGE_S_SHIFT            (10)
+
+#define PAGE_NG_MASK            (0xFFFFF7FF)
+#define PAGE_NG_SHIFT           (11)
+
+#define PAGE_NS_MASK            (0xFFFFFFF7)
+#define PAGE_NS_SHIFT           (3)
+
+#define OFFSET_1M               (0x00100000)
+#define OFFSET_64K              (0x00010000)
+#define OFFSET_4K               (0x00001000)
+
+#define DESCRIPTOR_FAULT        (0x00000000)
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+   SECTION,
+   PAGE_4k,
+   PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+   NORMAL,
+   DEVICE,
+   SHARED_DEVICE,
+   NON_SHARED_DEVICE,
+   STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+   NON_CACHEABLE,
+   WB_WA,
+   WT,
+   WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+   ECC_DISABLED,
+   ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+   EXECUTE,
+   NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+   GLOBAL,
+   NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+   NON_SHARED,
+   SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+   SECURE,
+   NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+   NO_ACCESS,
+   RW,
+   READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+    mmu_region_size_Type rg_t;
+    mmu_memory_Type mem_t;
+    uint8_t domain;
+    mmu_cacheability_Type inner_norm_t;
+    mmu_cacheability_Type outer_norm_t;
+    mmu_ecc_check_Type e_t;
+    mmu_execute_Type xn_t;
+    mmu_global_Type g_t;
+    mmu_secure_Type sec_t;
+    mmu_access_Type priv_t;
+    mmu_access_Type user_t;
+    mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+//Following macros define the descriptors and attributes
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
+#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
+#define section_normal_nc(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+/** \brief  Set section execution-never attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+  *descriptor_l1 &= SECTION_XN_MASK;
+  *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Section domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= SECTION_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section access privileges
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l1 &= SECTION_AP_MASK;
+  *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+  *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set section shareability
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_S_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Global attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+  *descriptor_l1 &= SECTION_NG_MASK;
+  *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+  return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief  Set 4k/64k page execution-never attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
+  \param [in]              page  Page size: PAGE_4k, PAGE_64k,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+  if (page == PAGE_4k)
+  {
+      *descriptor_l2 &= PAGE_XN_4K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+  }
+  else
+  {
+      *descriptor_l2 &= PAGE_XN_64K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Page domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= PAGE_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page access privileges
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x6; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l2 &= PAGE_AP_MASK;
+  *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+  *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set 4k/64k page shareability
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+  *descriptor_l2 &= PAGE_S_MASK;
+  *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Global attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+  *descriptor_l2 &= PAGE_NG_MASK;
+  *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= PAGE_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+  return 0;
+}
+
+/** \brief  Set Section memory attributes
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+  *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+  if (STRONGLY_ORDERED == mem)
+  {
+    return 0;
+  }
+  else if (SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+  }
+  else if (NON_SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+  }
+  else if (NORMAL == mem)
+  {
+   *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+   switch(inner)
+   {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+        break;
+    }
+    switch(outer)
+    {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+        break;
+    }
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page memory attributes
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]              page  Page size
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+  *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+  if (page == PAGE_64k)
+  {
+    //same as section
+    MMU_MemorySection(descriptor_l2, mem, outer, inner);
+  }
+  else
+  {
+    if (STRONGLY_ORDERED == mem)
+    {
+      return 0;
+    }
+    else if (SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+    }
+    else if (NON_SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+    }
+    else if (NORMAL == mem)
+    {
+      *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+      switch(inner)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+          break;
+      }
+      switch(outer)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+      }
+    }
+  }
+
+  return 0;
+}
+
+/** \brief  Create a L1 section descriptor
+
+  \param [out]     descriptor  L1 descriptor
+  \param [in]      reg  Section attributes
+  
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+
+  MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+  MMU_XNSection(descriptor,reg.xn_t);
+  MMU_DomainSection(descriptor, reg.domain);
+  MMU_PSection(descriptor, reg.e_t);
+  MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
+  MMU_SharedSection(descriptor,reg.sh_t);
+  MMU_GlobalSection(descriptor,reg.g_t);
+  MMU_SecureSection(descriptor,reg.sec_t);
+  *descriptor &= SECTION_MASK;
+  *descriptor |= SECTION_DESCRIPTOR;
+ 
+  return 0;
+}
+
+
+/** \brief  Create a L1 and L2 4k/64k page descriptor
+
+  \param [out]       descriptor  L1 descriptor
+  \param [out]      descriptor2  L2 descriptor
+  \param [in]               reg  4k/64k page attributes
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+  *descriptor2 = 0;
+
+  switch (reg.rg_t)
+  {
+    case PAGE_4k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_4K_MASK;
+      *descriptor2 |= PAGE_L2_4K_DESC;
+      break;
+
+    case PAGE_64k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_64K_MASK;
+      *descriptor2 |= PAGE_L2_64K_DESC;
+      break;
+
+    case SECTION:
+      //error
+      break;
+  }
+  
+  return 0;
+}
+
+/** \brief  Create a 1MB Section
+
+  \param [in]               ttb  Translation table base address
+  \param [in]      base_address  Section base address
+  \param [in]             count  Number of sections to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+  uint32_t offset;
+  uint32_t entry;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = (base_address & 0xFFF00000) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb = ttb + offset;
+
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb++ = entry;
+    entry += OFFSET_1M;
+  }
+}
+
+/** \brief  Create a 4k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  4k base address
+  \param [in]             count  Number of 4k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb_l2++ = entry2;
+    entry2 += OFFSET_4K;
+  }
+}
+
+/** \brief  Create a 64k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  64k base address
+  \param [in]             count  Number of 64k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i,j;
+
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //create 16 entries
+    for (j = 0; j < 16; j++)
+    {
+      //4 bytes aligned
+      *ttb_l2++ = entry2;
+    }
+    entry2 += OFFSET_64K;
+  }
+}
+
+/** \brief  Enable MMU
+*/
+__STATIC_INLINE void MMU_Enable(void)
+{
+  // Set M bit 0 to enable the MMU
+  // Set AFE bit to enable simplified access permissions model
+  // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+  __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+  __ISB();
+}
+
+/** \brief  Disable MMU
+*/
+__STATIC_INLINE void MMU_Disable(void)
+{
+  // Clear M bit 0 to disable the MMU
+  __set_SCTLR( __get_SCTLR() & ~1);
+  __ISB();
+}
+
+/** \brief  Invalidate entire unified TLB
+*/
+
+__STATIC_INLINE void MMU_InvalidateTLB(void)
+{
+  __set_TLBIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/irq_ctrl.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/irq_ctrl.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/irq_ctrl.h	(revision 374)
@@ -0,0 +1,186 @@
+/**************************************************************************//**
+ * @file     irq_ctrl.h
+ * @brief    Interrupt Controller API header file
+ * @version  V1.0.0
+ * @date     23. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
+#include <stdint.h>
+
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+/// Interrupt handler data type
+typedef void (*IRQHandler_t) (void);
+#endif
+
+#ifndef IRQN_ID_T
+#define IRQN_ID_T
+/// Interrupt ID number data type
+typedef int32_t IRQn_ID_t;
+#endif
+
+/* Interrupt mode bit-masks */
+#define IRQ_MODE_TRIG_Pos           (0U)
+#define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+#define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
+#define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
+
+#define IRQ_MODE_TYPE_Pos           (3U)
+#define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)
+#define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line
+#define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line
+
+#define IRQ_MODE_DOMAIN_Pos         (4U)
+#define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)
+#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain
+#define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain
+
+#define IRQ_MODE_CPU_Pos            (5U)
+#define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)
+#define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs
+#define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0
+#define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1
+#define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2
+#define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3
+#define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4
+#define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5
+#define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
+#define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
+
+#define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
+
+/* Interrupt priority bit-masks */
+#define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask
+#define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error
+
+/// Initialize interrupt controller.
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Initialize (void);
+
+/// Register interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     handler       interrupt handler function address
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
+
+/// Get the registered interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \return registered interrupt handler function address.
+IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
+
+/// Enable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Enable (IRQn_ID_t irqn);
+
+/// Disable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Disable (IRQn_ID_t irqn);
+
+/// Get interrupt enable state.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
+uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
+
+/// Configure interrupt request mode.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     mode          mode configuration
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
+
+/// Get interrupt mode configuration.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+uint32_t IRQ_GetMode (IRQn_ID_t irqn);
+
+/// Get ID number of current interrupt request (IRQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveIRQ (void);
+
+/// Get ID number of current fast interrupt request (FIQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveFIQ (void);
+
+/// Signal end of interrupt processing.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
+
+/// Set interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPending (IRQn_ID_t irqn);
+
+/// Get interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
+uint32_t IRQ_GetPending (IRQn_ID_t irqn);
+
+/// Clear interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_ClearPending (IRQn_ID_t irqn);
+
+/// Set interrupt priority value.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     priority      interrupt priority value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
+
+/// Get interrupt priority.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
+
+/// Set priority masking threshold.
+/// \param[in]     priority      priority masking threshold value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityMask (uint32_t priority);
+
+/// Get priority masking threshold
+/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityMask (void);
+
+/// Set priority grouping field split point
+/// \param[in]     bits          number of MSB bits included in the group priority field comparison
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
+
+/// Get priority grouping field split point
+/// \return current number of MSB bits included in the group priority field comparison with
+///         optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityGroupBits (void);
+
+#endif  // IRQ_CTRL_H_
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c	(revision 374)
@@ -0,0 +1,410 @@
+/**************************************************************************//**
+ * @file     irq_ctrl_gic.c
+ * @brief    Interrupt controller handling implementation for GIC
+ * @version  V1.0.1
+ * @date     9. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT      (1020U)
+#endif
+
+extern IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT];
+static uint32_t     IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+  uint32_t i;
+
+  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+    IRQTable[i] = (IRQHandler_t)NULL;
+  }
+  GIC_Enable();
+  return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    IRQTable[irqn] = handler;
+    status =  0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+  IRQHandler_t h;
+
+  // Ignore CPUID field (software generated interrupts)
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    h = IRQTable[irqn];
+  } else {
+    h = (IRQHandler_t)0;
+  }
+
+  return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EnableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_DisableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+  uint32_t enable;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+  } else {
+    enable = 0U;
+  }
+
+  return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+  uint32_t val;
+  uint8_t cfg;
+  uint8_t secure;
+  uint8_t cpu;
+  int32_t status = 0;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    // Check triggering mode
+    val = (mode & IRQ_MODE_TRIG_Msk);
+
+    if (val == IRQ_MODE_TRIG_LEVEL) {
+      cfg = 0x00U;
+    } else if (val == IRQ_MODE_TRIG_EDGE) {
+      cfg = 0x02U;
+    } else {
+      cfg = 0x00U;
+      status = -1;
+    }
+
+    // Check interrupt type
+    val = mode & IRQ_MODE_TYPE_Msk;
+
+    if (val != IRQ_MODE_TYPE_IRQ) {
+      status = -1;
+    }
+
+    // Check interrupt domain
+    val = mode & IRQ_MODE_DOMAIN_Msk;
+
+    if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+      secure = 0U;
+    } else {
+      // Check security extensions support
+      val = GIC_DistributorInfo() & (1UL << 10U);
+
+      if (val != 0U) {
+        // Security extensions are supported
+        secure = 1U;
+      } else {
+        secure = 0U;
+        status = -1;
+      }
+    }
+
+    // Check interrupt CPU targets
+    val = mode & IRQ_MODE_CPU_Msk;
+
+    if (val == IRQ_MODE_CPU_ALL) {
+      cpu = 0xFFU;
+    } else {
+      cpu = val >> IRQ_MODE_CPU_Pos;
+    }
+
+    // Apply configuration if no mode error
+    if (status == 0) {
+      GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+      GIC_SetTarget       ((IRQn_Type)irqn, cpu);
+
+      if (secure != 0U) {
+        GIC_SetGroup ((IRQn_Type)irqn, secure);
+      }
+    }
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+  uint32_t mode;
+  uint32_t val;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    mode = IRQ_MODE_TYPE_IRQ;
+
+    // Get trigger mode
+    val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+    if ((val & 2U) != 0U) {
+      // Corresponding interrupt is edge triggered
+      mode |= IRQ_MODE_TRIG_EDGE;
+    } else {
+      // Corresponding interrupt is level triggered
+      mode |= IRQ_MODE_TRIG_LEVEL;
+    }
+
+    // Get interrupt CPU targets
+    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+  } else {
+    mode = IRQ_MODE_ERROR;
+  }
+
+  return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+  IRQn_ID_t irqn;
+  uint32_t prio;
+
+  /* Dummy read to avoid GIC 390 errata 801120 */
+  GIC_GetHighPendingIRQ();
+
+  irqn = GIC_AcknowledgePending();
+
+  __DSB();
+
+  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */
+  /* The following workaround code is for a single-core system.  It would be       */
+  /* different in a multi-core system.                                             */
+  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+  /* so unlock it, otherwise service the interrupt as normal.                      */
+  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */
+  /* so will not occur here.                                                       */
+
+  if ((irqn == 0) || (irqn >= 0x3FE)) {
+    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+    prio = GIC_GetPriority((IRQn_Type)0);
+    GIC_SetPriority ((IRQn_Type)0, prio);
+
+    __DSB();
+
+    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+      /* If the ID is 0, is active and has not been seen before */
+      IRQ_ID0 = 1U;
+    }
+    /* End of Workaround GIC 390 errata 733075 */
+  }
+
+  return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+  return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+  int32_t status;
+  IRQn_Type irq = (IRQn_Type)irqn;
+
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EndInterrupt (irq);
+
+    if (irqn == 0) {
+      IRQ_ID0 = 0U;
+    }
+
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+  uint32_t pending;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+  } else {
+    pending = 0U;
+  }
+
+  return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPriority ((IRQn_Type)irqn, priority);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+  uint32_t priority;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    priority = GIC_GetPriority ((IRQn_Type)irqn);
+  } else {
+    priority = IRQ_PRIORITY_ERROR;
+  }
+
+  return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+  GIC_SetInterfacePriorityMask (priority);
+  return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+  return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+  int32_t status;
+
+  if (bits == IRQ_PRIORITY_Msk) {
+    bits = 7U;
+  }
+
+  if (bits < 8U) {
+    GIC_SetBinaryPoint (7U - bits);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+  uint32_t bp;
+
+  bp = GIC_GetBinaryPoint() & 0x07U;
+
+  return (7U - bp);
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_ca9.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_ca9.h	(revision 373)
+++ 	(revision )
@@ -1,276 +1,0 @@
-/**************************************************************************//**
- * @file     core_ca9.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     25 March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CA9_H_GENERIC
-#define __CORE_CA9_H_GENERIC
-
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_A9
-  @{
- */
-
-/*  CMSIS CA9 definitions */
-#define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \
-                                    __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#include <stdint.h>
-inline uint32_t __get_PSR(void) {
-	__ASM("mrs r0, cpsr");
-}
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-  #define __STATIC_ASM     static __asm
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_caInstr.h"                /*!< Core Instruction Access                         */
-#include "core_caFunc.h"                 /*!< Core Function Access                            */
-#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CA9_H_DEPENDANT
-#define __CORE_CA9_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CA9_REV
-    #define __CA9_REV               0x0000
-    #warning "__CA9_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             1
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    1
-  #endif
-
-  #if __Vendor_SysTickConfig == 0
-    #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_A9 */
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-A processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
-} APSR_Type;
-
-
-/*@} end of group CMSIS_CORE */
-
-/*@} end of CMSIS_Core_FPUFunctions */
-
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-
-
-#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_caFunc.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_caFunc.h	(revision 373)
+++ 	(revision )
@@ -1,1444 +1,0 @@
-/**************************************************************************//**
- * @file     core_caFunc.h
- * @brief    CMSIS Cortex-A Core Function Access Header File
- * @version  V3.10
- * @date     30 Oct 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CAFUNC_H__
-#define __CORE_CAFUNC_H__
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get CPSR Register
-
-    This function returns the content of the CPSR Register.
-
-    \return               CPSR Register value
- */
-__STATIC_INLINE uint32_t __get_CPSR(void)
-{
-  register uint32_t __regCPSR          __ASM("cpsr");
-  return(__regCPSR);
-}
-
-/** \brief  Set Stack Pointer
-
-    This function assigns the given value to the current stack pointer.
-
-    \param [in]    topOfStack  Stack Pointer value to set
- */
-register uint32_t __regSP              __ASM("sp");
-__STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
-    __regSP = topOfStack;
-}
-
-
-/** \brief  Get link register
-
-    This function returns the value of the link register
-
-    \return    Value of link register
- */
-register uint32_t __reglr         __ASM("lr");
-__STATIC_INLINE uint32_t __get_LR(void)
-{
-  return(__reglr);
-}
-
-/** \brief  Set link register
-
-    This function sets the value of the link register
-
-    \param [in]    lr  LR value to set
- */
-__STATIC_INLINE void __set_LR(uint32_t lr)
-{
-  __reglr = lr;
-}
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
-{
-    ARM
-    PRESERVE8
-
-    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
-    MRS     R1, CPSR
-    CPS     #MODE_SYS   ;no effect in USR mode
-    MOV     SP, R0
-    MSR     CPSR_c, R1  ;no effect in USR mode
-    ISB
-    BX      LR
-
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-__STATIC_ASM void __set_CPS_USR(void)
-{
-    ARM 
-
-    CPS  #MODE_USR  
-    BX   LR
-}
-
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-/** \brief  Get FPEXC
-
-    This function returns the current value of the Floating Point Exception Control register.
-
-    \return               Floating Point Exception Control register value
- */
-__STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  return(__regfpexc);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPEXC
-
-    This function assigns the given value to the Floating Point Exception Control register.
-
-    \param [in]    fpscr  Floating Point Exception Control value to set
- */
-__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpexc         __ASM("fpexc");
-  __regfpexc = (fpexc);
-#endif
-}
-
-/** \brief  Get CPACR
-
-    This function returns the current value of the Coprocessor Access Control register.
-
-    \return               Coprocessor Access Control register value
- */
-__STATIC_INLINE uint32_t __get_CPACR(void)
-{
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    return __regCPACR;
-}
-
-/** \brief  Set CPACR
-
-    This function assigns the given value to the Coprocessor Access Control register.
-
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    __regCPACR = cpacr;
-    __ISB();
-}
-
-/** \brief  Get CBAR
-
-    This function returns the value of the Configuration Base Address register.
-
-    \return               Configuration Base Address register value
- */
-__STATIC_INLINE uint32_t __get_CBAR() {
-    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
-    return(__regCBAR);
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__STATIC_INLINE uint32_t __get_TTBR0() {
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    return(__regTTBR0);
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    __regTTBR0 = ttbr0;
-    __ISB();
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__STATIC_INLINE uint32_t __get_DACR() {
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    return(__regDACR);
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    __regDACR = dacr;
-    __ISB();
-}
-
-/******************************** Cache and BTAC enable  ****************************************************/
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    __regSCTLR = sctlr;
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-__STATIC_INLINE uint32_t __get_SCTLR() {
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    return(__regSCTLR);
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-__STATIC_INLINE void __enable_caches(void) {
-    // Set I bit 12 to enable I Cache
-    // Set C bit  2 to enable D Cache
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Disable Caches
-
-    Disable Caches
- */
-__STATIC_INLINE void __disable_caches(void) {
-    // Clear I bit 12 to disable I Cache
-    // Clear C bit  2 to disable D Cache
-    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
-    __ISB();
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-__STATIC_INLINE void __enable_btac(void) {
-    // Set Z bit 11 to enable branch prediction
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Disable BTAC
-
-    Disable BTAC
- */
-__STATIC_INLINE void __disable_btac(void) {
-    // Clear Z bit 11 to disable branch prediction
-    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-__STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/** \brief  Disable MMU
-
-    Disable MMU
- */
-__STATIC_INLINE void __disable_mmu(void) {
-    // Clear M bit 0 to disable the MMU
-    __set_SCTLR( __get_SCTLR() & ~1);
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
-    __TLBIALL = 0;
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-
-__STATIC_INLINE void __v7_inv_btac(void) {
-    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
-    __BPIALL  = 0;
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__STATIC_INLINE void __v7_inv_icache_all(void) {
-    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
-    __ICIALLU = 0;
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief  Clean D$ by MVA
-
-    DCCMVAC. Data cache clean by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
-    __DCCMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Invalidate D$ by MVA
-
-    DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
-    __DCIMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
-    __DCCIMVAC = (uint32_t)va;
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-#pragma push
-#pragma arm
-__STATIC_ASM void __v7_all_cache(uint32_t op) {
-        ARM 
-
-        PUSH    {R4-R11}
-
-        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
-        ANDS    R3, R6, #0x07000000        // Extract coherency level
-        MOV     R3, R3, LSR #23            // Total cache levels << 1
-        BEQ     Finished                   // If 0, no need to clean
-
-        MOV     R10, #0                    // R10 holds current cache level << 1
-Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
-        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
-        AND     R1, R1, #7                 // Isolate those lower 3 bits
-        CMP     R1, #2
-        BLT     Skip                       // No cache or only instruction cache at this level
-
-        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
-        ISB                                // ISB to sync the change to the CacheSizeID reg
-        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
-        AND     R2, R1, #7                 // Extract the line length field
-        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
-        LDR     R4, =0x3FF
-        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
-        CLZ     R5, R4                     // R5 is the bit position of the way size increment
-        LDR     R7, =0x7FFF
-        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
-
-Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
-
-Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
-        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
-        CMP     R0, #0
-        BNE     Dccsw
-        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
-        B       cont
-Dccsw   CMP     R0, #1
-        BNE     Dccisw
-        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
-        B       cont
-Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
-cont    SUBS    R9, R9, #1                 // Decrement the Way number
-        BGE     Loop3
-        SUBS    R7, R7, #1                 // Decrement the Set number
-        BGE     Loop2
-Skip    ADD     R10, R10, #2               // Increment the cache number
-        CMP     R3, R10
-        BGT     Loop1
-
-Finished
-        DSB
-        POP    {R4-R11}
-        BX     lr
-
-}
-#pragma pop
-
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-
-#define __inline inline
-
-inline static uint32_t __disable_irq_iar() {
-  int irq_dis = __get_CPSR() & 0x80;      // 7bit CPSR.I
-  __disable_irq();
-  return irq_dis;
-}
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-// from rt_CMSIS.c
-__arm static inline void __set_PSP(uint32_t topOfProcStack) {
-__asm(
-  "    ARM\n"
-//  "    PRESERVE8\n"
-
-  "    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned \n"
-  "    MRS     R1, CPSR \n"
-  "    CPS     #0x1F   ;no effect in USR mode \n"        // MODE_SYS
-  "    MOV     SP, R0 \n"
-  "    MSR     CPSR_c, R1  ;no effect in USR mode \n"
-  "    ISB \n"
-  "    BX      LR \n");
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-// from rt_CMSIS.c
-__arm static inline void __set_CPS_USR(void) {
-__asm(
-  "    ARM \n"
-
-  "    CPS  #0x10  \n"                  // MODE_USR
-  "    BX   LR\n");
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-    __MCR(15, 0, ttbr0, 2, 0, 0);      // reg to cp15
-    __ISB();
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
-    __MCR(15, 0, dacr, 3, 0, 0);      // reg to cp15
-    __ISB();
-}
-
-
-/******************************** Cache and BTAC enable  ****************************************************/
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-// from __enable_mmu()
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
-    __MCR(15, 0, sctlr, 1, 0, 0);      // reg to cp15
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-// from __enable_mmu()
-__STATIC_INLINE uint32_t __get_SCTLR() {
-	uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
-	return __regSCTLR;
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_caches(void) {
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_btac(void) {
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 8, 7, 0);      // reg to cp15
-    __MCR(15, 0, val, 8, 6, 0);      // reg to cp15
-    __MCR(15, 0, val, 8, 5, 0);      // reg to cp15
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_btac(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 7, 5, 6);      // reg to cp15
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_icache_all(void) {
-	uint32_t val = 0;
-    __MCR(15, 0, val, 7, 5, 0);      // reg to cp15
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-// from __v7_inv_dcache_all()
-__arm static inline void __v7_all_cache(uint32_t op) {
-__asm(
-	"        ARM \n"
-
-	"        PUSH    {R4-R11} \n"
-
-	"        MRC     p15, 1, R6, c0, c0, 1\n"      // Read CLIDR
-	"        ANDS    R3, R6, #0x07000000\n"        // Extract coherency level
-	"        MOV     R3, R3, LSR #23\n"            // Total cache levels << 1
-	"        BEQ     Finished\n"                   // If 0, no need to clean
-
-	"        MOV     R10, #0\n"                    // R10 holds current cache level << 1
-    "Loop1:   ADD     R2, R10, R10, LSR #1\n"       // R2 holds cache "Set" position
-	"        MOV     R1, R6, LSR R2 \n"            // Bottom 3 bits are the Cache-type for this level
-	"        AND     R1, R1, #7 \n"                // Isolate those lower 3 bits
-	"        CMP     R1, #2 \n"
-	"        BLT     Skip \n"                      // No cache or only instruction cache at this level
-
-	"        MCR     p15, 2, R10, c0, c0, 0 \n"    // Write the Cache Size selection register
-	"        ISB \n"                               // ISB to sync the change to the CacheSizeID reg
-	"        MRC     p15, 1, R1, c0, c0, 0 \n"     // Reads current Cache Size ID register
-	"        AND     R2, R1, #7 \n"                // Extract the line length field
-	"        ADD     R2, R2, #4 \n"                // Add 4 for the line length offset (log2 16 bytes)
-	"        movw    R4, #0x3FF \n"
-	"        ANDS    R4, R4, R1, LSR #3 \n"        // R4 is the max number on the way size (right aligned)
-	"        CLZ     R5, R4 \n"                    // R5 is the bit position of the way size increment
-	"        movw    R7, #0x7FFF \n"
-	"        ANDS    R7, R7, R1, LSR #13 \n"       // R7 is the max number of the index size (right aligned)
-
-	"Loop2:   MOV     R9, R4 \n"                    // R9 working copy of the max way size (right aligned)
-
-	"Loop3:   ORR     R11, R10, R9, LSL R5 \n"      // Factor in the Way number and cache number into R11
-	"        ORR     R11, R11, R7, LSL R2 \n"      // Factor in the Set number
-	"        CMP     R0, #0 \n"
-	"        BNE     Dccsw \n"
-	"        MCR     p15, 0, R11, c7, c6, 2 \n"    // DCISW. Invalidate by Set/Way
-	"        B       cont \n"
-	"Dccsw:   CMP     R0, #1 \n"
-	"        BNE     Dccisw \n"
-	"        MCR     p15, 0, R11, c7, c10, 2 \n"   // DCCSW. Clean by Set/Way
-	"        B       cont \n"
-	"Dccisw:  MCR     p15, 0, R11, c7, c14, 2 \n"   // DCCISW, Clean and Invalidate by Set/Way
-	"cont:    SUBS    R9, R9, #1 \n"                // Decrement the Way number
-	"        BGE     Loop3 \n"
-	"        SUBS    R7, R7, #1 \n"                // Decrement the Set number
-	"        BGE     Loop2 \n"
-	"Skip:    ADD     R10, R10, #2 \n"              // increment the cache number
-	"        CMP     R3, R10 \n"
-	"        BGT     Loop1 \n"
-
-	"Finished: \n"
-	"        DSB \n"
-	"        POP    {R4-R11} \n"
-	"        BX     lr \n" );
-}
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-    __MCR(15, 0, (uint32_t)va, 7, 14, 1);
-    __DMB();
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-    __ASM volatile ("cpsie i");
-}
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("mrs %0, cpsr" : "=r" (result));
-    __ASM volatile ("cpsid i");
-    return(result & 0x80);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-#if 1
-  register uint32_t __regAPSR;
-  __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
-#else
-  register uint32_t __regAPSR          __ASM("apsr");
-#endif
-  return(__regAPSR);
-}
-
-
-/** \brief  Get CPSR Register
-
-    This function returns the content of the CPSR Register.
-
-    \return               CPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
-{
-#if 1
-  register uint32_t __regCPSR;
-  __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
-#else
-  register uint32_t __regCPSR          __ASM("cpsr");
-#endif
-  return(__regCPSR);
-}
-
-#if 0
-/** \brief  Set Stack Pointer
-
-    This function assigns the given value to the current stack pointer.
-
-    \param [in]    topOfStack  Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
-    register uint32_t __regSP       __ASM("sp");
-    __regSP = topOfStack;
-}
-#endif
-
-/** \brief  Get link register
-
-    This function returns the value of the link register
-
-    \return    Value of link register
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
-{
-  register uint32_t __reglr         __ASM("lr");
-  return(__reglr);
-}
-
-#if 0
-/** \brief  Set link register
-
-    This function sets the value of the link register
-
-    \param [in]    lr  LR value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
-{
-  register uint32_t __reglr         __ASM("lr");
-  __reglr = lr;
-}
-#endif
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    __asm__ volatile (
-    ".ARM;"
-    ".eabi_attribute Tag_ABI_align8_preserved,1;"
-
-    "BIC     R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
-    "MRS     R1, CPSR;"
-    "CPS     %0;"         /* ;no effect in USR mode */
-    "MOV     SP, R0;"
-    "MSR     CPSR_c, R1;" /* ;no effect in USR mode */
-    "ISB;"
-    //"BX      LR;"
-    :
-    : "i"(MODE_SYS)
-    : "r0", "r1");
-    return;
-}
-
-/** \brief  Set User Mode
-
-    This function changes the processor state to User Mode
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
-{
-    __asm__ volatile (
-    ".ARM;"
-
-    "CPS  %0;"
-    //"BX   LR;"
-    :
-    : "i"(MODE_USR)
-    : );
-    return;
-}
-
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq()                __asm__ volatile ("cpsie f")
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq()               __asm__ volatile ("cpsid f")
-
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
-    uint32_t result;
-
-    __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
-    return (result);
-#else
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#endif
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
-    __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
-#else
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-#endif
-}
-
-/** \brief  Get FPEXC
-
-    This function returns the current value of the Floating Point Exception Control register.
-
-    \return               Floating Point Exception Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
-    uint32_t result;
-
-    __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
-    return (result);
-#else
-  register uint32_t __regfpexc         __ASM("fpexc");
-  return(__regfpexc);
-#endif
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPEXC
-
-    This function assigns the given value to the Floating Point Exception Control register.
-
-    \param [in]    fpscr  Floating Point Exception Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
-    __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
-#else
-  register uint32_t __regfpexc         __ASM("fpexc");
-  __regfpexc = (fpexc);
-#endif
-#endif
-}
-
-/** \brief  Get CPACR
-
-    This function returns the current value of the Coprocessor Access Control register.
-
-    \return               Coprocessor Access Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
-{
-#if 1
-    register uint32_t __regCPACR;
-    __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
-#else
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-#endif
-    return __regCPACR;
-}
-
-/** \brief  Set CPACR
-
-    This function assigns the given value to the Coprocessor Access Control register.
-
-    \param [in]    cpacr  Coprocessor Acccess Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
-#else
-    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
-    __regCPACR = cpacr;
-#endif
-    __ISB();
-}
-
-/** \brief  Get CBAR
-
-    This function returns the value of the Configuration Base Address register.
-
-    \return               Configuration Base Address register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
-#if 1
-    register uint32_t __regCBAR;
-    __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
-#else
-    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
-#endif
-    return(__regCBAR);
-}
-
-/** \brief  Get TTBR0
-
-    This function returns the value of the Translation Table Base Register 0.
-
-    \return               Translation Table Base Register 0 value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
-#if 1
-    register uint32_t __regTTBR0;
-    __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
-#else
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-#endif
-    return(__regTTBR0);
-}
-
-/** \brief  Set TTBR0
-
-    This function assigns the given value to the Translation Table Base Register 0.
-
-    \param [in]    ttbr0  Translation Table Base Register 0 value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
-#else
-    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
-    __regTTBR0 = ttbr0;
-#endif
-    __ISB();
-}
-
-/** \brief  Get DACR
-
-    This function returns the value of the Domain Access Control Register.
-
-    \return               Domain Access Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
-#if 1
-    register uint32_t __regDACR;
-    __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
-#else
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-#endif
-    return(__regDACR);
-}
-
-/** \brief  Set DACR
-
-    This function assigns the given value to the Domain Access Control Register.
-
-    \param [in]    dacr   Domain Access Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
-#else
-    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
-    __regDACR = dacr;
-#endif
-    __ISB();
-}
-
-/******************************** Cache and BTAC enable  ****************************************************/
-
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
-    \param [in]    sctlr  System Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
-#else
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-    __regSCTLR = sctlr;
-#endif
-}
-
-/** \brief  Get SCTLR
-
-    This function returns the value of the System Control Register.
-
-    \return               System Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
-#if 1
-	register uint32_t __regSCTLR;
-	__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
-#else
-    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
-#endif
-    return(__regSCTLR);
-}
-
-/** \brief  Enable Caches
-
-    Enable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
-    // Set I bit 12 to enable I Cache
-    // Set C bit  2 to enable D Cache
-    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief  Disable Caches
-
-    Disable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
-    // Clear I bit 12 to disable I Cache
-    // Clear C bit  2 to disable D Cache
-    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
-    __ISB();
-}
-
-/** \brief  Enable BTAC
-
-    Enable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
-    // Set Z bit 11 to enable branch prediction
-    __set_SCTLR( __get_SCTLR() | (1 << 11));
-    __ISB();
-}
-
-/** \brief  Disable BTAC
-
-    Disable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
-    // Clear Z bit 11 to disable branch prediction
-    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief  Enable MMU
-
-    Enable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
-    // Set M bit 0 to enable the MMU
-    // Set AFE bit to enable simplified access permissions model
-    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
-    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
-    __ISB();
-}
-
-/** \brief  Disable MMU
-
-    Disable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
-    // Clear M bit 0 to disable the MMU
-    __set_SCTLR( __get_SCTLR() & ~1);
-    __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief  Invalidate the whole tlb
-
-    TLBIALL. Invalidate the whole tlb
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
-#else
-    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
-    __TLBIALL = 0;
-#endif
-    __DSB();
-    __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief  Invalidate entire branch predictor array
-
-    BPIALL. Branch Predictor Invalidate All.
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-#else
-    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
-    __BPIALL  = 0;
-#endif
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief  Invalidate the whole I$
-
-    ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
-#if 1
-	__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-#else
-    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
-    __ICIALLU = 0;
-#endif
-    __DSB();     //ensure completion of the invalidation
-    __ISB();     //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief  Clean D$ by MVA
-
-    DCCMVAC. Data cache clean by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
-    __DCCMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Invalidate D$ by MVA
-
-    DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
-    __DCIMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate D$ by MVA
-
-    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-#if 1
-    __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
-#else
-    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
-    __DCCIMVAC = (uint32_t)va;
-#endif
-    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief  Clean and Invalidate the entire data or unified cache
-
-    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-extern void __v7_all_cache(uint32_t op);
-
-
-/** \brief  Invalidate the whole D$
-
-    DCISW. Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
-    __v7_all_cache(0);
-}
-
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
-    __v7_all_cache(1);
-}
-
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
-    __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-
-#error TASKING Compiler support not implemented for Cortex-A
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CAFUNC_H__ */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_caInstr.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_caInstr.h	(revision 373)
+++ 	(revision )
@@ -1,45 +1,0 @@
-/**************************************************************************//**
- * @file     core_caInstr.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     04. December 2012
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#ifndef __CORE_CAINSTR_H__
-#define __CORE_CAINSTR_H__
-
-#define __CORTEX_M 0x3
-#include "core_cmInstr.h"
-#undef  __CORTEX_M
-
-#endif
-
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_ca_mmu.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_ca_mmu.h	(revision 373)
+++ 	(revision )
@@ -1,847 +1,0 @@
-;/**************************************************************************//**
-; * @file     core_ca_mmu.h
-; * @brief    MMU Startup File for A9_MP Device Series
-; * @version  V1.01
-; * @date     10 Sept 2014
-; *
-; * @note
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2012-2014 ARM LIMITED
-;
-;   All rights reserved.
-;   Redistribution and use in source and binary forms, with or without
-;   modification, are permitted provided that the following conditions are met:
-;   - Redistributions of source code must retain the above copyright
-;     notice, this list of conditions and the following disclaimer.
-;   - Redistributions in binary form must reproduce the above copyright
-;     notice, this list of conditions and the following disclaimer in the
-;     documentation and/or other materials provided with the distribution.
-;   - Neither the name of ARM nor the names of its contributors may be used
-;     to endorse or promote products derived from this software without
-;     specific prior written permission.
-;   *
-;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;   POSSIBILITY OF SUCH DAMAGE.
-;   ---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef _MMU_FUNC_H
-#define _MMU_FUNC_H
-
-#define SECTION_DESCRIPTOR      (0x2)
-#define SECTION_MASK            (0xFFFFFFFC)
-
-#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
-#define SECTION_B_SHIFT         (2)
-#define SECTION_C_SHIFT         (3)
-#define SECTION_TEX0_SHIFT      (12)
-#define SECTION_TEX1_SHIFT      (13)
-#define SECTION_TEX2_SHIFT      (14)
-
-#define SECTION_XN_MASK         (0xFFFFFFEF)
-#define SECTION_XN_SHIFT        (4)
-
-#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
-#define SECTION_DOMAIN_SHIFT    (5)
-
-#define SECTION_P_MASK          (0xFFFFFDFF)
-#define SECTION_P_SHIFT         (9)
-
-#define SECTION_AP_MASK         (0xFFFF73FF)
-#define SECTION_AP_SHIFT        (10)
-#define SECTION_AP2_SHIFT       (15)
-
-#define SECTION_S_MASK          (0xFFFEFFFF)
-#define SECTION_S_SHIFT         (16)
-
-#define SECTION_NG_MASK         (0xFFFDFFFF)
-#define SECTION_NG_SHIFT        (17)
-
-#define SECTION_NS_MASK         (0xFFF7FFFF)
-#define SECTION_NS_SHIFT        (19)
-
-
-#define PAGE_L1_DESCRIPTOR      (0x1)
-#define PAGE_L1_MASK            (0xFFFFFFFC)
-
-#define PAGE_L2_4K_DESC         (0x2)
-#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
-
-#define PAGE_L2_64K_DESC        (0x1)
-#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
-
-#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
-#define PAGE_4K_B_SHIFT         (2)
-#define PAGE_4K_C_SHIFT         (3)
-#define PAGE_4K_TEX0_SHIFT      (6)
-#define PAGE_4K_TEX1_SHIFT      (7)
-#define PAGE_4K_TEX2_SHIFT      (8)
-
-#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
-#define PAGE_64K_B_SHIFT        (2)
-#define PAGE_64K_C_SHIFT        (3)
-#define PAGE_64K_TEX0_SHIFT     (12)
-#define PAGE_64K_TEX1_SHIFT     (13)
-#define PAGE_64K_TEX2_SHIFT     (14)
-
-#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
-#define PAGE_B_SHIFT            (2)
-#define PAGE_C_SHIFT            (3)
-#define PAGE_TEX_SHIFT          (12)
-
-#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
-#define PAGE_XN_4K_SHIFT        (0)
-#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
-#define PAGE_XN_64K_SHIFT       (15)
-
-
-#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
-#define PAGE_DOMAIN_SHIFT       (5)
-
-#define PAGE_P_MASK             (0xFFFFFDFF)
-#define PAGE_P_SHIFT            (9)
-
-#define PAGE_AP_MASK            (0xFFFFFDCF)
-#define PAGE_AP_SHIFT           (4)
-#define PAGE_AP2_SHIFT          (9)
-
-#define PAGE_S_MASK             (0xFFFFFBFF)
-#define PAGE_S_SHIFT            (10)
-
-#define PAGE_NG_MASK            (0xFFFFF7FF)
-#define PAGE_NG_SHIFT           (11)
-
-#define PAGE_NS_MASK            (0xFFFFFFF7)
-#define PAGE_NS_SHIFT           (3)
-
-#define OFFSET_1M               (0x00100000)
-#define OFFSET_64K              (0x00010000)
-#define OFFSET_4K               (0x00001000)
-
-#define DESCRIPTOR_FAULT        (0x00000000)
-
-/* ###########################  MMU Function Access  ########################### */
-/** \ingroup  MMU_FunctionInterface
-    \defgroup MMU_Functions MMU Functions Interface
-  @{
- */
-
-/* Attributes enumerations */
-
-/* Region size attributes */
-typedef enum
-{
-   SECTION,
-   PAGE_4k,
-   PAGE_64k,
-} mmu_region_size_Type;
-
-/* Region type attributes */
-typedef enum
-{
-   NORMAL,
-   DEVICE,
-   SHARED_DEVICE,
-   NON_SHARED_DEVICE,
-   STRONGLY_ORDERED
-} mmu_memory_Type;
-
-/* Region cacheability attributes */
-typedef enum
-{
-   NON_CACHEABLE,
-   WB_WA,
-   WT,
-   WB_NO_WA,
-} mmu_cacheability_Type;
-
-/* Region parity check attributes */
-typedef enum
-{
-   ECC_DISABLED,
-   ECC_ENABLED,
-} mmu_ecc_check_Type;
-
-/* Region execution attributes */
-typedef enum
-{
-   EXECUTE,
-   NON_EXECUTE,
-} mmu_execute_Type;
-
-/* Region global attributes */
-typedef enum
-{
-   GLOBAL,
-   NON_GLOBAL,
-} mmu_global_Type;
-
-/* Region shareability attributes */
-typedef enum
-{
-   NON_SHARED,
-   SHARED,
-} mmu_shared_Type;
-
-/* Region security attributes */
-typedef enum
-{
-   SECURE,
-   NON_SECURE,
-} mmu_secure_Type;
-
-/* Region access attributes */
-typedef enum
-{
-   NO_ACCESS,
-   RW,
-   READ,
-} mmu_access_Type;
-
-/* Memory Region definition */
-typedef struct RegionStruct {
-    mmu_region_size_Type rg_t;
-    mmu_memory_Type mem_t;
-    uint8_t domain;
-    mmu_cacheability_Type inner_norm_t;
-    mmu_cacheability_Type outer_norm_t;
-    mmu_ecc_check_Type e_t;
-    mmu_execute_Type xn_t;
-    mmu_global_Type g_t;
-    mmu_secure_Type sec_t;
-    mmu_access_Type priv_t;
-    mmu_access_Type user_t;
-    mmu_shared_Type sh_t;
-
-} mmu_region_attributes_Type;
-
-/** \brief  Set section execution-never attribute
-
-    The function sets section execution-never attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
-
-    \return          0  
- */
-__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
-{
-    *descriptor_l1 &= SECTION_XN_MASK;
-    *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section domain
-
-    The function sets section domain
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]            domain  Section domain
-
-    \return          0  
- */
-__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
-{
-    *descriptor_l1 &= SECTION_DOMAIN_MASK;
-    *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section parity check
-
-    The function sets section parity check
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-    \return          0  
- */
-__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-    *descriptor_l1 &= SECTION_P_MASK;
-    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section access privileges
-
-    The function sets section access privileges
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-    \param [in]               afe  Access flag enable
-
-    \return          0  
- */
-__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
-{
-    uint32_t ap = 0;
-
-    if (afe == 0) { //full access
-        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    else { //Simplified access
-        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    *descriptor_l1 &= SECTION_AP_MASK;
-    *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
-    *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
-
-    return 0;
-}
-
-/** \brief  Set section shareability
-
-    The function sets section shareability
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
-
-    \return          0  
- */
-__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
-{
-    *descriptor_l1 &= SECTION_S_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section Global attribute
-
-    The function sets section Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
-
-    \return          0  
- */
-__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
-{
-    *descriptor_l1 &= SECTION_NG_MASK;
-    *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
-    return 0;
-}
-
-/** \brief  Set section Security attribute
-
-    The function sets section Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
-
-    \return          0  
- */
-__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-    *descriptor_l1 &= SECTION_NS_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
-    return 0;
-}
-
-/* Page 4k or 64k */
-/** \brief  Set 4k/64k page execution-never attribute
-
-    The function sets 4k/64k page execution-never attribute
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
-    \param [in]              page  Page size: PAGE_4k, PAGE_64k,
-   
-    \return          0  
- */
-__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
-{
-    if (page == PAGE_4k)
-    {
-        *descriptor_l2 &= PAGE_XN_4K_MASK;
-        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
-    }
-    else
-    {
-        *descriptor_l2 &= PAGE_XN_64K_MASK;
-        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
-    }
-    return 0;
-}
-
-/** \brief  Set 4k/64k page domain
-
-    The function sets 4k/64k page domain
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]            domain  Page domain
-
-    \return          0  
- */
-__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
-{
-    *descriptor_l1 &= PAGE_DOMAIN_MASK;
-    *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page parity check
-
-    The function sets 4k/64k page parity check
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
-    \return          0  
- */
-__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
-    *descriptor_l1 &= SECTION_P_MASK;
-    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page access privileges
-
-    The function sets 4k/64k page access privileges
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
-    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
-    \param [in]               afe  Access flag enable
-
-    \return          0  
- */
-__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
-{
-    uint32_t ap = 0;
-
-    if (afe == 0) { //full access
-        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
-        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
-        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x6; }
-    }
-
-    else { //Simplified access
-        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
-        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
-        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
-        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
-    }
-
-    *descriptor_l2 &= PAGE_AP_MASK;
-    *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
-    *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
-
-    return 0;
-}
-
-/** \brief  Set 4k/64k page shareability
-
-    The function sets 4k/64k page shareability
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
-
-    \return          0  
- */
-__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
-{
-    *descriptor_l2 &= PAGE_S_MASK;
-    *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page Global attribute
-
-    The function sets 4k/64k page Global attribute
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
-
-    \return          0  
- */
-__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
-{
-    *descriptor_l2 &= PAGE_NG_MASK;
-    *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
-    return 0;
-}
-
-/** \brief  Set 4k/64k page Security attribute
-
-    The function sets 4k/64k page Global attribute
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
-
-    \return          0  
- */
-__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
-    *descriptor_l1 &= PAGE_NS_MASK;
-    *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
-    return 0;
-}
-
-
-/** \brief  Set Section memory attributes
-
-    The function sets section memory attributes
-
-    \param [out]    descriptor_l1  L1 descriptor.
-    \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
-    \return          0  
- */
-__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
-{
-    *descriptor_l1 &= SECTION_TEXCB_MASK;
-
-    if (STRONGLY_ORDERED == mem)
-    {
-        return 0;
-    }
-    else if (SHARED_DEVICE == mem)
-    {
-        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-    }
-    else if (NON_SHARED_DEVICE == mem)
-    {
-        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
-    }
-    else if (NORMAL == mem)
-    {
-           *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
-           switch(inner)
-           {
-            case NON_CACHEABLE:
-            break;
-            case WB_WA:
-                *descriptor_l1 |= (1 << SECTION_B_SHIFT);
-                break;
-            case WT:
-                *descriptor_l1 |= 1 << SECTION_C_SHIFT;
-                break;
-            case WB_NO_WA:
-                *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
-                break;
-        }
-        switch(outer)
-        {
-            case NON_CACHEABLE:
-             break;
-            case WB_WA:
-                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
-                break;
-            case WT:
-                *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
-                break;
-            case WB_NO_WA:
-                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
-                break;
-        }
-    }
-
-    return 0;
-}
-
-/** \brief  Set 4k/64k page memory attributes
-
-    The function sets 4k/64k page memory attributes
-
-    \param [out]    descriptor_l2  L2 descriptor.
-    \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
-    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
-    \return          0  
- */
-__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
-{
-    *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
-
-    if (page == PAGE_64k)
-    {
-        //same as section
-        __memory_section(descriptor_l2, mem, outer, inner);
-    }
-    else
-    {
-        if (STRONGLY_ORDERED == mem)
-        {
-            return 0;
-        }
-        else if (SHARED_DEVICE == mem)
-        {
-            *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-        }
-        else if (NON_SHARED_DEVICE == mem)
-        {
-             *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
-        }
-        else if (NORMAL == mem)
-        {
-            *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
-            switch(inner)
-            {
-                case NON_CACHEABLE:
-                break;
-                case WB_WA:
-                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
-                     break;
-                case WT:
-                    *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
-                     break;
-                case WB_NO_WA:
-                    *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
-                    break;
-            }
-            switch(outer)
-            {
-                case NON_CACHEABLE:
-                break;
-                case WB_WA:
-                      *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
-                    break;
-                case WT:
-                     *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
-                    break;
-                case WB_NO_WA:
-                    *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
-                    break;
-            }
-        }
-    }
-
-    return 0;
-}
-
-/** \brief  Create a L1 section descriptor
-
-    The function creates a section descriptor.
-    
-    Assumptions:
-    - 16MB super sections not supported
-    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
-    - Functions always return 0
-
-    \param [out]       descriptor  L1 descriptor
-    \param [out]      descriptor2  L2 descriptor
-    \param [in]               reg  Section attributes
-
-    \return          0  
- */
-__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
-{
-    *descriptor  = 0;
-
-   __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
-   __xn_section(descriptor,reg.xn_t);
-   __domain_section(descriptor, reg.domain);
-   __p_section(descriptor, reg.e_t);
-   __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
-   __shared_section(descriptor,reg.sh_t);
-   __global_section(descriptor,reg.g_t);
-   __secure_section(descriptor,reg.sec_t);
-   *descriptor &= SECTION_MASK;
-   *descriptor |= SECTION_DESCRIPTOR;
-
-   return 0;
-
-}
-
-
-/** \brief  Create a L1 and L2 4k/64k page descriptor
-
-    The function creates a 4k/64k page descriptor.
-    Assumptions:
-    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
-    - Functions always return 0
-
-    \param [out]       descriptor  L1 descriptor
-    \param [out]      descriptor2  L2 descriptor
-    \param [in]               reg  4k/64k page attributes
-
-    \return          0  
- */
-__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
-{
-    *descriptor  = 0;
-    *descriptor2 = 0;
-
-    switch (reg.rg_t)
-    {
-        case PAGE_4k:
-            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
-            __xn_page(descriptor2, reg.xn_t, PAGE_4k);
-            __domain_page(descriptor, reg.domain);
-            __p_page(descriptor, reg.e_t);
-            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
-            __shared_page(descriptor2,reg.sh_t);
-            __global_page(descriptor2,reg.g_t);
-            __secure_page(descriptor,reg.sec_t);
-            *descriptor &= PAGE_L1_MASK;
-            *descriptor |= PAGE_L1_DESCRIPTOR;
-            *descriptor2 &= PAGE_L2_4K_MASK;
-            *descriptor2 |= PAGE_L2_4K_DESC;
-            break;
-
-        case PAGE_64k:
-            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
-            __xn_page(descriptor2, reg.xn_t, PAGE_64k);
-            __domain_page(descriptor, reg.domain);
-            __p_page(descriptor, reg.e_t);
-            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
-            __shared_page(descriptor2,reg.sh_t);
-            __global_page(descriptor2,reg.g_t);
-            __secure_page(descriptor,reg.sec_t);
-            *descriptor &= PAGE_L1_MASK;
-            *descriptor |= PAGE_L1_DESCRIPTOR;
-            *descriptor2 &= PAGE_L2_64K_MASK;
-            *descriptor2 |= PAGE_L2_64K_DESC;
-            break;
-
-        case SECTION:
-            //error
-            break;    
-
-    }
-
-   return 0;
-
-}
-
-/** \brief  Create a 1MB Section
-
-    \param [in]               ttb  Translation table base address
-    \param [in]      base_address  Section base address
-    \param [in]             count  Number of sections to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
-{
-    uint32_t offset;
-    uint32_t entry;
-    uint32_t i;
-
-    offset = base_address >> 20;
-    entry  = (base_address & 0xFFF00000) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb = ttb + offset;
-
-    for (i = 0; i < count; i++ )
-    {
-        //4 bytes aligned
-       *ttb++ = entry;
-       entry += OFFSET_1M;
-    }
-}
-
-/** \brief  Create a 4k page entry
-
-    \param [in]               ttb  L1 table base address
-    \param [in]      base_address  4k base address
-    \param [in]             count  Number of 4k pages to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-    \param [in]            ttb_l2  L2 table base address
-    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-
-    uint32_t offset, offset2;
-    uint32_t entry, entry2;
-    uint32_t i;
-
-
-    offset = base_address >> 20;
-    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb += offset;
-    //create l1_entry
-    *ttb = entry;
-
-    offset2 = (base_address & 0xff000) >> 12;
-    ttb_l2 += offset2;
-    entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
-    for (i = 0; i < count; i++ )
-    {
-        //4 bytes aligned
-       *ttb_l2++ = entry2;
-       entry2 += OFFSET_4K;
-    }
-}
-
-/** \brief  Create a 64k page entry
-
-    \param [in]               ttb  L1 table base address
-    \param [in]      base_address  64k base address
-    \param [in]             count  Number of 64k pages to create
-    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
-    \param [in]            ttb_l2  L2 table base address
-    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
-
- */
-__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-    uint32_t offset, offset2;
-    uint32_t entry, entry2;
-    uint32_t i,j;
-
-
-    offset = base_address >> 20;
-    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
-    //4 bytes aligned
-    ttb += offset;
-    //create l1_entry
-    *ttb = entry;
-
-    offset2 = (base_address & 0xff000) >> 12;
-    ttb_l2 += offset2;
-    entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
-    for (i = 0; i < count; i++ )
-    {
-        //create 16 entries
-        for (j = 0; j < 16; j++)
-            //4 bytes aligned
-            *ttb_l2++ = entry2;
-        entry2 += OFFSET_64K;
-    }
-}
-
-/*@} end of MMU_Functions */
-#endif
-
-#ifdef __cplusplus
-}
-#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm0.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm0.h	(revision 373)
+++ 	(revision )
@@ -1,750 +1,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-#ifdef __cplusplus
-  #define   __IM    volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __IM    volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __OM    volatile             /*!< Defines 'write only' permissions                */
-#define     __IOM   volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  __DSB();
-  __ISB();
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm0plus.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm0plus.h	(revision 373)
+++ 	(revision )
@@ -1,864 +1,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-#ifdef __cplusplus
-  #define   __IM    volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __IM    volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __OM    volatile             /*!< Defines 'write only' permissions                */
-#define     __IOM   volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-#else
-       uint32_t RESERVED0;
-#endif
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  __DSB();
-  __ISB();
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm3.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm3.h	(revision 373)
+++ 	(revision )
@@ -1,1732 +1,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-#ifdef __cplusplus
-  #define   __IM    volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __IM    volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __OM    volatile             /*!< Defines 'write only' permissions                */
-#define     __IOM   volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* CMSIS_VECTAB_VIRTUAL */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  __DSB();
-  __ISB();
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm4.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm4.h	(revision 373)
+++ 	(revision )
@@ -1,1898 +1,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-#ifdef __cplusplus
-  #define   __IM    volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __IM    volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __OM    volatile             /*!< Defines 'write only' permissions                */
-#define     __IOM   volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* CMSIS_VECTAB_VIRTUAL */
-
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  __DSB();
-  __ISB();
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm4_simd.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm4_simd.h	(revision 373)
+++ 	(revision )
@@ -1,673 +1,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm7.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm7.h	(revision 373)
+++ 	(revision )
@@ -1,2407 +1,0 @@
-/**************************************************************************//**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M7
-  @{
- */
-
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM7_REV
-    #define __CM7_REV               0x0000
-    #warning "__CM7_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ICACHE_PRESENT
-    #define __ICACHE_PRESENT          0
-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DCACHE_PRESENT
-    #define __DCACHE_PRESENT          0
-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DTCM_PRESENT
-    #define __DTCM_PRESENT            0
-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-#ifdef __cplusplus
-  #define   __IM    volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __IM    volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __OM    volatile             /*!< Defines 'write only' permissions                */
-#define     __IOM   volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[1];
-  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
-  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
-  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
-  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-       uint32_t RESERVED3[93];
-  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
-       uint32_t RESERVED4[15];
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
-  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
-       uint32_t RESERVED5[1];
-  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
-       uint32_t RESERVED6[1];
-  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
-  __O  uint32_t DCIMVAC;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
-  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
-  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
-  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
-  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
-  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
-  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
-       uint32_t RESERVED7[6];
-  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
-  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
-  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
-  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
-  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
-       uint32_t RESERVED8[1];
-  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* Cache Level ID register */
-#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
-
-/* Cache Type register */
-#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* Cache Size ID Register */
-#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* Cache Size Selection Register */
-#define SCB_CSSELR_LEVEL_Pos                1                                             /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register */
-#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register*/
-#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Registers */
-#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register */
-#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register */
-#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS control register */
-#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register */
-#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-       uint32_t RESERVED3[981];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  __DSB();
-  __ISB();
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if((int32_t)IRQn < 0) {
-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_FpuFunctions FPU Functions
-    \brief      Function that provides FPU type.
-    @{
- */
-
-/**
-  \fn          uint32_t SCB_GetFPUType(void)
-  \brief       get FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = SCB->MVFR0;
-  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
-    return 2UL;           // Double + Single precision FPU
-  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
-    return 1UL;           // Single precision FPU
-  } else {
-    return 0UL;           // No FPU
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################  Cache functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_CacheFunctions Cache Functions
-    \brief      Functions that configure Instruction and Data cache.
-    @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
-
-
-/** \brief Enable I-Cache
-
-    The function turns on I-Cache
-  */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
-  #if (__ICACHE_PRESENT == 1)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  // enable I-Cache
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Disable I-Cache
-
-    The function turns off I-Cache
-  */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
-  #if (__ICACHE_PRESENT == 1)
-    __DSB();
-    __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  // disable I-Cache
-    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Invalidate I-Cache
-
-    The function invalidates I-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
-  #if (__ICACHE_PRESENT == 1)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Enable D-Cache
-
-    The function turns on D-Cache
-  */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                   // invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-    __DSB();
-
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;   // enable D-Cache
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Disable D-Cache
-
-    The function turns off D-Cache
-  */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  // disable D-Cache
-
-    do {                                    // clean & invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Invalidate D-Cache
-
-    The function invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                    // invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Clean D-Cache
-
-    The function cleans D-Cache
-  */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                    // clean D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCSW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/** \brief Clean & Invalidate D-Cache
-
-    The function cleans and Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                    // clean & invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \fn          void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Invalidate by address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
-    uint32_t op_addr = (uint32_t)addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCIMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \fn          void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Clean by address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \fn          void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Clean and Invalidate by address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCIMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cmFunc.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cmFunc.h	(revision 373)
+++ 	(revision )
@@ -1,664 +1,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-    or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-	or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  __ASM volatile ("");
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
-  __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cmInstr.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cmInstr.h	(revision 373)
+++ 	(revision )
@@ -1,916 +1,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-  return(result);
-}
-#endif
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-#endif
-  return(result);
-}
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cmSimd.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cmSimd.h	(revision 373)
+++ 	(revision )
@@ -1,697 +1,0 @@
-/**************************************************************************//**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/mbed_cmsis_conf.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/mbed_cmsis_conf.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/mbed_cmsis_conf.h	(revision 374)
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_CMSIS_CONF_H
+#define MBED_CMSIS_CONF_H
+
+#ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE
+#define MBED_CONF_TZ_PROCESS_STACK_SIZE  512
+#endif
+#ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS
+#define MBED_CONF_TZ_PROCESS_STACK_SLOTS  8
+#endif
+
+#define TZ_PROCESS_STACK_SLOTS  MBED_CONF_TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SIZE  MBED_CONF_TZ_PROCESS_STACK_SIZE
+
+#endif /* MBED_CMSIS_CONF_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/can_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/can_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/can_api.h	(revision 374)
@@ -59,4 +59,5 @@
 
 void          can_init     (can_t *obj, PinName rd, PinName td);
+void          can_init_freq(can_t *obj, PinName rd, PinName td, int hz);
 void          can_free     (can_t *obj);
 int           can_frequency(can_t *obj, int hz);
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/can_helper.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/can_helper.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/can_helper.h	(revision 374)
@@ -26,4 +26,10 @@
 #endif
 
+/**
+ *
+ * \enum    CANFormat
+ *
+ * \brief   Values that represent CAN Format
+**/
 enum CANFormat {
     CANStandard = 0,
@@ -33,4 +39,10 @@
 typedef enum CANFormat CANFormat;
 
+/**
+ *
+ * \enum    CANType
+ *
+ * \brief   Values that represent CAN Type
+**/
 enum CANType {
     CANData   = 0,
@@ -39,10 +51,17 @@
 typedef enum CANType CANType;
 
+/**
+ *
+ * \struct  CAN_Message
+ *
+ * \brief   Holder for single CAN message.
+ *
+**/
 struct CAN_Message {
     unsigned int   id;                 // 29 bit identifier
     unsigned char  data[8];            // Data field
     unsigned char  len;                // Length of data field in bytes
-    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
-    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
+    CANFormat      format;             // Format ::CANFormat
+    CANType        type;               // Type ::CANType
 };
 typedef struct CAN_Message CAN_Message;
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/critical_section_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/critical_section_api.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/critical_section_api.h	(revision 374)
@@ -0,0 +1,107 @@
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CRITICAL_SECTION_API_H
+#define MBED_CRITICAL_SECTION_API_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_critical Critical Section HAL functions
+ * @{
+ */
+
+/**
+ * Mark the start of a critical section
+ *
+ * This function will be called by core_util_critical_section_enter() each time
+ * the application requests to enter a critical section. The purpose of the
+ * critical section is to ensure mutual-exclusion synchronisation of the
+ * processor by preventing any change in processor control, the default
+ * behaviour requires storing the state of interrupts in the system before
+ * disabling them.
+ *
+ * The critical section code supports nesting. When a thread has entered a
+ * critical section it can make additional calls to
+ * core_util_critical_section_enter() without deadlocking itself. The critical
+ * section driver API tracks the number of nested calls to the critical section.
+ * The critical section will only be exited when
+ * core_util_critical_section_exit() has been called once for each time it
+ * entered the critical section.
+ *
+ * On the first call to enter a critical section this function MUST store the
+ * state of any interrupts or other application settings it will modify to
+ * facilitate the critical section.
+ *
+ * Each successive call to enter the critical section MUST ignore storing or
+ * modifying any application state.
+ *
+ * The default implementation of this function which will save the current state
+ * of interrupts before disabling them. This implementation can be found in
+ * mbed_critical_section_api.c. This behaviour is can be overridden on a per
+ * platform basis by providing a different implementation within the correct
+ * targets directory.
+ */
+void hal_critical_section_enter(void);
+
+
+/** Mark the end of a critical section.
+ *
+ * The purpose of this function is to restore any state that was modified upon
+ * entering the critical section, allowing other threads or interrupts to change
+ * the processor control.
+ *
+ * This function will be called once by core_util_critical_section_exit() per
+ * critical section on last call to exit. When called, the application MUST
+ * restore the saved interrupt/application state that was saved when entering
+ * the critical section.
+ *
+ * There is a default implementation of this function, it will restore the state
+ * of interrupts that were previously saved when hal_critical_section_enter was
+ * first called, this implementation can be found in
+ * mbed_critical_section_api.c. This behaviour is overridable by providing a
+ * different function implementation within the correct targets directory.
+ */
+void hal_critical_section_exit(void);
+
+
+/** Determine if the application is currently running in a critical section
+ *
+ * The purpose of this function is to inform the caller whether or not the
+ * application is running in a critical section. This is done by checking if
+ * the current interrupt state has been saved in the underlying implementation,
+ * this could also be done by checking the state of the interrupts at the time
+ * of calling.
+ *
+ *  @return  True if running in a critical section, false if not.
+ */
+bool hal_in_critical_section(void);
+
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MBED_CRITICAL_SECTION_API_H
+
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/ethernet_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/ethernet_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/ethernet_api.h	(revision 374)
@@ -45,5 +45,5 @@
 int ethernet_send(void);
 
-// recieve from ethernet buffer, returning packet size, or 0 if no packet
+// receive from ethernet buffer, returning packet size, or 0 if no packet
 int ethernet_receive(void);
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/flash_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/flash_api.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/flash_api.h	(revision 374)
@@ -0,0 +1,130 @@
+/** \addtogroup hal */
+/** @{*/
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FLASH_API_H
+#define MBED_FLASH_API_H
+
+#include "device.h"
+#include <stdint.h>
+
+#if DEVICE_FLASH
+
+#define MBED_FLASH_INVALID_SIZE     0xFFFFFFFF
+
+typedef struct flash_s flash_t;
+
+#if TARGET_FLASH_CMSIS_ALGO
+#include "flash_data.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup flash_hal Flash HAL API
+ * @{
+ */
+
+/** Initialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_init(flash_t *obj);
+
+/** Uninitialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_free(flash_t *obj);
+
+/** Erase one sector starting at defined address
+ *
+ * The address should be at sector boundary. This function does not do any check for address alignments
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_erase_sector(flash_t *obj, uint32_t address);
+
+/** Read data starting at defined address
+ *
+ * This function has a WEAK implementation using memcpy for backwards compatibility.
+ * @param obj The flash object
+ * @param address Address to begin reading from
+ * @param data The buffer to read data into
+ * @param size The number of bytes to read
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size);
+
+/** Program pages starting at defined address
+ *
+ * The pages should not cross multiple sectors.
+ * This function does not do any check for address alignments or if size is aligned to a page size.
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @param data The data buffer to be programmed
+ * @param size The number of bytes to program
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size);
+
+/** Get sector size
+ *
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return The size of a sector
+ */
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
+
+/** Get page size
+ *
+ * The page size defines the writable page size
+ * @param obj The flash object
+ * @return The size of a page
+ */
+uint32_t flash_get_page_size(const flash_t *obj);
+
+/** Get start address for the flash region
+ *
+ * @param obj The flash object
+ * @return The start address for the flash region
+ */
+uint32_t flash_get_start_address(const flash_t *obj);
+
+/** Get the flash region size
+ *
+ * @param obj The flash object
+ * @return The flash region size
+ */
+uint32_t flash_get_size(const flash_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/gpio_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/gpio_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/gpio_api.h	(revision 374)
@@ -84,5 +84,5 @@
 /** Init the input pin and set mode to PullDefault
  *
- * @param obj The GPIO object
+ * @param gpio The GPIO object
  * @param pin The pin name
  */
@@ -91,5 +91,5 @@
 /** Init the input pin and set the mode
  *
- * @param obj  The GPIO object
+ * @param gpio  The GPIO object
  * @param pin  The pin name
  * @param mode The pin mode to be set
@@ -99,5 +99,5 @@
 /** Init the output pin as an output, with predefined output value 0
  *
- * @param obj The GPIO object
+ * @param gpio The GPIO object
  * @param pin The pin name
  * @return An integer value 1 or 0
@@ -107,5 +107,5 @@
 /** Init the pin as an output and set the output value
  *
- * @param obj   The GPIO object
+ * @param gpio  The GPIO object
  * @param pin   The pin name
  * @param value The value to be set
@@ -115,5 +115,5 @@
 /** Init the pin to be in/out
  *
- * @param obj       The GPIO object
+ * @param gpio      The GPIO object
  * @param pin       The pin name
  * @param direction The pin direction to be set
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/i2c_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/i2c_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/i2c_api.h	(revision 374)
@@ -157,4 +157,5 @@
 /** Configure I2C as slave or master.
  *  @param obj The I2C object
+ *  @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive
  *  @return non-zero if a value is available
  */
@@ -170,4 +171,6 @@
 /** Configure I2C as slave or master.
  *  @param obj The I2C object
+ *  @param data    The buffer for receiving
+ *  @param length  Number of bytes to read
  *  @return non-zero if a value is available
  */
@@ -176,4 +179,6 @@
 /** Configure I2C as slave or master.
  *  @param obj The I2C object
+ *  @param data    The buffer for sending
+ *  @param length  Number of bytes to write
  *  @return non-zero if a value is available
  */
@@ -209,4 +214,5 @@
  *  @param stop      If true, stop will be generated after the transfer is done
  *  @param handler   The I2C IRQ handler to be set
+ *  @param event     Event mask for the transfer. See \ref hal_I2CEvents
  *  @param hint      DMA hint usage
  */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/lp_ticker_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/lp_ticker_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/lp_ticker_api.h	(revision 374)
@@ -22,5 +22,5 @@
 #include "device.h"
 
-#if DEVICE_LOWPOWERTIMER
+#if DEVICE_LPTICKER
 
 #include "hal/ticker_api.h"
@@ -31,13 +31,54 @@
 
 /**
- * \defgroup hal_LpTicker Low Power Ticker Functions
+ * \defgroup hal_lp_ticker Low Power Ticker
+ * Low level interface to the low power ticker of a target
+ *
+ * # Defined behavior
+ * * Has a reported frequency between 4KHz and 64KHz - verified by ::lp_ticker_info_test
+ * * Has a counter that is at least 12 bits wide - verified by ::lp_ticker_info_test
+ * * Continues operating in deep sleep mode - verified by ::lp_ticker_deepsleep_test
+ * * All behavior defined by the @ref hal_ticker_shared "ticker specification"
+ *
+ * # Undefined behavior
+ * * See the @ref hal_ticker_shared "ticker specification"
+ * * Calling any function other than lp_ticker_init after calling lp_ticker_free
+ *
+ * # Potential bugs
+ * * Glitches due to ripple counter - Verified by ::lp_ticker_glitch_test
+ *
+ * @see hal_lp_ticker_tests
+ *
  * @{
  */
 
+/**
+ * \defgroup hal_lp_ticker_tests Low Power Ticker tests
+ * Tests to validate the proper implementation of the low power ticker
+ *
+ * To run the low power ticker hal tests use the command:
+ *
+ *     mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*,tests-mbed_hal-lp_ticker*
+ *
+ */
+
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/** Set low power ticker IRQ handler
+ *
+ * @param ticker_irq_handler IRQ handler to be connected
+ *
+ * @return previous ticker IRQ handler
+ *
+ * @note by default IRQ handler is set to ::ticker_irq_handler
+ * @note this function is primarily for testing purposes and it's not required part of HAL implementation
+ *
+ */
+ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
+
 /** Get low power ticker's data
  *
  * @return The low power ticker data
  */
-const ticker_data_t* get_lp_ticker_data(void);
+const ticker_data_t *get_lp_ticker_data(void);
 
 /** The wrapper for ticker_irq_handler, to pass lp ticker's data
@@ -50,10 +91,68 @@
 /** Initialize the low power ticker
  *
+ * Initialize or re-initialize the ticker. This resets all the
+ * clocking and prescaler registers, along with disabling
+ * the compare interrupt.
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_init()
+ * {
+ *     // Enable clock gate so processor can read LPTMR registers
+ *     POWER_CTRL |= POWER_CTRL_LPTMR_Msk;
+ *
+ *     // Disable the timer and ensure it is powered down
+ *     LPTMR_CTRL &= ~(LPTMR_CTRL_ENABLE_Msk | LPTMR_CTRL_COMPARE_ENABLE_Msk);
+ *
+ *     // Configure divisors - no division necessary
+ *     LPTMR_PRESCALE = 0;
+ *     LPTMR_CTRL |= LPTMR_CTRL_ENABLE_Msk;
+ *
+ *     // Install the interrupt handler
+ *     NVIC_SetVector(LPTMR_IRQn, (uint32_t)lp_ticker_irq_handler);
+ *     NVIC_EnableIRQ(LPTMR_IRQn);
+ * }
+ * @endcode
  */
 void lp_ticker_init(void);
 
-/** Read the current counter
- *
- * @return The current timer's counter value in microseconds
+/** Deinitialize the lower power ticker
+ *
+ * Powerdown the lp ticker in preparation for sleep, powerdown, or reset.
+ *
+ * After calling this function no other ticker functions should be called except
+ * lp_ticker_init(). Calling any function other than init after freeing is
+ * undefined.
+ *
+ * @note This function stops the ticker from counting.
+ */
+void lp_ticker_free(void);
+
+/** Read the current tick
+ *
+ * If no rollover has occurred, the seconds passed since lp_ticker_init()
+ * was called can be found by dividing the ticks returned by this function
+ * by the frequency returned by ::lp_ticker_get_info.
+ *
+ * @return The current timer's counter value in ticks
+ *
+ * Pseudo Code:
+ * @code
+ * uint32_t lp_ticker_read()
+ * {
+ *     uint16_t count;
+ *     uint16_t last_count;
+ *
+ *     // Loop until the same tick is read twice since this
+ *     // is ripple counter on a different clock domain.
+ *     count = LPTMR_COUNT;
+ *     do {
+ *         last_count = count;
+ *         count = LPTMR_COUNT;
+ *     } while (last_count != count);
+ *
+ *     return count;
+ * }
+ * @endcode
  */
 uint32_t lp_ticker_read(void);
@@ -61,5 +160,22 @@
 /** Set interrupt for specified timestamp
  *
- * @param timestamp The time in microseconds to be set
+ * @param timestamp The time in ticks to be set
+ *
+ * @note no special handling needs to be done for times in the past
+ * as the common timer code will detect this and call
+ * lp_ticker_fire_interrupt() if this is the case
+ *
+ * @note calling this function with timestamp of more than the supported
+ * number of bits returned by ::lp_ticker_get_info results in undefined
+ * behavior.
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_set_interrupt(timestamp_t timestamp)
+ * {
+ *     LPTMR_COMPARE = timestamp;
+ *     LPTMR_CTRL |= LPTMR_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
  */
 void lp_ticker_set_interrupt(timestamp_t timestamp);
@@ -67,4 +183,12 @@
 /** Disable low power ticker interrupt
  *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_disable_interrupt(void)
+ * {
+ *     // Disable the compare interrupt
+ *     LPTMR_CTRL &= ~LPTMR_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
  */
 void lp_ticker_disable_interrupt(void);
@@ -72,6 +196,42 @@
 /** Clear the low power ticker interrupt
  *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_clear_interrupt(void)
+ * {
+ *     // Write to the ICR (interrupt clear register) of the LPTMR
+ *     LPTMR_ICR = LPTMR_ICR_COMPARE_Msk;
+ * }
+ * @endcode
  */
 void lp_ticker_clear_interrupt(void);
+
+/** Set pending interrupt that should be fired right away.
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_fire_interrupt(void)
+ * {
+ *     NVIC_SetPendingIRQ(LPTMR_IRQn);
+ * }
+ * @endcode
+ */
+void lp_ticker_fire_interrupt(void);
+
+/** Get frequency and counter bits of this ticker.
+ *
+ * Pseudo Code:
+ * @code
+ * const ticker_info_t* lp_ticker_get_info()
+ * {
+ *     static const ticker_info_t info = {
+ *         32768,      // 32KHz
+ *         16          // 16 bit counter
+ *     };
+ *     return &info;
+ * }
+ * @endcode
+ */
+const ticker_info_t *lp_ticker_get_info(void);
 
 /**@}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_critical_section_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_critical_section_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_critical_section_api.c	(revision 374)
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "hal/critical_section_api.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+#include <stdbool.h>
+
+static volatile bool critical_interrupts_enabled = false;
+static volatile bool state_saved = false;
+
+static bool are_interrupts_enabled(void)
+{
+#if defined(__CORTEX_A9)
+    return ((__get_CPSR() & 0x80) == 0);
+#else
+    return ((__get_PRIMASK() & 0x1) == 0);
+#endif
+}
+
+
+MBED_WEAK void hal_critical_section_enter(void)
+{
+    const bool interrupt_state = are_interrupts_enabled();
+
+    __disable_irq();
+
+    if (state_saved == true) {
+        return;
+    }
+
+    critical_interrupts_enabled = interrupt_state;
+    state_saved = true;
+}
+
+MBED_WEAK void hal_critical_section_exit(void)
+{
+    // Interrupts must be disabled on invoking an exit from a critical section
+    MBED_ASSERT(!are_interrupts_enabled());
+    state_saved = false;
+
+    // Restore the IRQs to their state prior to entering the critical section
+    if (critical_interrupts_enabled == true) {
+        __enable_irq();
+    }
+}
+
+MBED_WEAK bool hal_in_critical_section(void)
+{
+    return (state_saved == true);
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_flash_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_flash_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_flash_api.c	(revision 374)
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "hal/flash_api.h"
+
+#if DEVICE_FLASH
+
+#include "platform/mbed_toolchain.h"
+#include <string.h>
+
+MBED_WEAK int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
+{
+    memcpy(data, (const void *)address, size);
+    return 0;
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_gpio.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_gpio.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_gpio.c	(revision 374)
@@ -35,25 +35,31 @@
 }
 
-void gpio_init_in(gpio_t* gpio, PinName pin) {
+void gpio_init_in(gpio_t *gpio, PinName pin)
+{
     gpio_init_in_ex(gpio, pin, PullDefault);
 }
 
-void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+void gpio_init_in_ex(gpio_t *gpio, PinName pin, PinMode mode)
+{
     _gpio_init_in(gpio, pin, mode);
 }
 
-void gpio_init_out(gpio_t* gpio, PinName pin) {
+void gpio_init_out(gpio_t *gpio, PinName pin)
+{
     gpio_init_out_ex(gpio, pin, 0);
 }
 
-void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+void gpio_init_out_ex(gpio_t *gpio, PinName pin, int value)
+{
     _gpio_init_out(gpio, pin, PullNone, value);
 }
 
-void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+void gpio_init_inout(gpio_t *gpio, PinName pin, PinDirection direction, PinMode mode, int value)
+{
     if (direction == PIN_INPUT) {
         _gpio_init_in(gpio, pin, mode);
-        if (pin != NC)
+        if (pin != NC) {
             gpio_write(gpio, value); // we prepare the value in case it is switched later
+        }
     } else {
         _gpio_init_out(gpio, pin, mode, value);
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_api.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_api.c	(revision 374)
@@ -15,8 +15,11 @@
  */
 #include "hal/lp_ticker_api.h"
+#include "hal/mbed_lp_ticker_wrapper.h"
 
-#if DEVICE_LOWPOWERTIMER
+#if DEVICE_LPTICKER
 
-static ticker_event_queue_t events;
+static ticker_event_queue_t events = { 0 };
+
+static ticker_irq_handler_type irq_handler = ticker_irq_handler;
 
 static const ticker_interface_t lp_interface = {
@@ -26,4 +29,7 @@
     .clear_interrupt = lp_ticker_clear_interrupt,
     .set_interrupt = lp_ticker_set_interrupt,
+    .fire_interrupt = lp_ticker_fire_interrupt,
+    .get_info = lp_ticker_get_info,
+    .free = lp_ticker_free,
 };
 
@@ -33,12 +39,31 @@
 };
 
-const ticker_data_t* get_lp_ticker_data(void)
+const ticker_data_t *get_lp_ticker_data(void)
 {
+#if LPTICKER_DELAY_TICKS > 0
+    return get_lp_ticker_wrapper_data(&lp_data);
+#else
     return &lp_data;
+#endif
+}
+
+ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler)
+{
+    ticker_irq_handler_type prev_irq_handler = irq_handler;
+
+    irq_handler = ticker_irq_handler;
+
+    return prev_irq_handler;
 }
 
 void lp_ticker_irq_handler(void)
 {
-    ticker_irq_handler(&lp_data);
+#if LPTICKER_DELAY_TICKS > 0
+    lp_ticker_wrapper_irq_handler(irq_handler);
+#else
+    if (irq_handler) {
+        irq_handler(&lp_data);
+    }
+#endif
 }
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_wrapper.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_wrapper.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_wrapper.c	(revision 374)
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/mbed_lp_ticker_wrapper.h"
+
+#if DEVICE_LPTICKER && (LPTICKER_DELAY_TICKS > 0)
+
+#include "hal/LowPowerTickerWrapper.h"
+#include "platform/mbed_critical.h"
+
+// Do not use SingletonPtr since this must be initialized in a critical section
+static LowPowerTickerWrapper *ticker_wrapper;
+static uint64_t ticker_wrapper_data[(sizeof(LowPowerTickerWrapper) + 7) / 8];
+static bool init = false;
+
+static void lp_ticker_wrapper_init()
+{
+    ticker_wrapper->init();
+}
+
+static uint32_t lp_ticker_wrapper_read()
+{
+    return ticker_wrapper->read();
+}
+
+static void lp_ticker_wrapper_set_interrupt(timestamp_t timestamp)
+{
+    ticker_wrapper->set_interrupt(timestamp);
+}
+
+static void lp_ticker_wrapper_disable_interrupt()
+{
+    ticker_wrapper->disable_interrupt();
+}
+
+static void lp_ticker_wrapper_clear_interrupt()
+{
+    ticker_wrapper->clear_interrupt();
+}
+
+static void lp_ticker_wrapper_fire_interrupt()
+{
+    ticker_wrapper->fire_interrupt();
+}
+
+static const ticker_info_t *lp_ticker_wrapper_get_info()
+{
+    return ticker_wrapper->get_info();
+}
+
+static void lp_ticker_wrapper_free()
+{
+    ticker_wrapper->free();
+}
+
+static const ticker_interface_t lp_interface = {
+    lp_ticker_wrapper_init,
+    lp_ticker_wrapper_read,
+    lp_ticker_wrapper_disable_interrupt,
+    lp_ticker_wrapper_clear_interrupt,
+    lp_ticker_wrapper_set_interrupt,
+    lp_ticker_wrapper_fire_interrupt,
+    lp_ticker_wrapper_free,
+    lp_ticker_wrapper_get_info
+};
+
+void lp_ticker_wrapper_irq_handler(ticker_irq_handler_type handler)
+{
+    core_util_critical_section_enter();
+
+    if (!init) {
+        // Force ticker to initialize
+        get_lp_ticker_data();
+    }
+
+    ticker_wrapper->irq_handler(handler);
+
+    core_util_critical_section_exit();
+}
+
+const ticker_data_t *get_lp_ticker_wrapper_data(const ticker_data_t *data)
+{
+    core_util_critical_section_enter();
+
+    if (!init) {
+        ticker_wrapper = new (ticker_wrapper_data) LowPowerTickerWrapper(data, &lp_interface, LPTICKER_DELAY_TICKS, LPTICKER_DELAY_TICKS);
+        init = true;
+    }
+
+    core_util_critical_section_exit();
+
+    return &ticker_wrapper->data;
+}
+
+void lp_ticker_wrapper_suspend()
+{
+    if (!init) {
+        // Force ticker to initialize
+        get_lp_ticker_data();
+    }
+
+    ticker_wrapper->suspend();
+}
+
+void lp_ticker_wrapper_resume()
+{
+    if (!init) {
+        // Force ticker to initialize
+        get_lp_ticker_data();
+    }
+
+    ticker_wrapper->resume();
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_wrapper.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_wrapper.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_lp_ticker_wrapper.h	(revision 374)
@@ -0,0 +1,78 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LP_TICKER_WRAPPER_H
+#define MBED_LP_TICKER_WRAPPER_H
+
+#include "device.h"
+
+#if DEVICE_LPTICKER
+
+#include "hal/ticker_api.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/**
+ * Interrupt handler for the wrapped lp ticker
+ *
+ * @param handler the function which would normally be called by the
+ *      lp ticker handler when it is not wrapped
+ */
+void lp_ticker_wrapper_irq_handler(ticker_irq_handler_type handler);
+
+/**
+ * Get wrapped lp ticker data
+ *
+ * @param data hardware low power ticker object
+ * @return wrapped low power ticker object
+ */
+const ticker_data_t *get_lp_ticker_wrapper_data(const ticker_data_t *data);
+
+/**
+ * Suspend the wrapper layer code
+ *
+ * Pass through all interrupts to the low power ticker and stop using
+ * the microsecond ticker.
+ */
+void lp_ticker_wrapper_suspend(void);
+
+/**
+ * Resume the wrapper layer code
+ *
+ * Resume operation of the wrapper layer. Interrupts will be filtered
+ * as normal and the microsecond timer will be used for interrupts scheduled
+ * too quickly back-to-back.
+ */
+void lp_ticker_wrapper_resume(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_pinmap_common.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_pinmap_common.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_pinmap_common.c	(revision 374)
@@ -17,7 +17,9 @@
 #include "platform/mbed_error.h"
 
-void pinmap_pinout(PinName pin, const PinMap *map) {
-    if (pin == NC)
+void pinmap_pinout(PinName pin, const PinMap *map)
+{
+    if (pin == NC) {
         return;
+    }
 
     while (map->pin != NC) {
@@ -30,27 +32,33 @@
         map++;
     }
-    error("could not pinout");
+    MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "could not pinout", pin);
 }
 
-uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+uint32_t pinmap_merge(uint32_t a, uint32_t b)
+{
     // both are the same (inc both NC)
-    if (a == b)
+    if (a == b) {
         return a;
+    }
 
     // one (or both) is not connected
-    if (a == (uint32_t)NC)
+    if (a == (uint32_t)NC) {
         return b;
-    if (b == (uint32_t)NC)
+    }
+    if (b == (uint32_t)NC) {
         return a;
+    }
 
     // mis-match error case
-    error("pinmap mis-match");
+    MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap mis-match", a);
     return (uint32_t)NC;
 }
 
-uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap *map)
+{
     while (map->pin != NC) {
-        if (map->pin == pin)
+        if (map->pin == pin) {
             return map->peripheral;
+        }
         map++;
     }
@@ -58,19 +66,24 @@
 }
 
-uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+uint32_t pinmap_peripheral(PinName pin, const PinMap *map)
+{
     uint32_t peripheral = (uint32_t)NC;
 
-    if (pin == (PinName)NC)
+    if (pin == (PinName)NC) {
         return (uint32_t)NC;
+    }
     peripheral = pinmap_find_peripheral(pin, map);
-    if ((uint32_t)NC == peripheral) // no mapping available
-        error("pinmap not found for peripheral");
+    if ((uint32_t)NC == peripheral) { // no mapping available
+        MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for peripheral", peripheral);
+    }
     return peripheral;
 }
 
-uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
+uint32_t pinmap_find_function(PinName pin, const PinMap *map)
+{
     while (map->pin != NC) {
-        if (map->pin == pin)
+        if (map->pin == pin) {
             return map->function;
+        }
         map++;
     }
@@ -78,12 +91,15 @@
 }
 
-uint32_t pinmap_function(PinName pin, const PinMap* map) {
+uint32_t pinmap_function(PinName pin, const PinMap *map)
+{
     uint32_t function = (uint32_t)NC;
 
-    if (pin == (PinName)NC)
+    if (pin == (PinName)NC) {
         return (uint32_t)NC;
+    }
     function = pinmap_find_function(pin, map);
-    if ((uint32_t)NC == function) // no mapping available
-        error("pinmap not found for function");
+    if ((uint32_t)NC == function) { // no mapping available
+        MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for function", function);
+    }
     return function;
 }
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_sleep_manager.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_sleep_manager.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_sleep_manager.c	(revision 374)
@@ -0,0 +1,251 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/mbed_assert.h"
+#include "platform/mbed_power_mgmt.h"
+#include "platform/mbed_critical.h"
+#include "hal/sleep_api.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_debug.h"
+#include "platform/mbed_stats.h"
+#include "hal/us_ticker_api.h"
+#include "hal/lp_ticker_api.h"
+#include <limits.h>
+#include <stdio.h>
+#include "platform/mbed_stats.h"
+
+
+#if DEVICE_SLEEP
+
+// deep sleep locking counter. A target is allowed to deep sleep if counter == 0
+static uint16_t deep_sleep_lock = 0U;
+static us_timestamp_t sleep_time = 0;
+static us_timestamp_t deep_sleep_time = 0;
+
+#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER)
+static ticker_data_t *sleep_ticker = NULL;
+#endif
+
+static inline us_timestamp_t read_us(void)
+{
+#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER)
+    if (NULL == sleep_ticker) {
+        sleep_ticker = (ticker_data_t *)get_lp_ticker_data();
+    }
+    return ticker_read_us(sleep_ticker);
+#else
+    return 0;
+#endif
+}
+
+us_timestamp_t mbed_time_idle(void)
+{
+    return (sleep_time + deep_sleep_time);
+}
+
+us_timestamp_t mbed_uptime(void)
+{
+    return read_us();
+}
+
+us_timestamp_t mbed_time_sleep(void)
+{
+    return sleep_time;
+}
+
+us_timestamp_t mbed_time_deepsleep(void)
+{
+    return deep_sleep_time;
+}
+
+#ifdef MBED_SLEEP_TRACING_ENABLED
+
+// Number of drivers that can be stored in the structure
+#define STATISTIC_COUNT  10
+
+typedef struct sleep_statistic {
+    const char *identifier;
+    uint8_t count;
+} sleep_statistic_t;
+
+static sleep_statistic_t sleep_stats[STATISTIC_COUNT];
+
+static sleep_statistic_t *sleep_tracker_find(const char *const filename)
+{
+    for (int i = 0; i < STATISTIC_COUNT; ++i) {
+        if (sleep_stats[i].identifier == filename) {
+            return &sleep_stats[i];
+        }
+    }
+
+    return NULL;
+}
+
+static sleep_statistic_t *sleep_tracker_add(const char *const filename)
+{
+    for (int i = 0; i < STATISTIC_COUNT; ++i) {
+        if (sleep_stats[i].identifier == NULL) {
+            sleep_stats[i].identifier = filename;
+
+            return &sleep_stats[i];
+        }
+    }
+
+    debug("No free indexes left to use in mbed sleep tracker.\r\n");
+
+    return NULL;
+}
+
+static void sleep_tracker_print_stats(void)
+{
+    debug("Sleep locks held:\r\n");
+    for (int i = 0; i < STATISTIC_COUNT; ++i) {
+        if (sleep_stats[i].count == 0) {
+            continue;
+        }
+
+        if (sleep_stats[i].identifier == NULL) {
+            return;
+        }
+
+        debug("[id: %s, count: %u]\r\n", sleep_stats[i].identifier,
+              sleep_stats[i].count);
+    }
+}
+
+void sleep_tracker_lock(const char *const filename, int line)
+{
+    sleep_statistic_t *stat = sleep_tracker_find(filename);
+
+    // Entry for this driver does not exist, create one.
+    if (stat == NULL) {
+        stat = sleep_tracker_add(filename);
+    }
+
+    core_util_atomic_incr_u8(&stat->count, 1);
+
+    debug("LOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock);
+}
+
+void sleep_tracker_unlock(const char *const filename, int line)
+{
+    sleep_statistic_t *stat = sleep_tracker_find(filename);
+
+    // Entry for this driver does not exist, something went wrong.
+    if (stat == NULL) {
+        debug("Unlocking sleep for driver that was not previously locked: %s, ln: %i\r\n", filename, line);
+        return;
+    }
+
+    core_util_atomic_decr_u8(&stat->count, 1);
+
+    debug("UNLOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock);
+}
+
+#endif // MBED_SLEEP_TRACING_ENABLED
+
+void sleep_manager_lock_deep_sleep_internal(void)
+{
+    core_util_critical_section_enter();
+    if (deep_sleep_lock == USHRT_MAX) {
+        core_util_critical_section_exit();
+        MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_OVERFLOW), "DeepSleepLock overflow (> USHRT_MAX)", deep_sleep_lock);
+    }
+    core_util_atomic_incr_u16(&deep_sleep_lock, 1);
+    core_util_critical_section_exit();
+}
+
+void sleep_manager_unlock_deep_sleep_internal(void)
+{
+    core_util_critical_section_enter();
+    if (deep_sleep_lock == 0) {
+        core_util_critical_section_exit();
+        MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_UNDERFLOW), "DeepSleepLock underflow (< 0)", deep_sleep_lock);
+    }
+    core_util_atomic_decr_u16(&deep_sleep_lock, 1);
+    core_util_critical_section_exit();
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+    return deep_sleep_lock == 0 ? true : false;
+}
+
+bool sleep_manager_can_deep_sleep_test_check()
+{
+    const uint32_t check_time_us = 2000;
+    const ticker_data_t *const ticker = get_us_ticker_data();
+    uint32_t start = ticker_read(ticker);
+    while ((ticker_read(ticker) - start) < check_time_us) {
+        if (sleep_manager_can_deep_sleep()) {
+            return true;
+        }
+    }
+    return false;
+}
+
+void sleep_manager_sleep_auto(void)
+{
+#ifdef MBED_SLEEP_TRACING_ENABLED
+    sleep_tracker_print_stats();
+#endif
+    core_util_critical_section_enter();
+    us_timestamp_t start = read_us();
+    bool deep = false;
+
+// debug profile should keep debuggers attached, no deep sleep allowed
+#ifdef MBED_DEBUG
+    hal_sleep();
+#else
+    if (sleep_manager_can_deep_sleep()) {
+        deep = true;
+        hal_deepsleep();
+    } else {
+        hal_sleep();
+    }
+#endif
+
+    us_timestamp_t end = read_us();
+    if (true == deep) {
+        deep_sleep_time += end - start;
+    } else {
+        sleep_time += end - start;
+    }
+    core_util_critical_section_exit();
+}
+
+#else
+
+// locking is valid only if DEVICE_SLEEP is defined
+// we provide empty implementation
+
+void sleep_manager_lock_deep_sleep_internal(void)
+{
+
+}
+
+void sleep_manager_unlock_deep_sleep_internal(void)
+{
+
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+    // no sleep implemented
+    return false;
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_ticker_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_ticker_api.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_ticker_api.c	(revision 374)
@@ -14,47 +14,342 @@
  * limitations under the License.
  */
+#include <stdio.h>
 #include <stddef.h>
 #include "hal/ticker_api.h"
 #include "platform/mbed_critical.h"
-
-void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler) {
-    data->interface->init();
-
-    data->queue->event_handler = handler;
-}
-
-void ticker_irq_handler(const ticker_data_t *const data) {
-    data->interface->clear_interrupt();
+#include "platform/mbed_assert.h"
+
+static void schedule_interrupt(const ticker_data_t *const ticker);
+static void update_present_time(const ticker_data_t *const ticker);
+
+/*
+ * Initialize a ticker instance.
+ */
+static void initialize(const ticker_data_t *ticker)
+{
+    // return if the queue has already been initialized, in that case the
+    // interface used by the queue is already initialized.
+    if (ticker->queue->initialized) {
+        return;
+    }
+    if (ticker->queue->suspended) {
+        return;
+    }
+
+    ticker->interface->init();
+
+    const ticker_info_t *info = ticker->interface->get_info();
+    uint32_t frequency = info->frequency;
+    if (info->frequency == 0) {
+        MBED_ASSERT(0);
+        frequency = 1000000;
+    }
+
+    uint8_t frequency_shifts = 0;
+    for (uint8_t i = 31; i > 0; --i) {
+        if ((1 << i) == frequency) {
+            frequency_shifts = i;
+            break;
+        }
+    }
+
+    uint32_t bits = info->bits;
+    if ((info->bits > 32) || (info->bits < 4)) {
+        MBED_ASSERT(0);
+        bits = 32;
+    }
+    uint32_t max_delta = 0x7 << (bits - 4); // 7/16th
+    uint64_t max_delta_us =
+        ((uint64_t)max_delta * 1000000 + frequency - 1) / frequency;
+
+    ticker->queue->event_handler = NULL;
+    ticker->queue->head = NULL;
+    ticker->queue->tick_last_read = ticker->interface->read();
+    ticker->queue->tick_remainder = 0;
+    ticker->queue->frequency = frequency;
+    ticker->queue->frequency_shifts = frequency_shifts;
+    ticker->queue->bitmask = ((uint64_t)1 << bits) - 1;
+    ticker->queue->max_delta = max_delta;
+    ticker->queue->max_delta_us = max_delta_us;
+    ticker->queue->present_time = 0;
+    ticker->queue->dispatching = false;
+    ticker->queue->suspended = false;
+    ticker->queue->initialized = true;
+
+    update_present_time(ticker);
+    schedule_interrupt(ticker);
+}
+
+/**
+ * Set the event handler function of a ticker instance.
+ */
+static void set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+    ticker->queue->event_handler = handler;
+}
+
+/*
+ * Convert a 32 bit timestamp into a 64 bit timestamp.
+ *
+ * A 64 bit timestamp is used as the point of time of reference while the
+ * timestamp to convert is relative to this point of time.
+ *
+ * The lower 32 bits of the timestamp returned will be equal to the timestamp to
+ * convert.
+ *
+ * If the timestamp to convert is less than the lower 32 bits of the time
+ * reference then the timestamp to convert is seen as an overflowed value and
+ * the upper 32 bit of the timestamp returned will be equal to the upper 32 bit
+ * of the reference point + 1.
+ * Otherwise, the upper 32 bit returned will be equal to the upper 32 bit of the
+ * reference point.
+ *
+ * @param ref: The 64 bit timestamp of reference.
+ * @param timestamp: The timestamp to convert.
+ */
+static us_timestamp_t convert_timestamp(us_timestamp_t ref, timestamp_t timestamp)
+{
+    bool overflow = timestamp < ((timestamp_t) ref) ? true : false;
+
+    us_timestamp_t result = (ref & ~((us_timestamp_t)UINT32_MAX)) | timestamp;
+    if (overflow) {
+        result += (1ULL << 32);
+    }
+
+    return result;
+}
+
+/**
+ * Update the present timestamp value of a ticker.
+ */
+static void update_present_time(const ticker_data_t *const ticker)
+{
+    ticker_event_queue_t *queue = ticker->queue;
+    if (queue->suspended) {
+        return;
+    }
+    uint32_t ticker_time = ticker->interface->read();
+    if (ticker_time == ticker->queue->tick_last_read) {
+        // No work to do
+        return;
+    }
+
+    uint64_t elapsed_ticks = (ticker_time - queue->tick_last_read) & queue->bitmask;
+    queue->tick_last_read = ticker_time;
+
+    uint64_t elapsed_us;
+    if (1000000 == queue->frequency) {
+        // Optimized for 1MHz
+
+        elapsed_us = elapsed_ticks;
+    } else if (0 != queue->frequency_shifts) {
+        // Optimized for frequencies divisible by 2
+        uint64_t us_x_ticks = elapsed_ticks * 1000000;
+        elapsed_us = us_x_ticks >> queue->frequency_shifts;
+
+        // Update remainder
+        queue->tick_remainder += us_x_ticks - (elapsed_us << queue->frequency_shifts);
+        if (queue->tick_remainder >= queue->frequency) {
+            elapsed_us += 1;
+            queue->tick_remainder -= queue->frequency;
+        }
+    } else {
+        // General case
+
+        uint64_t us_x_ticks = elapsed_ticks * 1000000;
+        elapsed_us = us_x_ticks / queue->frequency;
+
+        // Update remainder
+        queue->tick_remainder += us_x_ticks - elapsed_us * queue->frequency;
+        if (queue->tick_remainder >= queue->frequency) {
+            elapsed_us += 1;
+            queue->tick_remainder -= queue->frequency;
+        }
+    }
+
+    // Update current time
+    queue->present_time += elapsed_us;
+}
+
+/**
+ * Given the absolute timestamp compute the hal tick timestamp rounded up.
+ */
+static timestamp_t compute_tick_round_up(const ticker_data_t *const ticker, us_timestamp_t timestamp)
+{
+    ticker_event_queue_t *queue = ticker->queue;
+    us_timestamp_t delta_us = timestamp - queue->present_time;
+
+    timestamp_t delta = ticker->queue->max_delta;
+    if (delta_us <=  ticker->queue->max_delta_us) {
+        // Checking max_delta_us ensures the operation will not overflow
+
+        if (1000000 == queue->frequency) {
+            // Optimized for 1MHz
+
+            delta = delta_us;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        } else if (0 != queue->frequency_shifts) {
+            // Optimized frequencies divisible by 2
+
+            delta = ((delta_us << ticker->queue->frequency_shifts) + 1000000 - 1) / 1000000;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        } else {
+            // General case
+
+            delta = (delta_us * queue->frequency + 1000000 - 1) / 1000000;
+            if (delta > ticker->queue->max_delta) {
+                delta = ticker->queue->max_delta;
+            }
+        }
+    }
+    return (queue->tick_last_read + delta) & queue->bitmask;
+}
+
+/**
+ * Return 1 if the tick has incremented to or past match_tick, otherwise 0.
+ */
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick)
+{
+    if (match_tick > prev_tick) {
+        return (cur_tick >= match_tick) || (cur_tick < prev_tick);
+    } else {
+        return (cur_tick < prev_tick) && (cur_tick >= match_tick);
+    }
+}
+
+/**
+ * Compute the time when the interrupt has to be triggered and schedule it.
+ *
+ * If there is no event in the queue or the next event to execute is in more
+ * than ticker.queue.max_delta ticks from now then the ticker irq will be
+ * scheduled in ticker.queue.max_delta ticks. Otherwise the irq will be
+ * scheduled to happen when the running counter reach the timestamp of the
+ * first event in the queue.
+ *
+ * @note If there is no event in the queue then the interrupt is scheduled to
+ * in ticker.queue.max_delta. This is necessary to keep track
+ * of the timer overflow.
+ */
+static void schedule_interrupt(const ticker_data_t *const ticker)
+{
+    ticker_event_queue_t *queue = ticker->queue;
+    if (queue->suspended || ticker->queue->dispatching) {
+        // Don't schedule the next interrupt until dispatching is
+        // finished. This prevents repeated calls to interface->set_interrupt
+        return;
+    }
+
+    update_present_time(ticker);
+
+    if (ticker->queue->head) {
+        us_timestamp_t present = ticker->queue->present_time;
+        us_timestamp_t match_time = ticker->queue->head->timestamp;
+
+        // if the event at the head of the queue is in the past then schedule
+        // it immediately.
+        if (match_time <= present) {
+            ticker->interface->fire_interrupt();
+            return;
+        }
+
+        timestamp_t match_tick = compute_tick_round_up(ticker, match_time);
+
+        // The same tick should never occur since match_tick is rounded up.
+        // If the same tick is returned scheduling will not work correctly.
+        MBED_ASSERT(match_tick != queue->tick_last_read);
+
+        ticker->interface->set_interrupt(match_tick);
+        timestamp_t cur_tick = ticker->interface->read();
+
+        if (_ticker_match_interval_passed(queue->tick_last_read, cur_tick, match_tick)) {
+            ticker->interface->fire_interrupt();
+        }
+    } else {
+        uint32_t match_tick =
+            (queue->tick_last_read + queue->max_delta) & queue->bitmask;
+        ticker->interface->set_interrupt(match_tick);
+    }
+}
+
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+    initialize(ticker);
+
+    core_util_critical_section_enter();
+    set_handler(ticker, handler);
+    core_util_critical_section_exit();
+}
+
+void ticker_irq_handler(const ticker_data_t *const ticker)
+{
+    core_util_critical_section_enter();
+
+    ticker->interface->clear_interrupt();
+    if (ticker->queue->suspended) {
+        core_util_critical_section_exit();
+        return;
+    }
 
     /* Go through all the pending TimerEvents */
+    ticker->queue->dispatching = true;
     while (1) {
-        if (data->queue->head == NULL) {
-            // There are no more TimerEvents left, so disable matches.
-            data->interface->disable_interrupt();
-            return;
-        }
-
-        if ((int)(data->queue->head->timestamp - data->interface->read()) <= 0) {
+        if (ticker->queue->head == NULL) {
+            break;
+        }
+
+        // update the current timestamp used by the queue
+        update_present_time(ticker);
+
+        if (ticker->queue->head->timestamp <= ticker->queue->present_time) {
             // This event was in the past:
             //      point to the following one and execute its handler
-            ticker_event_t *p = data->queue->head;
-            data->queue->head = data->queue->head->next;
-            if (data->queue->event_handler != NULL) {
-                (*data->queue->event_handler)(p->id); // NOTE: the handler can set new events
+            ticker_event_t *p = ticker->queue->head;
+            ticker->queue->head = ticker->queue->head->next;
+            if (ticker->queue->event_handler != NULL) {
+                (*ticker->queue->event_handler)(p->id); // NOTE: the handler can set new events
             }
             /* Note: We continue back to examining the head because calling the
              * event handler may have altered the chain of pending events. */
         } else {
-            // This event and the following ones in the list are in the future:
-            //      set it as next interrupt and return
-            data->interface->set_interrupt(data->queue->head->timestamp);
-            return;
-        }
-    }
-}
-
-void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id) {
-    /* disable interrupts for the duration of the function */
-    core_util_critical_section_enter();
+            break;
+        }
+    }
+    ticker->queue->dispatching = false;
+
+    schedule_interrupt(ticker);
+
+    core_util_critical_section_exit();
+}
+
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id)
+{
+    core_util_critical_section_enter();
+
+    // update the current timestamp
+    update_present_time(ticker);
+    us_timestamp_t absolute_timestamp = convert_timestamp(
+                                            ticker->queue->present_time,
+                                            timestamp
+                                        );
+
+    // defer to ticker_insert_event_us
+    ticker_insert_event_us(
+        ticker,
+        obj, absolute_timestamp, id
+    );
+
+    core_util_critical_section_exit();
+}
+
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id)
+{
+    core_util_critical_section_enter();
+
+    // update the current timestamp
+    update_present_time(ticker);
 
     // initialise our data
@@ -65,8 +360,8 @@
        an element this should come before (which is possibly the
        head). */
-    ticker_event_t *prev = NULL, *p = data->queue->head;
+    ticker_event_t *prev = NULL, *p = ticker->queue->head;
     while (p != NULL) {
         /* check if we come before p */
-        if ((int)(timestamp - p->timestamp) < 0) {
+        if (timestamp < p->timestamp) {
             break;
         }
@@ -75,5 +370,5 @@
         p = p->next;
     }
-    
+
     /* if we're at the end p will be NULL, which is correct */
     obj->next = p;
@@ -81,6 +376,6 @@
     /* if prev is NULL we're at the head */
     if (prev == NULL) {
-        data->queue->head = obj;
-        data->interface->set_interrupt(timestamp);
+        ticker->queue->head = obj;
+        schedule_interrupt(ticker);
     } else {
         prev->next = obj;
@@ -90,19 +385,16 @@
 }
 
-void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj) {
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj)
+{
     core_util_critical_section_enter();
 
     // remove this object from the list
-    if (data->queue->head == obj) {
+    if (ticker->queue->head == obj) {
         // first in the list, so just drop me
-        data->queue->head = obj->next;
-        if (data->queue->head == NULL) {
-            data->interface->disable_interrupt();
-        } else {
-            data->interface->set_interrupt(data->queue->head->timestamp);
-        }
+        ticker->queue->head = obj->next;
+        schedule_interrupt(ticker);
     } else {
         // find the object before me, then drop me
-        ticker_event_t* p = data->queue->head;
+        ticker_event_t *p = ticker->queue->head;
         while (p != NULL) {
             if (p->next == obj) {
@@ -117,7 +409,18 @@
 }
 
-timestamp_t ticker_read(const ticker_data_t *const data)
-{
-    return data->interface->read();
+timestamp_t ticker_read(const ticker_data_t *const ticker)
+{
+    return ticker_read_us(ticker);
+}
+
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker)
+{
+    initialize(ticker);
+
+    core_util_critical_section_enter();
+    update_present_time(ticker);
+    core_util_critical_section_exit();
+
+    return ticker->queue->present_time;
 }
 
@@ -136,2 +439,28 @@
     return ret;
 }
+
+void ticker_suspend(const ticker_data_t *const ticker)
+{
+    core_util_critical_section_enter();
+
+    ticker->queue->suspended = true;
+
+    core_util_critical_section_exit();
+}
+
+void ticker_resume(const ticker_data_t *const ticker)
+{
+    core_util_critical_section_enter();
+
+    ticker->queue->suspended = false;
+    if (ticker->queue->initialized) {
+        ticker->queue->tick_last_read = ticker->interface->read();
+
+        update_present_time(ticker);
+        schedule_interrupt(ticker);
+    } else {
+        initialize(ticker);
+    }
+
+    core_util_critical_section_exit();
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_us_ticker_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_us_ticker_api.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/mbed_us_ticker_api.c	(revision 374)
@@ -16,5 +16,7 @@
 #include "hal/us_ticker_api.h"
 
-static ticker_event_queue_t events;
+static ticker_event_queue_t events = { 0 };
+
+static ticker_irq_handler_type irq_handler = ticker_irq_handler;
 
 static const ticker_interface_t us_interface = {
@@ -24,18 +26,32 @@
     .clear_interrupt = us_ticker_clear_interrupt,
     .set_interrupt = us_ticker_set_interrupt,
+    .fire_interrupt = us_ticker_fire_interrupt,
+    .get_info = us_ticker_get_info,
+    .free = us_ticker_free,
 };
 
 static const ticker_data_t us_data = {
     .interface = &us_interface,
-    .queue = &events,
+    .queue = &events
 };
 
-const ticker_data_t* get_us_ticker_data(void)
+const ticker_data_t *get_us_ticker_data(void)
 {
     return &us_data;
 }
 
+ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler)
+{
+    ticker_irq_handler_type prev_irq_handler = irq_handler;
+
+    irq_handler = ticker_irq_handler;
+
+    return prev_irq_handler;
+}
+
 void us_ticker_irq_handler(void)
 {
-    ticker_irq_handler(&us_data);
+    if (irq_handler) {
+        irq_handler(&us_data);
+    }
 }
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/rtc_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/rtc_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/rtc_api.h	(revision 374)
@@ -1,5 +1,2 @@
-
-/** \addtogroup hal */
-/** @{*/
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -17,10 +14,12 @@
  * limitations under the License.
  */
+
+/** \addtogroup hal */
+/** @{*/
+
 #ifndef MBED_RTC_API_H
 #define MBED_RTC_API_H
 
 #include "device.h"
-
-#if DEVICE_RTC
 
 #include <time.h>
@@ -31,10 +30,66 @@
 
 /**
- * \defgroup hal_rtc RTC hal functions
+ * \defgroup hal_rtc RTC hal
+ *
+ * The RTC hal provides a low level interface to the Real Time Counter (RTC) of a
+ * target.
+ *
+ * # Defined behaviour
+ * * The function ::rtc_init is safe to call repeatedly - Verified by test ::rtc_init_test.
+ * * RTC accuracy is at least 10% - Verified by test ::rtc_accuracy_test.
+ * * Init/free doesn't stop RTC from counting - Verified by test ::rtc_persist_test.
+ * * Software reset doesn't stop RTC from counting - Verified by test ::rtc_reset_test.
+ * * Sleep modes don't stop RTC from counting - Verified by test ::rtc_sleep_test.
+ * * Shutdown mode doesn't stop RTC from counting - Not verified.
+ * * The functions ::rtc_write/::rtc_read provides availability to set/get RTC time
+ * - Verified by test ::rtc_write_read_test.
+ * * The functions ::rtc_isenabled returns 1 if the RTC is counting and the time has been set,
+ * 0 otherwise - Verified by test ::rtc_enabled_test.
+ *
+ * # Undefined behaviour
+ * * Calling any function other than ::rtc_init before the initialisation of the RTC
+ *
+ * # Potential bugs
+ * * Incorrect overflow handling - Verified by ::rtc_range_test
+ * * Glitches due to ripple counter - Verified by ::rtc_glitch_test
+ *
+ * @see hal_rtc_tests
+ *
  * @{
  */
 
+/**
+ * \defgroup hal_rtc_tests RTC hal tests
+ * The RTC test validate proper implementation of the RTC hal.
+ *
+ * To run the RTC hal tests use the command:
+ *
+ *     mbed test -t <toolchain> -m <target> -n tests-mbed_hal-rtc*
+ */
+
+
 /** Initialize the RTC peripheral
  *
+ * Powerup the RTC in perpetration for access. This function must be called
+ * before any other RTC functions ares called. This does not change the state
+ * of the RTC. It just enables access to it.
+ *
+ * @note This function is safe to call repeatedly - Tested by ::rtc_init_test
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * void rtc_init()
+ * {
+ *     // Enable clock gate so processor can read RTC registers
+ *     POWER_CTRL |= POWER_CTRL_RTC_Msk;
+ *
+ *     // See if the RTC is already setup
+ *     if (!(RTC_STATUS & RTC_STATUS_COUNTING_Msk)) {
+ *
+ *         // Setup the RTC clock source
+ *         RTC_CTRL |= RTC_CTRL_CLK32_Msk;
+ *     }
+ * }
+ * @endcode
  */
 void rtc_init(void);
@@ -42,12 +97,38 @@
 /** Deinitialize RTC
  *
- * TODO: The function is not used by rtc api in mbed-drivers.
+ * Powerdown the RTC in preparation for sleep, powerdown or reset. That should only
+ * affect the CPU domain and not the time keeping logic.
+ * After this function is called no other RTC functions should be called
+ * except for ::rtc_init.
+ *
+ * @note This function does not stop the RTC from counting - Tested by ::rtc_persist_test
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * void rtc_free()
+ * {
+ *     // Disable clock gate since processor no longer needs to read RTC registers
+ *     POWER_CTRL &= ~POWER_CTRL_RTC_Msk;
+ * }
+ * @endcode
  */
 void rtc_free(void);
 
-/** Get the RTC enable status
+/** Check if the RTC has the time set and is counting
  *
- * @retval 0 disabled
- * @retval 1 enabled
+ * @retval 0 The time reported by the RTC is not valid
+ * @retval 1 The time has been set the RTC is counting
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * int rtc_isenabled()
+ * {
+ *     if (RTC_STATUS & RTC_STATUS_COUNTING_Msk) {
+ *         return 1;
+ *     } else {
+ *         return 0;
+ *     }
+ * }
+ * @endcode
  */
 int rtc_isenabled(void);
@@ -55,11 +136,42 @@
 /** Get the current time from the RTC peripheral
  *
- * @return The current time
+ * @return The current time in seconds
+ *
+ * @note Some RTCs are not synchronized with the main clock. If
+ * this is the case with your RTC then you must read the RTC time
+ * in a loop to prevent reading the wrong time due to a glitch.
+ * The test ::rtc_glitch_test is intended to catch this bug.
+ *
+ * Example implementation for an unsynchronized ripple counter:
+ * @code
+ * time_t rtc_read()
+ * {
+ *     uint32_t val;
+ *     uint32_t last_val;
+ *
+ *     // Loop until the same value is read twice
+ *     val = RTC_SECONDS;
+ *     do {
+ *         last_val = val;
+ *         val = RTC_SECONDS;
+ *     } while (last_val != val);
+ *
+ *     return (time_t)val;
+ * }
+ * @endcode
  */
 time_t rtc_read(void);
 
-/** Set the current time to the RTC peripheral
+/** Write the current time in seconds to the RTC peripheral
  *
- * @param t The current time to be set
+ * @param t The current time to be set in seconds.
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * void rtc_write(time_t t)
+ * {
+ *     RTC_SECONDS = t;
+ * }
+ * @endcode
  */
 void rtc_write(time_t t);
@@ -73,5 +185,3 @@
 #endif
 
-#endif
-
 /** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/sleep_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/sleep_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/sleep_api.h	(revision 374)
@@ -28,7 +28,43 @@
 #endif
 
+/**
+ * \defgroup hal_sleep sleep hal requirements
+ * Low level interface to the sleep mode of a target.
+ *
+ * # Defined behaviour
+ *
+ * * Sleep mode
+ *   * wake-up time should be less than 10 us - Verified by sleep_usticker_test().
+ *   * the processor can be woken up by any internal peripheral interrupt  - Verified by sleep_usticker_test().
+ *   * all peripherals operate as in run mode - not verified.
+ *   * the processor can be woken up by external pin interrupt - not verified.
+ * * Deep sleep
+ *   * the wake-up time should be less than 10 ms - Verified by deepsleep_lpticker_test().
+ *   * lp ticker should wake up a target from this mode - Verified by deepsleep_lpticker_test().
+ *   * RTC should wake up a target from this mode - not verified.
+ *   * an external interrupt on a pin should wake up a target from this mode - not verified.
+ *   * a watchdog timer should wake up a target from this mode - not verified.
+ *   * High-speed clocks are turned off - Verified by deepsleep_high_speed_clocks_turned_off_test().
+ *   * RTC keeps time - Verified by rtc_sleep_test().
+ *
+ * # Undefined behaviour
+ *
+ * * peripherals aside from RTC, GPIO and lp ticker result in undefined behaviour in deep sleep.
+ * @{
+ */
+
+/**
+ * \defgroup hal_sleep_tests sleep hal tests
+ * The sleep HAL tests ensure driver conformance to defined behaviour.
+ *
+ * To run the sleep hal tests use the command:
+ *
+ *     mbed test -t <toolchain> -m <target> -n tests-mbed_hal-sleep*
+ *
+ */
+
 /** Send the microcontroller to sleep
  *
- * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * The processor is setup ready for sleep, and sent to sleep. In this mode, the
  * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
  * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
@@ -37,8 +73,6 @@
  * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
  *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
+ * The wake-up time shall be less than 10 us.
+ *
  */
 void hal_sleep(void);
@@ -47,15 +81,14 @@
  *
  * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
- * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
- * is still maintained.
+ * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks.
+ * All state is still maintained.
  *
- * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer.
  *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
+ * The wake-up time shall be less than 10 ms.
  */
 void hal_deepsleep(void);
+
+/**@}*/
 
 #ifdef __cplusplus
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/spi_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/spi_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/spi_api.h	(revision 374)
@@ -34,4 +34,5 @@
 
 #define SPI_FILL_WORD         (0xFFFF)
+#define SPI_FILL_CHAR         (0xFF)
 
 #if DEVICE_SPI_ASYNCH
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/ticker_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/ticker_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/ticker_api.h	(revision 374)
@@ -21,12 +21,25 @@
 
 #include <stdint.h>
+#include <stdbool.h>
 #include "device.h"
 
+/**
+ * Legacy format representing a timestamp in us.
+ * Given it is modeled as a 32 bit integer, this type can represent timestamp
+ * up to 4294 seconds (71 minutes).
+ * Prefer using us_timestamp_t which store timestamp as 64 bits integer.
+ */
 typedef uint32_t timestamp_t;
 
+/**
+ * A us timestamp stored in a 64 bit integer.
+ * Can store timestamp up to 584810 years.
+ */
+typedef uint64_t us_timestamp_t;
+
 /** Ticker's event structure
  */
 typedef struct ticker_event_s {
-    timestamp_t            timestamp; /**< Event's timestamp */
+    us_timestamp_t         timestamp; /**< Event's timestamp */
     uint32_t               id;        /**< TimerEvent object */
     struct ticker_event_s *next;      /**< Next event in the queue */
@@ -34,4 +47,12 @@
 
 typedef void (*ticker_event_handler)(uint32_t id);
+
+/** Information about the ticker implementation
+ */
+typedef struct {
+    uint32_t frequency;                           /**< Frequency in Hz this ticker runs at */
+    uint32_t bits;                                /**< Number of bits this ticker supports */
+} ticker_info_t;
+
 
 /** Ticker's interface structure - required API for a ticker
@@ -43,4 +64,7 @@
     void (*clear_interrupt)(void);                /**< Clear interrupt function */
     void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+    void (*fire_interrupt)(void);                 /**< Fire interrupt right-away */
+    void (*free)(void);                           /**< Disable function */
+    const ticker_info_t *(*get_info)(void);       /**< Return info about this ticker's implementation */
 } ticker_interface_t;
 
@@ -50,4 +74,15 @@
     ticker_event_handler event_handler; /**< Event handler */
     ticker_event_t *head;               /**< A pointer to head */
+    uint32_t frequency;                 /**< Frequency of the timer in Hz */
+    uint32_t bitmask;                   /**< Mask to be applied to time values read */
+    uint32_t max_delta;                 /**< Largest delta in ticks that can be used when scheduling */
+    uint64_t max_delta_us;              /**< Largest delta in us that can be used when scheduling */
+    uint32_t tick_last_read;            /**< Last tick read */
+    uint64_t tick_remainder;            /**< Ticks that have not been added to base_time */
+    us_timestamp_t present_time;        /**< Store the timestamp used for present time */
+    bool initialized;                   /**< Indicate if the instance is initialized */
+    bool dispatching;                   /**< The function ticker_irq_handler is dispatching */
+    bool suspended;                     /**< Indicate if the instance is suspended */
+    uint8_t frequency_shifts;           /**< If frequency is a value of 2^n, this is n, otherwise 0 */
 } ticker_event_queue_t;
 
@@ -70,44 +105,118 @@
 /** Initialize a ticker and set the event handler
  *
- * @param data    The ticker's data
+ * @param ticker The ticker object.
  * @param handler A handler to be set
  */
-void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler);
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler);
 
 /** IRQ handler that goes through the events to trigger overdue events.
  *
- * @param data    The ticker's data
- */
-void ticker_irq_handler(const ticker_data_t *const data);
+ * @param ticker The ticker object.
+ */
+void ticker_irq_handler(const ticker_data_t *const ticker);
 
 /** Remove an event from the queue
  *
- * @param data The ticker's data
+ * @param ticker The ticker object.
  * @param obj  The event object to be removed from the queue
  */
-void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj);
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj);
 
 /** Insert an event to the queue
  *
- * @param data      The ticker's data
+ * The event will be executed in timestamp - ticker_read().
+ *
+ * @warning This function does not consider timestamp in the past. If an event
+ * is inserted with a timestamp less than the current timestamp then the event
+ * will be executed in timestamp - ticker_read() us.
+ * The internal counter wrap very quickly it is hard to decide weither an
+ * event is in the past or in 1 hour.
+ *
+ * @note prefer the use of ticker_insert_event_us which allows registration of
+ * absolute timestamp.
+ *
+ * @param ticker    The ticker object.
  * @param obj       The event object to be inserted to the queue
  * @param timestamp The event's timestamp
  * @param id        The event object
  */
-void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
-
-/** Read the current ticker's timestamp
- *
- * @param data The ticker's data
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+
+/** Insert an event to the queue
+ *
+ * The event will be executed in timestamp - ticker_read_us() us.
+ *
+ * @note If an event is inserted with a timestamp less than the current
+ * timestamp then the event will be scheduled immediately resulting in
+ * an instant call to event handler.
+ *
+ * @param ticker    The ticker object.
+ * @param obj       The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id        The event object
+ */
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id);
+
+/** Read the current (relative) ticker's timestamp
+ *
+ * @warning Return a relative timestamp because the counter wrap every 4294
+ * seconds.
+ *
+ * @param ticker The ticker object.
  * @return The current timestamp
  */
-timestamp_t ticker_read(const ticker_data_t *const data);
+timestamp_t ticker_read(const ticker_data_t *const ticker);
+
+/** Read the current (absolute) ticker's timestamp
+ *
+ * @warning Return an absolute timestamp counting from the initialization of the
+ * ticker.
+ *
+ * @param ticker The ticker object.
+ * @return The current timestamp
+ */
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker);
 
 /** Read the next event's timestamp
  *
- * @param data The ticker's data
+ * @param ticker        The ticker object.
+ * @param timestamp     The timestamp object.
  * @return 1 if timestamp is pending event, 0 if there's no event pending
  */
-int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp);
+int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp);
+
+/** Suspend this ticker
+ *
+ * When suspended reads will always return the same time and no
+ * events will be dispatched. When suspended the common layer
+ * will only ever call the interface function clear_interrupt()
+ * and that is only if ticker_irq_handler is called.
+ *
+ *
+ * @param ticker        The ticker object.
+ */
+void ticker_suspend(const ticker_data_t *const ticker);
+
+/** Resume this ticker
+ *
+ * When resumed the ticker will ignore any time that has passed
+ * and continue counting up where it left off.
+ *
+ * @param ticker        The ticker object.
+ */
+void ticker_resume(const ticker_data_t *const ticker);
+
+/* Private functions
+ *
+ * @cond PRIVATE
+ *
+ */
+
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick);
+
+/*
+ * @endcond PRIVATE
+ *
+ */
 
 /**@}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/trng_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/trng_api.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/trng_api.h	(revision 374)
@@ -0,0 +1,72 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRNG_API_H
+#define MBED_TRNG_API_H
+
+#include <stddef.h>
+#include "device.h"
+
+#if DEVICE_TRNG
+
+/** TRNG HAL structure. trng_s is declared in the target's HAL
+ */
+typedef struct trng_s trng_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_trng TRNG hal functions
+ * @{
+ */
+
+/** Initialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_init(trng_t *obj);
+
+/** Deinitialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_free(trng_t *obj);
+
+/** Get random data from TRNG peripheral
+ *
+ * @param obj The TRNG object
+ * @param output The pointer to an output array
+ * @param length The size of output data, to avoid buffer overwrite
+ * @param output_length The length of generated data
+ * @return 0 success, -1 fail
+ */
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/us_ticker_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/us_ticker_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/hal/us_ticker_api.h	(revision 374)
@@ -28,13 +28,99 @@
 
 /**
- * \defgroup hal_UsTicker Microseconds Ticker Functions
+ * \defgroup hal_us_ticker Microsecond Ticker
+ * Low level interface to the microsecond ticker of a target
+ *
+ * # Defined behavior
+ * * Has a reported frequency between 250KHz and 8MHz - Verified by test ::us_ticker_info_test
+ * * Has a counter that is at least 16 bits wide - Verified by test ::us_ticker_info_test
+ * * All behavior defined by the @ref hal_ticker_shared "ticker specification"
+ *
+ * # Undefined behavior
+ * * See the @ref hal_ticker_shared "ticker specification"
+ *
+ * @see hal_us_ticker_tests
+ *
  * @{
  */
 
+/**
+ * \defgroup hal_us_ticker_tests Microsecond Ticker tests
+ * Tests to validate the proper implementation of the microsecond ticker
+ *
+ * To run the microsecond ticker hal tests use the command:
+ *
+ *     mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*,tests-mbed_hal-us_ticker*
+ *
+ * @see hal_ticker_tests
+ *
+ */
+
+/**
+ * \defgroup hal_ticker_shared Ticker Hal
+ * Low level interface to the ticker of a target
+ *
+ * # Defined behavior
+ * * The function ticker_init is safe to call repeatedly - Verified by test ::ticker_init_test
+ * * The function ticker_init allows the ticker to keep counting and disables the ticker interrupt - Verified by test ::ticker_init_test
+ * * Ticker frequency is non-zero and counter is at least 8 bits - Verified by ::ticker_info_test
+ * * The ticker rolls over at (1 << bits) and continues counting starting from 0 - Verified by ::ticker_overflow_test
+ * * The ticker counts at the specified frequency +- 10% - Verified by ::ticker_frequency_test
+ * * The ticker increments by 1 each tick - Verified by ::ticker_increment_test
+ * * The ticker interrupt fires only when the ticker times increments to or past the value set by ticker_set_interrupt.
+ * Verified by ::ticker_interrupt_test and ::ticker_past_test
+ * * It is safe to call ticker_set_interrupt repeatedly before the handler is called - Verified by ::ticker_repeat_reschedule_test
+ * * The function ticker_fire_interrupt causes ticker_irq_handler to be called immediately from interrupt context -
+ * Verified by ::ticker_fire_now_test
+ * * The ticker operations ticker_read, ticker_clear_interrupt, ticker_set_interrupt and ticker_fire_interrupt
+ * take less than 20us to complete - Verified by ::ticker_speed_test
+ *
+ * # Undefined behavior
+ * * Calling any function other than ticker_init before the initialization of the ticker
+ * * Whether ticker_irq_handler is called a second time if the time wraps and matches the value set by ticker_set_interrupt again
+ * * Calling ticker_set_interrupt with a value that has more than the supported number of bits
+ * * Calling any function other than us_ticker_init after calling us_ticker_free
+ *
+ * # Potential bugs
+ * * Drift due to reschedule - Verified by ::ticker_repeat_reschedule_test
+ * * Incorrect overflow handling of timers - Verified by ::ticker_overflow_test
+ * * Interrupting at a time of 0 - Verified by ::ticker_overflow_test
+ * * Interrupt triggered more than once - Verified by ::ticker_interrupt_test
+ *
+ * @ingroup hal_us_ticker
+ * @ingroup hal_lp_ticker
+ */
+
+/**
+ * \defgroup hal_ticker_tests Ticker Tests
+ * Tests to validate the proper implementation of a ticker
+ *
+ * To run the ticker hal tests use the command:
+ *
+ *     mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*
+ *
+ * @ingroup hal_us_ticker
+ * @ingroup hal_lp_ticker
+ */
+
+
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/** Set ticker IRQ handler
+ *
+ * @param ticker_irq_handler IRQ handler to be connected
+ *
+ * @return previous ticker IRQ handler
+ *
+ * @note by default IRQ handler is set to ::ticker_irq_handler
+ * @note this function is primarily for testing purposes and it's not required part of HAL implementation
+ *
+ */
+ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
+
 /** Get ticker's data
  *
- * @return The low power ticker data
- */
-const ticker_data_t* get_us_ticker_data(void);
+ * @return The microsecond ticker data
+ */
+const ticker_data_t *get_us_ticker_data(void);
 
 
@@ -48,10 +134,79 @@
 /** Initialize the ticker
  *
+ * Initialize or re-initialize the ticker. This resets all the
+ * clocking and prescaler registers, along with disabling
+ * the compare interrupt.
+ *
+ * @note Initialization properties tested by ::ticker_init_test
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_init()
+ * {
+ *     // Enable clock gate so processor can read TIMER registers
+ *     POWER_CTRL |= POWER_CTRL_TIMER_Msk;
+ *
+ *     // Disable the timer and ensure it is powered down
+ *     TIMER_CTRL &= ~(TIMER_CTRL_ENABLE_Msk | TIMER_CTRL_COMPARE_ENABLE_Msk);
+ *
+ *     // Configure divisors
+ *     uint32_t prescale = SystemCoreClock / 1000000;
+ *     TIMER_PRESCALE = prescale - 1;
+ *     TIMER_CTRL |= TIMER_CTRL_ENABLE_Msk;
+ *
+ *     // Install the interrupt handler
+ *     NVIC_SetVector(TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+ *     NVIC_EnableIRQ(TIMER_IRQn);
+ * }
+ * @endcode
  */
 void us_ticker_init(void);
 
+/** Deinitialize the us ticker
+ *
+ * Powerdown the us ticker in preparation for sleep, powerdown, or reset.
+ *
+ * After this function is called, no other ticker functions should be called
+ * except us_ticker_init(), calling any function other than init is undefined.
+ *
+ * @note This function stops the ticker from counting.
+ *
+ * Pseudo Code:
+ * @code
+ * uint32_t us_ticker_free()
+ * {
+ *     // Disable timer
+ *     TIMER_CTRL &= ~TIMER_CTRL_ENABLE_Msk;
+ *
+ *     // Disable the compare interrupt
+ *     TIMER_CTRL &= ~TIMER_CTRL_COMPARE_ENABLE_Msk;
+ *
+ *     // Disable timer interrupt
+ *     NVIC_DisableIRQ(TIMER_IRQn);
+ *
+ *     // Disable clock gate so processor cannot read TIMER registers
+ *     POWER_CTRL &= ~POWER_CTRL_TIMER_Msk;
+ * }
+ * @endcode
+ *
+ */
+void us_ticker_free(void);
+
 /** Read the current counter
  *
- * @return The current timer's counter value in microseconds
+ * Read the current counter value without performing frequency conversions.
+ * If no rollover has occurred, the seconds passed since us_ticker_init()
+ * was called can be found by dividing the ticks returned by this function
+ * by the frequency returned by ::us_ticker_get_info.
+ *
+ * @return The current timer's counter value in ticks
+ *
+ * Pseudo Code:
+ * @code
+ * uint32_t us_ticker_read()
+ * {
+ *     return TIMER_COUNT;
+ * }
+ * @endcode
  */
 uint32_t us_ticker_read(void);
@@ -59,5 +214,22 @@
 /** Set interrupt for specified timestamp
  *
- * @param timestamp The time in microseconds to be set
+ * @param timestamp The time in ticks to be set
+ *
+ * @note no special handling needs to be done for times in the past
+ * as the common timer code will detect this and call
+ * us_ticker_fire_interrupt() if this is the case
+ *
+ * @note calling this function with timestamp of more than the supported
+ * number of bits returned by ::us_ticker_get_info results in undefined
+ * behavior.
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_set_interrupt(timestamp_t timestamp)
+ * {
+ *     TIMER_COMPARE = timestamp;
+ *     TIMER_CTRL |= TIMER_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
  */
 void us_ticker_set_interrupt(timestamp_t timestamp);
@@ -65,4 +237,12 @@
 /** Disable us ticker interrupt
  *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_disable_interrupt(void)
+ * {
+ *     // Disable the compare interrupt
+ *     TIMER_CTRL &= ~TIMER_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
  */
 void us_ticker_disable_interrupt(void);
@@ -70,6 +250,44 @@
 /** Clear us ticker interrupt
  *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_clear_interrupt(void)
+ * {
+ *     // Write to the ICR (interrupt clear register) of the TIMER
+ *     TIMER_ICR = TIMER_ICR_COMPARE_Msk;
+ * }
+ * @endcode
  */
 void us_ticker_clear_interrupt(void);
+
+/** Set pending interrupt that should be fired right away.
+ *
+ * The ticker should be initialized prior calling this function.
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_fire_interrupt(void)
+ * {
+ *     NVIC_SetPendingIRQ(TIMER_IRQn);
+ * }
+ * @endcode
+ */
+void us_ticker_fire_interrupt(void);
+
+/** Get frequency and counter bits of this ticker.
+ *
+ * Pseudo Code:
+ * @code
+ * const ticker_info_t* us_ticker_get_info()
+ * {
+ *     static const ticker_info_t info = {
+ *         1000000,    // 1 MHz
+ *         32          // 32 bit counter
+ *     };
+ *     return &info;
+ * }
+ * @endcode
+ */
+const ticker_info_t *us_ticker_get_info(void);
 
 /**@}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/mbed_stub.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/mbed_stub.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/mbed_stub.c	(revision 374)
@@ -0,0 +1,288 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
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+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+
+/*
+ *		ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+ */
+
+#include <kernel.h>
+#include <sil.h>
+#include "us_ticker_api.h"
+#include <sys/types.h>
+#include <errno.h>
+#include "kernel_cfg.h"
+#include "t_syslog.h"
+
+int main()
+{
+	const char *const args[] = {
+		1,
+		"asp3",
+		NULL,
+		NULL
+	};
+	musl_start(args);
+	return 0;
+}
+
+void wait_us(int us);
+
+void wait(float s)
+{
+	wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms)
+{
+	wait_us(ms * 1000);
+}
+
+void wait_us(int us)
+{
+	ER ercd;
+
+	ercd = dly_tsk(us);
+	if (ercd == E_CTX){
+		uint32_t start = us_ticker_read();
+		while ((us_ticker_read() - start) < (uint32_t)us);
+	}
+}
+
+int32_t IRQ_Initialize (void)
+{
+  GIC_Enable();
+  return (0);
+}
+
+__attribute__((weak))
+long SYS_poll()
+{
+	return -ENOSYS;
+}
+
+__attribute__((weak))
+long SYS_open()
+{
+	return -ENOSYS;
+}
+
+void *tid_address;
+
+__attribute__((weak))
+long SYS_set_tid_address(long a) {
+	tid_address = (void *)a;
+	return 0;
+}
+
+__attribute__((weak))
+long ARM_SYS_set_tls(long a)
+{
+	__asm__ __volatile__("mcr p15,0,%0,c13,c0,3" :: "r"(a));
+	return 0;
+}
+
+__attribute__((weak))
+long SYS_exit_group()
+{
+	ext_ker();
+	return 0;
+}
+
+__attribute__((weak))
+long SYS_exit()
+{
+	ext_ker();
+	return 0;
+}
+
+__attribute__((weak))
+long SYS_futex(long a, long b, long c, long d, long e, long f) {
+	//int futex(int *uaddr, int op, int val, const struct timespec *timeout, int *uaddr2, int val3);
+	return -ENOSYS;
+}
+
+#ifndef _MSC_VER
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+extern uint32_t __end__;
+#else
+uint8_t __HeapBase[14 * 4096];
+#define __HeapLimit __HeapBase[sizeof(__HeapBase)]
+#endif
+
+void *_sbrk(int incr)
+{
+    static unsigned char *heap = (unsigned char *)&__end__;
+    unsigned char        *prev_heap = heap;
+    unsigned char        *new_heap = heap + incr;
+
+    if (new_heap >= (unsigned char *)&__HeapLimit) {
+        errno = ENOMEM;
+        return (void *) -1;
+    }
+
+    heap = new_heap;
+    return (void *) prev_heap;
+}
+
+__attribute__((weak))
+void *SYS_brk(void *addr)
+{
+	if (addr == 0) {
+		return (void *)(&__HeapBase);
+	}
+	if ((addr >= (void *)&__HeapBase) && (addr < (void *)&__HeapLimit)) {
+		return addr;
+	}
+	return (void *)-1;
+}
+
+__attribute__((weak))
+void *SYS_mmap2(void *start, size_t length, int prot, int flags, int fd, off_t pgoffset)
+{
+	if (fd != -1)
+		return (void *)-EINVAL;
+
+	if ((length >= 0) && (length <= sizeof(&__HeapBase))) {
+		return &__HeapBase;
+	}
+	return (void *)-1;
+}
+
+__attribute__((weak))
+int SYS_mprotect(void *addr, size_t len, int prot)
+{
+	//if ((addr >= (void *)&__HeapBase) && (addr + len < (void *)&__HeapLimit)) {
+		return 0;
+	//}
+	//return -1;
+}
+
+__attribute__((weak))
+long SYS_madvise()
+{
+	return -ENOSYS;
+}
+
+__attribute__((weak))
+long SYS_mremap()
+{
+	return -ENOSYS;
+}
+
+__attribute__((weak))
+long SYS_munmap()
+{
+	return -ENOSYS;
+}
+
+int malloc_lock_sem_count[TNUM_TSKID];
+
+void __malloc_lock(struct _reent *_r)
+{
+	ER ercd;
+	ID tskid = 0;
+
+	ercd = get_tid(&tskid);
+	if (ercd != E_OK) {
+		goto error;
+	}
+
+	if (malloc_lock_sem_count[tskid - 1] == 0) {
+		ercd = wai_sem(SEM_MALLOC);
+		if (ercd != E_OK) {
+			goto error;
+		}
+	}
+
+	malloc_lock_sem_count[tskid - 1]++;
+	return;
+error:
+	syslog(LOG_ERROR, "%s (%d) __malloc_lock error.",
+		itron_strerror(ercd), SERCD(ercd));
+	asm("bkpt #0");
+	while(0);
+}
+
+void __malloc_unlock(struct _reent *_r)
+{
+	ER ercd;
+	ID tskid = 0;
+	int count;
+
+	ercd = get_tid(&tskid);
+	if (ercd != E_OK) {
+		goto error;
+	}
+
+	malloc_lock_sem_count[tskid - 1]--;
+	if (malloc_lock_sem_count[tskid - 1] > 0)
+		return;
+
+	if (malloc_lock_sem_count[tskid - 1] < 0) {
+		goto error;
+	}
+
+	ercd = sig_sem(SEM_MALLOC);
+	if (ercd != E_OK) {
+		goto error;
+	}
+	return;
+error:
+	syslog(LOG_ERROR, "%s (%d) __malloc_unlock error.",
+		itron_strerror(ercd), SERCD(ercd));
+	asm("bkpt #0");
+	while(0);
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/mbed_stub.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/mbed_stub.cfg	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/mbed_stub.cfg	(revision 374)
@@ -0,0 +1,7 @@
+/*
+ *		mbedç¨ã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ *
+ *  $Id$
+ */
+
+CRE_SEM(SEM_MALLOC, { TA_TPRI, 1, 1 });
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_assert.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_assert.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_assert.h	(revision 374)
@@ -2,4 +2,8 @@
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_Assert Assert macros
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -40,4 +44,17 @@
 #endif
 
+/** MBED_ASSERT
+ *  Declare runtime assertions: results in runtime error if condition is false
+ *
+ *  @note
+ *  Use of MBED_ASSERT is limited to Debug and Develop builds.
+ *
+ *  @code
+ *
+ *  int Configure(serial_t *obj) {
+ *      MBED_ASSERT(obj);
+ *  }
+ *  @endcode
+ */
 #ifdef NDEBUG
 #define MBED_ASSERT(expr) ((void)0)
@@ -112,2 +129,5 @@
 
 /** @}*/
+
+/**@}*/
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_board.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_board.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_board.c	(revision 374)
@@ -27,45 +27,31 @@
 #endif
 
-WEAK void mbed_die(void) {
+WEAK void mbed_die(void)
+{
 #if !defined (NRF51_H) && !defined(TARGET_EFM32)
     core_util_critical_section_enter();
 #endif
-#if   (DEVICE_ERROR_RED == 1)
-    gpio_t led_red; gpio_init_out(&led_red, LED_RED);
-#elif (DEVICE_ERROR_PATTERN == 1)
-    gpio_t led_1; gpio_init_out(&led_1, LED1);
-    gpio_t led_2; gpio_init_out(&led_2, LED2);
-    gpio_t led_3; gpio_init_out(&led_3, LED3);
-    gpio_t led_4; gpio_init_out(&led_4, LED4);
-#endif
+    gpio_t led_err;
+    gpio_init_out(&led_err, LED1);
 
     while (1) {
-#if   (DEVICE_ERROR_RED == 1)
-        gpio_write(&led_red, 1);
+        for (int i = 0; i < 4; ++i) {
+            gpio_write(&led_err, 1);
+            wait_ms(150);
+            gpio_write(&led_err, 0);
+            wait_ms(150);
+        }
 
-#elif (DEVICE_ERROR_PATTERN == 1)
-        gpio_write(&led_1, 1);
-        gpio_write(&led_2, 0);
-        gpio_write(&led_3, 0);
-        gpio_write(&led_4, 1);
-#endif
-
-        wait_ms(150);
-
-#if   (DEVICE_ERROR_RED == 1)
-        gpio_write(&led_red, 0);
-
-#elif (DEVICE_ERROR_PATTERN == 1)
-        gpio_write(&led_1, 0);
-        gpio_write(&led_2, 1);
-        gpio_write(&led_3, 1);
-        gpio_write(&led_4, 0);
-#endif
-
-        wait_ms(150);
+        for (int i = 0; i < 4; ++i) {
+            gpio_write(&led_err, 1);
+            wait_ms(400);
+            gpio_write(&led_err, 0);
+            wait_ms(400);
+        }
     }
 }
 
-void mbed_error_printf(const char* format, ...) {
+void mbed_error_printf(const char *format, ...)
+{
     va_list arg;
     va_start(arg, format);
@@ -74,6 +60,6 @@
 }
 
-#ifdef NTSHALL_MBED_API
-void mbed_error_vfprintf(const char * format, va_list arg) {
+void mbed_error_vfprintf(const char *format, va_list arg)
+{
 #if DEVICE_SERIAL
 #define ERROR_BUF_SIZE      (128)
@@ -89,5 +75,5 @@
         for (int i = 0; i < size; i++) {
             if (buffer[i] == '\n' && stdio_out_prev != '\r') {
-                 serial_putc(&stdio_uart, '\r');
+                serial_putc(&stdio_uart, '\r');
             }
             serial_putc(&stdio_uart, buffer[i]);
@@ -103,3 +89,2 @@
 #endif
 }
-#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_critical.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_critical.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_critical.c	(revision 374)
@@ -18,14 +18,31 @@
 /* Declare __STDC_LIMIT_MACROS so stdint.h defines UINT32_MAX when using C++ */
 #define __STDC_LIMIT_MACROS
-#include "platform/mbed_critical.h"
+#include "hal/critical_section_api.h"
 
 #include "cmsis.h"
 #include "platform/mbed_assert.h"
+#include "platform/mbed_critical.h"
 #include "platform/mbed_toolchain.h"
 
-#define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
-
-static volatile uint32_t interrupt_enable_counter = 0;
-static volatile bool critical_interrupts_disabled = false;
+// if __EXCLUSIVE_ACCESS rtx macro not defined, we need to get this via own-set architecture macros
+#ifndef MBED_EXCLUSIVE_ACCESS
+#ifndef __EXCLUSIVE_ACCESS
+#if ((__ARM_ARCH_7M__      == 1U) || \
+    (__ARM_ARCH_7EM__     == 1U) || \
+    (__ARM_ARCH_8M_BASE__ == 1U) || \
+    (__ARM_ARCH_8M_MAIN__ == 1U)) || \
+    (__ARM_ARCH_7A__ == 1U)
+#define MBED_EXCLUSIVE_ACCESS      1U
+#elif (__ARM_ARCH_6M__ == 1U)
+#define MBED_EXCLUSIVE_ACCESS      0U
+#else
+#error "Unknown architecture for exclusive access"
+#endif
+#else
+#define MBED_EXCLUSIVE_ACCESS __EXCLUSIVE_ACCESS
+#endif
+#endif
+
+static volatile uint32_t critical_section_reentrancy_counter = 0;
 
 bool core_util_are_interrupts_enabled(void)
@@ -38,156 +55,155 @@
 }
 
-MBED_WEAK void core_util_critical_section_enter(void)
-{
-    bool interrupts_disabled = !core_util_are_interrupts_enabled();
-    __disable_irq();
-
-    /* Save the interrupt disabled state as it was prior to any nested critical section lock use */
-    if (!interrupt_enable_counter) {
-        critical_interrupts_disabled = interrupts_disabled;
-    }
-
-    /* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
-       are enabled, then something has gone badly wrong thus assert an error.
-    */
-    MBED_ASSERT(interrupt_enable_counter < UINT32_MAX); 
-// FIXME
-#ifndef   FEATURE_UVISOR
-    if (interrupt_enable_counter > 0) {
-        MBED_ASSERT(interrupts_disabled);
-    }
-#else
-#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
-#endif /* FEATURE_UVISOR */
-    interrupt_enable_counter++;
-}
-
-MBED_WEAK void core_util_critical_section_exit(void)
-{
-    /* If critical_section_enter has not previously been called, do nothing */
-    if (interrupt_enable_counter) {
-
-// FIXME
-#ifndef   FEATURE_UVISOR
-        bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
-
-        MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
-#else
-#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
-#endif /* FEATURE_UVISOR */
-
-        interrupt_enable_counter--;
-
-        /* Only re-enable interrupts if we are exiting the last of the nested critical sections and
-           interrupts were enabled on entry to the first critical section.
-        */
-        if (!interrupt_enable_counter && !critical_interrupts_disabled) {
-            __enable_irq();
+bool core_util_is_isr_active(void)
+{
+#if defined(__CORTEX_A9)
+    switch (__get_CPSR() & 0x1FU) {
+        case CPSR_M_USR:
+        case CPSR_M_SYS:
+            return false;
+        case CPSR_M_SVC:
+        default:
+            return true;
+    }
+#else
+    return (__get_IPSR() != 0U);
+#endif
+}
+
+bool core_util_in_critical_section(void)
+{
+    return hal_in_critical_section();
+}
+
+void core_util_critical_section_enter(void)
+{
+    // If the reentrancy counter overflows something has gone badly wrong.
+    MBED_ASSERT(critical_section_reentrancy_counter < UINT32_MAX);
+
+    hal_critical_section_enter();
+
+    ++critical_section_reentrancy_counter;
+}
+
+void core_util_critical_section_exit(void)
+{
+
+    // If critical_section_enter has not previously been called, do nothing
+    if (critical_section_reentrancy_counter == 0) {
+        return;
+    }
+
+    --critical_section_reentrancy_counter;
+
+    if (critical_section_reentrancy_counter == 0) {
+        hal_critical_section_exit();
+    }
+}
+
+#if MBED_EXCLUSIVE_ACCESS
+
+/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
+#if defined (__CC_ARM)
+#pragma diag_suppress 3731
+#endif
+
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+    do {
+        uint8_t currentValue = __LDREXB(ptr);
+        if (currentValue != *expectedCurrentValue) {
+            *expectedCurrentValue = currentValue;
+            __CLREX();
+            return false;
         }
-    }
-}
-
-#if EXCLUSIVE_ACCESS
-
-/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
-#if defined (__CC_ARM) 
-#pragma diag_suppress 3731
-#endif
-
-bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
-{
-    uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
-    if (currentValue != *expectedCurrentValue) {
-        *expectedCurrentValue = currentValue;
-        __CLREX();
-        return false;
-    }
-
-    return !__STREXB(desiredValue, (volatile uint8_t*)ptr);
-}
-
-bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
-{
-    uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
-    if (currentValue != *expectedCurrentValue) {
-        *expectedCurrentValue = currentValue;
-        __CLREX();
-        return false;
-    }
-
-    return !__STREXH(desiredValue, (volatile uint16_t*)ptr);
-}
-
-
-bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
-{
-    uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
-    if (currentValue != *expectedCurrentValue) {
-        *expectedCurrentValue = currentValue;
-        __CLREX();
-        return false;
-    }
-
-    return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
-}
-
-uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+    } while (__STREXB(desiredValue, ptr));
+    return true;
+}
+
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+    do {
+        uint16_t currentValue = __LDREXH(ptr);
+        if (currentValue != *expectedCurrentValue) {
+            *expectedCurrentValue = currentValue;
+            __CLREX();
+            return false;
+        }
+    } while (__STREXH(desiredValue, ptr));
+    return true;
+}
+
+
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+    do {
+        uint32_t currentValue = __LDREXW(ptr);
+        if (currentValue != *expectedCurrentValue) {
+            *expectedCurrentValue = currentValue;
+            __CLREX();
+            return false;
+        }
+    } while (__STREXW(desiredValue, ptr));
+    return true;
+}
+
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
     do {
-        newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta;
-    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
-    return newValue;
-}
-
-uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+        newValue = __LDREXB(valuePtr) + delta;
+    } while (__STREXB(newValue, valuePtr));
+    return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
     do {
-        newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta;
-    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
-    return newValue;
-}
-
-uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+        newValue = __LDREXH(valuePtr) + delta;
+    } while (__STREXH(newValue, valuePtr));
+    return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
     do {
-        newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta;
-    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
-    return newValue;
-}
-
-
-uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+        newValue = __LDREXW(valuePtr) + delta;
+    } while (__STREXW(newValue, valuePtr));
+    return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
     do {
-        newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta;
-    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
-    return newValue;
-}
-
-uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+        newValue = __LDREXB(valuePtr) - delta;
+    } while (__STREXB(newValue, valuePtr));
+    return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
     do {
-        newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta;
-    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
-    return newValue;
-}
-
-uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+        newValue = __LDREXH(valuePtr) - delta;
+    } while (__STREXH(newValue, valuePtr));
+    return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
     do {
-        newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta;
-    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
-    return newValue;
-}
-
-#else
-
-bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+        newValue = __LDREXW(valuePtr) - delta;
+    } while (__STREXW(newValue, valuePtr));
+    return newValue;
+}
+
+#else
+
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
 {
     bool success;
@@ -206,5 +222,5 @@
 }
 
-bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
 {
     bool success;
@@ -224,5 +240,5 @@
 
 
-bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
 {
     bool success;
@@ -242,5 +258,5 @@
 
 
-uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
@@ -252,5 +268,5 @@
 }
 
-uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
@@ -262,5 +278,5 @@
 }
 
-uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
@@ -273,5 +289,5 @@
 
 
-uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
@@ -283,5 +299,5 @@
 }
 
-uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
@@ -293,5 +309,5 @@
 }
 
-uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
@@ -306,17 +322,20 @@
 
 
-bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
+bool core_util_atomic_cas_ptr(void *volatile *ptr, void **expectedCurrentValue, void *desiredValue)
+{
     return core_util_atomic_cas_u32(
-            (uint32_t *)ptr,
-            (uint32_t *)expectedCurrentValue,
-            (uint32_t)desiredValue);
-}
-
-void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
-    return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
-}
-
-void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
-    return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
-}
-
+               (volatile uint32_t *)ptr,
+               (uint32_t *)expectedCurrentValue,
+               (uint32_t)desiredValue);
+}
+
+void *core_util_atomic_incr_ptr(void *volatile *valuePtr, ptrdiff_t delta)
+{
+    return (void *)core_util_atomic_incr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta);
+}
+
+void *core_util_atomic_decr_ptr(void *volatile *valuePtr, ptrdiff_t delta)
+{
+    return (void *)core_util_atomic_decr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta);
+}
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_critical.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_critical.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_critical.h	(revision 374)
@@ -1,5 +1,3 @@
 
-/** \addtogroup platform */
-/** @{*/
 /*
  * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
@@ -30,9 +28,15 @@
 #endif
 
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_critical critical section function
+ * @{
+ */
 
 /** Determine the current interrupts enabled state
   *
   * This function can be called to determine whether or not interrupts are currently enabled.
-  * \note
+  * @note
   * NOTE:
   * This function works for both cortex-A and cortex-M, although the underlyng implementation
@@ -42,8 +46,19 @@
 bool core_util_are_interrupts_enabled(void);
 
+/** Determine if this code is executing from an interrupt
+  *
+  * This function can be called to determine if the code is running on interrupt context.
+  * @note
+  * NOTE:
+  * This function works for both cortex-A and cortex-M, although the underlyng implementation
+  * differs.
+  * @return true if in an isr, false otherwise
+  */
+bool core_util_is_isr_active(void);
+
 /** Mark the start of a critical section
   *
   * This function should be called to mark the start of a critical section of code.
-  * \note
+  * @note
   * NOTES:
   * 1) The use of this style of critical section is targetted at C based implementations.
@@ -58,5 +73,5 @@
   *
   * This function should be called to mark the end of a critical section of code.
-  * \note
+  * @note
   * NOTES:
   * 1) The use of this style of critical section is targetted at C based implementations.
@@ -69,4 +84,11 @@
 
 /**
+ * Determine if we are currently in a critical section
+ *
+ * @return true if in a critical section, false otherwise.
+ */
+bool core_util_in_critical_section(void);
+
+/**
  * Atomic compare and set. It compares the contents of a memory location to a
  * given value and, only if they are the same, modifies the contents of that
@@ -83,5 +105,5 @@
  *                              expected current value of the data being set atomically.
  *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
+ *                              @note: This is an in-out parameter. In the
  *                              failure case of atomic_cas (where the
  *                              destination isn't set), the pointee of expectedCurrentValue is
@@ -106,6 +128,6 @@
  * }
  *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
@@ -118,6 +140,10 @@
  *     return value + a
  * }
- */
-bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ */
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
 
 /**
@@ -136,5 +162,5 @@
  *                              expected current value of the data being set atomically.
  *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
+ *                              @note: This is an in-out parameter. In the
  *                              failure case of atomic_cas (where the
  *                              destination isn't set), the pointee of expectedCurrentValue is
@@ -159,6 +185,6 @@
  * }
  *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
@@ -171,6 +197,10 @@
  *     return value + a
  * }
- */
-bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ */
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
 
 /**
@@ -189,5 +219,5 @@
  *                              expected current value of the data being set atomically.
  *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
+ *                              @note: This is an in-out parameter. In the
  *                              failure case of atomic_cas (where the
  *                              destination isn't set), the pointee of expectedCurrentValue is
@@ -212,6 +242,6 @@
  * }
  *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
@@ -223,7 +253,11 @@
  *     }
  *     return value + a
- * }
- */
-bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ * }
+ */
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
 
 /**
@@ -242,5 +276,5 @@
  *                              expected current value of the data being set atomically.
  *                              The computed 'desiredValue' should be a function of this current value.
- *                              @Note: This is an in-out parameter. In the
+ *                              @note: This is an in-out parameter. In the
  *                              failure case of atomic_cas (where the
  *                              destination isn't set), the pointee of expectedCurrentValue is
@@ -265,6 +299,6 @@
  * }
  *
- * @Note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is still updated with the current value.
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
  * This property helps writing concise code for the following incr:
  *
@@ -277,6 +311,10 @@
  *     return value + a
  * }
- */
-bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ */
+bool core_util_atomic_cas_ptr(void *volatile *ptr, void **expectedCurrentValue, void *desiredValue);
 
 /**
@@ -286,5 +324,5 @@
  * @return          The new incremented value.
  */
-uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta);
 
 /**
@@ -294,5 +332,5 @@
  * @return          The new incremented value.
  */
-uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta);
 
 /**
@@ -302,5 +340,5 @@
  * @return          The new incremented value.
  */
-uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta);
 
 /**
@@ -313,5 +351,5 @@
  *       and the pointer is incremented by bytes.
  */
-void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
+void *core_util_atomic_incr_ptr(void *volatile *valuePtr, ptrdiff_t delta);
 
 /**
@@ -321,5 +359,5 @@
  * @return          The new decremented value.
  */
-uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta);
 
 /**
@@ -329,5 +367,5 @@
  * @return          The new decremented value.
  */
-uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta);
 
 /**
@@ -337,5 +375,5 @@
  * @return          The new decremented value.
  */
-uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta);
 
 /**
@@ -348,12 +386,15 @@
  *       and the pointer is decremented by bytes
  */
-void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
+void *core_util_atomic_decr_ptr(void *volatile *valuePtr, ptrdiff_t delta);
 
 #ifdef __cplusplus
 } // extern "C"
 #endif
-
+/**@}*/
+
+/**@}*/
 
 #endif // __MBED_UTIL_CRITICAL_H__
 
-/** @}*/
+
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_debug.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_debug.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_debug.h	(revision 374)
@@ -0,0 +1,81 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_debug Debug functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...)
+{
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+    va_list args;
+    va_start(args, format);
+    vfprintf(stderr, format, args);
+    va_end(args);
+#endif
+}
+
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (== 0) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (!= 0)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...)
+{
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+    if (condition) {
+        va_list args;
+        va_start(args, format);
+        vfprintf(stderr, format, args);
+        va_end(args);
+    }
+#endif
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**@}*/
+
+/**@}*/
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error.c	(revision 374)
@@ -16,13 +16,77 @@
 #include <stdlib.h>
 #include <stdarg.h>
+#include <string.h>
 #include "device.h"
-#include "platform/mbed_toolchain.h"
+#include "platform/mbed_critical.h"
 #include "platform/mbed_error.h"
+#include "platform/mbed_error_hist.h"
 #include "platform/mbed_interface.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "rtx_os.h"
+#endif
+
 #if DEVICE_STDIO_MESSAGES
 #include <stdio.h>
 #endif
 
-WEAK void error(const char* format, ...) {
+#define MBED_CONF_PLATFORM_ERROR_DECODE_HTTP_URL_STR                          "\nFor more info, visit: https://armmbed.github.io/mbedos-error/?error=0x%08X"                   // set by library:platform
+
+//Helper macro to get the current SP
+#define GET_CURRENT_SP(sp)                                                          \
+                        {                                                           \
+                            /*If in Handler mode we are always using MSP*/          \
+                            if ( __get_IPSR() != 0U ) {                             \
+                                sp = __get_MSP();                                   \
+                            } else {                                                \
+                                /*Look into CONTROL.SPSEL value*/                   \
+                                if ((__get_CONTROL() & 2U) == 0U) {                 \
+                                    sp = __get_MSP();/*Read MSP*/                   \
+                                } else {                                            \
+                                    sp = __get_PSP();/*Read PSP*/                   \
+                                }                                                   \
+                            }                                                       \
+                        }
+
+#ifndef NDEBUG
+#define ERROR_REPORT(ctx, error_msg) print_error_report(ctx, error_msg)
+#else
+#define ERROR_REPORT(ctx, error_msg) ((void) 0)
+#endif
+
+static uint8_t error_in_progress = 0;
+static int error_count = 0;
+static mbed_error_ctx first_error_ctx = {0};
+static mbed_error_ctx last_error_ctx = {0};
+static mbed_error_hook_t error_hook = NULL;
+static void print_error_report(mbed_error_ctx *ctx, const char *);
+static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller);
+
+//Helper function to halt the system
+static void mbed_halt_system(void)
+{
+    //If not in ISR context exit, otherwise spin on WFI
+    if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+        for (;;) {
+            __WFI();
+        }
+    } else {
+        //exit eventually calls mbed_die
+        exit(1);
+    }
+}
+
+WEAK void error(const char *format, ...)
+{
+
+    // Prevent recursion if error is called again
+    if (error_in_progress) {
+        return;
+    }
+
+    //Call handle_error/print_error_report permanently setting error_in_progress flag
+    handle_error(MBED_ERROR_UNKNOWN, 0, NULL, 0, MBED_CALLER_ADDR());
+    ERROR_REPORT(&last_error_ctx, "Fatal Run-time error");
+    error_in_progress = 1;
+
 #ifndef NDEBUG
     va_list arg;
@@ -33,2 +97,375 @@
     exit(1);
 }
+
+//Set an error status with the error handling system
+static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller)
+{
+    mbed_error_ctx current_error_ctx;
+
+    //Error status should always be < 0
+    if (error_status >= 0) {
+        //This is a weird situation, someone called mbed_error with invalid error code.
+        //We will still handle the situation but change the error code to ERROR_INVALID_ARGUMENT, atleast the context will have info on who called it
+        error_status = MBED_ERROR_INVALID_ARGUMENT;
+    }
+
+    //Prevent corruption by holding out other callers
+    //and we also need this until we remove the "error" call completely
+    while (error_in_progress == 1);
+
+    //Use critsect here, as we don't want inadvertant modification of this global variable
+    core_util_critical_section_enter();
+    error_in_progress = 1;
+    core_util_critical_section_exit();
+
+    //Increment error count
+    error_count++;
+
+    //Clear the context capturing buffer
+    memset(&current_error_ctx, sizeof(mbed_error_ctx), 0);
+    //Capture error information
+    current_error_ctx.error_status = error_status;
+    current_error_ctx.error_address = (uint32_t)caller;
+    current_error_ctx.error_value = error_value;
+#if 0 //def MBED_CONF_RTOS_PRESENT
+    //Capture thread info
+    osRtxThread_t *current_thread = osRtxInfo.thread.run.curr;
+    current_error_ctx.thread_id = (uint32_t)current_thread;
+    current_error_ctx.thread_entry_address = (uint32_t)current_thread->thread_addr;
+    current_error_ctx.thread_stack_size = current_thread->stack_size;
+    current_error_ctx.thread_stack_mem = (uint32_t)current_thread->stack_mem;
+#ifdef TARGET_CORTEX_M
+    GET_CURRENT_SP(current_error_ctx.thread_current_sp);
+#endif //TARGET_CORTEX_M
+
+#endif //MBED_CONF_RTOS_PRESENT
+
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+    //Capture filename/linenumber if provided
+    //Index for tracking error_filename
+    memset(&current_error_ctx.error_filename, 0, MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN);
+    strncpy(current_error_ctx.error_filename, filename, MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN);
+    current_error_ctx.error_line_number = line_number;
+#endif
+
+    //Capture the fist system error and store it
+    if (error_count == 1) { //first error
+        memcpy(&first_error_ctx, &current_error_ctx, sizeof(mbed_error_ctx));
+    }
+
+    //copy this error to last error
+    memcpy(&last_error_ctx, &current_error_ctx, sizeof(mbed_error_ctx));
+
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+    //Log the error with error log
+    mbed_error_hist_put(&current_error_ctx);
+#endif
+
+    //Call the error hook if available
+    if (error_hook != NULL) {
+        error_hook(&last_error_ctx);
+    }
+
+    error_in_progress = 0;
+
+    return MBED_SUCCESS;
+}
+
+//Return the first error
+mbed_error_status_t mbed_get_first_error(void)
+{
+    //return the first error recorded
+    return first_error_ctx.error_status;
+}
+
+//Return the last error
+mbed_error_status_t mbed_get_last_error(void)
+{
+    //return the last error recorded
+    return last_error_ctx.error_status;
+}
+
+//Gets the current error count
+int mbed_get_error_count(void)
+{
+    //return the current error count
+    return error_count;
+}
+
+//Sets a fatal error
+mbed_error_status_t mbed_warning(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number)
+{
+    return handle_error(error_status, error_value, filename, line_number, MBED_CALLER_ADDR());
+}
+
+//Sets a fatal error, this function is marked WEAK to be able to override this for some tests
+WEAK mbed_error_status_t mbed_error(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number)
+{
+    //set the error reported and then halt the system
+    if (MBED_SUCCESS != handle_error(error_status, error_value, filename, line_number, MBED_CALLER_ADDR())) {
+        return MBED_ERROR_FAILED_OPERATION;
+    }
+
+    //On fatal errors print the error context/report
+    ERROR_REPORT(&last_error_ctx, error_msg);
+    mbed_halt_system();
+
+    return MBED_ERROR_FAILED_OPERATION;
+}
+
+//Register an application defined callback with error handling
+mbed_error_status_t mbed_set_error_hook(mbed_error_hook_t error_hook_in)
+{
+    //register the new hook/callback
+    if (error_hook_in != NULL)  {
+        error_hook = error_hook_in;
+        return MBED_SUCCESS;
+    }
+
+    return MBED_ERROR_INVALID_ARGUMENT;
+}
+
+//Retrieve the first error context from error log
+mbed_error_status_t mbed_get_first_error_info(mbed_error_ctx *error_info)
+{
+    memcpy(error_info, &first_error_ctx, sizeof(first_error_ctx));
+    return MBED_SUCCESS;
+}
+
+//Retrieve the last error context from error log
+mbed_error_status_t mbed_get_last_error_info(mbed_error_ctx *error_info)
+{
+    memcpy(error_info, &last_error_ctx, sizeof(mbed_error_ctx));
+    return MBED_SUCCESS;
+}
+
+//Makes an mbed_error_status_t value
+mbed_error_status_t mbed_make_error(mbed_error_type_t error_type, mbed_module_type_t entity, mbed_error_code_t error_code)
+{
+    switch (error_type) {
+        case MBED_ERROR_TYPE_POSIX:
+            if (error_code >= MBED_POSIX_ERROR_BASE && error_code <= MBED_SYSTEM_ERROR_BASE) {
+                return -error_code;
+            }
+            break;
+
+        case MBED_ERROR_TYPE_SYSTEM:
+            if (error_code >= MBED_SYSTEM_ERROR_BASE && error_code <= MBED_CUSTOM_ERROR_BASE) {
+                return MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, entity, error_code);
+            }
+            break;
+
+        case MBED_ERROR_TYPE_CUSTOM:
+            if (error_code >= MBED_CUSTOM_ERROR_BASE) {
+                return MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, entity, error_code);
+            }
+            break;
+
+        default:
+            break;
+    }
+
+    //If we are passed incorrect values return a generic system error
+    return MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_UNKNOWN);
+}
+
+/**
+ * Clears all the last error, error count and all entries in the error log.
+ * @return                      0 or MBED_SUCCESS on success.
+ *
+ */
+mbed_error_status_t mbed_clear_all_errors(void)
+{
+    mbed_error_status_t status = MBED_SUCCESS;
+
+    //Make sure we dont multiple clients resetting
+    core_util_critical_section_enter();
+    //Clear the error and context capturing buffer
+    memset(&last_error_ctx, sizeof(mbed_error_ctx), 0);
+    //reset error count to 0
+    error_count = 0;
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+    status = mbed_error_hist_reset();
+#endif
+    core_util_critical_section_exit();
+
+    return status;
+}
+
+#if MBED_CONF_PLATFORM_ERROR_ALL_THREADS_INFO && defined(MBED_CONF_RTOS_PRESENT)
+/* Prints info of a thread(using osRtxThread_t struct)*/
+static void print_thread(osRtxThread_t *thread)
+{
+    mbed_error_printf("\nState: 0x%08X Entry: 0x%08X Stack Size: 0x%08X Mem: 0x%08X SP: 0x%08X", thread->state, thread->thread_addr, thread->stack_size, (uint32_t)thread->stack_mem, thread->sp);
+}
+
+/* Prints thread info from a list */
+static void print_threads_info(osRtxThread_t *threads)
+{
+    while (threads != NULL) {
+        print_thread(threads);
+        threads = threads->thread_next;
+    }
+}
+#endif
+
+#ifndef NDEBUG
+static void print_error_report(mbed_error_ctx *ctx, const char *error_msg)
+{
+    uint32_t error_code = MBED_GET_ERROR_CODE(ctx->error_status);
+    uint32_t error_module = MBED_GET_ERROR_MODULE(ctx->error_status);
+
+    mbed_error_printf("\n\n++ MbedOS Error Info ++\nError Status: 0x%X Code: %d Module: %d\nError Message: ", ctx->error_status, error_code, error_module);
+
+    switch (error_code) {
+        //These are errors reported by kernel handled from mbed_rtx_handlers
+        case MBED_ERROR_CODE_RTOS_EVENT:
+            mbed_error_printf("Kernel Error: 0x%X, ", ctx->error_value);
+            break;
+
+        case MBED_ERROR_CODE_RTOS_THREAD_EVENT:
+            mbed_error_printf("Thread: 0x%X, ", ctx->error_value);
+            break;
+
+        case MBED_ERROR_CODE_RTOS_MUTEX_EVENT:
+            mbed_error_printf("Mutex: 0x%X, ", ctx->error_value);
+            break;
+
+        case MBED_ERROR_CODE_RTOS_SEMAPHORE_EVENT:
+            mbed_error_printf("Semaphore: 0x%X, ", ctx->error_value);
+            break;
+
+        case MBED_ERROR_CODE_RTOS_MEMORY_POOL_EVENT:
+            mbed_error_printf("MemoryPool: 0x%X, ", ctx->error_value);
+            break;
+
+        case MBED_ERROR_CODE_RTOS_EVENT_FLAGS_EVENT:
+            mbed_error_printf("EventFlags: 0x%X, ", ctx->error_value);
+            break;
+
+        case MBED_ERROR_CODE_RTOS_TIMER_EVENT:
+            mbed_error_printf("Timer: 0x%X, ", ctx->error_value);
+            break;
+
+        case MBED_ERROR_CODE_RTOS_MESSAGE_QUEUE_EVENT:
+            mbed_error_printf("MessageQueue: 0x%X, ", ctx->error_value);
+            break;
+
+        default:
+            //Nothing to do here, just print the error info down
+            break;
+    }
+    mbed_error_printf(error_msg);
+    mbed_error_printf("\nLocation: 0x%X", ctx->error_address);
+
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED && !defined(NDEBUG)
+    if ((NULL != ctx->error_filename[0]) && (ctx->error_line_number != 0)) {
+        //for string, we must pass address of a ptr which has the address of the string
+        mbed_error_printf("\nFile:%s+%d", ctx->error_filename, ctx->error_line_number);
+    }
+#endif
+
+    mbed_error_printf("\nError Value: 0x%X", ctx->error_value);
+#ifdef TARGET_CORTEX_M
+    mbed_error_printf("\nCurrent Thread: Id: 0x%X Entry: 0x%X StackSize: 0x%X StackMem: 0x%X SP: 0x%X ",
+                      ctx->thread_id, ctx->thread_entry_address, ctx->thread_stack_size, ctx->thread_stack_mem, ctx->thread_current_sp);
+#else
+    //For Cortex-A targets we dont have support to capture the current SP
+    mbed_error_printf("\nCurrent Thread: Id: 0x%X Entry: 0x%X StackSize: 0x%X StackMem: 0x%X ",
+                      ctx->thread_id, ctx->thread_entry_address, ctx->thread_stack_size, ctx->thread_stack_mem);
+#endif //TARGET_CORTEX_M
+
+#if MBED_CONF_PLATFORM_ERROR_ALL_THREADS_INFO && defined(MBED_CONF_RTOS_PRESENT)
+    mbed_error_printf("\nNext:");
+    print_thread(osRtxInfo.thread.run.next);
+
+    mbed_error_printf("\nWait:");
+    osRtxThread_t *threads = (osRtxThread_t *)&osRtxInfo.thread.wait_list;
+    print_threads_info(threads);
+
+    mbed_error_printf("\nDelay:");
+    threads = (osRtxThread_t *)&osRtxInfo.thread.delay_list;
+    print_threads_info(threads);
+
+    mbed_error_printf("\nIdle:");
+    threads = (osRtxThread_t *)&osRtxInfo.thread.idle;
+    print_threads_info(threads);
+#endif
+    mbed_error_printf(MBED_CONF_PLATFORM_ERROR_DECODE_HTTP_URL_STR, ctx->error_status);
+    mbed_error_printf("\n-- MbedOS Error Info --\n");
+}
+#endif //ifndef NDEBUG
+
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+//Retrieve the error context from error log at the specified index
+mbed_error_status_t mbed_get_error_hist_info(int index, mbed_error_ctx *error_info)
+{
+    return mbed_error_hist_get(index, error_info);
+}
+
+//Retrieve the error log count
+int mbed_get_error_hist_count(void)
+{
+    return mbed_error_hist_get_count();
+}
+
+mbed_error_status_t mbed_save_error_hist(const char *path)
+{
+    mbed_error_status_t ret = MBED_SUCCESS;
+    mbed_error_ctx ctx = {0};
+    int log_count = mbed_error_hist_get_count();
+    FILE *error_log_file = NULL;
+
+    //Ensure path is valid
+    if (path == NULL) {
+        ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_INVALID_ARGUMENT);
+        goto exit;
+    }
+
+    //Open the file for saving the error log info
+    if ((error_log_file = fopen(path, "w")) == NULL) {
+        ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OPEN_FAILED);
+        goto exit;
+    }
+
+    //First store the first and last errors
+    if (fprintf(error_log_file, "\nFirst Error: Status:0x%x ThreadId:0x%x Address:0x%x Value:0x%x\n",
+                (unsigned int)first_error_ctx.error_status,
+                (unsigned int)first_error_ctx.thread_id,
+                (unsigned int)first_error_ctx.error_address,
+                (unsigned int)first_error_ctx.error_value) <= 0) {
+        ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_WRITE_FAILED);
+        goto exit;
+    }
+
+    if (fprintf(error_log_file, "\nLast Error: Status:0x%x ThreadId:0x%x Address:0x%x Value:0x%x\n",
+                (unsigned int)last_error_ctx.error_status,
+                (unsigned int)last_error_ctx.thread_id,
+                (unsigned int)last_error_ctx.error_address,
+                (unsigned int)last_error_ctx.error_value) <= 0) {
+        ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_WRITE_FAILED);
+        goto exit;
+    }
+
+    //Update with error log info
+    while (--log_count >= 0) {
+        mbed_error_hist_get(log_count, &ctx);
+        //first line of file will be error log count
+        if (fprintf(error_log_file, "\n%d: Status:0x%x ThreadId:0x%x Address:0x%x Value:0x%x\n",
+                    log_count,
+                    (unsigned int)ctx.error_status,
+                    (unsigned int)ctx.thread_id,
+                    (unsigned int)ctx.error_address,
+                    (unsigned int)ctx.error_value) <= 0) {
+            ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_WRITE_FAILED);
+            goto exit;
+        }
+    }
+
+exit:
+    fclose(error_log_file);
+
+    return ret;
+}
+#endif
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error.h	(revision 374)
@@ -1,5 +1,8 @@
-
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_error Error functions
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -20,5 +23,812 @@
 #define MBED_ERROR_H
 
+#include "platform/mbed_retarget.h"
+#include "platform/mbed_toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Define this macro to include filenames in error context. For release builds, do not include filename to save memory.
+ *  MBED_PLATFORM_CONF_ERROR_FILENAME_CAPTURE_ENABLED
+ */
+
+/** Define this macro to enable error history
+ *  MBED_PLATFORM_CONF_ERROR_HIST_ENABLED
+ */
+
+#ifndef MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
+#define MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN            16
+#else //MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
+#if MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN > 64
+//We have to limit this to 64 bytes since we use mbed_error_printf for error reporting
+//and mbed_error_vfprintf uses 128bytes internal buffer which may not be sufficient for anything
+//longer that 64 bytes with the current implementation.
+#error "Unsupported error filename buffer length detected, max supported length is 64 chars. Please change MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN or max-error-filename-len in configuration."
+#endif
+#endif
+
+#define MBED_ERROR_STATUS_CODE_MASK                 (0x0000FFFF)
+#define MBED_ERROR_STATUS_CODE_POS                  (0)
+#define MBED_ERROR_STATUS_CODE_FIELD_SIZE           (16)
+
+#define MBED_ERROR_STATUS_MODULE_MASK               (0x00FF0000)
+#define MBED_ERROR_STATUS_MODULE_POS                (16)
+#define MBED_ERROR_STATUS_MODULE_FIELD_SIZE         (8)
+
+#define MBED_ERROR_STATUS_TYPE_MASK                 (0x60000000)
+#define MBED_ERROR_STATUS_TYPE_POS                  (29)
+#define MBED_ERROR_STATUS_TYPE_FIELD_SIZE           (2)
+
+/* mbed_error_status_t Status Encoding */
+//|31(1 bit) Always Negative|30-29(2 bits)  |28-24              | 23-16(8 bits) |  15-0(16 bits) |
+//|-1                       |TYPE           |(unused/reserved)  | MODULE TYPE   |  ERROR CODE    |
+
+#define MAKE_MBED_ERROR(type, module, error_code)   (mbed_error_status_t)                                                                   \
+                                                    ((0x80000000) |                                                                     \
+                                                    (MBED_ERROR_STATUS_CODE_MASK & (error_code << MBED_ERROR_STATUS_CODE_POS)) |        \
+                                                    (MBED_ERROR_STATUS_MODULE_MASK & (module << MBED_ERROR_STATUS_MODULE_POS)) |        \
+                                                    (MBED_ERROR_STATUS_TYPE_MASK & (type << MBED_ERROR_STATUS_TYPE_POS)))
+
+#define MBED_GET_ERROR_TYPE( error_status )         ((error_status & MBED_ERROR_STATUS_TYPE_MASK) >> MBED_ERROR_STATUS_TYPE_POS)
+#define MBED_GET_ERROR_MODULE( error_status )       ((error_status & MBED_ERROR_STATUS_MODULE_MASK) >> MBED_ERROR_STATUS_MODULE_POS)
+#define MBED_GET_ERROR_CODE( error_status )         (int)((MBED_GET_ERROR_TYPE( error_status ) == MBED_ERROR_TYPE_POSIX)?(-error_status):((error_status & MBED_ERROR_STATUS_CODE_MASK) >> MBED_ERROR_STATUS_CODE_POS))
+
+/** mbed_error_status_t description
+ *
+ * mbed_error_status_t type represents the error status values under MbedOS. mbed_error_status_t values are signed integers and always be negative.\n
+ * Internally its encoded as below with bit-fields representing error type, module and error code:\n\n
+ * mbed_error_status_t Status Encoding:\n
+ *
+ \verbatim
+ | 31 Always Negative | 30-29(2 bits)  | 28-24              | 23-16(8 bits) | 15-0(16 bits) |
+ | -1                 | TYPE           | (unused/reserved)  | MODULE TYPE    | ERROR CODE    |
+ \endverbatim
+ *
+ * The error status value range for each error type is as follows:\n
+ *   Posix Error Status-es  - 0xFFFFFFFF to 0xFFFFFF01(-1 -255) - This corresponds to Posix error codes represented as negative.\n
+ *   System Error Status-es - 0x80XX0100 to 0x80XX0FFF - This corresponds to System error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n
+ *   Custom Error Status-es - 0xA0XX1000 to 0xA0XXFFFF - This corresponds to Custom error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n\n
+ *
+ * The ERROR CODE(values encoded into ERROR CODE bit-field in mbed_error_status_t) value range for each error type is also seperated as below:\n
+ *   Posix Error Codes  - 1 to 255.\n
+ *   System Error Codes - 256 to 4095.\n
+ *   Custom Error Codes - 4096 to 65535.\n
+ *
+ * @note Posix error codes are always encoded as negative of their actual value. For example, EPERM is encoded as -EPERM.
+ *       And, the MODULE TYPE for Posix error codes are always encoded as MBED_MODULE_UNKNOWN.\n
+ *       This is to enable easy injection of Posix error codes into MbedOS error handling system without altering the actual Posix error values.\n
+ *       Accordingly, Posix error codes are represented as -1 to -255 under MbedOS error status representation.
+ */
+typedef int mbed_error_status_t;
+
+/**
+ * Macro for defining a Posix error status. This macro is mainly used to define Posix error values in mbed_error_code_t enumeration.
+ * @param  error_name       Name of the error without the ERROR_ prefix
+ * @param  error_code       Error code value to be used, must be between 1 and 255(inclusive).
+ *
+ */
+#define MBED_DEFINE_POSIX_ERROR( error_name, error_code )   \
+                     MBED_ERROR_CODE_##error_name = error_code,  \
+                     MBED_ERROR_##error_name = -(MBED_POSIX_ERROR_BASE + error_code)
+
+/**
+ * Macro for defining a System error status. This macro is used to define System error values in mbed_error_code_t enumeration.
+ * @param  error_name       Name of the error without the ERROR_ prefix
+ * @param  error_code       Error code value to be used, must be between 256 and 4096(inclusive).
+ *
+ */
+#define MBED_DEFINE_SYSTEM_ERROR( error_name, error_code )   \
+                      MBED_ERROR_CODE_##error_name = MBED_SYSTEM_ERROR_BASE + error_code,  \
+                      MBED_ERROR_##error_name = MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_##error_name)
+
+/**
+ * Macro for defining a Custom error status. This macro is used to define custom error values in mbed_error_code_t enumeration.
+ * @param  error_name       Name of the error without the ERROR_ prefix
+ * @param  error_code       Error code value to be used, must be between 4097 and 65535(inclusive).
+ *
+ */
+#define MBED_DEFINE_CUSTOM_ERROR( error_name, error_code )   \
+                      MBED_ERROR_CODE_##error_name = MBED_CUSTOM_ERROR_BASE + error_code,  \
+                      MBED_ERROR_##error_name = MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_##error_name)
+
+
+/**
+ * Macros for setting a system warning. These macros will log the error, Its a wrapper for calling mbed_warning API.
+ * There are 2 versions of this macro. MBED_WARNING takes status and message. MBED_WARNING1 takes an additional context specific argument
+ * @param  error_status     mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param  error_msg        The error message to be printed out to STDIO/Serial.
+ * @param  error_value      Value associated with the error status. This would depend on error code/error scenario.
+ *
+ * @code
+ *
+ * MBED_WARNING( ERROR_INVALID_SIZE, "MyDriver: Invalid size in read" )
+ * MBED_WARNING1( ERROR_INVALID_SIZE, "MyDriver: Invalid size in read", size_val )
+ *
+ * @endcode
+ * @note The macro calls mbed_warning API with filename and line number info without caller explicitly passing them.
+ *        Since this macro is a wrapper for mbed_warning API callers should process the return value from this macro which is the return value from calling mbed_error API.
+ *
+ */
+#ifdef NDEBUG
+#define MBED_WARNING1( error_status, error_msg, error_value )         mbed_warning( error_status, (const char *)NULL, (uint32_t)error_value, NULL, 0 )
+#define MBED_WARNING( error_status, error_msg )                       mbed_warning( error_status, (const char *)NULL, (uint32_t)0,           NULL, 0 )
+#else //NDEBUG
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_WARNING1( error_status, error_msg, error_value )     mbed_warning( error_status, (const char *)error_msg, (uint32_t)error_value, (const char *)MBED_FILENAME, __LINE__ )
+#define MBED_WARNING( error_status, error_msg )                   mbed_warning( error_status, (const char *)error_msg, (uint32_t)0          , (const char *)MBED_FILENAME, __LINE__ )
+#else //MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_WARNING1( error_status, error_msg, error_value )     mbed_warning( error_status, (const char *)error_msg, (uint32_t)error_value, NULL, 0 )
+#define MBED_WARNING( error_status, error_msg )                   mbed_warning( error_status, (const char *)error_msg, (uint32_t)0,           NULL, 0 )
+#endif
+#endif
+
+/**
+ * Macros for setting a fatal system error. These macros will log the error, prints the error report and halts the system. Its a wrapper for calling mbed_error API.
+ * There are 2 versions of this macro. MBED_ERROR takes status and message. MBED_ERROR1 takes an additional context specific argument
+ * @param  error_status     mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param  error_msg        The error message to be printed out to STDIO/Serial.
+ * @param  error_value      Value associated with the error status. This would depend on error code/error scenario. Only available with MBED_ERROR1
+ * @return                  0 or MBED_SUCCESS.
+ *                          MBED_ERROR_INVALID_ARGUMENT if called with invalid error status/codes
+ *
+ * @code
+ *
+ * MBED_ERROR( MBED_ERROR_MUTEX_LOCK_FAILED, "MyDriver: Can't lock driver Mutex" )
+ * MBED_ERROR1( MBED_ERROR_MUTEX_LOCK_FAILED, "MyDriver: Can't lock driver Mutex", &my_mutex )
+ *
+ * @endcode
+ * @note The macro calls mbed_error API with filename and line number info without caller explicitly passing them.
+ *       Since this macro is a wrapper for mbed_error API callers should process the return value from this macro which is the return value from calling mbed_error API.
+ *
+ */
+#ifdef NDEBUG
+#define MBED_ERROR1( error_status, error_msg, error_value )           mbed_error( error_status, (const char *)NULL, (uint32_t)error_value, NULL, 0 )
+#define MBED_ERROR( error_status, error_msg )                         mbed_error( error_status, (const char *)NULL, (uint32_t)0          , NULL, 0 )
+#else //NDEBUG
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_ERROR1( error_status, error_msg, error_value )       mbed_error( error_status, (const char *)error_msg, (uint32_t)error_value, (const char *)MBED_FILENAME, __LINE__ )
+#define MBED_ERROR( error_status, error_msg )                     mbed_error( error_status, (const char *)error_msg, (uint32_t)0          , (const char *)MBED_FILENAME, __LINE__ )
+#else //MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_ERROR1( error_status, error_msg, error_value )       mbed_error( error_status, (const char *)error_msg, (uint32_t)error_value, NULL, 0 )
+#define MBED_ERROR( error_status, error_msg )                     mbed_error( error_status, (const char *)error_msg, (uint32_t)0          , NULL, 0 )
+#endif
+#endif
+
+//Error Type definition
+/** mbed_error_type_t definition
+ *  @note
+ *  This enumeration defines the Error types supported. The value of these enum values will be encoded into mbed_error_status_t TYPE field.\n
+ *      See mbed_error_status_t description for more info.\n
+ *         MBED_ERROR_TYPE_SYSTEM - Used to indicate that the error status is of System defined Error type.\n
+ *         MBED_ERROR_TYPE_CUSTOM - Used to indicate that the error status is of Custom defined Error type.\n
+ *         MBED_ERROR_TYPE_POSIX  - Used to indicate that the error status is of Posix error type.\n
+ *
+ */
+typedef enum _mbed_error_type_t {
+    MBED_ERROR_TYPE_SYSTEM = 0,
+    MBED_ERROR_TYPE_CUSTOM = 1,
+    //2 is reserved
+    //Use 3 for POSIX because we are mapping -1 to -255 to POSIX error codes
+    //and thus we must use 3 to match the type bits in error status representation which are from 0xFFFFFFFF to 0xFFFFFF00
+    MBED_ERROR_TYPE_POSIX = 3
+} mbed_error_type_t;
+
+//Module type/id definitions
+/** mbed_module_type_t definition
+ * @note
+ * This enumeration defines the module types. The value of these enum values will be encoded into mbed_error_status_t MODULE field.\n\n
+ *      See mbed_error_status_t description for more info.\n
+ *          MBED_MODULE_UNKNOWN - This module type can be used if caller of the mbed_error/mbed_warning doesn't know who is the actual originator of the error.\n
+ *                       Other module values can be used to provide more info on who/where the error originated from.\n\n
+ *                       For example, if I2C driver is the component originating the error you can use MBED_MODULE_DRIVER_I2C to provide more info.\n
+ *                       Its used in call to MBED_MAKE_ERROR/MBED_MAKE_SYSTEM_ERROR/MBED_MAKE_CUSTOM_ERROR macros.\n
+ *
+ * @code
+ *      Example: mbed_error_status_t i2c_driver_error = MBED_MAKE_ERROR( MBED_MODULE_DRIVER_I2C, MBED_ERROR_CONFIG_UNSUPPORTED );
+ * @endcode
+ *
+ * @note
+ *  \n Below are the module code mappings:\n
+    \verbatim
+    MBED_MODULE_APPLICATION              0       Application
+    MBED_MODULE_PLATFORM                 1       Platform
+    MODULE_KERNEL                   2       RTX Kernel
+    MBED_MODULE_NETWORK_STACK            3       Network stack
+    MBED_MODULE_HAL                      4       HAL - Hardware Abstraction Layer
+    MBED_MODULE_NETWORK_STACKMODULE_MEMORY_SUBSYSTEM         5       Memory Subsystem
+    MBED_MODULE_FILESYSTEM               6       Filesystem
+    MBED_MODULE_BLOCK_DEVICE             7       Block device
+    MBED_MODULE_DRIVER                   8       Driver
+    MBED_MODULE_DRIVER_SERIAL            9       Serial Driver
+    MBED_MODULE_DRIVER_RTC               10      RTC Driver
+    MBED_MODULE_DRIVER_I2C               11      I2C Driver
+    MODULE_DRIVER_SPI               12      SPI Driver
+    MODULE_DRIVER_GPIO              13      GPIO Driver
+    MODULE_DRIVER_ANALOG            14      Analog Driver
+    MODULE_DRIVER_DIGITAL           15      DigitalIO Driver
+    MODULE_DRIVER_CAN               16      CAN Driver
+    MODULE_DRIVER_ETHERNET          17      Ethernet Driver
+    MODULE_DRIVER_CRC               18      CRC Module
+    MODULE_DRIVER_PWM               19      PWM Driver
+    MODULE_DRIVER_QSPI              20      QSPI Driver
+    MODULE_DRIVER_USB               21      USB Driver
+    MODULE_TARGET_SDK               22      SDK
+
+    MBED_MODULE_UNKNOWN                  255     Unknown module
+    \endverbatim
+ *
+ */
+typedef enum _mbed_module_type {
+    MBED_MODULE_APPLICATION = 0,
+    MBED_MODULE_PLATFORM,
+    MBED_MODULE_KERNEL,
+    MBED_MODULE_NETWORK_STACK,
+    MBED_MODULE_HAL,
+    MBED_MODULE_NETWORK_STACKMODULE_MEMORY_SUBSYSTEM,
+    MBED_MODULE_FILESYSTEM,
+    MBED_MODULE_BLOCK_DEVICE,
+    MBED_MODULE_DRIVER,
+    MBED_MODULE_DRIVER_SERIAL,
+    MBED_MODULE_DRIVER_RTC,
+    MBED_MODULE_DRIVER_I2C,
+    MBED_MODULE_DRIVER_SPI,
+    MBED_MODULE_DRIVER_GPIO,
+    MBED_MODULE_DRIVER_ANALOG,
+    MBED_MODULE_DRIVER_DIGITAL,
+    MBED_MODULE_DRIVER_CAN,
+    MBED_MODULE_DRIVER_ETHERNET,
+    MBED_MODULE_DRIVER_CRC,
+    MBED_MODULE_DRIVER_PWM,
+    MBED_MODULE_DRIVER_QSPI,
+    MBED_MODULE_DRIVER_USB,
+    MBED_MODULE_TARGET_SDK,
+    MBED_MODULE_BLE,
+    /* Add More entities here as required */
+
+    MBED_MODULE_UNKNOWN = 255,
+    MBED_MODULE_MAX = MBED_MODULE_UNKNOWN
+} mbed_module_type_t;
+
+//Use MBED_SUCCESS(=0) or any postive number for successful returns
+#define MBED_SUCCESS           0
+
+#define MBED_POSIX_ERROR_BASE   0
+#define MBED_SYSTEM_ERROR_BASE  256
+#define MBED_CUSTOM_ERROR_BASE  4096
+
+//Error Code definitions
+/** mbed_error_code_t definition
+ *
+ *  mbed_error_code_t enumeration defines the Error codes and Error status values for MBED_MODULE_UNKNOWN.\n
+ *  It defines all of Posix Error Codes/Statuses and Mbed System Error Codes/Statuses.\n\n
+ *
+ *  @note
+ *  Posix Error codes are defined using the macro MBED_DEFINE_POSIX_ERROR\n
+ *  For example MBED_DEFINE_POSIX_ERROR( EPERM, EPERM ). This effectively defines the following values:\n
+ *      ERROR_CODE_EPERM = EPERM\n
+ *      ERROR_EPERM = -EPERM\n
+ *
+ *  Posix Error codes are defined using the macro MBED_DEFINE_POSIX_ERROR\n
+ *  For example MBED_DEFINE_POSIX_ERROR( EPERM, EPERM ). This macro defines the following values:\n
+ *      ERROR_CODE_EPERM = MBED_POSIX_ERROR_BASE+EPERM\n
+ *      ERROR_EPERM = -(MBED_POSIX_ERROR_BASE+EPERM)\n
+ *  Its effectively equivalent to:\n
+ *      ERROR_CODE_EPERM = 1\n
+ *      ERROR_EPERM = -1\n
+ *  All Posix error codes currently supported by MbedOS(defined in mbed_retarget.h) are defined using the MBED_DEFINE_POSIX_ERROR macro.\n\n
+ *  Below are the Posic error codes and the description:\n
+ *  \verbatim
+    EPERM                      1        Operation not permitted
+    ENOENT                     2        No such file or directory
+    ESRCH                      3        No such process
+    EINTR                      4        Interrupted system call
+    EIO                        5        I/O error
+    ENXIO                      6        No such device or address
+    E2BIG                      7        Argument list too long
+    ENOEXEC                    8        Exec format error
+    EBADF                      9        Bad file number
+    ECHILD                     10       No child processes
+    EAGAIN                     11       Try again
+    ENOMEM                     12       Out of memory
+    EACCES                     13       Permission denied
+    EFAULT                     14       Bad address
+    ENOTBLK                    15       Block device required
+    EBUSY                      16       Device or resource busy
+    EEXIST                     17       File exists
+    EXDEV                      18       Cross-device link
+    ENODEV                     19       No such device
+    ENOTDIR                    20       Not a directory
+    EISDIR                     21       Is a directory
+    EINVAL                     22       Invalid argument
+    ENFILE                     23       File table overflow
+    EMFILE                     24       Too many open files
+    ENOTTY                     25       Not a typewriter
+    ETXTBSY                    26       Text file busy
+    EFBIG                      27       File too large
+    ENOSPC                     28       No space left on device
+    ESPIPE                     29       Illegal seek
+    EROFS                      30       Read-only file system
+    EMLINK                     31       Too many links
+    EPIPE                      32       Broken pipe
+    EDOM                       33       Math argument out of domain of func
+    ERANGE                     34       Math result not representable
+    EDEADLK                    35       Resource deadlock would occur
+    ENAMETOOLONG               36       File name too long
+    ENOLCK                     37       No record locks available
+    ENOSYS                     38       Function not implemented
+    ENOTEMPTY                  39       Directory not empty
+    ELOOP                      40       Too many symbolic links encountered
+    EWOULDBLOCK                EAGAIN   Operation would block
+    ENOMSG                     42       No message of desired type
+    EIDRM                      43       Identifier removed
+    ECHRNG                     44       Channel number out of range
+    EL2NSYNC                   45       Level 2 not synchronized
+    EL3HLT                     46       Level 3 halted
+    EL3RST                     47       Level 3 reset
+    ELNRNG                     48       Link number out of range
+    EUNATCH                    49       Protocol driver not attached
+    ENOCSI                     50       No CSI structure available
+    EL2HLT                     51       Level 2 halted
+    EBADE                      52       Invalid exchange
+    EBADR                      53       Invalid request descriptor
+    EXFULL                     54       Exchange full
+    ENOANO                     55       No anode
+    EBADRQC                    56       Invalid request code
+    EBADSLT                    57       Invalid slot
+    EDEADLOCK                  EDEADLK  Resource deadlock would occur
+    EBFONT                     59       Bad font file format
+    ENOSTR                     60       Device not a stream
+    ENODATA                    61       No data available
+    ETIME                      62       Timer expired
+    ENOSR                      63       Out of streams resources
+    ENONET                     64       Machine is not on the network
+    ENOPKG                     65       Package not installed
+    EREMOTE                    66       Object is remote
+    ENOLINK                    67       Link has been severed
+    EADV                       68       Advertise error
+    ESRMNT                     69       Srmount error
+    ECOMM                      70       Communication error on send
+    EPROTO                     71       Protocol error
+    EMULTIHOP                  72       Multihop attempted
+    EDOTDOT                    73       RFS specific error
+    EBADMSG                    74       Not a data message
+    EOVERFLOW                  75       Value too large for defined data type
+    ENOTUNIQ                   76       Name not unique on network
+    EBADFD                     77       File descriptor in bad state
+    EREMCHG                    78       Remote address changed
+    ELIBACC                    79       Can not access a needed shared library
+    ELIBBAD                    80       Accessing a corrupted shared library
+    ELIBSCN                    81       .lib section in a.out corrupted
+    ELIBMAX                    82       Attempting to link in too many shared libraries
+    ELIBEXEC                   83       Cannot exec a shared library directly
+    EILSEQ                     84       Illegal byte sequence
+    ERESTART                   85       Interrupted system call should be restarted
+    ESTRPIPE                   86       Streams pipe error
+    EUSERS                     87       Too many users
+    ENOTSOCK                   88       Socket operation on non-socket
+    EDESTADDRREQ               89       Destination address required
+    EMSGSIZE                   90       Message too long
+    EPROTOTYPE                 91       Protocol wrong type for socket
+    ENOPROTOOPT                92       Protocol not available
+    EPROTONOSUPPORT            93       Protocol not supported
+    ESOCKTNOSUPPORT            94       Socket type not supported
+    EOPNOTSUPP                 95       Operation not supported on transport endpoint
+    EPFNOSUPPORT               96       Protocol family not supported
+    EAFNOSUPPORT               97       Address family not supported by protocol
+    EADDRINUSE                 98       Address already in use
+    EADDRNOTAVAIL              99       Cannot assign requested address
+    ENETDOWN                   100      Network is down
+    ENETUNREACH                101      Network is unreachable
+    ENETRESET                  102      Network dropped connection because of reset
+    ECONNABORTED               103      Software caused connection abort
+    ECONNRESET                 104      Connection reset by peer
+    ENOBUFS                    105      No buffer space available
+    EISCONN                    106      Transport endpoint is already connected
+    ENOTCONN                   107      Transport endpoint is not connected
+    ESHUTDOWN                  108      Cannot send after transport endpoint shutdown
+    ETOOMANYREFS               109      Too many references: cannot splice
+    ETIMEDOUT                  110      Connection timed out
+    ECONNREFUSED               111      Connection refused
+    EHOSTDOWN                  112      Host is down
+    EHOSTUNREACH               113      No route to host
+    EALREADY                   114      Operation already in progress
+    EINPROGRESS                115      Operation now in progress
+    ESTALE                     116      Stale NFS file handle
+    EUCLEAN                    117      Structure needs cleaning
+    ENOTNAM                    118      Not a XENIX named type file
+    ENAVAIL                    119      No XENIX semaphores available
+    EISNAM                     120      Is a named type file
+    EREMOTEIO                  121      Remote I/O error
+    EDQUOT                     122      Quota exceeded
+    ENOMEDIUM                  123      No medium found
+    EMEDIUMTYPE                124      Wrong medium type
+    ECANCELED                  125      Operation Canceled
+    ENOKEY                     126      Required key not available
+    EKEYEXPIRED                127      Key has expired
+    EKEYREVOKED                128      Key has been revoked
+    EKEYREJECTED               129      Key was rejected by service
+    EOWNERDEAD                 130      Owner died
+    ENOTRECOVERABLE            131      State not recoverable
+    \endverbatim
+ *
+ *  @note
+ *  MbedOS System Error codes are defined using the macro MBED_DEFINE_SYSTEM_ERROR\n
+ *  For example MBED_DEFINE_SYSTEM_ERROR( INVALID_ARGUMENT ,1 ) macro defines the following values:\n
+ *      ERROR_CODE_INVALID_ARGUMENT = MBED_SYSTEM_ERROR_BASE+1\n
+ *      ERROR_INVALID_ARGUMENT = MAKE_MBED_ERROR(ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, ERROR_CODE_INVALID_ARGUMENT)\n
+ *  Its effectively equivalent to:\n
+ *      ERROR_CODE_INVALID_ARGUMENT = 1\n
+ *      ERROR_INVALID_ARGUMENT = 0x80FF0001\n (Note that MODULE field is set to MBED_MODULE_UNKNOWN)
+ *  New System Error codes should be defined using MBED_DEFINE_SYSTEM_ERROR macro and must have an unique error code value\n
+ *  passed as the second argument in the MBED_DEFINE_SYSTEM_ERROR macro.\n\n
+ *  Below are the Mbed System error codes and the description:
+ *  \verbatim
+    UNKNOWN                    256      Unknown error
+    INVALID_ARGUMENT           257      Invalid Argument
+    INVALID_DATA               258      Invalid data
+    INVALID_FORMAT             259      Invalid format
+    INVALID_INDEX              260      Invalid Index
+    INVALID_SIZE               261      Inavlid Size
+    INVALID_OPERATION          262      Invalid Operation
+    NOT_FOUND                  263      Not Found
+    ACCESS_DENIED              264      Access Denied
+    NOT_SUPPORTED              265      Not supported
+    BUFFER_FULL                266      Buffer Full
+    MEDIA_FULL                 267      Media/Disk Full
+    ALREADY_IN_USE             268      Already in use
+    TIMEOUT                    269      Timeout error
+    NOT_READY                  270      Not Ready
+    FAILED_OPERATION           271      Requested Operation failed
+    OPERATION_PROHIBITED       272      Operation prohibited
+    OPERATION_ABORTED          273      Operation failed
+    WRITE_PROTECTED            274      Attempt to write to write-protected resource
+    NO_RESPONSE                275      No response
+    SEMAPHORE_LOCK_FAILED      276      Sempahore lock failed
+    MUTEX_LOCK_FAILED          277      Mutex lock failed
+    SEMAPHORE_UNLOCK_FAILED    278      Sempahore unlock failed
+    MUTEX_UNLOCK_FAILED        279      Mutex unlock failed
+    CRC_ERROR                  280      CRC error or mismatch
+    OPEN_FAILED                281      Open failed
+    CLOSE_FAILED               282      Close failed
+    READ_FAILED                283      Read failed
+    WRITE_FAILED               284      Write failed
+    INITIALIZATION_FAILED      285      Initialization failed
+    BOOT_FAILURE               286      Boot failure
+    OUT_OF_MEMORY              287      Out of memory
+    OUT_OF_RESOURCES           288      Out of resources
+    ALLOC_FAILED               289      Alloc failed
+    FREE_FAILED                290      Free failed
+    OVERFLOW                   291      Overflow error
+    UNDERFLOW                  292      Underflow error
+    STACK_OVERFLOW             293      Stack overflow error
+    ISR_QUEUE_OVERFLOW         294      ISR queue overflow
+    TIMER_QUEUE_OVERFLOW       295      Timer Queue overflow
+    CLIB_SPACE_UNAVAILABLE     296      Standard library error - Space unavailable
+    CLIB_EXCEPTION             297      Standard library error - Exception
+    CLIB_MUTEX_INIT_FAILURE    298      Standard library error - Mutex Init failure
+    CREATE_FAILED              299      Create failed
+    DELETE_FAILED              300      Delete failed
+    THREAD_CREATE_FAILED       301      Thread Create failed
+    THREAD_DELETE_FAILED       302      Thread Delete failed
+    PROHIBITED_IN_ISR_CONTEXT  303      Operation Prohibited in ISR context
+    PINMAP_INVALID             304      Pinmap Invalid
+    RTOS_EVENT                 305      Unknown Rtos Error
+    RTOS_THREAD_EVENT          306      Rtos Thread Error
+    RTOS_MUTEX_EVENT           307      Rtos Mutex Error
+    RTOS_SEMAPHORE_EVENT       308      Rtos Semaphore Error
+    RTOS_MEMORY_POOL_EVENT     309      Rtos Memory Pool Error
+    RTOS_TIMER_EVENT           310      Rtos Timer Error
+    RTOS_EVENT_FLAGS_EVENT     311      Rtos Event flags Error
+    RTOS_MESSAGE_QUEUE_EVENT   312      Rtos Message queue Error
+    DEVICE_BUSY                313      Device Busy
+    CONFIG_UNSUPPORTED         314      Configuration not supported
+    CONFIG_MISMATCH            315      Configuration mismatch
+    ALREADY_INITIALIZED        316      Already initialzied
+    HARDFAULT_EXCEPTION        317      HardFault exception
+    MEMMANAGE_EXCEPTION        318      MemManage exception
+    BUSFAULT_EXCEPTION         319      BusFault exception
+    USAGEFAULT_EXCEPTION       320      UsageFault exception
+    \endverbatim
+ *
+ *  @note
+ *  Custom Error codes can be defined using the macro DEFINE_CUSTOM_ERROR\n
+ *  This is mainly meant to capture non-generic error codes specific to a device.
+ *  For example DEFINE_CUSTOM_ERROR( MY_CUSTOM_ERROR ,1 ) macro defines the following values:\n
+ *      ERROR_CODE_MY_CUSTOM_ERROR = MBED_CUSTOM_ERROR_BASE+1\n
+ *      ERROR_MY_CUSTOM_ERROR = MAKE_MBED_ERROR(ERROR_TYPE_CUSTOM, MBED_MODULE_UNKNOWN, ERROR_CODE_MY_CUSTOM_ERROR)\n
+ *  Its effectively equivalent to:\n
+ *      ERROR_CODE_MY_CUSTOM_ERROR = 4097\n
+ *      ERROR_MY_CUSTOM_ERROR = 0xA0FF1001\n (Note that MODULE field is set to MBED_MODULE_UNKNOWN) \n\n
+ *
+ *  @note
+ *  **Using error codes:** \n
+ *  Posix error codes may be used in modules/functions currently using Posix error codes and switching them to Mbed-OS error codes
+ *  may cause interoperability issues. For example, some of the filesystem, network stack implementations may need to use
+ *  Posix error codes in order to keep them compatible with other modules interfacing with them, and may continue to use Posix error codes.
+ *
+ *  In all other cases, like for any native development of Mbed-OS modules Mbed-OS error codes should be used.
+ *  This makes it easy to use Mbed-OS error reporting/logging infrastructure and makes debugging error scenarios
+ *  much more efficient.
+ *
+ *  @note
+ *  **Searching for error codes in mbed-os source tree:** \n
+ *  If you get an error report as below which you want to search for in mbed-os source tree, first take note of "Error Code" number. \n
+ *  For example, the below error report has an error code of \b 259. Find the error name associated with the error code and in this case its \b INVALID_FORMAT. \n
+ *  Use that error name(\b INVALID_FORMAT) to search the source tree for code locations setting that specific error code. \n
+ *  If the Error module reported is not 255(which indicates unknown module), you can also use that to narrow down to the specific component reporting the error.
+ *  See mbed_module_type_t enum above for module mapping. \n
+ *
+ *  \verbatim
+    ++ MbedOS Error Info ++
+    Error Status: 0x80040103
+    Error Code: 259
+    Error Module: 04
+    Error Message: HAL Module error
+    Error Location: 0x000067C7
+    Error Value: 0x00005566
+    Current Thread: Id: 0x200024A8 EntryFn: 0x0000FB0D StackSize: 0x00001000 StackMem: 0x200014A8 SP: 0x2002FFD8
+    -- MbedOS Error Info --
+    \endverbatim
+ */
+
+typedef enum _mbed_error_code {
+    //Below are POSIX ERROR CODE definitions, which starts at MBED_POSIX_ERROR_BASE(=0)
+    //POSIX ERROR CODE definitions starts at offset 0(MBED_POSIX_ERROR_BASE) to align them with actual Posix Error Code
+    //defintions in mbed_retarget.h
+    //                  Error Name                                    Error Code
+    MBED_DEFINE_POSIX_ERROR(EPERM, EPERM),                              /* 1       Operation not permitted */
+    MBED_DEFINE_POSIX_ERROR(ENOENT, ENOENT),                            /* 2       No such file or directory */
+    MBED_DEFINE_POSIX_ERROR(ESRCH, ESRCH),                              /* 3       No such process */
+    MBED_DEFINE_POSIX_ERROR(EINTR, EINTR),                              /* 4       Interrupted system call */
+    MBED_DEFINE_POSIX_ERROR(EIO, EIO),                                  /* 5       I/O error */
+    MBED_DEFINE_POSIX_ERROR(ENXIO, ENXIO),                              /* 6       No such device or address */
+    MBED_DEFINE_POSIX_ERROR(E2BIG, E2BIG),                              /* 7       Argument list too long */
+    MBED_DEFINE_POSIX_ERROR(ENOEXEC, ENOEXEC),                          /* 8       Exec format error */
+    MBED_DEFINE_POSIX_ERROR(EBADF, EBADF),                              /* 9       Bad file number */
+    MBED_DEFINE_POSIX_ERROR(ECHILD, ECHILD),                            /* 10      No child processes */
+    MBED_DEFINE_POSIX_ERROR(EAGAIN, EAGAIN),                            /* 11      Try again */
+    MBED_DEFINE_POSIX_ERROR(ENOMEM, ENOMEM),                            /* 12      Out of memory */
+    MBED_DEFINE_POSIX_ERROR(EACCES, EACCES),                            /* 13      Permission denied */
+    MBED_DEFINE_POSIX_ERROR(EFAULT, EFAULT),                            /* 14      Bad address */
+    MBED_DEFINE_POSIX_ERROR(ENOTBLK, ENOTBLK),                          /* 15      Block device required */
+    MBED_DEFINE_POSIX_ERROR(EBUSY, EBUSY),                              /* 16      Device or resource busy */
+    MBED_DEFINE_POSIX_ERROR(EEXIST, EEXIST),                            /* 17      File exists */
+    MBED_DEFINE_POSIX_ERROR(EXDEV, EXDEV),                              /* 18      Cross-device link */
+    MBED_DEFINE_POSIX_ERROR(ENODEV, ENODEV),                            /* 19      No such device */
+    MBED_DEFINE_POSIX_ERROR(ENOTDIR, ENOTDIR),                          /* 20      Not a directory */
+    MBED_DEFINE_POSIX_ERROR(EISDIR, EISDIR),                            /* 21      Is a directory */
+    MBED_DEFINE_POSIX_ERROR(EINVAL, EINVAL),                            /* 22      Invalid argument */
+    MBED_DEFINE_POSIX_ERROR(ENFILE, ENFILE),                            /* 23      File table overflow */
+    MBED_DEFINE_POSIX_ERROR(EMFILE, EMFILE),                            /* 24      Too many open files */
+    MBED_DEFINE_POSIX_ERROR(ENOTTY, ENOTTY),                            /* 25      Not a typewriter */
+    MBED_DEFINE_POSIX_ERROR(ETXTBSY, ETXTBSY),                          /* 26      Text file busy */
+    MBED_DEFINE_POSIX_ERROR(EFBIG, EFBIG),                              /* 27      File too large */
+    MBED_DEFINE_POSIX_ERROR(ENOSPC, ENOSPC),                            /* 28      No space left on device */
+    MBED_DEFINE_POSIX_ERROR(ESPIPE, ESPIPE),                            /* 29      Illegal seek */
+    MBED_DEFINE_POSIX_ERROR(EROFS, EROFS),                              /* 30      Read-only file system */
+    MBED_DEFINE_POSIX_ERROR(EMLINK, EMLINK),                            /* 31      Too many links */
+    MBED_DEFINE_POSIX_ERROR(EPIPE, EPIPE),                              /* 32      Broken pipe */
+    MBED_DEFINE_POSIX_ERROR(EDOM, EDOM),                                /* 33      Math argument out of domain of func */
+    MBED_DEFINE_POSIX_ERROR(ERANGE, ERANGE),                            /* 34      Math result not representable */
+    MBED_DEFINE_POSIX_ERROR(EDEADLK, EDEADLK),                          /* 35      Resource deadlock would occur */
+    MBED_DEFINE_POSIX_ERROR(ENAMETOOLONG, ENAMETOOLONG),                /* 36      File name too long */
+    MBED_DEFINE_POSIX_ERROR(ENOLCK, ENOLCK),                            /* 37      No record locks available */
+    MBED_DEFINE_POSIX_ERROR(ENOSYS, ENOSYS),                            /* 38      Function not implemented */
+    MBED_DEFINE_POSIX_ERROR(ENOTEMPTY, ENOTEMPTY),                      /* 39      Directory not empty */
+    MBED_DEFINE_POSIX_ERROR(ELOOP, ELOOP),                              /* 40      Too many symbolic links encountered */
+    MBED_DEFINE_POSIX_ERROR(EWOULDBLOCK, EAGAIN),                       /* EAGAIN  Operation would block */
+    MBED_DEFINE_POSIX_ERROR(ENOMSG, ENOMSG),                            /* 42      No message of desired type */
+    MBED_DEFINE_POSIX_ERROR(EIDRM, EIDRM),                              /* 43      Identifier removed */
+    MBED_DEFINE_POSIX_ERROR(ECHRNG, ECHRNG),                            /* 44      Channel number out of range */
+    MBED_DEFINE_POSIX_ERROR(EL2NSYNC, EL2NSYNC),                        /* 45      Level 2 not synchronized */
+    MBED_DEFINE_POSIX_ERROR(EL3HLT, EL3HLT),                            /* 46      Level 3 halted */
+    MBED_DEFINE_POSIX_ERROR(EL3RST, EL3RST),                            /* 47      Level 3 reset */
+    MBED_DEFINE_POSIX_ERROR(ELNRNG, ELNRNG),                            /* 48      Link number out of range */
+    MBED_DEFINE_POSIX_ERROR(EUNATCH, EUNATCH),                          /* 49      Protocol driver not attached */
+    MBED_DEFINE_POSIX_ERROR(ENOCSI, ENOCSI),                            /* 50      No CSI structure available */
+    MBED_DEFINE_POSIX_ERROR(EL2HLT, EL2HLT),                            /* 51      Level 2 halted */
+    MBED_DEFINE_POSIX_ERROR(EBADE, EBADE),                              /* 52      Invalid exchange */
+    MBED_DEFINE_POSIX_ERROR(EBADR, EBADR),                              /* 53      Invalid request descriptor */
+    MBED_DEFINE_POSIX_ERROR(EXFULL, EXFULL),                            /* 54      Exchange full */
+    MBED_DEFINE_POSIX_ERROR(ENOANO, ENOANO),                            /* 55      No anode */
+    MBED_DEFINE_POSIX_ERROR(EBADRQC, EBADRQC),                          /* 56      Invalid request code */
+    MBED_DEFINE_POSIX_ERROR(EBADSLT, EBADSLT),                          /* 57      Invalid slot */
+    MBED_DEFINE_POSIX_ERROR(EDEADLOCK, EDEADLK),                        /* EDEADLK Resource deadlock would occur */
+    MBED_DEFINE_POSIX_ERROR(EBFONT, EBFONT),                            /* 59      Bad font file format */
+    MBED_DEFINE_POSIX_ERROR(ENOSTR, ENOSTR),                            /* 60      Device not a stream */
+    MBED_DEFINE_POSIX_ERROR(ENODATA, ENODATA),                          /* 61      No data available */
+    MBED_DEFINE_POSIX_ERROR(ETIME, ETIME),                              /* 62      Timer expired */
+    MBED_DEFINE_POSIX_ERROR(ENOSR, ENOSR),                              /* 63      Out of streams resources */
+    MBED_DEFINE_POSIX_ERROR(ENONET, ENONET),                            /* 64      Machine is not on the network */
+    MBED_DEFINE_POSIX_ERROR(ENOPKG, ENOPKG),                            /* 65      Package not installed */
+    MBED_DEFINE_POSIX_ERROR(EREMOTE, EREMOTE),                          /* 66      Object is remote */
+    MBED_DEFINE_POSIX_ERROR(ENOLINK, ENOLINK),                          /* 67      Link has been severed */
+    MBED_DEFINE_POSIX_ERROR(EADV, EADV),                                /* 68      Advertise error */
+    MBED_DEFINE_POSIX_ERROR(ESRMNT, ESRMNT),                            /* 69      Srmount error */
+    MBED_DEFINE_POSIX_ERROR(ECOMM, ECOMM),                              /* 70      Communication error on send */
+    MBED_DEFINE_POSIX_ERROR(EPROTO, EPROTO),                            /* 71      Protocol error */
+    MBED_DEFINE_POSIX_ERROR(EMULTIHOP, EMULTIHOP),                      /* 72      Multihop attempted */
+    MBED_DEFINE_POSIX_ERROR(EDOTDOT, EDOTDOT),                          /* 73      RFS specific error */
+    MBED_DEFINE_POSIX_ERROR(EBADMSG, EBADMSG),                          /* 74      Not a data message */
+    MBED_DEFINE_POSIX_ERROR(EOVERFLOW, EOVERFLOW),                      /* 75      Value too large for defined data type */
+    MBED_DEFINE_POSIX_ERROR(ENOTUNIQ, ENOTUNIQ),                        /* 76      Name not unique on network */
+    MBED_DEFINE_POSIX_ERROR(EBADFD, EBADFD),                            /* 77      File descriptor in bad state */
+    MBED_DEFINE_POSIX_ERROR(EREMCHG, EREMCHG),                          /* 78      Remote address changed */
+    MBED_DEFINE_POSIX_ERROR(ELIBACC, ELIBACC),                          /* 79      Can not access a needed shared library */
+    MBED_DEFINE_POSIX_ERROR(ELIBBAD, ELIBBAD),                          /* 80      Accessing a corrupted shared library */
+    MBED_DEFINE_POSIX_ERROR(ELIBSCN, ELIBSCN),                          /* 81      .lib section in a.out corrupted */
+    MBED_DEFINE_POSIX_ERROR(ELIBMAX, ELIBMAX),                          /* 82      Attempting to link in too many shared libraries */
+    MBED_DEFINE_POSIX_ERROR(ELIBEXEC, ELIBEXEC),                        /* 83      Cannot exec a shared library directly */
+    MBED_DEFINE_POSIX_ERROR(EILSEQ, EILSEQ),                            /* 84      Illegal byte sequence */
+    MBED_DEFINE_POSIX_ERROR(ERESTART, ERESTART),                        /* 85      Interrupted system call should be restarted */
+    MBED_DEFINE_POSIX_ERROR(ESTRPIPE, ESTRPIPE),                        /* 86      Streams pipe error */
+    MBED_DEFINE_POSIX_ERROR(EUSERS, EUSERS),                            /* 87      Too many users */
+    MBED_DEFINE_POSIX_ERROR(ENOTSOCK, ENOTSOCK),                        /* 88      Socket operation on non-socket */
+    MBED_DEFINE_POSIX_ERROR(EDESTADDRREQ, EDESTADDRREQ),                /* 89      Destination address required */
+    MBED_DEFINE_POSIX_ERROR(EMSGSIZE, EMSGSIZE),                        /* 90      Message too long */
+    MBED_DEFINE_POSIX_ERROR(EPROTOTYPE, EPROTOTYPE),                    /* 91      Protocol wrong type for socket */
+    MBED_DEFINE_POSIX_ERROR(ENOPROTOOPT, ENOPROTOOPT),                  /* 92      Protocol not available */
+    MBED_DEFINE_POSIX_ERROR(EPROTONOSUPPORT, EPROTONOSUPPORT),          /* 93      Protocol not supported */
+    MBED_DEFINE_POSIX_ERROR(ESOCKTNOSUPPORT, ESOCKTNOSUPPORT),          /* 94      Socket type not supported */
+    MBED_DEFINE_POSIX_ERROR(EOPNOTSUPP, EOPNOTSUPP),                    /* 95      Operation not supported on transport endpoint */
+    MBED_DEFINE_POSIX_ERROR(EPFNOSUPPORT, EPFNOSUPPORT),                /* 96      Protocol family not supported */
+    MBED_DEFINE_POSIX_ERROR(EAFNOSUPPORT, EAFNOSUPPORT),                /* 97      Address family not supported by protocol */
+    MBED_DEFINE_POSIX_ERROR(EADDRINUSE, EADDRINUSE),                    /* 98      Address already in use */
+    MBED_DEFINE_POSIX_ERROR(EADDRNOTAVAIL, EADDRNOTAVAIL),              /* 99      Cannot assign requested address */
+    MBED_DEFINE_POSIX_ERROR(ENETDOWN, ENETDOWN),                        /* 100     Network is down */
+    MBED_DEFINE_POSIX_ERROR(ENETUNREACH, ENETUNREACH),                  /* 101     Network is unreachable */
+    MBED_DEFINE_POSIX_ERROR(ENETRESET, ENETRESET),                      /* 102     Network dropped connection because of reset */
+    MBED_DEFINE_POSIX_ERROR(ECONNABORTED, ECONNABORTED),                /* 103     Software caused connection abort */
+    MBED_DEFINE_POSIX_ERROR(ECONNRESET, ECONNRESET),                    /* 104     Connection reset by peer */
+    MBED_DEFINE_POSIX_ERROR(ENOBUFS, ENOBUFS),                          /* 105     No buffer space available */
+    MBED_DEFINE_POSIX_ERROR(EISCONN, EISCONN),                          /* 106     Transport endpoint is already connected */
+    MBED_DEFINE_POSIX_ERROR(ENOTCONN, ENOTCONN),                        /* 107     Transport endpoint is not connected */
+    MBED_DEFINE_POSIX_ERROR(ESHUTDOWN, ESHUTDOWN),                      /* 108     Cannot send after transport endpoint shutdown */
+    MBED_DEFINE_POSIX_ERROR(ETOOMANYREFS, ETOOMANYREFS),                /* 109     Too many references: cannot splice */
+    MBED_DEFINE_POSIX_ERROR(ETIMEDOUT, ETIMEDOUT),                      /* 110     Connection timed out */
+    MBED_DEFINE_POSIX_ERROR(ECONNREFUSED, ECONNREFUSED),                /* 111     Connection refused */
+    MBED_DEFINE_POSIX_ERROR(EHOSTDOWN, EHOSTDOWN),                      /* 112     Host is down */
+    MBED_DEFINE_POSIX_ERROR(EHOSTUNREACH, EHOSTUNREACH),                /* 113     No route to host */
+    MBED_DEFINE_POSIX_ERROR(EALREADY, EALREADY),                        /* 114     Operation already in progress */
+    MBED_DEFINE_POSIX_ERROR(EINPROGRESS, EINPROGRESS),                  /* 115     Operation now in progress */
+    MBED_DEFINE_POSIX_ERROR(ESTALE, ESTALE),                            /* 116     Stale NFS file handle */
+    MBED_DEFINE_POSIX_ERROR(EUCLEAN, EUCLEAN),                          /* 117     Structure needs cleaning */
+    MBED_DEFINE_POSIX_ERROR(ENOTNAM, ENOTNAM),                          /* 118     Not a XENIX named type file */
+    MBED_DEFINE_POSIX_ERROR(ENAVAIL, ENAVAIL),                          /* 119     No XENIX semaphores available */
+    MBED_DEFINE_POSIX_ERROR(EISNAM, EISNAM),                            /* 120     Is a named type file */
+    MBED_DEFINE_POSIX_ERROR(EREMOTEIO, EREMOTEIO),                      /* 121     Remote I/O error */
+    MBED_DEFINE_POSIX_ERROR(EDQUOT, EDQUOT),                            /* 122     Quota exceeded */
+    MBED_DEFINE_POSIX_ERROR(ENOMEDIUM, ENOMEDIUM),                      /* 123     No medium found */
+    MBED_DEFINE_POSIX_ERROR(EMEDIUMTYPE, EMEDIUMTYPE),                  /* 124     Wrong medium type */
+    MBED_DEFINE_POSIX_ERROR(ECANCELED, ECANCELED),                      /* 125     Operation Canceled */
+    MBED_DEFINE_POSIX_ERROR(ENOKEY, ENOKEY),                            /* 126     Required key not available */
+    MBED_DEFINE_POSIX_ERROR(EKEYEXPIRED, EKEYEXPIRED),                  /* 127     Key has expired */
+    MBED_DEFINE_POSIX_ERROR(EKEYREVOKED, EKEYREVOKED),                  /* 128     Key has been revoked */
+    MBED_DEFINE_POSIX_ERROR(EKEYREJECTED, EKEYREJECTED),                /* 129     Key was rejected by service */
+    MBED_DEFINE_POSIX_ERROR(EOWNERDEAD, EOWNERDEAD),                    /* 130     Owner died */
+    MBED_DEFINE_POSIX_ERROR(ENOTRECOVERABLE, ENOTRECOVERABLE),          /* 131     State not recoverable */
+
+    //Below are MBED SYSTEM ERROR CODE definitions
+    //MBED SYSTEM ERROR CODE definitions starts at offset MBED_SYSTEM_ERROR_BASE, see above.
+    //                   Error Name                 Error Offset   Error Code
+    MBED_DEFINE_SYSTEM_ERROR(UNKNOWN, 0),                               /* 256      Unknown error */
+    MBED_DEFINE_SYSTEM_ERROR(INVALID_ARGUMENT, 1),                      /* 257      Invalid Argument */
+    MBED_DEFINE_SYSTEM_ERROR(INVALID_DATA_DETECTED, 2),                 /* 258      Invalid data detected */
+    MBED_DEFINE_SYSTEM_ERROR(INVALID_FORMAT, 3),                        /* 259      Invalid format */
+    MBED_DEFINE_SYSTEM_ERROR(INVALID_INDEX, 4),                         /* 260      Invalid Index */
+    MBED_DEFINE_SYSTEM_ERROR(INVALID_SIZE, 5),                          /* 261      Inavlid Size */
+    MBED_DEFINE_SYSTEM_ERROR(INVALID_OPERATION, 6),                     /* 262      Invalid Operation */
+    MBED_DEFINE_SYSTEM_ERROR(ITEM_NOT_FOUND, 7),                        /* 263      Item Not Found */
+    MBED_DEFINE_SYSTEM_ERROR(ACCESS_DENIED, 8),                         /* 264      Access Denied */
+    MBED_DEFINE_SYSTEM_ERROR(UNSUPPORTED, 9),                           /* 265      Unsupported */
+    MBED_DEFINE_SYSTEM_ERROR(BUFFER_FULL, 10),                          /* 266      Buffer Full */
+    MBED_DEFINE_SYSTEM_ERROR(MEDIA_FULL, 11),                           /* 267      Media/Disk Full */
+    MBED_DEFINE_SYSTEM_ERROR(ALREADY_IN_USE, 12),                       /* 268      Already in use */
+    MBED_DEFINE_SYSTEM_ERROR(TIME_OUT, 13),                             /* 269      Timeout error */
+    MBED_DEFINE_SYSTEM_ERROR(NOT_READY, 14),                            /* 270      Not Ready */
+    MBED_DEFINE_SYSTEM_ERROR(FAILED_OPERATION, 15),                     /* 271      Requested Operation failed */
+    MBED_DEFINE_SYSTEM_ERROR(OPERATION_PROHIBITED, 16),                 /* 272      Operation prohibited */
+    MBED_DEFINE_SYSTEM_ERROR(OPERATION_ABORTED, 17),                    /* 273      Operation failed */
+    MBED_DEFINE_SYSTEM_ERROR(WRITE_PROTECTED, 18),                      /* 274      Attempt to write to write-protected resource */
+    MBED_DEFINE_SYSTEM_ERROR(NO_RESPONSE, 19),                          /* 275      No response */
+    MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_LOCK_FAILED, 20),                /* 276      Sempahore lock failed */
+    MBED_DEFINE_SYSTEM_ERROR(MUTEX_LOCK_FAILED, 21),                    /* 277      Mutex lock failed */
+    MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_UNLOCK_FAILED, 22),              /* 278      Sempahore unlock failed */
+    MBED_DEFINE_SYSTEM_ERROR(MUTEX_UNLOCK_FAILED, 23),                  /* 279      Mutex unlock failed */
+    MBED_DEFINE_SYSTEM_ERROR(CRC_ERROR, 24),                            /* 280      CRC error or mismatch */
+    MBED_DEFINE_SYSTEM_ERROR(OPEN_FAILED, 25),                          /* 281      Open failed */
+    MBED_DEFINE_SYSTEM_ERROR(CLOSE_FAILED, 26),                         /* 282      Close failed */
+    MBED_DEFINE_SYSTEM_ERROR(READ_FAILED, 27),                          /* 283      Read failed */
+    MBED_DEFINE_SYSTEM_ERROR(WRITE_FAILED, 28),                         /* 284      Write failed */
+    MBED_DEFINE_SYSTEM_ERROR(INITIALIZATION_FAILED, 29),                /* 285      Initialization failed */
+    MBED_DEFINE_SYSTEM_ERROR(BOOT_FAILURE, 30),                         /* 286      Boot failure */
+    MBED_DEFINE_SYSTEM_ERROR(OUT_OF_MEMORY, 31),                        /* 287      Out of memory */
+    MBED_DEFINE_SYSTEM_ERROR(OUT_OF_RESOURCES, 32),                     /* 288      Out of resources */
+    MBED_DEFINE_SYSTEM_ERROR(ALLOC_FAILED, 33),                         /* 289      Alloc failed */
+    MBED_DEFINE_SYSTEM_ERROR(FREE_FAILED, 34),                          /* 290      Free failed */
+    MBED_DEFINE_SYSTEM_ERROR(OVERFLOW, 35),                             /* 291      Overflow error */
+    MBED_DEFINE_SYSTEM_ERROR(UNDERFLOW, 36),                            /* 292      Underflow error */
+    MBED_DEFINE_SYSTEM_ERROR(STACK_OVERFLOW, 37),                       /* 293      Stack overflow error */
+    MBED_DEFINE_SYSTEM_ERROR(ISR_QUEUE_OVERFLOW, 38),                   /* 294      ISR queue overflow */
+    MBED_DEFINE_SYSTEM_ERROR(TIMER_QUEUE_OVERFLOW, 39),                 /* 295      Timer Queue overflow */
+    MBED_DEFINE_SYSTEM_ERROR(CLIB_SPACE_UNAVAILABLE, 40),               /* 296      Standard library error - Space unavailable */
+    MBED_DEFINE_SYSTEM_ERROR(CLIB_EXCEPTION, 41),                       /* 297      Standard library error - Exception */
+    MBED_DEFINE_SYSTEM_ERROR(CLIB_MUTEX_INIT_FAILURE, 42),              /* 298      Standard library error - Mutex Init failure */
+    MBED_DEFINE_SYSTEM_ERROR(CREATE_FAILED, 43),                        /* 299      Create failed */
+    MBED_DEFINE_SYSTEM_ERROR(DELETE_FAILED, 44),                        /* 300      Delete failed */
+    MBED_DEFINE_SYSTEM_ERROR(THREAD_CREATE_FAILED, 45),                 /* 301      Thread Create failed */
+    MBED_DEFINE_SYSTEM_ERROR(THREAD_DELETE_FAILED, 46),                 /* 302      Thread Delete failed */
+    MBED_DEFINE_SYSTEM_ERROR(PROHIBITED_IN_ISR_CONTEXT, 47),            /* 303      Operation Prohibited in ISR context */
+    MBED_DEFINE_SYSTEM_ERROR(PINMAP_INVALID, 48),                       /* 304      Pinmap Invalid */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_EVENT, 49),                           /* 305      Unknown Rtos Error */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_THREAD_EVENT, 50),                    /* 306      Rtos Thread Error */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_MUTEX_EVENT, 51),                     /* 307      Rtos Mutex Error */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_SEMAPHORE_EVENT, 52),                 /* 308      Rtos Semaphore Error */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_MEMORY_POOL_EVENT, 53),               /* 309      Rtos Memory Pool Error */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_TIMER_EVENT, 54),                     /* 310      Rtos Timer Error */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_EVENT_FLAGS_EVENT, 55),               /* 311      Rtos Event flags Error */
+    MBED_DEFINE_SYSTEM_ERROR(RTOS_MESSAGE_QUEUE_EVENT, 56),             /* 312      Rtos Message queue Error */
+    MBED_DEFINE_SYSTEM_ERROR(DEVICE_BUSY, 57),                          /* 313      Device Busy */
+    MBED_DEFINE_SYSTEM_ERROR(CONFIG_UNSUPPORTED, 58),                   /* 314      Configuration not supported */
+    MBED_DEFINE_SYSTEM_ERROR(CONFIG_MISMATCH, 59),                      /* 315      Configuration mismatch */
+    MBED_DEFINE_SYSTEM_ERROR(ALREADY_INITIALIZED, 60),                  /* 316      Already initialzied */
+    MBED_DEFINE_SYSTEM_ERROR(HARDFAULT_EXCEPTION, 61),                  /* 317      HardFault exception */
+    MBED_DEFINE_SYSTEM_ERROR(MEMMANAGE_EXCEPTION, 62),                  /* 318      MemManage exception */
+    MBED_DEFINE_SYSTEM_ERROR(BUSFAULT_EXCEPTION, 63),                   /* 319      BusFault exception */
+    MBED_DEFINE_SYSTEM_ERROR(USAGEFAULT_EXCEPTION, 64),                 /* 320      UsageFault exception*/
+    MBED_DEFINE_SYSTEM_ERROR(BLE_NO_FRAME_INITIALIZED, 65),             /* 321      BLE No frame initialized */
+    MBED_DEFINE_SYSTEM_ERROR(BLE_BACKEND_CREATION_FAILED, 66),          /* 322      BLE Backend creation failed */
+    MBED_DEFINE_SYSTEM_ERROR(BLE_BACKEND_NOT_INITIALIZED, 67),          /* 323      BLE Backend not initialized */
+
+    //Everytime you add a new system error code, you must update
+    //Error documentation under Handbook to capture the info on
+    //the new error status/codes
+
+    //MBED CUSTOM ERROR CODE definitions starts at offset MBED_CUSTOM_ERROR_BASE, see above.
+    /* Add More/Custom Error Codes here, See example below */
+    //DEFINE_CUSTOM_ERROR( MY_CUSTOM_ERROR     , 1 ),
+
+} mbed_error_code_t;
+
+/** mbed_error_ctx struct
+ *
+ *  This struct captures the context information at the time of error.\n
+ *  It primarily contains information about the thread where the error originated,\n
+ *  filename/line number of the source file where the error occurred, a context specific error value(error_value)\n
+ *  and the address where the error originated.\n
+ *
+ *  @note
+ *  Below are the members of mbed_error_ctx struct\n
+ *      error_status              mbed_error_status_t value for this error\n
+ *      error_function_address    Address where the error occurred\n
+ *      thread_id                 ID of the thread which generated the error\n
+ *      thread_entry_address      Entry function of the thread which generated the error\n
+ *      thread_stack_size         Stack Size of the thread which generated the error\n
+ *      thread_stack_mem          Stack Top of the thread which generated the error\n
+ *      thread_current_sp         Current Stack Pointer of the thread which generated the error\n
+ *      error_value               A context/error specific value associated with this error\n
+ *      error_filename            Filename where the error originated\n
+ *      error_line_number         Line number in error_filename where the error originated\n
+ */
+typedef struct _mbed_error_ctx {
+    mbed_error_status_t error_status;
+    uint32_t error_address;
+    uint32_t error_value;
+    uint32_t thread_id;
+    uint32_t thread_entry_address;
+    uint32_t thread_stack_size;
+    uint32_t thread_stack_mem;
+    uint32_t thread_current_sp;
+#ifdef MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
+    char error_filename[MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN];
+    uint32_t error_line_number;
+#endif
+} mbed_error_ctx;
+
 /** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @param format    C string that contains data stream to be printed.
+ *                  Code snippets below show valid format.
  *
  * @code
@@ -54,12 +864,219 @@
  *     error("expected x to be less than 5, but got %d", x);
  * }
- * #endcode
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void error(const char* format, ...);
+ * @endcode
+ *
+ *
+ */
+
+void error(const char *format, ...);
+
+/**
+ * Call this Macro to generate a mbed_error_status_t value for a System error
+ * @param  module           Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
+ * @param  error_code       The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
+ *
+ * @code
+ *
+ * mbed_error_status_t driver_error = MBED_MAKE_SYSTEM_ERROR( MODULE_DRIVER_USB, MBED_ERROR_CODE_INITIALIZATION_FAILED )
+ *
+ * @endcode
+ * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_SYSTEM
+ *
+ */
+#define MBED_MAKE_SYSTEM_ERROR(module, error_code)                   MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, module, error_code)
+
+/**
+ * Call this Macro to generate a mbed_error_status_t value for a Custom error
+ * @param  module           Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
+ * @param  error_code       The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
+ *
+ * @code
+ *
+ * mbed_error_status_t custom_error = MBED_MAKE_CUSTOM_ERROR( MBED_MODULE_APPLICATION, 0xDEAD//16-bit custom error code )
+ *
+ * @endcode
+ * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_CUSTOM
+ *
+ */
+#define MBED_MAKE_CUSTOM_ERROR(module, error_code)                   MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, module, error_code)
+
+/**
+ * Call this Macro to generate a mbed_error_status_t value for a System error
+ * @param  module           Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
+ * @param  error_code       The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
+ *
+ * @code
+ *
+ * mbed_error_status_t new_error = MBED_MAKE_ERROR( MODULE_DRIVER_USB, MBED_ERROR_INITIALIZATION_FAILED )
+ *
+ * @endcode
+ * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_SYSTEM
+ *
+ */
+#define MBED_MAKE_ERROR(module, error_code)                          MBED_MAKE_SYSTEM_ERROR(module, error_code)
+
+/**
+ * Callback/Error hook function prototype. Applications needing a callback when an error is reported can use mbed_set_error_hook function
+ * to register a callback/error hook function using the following prototype. When an error happens in the system error handling
+ * implementation will invoke this callback with the mbed_error_status_t reported and the error context at the time of error.
+ * @param  error_status     mbed_error_status_t status being reported.
+ * @param  error_ctx        Error context structure associated with this error.
+ * @return                  void
+ *
+ */
+typedef void (*mbed_error_hook_t)(const mbed_error_ctx *error_ctx);
+
+/**
+ * Call this function to set a system error/warning. This function will log the error status with the context info and return to caller.
+ *
+ * @param  error_status     mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param  error_msg        The error message to be printed out to STDIO/Serial.
+ * @param  error_value      Value associated with the error status. This would depend on error code/error scenario.
+ * @param  filename         Name of the source file originating the error( Most callers can pass __FILE__ here ).
+ * @param  line_number      The line number of the source file originating the error( Most callers can pass __LINE__ here ) .
+ * @return                  0 or MBED_SUCCESS.
+ *                          MBED_ERROR_INVALID_ARGUMENT if called with invalid error status/codes
+ *
+ * @code
+ *
+ * mbed_error( ERROR_OUT_OF_MEMORY, "Out of memory error", 0, __FILE__, __LINE__ )
+ *
+ * @endcode
+ *
+ * @note See MBED_WARNING/MBED_ERROR macros which provides a wrapper on this API
+ */
+mbed_error_status_t mbed_warning(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number);
+
+/**
+ * Returns the first system error reported.
+ * @return                  mbed_error_status_t code logged for the first error or MBED_SUCCESS if no errors are logged.
+ *
+ */
+mbed_error_status_t mbed_get_first_error(void);
+
+/**
+ * Returns the most recent system error reported.
+ * @return                  mbed_error_status_t code logged for the last error or MBED_SUCCESS if no errors are logged.
+ *
+ */
+mbed_error_status_t mbed_get_last_error(void);
+
+/**
+ * Returns the number of system errors reported after boot.
+ * @return                  int Number of errors reported.
+ *
+ */
+int mbed_get_error_count(void);
+
+/**
+ * Call this function to set a fatal system error and halt the system. This function will log the fatal error with the context info and prints the error report and halts the system.
+ *
+ * @param  error_status     mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param  error_msg        The error message to be printed out to STDIO/Serial.
+ * @param  error_value      Value associated with the error status. This would depend on error code/error scenario.
+ * @param  filename         Name of the source file originating the error( Most callers can pass __FILE__ here ).
+ * @param  line_number      The line number of the source file originating the error( Most callers can pass __LINE__ here ) .
+ * @return                  0 or MBED_SUCCESS.
+ *                          MBED_ERROR_INVALID_ARGUMENT if called with invalid error status/codes
+ *
+ * @code
+ *
+ * mbed_error( MBED_ERROR_PROHIBITED_OPERATION, "Prohibited operation tried", 0, __FILE__, __LINE__ )
+ *
+ * @endcode
+ *
+ * @note See MBED_WARNING/MBED_ERROR macros which provides a wrapper on this API
+ */
+mbed_error_status_t mbed_error(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number);
+
+/**
+ * Registers an application defined error callback with the error handling system.
+ * This function will be called with error context info whenever system handles a mbed_error/mbed_warning call
+ * NOTE: This function should be implemented for re-entrancy as multiple threads may invoke mbed_error which may cause error hook to be called.
+ * @param  custom_error_hook    mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_INVALID_ARGUMENT in case of NULL for custom_error_hook
+ *
+ * @code
+ *
+ * mbed_error_status_t my_custom_error_hook(mbed_error_status_t error_status, const mbed_error_ctx *error_ctx) {
+ *    //Do something with the error_status or error_ctx
+ * }
+ *
+ * mbed_set_error_hook( my_custom_error_hook )
+ *
+ * @endcode
+ * @note The erro hook function implementation should be re-entrant.
+ *
+ */
+mbed_error_status_t mbed_set_error_hook(mbed_error_hook_t custom_error_hook);
+
+/**
+ * Reads the first error context information captured.
+ * @param  error_info           This is the mbed_error_context info captured as part of the first mbed_error call. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_INVALID_ARGUMENT in case of invalid index
+ *
+ */
+mbed_error_status_t mbed_get_first_error_info(mbed_error_ctx *error_info);
+
+/**
+ * Reads the last error context information captured.
+ * @param  error_info           This is the mbed_error_context info captured as part of the last mbed_error call. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
+ * @return                      0 or MBED_ERROR_SUCCESS on success.
+ *                              MBED_ERROR_INVALID_ARGUMENT in case of invalid index
+ *
+ */
+mbed_error_status_t mbed_get_last_error_info(mbed_error_ctx *error_info);
+
+/**
+ * Clears the last error, first error, error count and all entries in the error history.
+ * @return                      0 or MBED_SUCCESS on success.
+ *
+ */
+mbed_error_status_t mbed_clear_all_errors(void);
+
+/**
+ * Generates a mbed_error_status_t value based on passed in values for type, module and error code.
+ * @param  error_type           Error type based on mbed_error_type_t enum.
+ * @param  module               Module type based on mbed_module_type_t enum.
+ * @param  error_code           Error codes defined by mbed_error_code_t enum
+ * @return                      0 or MBED_ERROR_SUCCESS on success.
+ *
+ */
+mbed_error_status_t mbed_make_error(mbed_error_type_t error_type, mbed_module_type_t module, mbed_error_code_t error_code);
+
+/**
+ * Returns the current number of entries in the error history, if there has been more than max number of errors logged the number returned will be max depth of error history.
+ * @return                      Current number of entries in the error history.
+ *
+ */
+int mbed_get_error_hist_count(void);
+
+/**
+ * Reads the error context information for a specific error from error history, specified by the index.
+ *
+ * @param  index                index of the error context entry in the history to be retrieved.\n
+ *                              The number of entries in the error history is configured during build and the max index depends on max depth of error history.\n
+ *                              index = 0 points to the oldest entry in the history, and index = (max history depth - 1) points to the latest entry in the error history.\n
+ * @param  error_info           This is the mbed_error_context info captured as part of the error history. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_INVALID_ARGUMENT in case of invalid index
+ *
+ */
+mbed_error_status_t mbed_get_error_hist_info(int index, mbed_error_ctx *error_info);
+
+/**
+ * Saves the error history information to a file
+ *
+ * @param  path                 path to the file in the filesystem
+ * @return                      0 or MBED_ERROR_SUCCESS on success.
+ *                              MBED_ERROR_WRITE_FAILED if writing to file failed
+ *                              MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ * @note                        Filesystem support is required in order for this function to work.
+ *
+ */
+mbed_error_status_t mbed_save_error_hist(const char *path);
 
 #ifdef __cplusplus
@@ -70,2 +1087,5 @@
 
 /** @}*/
+/** @}*/
+
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error_hist.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error_hist.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error_hist.c	(revision 374)
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_interface.h"
+
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+#include "platform/mbed_error_hist.h"
+
+static mbed_error_ctx mbed_error_ctx_log[MBED_CONF_PLATFORM_ERROR_HIST_SIZE] = {0};
+static int error_log_count = -1;
+
+mbed_error_status_t mbed_error_hist_put(mbed_error_ctx *error_ctx)
+{
+    //Return error if error_ctx is NULL
+    if (NULL == error_ctx) {
+        return MBED_ERROR_INVALID_ARGUMENT;
+    }
+
+    core_util_critical_section_enter();
+    error_log_count++;
+    memcpy(&mbed_error_ctx_log[error_log_count % MBED_CONF_PLATFORM_ERROR_HIST_SIZE], error_ctx, sizeof(mbed_error_ctx));
+    core_util_critical_section_exit();
+
+    return MBED_SUCCESS;
+}
+
+mbed_error_status_t mbed_error_hist_get(int index, mbed_error_ctx *error_ctx)
+{
+    //Return error if index is more than max log size
+    if (index >= MBED_CONF_PLATFORM_ERROR_HIST_SIZE) {
+        return MBED_ERROR_INVALID_ARGUMENT;
+    }
+
+    core_util_critical_section_enter();
+    //calculate the index where we want to pick the ctx
+    if (error_log_count >= MBED_CONF_PLATFORM_ERROR_HIST_SIZE) {
+        index = (error_log_count + index + 1) % MBED_CONF_PLATFORM_ERROR_HIST_SIZE;
+    }
+    core_util_critical_section_exit();
+    memcpy(error_ctx, &mbed_error_ctx_log[index % MBED_CONF_PLATFORM_ERROR_HIST_SIZE], sizeof(mbed_error_ctx));
+
+    return MBED_SUCCESS;
+}
+
+mbed_error_ctx *mbed_error_hist_get_entry(void)
+{
+    core_util_critical_section_enter();
+    error_log_count++;
+    mbed_error_ctx *ctx = &mbed_error_ctx_log[error_log_count % MBED_CONF_PLATFORM_ERROR_HIST_SIZE];
+    core_util_critical_section_exit();
+
+    return ctx;
+}
+
+mbed_error_status_t mbed_error_hist_get_last_error(mbed_error_ctx *error_ctx)
+{
+    if (-1 == error_log_count) {
+        return MBED_ERROR_ITEM_NOT_FOUND;
+    }
+    core_util_critical_section_enter();
+    memcpy(error_ctx, &mbed_error_ctx_log[error_log_count % MBED_CONF_PLATFORM_ERROR_HIST_SIZE], sizeof(mbed_error_ctx));
+    core_util_critical_section_exit();
+
+    return MBED_SUCCESS;
+}
+
+int mbed_error_hist_get_count()
+{
+    return (error_log_count >= MBED_CONF_PLATFORM_ERROR_HIST_SIZE ? MBED_CONF_PLATFORM_ERROR_HIST_SIZE : error_log_count + 1);
+}
+
+mbed_error_status_t mbed_error_hist_reset()
+{
+    core_util_critical_section_enter();
+    error_log_count = -1;
+    core_util_critical_section_exit();
+
+    return MBED_SUCCESS;
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error_hist.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error_hist.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_error_hist.h	(revision 374)
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_HIST_H
+#define MBED_ERROR_HIST_H
+
+#ifndef MBED_CONF_PLATFORM_ERROR_HIST_SIZE
+#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE  4
+#else
+#if MBED_CONF_PLATFORM_ERROR_HIST_SIZE == 0
+#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE  1
+#endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Puts/Adds an error entry into the error history list
+ *
+ * @param  error_ctx            pointer to the mbed_error_ctx struct with the error context
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_WRITE_FAILED if writing to file failed
+ *                              MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_put(mbed_error_ctx *error_ctx);
+
+/*
+ * Reads the error entry from the error list with the specified index
+ *
+ * @param  index                Index of the error context to be retrieved. It starts from 0 and 0 is the oldest.
+ * @param  error_ctx            pointer to the mbed_error_ctx struct where the error context will be filled, this should be allocated by the caller
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_WRITE_FAILED if writing to file failed
+ *                              MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_get(int index, mbed_error_ctx *error_ctx);
+
+/*
+ * Gets a reference to the next error entry in the error log where in the error ctx can be filled in.
+ * Its like reserving the next error entry to fill in the error info
+ *
+ * @return                      Returns the pointer to the next error ctx entry
+ *
+ *
+ */
+mbed_error_ctx *mbed_error_hist_get_entry(void);
+
+/*
+ * Reads the last(latest) error entry from the error history
+ *
+ * @param  error_ctx            pointer to the mbed_error_ctx struct where the error context will be filled, this should be allocated by the caller
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_WRITE_FAILED if writing to file failed
+ *                              MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_get_last_error(mbed_error_ctx *error_ctx);
+
+/*
+ * Returns the number of error entries in the error history list
+ *
+ * @return                      Number of entries in the history list
+ *
+ *
+ */
+int mbed_error_hist_get_count(void);
+
+/*
+ * Resets the error log by resetting the number of errors to 0 and clears all previous errors in the history list
+ *
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_WRITE_FAILED if writing to file failed
+ *                              MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_reset(void);
+
+/*
+ * Saves the error log information to a file
+ *
+ * @param  path                 path to the file in the filesystem
+ * @return                      0 or MBED_SUCCESS on success.
+ *                              MBED_ERROR_WRITE_FAILED if writing to file failed
+ *                              MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ * @note                        Filesystem support is required in order for this function to work.
+ *
+ */
+mbed_error_status_t mbed_save_error_hist(const char *path);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_interface.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_interface.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_interface.c	(revision 374)
@@ -26,9 +26,11 @@
 
 // return true if a debugger is attached, indicating mbed interface is connected
-int mbed_interface_connected(void) {
+int mbed_interface_connected(void)
+{
     return semihost_connected();
 }
 
-int mbed_interface_reset(void) {
+int mbed_interface_reset(void)
+{
     if (mbed_interface_connected()) {
         semihost_reset();
@@ -39,5 +41,6 @@
 }
 
-WEAK int mbed_interface_uid(char *uid) {
+WEAK int mbed_interface_uid(char *uid)
+{
     if (mbed_interface_connected()) {
         return semihost_uid(uid); // Returns 0 if successful, -1 on failure
@@ -48,9 +51,11 @@
 }
 
-int mbed_interface_disconnect(void) {
+int mbed_interface_disconnect(void)
+{
     int res;
     if (mbed_interface_connected()) {
-        if ((res = semihost_disabledebug()) != 0)
+        if ((res = semihost_disabledebug()) != 0) {
             return res;
+        }
         while (mbed_interface_connected());
         return 0;
@@ -60,9 +65,11 @@
 }
 
-int mbed_interface_powerdown(void) {
+int mbed_interface_powerdown(void)
+{
     int res;
     if (mbed_interface_connected()) {
-        if ((res = semihost_powerdown()) != 0)
+        if ((res = semihost_powerdown()) != 0) {
             return res;
+        }
         while (mbed_interface_connected());
         return 0;
@@ -72,15 +79,19 @@
 }
 
-// for backward compatibility
-void mbed_reset(void) {
+MBED_DEPRECATED_SINCE("mbed-os-5.9", "This function shouldn't be used in new code."
+                      "For system reset funcionality use system_reset()")
+void mbed_reset(void)
+{
     mbed_interface_reset();
 }
 
-WEAK int mbed_uid(char *uid) {
+WEAK int mbed_uid(char *uid)
+{
     return mbed_interface_uid(uid);
 }
 #endif
 
-WEAK void mbed_mac_address(char *mac) {
+WEAK void mbed_mac_address(char *mac)
+{
 #if DEVICE_SEMIHOST
     char uid[DEVICE_ID_LENGTH + 1];
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_interface.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_interface.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_interface.h	(revision 374)
@@ -2,4 +2,9 @@
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_interface Network interface and other utility functions
+ * @{
+ */
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -42,4 +47,9 @@
 
 #if DEVICE_SEMIHOST
+
+/**
+ * \defgroup platform_interface interface functions
+ * @{
+ */
 
 /** Functions to control the mbed interface
@@ -114,7 +124,15 @@
 
 /** Print out an error message.  This is typically called when
- * hanlding a crash.
+ * handling a crash.
  *
- * @Note Synchronization level: Interrupt safe
+ * @note Synchronization level: Interrupt safe
+ *
+ * @param format    C string that contains data stream to be printed.
+ *                  Code snippets below show valid format.
+ *
+ * @code
+ * mbed_error_printf("Failed: %s, file: %s, line %d \n", expr, file, line);
+ * @endcode
+ *
  */
 void mbed_error_printf(const char* format, ...);
@@ -123,7 +141,12 @@
  * but uses a va_list.
  *
- * @Note Synchronization level: Interrupt safe
+ * @note Synchronization level: Interrupt safe
+ *
+ * @param format    C string that contains data stream to be printed.
+ * @param arg       Variable arguments list
+ *
  */
 void mbed_error_vfprintf(const char * format, va_list arg);
+/** @}*/
 
 #ifdef __cplusplus
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_mktime.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_mktime.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_mktime.c	(revision 374)
@@ -0,0 +1,193 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_mktime.h"
+
+/* Time constants. */
+#define SECONDS_BY_MINUTES 60
+#define MINUTES_BY_HOUR 60
+#define SECONDS_BY_HOUR (SECONDS_BY_MINUTES * MINUTES_BY_HOUR)
+#define HOURS_BY_DAY 24
+#define SECONDS_BY_DAY (SECONDS_BY_HOUR * HOURS_BY_DAY)
+#define LAST_VALID_YEAR 206
+
+/* Macros which will be used to determine if we are within valid range. */
+#define EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT 3220095     // 7th of February 1970 at 06:28:15
+#define EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT 3133695  // 6th of February 1970 at 06:28:15
+
+/*
+ * 2 dimensional array containing the number of seconds elapsed before a given
+ * month.
+ * The second index map to the month while the first map to the type of year:
+ *   - 0: non leap year
+ *   - 1: leap year
+ */
+static const uint32_t seconds_before_month[2][12] = {
+    {
+        0,
+        31 * SECONDS_BY_DAY,
+        (31 + 28) *SECONDS_BY_DAY,
+        (31 + 28 + 31) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31) *SECONDS_BY_DAY,
+        (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+    },
+    {
+        0,
+        31 * SECONDS_BY_DAY,
+        (31 + 29) *SECONDS_BY_DAY,
+        (31 + 29 + 31) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31) *SECONDS_BY_DAY,
+        (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+    }
+};
+
+bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support)
+{
+    /*
+     * since in practice, the value manipulated by this algorithm lie in the
+     * range: [70 : 206] the algorithm can be reduced to: year % 4 with exception for 200 (year 2100 is not leap year).
+     * The algorithm valid over the full range of value is:
+
+        year = 1900 + year;
+        if (year % 4) {
+            return false;
+        } else if (year % 100) {
+            return true;
+        } else if (year % 400) {
+            return false;
+        }
+        return true;
+
+     */
+    if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && year == 200) {
+        return false; // 2100 is not a leap year
+    }
+
+    return (year) % 4 ? false : true;
+}
+
+bool _rtc_maketime(const struct tm *time, time_t *seconds, rtc_leap_year_support_t leap_year_support)
+{
+    if (seconds == NULL || time == NULL) {
+        return false;
+    }
+
+    /* Partial check for the upper bound of the range - check years only. Full check will be performed after the
+     * elapsed time since the beginning of the year is calculated.
+     */
+    if ((time->tm_year < 70) || (time->tm_year > LAST_VALID_YEAR)) {
+        return false;
+    }
+
+    uint32_t result = time->tm_sec;
+    result += time->tm_min * SECONDS_BY_MINUTES;
+    result += time->tm_hour * SECONDS_BY_HOUR;
+    result += (time->tm_mday - 1) * SECONDS_BY_DAY;
+    result += seconds_before_month[_rtc_is_leap_year(time->tm_year, leap_year_support)][time->tm_mon];
+
+    /* Check if we are within valid range. */
+    if (time->tm_year == LAST_VALID_YEAR) {
+        if ((leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT) ||
+                (leap_year_support == RTC_4_YEAR_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT)) {
+            return false;
+        }
+    }
+
+    if (time->tm_year > 70) {
+        /* Valid in the range [70:206]. */
+        uint32_t count_of_leap_days = ((time->tm_year - 1) / 4) - (70 / 4);
+        if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT) {
+            if (time->tm_year > 200) {
+                count_of_leap_days--; // 2100 is not a leap year
+            }
+        }
+
+        result += (((time->tm_year - 70) * 365) + count_of_leap_days) * SECONDS_BY_DAY;
+    }
+
+    *seconds = result;
+
+    return true;
+}
+
+bool _rtc_localtime(time_t timestamp, struct tm *time_info, rtc_leap_year_support_t leap_year_support)
+{
+    if (time_info == NULL) {
+        return false;
+    }
+
+    uint32_t seconds = (uint32_t)timestamp;
+
+    time_info->tm_sec = seconds % 60;
+    seconds = seconds / 60;   // timestamp in minutes
+    time_info->tm_min = seconds % 60;
+    seconds = seconds / 60;  // timestamp in hours
+    time_info->tm_hour = seconds % 24;
+    seconds = seconds / 24;  // timestamp in days;
+
+    /* Compute the weekday.
+     * The 1st of January 1970 was a Thursday which is equal to 4 in the weekday representation ranging from [0:6].
+     */
+    time_info->tm_wday = (seconds + 4) % 7;
+
+    /* Years start at 70. */
+    time_info->tm_year = 70;
+    while (true) {
+        if (_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 366) {
+            ++time_info->tm_year;
+            seconds -= 366;
+        } else if (!_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 365) {
+            ++time_info->tm_year;
+            seconds -= 365;
+        } else {
+            /* The remaining days are less than a years. */
+            break;
+        }
+    }
+
+    time_info->tm_yday = seconds;
+
+    /* Convert days into seconds and find the current month. */
+    seconds *= SECONDS_BY_DAY;
+    time_info->tm_mon = 11;
+    bool leap = _rtc_is_leap_year(time_info->tm_year, leap_year_support);
+    for (uint32_t i = 0; i < 12; ++i) {
+        if ((uint32_t) seconds < seconds_before_month[leap][i]) {
+            time_info->tm_mon = i - 1;
+            break;
+        }
+    }
+
+    /* Remove month from timestamp and compute the number of days.
+     * Note: unlike other fields, days are not 0 indexed.
+     */
+    seconds -= seconds_before_month[leap][time_info->tm_mon];
+    time_info->tm_mday = (seconds / SECONDS_BY_DAY) + 1;
+
+    return true;
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_mktime.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_mktime.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_mktime.h	(revision 374)
@@ -0,0 +1,131 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_MKTIME_H
+#define MBED_MKTIME_H
+
+#include <time.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup platform_mktime mktime functions
+ * @{
+ */
+
+/* Time range across the whole 32-bit range should be supported which means that years in range 1970 - 2106 can be
+ * encoded. We have two types of RTC devices:
+ * a) RTCs which handles all leap years in the mentioned year range correctly. Leap year is determined by checking if
+ *    the year counter value is divisible by 400, 100, and 4. No problem here.
+ * b) RTCs which handles leap years correctly up to 2100. The RTC does a simple bit comparison to see if the two
+ *    lowest order bits of the year counter are zero. In this case 2100 year will be considered
+ *    incorrectly as a leap year, so the last valid point in time will be 28.02.2100 23:59:59 and next day will be
+ *    29.02.2100 (invalid). So after 28.02.2100 the day counter will be off by a day.
+ */
+typedef enum {
+    RTC_FULL_LEAP_YEAR_SUPPORT,
+    RTC_4_YEAR_LEAP_YEAR_SUPPORT
+} rtc_leap_year_support_t;
+
+/** Compute if a year is a leap year or not.
+ *
+ * @param year The year to test it shall be in the range [70:206]. Year 0 is
+ * translated into year 1900 CE.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ *
+ * @return true if the year in input is a leap year and false otherwise.
+ *
+ * @note For use by the HAL only
+ * @note Year 2100 is treated differently for devices with full leap year support and devices with
+ * partial leap year support. Devices with partial leap year support treats 2100 as a leap year.
+ */
+bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support);
+
+/* Convert a calendar time into time since UNIX epoch as a time_t.
+ *
+ * This function is a thread safe (partial) replacement for mktime. It is
+ * tailored around RTC peripherals needs and is not by any mean a complete
+ * replacement of mktime.
+ *
+ * @param time The calendar time to convert into a time_t since epoch.
+ * The fields from tm used for the computation are:
+ *   - tm_sec
+ *   - tm_min
+ *   - tm_hour
+ *   - tm_mday
+ *   - tm_mon
+ *   - tm_year
+ * Other fields are ignored and won't be renormalized by a call to this function.
+ * A valid calendar time is comprised between:
+ * the 1st of January 1970 at 00:00:00 to the 7th of February 2106 at 06:28:15.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ * @param seconds holder for the result - calendar time as seconds since UNIX epoch.
+ *
+ * @return true on success, false if conversion error occurred.
+ *
+ * @note Leap seconds are not supported.
+ * @note Values in output range from 0 to UINT_MAX.
+ * @note Full and partial leap years support.
+ * @note For use by the HAL only
+ */
+bool _rtc_maketime(const struct tm *time, time_t *seconds, rtc_leap_year_support_t leap_year_support);
+
+/* Convert a given time in seconds since epoch into calendar time.
+ *
+ * This function is a thread safe (partial) replacement for localtime. It is
+ * tailored around RTC peripherals specification and is not by any means a
+ * complete of localtime.
+ *
+ * @param timestamp The time (in seconds) to convert into calendar time. Valid
+ * input are in the range [0 : UINT32_MAX].
+ * @param calendar_time Pointer to the object which will contain the result of
+ * the conversion. The tm fields filled by this function are:
+ *   - tm_sec
+ *   - tm_min
+ *   - tm_hour
+ *   - tm_mday
+ *   - tm_mon
+ *   - tm_year
+ *   - tm_wday
+ *   - tm_yday
+ * The object remains untouched if the time in input is invalid.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ * @return true if the conversion was successful, false otherwise.
+ *
+ * @note For use by the HAL only.
+ * @note Full and partial leap years support.
+ */
+bool _rtc_localtime(time_t timestamp, struct tm *time_info, rtc_leap_year_support_t leap_year_support);
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_MKTIME_H */
+
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_power_mgmt.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_power_mgmt.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_power_mgmt.h	(revision 374)
@@ -0,0 +1,250 @@
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_power_mgmt Power management functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_POWER_MGMT_H
+#define MBED_POWER_MGMT_H
+
+#include "hal/sleep_api.h"
+#include "platform/mbed_toolchain.h"
+#include "hal/ticker_api.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Sleep manager API
+ * The sleep manager provides API to automatically select sleep mode.
+ *
+ * There are two sleep modes:
+ * - sleep
+ * - deepsleep
+ *
+ * Use locking/unlocking deepsleep for drivers that depend on features that
+ * are not allowed (=disabled) during the deepsleep. For instance, high frequency
+ * clocks.
+ *
+ * Example:
+ * @code
+ *
+ * void driver::handler()
+ * {
+ *     if (_sensor.get_event()) {
+ *         // any event - we are finished, unlock the deepsleep
+ *         sleep_manager_unlock_deep_sleep();
+ *         _callback();
+ *     }
+ * }
+ *
+ * int driver::measure(event_t event, callback_t& callback)
+ * {
+ *      _callback = callback;
+ *      sleep_manager_lock_deep_sleep();
+ *      // start async transaction, we are waiting for an event
+ *      return _sensor.start(event, callback);
+ * }
+ * @endcode
+ */
+#ifdef MBED_SLEEP_TRACING_ENABLED
+
+void sleep_tracker_lock(const char *const filename, int line);
+void sleep_tracker_unlock(const char *const filename, int line);
+
+#define sleep_manager_lock_deep_sleep()              \
+    do                                               \
+    {                                                \
+        sleep_manager_lock_deep_sleep_internal();    \
+        sleep_tracker_lock(MBED_FILENAME, __LINE__); \
+    } while (0);
+
+#define sleep_manager_unlock_deep_sleep()              \
+    do                                                 \
+    {                                                  \
+        sleep_manager_unlock_deep_sleep_internal();    \
+        sleep_tracker_unlock(MBED_FILENAME, __LINE__); \
+    } while (0);
+
+#else
+
+#define sleep_manager_lock_deep_sleep() \
+    sleep_manager_lock_deep_sleep_internal()
+
+#define sleep_manager_unlock_deep_sleep() \
+    sleep_manager_unlock_deep_sleep_internal()
+
+#endif // MBED_SLEEP_TRACING_ENABLED
+
+/** Lock the deep sleep mode
+ *
+ * This locks the automatic deep mode selection.
+ * sleep_manager_sleep_auto() will ignore deepsleep mode if
+ * this function is invoked at least once (the internal counter is non-zero)
+ *
+ * Use this locking mechanism for interrupt driven API that are
+ * running in the background and deepsleep could affect their functionality
+ *
+ * The lock is a counter, can be locked up to USHRT_MAX
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_lock_deep_sleep_internal(void);
+
+/** Unlock the deep sleep mode
+ *
+ * Use unlocking in pair with sleep_manager_lock_deep_sleep().
+ *
+ * The lock is a counter, should be equally unlocked as locked
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_unlock_deep_sleep_internal(void);
+
+/** Get the status of deep sleep allowance for a target
+ *
+ * @return true if a target can go to deepsleep, false otherwise
+ */
+bool sleep_manager_can_deep_sleep(void);
+
+/** Check if the target can deep sleep within a period of time
+ *
+ * This function in intended for use in testing. The amount
+ * of time this functions waits for deeps sleep to be available
+ * is currently 2ms. This may change in the future depending
+ * on testing requirements.
+ *
+ * @return true if a target can go to deepsleep, false otherwise
+ */
+bool sleep_manager_can_deep_sleep_test_check(void);
+
+/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based
+ *  on the deepsleep locking counter
+ *
+ * This function is IRQ and thread safe
+ *
+ * @note
+ * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
+ * to be active for debug modes.
+ *
+ */
+void sleep_manager_sleep_auto(void);
+
+/** Send the microcontroller to sleep
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
+ * @note This function will be a noop if the following conditions are met:
+ *   - The RTOS is present
+ *   - The processor turn off the Systick clock during sleep
+ *   - The target does not implement tickless mode
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+static inline void mcu_sleep(void)
+{
+#if DEVICE_SLEEP
+#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
+    sleep_manager_sleep_auto();
+#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
+#endif /* DEVICE_SLEEP */
+}
+
+/** Send the microcontroller to deep sleep
+ *
+ * @deprecated
+ * Do not use this function. Applications should use sleep() API which puts the system in deepsleep mode if supported.
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep. This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+
+MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
+static inline void deepsleep(void)
+{
+#if DEVICE_SLEEP
+    sleep_manager_sleep_auto();
+#endif /* DEVICE_SLEEP */
+}
+
+/** Resets the processor and most of the sub-system
+ *
+ * @note Does not affect the debug sub-system
+ */
+static inline void system_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+/** Provides the time spent in sleep mode since boot.
+ *
+ *  @return  Time spent in sleep
+ *  @note  Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_time_sleep(void);
+
+/** Provides the time spent in deep sleep mode since boot.
+ *
+ *  @return  Time spent in deep sleep
+ *  @note  Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_time_deepsleep(void);
+
+/** Provides the time spent in idle mode since boot.
+ *
+ * @return  Idle thread time.
+ * @note  Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_time_idle(void);
+
+/** Provides the time since the system is up i.e. boot.
+ *
+ * @return  System uptime.
+ * @note  Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_uptime(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_preprocessor.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_preprocessor.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_preprocessor.h	(revision 374)
@@ -1,4 +1,9 @@
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_preprocessor preprocessor macros
+ * @{
+ */
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -48,6 +53,34 @@
 #define MBED_STRINGIFY_(a) #a
 
+/** MBED_STRLEN
+ *  Reports string token length
+ *
+ *  @note
+ *  Expands tokens before calculating length
+ *
+ *  @code
+ *  // Get string length
+ *  const int len = MBED_STRLEN("Get the length")
+ *  @endcode
+ */
+#define MBED_STRLEN(a) MBED_STRLEN_(a)
+#define MBED_STRLEN_(a) (sizeof(a) - 1)
+
+/** MBED_COUNT_VA_ARGS(...)
+ *  Reports number of tokens passed
+ *
+ *  @note
+ *  Token limit is 16
+ *
+ *  @code
+ *  // Get number of arguments
+ *  const int count = MBED_COUNT_VA_ARGS("Address 0x%x, Data[0] = %d Data[1] = %d", 0x20001234, 10, 20)
+ *  @endcode
+ */
+#define MBED_COUNT_VA_ARGS(...) GET_NTH_ARG_(__VA_ARGS__, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
+#define GET_NTH_ARG_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, N, ...) N
 
 #endif
 
 /** @}*/
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_retarget.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_retarget.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_retarget.h	(revision 374)
@@ -0,0 +1,30 @@
+#ifndef RETARGET_H
+#define RETARGET_H
+
+#ifdef __cplusplus
+#include <cstdio>
+#else
+#include <stdio.h>
+#endif //__cplusplus
+
+#include <errno.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/statvfs.h>
+#include <unistd.h>
+
+#ifdef __cplusplus
+namespace mbed {
+
+class FileHandle;
+class DirHandle;
+
+std::FILE *fdopen(FileHandle *fh, const char *mode);
+
+}
+#endif
+
+#endif //RETARGET_H
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_rtc_time.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_rtc_time.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_rtc_time.h	(revision 374)
@@ -2,4 +2,8 @@
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_rtc_time rtc_time functions
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -62,5 +66,5 @@
  * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
  *
- * @Note Synchronization level: Thread safe
+ * @note Synchronization level: Thread safe
  *
  * Example:
@@ -77,5 +81,5 @@
 /** Attach an external RTC to be used for the C time functions
  *
- * @Note Synchronization level: Thread safe
+ * @note Synchronization level: Thread safe
  *
  * @param read_rtc pointer to function which returns current UNIX timestamp
@@ -91,2 +95,3 @@
 
 /** @}*/
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_semihost_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_semihost_api.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_semihost_api.c	(revision 374)
@@ -45,5 +45,6 @@
 
 #if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char* name, int openmode) {
+FILEHANDLE semihost_open(const char* name, int openmode)
+{
     uint32_t args[3];
     args[0] = (uint32_t)name;
@@ -53,10 +54,14 @@
 }
 
-int semihost_close(FILEHANDLE fh) {
+int semihost_close(FILEHANDLE fh)
+{
     return __semihost(SYS_CLOSE, &fh);
 }
 
-int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
-    if (length == 0) return 0;
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode)
+{
+    if (length == 0) {
+        return 0;
+    }
 
     uint32_t args[3];
@@ -67,5 +72,6 @@
 }
 
-int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+int semihost_read(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode)
+{
     uint32_t args[3];
     args[0] = (uint32_t)fh;
@@ -75,9 +81,11 @@
 }
 
-int semihost_istty(FILEHANDLE fh) {
+int semihost_istty(FILEHANDLE fh)
+{
     return __semihost(SYS_ISTTY, &fh);
 }
 
-int semihost_seek(FILEHANDLE fh, long position) {
+int semihost_seek(FILEHANDLE fh, long position)
+{
     uint32_t args[2];
     args[0] = (uint32_t)fh;
@@ -86,13 +94,16 @@
 }
 
-int semihost_ensure(FILEHANDLE fh) {
+int semihost_ensure(FILEHANDLE fh)
+{
     return __semihost(SYS_ENSURE, &fh);
 }
 
-long semihost_flen(FILEHANDLE fh) {
+long semihost_flen(FILEHANDLE fh)
+{
     return __semihost(SYS_FLEN, &fh);
 }
 
-int semihost_remove(const char *name) {
+int semihost_remove(const char *name)
+{
     uint32_t args[2];
     args[0] = (uint32_t)name;
@@ -101,5 +112,6 @@
 }
 
-int semihost_rename(const char *old_name, const char *new_name) {
+int semihost_rename(const char *old_name, const char *new_name)
+{
     uint32_t args[4];
     args[0] = (uint32_t)old_name;
@@ -111,10 +123,12 @@
 #endif
 
-int semihost_exit(void) {
+int semihost_exit(void)
+{
     uint32_t args[4];
     return __semihost(SYS_EXIT, args);
 }
 
-int semihost_uid(char *uid) {
+int semihost_uid(char *uid)
+{
     uint32_t args[2];
     args[0] = (uint32_t)uid;
@@ -123,5 +137,6 @@
 }
 
-int semihost_reset(void) {
+int semihost_reset(void)
+{
     // Does not normally return, however if used with older firmware versions
     // that do not support this call it will return -1.
@@ -129,9 +144,11 @@
 }
 
-int semihost_vbus(void) {
+int semihost_vbus(void)
+{
     return __semihost(USR_VBUS, NULL);
 }
 
-int semihost_powerdown(void) {
+int semihost_powerdown(void)
+{
     return __semihost(USR_POWERDOWN, NULL);
 }
@@ -139,5 +156,6 @@
 #if DEVICE_DEBUG_AWARENESS
 
-int semihost_connected(void) {
+int semihost_connected(void)
+{
     return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
 }
@@ -147,10 +165,12 @@
 static int is_debugger_attached = 1;
 
-int semihost_connected(void) {
+int semihost_connected(void)
+{
     return is_debugger_attached;
 }
 #endif
 
-int semihost_disabledebug(void) {
+int semihost_disabledebug(void)
+{
     uint32_t args[1];
 #if !(DEVICE_DEBUG_AWARENESS)
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_semihost_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_semihost_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_semihost_api.h	(revision 374)
@@ -1,5 +1,3 @@
 
-/** \addtogroup platform */
-/** @{*/
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -29,8 +27,9 @@
 #if DEVICE_SEMIHOST
 
-#ifndef __CC_ARM
+#if !defined(__CC_ARM) && !defined(__ARMCC_VERSION)
 
 #if defined(__ICCARM__)
-static inline int __semihost(int reason, const void *arg) {
+static inline int __semihost(int reason, const void *arg)
+{
     return __semihosting(reason, (void*)arg);
 }
@@ -47,5 +46,6 @@
 #endif
 
-static inline int __semihost(int reason, const void *arg) {
+static inline int __semihost(int reason, const void *arg)
+{
     int value;
 
@@ -96,3 +96,3 @@
 #endif
 
-/** @}*/
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_stats.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_stats.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_stats.c	(revision 374)
@@ -0,0 +1,150 @@
+#include "platform/mbed_assert.h"
+#include "mbed_stats.h"
+#include "mbed_power_mgmt.h"
+#include "platform/mbed_version.h"
+#include <string.h>
+#include <stdlib.h>
+
+#include "device.h"
+#if 0 //def MBED_CONF_RTOS_PRESENT
+#include "cmsis_os2.h"
+#include "rtos/rtos_idle.h"
+#elif defined(MBED_STACK_STATS_ENABLED) || defined(MBED_THREAD_STATS_ENABLED) || defined(MBED_CPU_STATS_ENABLED)
+#warning Statistics are currently not supported without the rtos.
+#endif
+
+#if defined(MBED_CPU_STATS_ENABLED) && (!defined(DEVICE_LPTICKER) || !defined(DEVICE_SLEEP))
+#warning CPU statistics are not supported without low power timer support.
+#endif
+
+void mbed_stats_cpu_get(mbed_stats_cpu_t *stats)
+{
+    MBED_ASSERT(stats != NULL);
+    memset(stats, 0, sizeof(mbed_stats_cpu_t));
+#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER) && defined(DEVICE_SLEEP)
+    stats->uptime = mbed_uptime();
+    stats->idle_time = mbed_time_idle();
+    stats->sleep_time = mbed_time_sleep();
+    stats->deep_sleep_time = mbed_time_deepsleep();
+#endif
+}
+
+// note: mbed_stats_heap_get defined in mbed_alloc_wrappers.cpp
+void mbed_stats_stack_get(mbed_stats_stack_t *stats)
+{
+    MBED_ASSERT(stats != NULL);
+    memset(stats, 0, sizeof(mbed_stats_stack_t));
+
+#if defined(MBED_STACK_STATS_ENABLED) && defined(MBED_CONF_RTOS_PRESENT)
+    uint32_t thread_n = osThreadGetCount();
+    unsigned i;
+    osThreadId_t *threads;
+
+    threads = malloc(sizeof(osThreadId_t) * thread_n);
+    // Don't fail on lack of memory
+    if (!threads) {
+        return;
+    }
+
+    osKernelLock();
+    thread_n = osThreadEnumerate(threads, thread_n);
+
+    for (i = 0; i < thread_n; i++) {
+        uint32_t stack_size = osThreadGetStackSize(threads[i]);
+        stats->max_size += stack_size - osThreadGetStackSpace(threads[i]);
+        stats->reserved_size += stack_size;
+        stats->stack_cnt++;
+    }
+    osKernelUnlock();
+
+    free(threads);
+#endif
+}
+
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count)
+{
+    MBED_ASSERT(stats != NULL);
+    memset(stats, 0, count * sizeof(mbed_stats_stack_t));
+
+    size_t i = 0;
+
+#if defined(MBED_STACK_STATS_ENABLED) && defined(MBED_CONF_RTOS_PRESENT)
+    osThreadId_t *threads;
+
+    threads = malloc(sizeof(osThreadId_t) * count);
+    // Don't fail on lack of memory
+    if (!threads) {
+        return 0;
+    }
+
+    osKernelLock();
+    count = osThreadEnumerate(threads, count);
+
+    for (i = 0; i < count; i++) {
+        uint32_t stack_size = osThreadGetStackSize(threads[i]);
+        stats[i].max_size = stack_size - osThreadGetStackSpace(threads[i]);
+        stats[i].reserved_size = stack_size;
+        stats[i].thread_id = (uint32_t)threads[i];
+        stats[i].stack_cnt = 1;
+    }
+    osKernelUnlock();
+
+    free(threads);
+#endif
+
+    return i;
+}
+
+size_t mbed_stats_thread_get_each(mbed_stats_thread_t *stats, size_t count)
+{
+    MBED_ASSERT(stats != NULL);
+    memset(stats, 0, count * sizeof(mbed_stats_thread_t));
+    size_t i = 0;
+
+#if defined(MBED_THREAD_STATS_ENABLED) && defined(MBED_CONF_RTOS_PRESENT)
+    osThreadId_t *threads;
+
+    threads = malloc(sizeof(osThreadId_t) * count);
+    MBED_ASSERT(threads != NULL);
+
+    osKernelLock();
+    count = osThreadEnumerate(threads, count);
+
+    for (i = 0; i < count; i++) {
+        stats[i].id = (uint32_t)threads[i];
+        stats[i].state = (uint32_t)osThreadGetState(threads[i]);
+        stats[i].priority = (uint32_t)osThreadGetPriority(threads[i]);
+        stats[i].stack_size = osThreadGetStackSize(threads[i]);
+        stats[i].stack_space = osThreadGetStackSpace(threads[i]);
+        stats[i].name = osThreadGetName(threads[i]);
+    }
+    osKernelUnlock();
+    free(threads);
+#endif
+    return i;
+}
+
+void mbed_stats_sys_get(mbed_stats_sys_t *stats)
+{
+    MBED_ASSERT(stats != NULL);
+    memset(stats, 0, sizeof(mbed_stats_sys_t));
+
+#if defined(MBED_SYS_STATS_ENABLED)
+    stats->os_version = MBED_VERSION;
+#if defined(__CORTEX_M)
+    stats->cpu_id = SCB->CPUID;
+#endif
+#if defined(__IAR_SYSTEMS_ICC__)
+    stats->compiler_id = IAR;
+    stats->compiler_version = __VER__;
+#elif defined(__CC_ARM)
+    stats->compiler_id = ARM;
+    stats->compiler_version = __ARMCC_VERSION;
+#elif defined(__GNUC__)
+    stats->compiler_id = GCC_ARM;
+    stats->compiler_version = (__GNUC__ * 10000 + __GNUC_MINOR__ * 100);
+#endif
+
+#endif
+    return;
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_stats.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_stats.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_stats.h	(revision 374)
@@ -0,0 +1,161 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_stats stats functions
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STATS_H
+#define MBED_STATS_H
+#include <stdint.h>
+#include <stddef.h>
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef MBED_ALL_STATS_ENABLED
+#define MBED_SYS_STATS_ENABLED      1
+#define MBED_STACK_STATS_ENABLED    1
+#define MBED_CPU_STATS_ENABLED      1
+#define MBED_HEAP_STATS_ENABLED     1
+#define MBED_THREAD_STATS_ENABLED   1
+#endif
+
+/**
+ * struct mbed_stats_heap_t definition
+ */
+typedef struct {
+    uint32_t current_size;      /**< Bytes allocated currently. */
+    uint32_t max_size;          /**< Max bytes allocated at a given time. */
+    uint32_t total_size;        /**< Cumulative sum of bytes ever allocated. */
+    uint32_t reserved_size;     /**< Current number of bytes allocated for the heap. */
+    uint32_t alloc_cnt;         /**< Current number of allocations. */
+    uint32_t alloc_fail_cnt;    /**< Number of failed allocations. */
+} mbed_stats_heap_t;
+
+/**
+ *  Fill the passed in heap stat structure with heap stats.
+ *
+ *  @param stats    A pointer to the mbed_stats_heap_t structure to fill
+ */
+void mbed_stats_heap_get(mbed_stats_heap_t *stats);
+
+/**
+ * struct mbed_stats_stack_t definition
+ */
+typedef struct {
+    uint32_t thread_id;         /**< Identifier for thread that owns the stack or 0 if multiple threads. */
+    uint32_t max_size;          /**< Maximum number of bytes used on the stack. */
+    uint32_t reserved_size;     /**< Current number of bytes allocated for the stack. */
+    uint32_t stack_cnt;         /**< Number of stacks stats accumulated in the structure. */
+} mbed_stats_stack_t;
+
+/**
+ *  Fill the passed in structure with stack stats accumulated for all threads. The thread_id will be 0
+ *  and stack_cnt will represent number of threads.
+ *
+ *  @param stats    A pointer to the mbed_stats_stack_t structure to fill
+ */
+void mbed_stats_stack_get(mbed_stats_stack_t *stats);
+
+/**
+ *  Fill the passed array of stat structures with the stack stats for each available thread.
+ *
+ *  @param stats    A pointer to an array of mbed_stats_stack_t structures to fill
+ *  @param count    The number of mbed_stats_stack_t structures in the provided array
+ *  @return         The number of mbed_stats_stack_t structures that have been filled,
+ *                  this is equal to the number of stacks on the system.
+ */
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
+
+/**
+ * struct mbed_stats_cpu_t definition
+ */
+typedef struct {
+    us_timestamp_t uptime;            /**< Time since system is up and running */
+    us_timestamp_t idle_time;         /**< Time spent in idle thread since system is up and running */
+    us_timestamp_t sleep_time;        /**< Time spent in sleep since system is up and running */
+    us_timestamp_t deep_sleep_time;   /**< Time spent in deep sleep since system is up and running */
+} mbed_stats_cpu_t;
+
+/**
+ *  Fill the passed in CPU stat structure with CPU statistics.
+ *
+ *  @param stats    A pointer to the mbed_stats_cpu_t structure to fill
+ */
+void mbed_stats_cpu_get(mbed_stats_cpu_t *stats);
+
+/**
+ * struct mbed_stats_thread_t definition
+ */
+typedef struct {
+    uint32_t id;                /**< Thread Object Identifier */
+    uint32_t state;             /**< Thread Object State */
+    uint32_t priority;          /**< Thread Priority */
+    uint32_t stack_size;        /**< Thread Stack Size */
+    uint32_t stack_space;       /**< Thread remaining stack size */
+    const char   *name;         /**< Thread Object name */
+} mbed_stats_thread_t;
+
+/**
+ *  Fill the passed array of stat structures with the thread stats for each available thread.
+ *
+ *  @param stats    A pointer to an array of mbed_stats_thread_t structures to fill
+ *  @param count    The number of mbed_stats_thread_t structures in the provided array
+ *  @return         The number of mbed_stats_thread_t structures that have been filled,
+ *                  this is equal to the number of threads on the system.
+ */
+size_t mbed_stats_thread_get_each(mbed_stats_thread_t *stats, size_t count);
+
+/**
+ * enum mbed_compiler_id_t definition
+ */
+typedef enum {
+    ARM = 1,                    /**< ARM */
+    GCC_ARM,                    /**< GNU ARM */
+    IAR                         /**< IAR */
+} mbed_compiler_id_t;
+
+/**
+ * struct mbed_stats_sys_t definition
+ */
+typedef struct {
+    uint32_t os_version;                /**< Mbed OS Version (Release only) */
+    uint32_t cpu_id;                    /**< CPUID Register data (Cortex-M only supported) */
+    mbed_compiler_id_t compiler_id;     /**< Compiler ID \ref mbed_compiler_id_t */
+    uint32_t compiler_version;          /**< Compiler version */
+} mbed_stats_sys_t;
+
+/**
+ *  Fill the passed in sys stat structure with system stats.
+ *
+ *  @param stats    A pointer to the mbed_stats_sys_t structure to fill
+ */
+void mbed_stats_sys_get(mbed_stats_sys_t *stats);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_toolchain.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_toolchain.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_toolchain.h	(revision 374)
@@ -2,4 +2,9 @@
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_toolchain Toolchain functions
+ * @{
+ */
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -93,9 +98,35 @@
 #endif
 
+/** MBED_USED
+ *  Inform the compiler that a static variable is to be retained in the object file, even if it is unreferenced.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_USED int foo;
+ *
+ *  @endcode
+ */
+#ifndef MBED_USED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_USED __attribute__((used))
+#elif defined(__ICCARM__)
+#define MBED_USED __root
+#else
+#define MBED_USED
+#endif
+#endif
+
 /** MBED_WEAK
  *  Mark a function as being weak.
  *  
  *  @note
- *  weak functions are not friendly to making code re-usable, as they can only
+ *  Functions should only be marked as weak in the source file. The header file
+ *  should contain a regular function declaration to insure the function is emitted.
+ *  A function marked weak will not be emitted if an alternative non-weak
+ *  implementation is defined.
+ *
+ *  @note
+ *  Weak functions are not friendly to making code re-usable, as they can only
  *  be overridden once (and if they are multiply overridden the linker will emit
  *  no warning). You should not normally use weak symbols as part of the API to
@@ -135,4 +166,25 @@
 #else
 #define MBED_PURE
+#endif
+#endif
+
+/** MBED_NOINLINE
+ *  Declare a function that must not be inlined.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_NOINLINE void foo() {
+ *
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_NOINLINE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_NOINLINE __attribute__((noinline))
+#elif defined(__ICCARM__)
+#define MBED_NOINLINE _Pragma("inline=never")
+#else
+#define MBED_NOINLINE
 #endif
 #endif
@@ -279,4 +331,64 @@
 #endif
 
+/**
+ * Macro expanding to a string literal of the enclosing function name.
+ *
+ * The string returned takes into account language specificity and yield human
+ * readable content.
+ *
+ * As an example, if the macro is used within a C++ function then the string
+ * literal containing the function name will contain the complete signature of
+ * the function - including template parameters - and namespace qualifications.
+ */
+#ifndef MBED_PRETTY_FUNCTION
+#define MBED_PRETTY_FUNCTION __PRETTY_FUNCTION__
+#endif
+
+#ifndef MBED_PRINTF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx)))
+#else
+#define MBED_PRINTF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_PRINTF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx, first_param_idx)))
+#else
+#define MBED_SCANF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_SCANF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+// Macro containing the filename part of the value of __FILE__. Defined as
+// string literal.
+#ifndef MBED_FILENAME
+#if defined(__CC_ARM)
+#define MBED_FILENAME __MODULE__
+#elif defined(__GNUC__)
+#define MBED_FILENAME (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__)
+#elif defined(__ICCARM__)
+#define MBED_FILENAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : strrchr(__FILE__, '\\') ? strrchr(__FILE__, '\\') + 1 : __FILE__)
+#else
+#define MBED_FILENAME __FILE__
+#endif
+#endif // #ifndef MBED_FILENAME
+
 // FILEHANDLE declaration
 #if defined(TOOLCHAIN_ARM)
@@ -301,5 +413,27 @@
 #endif
 
+/** MBED_NONSECURE_ENTRY
+ *  Declare a function that can be called from non-secure world or secure world
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_NONSECURE_ENTRY void foo() {
+ *
+ *  }
+ *  @endcode
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)
+#if defined (__ICCARM__)
+#define MBED_NONSECURE_ENTRY       __cmse_nonsecure_entry
+#else
+#define MBED_NONSECURE_ENTRY       __attribute__((cmse_nonsecure_entry))
+#endif
+#else
+#define MBED_NONSECURE_ENTRY
+#endif
+
 #endif
 
 /** @}*/
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_version.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_version.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_version.h	(revision 374)
@@ -0,0 +1,71 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_version Version macros
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_VERSION_H
+#define MBED_VERSION_H
+
+/** MBED_MAJOR_VERSION
+  * Mbed OS major version
+  *
+  * @note 99 is default value for development version (master branch)
+  */
+#define MBED_MAJOR_VERSION 5
+
+/** MBED_MINOR_VERSION
+  * Mbed OS minor version
+  *
+  * @note 99 is default value for development version (master branch)
+  */
+#define MBED_MINOR_VERSION 10
+
+/** MBED_PATCH_VERSION
+  * Mbed OS patch version
+  *
+  * @note 99 is default value for development version (master branch)
+  */
+#define MBED_PATCH_VERSION 0
+
+#define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))
+
+/** MBED_VERSION
+  * Mbed OS 5 version (MMmmpp - M(Major); m(minor); p(patch))
+  *
+  * @note 999999 is default value for development version (master branch)
+  */
+#define MBED_VERSION MBED_ENCODE_VERSION(MBED_MAJOR_VERSION, MBED_MINOR_VERSION, MBED_PATCH_VERSION)
+
+/** MBED_VERSION_CHECK
+  * Macro can be used to check minimum Mbed OS version required for feature/library. If current version
+  * is less than required, it will assert.
+  *
+  * @note: Version of master branch will be 999999 as default, hence no assert/warning is provided for
+  * master branch code
+  */
+#define MBED_VERSION_CHECK(major, minor, patch) do { \
+                                       MBED_STATIC_ASSERT((MBED_VERSION >= MBED_ENCODE_VERSION((major),(minor),(patch))), "Incompatible mbed-os version detected!!"); \
+                                     } while(0)
+
+#endif
+
+/** @}*/
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_wait_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_wait_api.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_wait_api.h	(revision 374)
@@ -2,4 +2,9 @@
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_wait_api wait_api functions
+ * @{
+ */
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
@@ -42,4 +47,5 @@
  *     }
  * }
+ * @endcode
  */
 
@@ -48,4 +54,9 @@
  *
  *  @param s number of seconds to wait
+ *
+ *  @note
+ *    If the RTOS is present, this function always spins to get the exact number of microseconds,
+ *    which potentially affects power (such as preventing deep sleep) and multithread performance.
+ *    You can avoid it by using Thread::wait().
  */
 void wait(float s);
@@ -54,4 +65,9 @@
  *
  *  @param ms the whole number of milliseconds to wait
+ *
+ *  @note
+ *    If the RTOS is present, this function always spins to get the exact number of microseconds,
+ *    which potentially affects power (such as preventing deep sleep) and multithread performance.
+ *    You can avoid it by using Thread::wait().
  */
 void wait_ms(int ms);
@@ -60,4 +76,8 @@
  *
  *  @param us the whole number of microseconds to wait
+ *
+ *  @note
+ *    If the RTOS is present, this function always spins to get the exact number of microseconds,
+ *    which potentially affects power (such as preventing deep sleep) and multithread performance.
  */
 void wait_us(int us);
@@ -70,2 +90,3 @@
 
 /** @}*/
+/** @}*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_wait_api_no_rtos.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_wait_api_no_rtos.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/platform/mbed_wait_api_no_rtos.c	(revision 374)
@@ -22,15 +22,19 @@
 #include "hal/us_ticker_api.h"
 
-void wait(float s) {
+void wait(float s)
+{
     wait_us(s * 1000000.0f);
 }
 
-void wait_ms(int ms) {
+void wait_ms(int ms)
+{
     wait_us(ms * 1000);
 }
 
-void wait_us(int us) {
-    uint32_t start = us_ticker_read();
-    while ((us_ticker_read() - start) < (uint32_t)us);
+void wait_us(int us)
+{
+    const ticker_data_t *const ticker = get_us_ticker_data();
+    uint32_t start = ticker_read(ticker);
+    while ((ticker_read(ticker) - start) < (uint32_t)us);
 }
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/rtos/TARGET_CORTEX/mbed_rtx_conf.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/rtos/TARGET_CORTEX/mbed_rtx_conf.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/rtos/TARGET_CORTEX/mbed_rtx_conf.h	(revision 374)
@@ -0,0 +1,251 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_RTX_CONF_H
+#define MBED_RTX_CONF_H
+
+#include "mbed_rtx.h"
+
+/** Any access to RTX5 specific data structures used in common code should be wrapped in ifdef MBED_OS_BACKEND_RTX5 */
+#define MBED_OS_BACKEND_RTX5
+
+/** The thread's stack size can be configured by the application, if not explicitly specified it'll default to 4K */
+#ifndef MBED_CONF_APP_THREAD_STACK_SIZE
+#define MBED_CONF_APP_THREAD_STACK_SIZE 4096
+#endif
+
+#define OS_STACK_SIZE               MBED_CONF_APP_THREAD_STACK_SIZE
+
+/** The timer thread's stack size can be configured by the application, if not explicitly specified, it'll default to 768 */
+#ifndef MBED_CONF_APP_TIMER_THREAD_STACK_SIZE
+#define MBED_CONF_APP_TIMER_THREAD_STACK_SIZE   768
+#endif
+
+#define OS_TIMER_THREAD_STACK_SIZE  MBED_CONF_APP_TIMER_THREAD_STACK_SIZE
+
+/** The idle thread's stack size can be configured by the application, if not explicitly specified, it'll default to 512 */
+#ifndef MBED_CONF_APP_IDLE_THREAD_STACK_SIZE
+#define MBED_CONF_APP_IDLE_THREAD_STACK_SIZE    512
+#endif
+
+#define OS_IDLE_THREAD_STACK_SIZE   MBED_CONF_APP_IDLE_THREAD_STACK_SIZE
+
+#define OS_DYNAMIC_MEM_SIZE         0
+
+#if defined(OS_TICK_FREQ) && (OS_TICK_FREQ != 1000)
+#error "OS Tickrate must be 1000 for system timing"
+#endif
+
+#if !defined(OS_STACK_WATERMARK) && (defined(MBED_STACK_STATS_ENABLED) || defined(MBED_ALL_STATS_ENABLED))
+#define OS_STACK_WATERMARK          1
+#endif
+
+#if !defined(OS_STACK_WATERMARK) && defined(MBED_THREAD_STATS_ENABLED)
+#define OS_STACK_WATERMARK          1
+#endif
+
+
+#define OS_IDLE_THREAD_TZ_MOD_ID     1
+#define OS_TIMER_THREAD_TZ_MOD_ID    1
+
+
+// Don't adopt default multi-thread support for ARM/ARMC6 toolchains from RTX code base.
+// Provide Mbed-specific instead.
+#define RTX_NO_MULTITHREAD_CLIB
+// LIBSPACE default value set for ARMCC
+#define OS_THREAD_LIBSPACE_NUM      4
+
+#define OS_IDLE_THREAD_NAME         "idle_thread"
+#define OS_TIMER_THREAD_NAME        "timer_thread"
+
+/* Enable only the evr events we use in Mbed-OS to save flash space. */
+//Following events are used by Mbed-OS, DO NOT disable them
+//#define EVR_RTX_KERNEL_ERROR_DISABLE
+//#define EVR_RTX_THREAD_ERROR_DISABLE
+//#define EVR_RTX_THREAD_EXIT_DISABLE
+//#define EVR_RTX_THREAD_TERMINATE_DISABLE
+//#define EVR_RTX_TIMER_ERROR_DISABLE
+//#define EVR_RTX_EVENT_FLAGS_ERROR_DISABLE
+//#define EVR_RTX_MUTEX_ERROR_DISABLE
+//#define EVR_RTX_SEMAPHORE_ERROR_DISABLE
+//#define EVR_RTX_MEMORY_POOL_ERROR_DISABLE
+//#define EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE
+
+//Following events are NOT used by Mbed-OS, you may enable them if needed for debug purposes
+#define EVR_RTX_MEMORY_INIT_DISABLE
+#define EVR_RTX_MEMORY_ALLOC_DISABLE
+#define EVR_RTX_MEMORY_FREE_DISABLE
+#define EVR_RTX_MEMORY_BLOCK_INIT_DISABLE
+#define EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE
+#define EVR_RTX_MEMORY_BLOCK_FREE_DISABLE
+#define EVR_RTX_KERNEL_INITIALIZE_DISABLE
+#define EVR_RTX_KERNEL_INITIALIZED_DISABLE
+#define EVR_RTX_KERNEL_GET_INFO_DISABLE
+#define EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE
+#define EVR_RTX_KERNEL_GET_STATE_DISABLE
+#define EVR_RTX_KERNEL_START_DISABLE
+#define EVR_RTX_KERNEL_STARTED_DISABLE
+#define EVR_RTX_KERNEL_LOCK_DISABLE
+#define EVR_RTX_KERNEL_LOCKED_DISABLE
+#define EVR_RTX_KERNEL_UNLOCK_DISABLE
+#define EVR_RTX_KERNEL_UNLOCKED_DISABLE
+#define EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE
+#define EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE
+#define EVR_RTX_KERNEL_SUSPEND_DISABLE
+#define EVR_RTX_KERNEL_SUSPENDED_DISABLE
+#define EVR_RTX_KERNEL_RESUME_DISABLE
+#define EVR_RTX_KERNEL_RESUMED_DISABLE
+#define EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE
+#define EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE
+#define EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE
+#define EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE
+#define EVR_RTX_THREAD_NEW_DISABLE
+#define EVR_RTX_THREAD_CREATED_DISABLE
+#define EVR_RTX_THREAD_GET_NAME_DISABLE
+#define EVR_RTX_THREAD_GET_ID_DISABLE
+#define EVR_RTX_THREAD_GET_STATE_DISABLE
+#define EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE
+#define EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE
+#define EVR_RTX_THREAD_SET_PRIORITY_DISABLE
+#define EVR_RTX_THREAD_GET_PRIORITY_DISABLE
+#define EVR_RTX_THREAD_YIELD_DISABLE
+#define EVR_RTX_THREAD_SUSPEND_DISABLE
+#define EVR_RTX_THREAD_SUSPENDED_DISABLE
+#define EVR_RTX_THREAD_RESUME_DISABLE
+#define EVR_RTX_THREAD_RESUMED_DISABLE
+#define EVR_RTX_THREAD_DETACH_DISABLE
+#define EVR_RTX_THREAD_DETACHED_DISABLE
+#define EVR_RTX_THREAD_JOIN_DISABLE
+#define EVR_RTX_THREAD_JOIN_PENDING_DISABLE
+#define EVR_RTX_THREAD_JOINED_DISABLE
+#define EVR_RTX_THREAD_BLOCKED_DISABLE
+#define EVR_RTX_THREAD_UNBLOCKED_DISABLE
+#define EVR_RTX_THREAD_PREEMPTED_DISABLE
+#define EVR_RTX_THREAD_SWITCHED_DISABLE
+#define EVR_RTX_THREAD_DESTROYED_DISABLE
+#define EVR_RTX_THREAD_GET_COUNT_DISABLE
+#define EVR_RTX_THREAD_ENUMERATE_DISABLE
+#define EVR_RTX_THREAD_FLAGS_SET_DISABLE
+#define EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE
+#define EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE
+#define EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE
+#define EVR_RTX_THREAD_FLAGS_GET_DISABLE
+#define EVR_RTX_THREAD_FLAGS_WAIT_DISABLE
+#define EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE
+#define EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE
+#define EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE
+#define EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE
+#define EVR_RTX_THREAD_DELAY_DISABLE
+#define EVR_RTX_THREAD_DELAY_UNTIL_DISABLE
+#define EVR_RTX_THREAD_DELAY_COMPLETED_DISABLE
+#define EVR_RTX_TIMER_CALLBACK_DISABLE
+#define EVR_RTX_TIMER_NEW_DISABLE
+#define EVR_RTX_TIMER_CREATED_DISABLE
+#define EVR_RTX_TIMER_GET_NAME_DISABLE
+#define EVR_RTX_TIMER_START_DISABLE
+#define EVR_RTX_TIMER_STARTED_DISABLE
+#define EVR_RTX_TIMER_STOP_DISABLE
+#define EVR_RTX_TIMER_STOPPED_DISABLE
+#define EVR_RTX_TIMER_IS_RUNNING_DISABLE
+#define EVR_RTX_TIMER_DELETE_DISABLE
+#define EVR_RTX_TIMER_DESTROYED_DISABLE
+#define EVR_RTX_EVENT_FLAGS_NEW_DISABLE
+#define EVR_RTX_EVENT_FLAGS_CREATED_DISABLE
+#define EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE
+#define EVR_RTX_EVENT_FLAGS_SET_DISABLE
+#define EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE
+#define EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE
+#define EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE
+#define EVR_RTX_EVENT_FLAGS_GET_DISABLE
+#define EVR_RTX_EVENT_FLAGS_WAIT_DISABLE
+#define EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE
+#define EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE
+#define EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE
+#define EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE
+#define EVR_RTX_EVENT_FLAGS_DELETE_DISABLE
+#define EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE
+#define EVR_RTX_MUTEX_NEW_DISABLE
+#define EVR_RTX_MUTEX_CREATED_DISABLE
+#define EVR_RTX_MUTEX_GET_NAME_DISABLE
+#define EVR_RTX_MUTEX_ACQUIRE_DISABLE
+#define EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE
+#define EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE
+#define EVR_RTX_MUTEX_ACQUIRED_DISABLE
+#define EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE
+#define EVR_RTX_MUTEX_RELEASE_DISABLE
+#define EVR_RTX_MUTEX_RELEASED_DISABLE
+#define EVR_RTX_MUTEX_GET_OWNER_DISABLE
+#define EVR_RTX_MUTEX_DELETE_DISABLE
+#define EVR_RTX_MUTEX_DESTROYED_DISABLE
+#define EVR_RTX_SEMAPHORE_NEW_DISABLE
+#define EVR_RTX_SEMAPHORE_CREATED_DISABLE
+#define EVR_RTX_SEMAPHORE_GET_NAME_DISABLE
+#define EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE
+#define EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE
+#define EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE
+#define EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE
+#define EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE
+#define EVR_RTX_SEMAPHORE_RELEASE_DISABLE
+#define EVR_RTX_SEMAPHORE_RELEASED_DISABLE
+#define EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE
+#define EVR_RTX_SEMAPHORE_DELETE_DISABLE
+#define EVR_RTX_SEMAPHORE_DESTROYED_DISABLE
+#define EVR_RTX_MEMORY_POOL_NEW_DISABLE
+#define EVR_RTX_MEMORY_POOL_CREATED_DISABLE
+#define EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE
+#define EVR_RTX_MEMORY_POOL_ALLOC_DISABLE
+#define EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE
+#define EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE
+#define EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE
+#define EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE
+#define EVR_RTX_MEMORY_POOL_FREE_DISABLE
+#define EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE
+#define EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE
+#define EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE
+#define EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE
+#define EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE
+#define EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE
+#define EVR_RTX_MEMORY_POOL_DELETE_DISABLE
+#define EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE
+#define EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE
+
+#endif /* MBED_RTX_CONF_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/tMbedSerial.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/tMbedSerial.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/tMbedSerial.c	(revision 374)
@@ -0,0 +1,222 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id$
+ */
+
+/*
+ *		FIFOå
+èµã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ç¨ ç°¡æSIOãã©ã¤ã
+ */
+
+#include <sil.h>
+#include "tMbedSerial_tecsgen.h"
+#include "serial_api.h"
+
+static void mbed_serial_irq_handler(uint32_t id, SerialIrq event);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+void
+eSIOPort_open(CELLIDX idx)
+{
+	CELLCB	*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+	uint_t	brr;
+
+	if (VAR_initialized) {
+		/*
+		 *  æ¢ã«åæåãã¦ããå ´åã¯ãäºéã«åæåããªãï¼
+		 */
+		return;
+	}
+
+	serial_init(obj, ATTR_tx, ATTR_rx);
+	serial_baud(obj, ATTR_baudRate);
+	serial_format(obj, 8, ParityNone, 1);
+
+	serial_irq_handler(obj, mbed_serial_irq_handler, idx);
+
+	VAR_initialized = true;
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+void
+eSIOPort_close(CELLIDX idx)
+{
+	CELLCB	*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+
+	serial_free(obj);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+bool_t
+eSIOPort_putChar(CELLIDX idx, char c)
+{
+	CELLCB	*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+
+	if (serial_writable(obj)){
+		serial_putc(obj, c);
+		return(true);
+	}
+	return(false);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+int_t
+eSIOPort_getChar(CELLIDX idx)
+{
+	CELLCB	*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+	char	c;
+
+	if (serial_readable(obj)) {
+		if (c = serial_getc(obj)) {
+			return((int_t) c);
+		}
+	}
+	return(-1);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+void
+eSIOPort_enableCBR(CELLIDX idx, uint_t cbrtn)
+{
+	CELLCB		*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+
+	switch (cbrtn) {
+	case SIOSendReady:
+		serial_irq_set(obj, TxIrq, true);
+		break;
+	case SIOReceiveReady:
+		serial_irq_set(obj, RxIrq, true);
+		break;
+	}
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+void
+eSIOPort_disableCBR(CELLIDX idx, uint_t cbrtn)
+{
+	CELLCB		*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+
+	switch (cbrtn) {
+	case SIOSendReady:
+		serial_irq_set(obj, TxIrq, false);
+		break;
+	case SIOReceiveReady:
+		serial_irq_set(obj, RxIrq, false);
+		break;
+	}
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã«å¯¾ããåä¿¡å²è¾¼ã¿å¦ç
+ */
+void
+eiRxISR_main(CELLIDX idx)
+{
+	CELLCB	*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+
+	if (serial_readable(obj)) {
+		/*
+		 *  åä¿¡éç¥ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
+		 */
+		ciSIOCBR_readyReceive();
+	}
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã«å¯¾ããéä¿¡å²è¾¼ã¿å¦ç
+ */
+void
+eiTxISR_main(CELLIDX idx)
+{
+	CELLCB	*p_cellcb = GET_CELLCB(idx);
+	serial_t *obj = &p_cellcb->serial;
+
+	if (serial_writable(obj)) {
+		/*
+		 *  éä¿¡å¯è½ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
+		 */
+		ciSIOCBR_readySend();
+	}
+}
+
+void
+mbed_serial_irq_handler(uint32_t id, SerialIrq event)
+{
+	switch (event) {
+	case TxIrq:
+		eiTxISR_main(id);
+		break;
+	case RxIrq:
+		eiRxISR_main(id);
+		break;
+	}
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/tMbedSerial.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/tMbedSerial.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/tMbedSerial.cdl	(revision 374)
@@ -0,0 +1,88 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ * 
+ *  Copyright (C) 2015 by Ushio Laboratory
+ *              Graduate School of Engineering Science, Osaka Univ., JAPAN
+ *  Copyright (C) 2015,2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id$
+ */
+
+/*
+ *		FIFOå
+èµã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ç¨ ç°¡æSIOãã©
+ *		ã¤ãã®ã³ã³ãã¼ãã³ãè¨è¿°
+ */
+
+/*
+ *  FIFOå
+èµã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ã«é¢ããå®ç¾©ã®ã¤ã³
+ *  ãã¼ã
+ */
+import_C("serial_api.h");
+
+/*
+ *  FIFOå
+èµã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ç¨ ç°¡æSIOãã©ã¤ã
+ *  ã®ã»ã«ã¿ã¤ã
+ */
+celltype tMbedSerial {
+	entry	sSIOPort	eSIOPort;
+	call	siSIOCBR	ciSIOCBR;
+
+	attr {
+		int32_t tx;
+		int32_t rx;
+		uint32_t	baudRate;		/* ãã¼ã¬ã¼ãã®è¨­å®å¤ */
+	};
+	var {
+		bool_t		initialized = false;	/* åæåæ¸ã¿ */
+		serial_t	serial;
+	};
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/PeripheralPins.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/PeripheralPins.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/PeripheralPins.h	(revision 374)
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+typedef struct {
+    PinName pin;
+    int function;
+    int pm;
+} PinFunc;
+
+/************IRQ***************/
+extern const PinMap PinMap_IRQ[];
+
+/************PINMAP***************/
+extern const PinFunc PIPC_0_tbl[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************DAC***************/
+extern const PinMap PinMap_DAC[];
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_CTS[];
+extern const PinMap PinMap_UART_RTS[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+/************PWM***************/
+extern const PinMap PinMap_PWM[];
+
+/************CAN***************/
+extern const PinMap PinMap_CAN_RD[];
+extern const PinMap PinMap_CAN_TD[];
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PeripheralNames.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PeripheralNames.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PeripheralNames.h	(revision 374)
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART0,
+    UART1,
+    UART2,
+    UART3,
+    UART4,
+    UART5,
+    UART6,
+    UART7,
+} UARTName;
+
+typedef enum {
+    PWM_PWM1A  = 0,
+    PWM_PWM1B,
+    PWM_PWM1C,
+    PWM_PWM1D,
+    PWM_PWM1E,
+    PWM_PWM1F,
+    PWM_PWM1G,
+    PWM_PWM1H,
+    PWM_PWM2A,
+    PWM_PWM2B,
+    PWM_PWM2C,
+    PWM_PWM2D,
+    PWM_PWM2E,
+    PWM_PWM2F,
+    PWM_PWM2G,
+    PWM_PWM2H,
+    PWM_TIOC0A = 0x20,
+    PWM_TIOC0C,
+    PWM_TIOC1A,
+    PWM_TIOC2A,
+    PWM_TIOC3A,
+    PWM_TIOC3C,
+    PWM_TIOC4A,
+    PWM_TIOC4C,
+} PWMName;
+
+typedef enum {
+    AN0= 0,
+    AN1= 1,
+    AN2= 2,
+    AN3= 3,
+    AN4= 4,
+    AN5= 5,
+    AN6= 6,
+    AN7= 7,
+} ADCName;
+
+typedef enum {
+    SPI_0 = 0,
+    SPI_1,
+    SPI_2,
+    SPI_3,
+    SPI_4,
+} SPIName;
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1,
+    I2C_2,
+    I2C_3,
+} I2CName;
+
+typedef enum {
+    CAN_0 = 0,
+    CAN_1,
+    CAN_2,
+    CAN_3,
+    CAN_4,
+} CANName;
+
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART2
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PeripheralPins.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PeripheralPins.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PeripheralPins.c	(revision 374)
@@ -0,0 +1,339 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "PeripheralPins.h"
+
+/************IRQ***************/
+enum {
+    IRQ0,IRQ1,
+    IRQ2,IRQ3,
+    IRQ4,IRQ5,
+    IRQ6,IRQ7,
+} IRQNo;
+const PinMap PinMap_IRQ[] = {
+    {P1_0,  IRQ0, 4}, {P1_1,  IRQ1, 4}, {P1_2,  IRQ2, 4},
+    {P1_3,  IRQ3, 4}, {P1_4,  IRQ4, 4}, {P1_5,  IRQ5, 4},
+    {P1_6,  IRQ6, 4}, {P1_7,  IRQ7, 4}, {P1_8,  IRQ2, 3},
+    {P1_9,  IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
+    {P2_0,  IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
+    {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
+    {P3_0,  IRQ2, 3}, {P3_1,  IRQ6, 3}, {P3_3,  IRQ4, 3},
+    {P3_9,  IRQ6, 8}, // 20
+    {P4_8,  IRQ0, 8}, {P4_9,  IRQ1, 8}, {P4_10, IRQ2, 8},
+    {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
+    {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
+    {P5_6,  IRQ6, 6}, {P5_8,  IRQ0, 2}, {P5_9,  IRQ2, 4}, // 31
+    {P6_0,  IRQ5, 6}, {P6_1,  IRQ4, 4}, {P6_2,  IRQ7, 4},
+    {P6_3,  IRQ2, 4}, {P6_4,  IRQ3, 4}, {P6_8,  IRQ0, 8},
+    {P6_9,  IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
+    {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
+    {P6_15, IRQ7, 8}, // 44
+    {P7_8,  IRQ1, 8}, {P7_9,  IRQ0, 8}, {P7_10, IRQ2, 8},
+    {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
+    {P7_14, IRQ6, 8}, // 51
+    {P8_2,  IRQ0, 5}, {P8_3,  IRQ1, 6}, {P8_7,  IRQ5, 4},
+    {P9_1,  IRQ0, 4}, // 55
+    {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
+    {NC,    NC,     0}
+};
+
+/************PINMAP***************/
+const PinFunc PIPC_0_tbl[] = {
+//   pin      func     pm
+    {P4_0   , 2      , -1}, /* TIOC0A */
+    {P5_0   , 6      , -1}, /* TIOC0A */
+    {P7_0   , 7      , -1}, /* TIOC0A */
+    {P10_4  , 2      , -1}, /* TIOC0A */
+    {P4_1   , 2      , -1}, /* TIOC0B */
+    {P5_1   , 6      , -1}, /* TIOC0B */
+    {P7_1   , 7      , -1}, /* TIOC0B */
+    {P10_5  , 2      , -1}, /* TIOC0B */
+    {P4_2   , 2      , -1}, /* TIOC0C */
+    {P5_5   , 6      , -1}, /* TIOC0C */
+    {P7_2   , 7      , -1}, /* TIOC0C */
+    {P10_6  , 2      , -1}, /* TIOC0C */
+    {P4_3   , 2      , -1}, /* TIOC0D */
+    {P5_7   , 6      , -1}, /* TIOC0D */
+    {P7_3   , 7      , -1}, /* TIOC0D */
+    {P10_7  , 2      , -1}, /* TIOC0D */
+    {P2_11  , 5      , -1}, /* TIOC1A */
+    {P6_0   , 5      , -1}, /* TIOC1A */
+    {P7_4   , 7      , -1}, /* TIOC1A */
+    {P8_8   , 5      , -1}, /* TIOC1A */
+    {P9_7   , 4      , -1}, /* TIOC1A */
+    {P10_8  , 2      , -1}, /* TIOC1A */
+    {P2_12  , 8      , -1}, /* TIOC1B */
+    {P5_2   , 6      , -1}, /* TIOC1B */
+    {P6_1   , 5      , -1}, /* TIOC1B */
+    {P7_5   , 7      , -1}, /* TIOC1B */
+    {P8_9   , 5      , -1}, /* TIOC1B */
+    {P10_9  , 2      , -1}, /* TIOC1B */
+    {P2_1   , 6      , -1}, /* TIOC2A */
+    {P6_2   , 6      , -1}, /* TIOC2A */
+    {P7_6   , 7      , -1}, /* TIOC2A */
+    {P8_14  , 4      , -1}, /* TIOC2A */
+    {P10_10 , 2      , -1}, /* TIOC2A */
+    {P2_2   , 6      , -1}, /* TIOC2B */
+    {P6_3   , 6      , -1}, /* TIOC2B */
+    {P7_7   , 7      , -1}, /* TIOC2B */
+    {P8_15  , 4      , -1}, /* TIOC2B */
+    {P10_11 , 2      , -1}, /* TIOC2B */
+    {P10_11 , 2      , -1}, /* TIOC2B */
+    {P3_4   , 6      , -1}, /* TIOC3A */
+    {P7_8   , 7      , -1}, /* TIOC3A */
+    {P8_10  , 4      , -1}, /* TIOC3A */
+    {P3_5   , 6      , -1}, /* TIOC3B */
+    {P7_9   , 7      , -1}, /* TIOC3B */
+    {P8_11  , 4      , -1}, /* TIOC3B */
+    {P3_6   , 6      , -1}, /* TIOC3C */
+    {P5_3   , 6      , -1}, /* TIOC3C */
+    {P7_10  , 7      , -1}, /* TIOC3C */
+    {P8_12  , 4      , -1}, /* TIOC3C */
+    {P3_7   , 6      , -1}, /* TIOC3D */
+    {P5_4   , 6      , -1}, /* TIOC3D */
+    {P7_11  , 7      , -1}, /* TIOC3D */
+    {P8_13  , 4      , -1}, /* TIOC3D */
+    {P3_8   , 6      , -1}, /* TIOC4A */
+    {P4_4   , 3      , -1}, /* TIOC4A */
+    {P7_12  , 7      , -1}, /* TIOC4A */
+    {P11_0  , 2      , -1}, /* TIOC4A */
+    {P3_9   , 6      , -1}, /* TIOC4B */
+    {P4_5   , 3      , -1}, /* TIOC4B */
+    {P7_13  , 7      , -1}, /* TIOC4B */
+    {P11_1  , 2      , -1}, /* TIOC4B */
+    {P3_10  , 6      , -1}, /* TIOC4C */
+    {P4_6   , 3      , -1}, /* TIOC4C */
+    {P7_14  , 7      , -1}, /* TIOC4C */
+    {P11_2  , 2      , -1}, /* TIOC4C */
+    {P3_11  , 6      , -1}, /* TIOC4D */
+    {P4_7   , 3      , -1}, /* TIOC4D */
+    {P7_15  , 7      , -1}, /* TIOC4D */
+    {P11_3  , 2      , -1}, /* TIOC4D */
+    {P5_7   , 1      , 1 }, /* TXOUT0M   */
+    {P5_6   , 1      , 1 }, /* TXOUT0P   */
+    {P5_5   , 1      , 1 }, /* TXOUT1M   */
+    {P5_4   , 1      , 1 }, /* TXOUT1P   */
+    {P5_3   , 1      , 1 }, /* TXOUT2M   */
+    {P5_2   , 1      , 1 }, /* TXOUT2P   */
+    {P5_1   , 1      , 1 }, /* TXCLKOUTM */
+    {P5_0   , 1      , 1 }, /* TXCLKOUTP */
+    {P2_11  , 4      , 0 }, /* SSITxD0 */
+    {P4_7   , 5      , 0 }, /* SSITxD0 */
+    {P7_4   , 6      , 0 }, /* SSITxD1 */
+    {P10_15 , 2      , 0 }, /* SSITxD1 */
+    {P4_15  , 6      , 0 }, /* SSITxD3 */
+    {P7_11  , 2      , 0 }, /* SSITxD3 */
+    {P2_7   , 4      , 0 }, /* SSITxD5 */
+    {P4_11  , 5      , 0 }, /* SSITxD5 */
+    {P8_10  , 8      , 0 }, /* SSITxD5 */
+    {P3_7   , 8      , 0 }, /* WDTOVF */
+    {NC     , 0      , -1}
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P1_8,  AN0, 1},
+    {P1_9,  AN1, 1},
+    {P1_10, AN2, 1},
+    {P1_11, AN3, 1},
+    {P1_12, AN4, 1},
+    {P1_13, AN5, 1},
+    {P1_14, AN6, 1},
+    {P1_15, AN7, 1},
+    {NC   , NC , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P1_1 , I2C_0, 1},
+    {P1_3 , I2C_1, 1},
+    {P1_7 , I2C_3, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P1_0 , I2C_0, 1},
+    {P1_2 , I2C_1, 1},
+    {P1_6 , I2C_3, 1},
+    {NC   , NC   , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P2_14 , UART0, 6},
+    {P2_5  , UART1, 6},
+    {P4_12 , UART1, 7},
+    {P6_3  , UART2, 7},
+    {P4_14 , UART2, 7},
+    {P5_3  , UART3, 5},
+    {P8_8  , UART3, 7},
+    {P5_0  , UART4, 5},
+    {P8_14 , UART4, 7},
+    {P8_13 , UART5, 5},
+    {P11_10, UART5, 3},
+    {P6_6  , UART5, 5},
+    {P5_6  , UART6, 5},
+    {P11_1 , UART6, 4},
+    {P7_4  , UART7, 4},
+    {NC    , NC   , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P2_15 , UART0, 6},
+    {P2_6  , UART1, 6},
+    {P4_13 , UART1, 7},
+    {P6_2  , UART2, 7},
+    {P4_15 , UART2, 7},
+    {P5_4  , UART3, 5},
+    {P8_9  , UART3, 7},
+    {P5_1  , UART4, 5},
+    {P8_15 , UART4, 7},
+    {P8_11 , UART5, 5},
+    {P11_11, UART5, 3},
+    {P6_7  , UART5, 5},
+    {P5_7  , UART6, 5},
+    {P11_2 , UART6, 4},
+    {P7_5  , UART7, 4},
+    {NC    , NC   , 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {P2_3  , UART1, 6},
+    {P11_7 , UART5, 3},
+    {P7_6  , UART7, 4},
+    {NC    , NC   , 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {P2_7  , UART1, 6},
+    {P11_8 , UART5, 3},
+    {P7_7  , UART7, 4},
+    {NC    , NC   , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P10_12, SPI_0, 4},
+    {P4_4  , SPI_1, 2},
+    {P6_4  , SPI_1, 7},
+    {P11_12, SPI_1, 2},
+    {P8_3  , SPI_2, 3},
+    {P5_0  , SPI_3, 8},
+    {NC    , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P10_14, SPI_0, 4},
+    {P4_6  , SPI_1, 2},
+    {P6_6  , SPI_1, 7},
+    {P11_14, SPI_1, 2},
+    {P8_5  , SPI_2, 3},
+    {P5_2  , SPI_3, 8},
+    {NC    , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P10_15, SPI_0, 4},
+    {P4_7  , SPI_1, 2},
+    {P6_7  , SPI_1, 7},
+    {P11_15, SPI_1, 2},
+    {P8_6  , SPI_2, 3},
+    {P5_3  , SPI_3, 8},
+    {NC    , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P10_13, SPI_0, 4},
+    {P4_5  , SPI_1, 2},
+    {P6_5  , SPI_1, 7},
+    {P11_13, SPI_1, 2},
+    {P8_4  , SPI_2, 3},
+    {P5_1  , SPI_3, 8},
+    {NC    , NC   , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {P2_1  , PWM_TIOC2A, 6},
+    {P2_11 , PWM_TIOC1A, 5},
+    {P3_8  , PWM_TIOC4A, 6},
+    {P3_10 , PWM_TIOC4C, 6},
+    {P4_0  , PWM_TIOC0A, 2},
+    {P4_4  , PWM_TIOC4A, 3},
+    {P4_6  , PWM_TIOC4C, 3},
+    {P5_0  , PWM_TIOC0A, 6},
+    {P5_5  , PWM_TIOC0C, 6},
+    {P7_2  , PWM_TIOC0C, 7},
+    {P7_4  , PWM_TIOC1A, 7},
+    {P7_6  , PWM_TIOC2A, 7},
+    {P7_12 , PWM_TIOC4A, 7},
+    {P7_14 , PWM_TIOC4C, 7},
+    {P8_8  , PWM_TIOC1A, 5},
+    {P8_14 , PWM_TIOC2A, 4},
+    {P11_0 , PWM_TIOC4A, 2},
+    {P11_2 , PWM_TIOC4C, 2},
+    {P4_4  , PWM_PWM2E , 4},
+    {P3_2  , PWM_PWM2C , 7},
+    {P4_6  , PWM_PWM2G , 4},
+    {P4_7  , PWM_PWM2H , 4},
+    {P8_14 , PWM_PWM1G , 6},
+    {P8_15 , PWM_PWM1H , 6},
+    {P8_13 , PWM_PWM1F , 6},
+    {P8_11 , PWM_PWM1D , 6},
+    {P8_8  , PWM_PWM1A , 6},
+    {P10_0 , PWM_PWM2A , 3},
+    {P8_12 , PWM_PWM1E , 6},
+    {P8_9  , PWM_PWM1B , 6},
+    {P8_10 , PWM_PWM1C , 6},
+    {P4_5  , PWM_PWM2F , 4},
+    {NC    , NC        , 0}
+};
+
+/************CAN***************/
+const PinMap PinMap_CAN_RD[] = {
+    {P7_8  , CAN_0, 4},
+    {P9_1  , CAN_0, 3},
+    {P1_4  , CAN_1, 3},
+    {P5_9  , CAN_1, 5},
+    {P7_11 , CAN_1, 4},
+    {P11_12, CAN_1, 1},
+    {P4_9  , CAN_2, 6},
+    {P6_4  , CAN_2, 3},
+    {P7_2  , CAN_2, 5},
+    {P2_12 , CAN_3, 5},
+    {P4_2  , CAN_3, 4},
+    {P1_5  , CAN_4, 3},
+    {P2_14 , CAN_4, 5},
+    {NC    , NC   , 0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {P7_9  , CAN_0, 4},
+    {P9_0  , CAN_0, 3},
+    {P5_10 , CAN_1, 5},
+    {P7_10 , CAN_1, 4},
+    {P11_13, CAN_1, 1},
+    {P4_8  , CAN_2, 6},
+    {P6_5  , CAN_2, 3},
+    {P7_3  , CAN_2, 5},
+    {P2_13 , CAN_3, 5},
+    {P4_3  , CAN_3, 4},
+    {P4_11 , CAN_4, 6},
+    {P8_10 , CAN_4, 5},
+    {NC    , NC   , 0}
+};
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PinNames.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PinNames.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PinNames.h	(revision 374)
@@ -0,0 +1,112 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  4
+
+typedef enum {
+    P0_0 = 0,
+          P0_1, P0_2, P0_3, P0_4, P0_5,_P0_6,_P0_7,_P0_8,_P0_9,_P0_10,_P0_11,_P0_12,_P0_13,_P0_14,_P0_15,
+    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, 
+    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, 
+    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, 
+    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, 
+    P5_0, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, 
+    P6_0, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, 
+    P7_0, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15, 
+    P8_0, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15, 
+    P9_0, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, P9_8, P9_9, P9_10, P9_11, P9_12, P9_13, P9_14, P9_15, 
+    P10_0,P10_1,P10_2,P10_3,P10_4,P10_5,P10_6,P10_7,P10_8,P10_9,P10_10,P10_11,P10_12,P10_13,P10_14,P10_15,
+    P11_0,P11_1,P11_2,P11_3,P11_4,P11_5,P11_6,P11_7,P11_8,P11_9,P11_10,P11_11,P11_12,P11_13,P11_14,P11_15, 
+
+    // mbed Pin Names
+    LED1 = P6_13,
+    LED2 = P6_14,
+    LED3 = P6_15,
+    LED4 = P6_12,
+
+    LED_RED  = LED1,
+    LED_GREEN= LED2,
+    LED_BLUE = LED3,
+    LED_USER = LED4,
+
+    USBTX = P6_3,
+    USBRX = P6_2,
+
+    // Arduiono Pin Names
+    D0 = P2_15,
+    D1 = P2_14,
+    D2 = P4_7,
+    D3 = P4_6,
+    D4 = P4_5,
+    D5 = P4_4,
+    D6 = P8_13,
+    D7 = P8_11,
+    D8 = P8_15,
+    D9 = P8_14,
+    D10 = P10_13,
+    D11 = P10_14,
+    D12 = P10_15,
+    D13 = P10_12,
+    D14 = P1_3,
+    D15 = P1_2,
+
+    A0 = P1_8,
+    A1 = P1_9,
+    A2 = P1_10,
+    A3 = P1_11,
+    A4 = P1_13,
+    A5 = P1_15,
+
+    I2C_SCL = D15,
+    I2C_SDA = D14,
+
+    USER_BUTTON0 = P6_0,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON0,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullUp = 0,
+    PullDown = 3,
+    PullNone = 2,
+    OpenDrain = 4,
+    PullDefault = PullDown
+} PinMode;
+
+#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f)
+#define PINNO(pin) ((pin)&0x0f)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PortNames.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PortNames.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PortNames.h	(revision 374)
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1,
+    Port2 = 2,
+    Port3 = 3,
+    Port4 = 4,
+    Port5 = 5,
+    Port6 = 6,
+    Port7 = 7,
+    Port8 = 8,
+    Port9 = 9,
+    Port10 = 10,
+    Port11 = 11
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h	(revision 374)
@@ -0,0 +1,22 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef RESERVED_PINS_H
+#define RESERVED_PINS_H
+
+#define TARGET_RESERVED_PINS {}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device.h	(revision 374)
@@ -0,0 +1,50 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+/* ->Take measures about optimization problems of web compiler */
+   /* Web compiler has problem that inlining code may not be generated correctly */
+   /* when "-O3 -Otime" was specified. */
+#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027)
+#pragma Ospace
+#endif
+/* <-Take measures about optimization problems of web compiler */
+
+
+
+
+
+
+#define TRANSACTION_QUEUE_SIZE_SPI 16
+
+
+
+
+
+#define DEVICE_ID_LENGTH            32
+#define DEVICE_MAC_OFFSET           20
+
+
+
+
+
+#include "objects.h"
+#include "hal/dma_api.h"
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/MBRZA1H.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/MBRZA1H.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/MBRZA1H.h	(revision 374)
@@ -0,0 +1,1 @@
+#include "RZ_A1H.h"
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/RZ_A1_Init.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/RZ_A1_Init.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/RZ_A1_Init.c	(revision 374)
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         RZ_A1_Init.c
+* $Rev: 624 $
+* $Date:: 2013-04-24 13:37:48 +0900#$
+* @brief        RZ_A1 Initialize
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "MBRZA1H.h"
+#include "RZ_A1_Init.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: RZ_A1_SetSramWriteEnable
+* @brief         Initialize Board settings
+*
+*                Description:<br>
+*                Set SRAM write enable
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A1_SetSramWriteEnable(void)
+{
+    /* Enable SRAM write access */
+    CPG.SYSCR3 = 0x0F;
+
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitClock
+* @brief         Initialize Board settings
+*
+*                Description:<br>
+*                Initialize Clock
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A1_InitClock(void)
+{
+    /* Cancel L2C standby status before clock change */
+    L2CREG15_POWER_CTRL = 0x00000001;
+
+    /* Clock settings */
+    /* ClockMode0 */
+    CPG.FRQCR  = 0x1035;    /* CPU Clock =399.99MHz */
+    CPG.FRQCR2 = 0x0001;    /* G Clock   =266.66MHz */
+
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_IsClockMode0
+* @brief         Query Clock Mode
+*
+*                Description:<br>
+*                Answer ClockMode0 or not
+* @param         none
+* @retval        true  : clock mode 0
+* @retval        false : clock mode 1
+******************************************************************************/
+int RZ_A1_IsClockMode0(void)
+{
+    /* ClockMode0 */
+    return true;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitBus
+* @brief         Initialize Bus
+*
+*                Description:<br>
+*                Initialize Pin Setting
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A1_InitBus(void)
+{
+    /*************************************************************************/
+    /* If need Pin Setting before run program, the setting will be wrote here*/
+    /*************************************************************************/
+
+    return;
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld	(revision 374)
@@ -0,0 +1,247 @@
+/* Linker script for mbed RZ_A1H */
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+PROVIDE(IRQTable = _kernel_inh_table);
+PROVIDE(IRQ_NestLevel = _kernel_excpt_nest_count);
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  ROM   (rx)  : ORIGIN = 0x00000000, LENGTH = 0x02000000
+  BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000 
+  SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000 
+  L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000 
+  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000
+  RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .boot :
+    {
+        KEEP(*(.boot_loader)) 
+    } > BOOT_LOADER 
+
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+
+        KEEP(*(.isr_vector))
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+        Image$$VECTORS$$Limit = .;
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > SFLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > SFLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > SFLASH
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__nc_data_start)
+        LONG (__nc_data_end - __nc_data_start)
+        LONG (LOADADDR(.ram_code))
+        LONG (ADDR(.ram_code))
+        LONG (SIZEOF(.ram_code))
+        __copy_table_end__ = .;
+    } > SFLASH
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__nc_bss_start)
+        LONG (__nc_bss_end - __nc_bss_start)
+        __zero_table_end__ = .;
+    } > SFLASH
+
+    .ram_code : ALIGN( 0x4 ) {
+        __ram_code_load  = .;
+        __ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
+
+        *(RAM_CODE)
+
+        *(RAM_CONST)
+
+        . = ALIGN( 0x4 );
+        __ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
+    } > RAM AT > SFLASH
+
+    Load$$SEC_RAM_CODE$$Base    = LOADADDR(.ram_code);
+    Image$$SEC_RAM_CODE$$Base   = ADDR(.ram_code);
+    Load$$SEC_RAM_CODE$$Length  = SIZEOF(.ram_code);
+
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += 0x00004000;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    __etext = Load$$SEC_RAM_CODE$$Base + SIZEOF(.ram_code);
+
+    .data : AT (__etext)
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss ALIGN(0x10):
+    {
+        Image$$RW_IRAM1$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$RW_IRAM1$$Limit = .;
+    } > RAM
+
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    __HeapLimit = __StackLimit;
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+    __etext2 = __etext + SIZEOF(.data);
+    .nc_data : AT (__etext2)
+    {
+        Image$$RW_DATA_NC$$Base = .;
+        __nc_data_start = .;
+        *(NC_DATA)
+
+        . = ALIGN(4);
+        __nc_data_end = .;
+        Image$$RW_DATA_NC$$Limit = .;
+    } > RAM_NC
+
+    .nc_bss (NOLOAD) :
+    {
+        Image$$ZI_DATA_NC$$Base = .;
+        __nc_bss_start = .;
+        *(NC_BSS)
+
+        . = ALIGN(4);
+        __nc_bss_end = .;
+        Image$$ZI_DATA_NC$$Limit = .;
+    } > RAM_NC
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S	(revision 374)
@@ -0,0 +1,253 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with 
+ *   GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ * 
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+    .syntax unified
+    .extern _start
+ 
+@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
+    .equ    Mode_USR        ,   0x10
+    .equ    Mode_FIQ        ,   0x11
+    .equ    Mode_IRQ        ,   0x12
+    .equ    Mode_SVC        ,   0x13
+    .equ    Mode_ABT        ,   0x17
+    .equ    Mode_UND        ,   0x1B
+    .equ    Mode_SYS        ,   0x1F
+
+    .equ    I_Bit           ,   0x80            @ when I bit is set, IRQ is disabled 
+    .equ    F_Bit           ,   0x40            @ when F bit is set, FIQ is disabled 
+    .equ    T_Bit           ,   0x20            @ when T bit is set, core is in Thumb state 
+
+@ Stack Configuration
+
+    .EQU    UND_Stack_Size  , 0x00000100
+    .EQU    SVC_Stack_Size  , 0x00008000
+    .EQU    ABT_Stack_Size  , 0x00000100
+    .EQU    FIQ_Stack_Size  , 0x00000100
+    .EQU    IRQ_Stack_Size  , 0x00008000
+    .EQU    USR_Stack_Size  , 0x00004000
+
+    .EQU    ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
+
+    .section .stack
+    .align 3
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    ISR_Stack_Size
+__initial_sp:
+    .space    USR_Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+
+@ Heap Configuration
+
+    .EQU    Heap_Size       , 0x00080000
+
+    .section .heap
+    .align 3
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+
+
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   0xe59ff018 /* 0x00 */
+    .long   0xe59ff018 /* 0x04 */
+    .long   0xe59ff018 /* 0x08 */
+    .long   0xe59ff018 /* 0x0c */
+    .long   0xe59ff018 /* 0x10 */
+    .long   0xe59ff018 /* 0x14 */
+    .long   0xe59ff018 /* 0x18 */
+    .long   0xe59ff018 /* 0x1c */
+
+    .long   Reset_Handler         /* 0x20 */
+    .long   _kernel_undef_handler  /* 0x24 */
+    .long   _kernel_svc_handler    /* 0x28 */
+    .long   _kernel_pabort_handler /* 0x2c */
+    .long   _kernel_dabort_handler /* 0x30 */
+    .long   0                     /* Reserved */
+    .long   _kernel_irq_handler    /* IRQ */
+    .long   _kernel_fiq_handler    /* FIQ */
+
+
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .align 2
+    .globl          Reset_Handler
+    .type          Reset_Handler, %function
+Reset_Handler:
+    @ Mask interrupts
+    CPSID   if                           
+
+    @ Put any cores other than 0 to sleep
+    mrc     p15, 0, r0, c0, c0, 5   @ Read MPIDR
+    ands    r0, r0, #3
+goToSleep:
+    wfine
+    bne     goToSleep
+
+    @ Reset SCTLR Settings
+    mrc     p15, 0, r0, c1, c0, 0       @ Read CP15 System Control register 
+    bic     r0, r0, #(0x1 << 12)        @ Clear I bit 12 to disable I Cache 
+    bic     r0, r0, #(0x1 <<  2)        @ Clear C bit  2 to disable D Cache 
+    bic     r0, r0, #0x1                @ Clear M bit  0 to disable MMU 
+    bic     r0, r0, #(0x1 << 11)        @ Clear Z bit 11 to disable branch prediction 
+    bic     r0, r0, #(0x1 << 13)        @ Clear V bit 13 to disable hivecs 
+    mcr     p15, 0, r0, c1, c0, 0       @ Write value back to CP15 System Control register 
+    isb
+
+    @ Configure ACTLR
+    MRC     p15, 0, r0, c1, c0, 1       @ Read CP15 Auxiliary Control Register
+    ORR     r0, r0, #(1 <<  1)          @ Enable L2 prefetch hint (UNK/WI since r4p1)
+    MCR     p15, 0, r0, c1, c0, 1       @ Write CP15 Auxiliary Control Register
+
+@ Set Vector Base Address Register (VBAR) to point to this application's vector table
+    ldr     r0, =__isr_vector
+    mcr     p15, 0, r0, c12, c0, 0
+ 
+@ Setup Stack for each exceptional mode 
+/*    ldr     r0, =__StackTop  */
+    ldr     r0, =(__StackTop - USR_Stack_Size)
+
+@ Enter Undefined Instruction Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_UND | I_Bit | F_Bit)
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+@ Enter Abort Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
+    mov     sp, r0 
+    sub     r0, r0, #ABT_Stack_Size
+
+@ Enter FIQ Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
+    mov     sp, r0 
+    sub     r0, r0, #FIQ_Stack_Size
+
+@ Enter IRQ Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
+    mov     sp, r0 
+    sub     r0, r0, #IRQ_Stack_Size
+
+@ Enter Supervisor Mode and set its Stack Pointer 
+    msr     cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
+    mov     sp, r0 
+    sub     r0, r0, #SVC_Stack_Size
+
+@ Enter System Mode to complete initialization and enter kernel 
+    msr     cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
+    mov     sp, r0 
+
+@  USR/SYS stack pointer will be set during kernel init
+    ldr     r0, =SystemInit
+    blx     r0
+
+    @ Unmask interrupts
+    CPSIE  if
+
+@ data sections copy
+    ldr     r4, =__copy_table_start__
+    ldr     r5, =__copy_table_end__
+
+.L_loop0:
+    cmp     r4, r5
+    bge     .L_loop0_done
+    ldr     r1, [r4]
+    ldr     r2, [r4, #4]
+    ldr     r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    ittt    ge
+    ldrge   r0, [r1, r3]
+    strge   r0, [r2, r3]
+    bge     .L_loop0_0
+
+    adds    r4, #12
+    b       .L_loop0
+
+.L_loop0_done:
+
+@ bss sections clear
+    ldr     r3, =__zero_table_start__
+    ldr     r4, =__zero_table_end__
+
+.L_loop2:
+    cmp     r3, r4
+    bge     .L_loop2_done
+    ldr     r1, [r3]
+    ldr     r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    itt     ge
+    strge   r0, [r1, r2]
+    bge     .L_loop2_0
+
+    adds    r3, #8
+    b       .L_loop2
+.L_loop2_done:
+
+
+    ldr     r0, =_start
+    bx      r0
+
+    ldr     r0, sf_boot     @ dummy to keep boot loader area
+loop_here:
+    b       loop_here
+
+sf_boot: 
+    .word   boot_loader
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+
+    .text
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+                .macro    def_default_handler    handler_name
+                .align 1
+                .thumb_func
+                .weak    \handler_name
+                .type    \handler_name, %function
+\handler_name :
+                b    .
+                .size    \handler_name, . - \handler_name
+                .endm
+
+                def_default_handler    Undef_Handler
+                def_default_handler    SVC_Handler
+                def_default_handler    PAbt_Handler
+                def_default_handler    DAbt_Handler
+                def_default_handler    IRQ_Handler
+                def_default_handler    FIQ_Handler
+
+                .END
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/cmsis.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/cmsis.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/cmsis.h	(revision 374)
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC1768 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MBRZA1H.h"
+#include "cmsis_nvic.h"
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h	(revision 374)
@@ -0,0 +1,922 @@
+/******************************************************************************
+ * @file     RZ_A1H.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File 
+ * @version  V1.00
+ * @data     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __RZ_A1H_H__
+#define __RZ_A1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/******  SGI Interrupts Numbers                 ****************************************/
+  SGI0_IRQn            =  0,
+  SGI1_IRQn            =  1,
+  SGI2_IRQn            =  2,
+  SGI3_IRQn            =  3,
+  SGI4_IRQn            =  4,
+  SGI5_IRQn            =  5,
+  SGI6_IRQn            =  6,
+  SGI7_IRQn            =  7,
+  SGI8_IRQn            =  8,
+  SGI9_IRQn            =  9,
+  SGI10_IRQn           = 10,
+  SGI11_IRQn           = 11,
+  SGI12_IRQn           = 12,
+  SGI13_IRQn           = 13,
+  SGI14_IRQn           = 14,
+  SGI15_IRQn           = 15,
+
+/******  Cortex-A9 Processor Exceptions Numbers ****************************************/
+  /* 16 - 578 */
+  PMUIRQ0_IRQn         = 16,
+  COMMRX0_IRQn         = 17,
+  COMMTX0_IRQn         = 18,
+  CTIIRQ0_IRQn         = 19,
+
+  IRQ0_IRQn            = 32,
+  IRQ1_IRQn            = 33,
+  IRQ2_IRQn            = 34,
+  IRQ3_IRQn            = 35,
+  IRQ4_IRQn            = 36,
+  IRQ5_IRQn            = 37,
+  IRQ6_IRQn            = 38,
+  IRQ7_IRQn            = 39,
+
+  PL310ERR_IRQn        = 40,
+
+  DMAINT0_IRQn         = 41,        /*!< DMAC Interrupt         */
+  DMAINT1_IRQn         = 42,        /*!< DMAC Interrupt         */
+  DMAINT2_IRQn         = 43,        /*!< DMAC Interrupt         */
+  DMAINT3_IRQn         = 44,        /*!< DMAC Interrupt         */
+  DMAINT4_IRQn         = 45,        /*!< DMAC Interrupt         */
+  DMAINT5_IRQn         = 46,        /*!< DMAC Interrupt         */
+  DMAINT6_IRQn         = 47,        /*!< DMAC Interrupt         */
+  DMAINT7_IRQn         = 48,        /*!< DMAC Interrupt         */
+  DMAINT8_IRQn         = 49,        /*!< DMAC Interrupt         */
+  DMAINT9_IRQn         = 50,        /*!< DMAC Interrupt         */
+  DMAINT10_IRQn        = 51,        /*!< DMAC Interrupt         */
+  DMAINT11_IRQn        = 52,        /*!< DMAC Interrupt         */
+  DMAINT12_IRQn        = 53,        /*!< DMAC Interrupt         */
+  DMAINT13_IRQn        = 54,        /*!< DMAC Interrupt         */
+  DMAINT14_IRQn        = 55,        /*!< DMAC Interrupt         */
+  DMAINT15_IRQn        = 56,        /*!< DMAC Interrupt         */
+  DMAERR_IRQn          = 57,        /*!< DMAC Interrupt         */
+
+  /* 58-72 Reserved */
+
+  USBI0_IRQn           = 73,
+  USBI1_IRQn           = 74,
+
+  S0_VI_VSYNC0_IRQn    = 75,
+  S0_LO_VSYNC0_IRQn    = 76,
+  S0_VSYNCERR0_IRQn    = 77,
+  GR3_VLINE0_IRQn      = 78,
+  S0_VFIELD0_IRQn      = 79,
+  IV1_VBUFERR0_IRQn    = 80,
+  IV3_VBUFERR0_IRQn    = 81,
+  IV5_VBUFERR0_IRQn    = 82,
+  IV6_VBUFERR0_IRQn    = 83,
+  S0_WLINE0_IRQn       = 84,
+  S1_VI_VSYNC0_IRQn    = 85,
+  S1_LO_VSYNC0_IRQn    = 86,
+  S1_VSYNCERR0_IRQn    = 87,
+  S1_VFIELD0_IRQn      = 88,
+  IV2_VBUFERR0_IRQn    = 89,
+  IV4_VBUFERR0_IRQn    = 90,
+  S1_WLINE0_IRQn       = 91,
+  OIR_VI_VSYNC0_IRQn   = 92,
+  OIR_LO_VSYNC0_IRQn   = 93,
+  OIR_VSYNCERR0_IRQn   = 94,
+  OIR_VFIELD0_IRQn     = 95,
+  IV7_VBUFERR0_IRQn    = 96,
+  IV8_VBUFERR0_IRQn    = 97,
+  /* 98 Reserved */
+  S0_VI_VSYNC1_IRQn    = 99,
+  S0_LO_VSYNC1_IRQn    = 100,
+  S0_VSYNCERR1_IRQn    = 101,
+  GR3_VLINE1_IRQn      = 102,
+  S0_VFIELD1_IRQn      = 103,
+  IV1_VBUFERR1_IRQn    = 104,
+  IV3_VBUFERR1_IRQn    = 105,
+  IV5_VBUFERR1_IRQn    = 106,
+  IV6_VBUFERR1_IRQn    = 107,
+  S0_WLINE1_IRQn       = 108,
+  S1_VI_VSYNC1_IRQn    = 109,
+  S1_LO_VSYNC1_IRQn    = 110,
+  S1_VSYNCERR1_IRQn    = 111,
+  S1_VFIELD1_IRQn      = 112,
+  IV2_VBUFERR1_IRQn    = 113,
+  IV4_VBUFERR1_IRQn    = 114,
+  S1_WLINE1_IRQn       = 115,
+  OIR_VI_VSYNC1_IRQn   = 116,
+  OIR_LO_VSYNC1_IRQn   = 117,
+  OIR_VSYNCERR1_IRQn   = 118,
+  OIR_VFIELD1_IRQn     = 119,
+  IV7_VBUFERR1_IRQn    = 120,
+  IV8_VBUFERR1_IRQn    = 121,
+  /* Reserved = 122 */
+
+  IMRDI_IRQn           = 123,
+  IMR2I0_IRQn          = 124,
+  IMR2I1_IRQn          = 125,
+
+  JEDI_IRQn            = 126,
+  JDTI_IRQn            = 127,
+
+  CMP0_IRQn            = 128,
+  CMP1_IRQn            = 129,
+
+  INT0_IRQn            = 130,
+  INT1_IRQn            = 131,
+  INT2_IRQn            = 132,
+  INT3_IRQn            = 133,
+
+  OSTMI0TINT_IRQn      = 134,       /*!< OSTM Interrupt         */
+  OSTMI1TINT_IRQn      = 135,       /*!< OSTM Interrupt         */
+
+  CMI_IRQn             = 136,
+  WTOUT_IRQn           = 137,
+
+  ITI_IRQn             = 138,
+
+  TGI0A_IRQn           = 139,
+  TGI0B_IRQn           = 140,
+  TGI0C_IRQn           = 141,
+  TGI0D_IRQn           = 142,
+  TGI0V_IRQn           = 143,
+  TGI0E_IRQn           = 144,
+  TGI0F_IRQn           = 145,
+  TGI1A_IRQn           = 146,
+  TGI1B_IRQn           = 147,
+  TGI1V_IRQn           = 148,
+  TGI1U_IRQn           = 149,
+  TGI2A_IRQn           = 150,
+  TGI2B_IRQn           = 151,
+  TGI2V_IRQn           = 152,
+  TGI2U_IRQn           = 153,
+  TGI3A_IRQn           = 154,
+  TGI3B_IRQn           = 155,
+  TGI3C_IRQn           = 156,
+  TGI3D_IRQn           = 157,
+  TGI3V_IRQn           = 158,
+  TGI4A_IRQn           = 159,
+  TGI4B_IRQn           = 160,
+  TGI4C_IRQn           = 161,
+  TGI4D_IRQn           = 162,
+  TGI4V_IRQn           = 163,
+
+  CMI1_IRQn            = 164,
+  CMI2_IRQn            = 165,
+
+  SGDEI0_IRQn          = 166,
+  SGDEI1_IRQn          = 167,
+  SGDEI2_IRQn          = 168,
+  SGDEI3_IRQn          = 169,
+
+  ADI_IRQn             = 170,
+  LMTI_IRQn            = 171,
+
+  SSII0_IRQn           = 172,       /*!< SSIF Interrupt         */
+  SSIRXI0_IRQn         = 173,       /*!< SSIF Interrupt         */
+  SSITXI0_IRQn         = 174,       /*!< SSIF Interrupt         */
+  SSII1_IRQn           = 175,       /*!< SSIF Interrupt         */
+  SSIRXI1_IRQn         = 176,       /*!< SSIF Interrupt         */
+  SSITXI1_IRQn         = 177,       /*!< SSIF Interrupt         */
+  SSII2_IRQn           = 178,       /*!< SSIF Interrupt         */
+  SSIRTI2_IRQn         = 179,       /*!< SSIF Interrupt         */
+  SSII3_IRQn           = 180,       /*!< SSIF Interrupt         */
+  SSIRXI3_IRQn         = 181,       /*!< SSIF Interrupt         */
+  SSITXI3_IRQn         = 182,       /*!< SSIF Interrupt         */
+  SSII4_IRQn           = 183,       /*!< SSIF Interrupt         */
+  SSIRTI4_IRQn         = 184,       /*!< SSIF Interrupt         */
+  SSII5_IRQn           = 185,       /*!< SSIF Interrupt         */
+  SSIRXI5_IRQn         = 186,       /*!< SSIF Interrupt         */
+  SSITXI5_IRQn         = 187,       /*!< SSIF Interrupt         */
+
+  SPDIFI_IRQn          = 188,
+
+  INTIICTEI0_IRQn      = 189,       /*!< RIIC Interrupt         */
+  INTIICRI0_IRQn       = 190,       /*!< RIIC Interrupt         */
+  INTIICTI0_IRQn       = 191,       /*!< RIIC Interrupt         */
+  INTIICSPI0_IRQn      = 192,       /*!< RIIC Interrupt         */
+  INTIICSTI0_IRQn      = 193,       /*!< RIIC Interrupt         */
+  INTIICNAKI0_IRQn     = 194,       /*!< RIIC Interrupt         */
+  INTIICALI0_IRQn      = 195,       /*!< RIIC Interrupt         */
+  INTIICTMOI0_IRQn     = 196,       /*!< RIIC Interrupt         */
+  INTIICTEI1_IRQn      = 197,       /*!< RIIC Interrupt         */
+  INTIICRI1_IRQn       = 198,       /*!< RIIC Interrupt         */
+  INTIICTI1_IRQn       = 199,       /*!< RIIC Interrupt         */
+  INTIICSPI1_IRQn      = 200,       /*!< RIIC Interrupt         */
+  INTIICSTI1_IRQn      = 201,       /*!< RIIC Interrupt         */
+  INTIICNAKI1_IRQn     = 202,       /*!< RIIC Interrupt         */
+  INTIICALI1_IRQn      = 203,       /*!< RIIC Interrupt         */
+  INTIICTMOI1_IRQn     = 204,       /*!< RIIC Interrupt         */
+  INTIICTEI2_IRQn      = 205,       /*!< RIIC Interrupt         */
+  INTIICRI2_IRQn       = 206,       /*!< RIIC Interrupt         */
+  INTIICTI2_IRQn       = 207,       /*!< RIIC Interrupt         */
+  INTIICSPI2_IRQn      = 208,       /*!< RIIC Interrupt         */
+  INTIICSTI2_IRQn      = 209,       /*!< RIIC Interrupt         */
+  INTIICNAKI2_IRQn     = 210,       /*!< RIIC Interrupt         */
+  INTIICALI2_IRQn      = 211,       /*!< RIIC Interrupt         */
+  INTIICTMOI2_IRQn     = 212,       /*!< RIIC Interrupt         */
+  INTIICTEI3_IRQn      = 213,       /*!< RIIC Interrupt         */
+  INTIICRI3_IRQn       = 214,       /*!< RIIC Interrupt         */
+  INTIICTI3_IRQn       = 215,       /*!< RIIC Interrupt         */
+  INTIICSPI3_IRQn      = 216,       /*!< RIIC Interrupt         */
+  INTIICSTI3_IRQn      = 217,       /*!< RIIC Interrupt         */
+  INTIICNAKI3_IRQn     = 218,       /*!< RIIC Interrupt         */
+  INTIICALI3_IRQn      = 219,       /*!< RIIC Interrupt         */
+  INTIICTMOI3_IRQn     = 220,       /*!< RIIC Interrupt         */
+
+  SCIFBRI0_IRQn        = 221,       /*!< SCIF Interrupt         */
+  SCIFERI0_IRQn        = 222,       /*!< SCIF Interrupt         */
+  SCIFRXI0_IRQn        = 223,       /*!< SCIF Interrupt         */
+  SCIFTXI0_IRQn        = 224,       /*!< SCIF Interrupt         */
+  SCIFBRI1_IRQn        = 225,       /*!< SCIF Interrupt         */
+  SCIFERI1_IRQn        = 226,       /*!< SCIF Interrupt         */
+  SCIFRXI1_IRQn        = 227,       /*!< SCIF Interrupt         */
+  SCIFTXI1_IRQn        = 228,       /*!< SCIF Interrupt         */
+  SCIFBRI2_IRQn        = 229,       /*!< SCIF Interrupt         */
+  SCIFERI2_IRQn        = 230,       /*!< SCIF Interrupt         */
+  SCIFRXI2_IRQn        = 231,       /*!< SCIF Interrupt         */
+  SCIFTXI2_IRQn        = 232,       /*!< SCIF Interrupt         */
+  SCIFBRI3_IRQn        = 233,       /*!< SCIF Interrupt         */
+  SCIFERI3_IRQn        = 234,       /*!< SCIF Interrupt         */
+  SCIFRXI3_IRQn        = 235,       /*!< SCIF Interrupt         */
+  SCIFTXI3_IRQn        = 236,       /*!< SCIF Interrupt         */
+  SCIFBRI4_IRQn        = 237,       /*!< SCIF Interrupt         */
+  SCIFERI4_IRQn        = 238,       /*!< SCIF Interrupt         */
+  SCIFRXI4_IRQn        = 239,       /*!< SCIF Interrupt         */
+  SCIFTXI4_IRQn        = 240,       /*!< SCIF Interrupt         */
+  SCIFBRI5_IRQn        = 241,       /*!< SCIF Interrupt         */
+  SCIFERI5_IRQn        = 242,       /*!< SCIF Interrupt         */
+  SCIFRXI5_IRQn        = 243,       /*!< SCIF Interrupt         */
+  SCIFTXI5_IRQn        = 244,       /*!< SCIF Interrupt         */
+  SCIFBRI6_IRQn        = 245,       /*!< SCIF Interrupt         */
+  SCIFERI6_IRQn        = 246,       /*!< SCIF Interrupt         */
+  SCIFRXI6_IRQn        = 247,       /*!< SCIF Interrupt         */
+  SCIFTXI6_IRQn        = 248,       /*!< SCIF Interrupt         */
+  SCIFBRI7_IRQn        = 249,       /*!< SCIF Interrupt         */
+  SCIFERI7_IRQn        = 250,       /*!< SCIF Interrupt         */
+  SCIFRXI7_IRQn        = 251,       /*!< SCIF Interrupt         */
+  SCIFTXI7_IRQn        = 252,       /*!< SCIF Interrupt         */
+
+  INTRCANGERR_IRQn     = 253,
+  INTRCANGRECC_IRQn    = 254,
+  INTRCAN0REC_IRQn     = 255,
+  INTRCAN0ERR_IRQn     = 256,
+  INTRCAN0TRX_IRQn     = 257,
+  INTRCAN1REC_IRQn     = 258,
+  INTRCAN1ERR_IRQn     = 259,
+  INTRCAN1TRX_IRQn     = 260,
+  INTRCAN2REC_IRQn     = 261,
+  INTRCAN2ERR_IRQn     = 262,
+  INTRCAN2TRX_IRQn     = 263,
+  INTRCAN3REC_IRQn     = 264,
+  INTRCAN3ERR_IRQn     = 265,
+  INTRCAN3TRX_IRQn     = 266,
+  INTRCAN4REC_IRQn     = 267,
+  INTRCAN4ERR_IRQn     = 268,
+  INTRCAN4TRX_IRQn     = 269,
+
+  RSPISPEI0_IRQn       = 270,       /*!< RSPI Interrupt         */
+  RSPISPRI0_IRQn       = 271,       /*!< RSPI Interrupt         */
+  RSPISPTI0_IRQn       = 272,       /*!< RSPI Interrupt         */
+  RSPISPEI1_IRQn       = 273,       /*!< RSPI Interrupt         */
+  RSPISPRI1_IRQn       = 274,       /*!< RSPI Interrupt         */
+  RSPISPTI1_IRQn       = 275,       /*!< RSPI Interrupt         */
+  RSPISPEI2_IRQn       = 276,       /*!< RSPI Interrupt         */
+  RSPISPRI2_IRQn       = 277,       /*!< RSPI Interrupt         */
+  RSPISPTI2_IRQn       = 278,       /*!< RSPI Interrupt         */
+  RSPISPEI3_IRQn       = 279,       /*!< RSPI Interrupt         */
+  RSPISPRI3_IRQn       = 280,       /*!< RSPI Interrupt         */
+  RSPISPTI3_IRQn       = 281,       /*!< RSPI Interrupt         */
+  RSPISPEI4_IRQn       = 282,       /*!< RSPI Interrupt         */
+  RSPISPRI4_IRQn       = 283,       /*!< RSPI Interrupt         */
+  RSPISPTI4_IRQn       = 284,       /*!< RSPI Interrupt         */
+
+  IEBBTD_IRQn          = 285,
+  IEBBTERR_IRQn        = 286,
+  IEBBTSTA_IRQn        = 287,
+  IEBBTV_IRQn          = 288,
+
+  ISY_IRQn             = 289,
+  IERR_IRQn            = 290,
+  ITARG_IRQn           = 291,
+  ISEC_IRQn            = 292,
+  IBUF_IRQn            = 293,
+  IREADY_IRQn          = 294,
+
+  STERB_IRQn           = 295,
+  FLTENDI_IRQn         = 296,
+  FLTREQ0I_IRQn        = 297,
+  FLTREQ1I_IRQn        = 298,
+
+  MMC0_IRQn            = 299,
+  MMC1_IRQn            = 300,
+  MMC2_IRQn            = 301,
+
+  SCHI0_3_IRQn         = 302,
+  SDHI0_0_IRQn         = 303,
+  SDHI0_1_IRQn         = 304,
+  SCHI1_3_IRQn         = 305,
+  SDHI1_0_IRQn         = 306,
+  SDHI1_1_IRQn         = 307,
+
+  ARM_IRQn             = 308,
+  PRD_IRQn             = 309,
+  CUP_IRQn             = 310,
+
+  SCUAI0_IRQn          = 311,
+  SCUAI1_IRQn          = 312,
+  SCUFDI0_IRQn         = 313,
+  SCUFDI1_IRQn         = 314,
+  SCUFDI2_IRQn         = 315,
+  SCUFDI3_IRQn         = 316,
+  SCUFUI0_IRQn         = 317,
+  SCUFUI1_IRQn         = 318,
+  SCUFUI2_IRQn         = 319,
+  SCUFUI3_IRQn         = 320,
+  SCUDVI0_IRQn         = 321,
+  SCUDVI1_IRQn         = 322,
+  SCUDVI2_IRQn         = 323,
+  SCUDVI3_IRQn         = 324,
+
+  MLB_CINT_IRQn        = 325,
+  MLB_SINT_IRQn        = 326,
+
+  DRC10_IRQn           = 327,
+  DRC11_IRQn           = 328,
+
+  /* 329-330 Reserved  */
+
+  LINI0_INT_T_IRQn     = 331,
+  LINI0_INT_R_IRQn     = 332,
+  LINI0_INT_S_IRQn     = 333,
+  LINI0_INT_M_IRQn     = 334,
+  LINI1_INT_T_IRQn     = 335,
+  LINI1_INT_R_IRQn     = 336,
+  LINI1_INT_S_IRQn     = 337,
+  LINI1_INT_M_IRQn     = 338,
+
+  /* 339-346 Reserved */
+
+  SCIERI0_IRQn         = 347,
+  SCIRXI0_IRQn         = 348,
+  SCITXI0_IRQn         = 349,
+  SCITEI0_IRQn         = 350,
+  SCIERI1_IRQn         = 351,
+  SCIRXI1_IRQn         = 352,
+  SCITXI1_IRQn         = 353,
+  SCITEI1_IRQn         = 354,
+
+  AVBI_DATA            = 355,
+  AVBI_ERROR           = 356,
+  AVBI_MANAGE          = 357,
+  AVBI_MAC             = 358,
+
+  ETHERI_IRQn          = 359,
+
+  /* 360-363 Reserved */
+
+  CEUI_IRQn            = 364,
+
+  /* 365-380 Reserved */
+
+  H2XMLB_ERRINT_IRQn   = 381,
+  H2XIC1_ERRINT_IRQn   = 382,
+  X2HPERI1_ERRINT_IRQn = 383,
+  X2HPERR2_ERRINT_IRQn = 384,
+  X2HPERR34_ERRINT_IRQn= 385,
+  X2HPERR5_ERRINT_IRQn = 386,
+  X2HPERR67_ERRINT_IRQn= 387,
+  X2HDBGR_ERRINT_IRQn  = 388,
+  X2HBSC_ERRINT_IRQn   = 389,   
+  X2HSPI1_ERRINT_IRQn  = 390,   
+  X2HSPI2_ERRINT_IRQn  = 391,   
+  PRRI_IRQn            = 392,
+
+  IFEI0_IRQn           = 393,
+  OFFI0_IRQn           = 394,
+  PFVEI0_IRQn          = 395,
+  IFEI1_IRQn           = 396,
+  OFFI1_IRQn           = 397,
+  PFVEI1_IRQn          = 398,
+
+  /* 399-415 Reserved */
+
+  TINT0_IRQn           = 416,
+  TINT1_IRQn           = 417,
+  TINT2_IRQn           = 418,
+  TINT3_IRQn           = 419,
+  TINT4_IRQn           = 420,
+  TINT5_IRQn           = 421,
+  TINT6_IRQn           = 422,
+  TINT7_IRQn           = 423,
+  TINT8_IRQn           = 424,
+  TINT9_IRQn           = 425,
+  TINT10_IRQn          = 426,
+  TINT11_IRQn          = 427,
+  TINT12_IRQn          = 428,
+  TINT13_IRQn          = 429,
+  TINT14_IRQn          = 430,
+  TINT15_IRQn          = 431,
+  TINT16_IRQn          = 432,
+  TINT17_IRQn          = 433,
+  TINT18_IRQn          = 434,
+  TINT19_IRQn          = 435,
+  TINT20_IRQn          = 436,
+  TINT21_IRQn          = 437,
+  TINT22_IRQn          = 438,
+  TINT23_IRQn          = 439,
+  TINT24_IRQn          = 440,
+  TINT25_IRQn          = 441,
+  TINT26_IRQn          = 442,
+  TINT27_IRQn          = 443,
+  TINT28_IRQn          = 444,
+  TINT29_IRQn          = 445,
+  TINT30_IRQn          = 446,
+  TINT31_IRQn          = 447,
+  TINT32_IRQn          = 448,
+  TINT33_IRQn          = 449,
+  TINT34_IRQn          = 450,
+  TINT35_IRQn          = 451,
+  TINT36_IRQn          = 452,
+  TINT37_IRQn          = 453,
+  TINT38_IRQn          = 454,
+  TINT39_IRQn          = 455,
+  TINT40_IRQn          = 456,
+  TINT41_IRQn          = 457,
+  TINT42_IRQn          = 458,
+  TINT43_IRQn          = 459,
+  TINT44_IRQn          = 460,
+  TINT45_IRQn          = 461,
+  TINT46_IRQn          = 462,
+  TINT47_IRQn          = 463,
+  TINT48_IRQn          = 464,
+  TINT49_IRQn          = 465,
+  TINT50_IRQn          = 466,
+  TINT51_IRQn          = 467,
+  TINT52_IRQn          = 468,
+  TINT53_IRQn          = 469,
+  TINT54_IRQn          = 470,
+  TINT55_IRQn          = 471,
+  TINT56_IRQn          = 472,
+  TINT57_IRQn          = 473,
+  TINT58_IRQn          = 474,
+  TINT59_IRQn          = 475,
+  TINT60_IRQn          = 476,
+  TINT61_IRQn          = 477,
+  TINT62_IRQn          = 478,
+  TINT63_IRQn          = 479,
+  TINT64_IRQn          = 480,
+  TINT65_IRQn          = 481,
+  TINT66_IRQn          = 482,
+  TINT67_IRQn          = 483,
+  TINT68_IRQn          = 484,
+  TINT69_IRQn          = 485,
+  TINT70_IRQn          = 486,
+  TINT71_IRQn          = 487,
+  TINT72_IRQn          = 488,
+  TINT73_IRQn          = 489,
+  TINT74_IRQn          = 490,
+  TINT75_IRQn          = 491,
+  TINT76_IRQn          = 492,
+  TINT77_IRQn          = 493,
+  TINT78_IRQn          = 494,
+  TINT79_IRQn          = 495,
+  TINT80_IRQn          = 496,
+  TINT81_IRQn          = 497,
+  TINT82_IRQn          = 498,
+  TINT83_IRQn          = 499,
+  TINT84_IRQn          = 500,
+  TINT85_IRQn          = 501,
+  TINT86_IRQn          = 502,
+  TINT87_IRQn          = 503,
+  TINT88_IRQn          = 504,
+  TINT89_IRQn          = 505,
+  TINT90_IRQn          = 506,
+  TINT91_IRQn          = 507,
+  TINT92_IRQn          = 508,
+  TINT93_IRQn          = 509,
+  TINT94_IRQn          = 510,
+  TINT95_IRQn          = 511,
+  TINT96_IRQn          = 512,
+  TINT97_IRQn          = 513,
+  TINT98_IRQn          = 514,
+  TINT99_IRQn          = 515,
+  TINT100_IRQn         = 516,
+  TINT101_IRQn         = 517,
+  TINT102_IRQn         = 518,
+  TINT103_IRQn         = 519,
+  TINT104_IRQn         = 520,
+  TINT105_IRQn         = 521,
+  TINT106_IRQn         = 522,
+  TINT107_IRQn         = 523,
+  TINT108_IRQn         = 524,
+  TINT109_IRQn         = 525,
+  TINT110_IRQn         = 526,
+  TINT111_IRQn         = 527,
+  TINT112_IRQn         = 528,
+  TINT113_IRQn         = 529,
+  TINT114_IRQn         = 530,
+  TINT115_IRQn         = 531,
+  TINT116_IRQn         = 532,
+  TINT117_IRQn         = 533,
+  TINT118_IRQn         = 534,
+  TINT119_IRQn         = 535,
+  TINT120_IRQn         = 536,
+  TINT121_IRQn         = 537,
+  TINT122_IRQn         = 538,
+  TINT123_IRQn         = 539,
+  TINT124_IRQn         = 540,
+  TINT125_IRQn         = 541,
+  TINT126_IRQn         = 542,
+  TINT127_IRQn         = 543,
+  TINT128_IRQn         = 544,
+  TINT129_IRQn         = 545,
+  TINT130_IRQn         = 546,
+  TINT131_IRQn         = 547,
+  TINT132_IRQn         = 548,
+  TINT133_IRQn         = 549,
+  TINT134_IRQn         = 550,
+  TINT135_IRQn         = 551,
+  TINT136_IRQn         = 552,
+  TINT137_IRQn         = 553,
+  TINT138_IRQn         = 554,
+  TINT139_IRQn         = 555,
+  TINT140_IRQn         = 556,
+  TINT141_IRQn         = 557,
+  TINT142_IRQn         = 558,
+  TINT143_IRQn         = 559,
+  TINT144_IRQn         = 560,
+  TINT145_IRQn         = 561,
+  TINT146_IRQn         = 562,
+  TINT147_IRQn         = 563,
+  TINT148_IRQn         = 564,
+  TINT149_IRQn         = 565,
+  TINT150_IRQn         = 566,
+  TINT151_IRQn         = 567,
+  TINT152_IRQn         = 568,
+  TINT153_IRQn         = 569,
+  TINT154_IRQn         = 570,
+  TINT155_IRQn         = 571,
+  TINT156_IRQn         = 572,
+  TINT157_IRQn         = 573,
+  TINT158_IRQn         = 574,
+  TINT159_IRQn         = 575,
+  TINT160_IRQn         = 576,
+  TINT161_IRQn         = 577,
+  TINT162_IRQn         = 578,
+  TINT163_IRQn         = 579,
+  TINT164_IRQn         = 580,
+  TINT165_IRQn         = 581,
+  TINT166_IRQn         = 582,
+  TINT167_IRQn         = 583,
+  TINT168_IRQn         = 584,
+  TINT169_IRQn         = 585,
+  TINT170_IRQn         = 586
+
+} IRQn_Type;
+
+#define RZ_A1_IRQ_MAX  TINT170_IRQn
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+#define RZ_A1_NORFLASH_BASE0               (0x00000000UL)                        /*!< (FLASH0    ) Base Address */
+#define RZ_A1_NORFLASH_BASE1               (0x04000000UL)                        /*!< (FLASH1    ) Base Address */
+#define RZ_A1_SDRAM_BASE0                  (0x08000000UL)                        /*!< (SDRAM0    ) Base Address */
+#define RZ_A1_SDRAM_BASE1                  (0x0C000000UL)                        /*!< (SDRAM1    ) Base Address */
+#define RZ_A1_USER_AREA0                   (0x10000000UL)                        /*!< (USER0     ) Base Address */
+#define RZ_A1_USER_AREA1                   (0x14000000UL)                        /*!< (USER1     ) Base Address */
+#define RZ_A1_SPI_IO0                      (0x18000000UL)                        /*!< (SPI_IO0   ) Base Address */
+#define RZ_A1_SPI_IO1                      (0x1C000000UL)                        /*!< (SPI_IO1   ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_BASE             (0x20000000UL)                        /*!< (SRAM_OC   ) Base Address */
+#define RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
+#define RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
+#define RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
+#define RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
+#define RZ_A1_GIC_DISTRIBUTOR_BASE         (0xe8201000UL)                        /*!< (GIC DIST  ) Base Address */
+#define RZ_A1_GIC_INTERFACE_BASE           (0xe8202000UL)                        /*!< (GIC CPU IF) Base Address */
+#define RZ_A1_PL310_BASE                   (0x3ffff000UL)                        /*!< (PL310     ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_NC_BASE          (0x60000000UL)                        /*!< (SRAM_OC   ) Base Address */
+#define RZ_A1_PRIVATE_TIMER                (0x00000600UL + 0x82000000UL)         /*!< (PTIM      ) Base Address */
+#define GIC_DISTRIBUTOR_BASE               RZ_A1_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE                 RZ_A1_GIC_INTERFACE_BASE
+#define L2C_310_BASE                       RZ_A1_PL310_BASE
+#define TIMER_BASE                         RZ_A1_PRIVATE_TIMER
+
+/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
+#define __CA_REV        0x0000U    /*!< Core revision r0p0                          */
+#define __CORTEX_A           9U    /*!< Cortex-A9 Core                              */
+#if (__FPU_PRESENT != 1)
+#undef __FPU_PRESENT
+#define __FPU_PRESENT        1U    /* FPU present                                   */
+#endif
+#define __GIC_PRESENT        1U    /* GIC present                                   */
+#define __TIM_PRESENT        0U    /* TIM present                                   */
+#define __L2C_PRESENT        1U    /* L2C present                                   */
+
+#include "core_ca.h"
+#include "nvic_wrapper.h"
+#include <system_RZ_A1H.h>
+#include "iodefine.h"
+
+/******************************************************************************/
+/*                         Clock Settings                                     */
+/******************************************************************************/
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ *   GFC[1:0]  =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN  ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO   ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK  (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK  (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK  (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ *   GFC[1:0]  =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN  ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO   ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/******************************************************************************/
+/*                         CPG   Settings                                     */
+/******************************************************************************/
+#define CPG_FRQCR_SHIFT_CKOEN2  (14)
+#define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0  (12)
+#define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC     (8)
+#define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC    (0)
+#define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY     (0x80u)
+#define CPG_STBCR1_BIT_DEEP     (0x40u)
+#define CPG_STBCR2_BIT_HIZ      (0x80u)
+#define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP31   (0x02u) /* A/D converter (analog voltage) */
+#define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67   (0x80u) /* A/D converter (clock) */
+#define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */   
+#define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range compression0 */
+#define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range compression1 */
+#define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ethernet */
+#define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP82   (0x04u) /* EthernetAVB */
+#define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
+#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
+#define CPG_CPUSTS_BIT_ISBUSY   (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
+#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
+#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
+#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
+#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
+#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
+#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
+#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
+#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
+#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
+#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
+#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
+#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
+#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
+#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
+#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
+#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
+#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
+#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
+#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
+#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
+#define CPG_RRAMKP_BIT_RRAMKP3  (0x08u) /* RRAM KP Page3 */
+#define CPG_RRAMKP_BIT_RRAMKP2  (0x04u) /* RRAM KP Page2 */
+#define CPG_RRAMKP_BIT_RRAMKP1  (0x02u) /* RRAM KP Page1 */
+#define CPG_RRAMKP_BIT_RRAMKP0  (0x01u) /* RRAM KP Page0 */
+#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
+#define CPG_DSCTR_BIT_RAMBOOT   (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
+#define CPG_DSSSR_BIT_P6_2      (0x4000u) /* P6_2 */
+#define CPG_DSSSR_BIT_P3_9      (0x2000u) /* P3_9 */
+#define CPG_DSSSR_BIT_P3_1      (0x1000u) /* P3_1 */
+#define CPG_DSSSR_BIT_P2_12     (0x0800u) /* P2_12 */
+#define CPG_DSSSR_BIT_P8_7      (0x0400u) /* P8_7 */
+#define CPG_DSSSR_BIT_P3_3      (0x0200u) /* P3_3 */
+#define CPG_DSSSR_BIT_NMI       (0x0100u) /* NMI */
+#define CPG_DSSSR_BIT_RTCAR     (0x0040u) /* RTCAR */
+#define CPG_DSSSR_BIT_P6_4      (0x0020u) /* P6_4 */
+#define CPG_DSSSR_BIT_P5_9      (0x0010u) /* P5_9 */
+#define CPG_DSSSR_BIT_P7_8      (0x0008u) /* P7_8 */
+#define CPG_DSSSR_BIT_P2_15     (0x0004u) /* P2_15 */
+#define CPG_DSSSR_BIT_P9_1      (0x0002u) /* P9_1 */
+#define CPG_DSSSR_BIT_P8_2      (0x0001u) /* P8_2 */
+#define CPG_DSESR_BIT_P6_2E     (0x4000u) /* P6_2 */
+#define CPG_DSESR_BIT_P3_9E     (0x2000u) /* P3_9 */
+#define CPG_DSESR_BIT_P3_1E     (0x1000u) /* P3_1 */
+#define CPG_DSESR_BIT_P2_12E    (0x0800u) /* P2_12 */
+#define CPG_DSESR_BIT_P8_7E     (0x0400u) /* P8_7 */
+#define CPG_DSESR_BIT_P3_3E     (0x0200u) /* P3_3 */
+#define CPG_DSESR_BIT_NMIE      (0x0100u) /* NMI */
+#define CPG_DSESR_BIT_P6_4E     (0x0020u) /* P6_4 */
+#define CPG_DSESR_BIT_P5_9E     (0x0010u) /* P5_9 */
+#define CPG_DSESR_BIT_P7_8E     (0x0008u) /* P7_8 */
+#define CPG_DSESR_BIT_P2_15E    (0x0004u) /* P2_15 */
+#define CPG_DSESR_BIT_P9_1E     (0x0002u) /* P9_1 */
+#define CPG_DSESR_BIT_P8_2E     (0x0001u) /* P8_2 */
+#define CPG_DSFR_BIT_IOKEEP     (0x8000u) /* Release of Pin State Retention */
+#define CPG_DSFR_BIT_P6_2F      (0x4000u) /* P6_2 */
+#define CPG_DSFR_BIT_P3_9F      (0x2000u) /* P3_9 */
+#define CPG_DSFR_BIT_P3_1F      (0x1000u) /* P3_1 */
+#define CPG_DSFR_BIT_P2_12F     (0x0800u) /* P2_12 */
+#define CPG_DSFR_BIT_P8_7F      (0x0400u) /* P8_7 */
+#define CPG_DSFR_BIT_P3_3F      (0x0200u) /* P3_3 */
+#define CPG_DSFR_BIT_NMIF       (0x0100u) /* NMI */
+#define CPG_DSFR_BIT_RTCARF     (0x0040u) /* RTCAR */
+#define CPG_DSFR_BIT_P6_4F      (0x0020u) /* P6_4 */
+#define CPG_DSFR_BIT_P5_9F      (0x0010u) /* P5_9 */
+#define CPG_DSFR_BIT_P7_8F      (0x0008u) /* P7_8 */
+#define CPG_DSFR_BIT_P2_15F     (0x0004u) /* P2_15 */
+#define CPG_DSFR_BIT_P9_1F      (0x0002u) /* P9_1 */
+#define CPG_DSFR_BIT_P8_2F      (0x0001u) /* P8_2 */
+#define CPG_XTALCTR_BIT_GAIN1   (0x02u)   /* RTC_X3, RTC_X4 */
+#define CPG_XTALCTR_BIT_GAIN0   (0x01u)   /* EXTAL, XTAL */
+
+/******************************************************************************/
+/*                        GPIO   Settings                                     */
+/******************************************************************************/
+#define GPIO_BIT_N0  (1u <<  0)
+#define GPIO_BIT_N1  (1u <<  1)
+#define GPIO_BIT_N2  (1u <<  2)
+#define GPIO_BIT_N3  (1u <<  3)
+#define GPIO_BIT_N4  (1u <<  4)
+#define GPIO_BIT_N5  (1u <<  5)
+#define GPIO_BIT_N6  (1u <<  6)
+#define GPIO_BIT_N7  (1u <<  7)
+#define GPIO_BIT_N8  (1u <<  8)
+#define GPIO_BIT_N9  (1u <<  9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+#define MD_BOOT10_MASK    (0x3)
+
+#define MD_BOOT10_BM0     (0x0)
+#define MD_BOOT10_BM1     (0x2)
+#define MD_BOOT10_BM3     (0x1)
+#define MD_BOOT10_BM4_5   (0x3)
+
+#define MD_CLK        (1u << 2)
+#define MD_CLKS       (1u << 3)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __RZ_A1H_H__
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h	(revision 374)
@@ -0,0 +1,357 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : bsc_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : BSC register define header
+*******************************************************************************/
+#ifndef BSC_IOBITMASK_H
+#define BSC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define BSC_CMNCR_HIZCNT                (0x00000001uL)
+#define BSC_CMNCR_HIZMEM                (0x00000002uL)
+#define BSC_CMNCR_DPRTY                 (0x00000600uL)
+#define BSC_CMNCR_AL0                   (0x01000000uL)
+#define BSC_CMNCR_TL0                   (0x10000000uL)
+
+#define BSC_CS0BCR_BSZ                  (0x00000600uL)
+#define BSC_CS0BCR_TYPE                 (0x00007000uL)
+#define BSC_CS0BCR_IWRRS                (0x00070000uL)
+#define BSC_CS0BCR_IWRRD                (0x00380000uL)
+#define BSC_CS0BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS0BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS0BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS1BCR_BSZ                  (0x00000600uL)
+#define BSC_CS1BCR_TYPE                 (0x00007000uL)
+#define BSC_CS1BCR_IWRRS                (0x00070000uL)
+#define BSC_CS1BCR_IWRRD                (0x00380000uL)
+#define BSC_CS1BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS1BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS1BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS2BCR_BSZ                  (0x00000600uL)
+#define BSC_CS2BCR_TYPE                 (0x00007000uL)
+#define BSC_CS2BCR_IWRRS                (0x00070000uL)
+#define BSC_CS2BCR_IWRRD                (0x00380000uL)
+#define BSC_CS2BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS2BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS2BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS3BCR_BSZ                  (0x00000600uL)
+#define BSC_CS3BCR_TYPE                 (0x00007000uL)
+#define BSC_CS3BCR_IWRRS                (0x00070000uL)
+#define BSC_CS3BCR_IWRRD                (0x00380000uL)
+#define BSC_CS3BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS3BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS3BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS4BCR_BSZ                  (0x00000600uL)
+#define BSC_CS4BCR_TYPE                 (0x00007000uL)
+#define BSC_CS4BCR_IWRRS                (0x00070000uL)
+#define BSC_CS4BCR_IWRRD                (0x00380000uL)
+#define BSC_CS4BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS4BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS4BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS5BCR_BSZ                  (0x00000600uL)
+#define BSC_CS5BCR_TYPE                 (0x00007000uL)
+#define BSC_CS5BCR_IWRRS                (0x00070000uL)
+#define BSC_CS5BCR_IWRRD                (0x00380000uL)
+#define BSC_CS5BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS5BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS5BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS0WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS0WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS0WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS0WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS0WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS1WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS1WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS1WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS1WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS1WCR_NORMAL_WW            (0x00070000uL)
+#define BSC_CS1WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS2WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS2WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS2WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS3WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS3WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS3WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS4WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS4WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS4WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS4WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS4WCR_NORMAL_WW            (0x00070000uL)
+#define BSC_CS4WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS5WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS5WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS5WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS5WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS5WCR_NORMAL_WW            (0x00070000uL)
+#define BSC_CS5WCR_NORMAL_MPXWBAS       (0x00100000uL)
+#define BSC_CS5WCR_NORMAL_SZSEL         (0x00200000uL)
+
+#define BSC_CS0WCR_BROM_ASY_WM          (0x00000040uL)
+#define BSC_CS0WCR_BROM_ASY_W           (0x00000780uL)
+#define BSC_CS0WCR_BROM_ASY_BW          (0x00030000uL)
+#define BSC_CS0WCR_BROM_ASY_BST         (0x00300000uL)
+
+#define BSC_CS4WCR_BROM_ASY_HW          (0x00000003uL)
+#define BSC_CS4WCR_BROM_ASY_WM          (0x00000040uL)
+#define BSC_CS4WCR_BROM_ASY_W           (0x00000780uL)
+#define BSC_CS4WCR_BROM_ASY_SW          (0x00001800uL)
+#define BSC_CS4WCR_BROM_ASY_BW          (0x00030000uL)
+#define BSC_CS4WCR_BROM_ASY_BST         (0x00300000uL)
+
+#define BSC_CS2WCR_SDRAM_A2CL           (0x00000180uL)
+
+#define BSC_CS3WCR_SDRAM_WTRC           (0x00000003uL)
+#define BSC_CS3WCR_SDRAM_TRWL           (0x00000018uL)
+#define BSC_CS3WCR_SDRAM_A3CL           (0x00000180uL)
+#define BSC_CS3WCR_SDRAM_WTRCD          (0x00000C00uL)
+#define BSC_CS3WCR_SDRAM_WTRP           (0x00006000uL)
+
+#define BSC_CS0WCR_BROM_SY_WM           (0x00000040uL)
+#define BSC_CS0WCR_BROM_SY_W            (0x00000780uL)
+#define BSC_CS0WCR_BROM_SY_BW           (0x00030000uL)
+
+#define BSC_SDCR_A3COL                  (0x00000003uL)
+#define BSC_SDCR_A3ROW                  (0x00000018uL)
+#define BSC_SDCR_BACTV                  (0x00000100uL)
+#define BSC_SDCR_PDOWN                  (0x00000200uL)
+#define BSC_SDCR_RMODE                  (0x00000400uL)
+#define BSC_SDCR_RFSH                   (0x00000800uL)
+#define BSC_SDCR_DEEP                   (0x00002000uL)
+#define BSC_SDCR_A2COL                  (0x00030000uL)
+#define BSC_SDCR_A2ROW                  (0x00180000uL)
+
+#define BSC_RTCSR_RRC                   (0x00000007uL)
+#define BSC_RTCSR_CKS                   (0x00000038uL)
+#define BSC_RTCSR_CMIE                  (0x00000040uL)
+#define BSC_RTCSR_CMF                   (0x00000080uL)
+
+#define BSC_RTCNT_D                     (0xFFFFFFFFuL)
+
+#define BSC_RTCOR_D                     (0xFFFFFFFFuL)
+
+#define BSC_TOSCOR0_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR1_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR2_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR3_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR4_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR5_D                   (0x0000FFFFuL)
+
+#define BSC_TOSTR_CS0TOSTF              (0x00000001uL)
+#define BSC_TOSTR_CS1TOSTF              (0x00000002uL)
+#define BSC_TOSTR_CS2TOSTF              (0x00000004uL)
+#define BSC_TOSTR_CS3TOSTF              (0x00000008uL)
+#define BSC_TOSTR_CS4TOSTF              (0x00000010uL)
+#define BSC_TOSTR_CS5TOSTF              (0x00000020uL)
+
+#define BSC_TOENR_CS0TOEN               (0x00000001uL)
+#define BSC_TOENR_CS1TOEN               (0x00000002uL)
+#define BSC_TOENR_CS2TOEN               (0x00000004uL)
+#define BSC_TOENR_CS3TOEN               (0x00000008uL)
+#define BSC_TOENR_CS4TOEN               (0x00000010uL)
+#define BSC_TOENR_CS5TOEN               (0x00000020uL)
+
+
+/* ==== Shift values for IO registers ==== */
+#define BSC_CMNCR_HIZCNT_SHIFT          (0u)
+#define BSC_CMNCR_HIZMEM_SHIFT          (1u)
+#define BSC_CMNCR_DPRTY_SHIFT           (9u)
+#define BSC_CMNCR_AL0_SHIFT             (24u)
+#define BSC_CMNCR_TL0_SHIFT             (28u)
+
+#define BSC_CS0BCR_BSZ_SHIFT            (9u)
+#define BSC_CS0BCR_TYPE_SHIFT           (12u)
+#define BSC_CS0BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS0BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS0BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS0BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS0BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS1BCR_BSZ_SHIFT            (9u)
+#define BSC_CS1BCR_TYPE_SHIFT           (12u)
+#define BSC_CS1BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS1BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS1BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS1BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS1BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS2BCR_BSZ_SHIFT            (9u)
+#define BSC_CS2BCR_TYPE_SHIFT           (12u)
+#define BSC_CS2BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS2BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS2BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS2BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS2BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS3BCR_BSZ_SHIFT            (9u)
+#define BSC_CS3BCR_TYPE_SHIFT           (12u)
+#define BSC_CS3BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS3BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS3BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS3BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS3BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS4BCR_BSZ_SHIFT            (9u)
+#define BSC_CS4BCR_TYPE_SHIFT           (12u)
+#define BSC_CS4BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS4BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS4BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS4BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS4BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS5BCR_BSZ_SHIFT            (9u)
+#define BSC_CS5BCR_TYPE_SHIFT           (12u)
+#define BSC_CS5BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS5BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS5BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS5BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS5BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS0WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS0WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS0WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS0WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS0WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS1WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS1WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS1WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS1WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS1WCR_NORMAL_WW_SHIFT      (16u)
+#define BSC_CS1WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS2WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS2WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS2WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS3WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS3WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS3WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS4WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS4WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS4WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS4WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS4WCR_NORMAL_WW_SHIFT      (16u)
+#define BSC_CS4WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS5WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS5WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS5WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS5WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS5WCR_NORMAL_WW_SHIFT      (16u)
+#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u)
+#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT   (21u)
+
+#define BSC_CS0WCR_BROM_ASY_WM_SHIFT    (6u)
+#define BSC_CS0WCR_BROM_ASY_W_SHIFT     (7u)
+#define BSC_CS0WCR_BROM_ASY_BW_SHIFT    (16u)
+#define BSC_CS0WCR_BROM_ASY_BST_SHIFT   (20u)
+
+#define BSC_CS4WCR_BROM_ASY_HW_SHIFT    (0u)
+#define BSC_CS4WCR_BROM_ASY_WM_SHIFT    (6u)
+#define BSC_CS4WCR_BROM_ASY_W_SHIFT     (7u)
+#define BSC_CS4WCR_BROM_ASY_SW_SHIFT    (11u)
+#define BSC_CS4WCR_BROM_ASY_BW_SHIFT    (16u)
+#define BSC_CS4WCR_BROM_ASY_BST_SHIFT   (20u)
+
+#define BSC_CS2WCR_SDRAM_A2CL_SHIFT     (7u)
+
+#define BSC_CS3WCR_SDRAM_WTRC_SHIFT     (0u)
+#define BSC_CS3WCR_SDRAM_TRWL_SHIFT     (3u)
+#define BSC_CS3WCR_SDRAM_A3CL_SHIFT     (7u)
+#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT    (10u)
+#define BSC_CS3WCR_SDRAM_WTRP_SHIFT     (13u)
+
+#define BSC_CS0WCR_BROM_SY_WM_SHIFT     (6u)
+#define BSC_CS0WCR_BROM_SY_W_SHIFT      (7u)
+#define BSC_CS0WCR_BROM_SY_BW_SHIFT     (16u)
+
+#define BSC_SDCR_A3COL_SHIFT            (0u)
+#define BSC_SDCR_A3ROW_SHIFT            (3u)
+#define BSC_SDCR_BACTV_SHIFT            (8u)
+#define BSC_SDCR_PDOWN_SHIFT            (9u)
+#define BSC_SDCR_RMODE_SHIFT            (10u)
+#define BSC_SDCR_RFSH_SHIFT             (11u)
+#define BSC_SDCR_DEEP_SHIFT             (13u)
+#define BSC_SDCR_A2COL_SHIFT            (16u)
+#define BSC_SDCR_A2ROW_SHIFT            (19u)
+
+#define BSC_RTCSR_RRC_SHIFT             (0u)
+#define BSC_RTCSR_CKS_SHIFT             (3u)
+#define BSC_RTCSR_CMIE_SHIFT            (6u)
+#define BSC_RTCSR_CMF_SHIFT             (7u)
+
+#define BSC_RTCNT_D_SHIFT               (0u)
+
+#define BSC_RTCOR_D_SHIFT               (0u)
+
+#define BSC_TOSCOR0_D_SHIFT             (0u)
+
+#define BSC_TOSCOR1_D_SHIFT             (0u)
+
+#define BSC_TOSCOR2_D_SHIFT             (0u)
+
+#define BSC_TOSCOR3_D_SHIFT             (0u)
+
+#define BSC_TOSCOR4_D_SHIFT             (0u)
+
+#define BSC_TOSCOR5_D_SHIFT             (0u)
+
+#define BSC_TOSTR_CS0TOSTF_SHIFT        (0u)
+#define BSC_TOSTR_CS1TOSTF_SHIFT        (1u)
+#define BSC_TOSTR_CS2TOSTF_SHIFT        (2u)
+#define BSC_TOSTR_CS3TOSTF_SHIFT        (3u)
+#define BSC_TOSTR_CS4TOSTF_SHIFT        (4u)
+#define BSC_TOSTR_CS5TOSTF_SHIFT        (5u)
+
+#define BSC_TOENR_CS0TOEN_SHIFT         (0u)
+#define BSC_TOENR_CS1TOEN_SHIFT         (1u)
+#define BSC_TOENR_CS2TOEN_SHIFT         (2u)
+#define BSC_TOENR_CS3TOEN_SHIFT         (3u)
+#define BSC_TOENR_CS4TOEN_SHIFT         (4u)
+#define BSC_TOENR_CS5TOEN_SHIFT         (5u)
+
+
+#endif /* BSC_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h	(revision 374)
@@ -0,0 +1,461 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : cpg_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : CPG register define header
+*******************************************************************************/
+#ifndef CPG_IOBITMASK_H
+#define CPG_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define CPG_FRQCR_IFC                   (0x0300u)
+#define CPG_FRQCR_CKOEN                 (0x3000u)
+#define CPG_FRQCR_CKOEN2                (0x4000u)
+
+#define CPG_FRQCR2_GFC                  (0x0003u)
+
+#define CPG_CPUSTS_ISBUSY               (0x10u)
+
+#define CPG_STBCR1_DEEP                 (0x40u)
+#define CPG_STBCR1_STBY                 (0x80u)
+
+#define CPG_STBCR2_MSTP20               (0x01u)
+#define CPG_STBCR2_HIZ                  (0x80u)
+
+#define CPG_STBREQ1_STBRQ10             (0x01u)
+#define CPG_STBREQ1_STBRQ12             (0x04u)
+#define CPG_STBREQ1_STBRQ13             (0x08u)
+#define CPG_STBREQ1_STBRQ15             (0x20u)
+
+#define CPG_STBREQ2_STBRQ20             (0x01u)
+#define CPG_STBREQ2_STBRQ21             (0x02u)
+#define CPG_STBREQ2_STBRQ22             (0x04u)
+#define CPG_STBREQ2_STBRQ23             (0x08u)
+#define CPG_STBREQ2_STBRQ24             (0x10u)
+#define CPG_STBREQ2_STBRQ25             (0x20u)
+#define CPG_STBREQ2_STBRQ26             (0x40u)
+#define CPG_STBREQ2_STBRQ27             (0x80u)
+
+#define CPG_STBACK1_STBAK10             (0x01u)
+#define CPG_STBACK1_STBAK12             (0x04u)
+#define CPG_STBACK1_STBAK13             (0x08u)
+#define CPG_STBACK1_STBAK15             (0x20u)
+
+#define CPG_STBACK2_STBAK20             (0x01u)
+#define CPG_STBACK2_STBAK21             (0x02u)
+#define CPG_STBACK2_STBAK22             (0x04u)
+#define CPG_STBACK2_STBAK23             (0x08u)
+#define CPG_STBACK2_STBAK24             (0x10u)
+#define CPG_STBACK2_STBAK25             (0x20u)
+#define CPG_STBACK2_STBAK26             (0x40u)
+#define CPG_STBACK2_STBAK27             (0x80u)
+
+#define CPG_SYSCR1_VRAME0               (0x01u)
+#define CPG_SYSCR1_VRAME1               (0x02u)
+#define CPG_SYSCR1_VRAME2               (0x04u)
+#define CPG_SYSCR1_VRAME3               (0x08u)
+#define CPG_SYSCR1_VRAME4               (0x10u)
+
+#define CPG_SYSCR2_VRAMWE0              (0x01u)
+#define CPG_SYSCR2_VRAMWE1              (0x02u)
+#define CPG_SYSCR2_VRAMWE2              (0x04u)
+#define CPG_SYSCR2_VRAMWE3              (0x08u)
+#define CPG_SYSCR2_VRAMWE4              (0x10u)
+
+#define CPG_SYSCR3_RRAMWE0              (0x01u)
+#define CPG_SYSCR3_RRAMWE1              (0x02u)
+#define CPG_SYSCR3_RRAMWE2              (0x04u)
+#define CPG_SYSCR3_RRAMWE3              (0x08u)
+
+#define CPG_STBCR3_MSTP30               (0x01u)
+#define CPG_STBCR3_MSTP31               (0x02u)
+#define CPG_STBCR3_MSTP32               (0x04u)
+#define CPG_STBCR3_MSTP33               (0x08u)
+#define CPG_STBCR3_MSTP34               (0x10u)
+#define CPG_STBCR3_MSTP35               (0x20u)
+#define CPG_STBCR3_MSTP36               (0x40u)
+#define CPG_STBCR3_MSTP37               (0x80u)
+
+#define CPG_STBCR4_MSTP40               (0x01u)
+#define CPG_STBCR4_MSTP41               (0x02u)
+#define CPG_STBCR4_MSTP42               (0x04u)
+#define CPG_STBCR4_MSTP43               (0x08u)
+#define CPG_STBCR4_MSTP44               (0x10u)
+#define CPG_STBCR4_MSTP45               (0x20u)
+#define CPG_STBCR4_MSTP46               (0x40u)
+#define CPG_STBCR4_MSTP47               (0x80u)
+
+#define CPG_STBCR5_MSTP50               (0x01u)
+#define CPG_STBCR5_MSTP51               (0x02u)
+#define CPG_STBCR5_MSTP52               (0x04u)
+#define CPG_STBCR5_MSTP53               (0x08u)
+#define CPG_STBCR5_MSTP54               (0x10u)
+#define CPG_STBCR5_MSTP55               (0x20u)
+#define CPG_STBCR5_MSTP56               (0x40u)
+#define CPG_STBCR5_MSTP57               (0x80u)
+
+#define CPG_STBCR6_MSTP60               (0x01u)
+#define CPG_STBCR6_MSTP61               (0x02u)
+#define CPG_STBCR6_MSTP62               (0x04u)
+#define CPG_STBCR6_MSTP63               (0x08u)
+#define CPG_STBCR6_MSTP64               (0x10u)
+#define CPG_STBCR6_MSTP65               (0x20u)
+#define CPG_STBCR6_MSTP66               (0x40u)
+#define CPG_STBCR6_MSTP67               (0x80u)
+
+#define CPG_STBCR7_MSTP70               (0x01u)
+#define CPG_STBCR7_MSTP71               (0x02u)
+#define CPG_STBCR7_MSTP73               (0x08u)
+#define CPG_STBCR7_MSTP74               (0x10u)
+#define CPG_STBCR7_MSTP76               (0x40u)
+#define CPG_STBCR7_MSTP77               (0x80u)
+
+#define CPG_STBCR8_MSTP81               (0x02u)
+#define CPG_STBCR8_MSTP82               (0x04u)
+#define CPG_STBCR8_MSTP83               (0x08u)
+#define CPG_STBCR8_MSTP84               (0x10u)
+#define CPG_STBCR8_MSTP85               (0x20u)
+#define CPG_STBCR8_MSTP86               (0x40u)
+#define CPG_STBCR8_MSTP87               (0x80u)
+
+#define CPG_STBCR9_MSTP90               (0x01u)
+#define CPG_STBCR9_MSTP91               (0x02u)
+#define CPG_STBCR9_MSTP92               (0x04u)
+#define CPG_STBCR9_MSTP93               (0x08u)
+#define CPG_STBCR9_MSTP94               (0x10u)
+#define CPG_STBCR9_MSTP95               (0x20u)
+#define CPG_STBCR9_MSTP96               (0x40u)
+#define CPG_STBCR9_MSTP97               (0x80u)
+
+#define CPG_STBCR10_MSTP100             (0x01u)
+#define CPG_STBCR10_MSTP101             (0x02u)
+#define CPG_STBCR10_MSTP102             (0x04u)
+#define CPG_STBCR10_MSTP103             (0x08u)
+#define CPG_STBCR10_MSTP104             (0x10u)
+#define CPG_STBCR10_MSTP105             (0x20u)
+#define CPG_STBCR10_MSTP106             (0x40u)
+#define CPG_STBCR10_MSTP107             (0x80u)
+
+#define CPG_STBCR11_MSTP110             (0x01u)
+#define CPG_STBCR11_MSTP111             (0x02u)
+#define CPG_STBCR11_MSTP112             (0x04u)
+#define CPG_STBCR11_MSTP113             (0x08u)
+#define CPG_STBCR11_MSTP114             (0x10u)
+#define CPG_STBCR11_MSTP115             (0x20u)
+
+#define CPG_STBCR12_MSTP120             (0x01u)
+#define CPG_STBCR12_MSTP121             (0x02u)
+#define CPG_STBCR12_MSTP122             (0x04u)
+#define CPG_STBCR12_MSTP123             (0x08u)
+
+#define CPG_STBCR13_MSTP131             (0x02u)
+#define CPG_STBCR13_MSTP132             (0x04u)
+
+#define CPG_SWRSTCR1_SRST11             (0x02u)
+#define CPG_SWRSTCR1_SRST12             (0x04u)
+#define CPG_SWRSTCR1_SRST13             (0x08u)
+#define CPG_SWRSTCR1_SRST14             (0x10u)
+#define CPG_SWRSTCR1_SRST15             (0x20u)
+#define CPG_SWRSTCR1_SRST16             (0x40u)
+#define CPG_SWRSTCR1_AXTALE             (0x80u)
+
+#define CPG_SWRSTCR2_SRST21             (0x02u)
+
+#define CPG_SWRSTCR3_SRST32             (0x04u)
+
+#define CPG_RRAMKP_RRAMKP0              (0x01u)
+#define CPG_RRAMKP_RRAMKP1              (0x02u)
+#define CPG_RRAMKP_RRAMKP2              (0x04u)
+#define CPG_RRAMKP_RRAMKP3              (0x08u)
+
+#define CPG_DSCTR_RAMBOOT               (0x40u)
+#define CPG_DSCTR_EBUSKEEPE             (0x80u)
+
+#define CPG_DSSSR_P8_2                  (0x0001u)
+#define CPG_DSSSR_P9_1                  (0x0002u)
+#define CPG_DSSSR_P2_15                 (0x0004u)
+#define CPG_DSSSR_P7_8                  (0x0008u)
+#define CPG_DSSSR_P5_9                  (0x0010u)
+#define CPG_DSSSR_P6_4                  (0x0020u)
+#define CPG_DSSSR_RTCAR                 (0x0040u)
+#define CPG_DSSSR_NMI                   (0x0100u)
+#define CPG_DSSSR_P3_3                  (0x0200u)
+#define CPG_DSSSR_P8_7                  (0x0400u)
+#define CPG_DSSSR_P2_12                 (0x0800u)
+#define CPG_DSSSR_P3_1                  (0x1000u)
+#define CPG_DSSSR_P3_9                  (0x2000u)
+#define CPG_DSSSR_P6_2                  (0x4000u)
+
+#define CPG_DSESR_P8_2E                 (0x0001u)
+#define CPG_DSESR_P9_1E                 (0x0002u)
+#define CPG_DSESR_P2_15E                (0x0004u)
+#define CPG_DSESR_P7_8E                 (0x0008u)
+#define CPG_DSESR_P5_9E                 (0x0010u)
+#define CPG_DSESR_P6_4E                 (0x0020u)
+#define CPG_DSESR_NMIE                  (0x0100u)
+#define CPG_DSESR_P3_3E                 (0x0200u)
+#define CPG_DSESR_P8_7E                 (0x0400u)
+#define CPG_DSESR_P2_12E                (0x0800u)
+#define CPG_DSESR_P3_1E                 (0x1000u)
+#define CPG_DSESR_P3_9E                 (0x2000u)
+#define CPG_DSESR_P6_2E                 (0x4000u)
+
+#define CPG_DSFR_P8_2F                  (0x0001u)
+#define CPG_DSFR_P9_1F                  (0x0002u)
+#define CPG_DSFR_P2_15F                 (0x0004u)
+#define CPG_DSFR_P7_8F                  (0x0008u)
+#define CPG_DSFR_P5_9F                  (0x0010u)
+#define CPG_DSFR_P6_4F                  (0x0020u)
+#define CPG_DSFR_RTCARF                 (0x0040u)
+#define CPG_DSFR_NMIF                   (0x0100u)
+#define CPG_DSFR_P3_3F                  (0x0200u)
+#define CPG_DSFR_P8_7F                  (0x0400u)
+#define CPG_DSFR_P2_12F                 (0x0800u)
+#define CPG_DSFR_P3_1F                  (0x1000u)
+#define CPG_DSFR_P3_9F                  (0x2000u)
+#define CPG_DSFR_P6_2F                  (0x4000u)
+#define CPG_DSFR_IOKEEP                 (0x8000u)
+
+#define CPG_XTALCTR_GAIN0               (0x01u)
+#define CPG_XTALCTR_GAIN1               (0x02u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define CPG_FRQCR_IFC_SHIFT             (8u)
+#define CPG_FRQCR_CKOEN_SHIFT           (12u)
+#define CPG_FRQCR_CKOEN2_SHIFT          (14u)
+
+#define CPG_FRQCR2_GFC_SHIFT            (0u)
+
+#define CPG_CPUSTS_ISBUSY_SHIFT         (4u)
+
+#define CPG_STBCR1_DEEP_SHIFT           (6u)
+#define CPG_STBCR1_STBY_SHIFT           (7u)
+
+#define CPG_STBCR2_MSTP20_SHIFT         (0u)
+#define CPG_STBCR2_HIZ_SHIFT            (7u)
+
+#define CPG_STBREQ1_STBRQ10_SHIFT       (0u)
+#define CPG_STBREQ1_STBRQ12_SHIFT       (2u)
+#define CPG_STBREQ1_STBRQ13_SHIFT       (3u)
+#define CPG_STBREQ1_STBRQ15_SHIFT       (5u)
+
+#define CPG_STBREQ2_STBRQ20_SHIFT       (0u)
+#define CPG_STBREQ2_STBRQ21_SHIFT       (1u)
+#define CPG_STBREQ2_STBRQ22_SHIFT       (2u)
+#define CPG_STBREQ2_STBRQ23_SHIFT       (3u)
+#define CPG_STBREQ2_STBRQ24_SHIFT       (4u)
+#define CPG_STBREQ2_STBRQ25_SHIFT       (5u)
+#define CPG_STBREQ2_STBRQ26_SHIFT       (6u)
+#define CPG_STBREQ2_STBRQ27_SHIFT       (7u)
+
+#define CPG_STBACK1_STBAK10_SHIFT       (0u)
+#define CPG_STBACK1_STBAK12_SHIFT       (2u)
+#define CPG_STBACK1_STBAK13_SHIFT       (3u)
+#define CPG_STBACK1_STBAK15_SHIFT       (5u)
+
+#define CPG_STBACK2_STBAK20_SHIFT       (0u)
+#define CPG_STBACK2_STBAK21_SHIFT       (1u)
+#define CPG_STBACK2_STBAK22_SHIFT       (2u)
+#define CPG_STBACK2_STBAK23_SHIFT       (3u)
+#define CPG_STBACK2_STBAK24_SHIFT       (4u)
+#define CPG_STBACK2_STBAK25_SHIFT       (5u)
+#define CPG_STBACK2_STBAK26_SHIFT       (6u)
+#define CPG_STBACK2_STBAK27_SHIFT       (7u)
+
+#define CPG_SYSCR1_VRAME0_SHIFT         (0u)
+#define CPG_SYSCR1_VRAME1_SHIFT         (1u)
+#define CPG_SYSCR1_VRAME2_SHIFT         (2u)
+#define CPG_SYSCR1_VRAME3_SHIFT         (3u)
+#define CPG_SYSCR1_VRAME4_SHIFT         (4u)
+
+#define CPG_SYSCR2_VRAMWE0_SHIFT        (0u)
+#define CPG_SYSCR2_VRAMWE1_SHIFT        (1u)
+#define CPG_SYSCR2_VRAMWE2_SHIFT        (2u)
+#define CPG_SYSCR2_VRAMWE3_SHIFT        (3u)
+#define CPG_SYSCR2_VRAMWE4_SHIFT        (4u)
+
+#define CPG_SYSCR3_RRAMWE0_SHIFT        (0u)
+#define CPG_SYSCR3_RRAMWE1_SHIFT        (1u)
+#define CPG_SYSCR3_RRAMWE2_SHIFT        (2u)
+#define CPG_SYSCR3_RRAMWE3_SHIFT        (3u)
+
+#define CPG_STBCR3_MSTP30_SHIFT         (0u)
+#define CPG_STBCR3_MSTP31_SHIFT         (1u)
+#define CPG_STBCR3_MSTP32_SHIFT         (2u)
+#define CPG_STBCR3_MSTP33_SHIFT         (3u)
+#define CPG_STBCR3_MSTP34_SHIFT         (4u)
+#define CPG_STBCR3_MSTP35_SHIFT         (5u)
+#define CPG_STBCR3_MSTP36_SHIFT         (6u)
+#define CPG_STBCR3_MSTP37_SHIFT         (7u)
+
+#define CPG_STBCR4_MSTP40_SHIFT         (0u)
+#define CPG_STBCR4_MSTP41_SHIFT         (1u)
+#define CPG_STBCR4_MSTP42_SHIFT         (2u)
+#define CPG_STBCR4_MSTP43_SHIFT         (3u)
+#define CPG_STBCR4_MSTP44_SHIFT         (4u)
+#define CPG_STBCR4_MSTP45_SHIFT         (5u)
+#define CPG_STBCR4_MSTP46_SHIFT         (6u)
+#define CPG_STBCR4_MSTP47_SHIFT         (7u)
+
+#define CPG_STBCR5_MSTP50_SHIFT         (0u)
+#define CPG_STBCR5_MSTP51_SHIFT         (1u)
+#define CPG_STBCR5_MSTP52_SHIFT         (2u)
+#define CPG_STBCR5_MSTP53_SHIFT         (3u)
+#define CPG_STBCR5_MSTP54_SHIFT         (4u)
+#define CPG_STBCR5_MSTP55_SHIFT         (5u)
+#define CPG_STBCR5_MSTP56_SHIFT         (6u)
+#define CPG_STBCR5_MSTP57_SHIFT         (7u)
+
+#define CPG_STBCR6_MSTP60_SHIFT         (0u)
+#define CPG_STBCR6_MSTP61_SHIFT         (1u)
+#define CPG_STBCR6_MSTP62_SHIFT         (2u)
+#define CPG_STBCR6_MSTP63_SHIFT         (3u)
+#define CPG_STBCR6_MSTP64_SHIFT         (4u)
+#define CPG_STBCR6_MSTP65_SHIFT         (5u)
+#define CPG_STBCR6_MSTP66_SHIFT         (6u)
+#define CPG_STBCR6_MSTP67_SHIFT         (7u)
+
+#define CPG_STBCR7_MSTP70_SHIFT         (0u)
+#define CPG_STBCR7_MSTP71_SHIFT         (1u)
+#define CPG_STBCR7_MSTP73_SHIFT         (3u)
+#define CPG_STBCR7_MSTP74_SHIFT         (4u)
+#define CPG_STBCR7_MSTP76_SHIFT         (6u)
+#define CPG_STBCR7_MSTP77_SHIFT         (7u)
+
+#define CPG_STBCR8_MSTP81_SHIFT         (1u)
+#define CPG_STBCR8_MSTP82_SHIFT         (2u)
+#define CPG_STBCR8_MSTP83_SHIFT         (3u)
+#define CPG_STBCR8_MSTP84_SHIFT         (4u)
+#define CPG_STBCR8_MSTP85_SHIFT         (5u)
+#define CPG_STBCR8_MSTP86_SHIFT         (6u)
+#define CPG_STBCR8_MSTP87_SHIFT         (7u)
+
+#define CPG_STBCR9_MSTP90_SHIFT         (0u)
+#define CPG_STBCR9_MSTP91_SHIFT         (1u)
+#define CPG_STBCR9_MSTP92_SHIFT         (2u)
+#define CPG_STBCR9_MSTP93_SHIFT         (3u)
+#define CPG_STBCR9_MSTP94_SHIFT         (4u)
+#define CPG_STBCR9_MSTP95_SHIFT         (5u)
+#define CPG_STBCR9_MSTP96_SHIFT         (6u)
+#define CPG_STBCR9_MSTP97_SHIFT         (7u)
+
+#define CPG_STBCR10_MSTP100_SHIFT       (0u)
+#define CPG_STBCR10_MSTP101_SHIFT       (1u)
+#define CPG_STBCR10_MSTP102_SHIFT       (2u)
+#define CPG_STBCR10_MSTP103_SHIFT       (3u)
+#define CPG_STBCR10_MSTP104_SHIFT       (4u)
+#define CPG_STBCR10_MSTP105_SHIFT       (5u)
+#define CPG_STBCR10_MSTP106_SHIFT       (6u)
+#define CPG_STBCR10_MSTP107_SHIFT       (7u)
+
+#define CPG_STBCR11_MSTP110_SHIFT       (0u)
+#define CPG_STBCR11_MSTP111_SHIFT       (1u)
+#define CPG_STBCR11_MSTP112_SHIFT       (2u)
+#define CPG_STBCR11_MSTP113_SHIFT       (3u)
+#define CPG_STBCR11_MSTP114_SHIFT       (4u)
+#define CPG_STBCR11_MSTP115_SHIFT       (5u)
+
+#define CPG_STBCR12_MSTP120_SHIFT       (0u)
+#define CPG_STBCR12_MSTP121_SHIFT       (1u)
+#define CPG_STBCR12_MSTP122_SHIFT       (2u)
+#define CPG_STBCR12_MSTP123_SHIFT       (3u)
+
+#define CPG_STBCR13_MSTP131_SHIFT       (1u)
+#define CPG_STBCR13_MSTP132_SHIFT       (2u)
+
+#define CPG_SWRSTCR1_SRST11_SHIFT       (1u)
+#define CPG_SWRSTCR1_SRST12_SHIFT       (2u)
+#define CPG_SWRSTCR1_SRST13_SHIFT       (3u)
+#define CPG_SWRSTCR1_SRST14_SHIFT       (4u)
+#define CPG_SWRSTCR1_SRST15_SHIFT       (5u)
+#define CPG_SWRSTCR1_SRST16_SHIFT       (6u)
+#define CPG_SWRSTCR1_AXTALE_SHIFT       (7u)
+
+#define CPG_SWRSTCR2_SRST21_SHIFT       (1u)
+
+#define CPG_SWRSTCR3_SRST32_SHIFT       (2u)
+
+#define CPG_RRAMKP_RRAMKP0_SHIFT        (0u)
+#define CPG_RRAMKP_RRAMKP1_SHIFT        (1u)
+#define CPG_RRAMKP_RRAMKP2_SHIFT        (2u)
+#define CPG_RRAMKP_RRAMKP3_SHIFT        (3u)
+
+#define CPG_DSCTR_RAMBOOT_SHIFT         (6u)
+#define CPG_DSCTR_EBUSKEEPE_SHIFT       (7u)
+
+#define CPG_DSSSR_P8_2_SHIFT            (0u)
+#define CPG_DSSSR_P9_1_SHIFT            (1u)
+#define CPG_DSSSR_P2_15_SHIFT           (2u)
+#define CPG_DSSSR_P7_8_SHIFT            (3u)
+#define CPG_DSSSR_P5_9_SHIFT            (4u)
+#define CPG_DSSSR_P6_4_SHIFT            (5u)
+#define CPG_DSSSR_RTCAR_SHIFT           (6u)
+#define CPG_DSSSR_NMI_SHIFT             (8u)
+#define CPG_DSSSR_P3_3_SHIFT            (9u)
+#define CPG_DSSSR_P8_7_SHIFT            (10u)
+#define CPG_DSSSR_P2_12_SHIFT           (11u)
+#define CPG_DSSSR_P3_1_SHIFT            (12u)
+#define CPG_DSSSR_P3_9_SHIFT            (13u)
+#define CPG_DSSSR_P6_2_SHIFT            (14u)
+
+#define CPG_DSESR_P8_2E_SHIFT           (0u)
+#define CPG_DSESR_P9_1E_SHIFT           (1u)
+#define CPG_DSESR_P2_15E_SHIFT          (2u)
+#define CPG_DSESR_P7_8E_SHIFT           (3u)
+#define CPG_DSESR_P5_9E_SHIFT           (4u)
+#define CPG_DSESR_P6_4E_SHIFT           (5u)
+#define CPG_DSESR_NMIE_SHIFT            (8u)
+#define CPG_DSESR_P3_3E_SHIFT           (9u)
+#define CPG_DSESR_P8_7E_SHIFT           (10u)
+#define CPG_DSESR_P2_12E_SHIFT          (11u)
+#define CPG_DSESR_P3_1E_SHIFT           (12u)
+#define CPG_DSESR_P3_9E_SHIFT           (13u)
+#define CPG_DSESR_P6_2E_SHIFT           (14u)
+
+#define CPG_DSFR_P8_2F_SHIFT            (0u)
+#define CPG_DSFR_P9_1F_SHIFT            (1u)
+#define CPG_DSFR_P2_15F_SHIFT           (2u)
+#define CPG_DSFR_P7_8F_SHIFT            (3u)
+#define CPG_DSFR_P5_9F_SHIFT            (4u)
+#define CPG_DSFR_P6_4F_SHIFT            (5u)
+#define CPG_DSFR_RTCARF_SHIFT           (6u)
+#define CPG_DSFR_NMIF_SHIFT             (8u)
+#define CPG_DSFR_P3_3F_SHIFT            (9u)
+#define CPG_DSFR_P8_7F_SHIFT            (10u)
+#define CPG_DSFR_P2_12F_SHIFT           (11u)
+#define CPG_DSFR_P3_1F_SHIFT            (12u)
+#define CPG_DSFR_P3_9F_SHIFT            (13u)
+#define CPG_DSFR_P6_2F_SHIFT            (14u)
+#define CPG_DSFR_IOKEEP_SHIFT           (15u)
+
+#define CPG_XTALCTR_GAIN0_SHIFT         (0u)
+#define CPG_XTALCTR_GAIN1_SHIFT         (1u)
+
+
+#endif /* CPG_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h	(revision 374)
@@ -0,0 +1,2675 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : dmac_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : DMAC register define header
+*******************************************************************************/
+#ifndef DMAC_IOBITMASK_H
+#define DMAC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- DMAC0 ---- */
+#define DMAC0_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC0_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC0_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC0_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC0_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC0_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC0_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC0_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC0_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC0_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC0_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC0_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC0_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC0_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC0_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC0_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC0_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC0_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC0_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC0_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC0_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC0_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC0_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC0_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC0_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC0_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC0_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC0_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC0_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC0_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC0_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC0_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC0_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC0_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC0_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC0_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC0_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC0_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC0_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC0_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC0_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC0_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC0_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC0_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC0_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC0_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC0_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC0_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC0_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC0_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC0_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC0_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC1 ---- */
+#define DMAC1_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC1_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC1_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC1_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC1_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC1_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC1_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC1_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC1_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC1_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC1_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC1_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC1_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC1_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC1_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC1_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC1_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC1_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC1_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC1_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC1_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC1_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC1_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC1_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC1_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC1_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC1_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC1_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC1_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC1_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC1_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC1_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC1_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC1_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC1_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC1_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC1_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC1_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC1_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC1_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC1_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC1_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC1_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC1_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC1_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC1_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC1_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC1_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC1_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC1_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC1_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC1_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC2 ---- */
+#define DMAC2_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC2_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC2_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC2_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC2_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC2_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC2_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC2_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC2_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC2_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC2_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC2_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC2_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC2_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC2_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC2_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC2_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC2_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC2_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC2_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC2_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC2_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC2_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC2_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC2_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC2_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC2_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC2_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC2_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC2_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC2_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC2_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC2_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC2_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC2_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC2_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC2_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC2_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC2_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC2_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC2_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC2_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC2_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC2_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC2_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC2_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC2_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC2_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC2_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC2_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC2_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC2_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC3 ---- */
+#define DMAC3_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC3_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC3_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC3_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC3_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC3_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC3_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC3_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC3_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC3_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC3_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC3_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC3_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC3_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC3_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC3_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC3_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC3_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC3_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC3_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC3_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC3_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC3_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC3_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC3_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC3_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC3_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC3_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC3_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC3_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC3_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC3_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC3_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC3_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC3_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC3_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC3_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC3_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC3_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC3_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC3_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC3_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC3_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC3_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC3_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC3_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC3_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC3_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC3_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC3_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC3_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC3_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC4 ---- */
+#define DMAC4_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC4_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC4_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC4_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC4_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC4_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC4_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC4_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC4_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC4_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC4_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC4_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC4_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC4_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC4_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC4_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC4_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC4_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC4_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC4_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC4_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC4_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC4_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC4_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC4_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC4_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC4_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC4_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC4_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC4_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC4_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC4_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC4_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC4_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC4_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC4_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC4_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC4_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC4_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC4_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC4_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC4_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC4_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC4_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC4_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC4_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC4_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC4_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC4_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC4_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC4_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC4_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC5 ---- */
+#define DMAC5_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC5_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC5_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC5_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC5_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC5_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC5_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC5_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC5_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC5_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC5_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC5_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC5_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC5_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC5_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC5_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC5_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC5_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC5_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC5_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC5_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC5_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC5_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC5_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC5_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC5_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC5_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC5_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC5_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC5_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC5_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC5_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC5_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC5_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC5_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC5_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC5_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC5_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC5_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC5_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC5_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC5_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC5_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC5_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC5_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC5_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC5_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC5_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC5_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC5_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC5_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC5_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC6 ---- */
+#define DMAC6_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC6_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC6_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC6_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC6_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC6_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC6_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC6_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC6_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC6_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC6_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC6_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC6_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC6_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC6_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC6_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC6_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC6_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC6_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC6_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC6_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC6_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC6_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC6_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC6_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC6_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC6_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC6_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC6_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC6_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC6_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC6_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC6_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC6_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC6_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC6_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC6_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC6_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC6_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC6_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC6_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC6_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC6_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC6_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC6_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC6_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC6_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC6_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC6_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC6_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC6_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC6_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC7 ---- */
+#define DMAC7_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC7_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC7_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC7_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC7_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC7_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC7_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC7_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC7_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC7_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC7_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC7_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC7_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC7_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC7_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC7_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC7_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC7_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC7_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC7_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC7_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC7_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC7_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC7_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC7_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC7_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC7_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC7_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC7_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC7_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC7_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC7_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC7_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC7_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC7_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC7_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC7_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC7_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC7_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC7_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC7_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC7_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC7_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC7_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC7_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC7_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC7_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC7_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC7_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC7_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC7_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC7_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC0-7 ---- */
+#define DMAC07_DCTRL_0_7_PR                 (0x00000001uL)
+#define DMAC07_DCTRL_0_7_LVINT              (0x00000002uL)
+#define DMAC07_DCTRL_0_7_LDCA               (0x0000003CuL)
+#define DMAC07_DCTRL_0_7_LWCA               (0x000003C0uL)
+
+#define DMAC07_DSTAT_EN_0_7_EN0             (0x00000001uL)
+#define DMAC07_DSTAT_EN_0_7_EN1             (0x00000002uL)
+#define DMAC07_DSTAT_EN_0_7_EN2             (0x00000004uL)
+#define DMAC07_DSTAT_EN_0_7_EN3             (0x00000008uL)
+#define DMAC07_DSTAT_EN_0_7_EN4             (0x00000010uL)
+#define DMAC07_DSTAT_EN_0_7_EN5             (0x00000020uL)
+#define DMAC07_DSTAT_EN_0_7_EN6             (0x00000040uL)
+#define DMAC07_DSTAT_EN_0_7_EN7             (0x00000080uL)
+
+#define DMAC07_DSTAT_ER_0_7_ER0             (0x00000001uL)
+#define DMAC07_DSTAT_ER_0_7_ER1             (0x00000002uL)
+#define DMAC07_DSTAT_ER_0_7_ER2             (0x00000004uL)
+#define DMAC07_DSTAT_ER_0_7_ER3             (0x00000008uL)
+#define DMAC07_DSTAT_ER_0_7_ER4             (0x00000010uL)
+#define DMAC07_DSTAT_ER_0_7_ER5             (0x00000020uL)
+#define DMAC07_DSTAT_ER_0_7_ER6             (0x00000040uL)
+#define DMAC07_DSTAT_ER_0_7_ER7             (0x00000080uL)
+
+#define DMAC07_DSTAT_END_0_7_END0           (0x00000001uL)
+#define DMAC07_DSTAT_END_0_7_END1           (0x00000002uL)
+#define DMAC07_DSTAT_END_0_7_END2           (0x00000004uL)
+#define DMAC07_DSTAT_END_0_7_END3           (0x00000008uL)
+#define DMAC07_DSTAT_END_0_7_END4           (0x00000010uL)
+#define DMAC07_DSTAT_END_0_7_END5           (0x00000020uL)
+#define DMAC07_DSTAT_END_0_7_END6           (0x00000040uL)
+#define DMAC07_DSTAT_END_0_7_END7           (0x00000080uL)
+
+#define DMAC07_DSTAT_TC_0_7_TC0             (0x00000001uL)
+#define DMAC07_DSTAT_TC_0_7_TC1             (0x00000002uL)
+#define DMAC07_DSTAT_TC_0_7_TC2             (0x00000004uL)
+#define DMAC07_DSTAT_TC_0_7_TC3             (0x00000008uL)
+#define DMAC07_DSTAT_TC_0_7_TC4             (0x00000010uL)
+#define DMAC07_DSTAT_TC_0_7_TC5             (0x00000020uL)
+#define DMAC07_DSTAT_TC_0_7_TC6             (0x00000040uL)
+#define DMAC07_DSTAT_TC_0_7_TC7             (0x00000080uL)
+
+#define DMAC07_DSTAT_SUS_0_7_SUS0           (0x00000001uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS1           (0x00000002uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS2           (0x00000004uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS3           (0x00000008uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS4           (0x00000010uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS5           (0x00000020uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS6           (0x00000040uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS7           (0x00000080uL)
+
+/* ---- DMAC8 ---- */
+#define DMAC8_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC8_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC8_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC8_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC8_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC8_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC8_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC8_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC8_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC8_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC8_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC8_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC8_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC8_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC8_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC8_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC8_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC8_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC8_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC8_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC8_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC8_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC8_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC8_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC8_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC8_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC8_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC8_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC8_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC8_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC8_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC8_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC8_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC8_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC8_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC8_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC8_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC8_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC8_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC8_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC8_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC8_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC8_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC8_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC8_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC8_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC8_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC8_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC8_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC8_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC8_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC8_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC9 ---- */
+#define DMAC9_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC9_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC9_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC9_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC9_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC9_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC9_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC9_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC9_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC9_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC9_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC9_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC9_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC9_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC9_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC9_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC9_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC9_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC9_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC9_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC9_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC9_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC9_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC9_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC9_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC9_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC9_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC9_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC9_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC9_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC9_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC9_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC9_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC9_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC9_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC9_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC9_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC9_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC9_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC9_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC9_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC9_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC9_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC9_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC9_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC9_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC9_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC9_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC9_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC9_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC9_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC9_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC10 ---- */
+#define DMAC10_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC10_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC10_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC10_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC10_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC10_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC10_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC10_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC10_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC10_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC10_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC10_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC10_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC10_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC10_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC10_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC10_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC10_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC10_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC10_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC10_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC10_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC10_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC10_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC10_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC10_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC10_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC10_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC10_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC10_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC10_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC10_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC10_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC10_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC10_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC10_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC10_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC10_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC10_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC10_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC10_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC10_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC10_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC10_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC10_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC10_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC10_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC10_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC10_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC10_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC10_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC10_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC11 ---- */
+#define DMAC11_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC11_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC11_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC11_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC11_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC11_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC11_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC11_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC11_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC11_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC11_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC11_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC11_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC11_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC11_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC11_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC11_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC11_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC11_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC11_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC11_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC11_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC11_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC11_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC11_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC11_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC11_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC11_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC11_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC11_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC11_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC11_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC11_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC11_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC11_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC11_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC11_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC11_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC11_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC11_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC11_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC11_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC11_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC11_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC11_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC11_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC11_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC11_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC11_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC11_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC11_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC11_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC12 ---- */
+#define DMAC12_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC12_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC12_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC12_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC12_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC12_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC12_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC12_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC12_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC12_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC12_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC12_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC12_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC12_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC12_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC12_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC12_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC12_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC12_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC12_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC12_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC12_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC12_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC12_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC12_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC12_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC12_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC12_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC12_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC12_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC12_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC12_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC12_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC12_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC12_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC12_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC12_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC12_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC12_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC12_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC12_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC12_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC12_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC12_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC12_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC12_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC12_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC12_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC12_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC12_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC12_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC12_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC13 ---- */
+#define DMAC13_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC13_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC13_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC13_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC13_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC13_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC13_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC13_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC13_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC13_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC13_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC13_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC13_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC13_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC13_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC13_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC13_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC13_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC13_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC13_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC13_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC13_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC13_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC13_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC13_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC13_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC13_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC13_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC13_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC13_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC13_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC13_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC13_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC13_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC13_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC13_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC13_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC13_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC13_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC13_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC13_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC13_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC13_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC13_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC13_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC13_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC13_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC13_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC13_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC13_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC13_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC13_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC14 ---- */
+#define DMAC14_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC14_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC14_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC14_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC14_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC14_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC14_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC14_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC14_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC14_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC14_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC14_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC14_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC14_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC14_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC14_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC14_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC14_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC14_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC14_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC14_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC14_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC14_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC14_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC14_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC14_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC14_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC14_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC14_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC14_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC14_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC14_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC14_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC14_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC14_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC14_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC14_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC14_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC14_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC14_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC14_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC14_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC14_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC14_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC14_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC14_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC14_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC14_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC14_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC14_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC14_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC14_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC15 ---- */
+#define DMAC15_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC15_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC15_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC15_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC15_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC15_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC15_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC15_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC15_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC15_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC15_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC15_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC15_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC15_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC15_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC15_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC15_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC15_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC15_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC15_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC15_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC15_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC15_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC15_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC15_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC15_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC15_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC15_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC15_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC15_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC15_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC15_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC15_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC15_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC15_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC15_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC15_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC15_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC15_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC15_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC15_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC15_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC15_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC15_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC15_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC15_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC15_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC15_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC15_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC15_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC15_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC15_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC8-15 ---- */
+#define DMAC815_DCTRL_8_15_PR               (0x00000001uL)
+#define DMAC815_DCTRL_8_15_LVINT            (0x00000002uL)
+#define DMAC815_DCTRL_8_15_LDCA             (0x0000003CuL)
+#define DMAC815_DCTRL_8_15_LWCA             (0x00003C00uL)
+
+#define DMAC815_DSTAT_EN_8_15_EN8           (0x00000001uL)
+#define DMAC815_DSTAT_EN_8_15_EN9           (0x00000002uL)
+#define DMAC815_DSTAT_EN_8_15_EN10          (0x00000004uL)
+#define DMAC815_DSTAT_EN_8_15_EN11          (0x00000008uL)
+#define DMAC815_DSTAT_EN_8_15_EN12          (0x00000010uL)
+#define DMAC815_DSTAT_EN_8_15_EN13          (0x00000020uL)
+#define DMAC815_DSTAT_EN_8_15_EN14          (0x00000040uL)
+#define DMAC815_DSTAT_EN_8_15_EN15          (0x00000080uL)
+
+#define DMAC815_DSTAT_ER_8_15_ER8           (0x00000001uL)
+#define DMAC815_DSTAT_ER_8_15_ER9           (0x00000002uL)
+#define DMAC815_DSTAT_ER_8_15_ER10          (0x00000004uL)
+#define DMAC815_DSTAT_ER_8_15_ER11          (0x00000008uL)
+#define DMAC815_DSTAT_ER_8_15_ER12          (0x00000010uL)
+#define DMAC815_DSTAT_ER_8_15_ER13          (0x00000020uL)
+#define DMAC815_DSTAT_ER_8_15_ER14          (0x00000040uL)
+#define DMAC815_DSTAT_ER_8_15_ER15          (0x00000080uL)
+
+#define DMAC815_DSTAT_END_8_15_END8         (0x00000001uL)
+#define DMAC815_DSTAT_END_8_15_END9         (0x00000002uL)
+#define DMAC815_DSTAT_END_8_15_END10        (0x00000004uL)
+#define DMAC815_DSTAT_END_8_15_END11        (0x00000008uL)
+#define DMAC815_DSTAT_END_8_15_END12        (0x00000010uL)
+#define DMAC815_DSTAT_END_8_15_END13        (0x00000020uL)
+#define DMAC815_DSTAT_END_8_15_END14        (0x00000040uL)
+#define DMAC815_DSTAT_END_8_15_END15        (0x00000080uL)
+
+#define DMAC815_DSTAT_TC_8_15_TC8           (0x00000001uL)
+#define DMAC815_DSTAT_TC_8_15_TC9           (0x00000002uL)
+#define DMAC815_DSTAT_TC_8_15_TC10          (0x00000004uL)
+#define DMAC815_DSTAT_TC_8_15_TC11          (0x00000008uL)
+#define DMAC815_DSTAT_TC_8_15_TC12          (0x00000010uL)
+#define DMAC815_DSTAT_TC_8_15_TC13          (0x00000020uL)
+#define DMAC815_DSTAT_TC_8_15_TC14          (0x00000040uL)
+#define DMAC815_DSTAT_TC_8_15_TC15          (0x00000080uL)
+
+#define DMAC815_DSTAT_SUS_8_15_SUS8         (0x00000001uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS9         (0x00000002uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS10        (0x00000004uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS11        (0x00000008uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS12        (0x00000010uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS13        (0x00000020uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS14        (0x00000040uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS15        (0x00000080uL)
+
+/* ---- DMAC0-1 ---- */
+#define DMAC01_DMARS_CH0_RID                (0x00000003uL)
+#define DMAC01_DMARS_CH0_MID                (0x000001FCuL)
+#define DMAC01_DMARS_CH1_RID                (0x00030000uL)
+#define DMAC01_DMARS_CH1_MID                (0x01FC0000uL)
+
+/* ---- DMAC2-3 ---- */
+#define DMAC23_DMARS_CH2_RID                (0x00000003uL)
+#define DMAC23_DMARS_CH2_MID                (0x000001FCuL)
+#define DMAC23_DMARS_CH3_RID                (0x00030000uL)
+#define DMAC23_DMARS_CH3_MID                (0x01FC0000uL)
+
+/* ---- DMAC4-5 ---- */
+#define DMAC45_DMARS_CH4_RID                (0x00000003uL)
+#define DMAC45_DMARS_CH4_MID                (0x000001FCuL)
+#define DMAC45_DMARS_CH5_RID                (0x00030000uL)
+#define DMAC45_DMARS_CH5_MID                (0x01FC0000uL)
+
+/* ---- DMAC6-7 ---- */
+#define DMAC67_DMARS_CH6_RID                (0x00000003uL)
+#define DMAC67_DMARS_CH6_MID                (0x000001FCuL)
+#define DMAC67_DMARS_CH7_RID                (0x00030000uL)
+#define DMAC67_DMARS_CH7_MID                (0x01FC0000uL)
+
+/* ---- DMAC8-9 ---- */
+#define DMAC89_DMARS_CH8_RID                (0x00000003uL)
+#define DMAC89_DMARS_CH8_MID                (0x000001FCuL)
+#define DMAC89_DMARS_CH9_RID                (0x00030000uL)
+#define DMAC89_DMARS_CH9_MID                (0x01FC0000uL)
+
+/* ---- DMAC10-11 ---- */
+#define DMAC1011_DMARS_CH10_RID             (0x00000003uL)
+#define DMAC1011_DMARS_CH10_MID             (0x000001FCuL)
+#define DMAC1011_DMARS_CH11_RID             (0x00030000uL)
+#define DMAC1011_DMARS_CH11_MID             (0x01FC0000uL)
+
+/* ---- DMAC12-13 ---- */
+#define DMAC1213_DMARS_CH12_RID             (0x00000003uL)
+#define DMAC1213_DMARS_CH12_MID             (0x000001FCuL)
+#define DMAC1213_DMARS_CH13_RID             (0x00030000uL)
+#define DMAC1213_DMARS_CH13_MID             (0x01FC0000uL)
+
+/* ---- DMAC14-15 ---- */
+#define DMAC1415_DMARS_CH14_RID             (0x00000003uL)
+#define DMAC1415_DMARS_CH14_MID             (0x000001FCuL)
+#define DMAC1415_DMARS_CH15_RID             (0x00030000uL)
+#define DMAC1415_DMARS_CH15_MID             (0x01FC0000uL)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- DMAC0 ---- */
+#define DMAC0_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC0_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC0_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC0_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC0_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC0_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC0_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC0_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC0_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC0_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC0_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC0_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC0_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC0_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC0_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC0_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC0_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC0_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC0_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC0_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC0_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC0_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC0_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC0_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC0_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC0_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC0_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC0_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC0_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC0_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC0_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC0_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC0_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC0_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC0_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC0_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC0_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC0_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC0_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC0_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC0_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC0_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC0_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC0_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC0_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC0_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC0_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC0_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC0_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC0_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC0_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC0_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC0_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC0_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC0_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC1 ---- */
+#define DMAC1_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC1_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC1_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC1_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC1_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC1_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC1_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC1_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC1_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC1_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC1_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC1_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC1_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC1_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC1_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC1_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC1_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC1_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC1_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC1_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC1_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC1_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC1_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC1_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC1_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC1_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC1_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC1_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC1_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC1_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC1_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC1_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC1_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC1_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC1_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC1_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC1_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC1_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC1_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC1_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC1_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC1_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC1_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC1_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC1_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC1_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC1_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC1_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC1_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC1_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC1_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC1_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC1_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC1_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC1_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC2 ---- */
+#define DMAC2_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC2_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC2_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC2_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC2_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC2_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC2_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC2_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC2_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC2_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC2_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC2_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC2_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC2_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC2_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC2_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC2_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC2_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC2_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC2_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC2_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC2_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC2_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC2_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC2_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC2_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC2_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC2_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC2_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC2_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC2_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC2_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC2_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC2_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC2_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC2_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC2_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC2_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC2_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC2_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC2_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC2_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC2_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC2_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC2_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC2_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC2_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC2_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC2_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC2_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC2_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC2_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC2_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC2_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC2_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC3 ---- */
+#define DMAC3_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC3_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC3_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC3_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC3_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC3_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC3_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC3_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC3_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC3_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC3_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC3_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC3_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC3_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC3_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC3_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC3_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC3_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC3_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC3_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC3_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC3_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC3_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC3_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC3_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC3_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC3_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC3_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC3_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC3_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC3_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC3_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC3_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC3_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC3_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC3_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC3_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC3_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC3_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC3_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC3_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC3_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC3_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC3_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC3_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC3_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC3_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC3_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC3_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC3_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC3_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC3_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC3_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC3_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC3_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC4 ---- */
+#define DMAC4_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC4_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC4_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC4_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC4_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC4_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC4_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC4_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC4_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC4_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC4_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC4_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC4_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC4_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC4_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC4_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC4_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC4_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC4_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC4_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC4_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC4_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC4_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC4_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC4_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC4_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC4_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC4_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC4_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC4_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC4_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC4_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC4_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC4_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC4_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC4_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC4_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC4_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC4_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC4_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC4_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC4_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC4_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC4_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC4_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC4_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC4_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC4_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC4_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC4_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC4_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC4_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC4_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC4_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC4_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC5 ---- */
+#define DMAC5_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC5_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC5_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC5_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC5_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC5_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC5_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC5_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC5_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC5_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC5_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC5_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC5_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC5_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC5_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC5_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC5_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC5_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC5_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC5_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC5_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC5_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC5_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC5_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC5_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC5_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC5_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC5_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC5_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC5_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC5_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC5_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC5_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC5_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC5_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC5_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC5_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC5_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC5_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC5_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC5_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC5_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC5_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC5_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC5_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC5_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC5_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC5_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC5_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC5_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC5_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC5_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC5_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC5_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC5_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC6 ---- */
+#define DMAC6_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC6_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC6_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC6_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC6_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC6_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC6_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC6_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC6_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC6_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC6_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC6_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC6_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC6_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC6_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC6_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC6_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC6_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC6_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC6_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC6_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC6_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC6_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC6_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC6_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC6_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC6_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC6_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC6_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC6_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC6_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC6_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC6_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC6_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC6_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC6_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC6_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC6_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC6_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC6_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC6_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC6_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC6_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC6_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC6_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC6_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC6_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC6_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC6_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC6_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC6_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC6_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC6_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC6_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC6_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC7 ---- */
+#define DMAC7_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC7_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC7_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC7_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC7_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC7_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC7_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC7_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC7_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC7_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC7_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC7_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC7_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC7_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC7_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC7_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC7_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC7_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC7_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC7_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC7_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC7_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC7_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC7_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC7_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC7_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC7_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC7_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC7_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC7_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC7_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC7_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC7_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC7_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC7_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC7_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC7_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC7_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC7_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC7_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC7_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC7_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC7_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC7_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC7_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC7_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC7_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC7_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC7_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC7_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC7_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC7_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC7_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC7_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC7_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC0-7 ---- */
+#define DMAC07_DCTRL_0_7_PR_SHIFT           (0u)
+#define DMAC07_DCTRL_0_7_LVINT_SHIFT        (1u)
+#define DMAC07_DCTRL_0_7_LDCA_SHIFT         (2u)
+#define DMAC07_DCTRL_0_7_LWCA_SHIFT         (6u)
+
+#define DMAC07_DSTAT_EN_0_7_EN0_SHIFT       (0u)
+#define DMAC07_DSTAT_EN_0_7_EN1_SHIFT       (1u)
+#define DMAC07_DSTAT_EN_0_7_EN2_SHIFT       (2u)
+#define DMAC07_DSTAT_EN_0_7_EN3_SHIFT       (3u)
+#define DMAC07_DSTAT_EN_0_7_EN4_SHIFT       (4u)
+#define DMAC07_DSTAT_EN_0_7_EN5_SHIFT       (5u)
+#define DMAC07_DSTAT_EN_0_7_EN6_SHIFT       (6u)
+#define DMAC07_DSTAT_EN_0_7_EN7_SHIFT       (7u)
+
+#define DMAC07_DSTAT_ER_0_7_ER0_SHIFT       (0u)
+#define DMAC07_DSTAT_ER_0_7_ER1_SHIFT       (1u)
+#define DMAC07_DSTAT_ER_0_7_ER2_SHIFT       (2u)
+#define DMAC07_DSTAT_ER_0_7_ER3_SHIFT       (3u)
+#define DMAC07_DSTAT_ER_0_7_ER4_SHIFT       (4u)
+#define DMAC07_DSTAT_ER_0_7_ER5_SHIFT       (5u)
+#define DMAC07_DSTAT_ER_0_7_ER6_SHIFT       (6u)
+#define DMAC07_DSTAT_ER_0_7_ER7_SHIFT       (7u)
+
+#define DMAC07_DSTAT_END_0_7_END0_SHIFT     (0u)
+#define DMAC07_DSTAT_END_0_7_END1_SHIFT     (1u)
+#define DMAC07_DSTAT_END_0_7_END2_SHIFT     (2u)
+#define DMAC07_DSTAT_END_0_7_END3_SHIFT     (3u)
+#define DMAC07_DSTAT_END_0_7_END4_SHIFT     (4u)
+#define DMAC07_DSTAT_END_0_7_END5_SHIFT     (5u)
+#define DMAC07_DSTAT_END_0_7_END6_SHIFT     (6u)
+#define DMAC07_DSTAT_END_0_7_END7_SHIFT     (7u)
+
+#define DMAC07_DSTAT_TC_0_7_TC0_SHIFT       (0u)
+#define DMAC07_DSTAT_TC_0_7_TC1_SHIFT       (1u)
+#define DMAC07_DSTAT_TC_0_7_TC2_SHIFT       (2u)
+#define DMAC07_DSTAT_TC_0_7_TC3_SHIFT       (3u)
+#define DMAC07_DSTAT_TC_0_7_TC4_SHIFT       (4u)
+#define DMAC07_DSTAT_TC_0_7_TC5_SHIFT       (5u)
+#define DMAC07_DSTAT_TC_0_7_TC6_SHIFT       (6u)
+#define DMAC07_DSTAT_TC_0_7_TC7_SHIFT       (7u)
+
+#define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT     (0u)
+#define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT     (1u)
+#define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT     (2u)
+#define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT     (3u)
+#define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT     (4u)
+#define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT     (5u)
+#define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT     (6u)
+#define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT     (7u)
+
+/* ---- DMAC8 ---- */
+#define DMAC8_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC8_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC8_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC8_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC8_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC8_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC8_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC8_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC8_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC8_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC8_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC8_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC8_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC8_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC8_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC8_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC8_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC8_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC8_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC8_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC8_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC8_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC8_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC8_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC8_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC8_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC8_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC8_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC8_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC8_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC8_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC8_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC8_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC8_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC8_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC8_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC8_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC8_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC8_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC8_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC8_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC8_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC8_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC8_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC8_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC8_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC8_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC8_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC8_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC8_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC8_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC8_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC8_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC8_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC8_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC9 ---- */
+#define DMAC9_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC9_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC9_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC9_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC9_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC9_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC9_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC9_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC9_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC9_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC9_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC9_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC9_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC9_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC9_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC9_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC9_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC9_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC9_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC9_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC9_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC9_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC9_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC9_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC9_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC9_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC9_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC9_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC9_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC9_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC9_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC9_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC9_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC9_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC9_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC9_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC9_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC9_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC9_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC9_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC9_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC9_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC9_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC9_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC9_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC9_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC9_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC9_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC9_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC9_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC9_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC9_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC9_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC9_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC9_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC10 ---- */
+#define DMAC10_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC10_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC10_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC10_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC10_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC10_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC10_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC10_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC10_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC10_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC10_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC10_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC10_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC10_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC10_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC10_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC10_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC10_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC10_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC10_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC10_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC10_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC10_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC10_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC10_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC10_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC10_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC10_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC10_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC10_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC10_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC10_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC10_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC10_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC10_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC10_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC10_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC10_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC10_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC10_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC10_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC10_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC10_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC10_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC10_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC10_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC10_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC10_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC10_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC10_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC10_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC10_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC10_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC10_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC10_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC11 ---- */
+#define DMAC11_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC11_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC11_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC11_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC11_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC11_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC11_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC11_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC11_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC11_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC11_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC11_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC11_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC11_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC11_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC11_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC11_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC11_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC11_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC11_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC11_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC11_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC11_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC11_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC11_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC11_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC11_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC11_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC11_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC11_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC11_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC11_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC11_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC11_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC11_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC11_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC11_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC11_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC11_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC11_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC11_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC11_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC11_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC11_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC11_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC11_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC11_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC11_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC11_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC11_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC11_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC11_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC11_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC11_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC11_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC12 ---- */
+#define DMAC12_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC12_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC12_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC12_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC12_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC12_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC12_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC12_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC12_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC12_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC12_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC12_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC12_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC12_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC12_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC12_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC12_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC12_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC12_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC12_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC12_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC12_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC12_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC12_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC12_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC12_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC12_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC12_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC12_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC12_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC12_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC12_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC12_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC12_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC12_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC12_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC12_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC12_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC12_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC12_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC12_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC12_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC12_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC12_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC12_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC12_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC12_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC12_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC12_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC12_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC12_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC12_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC12_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC12_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC12_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC13 ---- */
+#define DMAC13_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC13_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC13_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC13_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC13_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC13_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC13_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC13_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC13_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC13_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC13_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC13_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC13_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC13_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC13_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC13_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC13_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC13_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC13_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC13_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC13_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC13_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC13_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC13_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC13_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC13_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC13_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC13_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC13_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC13_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC13_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC13_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC13_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC13_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC13_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC13_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC13_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC13_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC13_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC13_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC13_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC13_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC13_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC13_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC13_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC13_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC13_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC13_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC13_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC13_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC13_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC13_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC13_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC13_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC13_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC14 ---- */
+#define DMAC14_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC14_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC14_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC14_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC14_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC14_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC14_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC14_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC14_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC14_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC14_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC14_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC14_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC14_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC14_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC14_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC14_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC14_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC14_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC14_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC14_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC14_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC14_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC14_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC14_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC14_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC14_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC14_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC14_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC14_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC14_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC14_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC14_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC14_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC14_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC14_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC14_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC14_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC14_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC14_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC14_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC14_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC14_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC14_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC14_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC14_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC14_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC14_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC14_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC14_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC14_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC14_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC14_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC14_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC14_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC15 ---- */
+#define DMAC15_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC15_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC15_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC15_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC15_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC15_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC15_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC15_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC15_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC15_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC15_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC15_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC15_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC15_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC15_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC15_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC15_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC15_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC15_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC15_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC15_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC15_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC15_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC15_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC15_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC15_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC15_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC15_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC15_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC15_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC15_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC15_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC15_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC15_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC15_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC15_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC15_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC15_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC15_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC15_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC15_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC15_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC15_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC15_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC15_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC15_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC15_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC15_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC15_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC15_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC15_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC15_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC15_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC15_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC15_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC8-15 ---- */
+#define DMAC815_DCTRL_8_15_PR_SHIFT         (0u)
+#define DMAC815_DCTRL_8_15_LVINT_SHIFT      (1u)
+#define DMAC815_DCTRL_8_15_LDCA_SHIFT       (2u)
+#define DMAC815_DCTRL_8_15_LWCA_SHIFT       (10u)
+
+#define DMAC815_DSTAT_EN_8_15_EN8_SHIFT     (0u)
+#define DMAC815_DSTAT_EN_8_15_EN9_SHIFT     (1u)
+#define DMAC815_DSTAT_EN_8_15_EN10_SHIFT    (2u)
+#define DMAC815_DSTAT_EN_8_15_EN11_SHIFT    (3u)
+#define DMAC815_DSTAT_EN_8_15_EN12_SHIFT    (4u)
+#define DMAC815_DSTAT_EN_8_15_EN13_SHIFT    (5u)
+#define DMAC815_DSTAT_EN_8_15_EN14_SHIFT    (6u)
+#define DMAC815_DSTAT_EN_8_15_EN15_SHIFT    (7u)
+
+#define DMAC815_DSTAT_ER_8_15_ER8_SHIFT     (0u)
+#define DMAC815_DSTAT_ER_8_15_ER9_SHIFT     (1u)
+#define DMAC815_DSTAT_ER_8_15_ER10_SHIFT    (2u)
+#define DMAC815_DSTAT_ER_8_15_ER11_SHIFT    (3u)
+#define DMAC815_DSTAT_ER_8_15_ER12_SHIFT    (4u)
+#define DMAC815_DSTAT_ER_8_15_ER13_SHIFT    (5u)
+#define DMAC815_DSTAT_ER_8_15_ER14_SHIFT    (6u)
+#define DMAC815_DSTAT_ER_8_15_ER15_SHIFT    (7u)
+
+#define DMAC815_DSTAT_END_8_15_END8_SHIFT   (0u)
+#define DMAC815_DSTAT_END_8_15_END9_SHIFT   (1u)
+#define DMAC815_DSTAT_END_8_15_END10_SHIFT  (2u)
+#define DMAC815_DSTAT_END_8_15_END11_SHIFT  (3u)
+#define DMAC815_DSTAT_END_8_15_END12_SHIFT  (4u)
+#define DMAC815_DSTAT_END_8_15_END13_SHIFT  (5u)
+#define DMAC815_DSTAT_END_8_15_END14_SHIFT  (6u)
+#define DMAC815_DSTAT_END_8_15_END15_SHIFT  (7u)
+
+#define DMAC815_DSTAT_TC_8_15_TC8_SHIFT     (0u)
+#define DMAC815_DSTAT_TC_8_15_TC9_SHIFT     (1u)
+#define DMAC815_DSTAT_TC_8_15_TC10_SHIFT    (2u)
+#define DMAC815_DSTAT_TC_8_15_TC11_SHIFT    (3u)
+#define DMAC815_DSTAT_TC_8_15_TC12_SHIFT    (4u)
+#define DMAC815_DSTAT_TC_8_15_TC13_SHIFT    (5u)
+#define DMAC815_DSTAT_TC_8_15_TC14_SHIFT    (6u)
+#define DMAC815_DSTAT_TC_8_15_TC15_SHIFT    (7u)
+
+#define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT   (0u)
+#define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT   (1u)
+#define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT  (2u)
+#define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT  (3u)
+#define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT  (4u)
+#define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT  (5u)
+#define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT  (6u)
+#define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT  (7u)
+
+/* ---- DMAC0-1 ---- */
+#define DMAC01_DMARS_CH0_RID_SHIFT          (0u)
+#define DMAC01_DMARS_CH0_MID_SHIFT          (2u)
+#define DMAC01_DMARS_CH1_RID_SHIFT          (16u)
+#define DMAC01_DMARS_CH1_MID_SHIFT          (18u)
+
+/* ---- DMAC2-3 ---- */
+#define DMAC23_DMARS_CH2_RID_SHIFT          (0u)
+#define DMAC23_DMARS_CH2_MID_SHIFT          (2u)
+#define DMAC23_DMARS_CH3_RID_SHIFT          (16u)
+#define DMAC23_DMARS_CH3_MID_SHIFT          (18u)
+
+/* ---- DMAC4-5 ---- */
+#define DMAC45_DMARS_CH4_RID_SHIFT          (0u)
+#define DMAC45_DMARS_CH4_MID_SHIFT          (2u)
+#define DMAC45_DMARS_CH5_RID_SHIFT          (16u)
+#define DMAC45_DMARS_CH5_MID_SHIFT          (18u)
+
+/* ---- DMAC6-7 ---- */
+#define DMAC67_DMARS_CH6_RID_SHIFT          (0u)
+#define DMAC67_DMARS_CH6_MID_SHIFT          (2u)
+#define DMAC67_DMARS_CH7_RID_SHIFT          (16u)
+#define DMAC67_DMARS_CH7_MID_SHIFT          (18u)
+
+/* ---- DMAC8-9 ---- */
+#define DMAC89_DMARS_CH8_RID_SHIFT          (0u)
+#define DMAC89_DMARS_CH8_MID_SHIFT          (2u)
+#define DMAC89_DMARS_CH9_RID_SHIFT          (16u)
+#define DMAC89_DMARS_CH9_MID_SHIFT          (18u)
+
+/* ---- DMAC10-11 ---- */
+#define DMAC1011_DMARS_CH10_RID_SHIFT       (0u)
+#define DMAC1011_DMARS_CH10_MID_SHIFT       (2u)
+#define DMAC1011_DMARS_CH11_RID_SHIFT       (16u)
+#define DMAC1011_DMARS_CH11_MID_SHIFT       (18u)
+
+/* ---- DMAC12-13 ---- */
+#define DMAC1213_DMARS_CH12_RID_SHIFT       (0u)
+#define DMAC1213_DMARS_CH12_MID_SHIFT       (2u)
+#define DMAC1213_DMARS_CH13_RID_SHIFT       (16u)
+#define DMAC1213_DMARS_CH13_MID_SHIFT       (18u)
+
+/* ---- DMAC14-15 ---- */
+#define DMAC1415_DMARS_CH14_RID_SHIFT       (0u)
+#define DMAC1415_DMARS_CH14_MID_SHIFT       (2u)
+#define DMAC1415_DMARS_CH15_RID_SHIFT       (16u)
+#define DMAC1415_DMARS_CH15_MID_SHIFT       (18u)
+
+
+#endif /* DMAC_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h	(revision 374)
@@ -0,0 +1,5793 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : gpio_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : General purpose I/O ports register define header
+*******************************************************************************/
+#ifndef GPIO_IOBITMASK_H
+#define GPIO_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- P0 ---- */
+#define GPIO_PPR0_PPR00                         (0x0001u)
+#define GPIO_PPR0_PPR01                         (0x0002u)
+#define GPIO_PPR0_PPR02                         (0x0004u)
+#define GPIO_PPR0_PPR03                         (0x0008u)
+#define GPIO_PPR0_PPR04                         (0x0010u)
+#define GPIO_PPR0_PPR05                         (0x0020u)
+
+#define GPIO_PMC0_PMC04                         (0x0010u)
+#define GPIO_PMC0_PMC05                         (0x0020u)
+
+#define GPIO_PMCSR0_PMCSR04                     (0x00000010uL)
+#define GPIO_PMCSR0_PMCSR05                     (0x00000020uL)
+
+#define GPIO_PIBC0_PIBC00                       (0x0001u)
+#define GPIO_PIBC0_PIBC01                       (0x0002u)
+#define GPIO_PIBC0_PIBC02                       (0x0004u)
+#define GPIO_PIBC0_PIBC03                       (0x0008u)
+#define GPIO_PIBC0_PIBC04                       (0x0010u)
+#define GPIO_PIBC0_PIBC05                       (0x0020u)
+
+/* ---- P1 ---- */
+#define GPIO_P1_P10                             (0x0001u)
+#define GPIO_P1_P11                             (0x0002u)
+#define GPIO_P1_P12                             (0x0004u)
+#define GPIO_P1_P13                             (0x0008u)
+#define GPIO_P1_P14                             (0x0010u)
+#define GPIO_P1_P15                             (0x0020u)
+#define GPIO_P1_P16                             (0x0040u)
+#define GPIO_P1_P17                             (0x0080u)
+
+#define GPIO_PSR1_PSR10                         (0x00000001uL)
+#define GPIO_PSR1_PSR11                         (0x00000002uL)
+#define GPIO_PSR1_PSR12                         (0x00000004uL)
+#define GPIO_PSR1_PSR13                         (0x00000008uL)
+#define GPIO_PSR1_PSR14                         (0x00000010uL)
+#define GPIO_PSR1_PSR15                         (0x00000020uL)
+#define GPIO_PSR1_PSR16                         (0x00000040uL)
+#define GPIO_PSR1_PSR17                         (0x00000080uL)
+#define GPIO_PSR1_PSR116                        (0x00010000uL)
+#define GPIO_PSR1_PSR117                        (0x00020000uL)
+#define GPIO_PSR1_PSR118                        (0x00040000uL)
+#define GPIO_PSR1_PSR119                        (0x00080000uL)
+#define GPIO_PSR1_PSR120                        (0x00100000uL)
+#define GPIO_PSR1_PSR121                        (0x00200000uL)
+#define GPIO_PSR1_PSR122                        (0x00400000uL)
+#define GPIO_PSR1_PSR123                        (0x00800000uL)
+
+#define GPIO_PPR1_PPR10                         (0x0001u)
+#define GPIO_PPR1_PPR11                         (0x0002u)
+#define GPIO_PPR1_PPR12                         (0x0004u)
+#define GPIO_PPR1_PPR13                         (0x0008u)
+#define GPIO_PPR1_PPR14                         (0x0010u)
+#define GPIO_PPR1_PPR15                         (0x0020u)
+#define GPIO_PPR1_PPR16                         (0x0040u)
+#define GPIO_PPR1_PPR17                         (0x0080u)
+#define GPIO_PPR1_PPR18                         (0x0100u)
+#define GPIO_PPR1_PPR19                         (0x0200u)
+#define GPIO_PPR1_PPR110                        (0x0400u)
+#define GPIO_PPR1_PPR111                        (0x0800u)
+#define GPIO_PPR1_PPR112                        (0x1000u)
+#define GPIO_PPR1_PPR113                        (0x2000u)
+#define GPIO_PPR1_PPR114                        (0x4000u)
+#define GPIO_PPR1_PPR115                        (0x8000u)
+
+#define GPIO_PM1_PM10                           (0x0001u)
+#define GPIO_PM1_PM11                           (0x0002u)
+#define GPIO_PM1_PM12                           (0x0004u)
+#define GPIO_PM1_PM13                           (0x0008u)
+#define GPIO_PM1_PM14                           (0x0010u)
+#define GPIO_PM1_PM15                           (0x0020u)
+#define GPIO_PM1_PM16                           (0x0040u)
+#define GPIO_PM1_PM17                           (0x0080u)
+
+#define GPIO_PMC1_PMC10                         (0x0001u)
+#define GPIO_PMC1_PMC11                         (0x0002u)
+#define GPIO_PMC1_PMC12                         (0x0004u)
+#define GPIO_PMC1_PMC13                         (0x0008u)
+#define GPIO_PMC1_PMC14                         (0x0010u)
+#define GPIO_PMC1_PMC15                         (0x0020u)
+#define GPIO_PMC1_PMC16                         (0x0040u)
+#define GPIO_PMC1_PMC17                         (0x0080u)
+#define GPIO_PMC1_PMC18                         (0x0100u)
+#define GPIO_PMC1_PMC19                         (0x0200u)
+#define GPIO_PMC1_PMC110                        (0x0400u)
+#define GPIO_PMC1_PMC111                        (0x0800u)
+#define GPIO_PMC1_PMC112                        (0x1000u)
+#define GPIO_PMC1_PMC113                        (0x2000u)
+#define GPIO_PMC1_PMC114                        (0x4000u)
+#define GPIO_PMC1_PMC115                        (0x8000u)
+
+#define GPIO_PFC1_PFC10                         (0x0001u)
+#define GPIO_PFC1_PFC11                         (0x0002u)
+#define GPIO_PFC1_PFC12                         (0x0004u)
+#define GPIO_PFC1_PFC13                         (0x0008u)
+#define GPIO_PFC1_PFC14                         (0x0010u)
+#define GPIO_PFC1_PFC15                         (0x0020u)
+#define GPIO_PFC1_PFC16                         (0x0040u)
+#define GPIO_PFC1_PFC17                         (0x0080u)
+#define GPIO_PFC1_PFC18                         (0x0100u)
+#define GPIO_PFC1_PFC19                         (0x0200u)
+#define GPIO_PFC1_PFC110                        (0x0400u)
+#define GPIO_PFC1_PFC111                        (0x0800u)
+#define GPIO_PFC1_PFC112                        (0x1000u)
+#define GPIO_PFC1_PFC113                        (0x2000u)
+#define GPIO_PFC1_PFC114                        (0x4000u)
+#define GPIO_PFC1_PFC115                        (0x8000u)
+
+#define GPIO_PFCE1_PFCE10                       (0x0001u)
+#define GPIO_PFCE1_PFCE11                       (0x0002u)
+#define GPIO_PFCE1_PFCE12                       (0x0004u)
+#define GPIO_PFCE1_PFCE13                       (0x0008u)
+#define GPIO_PFCE1_PFCE14                       (0x0010u)
+#define GPIO_PFCE1_PFCE15                       (0x0020u)
+#define GPIO_PFCE1_PFCE16                       (0x0040u)
+#define GPIO_PFCE1_PFCE17                       (0x0080u)
+#define GPIO_PFCE1_PFCE18                       (0x0100u)
+#define GPIO_PFCE1_PFCE19                       (0x0200u)
+#define GPIO_PFCE1_PFCE110                      (0x0400u)
+#define GPIO_PFCE1_PFCE111                      (0x0800u)
+#define GPIO_PFCE1_PFCE112                      (0x1000u)
+#define GPIO_PFCE1_PFCE113                      (0x2000u)
+#define GPIO_PFCE1_PFCE114                      (0x4000u)
+#define GPIO_PFCE1_PFCE115                      (0x8000u)
+
+#define GPIO_PNOT1_PNOT10                       (0x0001u)
+#define GPIO_PNOT1_PNOT11                       (0x0002u)
+#define GPIO_PNOT1_PNOT12                       (0x0004u)
+#define GPIO_PNOT1_PNOT13                       (0x0008u)
+#define GPIO_PNOT1_PNOT14                       (0x0010u)
+#define GPIO_PNOT1_PNOT15                       (0x0020u)
+#define GPIO_PNOT1_PNOT16                       (0x0040u)
+#define GPIO_PNOT1_PNOT17                       (0x0080u)
+
+#define GPIO_PMSR1_PMSR10                       (0x00000001uL)
+#define GPIO_PMSR1_PMSR11                       (0x00000002uL)
+#define GPIO_PMSR1_PMSR12                       (0x00000004uL)
+#define GPIO_PMSR1_PMSR13                       (0x00000008uL)
+#define GPIO_PMSR1_PMSR14                       (0x00000010uL)
+#define GPIO_PMSR1_PMSR15                       (0x00000020uL)
+#define GPIO_PMSR1_PMSR16                       (0x00000040uL)
+#define GPIO_PMSR1_PMSR17                       (0x00000080uL)
+#define GPIO_PMSR1_PMSR116                      (0x00010000uL)
+#define GPIO_PMSR1_PMSR117                      (0x00020000uL)
+#define GPIO_PMSR1_PMSR118                      (0x00040000uL)
+#define GPIO_PMSR1_PMSR119                      (0x00080000uL)
+#define GPIO_PMSR1_PMSR120                      (0x00100000uL)
+#define GPIO_PMSR1_PMSR121                      (0x00200000uL)
+#define GPIO_PMSR1_PMSR122                      (0x00400000uL)
+#define GPIO_PMSR1_PMSR123                      (0x00800000uL)
+
+#define GPIO_PMCSR1_PMCSR10                     (0x00000001uL)
+#define GPIO_PMCSR1_PMCSR11                     (0x00000002uL)
+#define GPIO_PMCSR1_PMCSR12                     (0x00000004uL)
+#define GPIO_PMCSR1_PMCSR13                     (0x00000008uL)
+#define GPIO_PMCSR1_PMCSR14                     (0x00000010uL)
+#define GPIO_PMCSR1_PMCSR15                     (0x00000020uL)
+#define GPIO_PMCSR1_PMCSR16                     (0x00000040uL)
+#define GPIO_PMCSR1_PMCSR17                     (0x00000080uL)
+#define GPIO_PMCSR1_PMCSR116                    (0x00010000uL)
+#define GPIO_PMCSR1_PMCSR117                    (0x00020000uL)
+#define GPIO_PMCSR1_PMCSR118                    (0x00040000uL)
+#define GPIO_PMCSR1_PMCSR119                    (0x00080000uL)
+#define GPIO_PMCSR1_PMCSR120                    (0x00100000uL)
+#define GPIO_PMCSR1_PMCSR121                    (0x00200000uL)
+#define GPIO_PMCSR1_PMCSR122                    (0x00400000uL)
+#define GPIO_PMCSR1_PMCSR123                    (0x00800000uL)
+
+#define GPIO_PFCAE1_PFCAE10                     (0x0001u)
+#define GPIO_PFCAE1_PFCAE11                     (0x0002u)
+#define GPIO_PFCAE1_PFCAE12                     (0x0004u)
+#define GPIO_PFCAE1_PFCAE13                     (0x0008u)
+#define GPIO_PFCAE1_PFCAE14                     (0x0010u)
+#define GPIO_PFCAE1_PFCAE15                     (0x0020u)
+#define GPIO_PFCAE1_PFCAE16                     (0x0040u)
+#define GPIO_PFCAE1_PFCAE17                     (0x0080u)
+#define GPIO_PFCAE1_PFCAE18                     (0x0100u)
+#define GPIO_PFCAE1_PFCAE19                     (0x0200u)
+#define GPIO_PFCAE1_PFCAE110                    (0x0400u)
+#define GPIO_PFCAE1_PFCAE111                    (0x0800u)
+#define GPIO_PFCAE1_PFCAE112                    (0x1000u)
+#define GPIO_PFCAE1_PFCAE113                    (0x2000u)
+#define GPIO_PFCAE1_PFCAE114                    (0x4000u)
+#define GPIO_PFCAE1_PFCAE115                    (0x8000u)
+
+#define GPIO_PIBC1_PIBC10                       (0x0001u)
+#define GPIO_PIBC1_PIBC11                       (0x0002u)
+#define GPIO_PIBC1_PIBC12                       (0x0004u)
+#define GPIO_PIBC1_PIBC13                       (0x0008u)
+#define GPIO_PIBC1_PIBC14                       (0x0010u)
+#define GPIO_PIBC1_PIBC15                       (0x0020u)
+#define GPIO_PIBC1_PIBC16                       (0x0040u)
+#define GPIO_PIBC1_PIBC17                       (0x0080u)
+#define GPIO_PIBC1_PIBC18                       (0x0100u)
+#define GPIO_PIBC1_PIBC19                       (0x0200u)
+#define GPIO_PIBC1_PIBC110                      (0x0400u)
+#define GPIO_PIBC1_PIBC111                      (0x0800u)
+#define GPIO_PIBC1_PIBC112                      (0x1000u)
+#define GPIO_PIBC1_PIBC113                      (0x2000u)
+#define GPIO_PIBC1_PIBC114                      (0x4000u)
+#define GPIO_PIBC1_PIBC115                      (0x8000u)
+
+#define GPIO_PBDC1_PBDC10                       (0x0001u)
+#define GPIO_PBDC1_PBDC11                       (0x0002u)
+#define GPIO_PBDC1_PBDC12                       (0x0004u)
+#define GPIO_PBDC1_PBDC13                       (0x0008u)
+#define GPIO_PBDC1_PBDC14                       (0x0010u)
+#define GPIO_PBDC1_PBDC15                       (0x0020u)
+#define GPIO_PBDC1_PBDC16                       (0x0040u)
+#define GPIO_PBDC1_PBDC17                       (0x0080u)
+#define GPIO_PBDC1_PBDC18                       (0x0100u)
+#define GPIO_PBDC1_PBDC19                       (0x0200u)
+#define GPIO_PBDC1_PBDC110                      (0x0400u)
+#define GPIO_PBDC1_PBDC111                      (0x0800u)
+#define GPIO_PBDC1_PBDC112                      (0x1000u)
+#define GPIO_PBDC1_PBDC113                      (0x2000u)
+#define GPIO_PBDC1_PBDC114                      (0x4000u)
+#define GPIO_PBDC1_PBDC115                      (0x8000u)
+
+#define GPIO_PIPC1_PIPC10                       (0x0001u)
+#define GPIO_PIPC1_PIPC11                       (0x0002u)
+#define GPIO_PIPC1_PIPC12                       (0x0004u)
+#define GPIO_PIPC1_PIPC13                       (0x0008u)
+#define GPIO_PIPC1_PIPC14                       (0x0010u)
+#define GPIO_PIPC1_PIPC15                       (0x0020u)
+#define GPIO_PIPC1_PIPC16                       (0x0040u)
+#define GPIO_PIPC1_PIPC17                       (0x0080u)
+
+/* ---- P2 ---- */
+#define GPIO_P2_P20                             (0x0001u)
+#define GPIO_P2_P21                             (0x0002u)
+#define GPIO_P2_P22                             (0x0004u)
+#define GPIO_P2_P23                             (0x0008u)
+#define GPIO_P2_P24                             (0x0010u)
+#define GPIO_P2_P25                             (0x0020u)
+#define GPIO_P2_P26                             (0x0040u)
+#define GPIO_P2_P27                             (0x0080u)
+#define GPIO_P2_P28                             (0x0100u)
+#define GPIO_P2_P29                             (0x0200u)
+#define GPIO_P2_P210                            (0x0400u)
+#define GPIO_P2_P211                            (0x0800u)
+#define GPIO_P2_P212                            (0x1000u)
+#define GPIO_P2_P213                            (0x2000u)
+#define GPIO_P2_P214                            (0x4000u)
+#define GPIO_P2_P215                            (0x8000u)
+
+#define GPIO_PSR2_PSR20                         (0x00000001uL)
+#define GPIO_PSR2_PSR21                         (0x00000002uL)
+#define GPIO_PSR2_PSR22                         (0x00000004uL)
+#define GPIO_PSR2_PSR23                         (0x00000008uL)
+#define GPIO_PSR2_PSR24                         (0x00000010uL)
+#define GPIO_PSR2_PSR25                         (0x00000020uL)
+#define GPIO_PSR2_PSR26                         (0x00000040uL)
+#define GPIO_PSR2_PSR27                         (0x00000080uL)
+#define GPIO_PSR2_PSR28                         (0x00000100uL)
+#define GPIO_PSR2_PSR29                         (0x00000200uL)
+#define GPIO_PSR2_PSR210                        (0x00000400uL)
+#define GPIO_PSR2_PSR211                        (0x00000800uL)
+#define GPIO_PSR2_PSR212                        (0x00001000uL)
+#define GPIO_PSR2_PSR213                        (0x00002000uL)
+#define GPIO_PSR2_PSR214                        (0x00004000uL)
+#define GPIO_PSR2_PSR215                        (0x00008000uL)
+#define GPIO_PSR2_PSR216                        (0x00010000uL)
+#define GPIO_PSR2_PSR217                        (0x00020000uL)
+#define GPIO_PSR2_PSR218                        (0x00040000uL)
+#define GPIO_PSR2_PSR219                        (0x00080000uL)
+#define GPIO_PSR2_PSR220                        (0x00100000uL)
+#define GPIO_PSR2_PSR221                        (0x00200000uL)
+#define GPIO_PSR2_PSR222                        (0x00400000uL)
+#define GPIO_PSR2_PSR223                        (0x00800000uL)
+#define GPIO_PSR2_PSR224                        (0x01000000uL)
+#define GPIO_PSR2_PSR225                        (0x02000000uL)
+#define GPIO_PSR2_PSR226                        (0x04000000uL)
+#define GPIO_PSR2_PSR227                        (0x08000000uL)
+#define GPIO_PSR2_PSR228                        (0x10000000uL)
+#define GPIO_PSR2_PSR229                        (0x20000000uL)
+#define GPIO_PSR2_PSR230                        (0x40000000uL)
+#define GPIO_PSR2_PSR231                        (0x80000000uL)
+
+#define GPIO_PPR2_PPR20                         (0x0001u)
+#define GPIO_PPR2_PPR21                         (0x0002u)
+#define GPIO_PPR2_PPR22                         (0x0004u)
+#define GPIO_PPR2_PPR23                         (0x0008u)
+#define GPIO_PPR2_PPR24                         (0x0010u)
+#define GPIO_PPR2_PPR25                         (0x0020u)
+#define GPIO_PPR2_PPR26                         (0x0040u)
+#define GPIO_PPR2_PPR27                         (0x0080u)
+#define GPIO_PPR2_PPR28                         (0x0100u)
+#define GPIO_PPR2_PPR29                         (0x0200u)
+#define GPIO_PPR2_PPR210                        (0x0400u)
+#define GPIO_PPR2_PPR211                        (0x0800u)
+#define GPIO_PPR2_PPR212                        (0x1000u)
+#define GPIO_PPR2_PPR213                        (0x2000u)
+#define GPIO_PPR2_PPR214                        (0x4000u)
+#define GPIO_PPR2_PPR215                        (0x8000u)
+
+#define GPIO_PM2_PM20                           (0x0001u)
+#define GPIO_PM2_PM21                           (0x0002u)
+#define GPIO_PM2_PM22                           (0x0004u)
+#define GPIO_PM2_PM23                           (0x0008u)
+#define GPIO_PM2_PM24                           (0x0010u)
+#define GPIO_PM2_PM25                           (0x0020u)
+#define GPIO_PM2_PM26                           (0x0040u)
+#define GPIO_PM2_PM27                           (0x0080u)
+#define GPIO_PM2_PM28                           (0x0100u)
+#define GPIO_PM2_PM29                           (0x0200u)
+#define GPIO_PM2_PM210                          (0x0400u)
+#define GPIO_PM2_PM211                          (0x0800u)
+#define GPIO_PM2_PM212                          (0x1000u)
+#define GPIO_PM2_PM213                          (0x2000u)
+#define GPIO_PM2_PM214                          (0x4000u)
+#define GPIO_PM2_PM215                          (0x8000u)
+
+#define GPIO_PMC2_PMC20                         (0x0001u)
+#define GPIO_PMC2_PMC21                         (0x0002u)
+#define GPIO_PMC2_PMC22                         (0x0004u)
+#define GPIO_PMC2_PMC23                         (0x0008u)
+#define GPIO_PMC2_PMC24                         (0x0010u)
+#define GPIO_PMC2_PMC25                         (0x0020u)
+#define GPIO_PMC2_PMC26                         (0x0040u)
+#define GPIO_PMC2_PMC27                         (0x0080u)
+#define GPIO_PMC2_PMC28                         (0x0100u)
+#define GPIO_PMC2_PMC29                         (0x0200u)
+#define GPIO_PMC2_PMC210                        (0x0400u)
+#define GPIO_PMC2_PMC211                        (0x0800u)
+#define GPIO_PMC2_PMC212                        (0x1000u)
+#define GPIO_PMC2_PMC213                        (0x2000u)
+#define GPIO_PMC2_PMC214                        (0x4000u)
+#define GPIO_PMC2_PMC215                        (0x8000u)
+
+#define GPIO_PFC2_PFC20                         (0x0001u)
+#define GPIO_PFC2_PFC21                         (0x0002u)
+#define GPIO_PFC2_PFC22                         (0x0004u)
+#define GPIO_PFC2_PFC23                         (0x0008u)
+#define GPIO_PFC2_PFC24                         (0x0010u)
+#define GPIO_PFC2_PFC25                         (0x0020u)
+#define GPIO_PFC2_PFC26                         (0x0040u)
+#define GPIO_PFC2_PFC27                         (0x0080u)
+#define GPIO_PFC2_PFC28                         (0x0100u)
+#define GPIO_PFC2_PFC29                         (0x0200u)
+#define GPIO_PFC2_PFC210                        (0x0400u)
+#define GPIO_PFC2_PFC211                        (0x0800u)
+#define GPIO_PFC2_PFC212                        (0x1000u)
+#define GPIO_PFC2_PFC213                        (0x2000u)
+#define GPIO_PFC2_PFC214                        (0x4000u)
+#define GPIO_PFC2_PFC215                        (0x8000u)
+
+#define GPIO_PFCE2_PFCE20                       (0x0001u)
+#define GPIO_PFCE2_PFCE21                       (0x0002u)
+#define GPIO_PFCE2_PFCE22                       (0x0004u)
+#define GPIO_PFCE2_PFCE23                       (0x0008u)
+#define GPIO_PFCE2_PFCE24                       (0x0010u)
+#define GPIO_PFCE2_PFCE25                       (0x0020u)
+#define GPIO_PFCE2_PFCE26                       (0x0040u)
+#define GPIO_PFCE2_PFCE27                       (0x0080u)
+#define GPIO_PFCE2_PFCE28                       (0x0100u)
+#define GPIO_PFCE2_PFCE29                       (0x0200u)
+#define GPIO_PFCE2_PFCE210                      (0x0400u)
+#define GPIO_PFCE2_PFCE211                      (0x0800u)
+#define GPIO_PFCE2_PFCE212                      (0x1000u)
+#define GPIO_PFCE2_PFCE213                      (0x2000u)
+#define GPIO_PFCE2_PFCE214                      (0x4000u)
+#define GPIO_PFCE2_PFCE215                      (0x8000u)
+
+#define GPIO_PNOT2_PNOT20                       (0x0001u)
+#define GPIO_PNOT2_PNOT21                       (0x0002u)
+#define GPIO_PNOT2_PNOT22                       (0x0004u)
+#define GPIO_PNOT2_PNOT23                       (0x0008u)
+#define GPIO_PNOT2_PNOT24                       (0x0010u)
+#define GPIO_PNOT2_PNOT25                       (0x0020u)
+#define GPIO_PNOT2_PNOT26                       (0x0040u)
+#define GPIO_PNOT2_PNOT27                       (0x0080u)
+#define GPIO_PNOT2_PNOT28                       (0x0100u)
+#define GPIO_PNOT2_PNOT29                       (0x0200u)
+#define GPIO_PNOT2_PNOT210                      (0x0400u)
+#define GPIO_PNOT2_PNOT211                      (0x0800u)
+#define GPIO_PNOT2_PNOT212                      (0x1000u)
+#define GPIO_PNOT2_PNOT213                      (0x2000u)
+#define GPIO_PNOT2_PNOT214                      (0x4000u)
+#define GPIO_PNOT2_PNOT215                      (0x8000u)
+
+#define GPIO_PMSR2_PMSR20                       (0x00000001uL)
+#define GPIO_PMSR2_PMSR21                       (0x00000002uL)
+#define GPIO_PMSR2_PMSR22                       (0x00000004uL)
+#define GPIO_PMSR2_PMSR23                       (0x00000008uL)
+#define GPIO_PMSR2_PMSR24                       (0x00000010uL)
+#define GPIO_PMSR2_PMSR25                       (0x00000020uL)
+#define GPIO_PMSR2_PMSR26                       (0x00000040uL)
+#define GPIO_PMSR2_PMSR27                       (0x00000080uL)
+#define GPIO_PMSR2_PMSR28                       (0x00000100uL)
+#define GPIO_PMSR2_PMSR29                       (0x00000200uL)
+#define GPIO_PMSR2_PMSR210                      (0x00000400uL)
+#define GPIO_PMSR2_PMSR211                      (0x00000800uL)
+#define GPIO_PMSR2_PMSR212                      (0x00001000uL)
+#define GPIO_PMSR2_PMSR213                      (0x00002000uL)
+#define GPIO_PMSR2_PMSR214                      (0x00004000uL)
+#define GPIO_PMSR2_PMSR215                      (0x00008000uL)
+#define GPIO_PMSR2_PMSR216                      (0x00010000uL)
+#define GPIO_PMSR2_PMSR217                      (0x00020000uL)
+#define GPIO_PMSR2_PMSR218                      (0x00040000uL)
+#define GPIO_PMSR2_PMSR219                      (0x00080000uL)
+#define GPIO_PMSR2_PMSR220                      (0x00100000uL)
+#define GPIO_PMSR2_PMSR221                      (0x00200000uL)
+#define GPIO_PMSR2_PMSR222                      (0x00400000uL)
+#define GPIO_PMSR2_PMSR223                      (0x00800000uL)
+#define GPIO_PMSR2_PMSR224                      (0x01000000uL)
+#define GPIO_PMSR2_PMSR225                      (0x02000000uL)
+#define GPIO_PMSR2_PMSR226                      (0x04000000uL)
+#define GPIO_PMSR2_PMSR227                      (0x08000000uL)
+#define GPIO_PMSR2_PMSR228                      (0x10000000uL)
+#define GPIO_PMSR2_PMSR229                      (0x20000000uL)
+#define GPIO_PMSR2_PMSR230                      (0x40000000uL)
+#define GPIO_PMSR2_PMSR231                      (0x80000000uL)
+
+#define GPIO_PMCSR2_PMCSR20                     (0x00000001uL)
+#define GPIO_PMCSR2_PMCSR21                     (0x00000002uL)
+#define GPIO_PMCSR2_PMCSR22                     (0x00000004uL)
+#define GPIO_PMCSR2_PMCSR23                     (0x00000008uL)
+#define GPIO_PMCSR2_PMCSR24                     (0x00000010uL)
+#define GPIO_PMCSR2_PMCSR25                     (0x00000020uL)
+#define GPIO_PMCSR2_PMCSR26                     (0x00000040uL)
+#define GPIO_PMCSR2_PMCSR27                     (0x00000080uL)
+#define GPIO_PMCSR2_PMCSR28                     (0x00000100uL)
+#define GPIO_PMCSR2_PMCSR29                     (0x00000200uL)
+#define GPIO_PMCSR2_PMCSR210                    (0x00000400uL)
+#define GPIO_PMCSR2_PMCSR211                    (0x00000800uL)
+#define GPIO_PMCSR2_PMCSR212                    (0x00001000uL)
+#define GPIO_PMCSR2_PMCSR213                    (0x00002000uL)
+#define GPIO_PMCSR2_PMCSR214                    (0x00004000uL)
+#define GPIO_PMCSR2_PMCSR215                    (0x00008000uL)
+#define GPIO_PMCSR2_PMCSR216                    (0x00010000uL)
+#define GPIO_PMCSR2_PMCSR217                    (0x00020000uL)
+#define GPIO_PMCSR2_PMCSR218                    (0x00040000uL)
+#define GPIO_PMCSR2_PMCSR219                    (0x00080000uL)
+#define GPIO_PMCSR2_PMCSR220                    (0x00100000uL)
+#define GPIO_PMCSR2_PMCSR221                    (0x00200000uL)
+#define GPIO_PMCSR2_PMCSR222                    (0x00400000uL)
+#define GPIO_PMCSR2_PMCSR223                    (0x00800000uL)
+#define GPIO_PMCSR2_PMCSR224                    (0x01000000uL)
+#define GPIO_PMCSR2_PMCSR225                    (0x02000000uL)
+#define GPIO_PMCSR2_PMCSR226                    (0x04000000uL)
+#define GPIO_PMCSR2_PMCSR227                    (0x08000000uL)
+#define GPIO_PMCSR2_PMCSR228                    (0x10000000uL)
+#define GPIO_PMCSR2_PMCSR229                    (0x20000000uL)
+#define GPIO_PMCSR2_PMCSR230                    (0x40000000uL)
+#define GPIO_PMCSR2_PMCSR231                    (0x80000000uL)
+
+#define GPIO_PFCAE2_PFCAE20                     (0x0001u)
+#define GPIO_PFCAE2_PFCAE21                     (0x0002u)
+#define GPIO_PFCAE2_PFCAE22                     (0x0004u)
+#define GPIO_PFCAE2_PFCAE23                     (0x0008u)
+#define GPIO_PFCAE2_PFCAE24                     (0x0010u)
+#define GPIO_PFCAE2_PFCAE25                     (0x0020u)
+#define GPIO_PFCAE2_PFCAE26                     (0x0040u)
+#define GPIO_PFCAE2_PFCAE27                     (0x0080u)
+#define GPIO_PFCAE2_PFCAE28                     (0x0100u)
+#define GPIO_PFCAE2_PFCAE29                     (0x0200u)
+#define GPIO_PFCAE2_PFCAE210                    (0x0400u)
+#define GPIO_PFCAE2_PFCAE211                    (0x0800u)
+#define GPIO_PFCAE2_PFCAE212                    (0x1000u)
+#define GPIO_PFCAE2_PFCAE213                    (0x2000u)
+#define GPIO_PFCAE2_PFCAE214                    (0x4000u)
+#define GPIO_PFCAE2_PFCAE215                    (0x8000u)
+
+#define GPIO_PIBC2_PIBC20                       (0x0001u)
+#define GPIO_PIBC2_PIBC21                       (0x0002u)
+#define GPIO_PIBC2_PIBC22                       (0x0004u)
+#define GPIO_PIBC2_PIBC23                       (0x0008u)
+#define GPIO_PIBC2_PIBC24                       (0x0010u)
+#define GPIO_PIBC2_PIBC25                       (0x0020u)
+#define GPIO_PIBC2_PIBC26                       (0x0040u)
+#define GPIO_PIBC2_PIBC27                       (0x0080u)
+#define GPIO_PIBC2_PIBC28                       (0x0100u)
+#define GPIO_PIBC2_PIBC29                       (0x0200u)
+#define GPIO_PIBC2_PIBC210                      (0x0400u)
+#define GPIO_PIBC2_PIBC211                      (0x0800u)
+#define GPIO_PIBC2_PIBC212                      (0x1000u)
+#define GPIO_PIBC2_PIBC213                      (0x2000u)
+#define GPIO_PIBC2_PIBC214                      (0x4000u)
+#define GPIO_PIBC2_PIBC215                      (0x8000u)
+
+#define GPIO_PBDC2_PBDC20                       (0x0001u)
+#define GPIO_PBDC2_PBDC21                       (0x0002u)
+#define GPIO_PBDC2_PBDC22                       (0x0004u)
+#define GPIO_PBDC2_PBDC23                       (0x0008u)
+#define GPIO_PBDC2_PBDC24                       (0x0010u)
+#define GPIO_PBDC2_PBDC25                       (0x0020u)
+#define GPIO_PBDC2_PBDC26                       (0x0040u)
+#define GPIO_PBDC2_PBDC27                       (0x0080u)
+#define GPIO_PBDC2_PBDC28                       (0x0100u)
+#define GPIO_PBDC2_PBDC29                       (0x0200u)
+#define GPIO_PBDC2_PBDC210                      (0x0400u)
+#define GPIO_PBDC2_PBDC211                      (0x0800u)
+#define GPIO_PBDC2_PBDC212                      (0x1000u)
+#define GPIO_PBDC2_PBDC213                      (0x2000u)
+#define GPIO_PBDC2_PBDC214                      (0x4000u)
+#define GPIO_PBDC2_PBDC215                      (0x8000u)
+
+#define GPIO_PIPC2_PIPC20                       (0x0001u)
+#define GPIO_PIPC2_PIPC21                       (0x0002u)
+#define GPIO_PIPC2_PIPC22                       (0x0004u)
+#define GPIO_PIPC2_PIPC23                       (0x0008u)
+#define GPIO_PIPC2_PIPC24                       (0x0010u)
+#define GPIO_PIPC2_PIPC25                       (0x0020u)
+#define GPIO_PIPC2_PIPC26                       (0x0040u)
+#define GPIO_PIPC2_PIPC27                       (0x0080u)
+#define GPIO_PIPC2_PIPC28                       (0x0100u)
+#define GPIO_PIPC2_PIPC29                       (0x0200u)
+#define GPIO_PIPC2_PIPC210                      (0x0400u)
+#define GPIO_PIPC2_PIPC211                      (0x0800u)
+#define GPIO_PIPC2_PIPC212                      (0x1000u)
+#define GPIO_PIPC2_PIPC213                      (0x2000u)
+#define GPIO_PIPC2_PIPC214                      (0x4000u)
+#define GPIO_PIPC2_PIPC215                      (0x8000u)
+
+/* ---- P3 ---- */
+#define GPIO_P3_P30                             (0x0001u)
+#define GPIO_P3_P31                             (0x0002u)
+#define GPIO_P3_P32                             (0x0004u)
+#define GPIO_P3_P33                             (0x0008u)
+#define GPIO_P3_P34                             (0x0010u)
+#define GPIO_P3_P35                             (0x0020u)
+#define GPIO_P3_P36                             (0x0040u)
+#define GPIO_P3_P37                             (0x0080u)
+#define GPIO_P3_P38                             (0x0100u)
+#define GPIO_P3_P39                             (0x0200u)
+#define GPIO_P3_P310                            (0x0400u)
+#define GPIO_P3_P311                            (0x0800u)
+#define GPIO_P3_P312                            (0x1000u)
+#define GPIO_P3_P313                            (0x2000u)
+#define GPIO_P3_P314                            (0x4000u)
+#define GPIO_P3_P315                            (0x8000u)
+
+#define GPIO_PSR3_PSR30                         (0x00000001uL)
+#define GPIO_PSR3_PSR31                         (0x00000002uL)
+#define GPIO_PSR3_PSR32                         (0x00000004uL)
+#define GPIO_PSR3_PSR33                         (0x00000008uL)
+#define GPIO_PSR3_PSR34                         (0x00000010uL)
+#define GPIO_PSR3_PSR35                         (0x00000020uL)
+#define GPIO_PSR3_PSR36                         (0x00000040uL)
+#define GPIO_PSR3_PSR37                         (0x00000080uL)
+#define GPIO_PSR3_PSR38                         (0x00000100uL)
+#define GPIO_PSR3_PSR39                         (0x00000200uL)
+#define GPIO_PSR3_PSR310                        (0x00000400uL)
+#define GPIO_PSR3_PSR311                        (0x00000800uL)
+#define GPIO_PSR3_PSR312                        (0x00001000uL)
+#define GPIO_PSR3_PSR313                        (0x00002000uL)
+#define GPIO_PSR3_PSR314                        (0x00004000uL)
+#define GPIO_PSR3_PSR315                        (0x00008000uL)
+#define GPIO_PSR3_PSR316                        (0x00010000uL)
+#define GPIO_PSR3_PSR317                        (0x00020000uL)
+#define GPIO_PSR3_PSR318                        (0x00040000uL)
+#define GPIO_PSR3_PSR319                        (0x00080000uL)
+#define GPIO_PSR3_PSR320                        (0x00100000uL)
+#define GPIO_PSR3_PSR321                        (0x00200000uL)
+#define GPIO_PSR3_PSR322                        (0x00400000uL)
+#define GPIO_PSR3_PSR323                        (0x00800000uL)
+#define GPIO_PSR3_PSR324                        (0x01000000uL)
+#define GPIO_PSR3_PSR325                        (0x02000000uL)
+#define GPIO_PSR3_PSR326                        (0x04000000uL)
+#define GPIO_PSR3_PSR327                        (0x08000000uL)
+#define GPIO_PSR3_PSR328                        (0x10000000uL)
+#define GPIO_PSR3_PSR329                        (0x20000000uL)
+#define GPIO_PSR3_PSR330                        (0x40000000uL)
+#define GPIO_PSR3_PSR331                        (0x80000000uL)
+
+#define GPIO_PPR3_PPR30                         (0x0001u)
+#define GPIO_PPR3_PPR31                         (0x0002u)
+#define GPIO_PPR3_PPR32                         (0x0004u)
+#define GPIO_PPR3_PPR33                         (0x0008u)
+#define GPIO_PPR3_PPR34                         (0x0010u)
+#define GPIO_PPR3_PPR35                         (0x0020u)
+#define GPIO_PPR3_PPR36                         (0x0040u)
+#define GPIO_PPR3_PPR37                         (0x0080u)
+#define GPIO_PPR3_PPR38                         (0x0100u)
+#define GPIO_PPR3_PPR39                         (0x0200u)
+#define GPIO_PPR3_PPR310                        (0x0400u)
+#define GPIO_PPR3_PPR311                        (0x0800u)
+#define GPIO_PPR3_PPR312                        (0x1000u)
+#define GPIO_PPR3_PPR313                        (0x2000u)
+#define GPIO_PPR3_PPR314                        (0x4000u)
+#define GPIO_PPR3_PPR315                        (0x8000u)
+
+#define GPIO_PM3_PM30                           (0x0001u)
+#define GPIO_PM3_PM31                           (0x0002u)
+#define GPIO_PM3_PM32                           (0x0004u)
+#define GPIO_PM3_PM33                           (0x0008u)
+#define GPIO_PM3_PM34                           (0x0010u)
+#define GPIO_PM3_PM35                           (0x0020u)
+#define GPIO_PM3_PM36                           (0x0040u)
+#define GPIO_PM3_PM37                           (0x0080u)
+#define GPIO_PM3_PM38                           (0x0100u)
+#define GPIO_PM3_PM39                           (0x0200u)
+#define GPIO_PM3_PM310                          (0x0400u)
+#define GPIO_PM3_PM311                          (0x0800u)
+#define GPIO_PM3_PM312                          (0x1000u)
+#define GPIO_PM3_PM313                          (0x2000u)
+#define GPIO_PM3_PM314                          (0x4000u)
+#define GPIO_PM3_PM315                          (0x8000u)
+
+#define GPIO_PMC3_PMC30                         (0x0001u)
+#define GPIO_PMC3_PMC31                         (0x0002u)
+#define GPIO_PMC3_PMC32                         (0x0004u)
+#define GPIO_PMC3_PMC33                         (0x0008u)
+#define GPIO_PMC3_PMC34                         (0x0010u)
+#define GPIO_PMC3_PMC35                         (0x0020u)
+#define GPIO_PMC3_PMC36                         (0x0040u)
+#define GPIO_PMC3_PMC37                         (0x0080u)
+#define GPIO_PMC3_PMC38                         (0x0100u)
+#define GPIO_PMC3_PMC39                         (0x0200u)
+#define GPIO_PMC3_PMC310                        (0x0400u)
+#define GPIO_PMC3_PMC311                        (0x0800u)
+#define GPIO_PMC3_PMC312                        (0x1000u)
+#define GPIO_PMC3_PMC313                        (0x2000u)
+#define GPIO_PMC3_PMC314                        (0x4000u)
+#define GPIO_PMC3_PMC315                        (0x8000u)
+
+#define GPIO_PFC3_PFC30                         (0x0001u)
+#define GPIO_PFC3_PFC31                         (0x0002u)
+#define GPIO_PFC3_PFC32                         (0x0004u)
+#define GPIO_PFC3_PFC33                         (0x0008u)
+#define GPIO_PFC3_PFC34                         (0x0010u)
+#define GPIO_PFC3_PFC35                         (0x0020u)
+#define GPIO_PFC3_PFC36                         (0x0040u)
+#define GPIO_PFC3_PFC37                         (0x0080u)
+#define GPIO_PFC3_PFC38                         (0x0100u)
+#define GPIO_PFC3_PFC39                         (0x0200u)
+#define GPIO_PFC3_PFC310                        (0x0400u)
+#define GPIO_PFC3_PFC311                        (0x0800u)
+#define GPIO_PFC3_PFC312                        (0x1000u)
+#define GPIO_PFC3_PFC313                        (0x2000u)
+#define GPIO_PFC3_PFC314                        (0x4000u)
+#define GPIO_PFC3_PFC315                        (0x8000u)
+
+#define GPIO_PFCE3_PFCE30                       (0x0001u)
+#define GPIO_PFCE3_PFCE31                       (0x0002u)
+#define GPIO_PFCE3_PFCE32                       (0x0004u)
+#define GPIO_PFCE3_PFCE33                       (0x0008u)
+#define GPIO_PFCE3_PFCE34                       (0x0010u)
+#define GPIO_PFCE3_PFCE35                       (0x0020u)
+#define GPIO_PFCE3_PFCE36                       (0x0040u)
+#define GPIO_PFCE3_PFCE37                       (0x0080u)
+#define GPIO_PFCE3_PFCE38                       (0x0100u)
+#define GPIO_PFCE3_PFCE39                       (0x0200u)
+#define GPIO_PFCE3_PFCE310                      (0x0400u)
+#define GPIO_PFCE3_PFCE311                      (0x0800u)
+#define GPIO_PFCE3_PFCE312                      (0x1000u)
+#define GPIO_PFCE3_PFCE313                      (0x2000u)
+#define GPIO_PFCE3_PFCE314                      (0x4000u)
+#define GPIO_PFCE3_PFCE315                      (0x8000u)
+
+#define GPIO_PNOT3_PNOT30                       (0x0001u)
+#define GPIO_PNOT3_PNOT31                       (0x0002u)
+#define GPIO_PNOT3_PNOT32                       (0x0004u)
+#define GPIO_PNOT3_PNOT33                       (0x0008u)
+#define GPIO_PNOT3_PNOT34                       (0x0010u)
+#define GPIO_PNOT3_PNOT35                       (0x0020u)
+#define GPIO_PNOT3_PNOT36                       (0x0040u)
+#define GPIO_PNOT3_PNOT37                       (0x0080u)
+#define GPIO_PNOT3_PNOT38                       (0x0100u)
+#define GPIO_PNOT3_PNOT39                       (0x0200u)
+#define GPIO_PNOT3_PNOT310                      (0x0400u)
+#define GPIO_PNOT3_PNOT311                      (0x0800u)
+#define GPIO_PNOT3_PNOT312                      (0x1000u)
+#define GPIO_PNOT3_PNOT313                      (0x2000u)
+#define GPIO_PNOT3_PNOT314                      (0x4000u)
+#define GPIO_PNOT3_PNOT315                      (0x8000u)
+
+#define GPIO_PMSR3_PMSR30                       (0x00000001uL)
+#define GPIO_PMSR3_PMSR31                       (0x00000002uL)
+#define GPIO_PMSR3_PMSR32                       (0x00000004uL)
+#define GPIO_PMSR3_PMSR33                       (0x00000008uL)
+#define GPIO_PMSR3_PMSR34                       (0x00000010uL)
+#define GPIO_PMSR3_PMSR35                       (0x00000020uL)
+#define GPIO_PMSR3_PMSR36                       (0x00000040uL)
+#define GPIO_PMSR3_PMSR37                       (0x00000080uL)
+#define GPIO_PMSR3_PMSR38                       (0x00000100uL)
+#define GPIO_PMSR3_PMSR39                       (0x00000200uL)
+#define GPIO_PMSR3_PMSR310                      (0x00000400uL)
+#define GPIO_PMSR3_PMSR311                      (0x00000800uL)
+#define GPIO_PMSR3_PMSR312                      (0x00001000uL)
+#define GPIO_PMSR3_PMSR313                      (0x00002000uL)
+#define GPIO_PMSR3_PMSR314                      (0x00004000uL)
+#define GPIO_PMSR3_PMSR315                      (0x00008000uL)
+#define GPIO_PMSR3_PMSR316                      (0x00010000uL)
+#define GPIO_PMSR3_PMSR317                      (0x00020000uL)
+#define GPIO_PMSR3_PMSR318                      (0x00040000uL)
+#define GPIO_PMSR3_PMSR319                      (0x00080000uL)
+#define GPIO_PMSR3_PMSR320                      (0x00100000uL)
+#define GPIO_PMSR3_PMSR321                      (0x00200000uL)
+#define GPIO_PMSR3_PMSR322                      (0x00400000uL)
+#define GPIO_PMSR3_PMSR323                      (0x00800000uL)
+#define GPIO_PMSR3_PMSR324                      (0x01000000uL)
+#define GPIO_PMSR3_PMSR325                      (0x02000000uL)
+#define GPIO_PMSR3_PMSR326                      (0x04000000uL)
+#define GPIO_PMSR3_PMSR327                      (0x08000000uL)
+#define GPIO_PMSR3_PMSR328                      (0x10000000uL)
+#define GPIO_PMSR3_PMSR329                      (0x20000000uL)
+#define GPIO_PMSR3_PMSR330                      (0x40000000uL)
+#define GPIO_PMSR3_PMSR331                      (0x80000000uL)
+
+#define GPIO_PMCSR3_PMCSR30                     (0x00000001uL)
+#define GPIO_PMCSR3_PMCSR31                     (0x00000002uL)
+#define GPIO_PMCSR3_PMCSR32                     (0x00000004uL)
+#define GPIO_PMCSR3_PMCSR33                     (0x00000008uL)
+#define GPIO_PMCSR3_PMCSR34                     (0x00000010uL)
+#define GPIO_PMCSR3_PMCSR35                     (0x00000020uL)
+#define GPIO_PMCSR3_PMCSR36                     (0x00000040uL)
+#define GPIO_PMCSR3_PMCSR37                     (0x00000080uL)
+#define GPIO_PMCSR3_PMCSR38                     (0x00000100uL)
+#define GPIO_PMCSR3_PMCSR39                     (0x00000200uL)
+#define GPIO_PMCSR3_PMCSR310                    (0x00000400uL)
+#define GPIO_PMCSR3_PMCSR311                    (0x00000800uL)
+#define GPIO_PMCSR3_PMCSR312                    (0x00001000uL)
+#define GPIO_PMCSR3_PMCSR313                    (0x00002000uL)
+#define GPIO_PMCSR3_PMCSR314                    (0x00004000uL)
+#define GPIO_PMCSR3_PMCSR315                    (0x00008000uL)
+#define GPIO_PMCSR3_PMCSR316                    (0x00010000uL)
+#define GPIO_PMCSR3_PMCSR317                    (0x00020000uL)
+#define GPIO_PMCSR3_PMCSR318                    (0x00040000uL)
+#define GPIO_PMCSR3_PMCSR319                    (0x00080000uL)
+#define GPIO_PMCSR3_PMCSR320                    (0x00100000uL)
+#define GPIO_PMCSR3_PMCSR321                    (0x00200000uL)
+#define GPIO_PMCSR3_PMCSR322                    (0x00400000uL)
+#define GPIO_PMCSR3_PMCSR323                    (0x00800000uL)
+#define GPIO_PMCSR3_PMCSR324                    (0x01000000uL)
+#define GPIO_PMCSR3_PMCSR325                    (0x02000000uL)
+#define GPIO_PMCSR3_PMCSR326                    (0x04000000uL)
+#define GPIO_PMCSR3_PMCSR327                    (0x08000000uL)
+#define GPIO_PMCSR3_PMCSR328                    (0x10000000uL)
+#define GPIO_PMCSR3_PMCSR329                    (0x20000000uL)
+#define GPIO_PMCSR3_PMCSR330                    (0x40000000uL)
+#define GPIO_PMCSR3_PMCSR331                    (0x80000000uL)
+
+#define GPIO_PFCAE3_PFCAE30                     (0x0001u)
+#define GPIO_PFCAE3_PFCAE31                     (0x0002u)
+#define GPIO_PFCAE3_PFCAE32                     (0x0004u)
+#define GPIO_PFCAE3_PFCAE33                     (0x0008u)
+#define GPIO_PFCAE3_PFCAE34                     (0x0010u)
+#define GPIO_PFCAE3_PFCAE35                     (0x0020u)
+#define GPIO_PFCAE3_PFCAE36                     (0x0040u)
+#define GPIO_PFCAE3_PFCAE37                     (0x0080u)
+#define GPIO_PFCAE3_PFCAE38                     (0x0100u)
+#define GPIO_PFCAE3_PFCAE39                     (0x0200u)
+#define GPIO_PFCAE3_PFCAE310                    (0x0400u)
+#define GPIO_PFCAE3_PFCAE311                    (0x0800u)
+#define GPIO_PFCAE3_PFCAE312                    (0x1000u)
+#define GPIO_PFCAE3_PFCAE313                    (0x2000u)
+#define GPIO_PFCAE3_PFCAE314                    (0x4000u)
+#define GPIO_PFCAE3_PFCAE315                    (0x8000u)
+
+#define GPIO_PIBC3_PIBC30                       (0x0001u)
+#define GPIO_PIBC3_PIBC31                       (0x0002u)
+#define GPIO_PIBC3_PIBC32                       (0x0004u)
+#define GPIO_PIBC3_PIBC33                       (0x0008u)
+#define GPIO_PIBC3_PIBC34                       (0x0010u)
+#define GPIO_PIBC3_PIBC35                       (0x0020u)
+#define GPIO_PIBC3_PIBC36                       (0x0040u)
+#define GPIO_PIBC3_PIBC37                       (0x0080u)
+#define GPIO_PIBC3_PIBC38                       (0x0100u)
+#define GPIO_PIBC3_PIBC39                       (0x0200u)
+#define GPIO_PIBC3_PIBC310                      (0x0400u)
+#define GPIO_PIBC3_PIBC311                      (0x0800u)
+#define GPIO_PIBC3_PIBC312                      (0x1000u)
+#define GPIO_PIBC3_PIBC313                      (0x2000u)
+#define GPIO_PIBC3_PIBC314                      (0x4000u)
+#define GPIO_PIBC3_PIBC315                      (0x8000u)
+
+#define GPIO_PBDC3_PBDC30                       (0x0001u)
+#define GPIO_PBDC3_PBDC31                       (0x0002u)
+#define GPIO_PBDC3_PBDC32                       (0x0004u)
+#define GPIO_PBDC3_PBDC33                       (0x0008u)
+#define GPIO_PBDC3_PBDC34                       (0x0010u)
+#define GPIO_PBDC3_PBDC35                       (0x0020u)
+#define GPIO_PBDC3_PBDC36                       (0x0040u)
+#define GPIO_PBDC3_PBDC37                       (0x0080u)
+#define GPIO_PBDC3_PBDC38                       (0x0100u)
+#define GPIO_PBDC3_PBDC39                       (0x0200u)
+#define GPIO_PBDC3_PBDC310                      (0x0400u)
+#define GPIO_PBDC3_PBDC311                      (0x0800u)
+#define GPIO_PBDC3_PBDC312                      (0x1000u)
+#define GPIO_PBDC3_PBDC313                      (0x2000u)
+#define GPIO_PBDC3_PBDC314                      (0x4000u)
+#define GPIO_PBDC3_PBDC315                      (0x8000u)
+
+#define GPIO_PIPC3_PIPC30                       (0x0001u)
+#define GPIO_PIPC3_PIPC31                       (0x0002u)
+#define GPIO_PIPC3_PIPC32                       (0x0004u)
+#define GPIO_PIPC3_PIPC33                       (0x0008u)
+#define GPIO_PIPC3_PIPC34                       (0x0010u)
+#define GPIO_PIPC3_PIPC35                       (0x0020u)
+#define GPIO_PIPC3_PIPC36                       (0x0040u)
+#define GPIO_PIPC3_PIPC37                       (0x0080u)
+#define GPIO_PIPC3_PIPC38                       (0x0100u)
+#define GPIO_PIPC3_PIPC39                       (0x0200u)
+#define GPIO_PIPC3_PIPC310                      (0x0400u)
+#define GPIO_PIPC3_PIPC311                      (0x0800u)
+#define GPIO_PIPC3_PIPC312                      (0x1000u)
+#define GPIO_PIPC3_PIPC313                      (0x2000u)
+#define GPIO_PIPC3_PIPC314                      (0x4000u)
+#define GPIO_PIPC3_PIPC315                      (0x8000u)
+
+/* ---- P4 ---- */
+#define GPIO_P4_P40                             (0x0001u)
+#define GPIO_P4_P41                             (0x0002u)
+#define GPIO_P4_P42                             (0x0004u)
+#define GPIO_P4_P43                             (0x0008u)
+#define GPIO_P4_P44                             (0x0010u)
+#define GPIO_P4_P45                             (0x0020u)
+#define GPIO_P4_P46                             (0x0040u)
+#define GPIO_P4_P47                             (0x0080u)
+#define GPIO_P4_P48                             (0x0100u)
+#define GPIO_P4_P49                             (0x0200u)
+#define GPIO_P4_P410                            (0x0400u)
+#define GPIO_P4_P411                            (0x0800u)
+#define GPIO_P4_P412                            (0x1000u)
+#define GPIO_P4_P413                            (0x2000u)
+#define GPIO_P4_P414                            (0x4000u)
+#define GPIO_P4_P415                            (0x8000u)
+
+#define GPIO_PSR4_PSR40                         (0x00000001uL)
+#define GPIO_PSR4_PSR41                         (0x00000002uL)
+#define GPIO_PSR4_PSR42                         (0x00000004uL)
+#define GPIO_PSR4_PSR43                         (0x00000008uL)
+#define GPIO_PSR4_PSR44                         (0x00000010uL)
+#define GPIO_PSR4_PSR45                         (0x00000020uL)
+#define GPIO_PSR4_PSR46                         (0x00000040uL)
+#define GPIO_PSR4_PSR47                         (0x00000080uL)
+#define GPIO_PSR4_PSR48                         (0x00000100uL)
+#define GPIO_PSR4_PSR49                         (0x00000200uL)
+#define GPIO_PSR4_PSR410                        (0x00000400uL)
+#define GPIO_PSR4_PSR411                        (0x00000800uL)
+#define GPIO_PSR4_PSR412                        (0x00001000uL)
+#define GPIO_PSR4_PSR413                        (0x00002000uL)
+#define GPIO_PSR4_PSR414                        (0x00004000uL)
+#define GPIO_PSR4_PSR415                        (0x00008000uL)
+#define GPIO_PSR4_PSR416                        (0x00010000uL)
+#define GPIO_PSR4_PSR417                        (0x00020000uL)
+#define GPIO_PSR4_PSR418                        (0x00040000uL)
+#define GPIO_PSR4_PSR419                        (0x00080000uL)
+#define GPIO_PSR4_PSR420                        (0x00100000uL)
+#define GPIO_PSR4_PSR421                        (0x00200000uL)
+#define GPIO_PSR4_PSR422                        (0x00400000uL)
+#define GPIO_PSR4_PSR423                        (0x00800000uL)
+#define GPIO_PSR4_PSR424                        (0x01000000uL)
+#define GPIO_PSR4_PSR425                        (0x02000000uL)
+#define GPIO_PSR4_PSR426                        (0x04000000uL)
+#define GPIO_PSR4_PSR427                        (0x08000000uL)
+#define GPIO_PSR4_PSR428                        (0x10000000uL)
+#define GPIO_PSR4_PSR429                        (0x20000000uL)
+#define GPIO_PSR4_PSR430                        (0x40000000uL)
+#define GPIO_PSR4_PSR431                        (0x80000000uL)
+
+#define GPIO_PPR4_PPR40                         (0x0001u)
+#define GPIO_PPR4_PPR41                         (0x0002u)
+#define GPIO_PPR4_PPR42                         (0x0004u)
+#define GPIO_PPR4_PPR43                         (0x0008u)
+#define GPIO_PPR4_PPR44                         (0x0010u)
+#define GPIO_PPR4_PPR45                         (0x0020u)
+#define GPIO_PPR4_PPR46                         (0x0040u)
+#define GPIO_PPR4_PPR47                         (0x0080u)
+#define GPIO_PPR4_PPR48                         (0x0100u)
+#define GPIO_PPR4_PPR49                         (0x0200u)
+#define GPIO_PPR4_PPR410                        (0x0400u)
+#define GPIO_PPR4_PPR411                        (0x0800u)
+#define GPIO_PPR4_PPR412                        (0x1000u)
+#define GPIO_PPR4_PPR413                        (0x2000u)
+#define GPIO_PPR4_PPR414                        (0x4000u)
+#define GPIO_PPR4_PPR415                        (0x8000u)
+
+#define GPIO_PM4_PM40                           (0x0001u)
+#define GPIO_PM4_PM41                           (0x0002u)
+#define GPIO_PM4_PM42                           (0x0004u)
+#define GPIO_PM4_PM43                           (0x0008u)
+#define GPIO_PM4_PM44                           (0x0010u)
+#define GPIO_PM4_PM45                           (0x0020u)
+#define GPIO_PM4_PM46                           (0x0040u)
+#define GPIO_PM4_PM47                           (0x0080u)
+#define GPIO_PM4_PM48                           (0x0100u)
+#define GPIO_PM4_PM49                           (0x0200u)
+#define GPIO_PM4_PM410                          (0x0400u)
+#define GPIO_PM4_PM411                          (0x0800u)
+#define GPIO_PM4_PM412                          (0x1000u)
+#define GPIO_PM4_PM413                          (0x2000u)
+#define GPIO_PM4_PM414                          (0x4000u)
+#define GPIO_PM4_PM415                          (0x8000u)
+
+#define GPIO_PMC4_PMC40                         (0x0001u)
+#define GPIO_PMC4_PMC41                         (0x0002u)
+#define GPIO_PMC4_PMC42                         (0x0004u)
+#define GPIO_PMC4_PMC43                         (0x0008u)
+#define GPIO_PMC4_PMC44                         (0x0010u)
+#define GPIO_PMC4_PMC45                         (0x0020u)
+#define GPIO_PMC4_PMC46                         (0x0040u)
+#define GPIO_PMC4_PMC47                         (0x0080u)
+#define GPIO_PMC4_PMC48                         (0x0100u)
+#define GPIO_PMC4_PMC49                         (0x0200u)
+#define GPIO_PMC4_PMC410                        (0x0400u)
+#define GPIO_PMC4_PMC411                        (0x0800u)
+#define GPIO_PMC4_PMC412                        (0x1000u)
+#define GPIO_PMC4_PMC413                        (0x2000u)
+#define GPIO_PMC4_PMC414                        (0x4000u)
+#define GPIO_PMC4_PMC415                        (0x8000u)
+
+#define GPIO_PFC4_PFC40                         (0x0001u)
+#define GPIO_PFC4_PFC41                         (0x0002u)
+#define GPIO_PFC4_PFC42                         (0x0004u)
+#define GPIO_PFC4_PFC43                         (0x0008u)
+#define GPIO_PFC4_PFC44                         (0x0010u)
+#define GPIO_PFC4_PFC45                         (0x0020u)
+#define GPIO_PFC4_PFC46                         (0x0040u)
+#define GPIO_PFC4_PFC47                         (0x0080u)
+#define GPIO_PFC4_PFC48                         (0x0100u)
+#define GPIO_PFC4_PFC49                         (0x0200u)
+#define GPIO_PFC4_PFC410                        (0x0400u)
+#define GPIO_PFC4_PFC411                        (0x0800u)
+#define GPIO_PFC4_PFC412                        (0x1000u)
+#define GPIO_PFC4_PFC413                        (0x2000u)
+#define GPIO_PFC4_PFC414                        (0x4000u)
+#define GPIO_PFC4_PFC415                        (0x8000u)
+
+#define GPIO_PFCE4_PFCE40                       (0x0001u)
+#define GPIO_PFCE4_PFCE41                       (0x0002u)
+#define GPIO_PFCE4_PFCE42                       (0x0004u)
+#define GPIO_PFCE4_PFCE43                       (0x0008u)
+#define GPIO_PFCE4_PFCE44                       (0x0010u)
+#define GPIO_PFCE4_PFCE45                       (0x0020u)
+#define GPIO_PFCE4_PFCE46                       (0x0040u)
+#define GPIO_PFCE4_PFCE47                       (0x0080u)
+#define GPIO_PFCE4_PFCE48                       (0x0100u)
+#define GPIO_PFCE4_PFCE49                       (0x0200u)
+#define GPIO_PFCE4_PFCE410                      (0x0400u)
+#define GPIO_PFCE4_PFCE411                      (0x0800u)
+#define GPIO_PFCE4_PFCE412                      (0x1000u)
+#define GPIO_PFCE4_PFCE413                      (0x2000u)
+#define GPIO_PFCE4_PFCE414                      (0x4000u)
+#define GPIO_PFCE4_PFCE415                      (0x8000u)
+
+#define GPIO_PNOT4_PNOT40                       (0x0001u)
+#define GPIO_PNOT4_PNOT41                       (0x0002u)
+#define GPIO_PNOT4_PNOT42                       (0x0004u)
+#define GPIO_PNOT4_PNOT43                       (0x0008u)
+#define GPIO_PNOT4_PNOT44                       (0x0010u)
+#define GPIO_PNOT4_PNOT45                       (0x0020u)
+#define GPIO_PNOT4_PNOT46                       (0x0040u)
+#define GPIO_PNOT4_PNOT47                       (0x0080u)
+#define GPIO_PNOT4_PNOT48                       (0x0100u)
+#define GPIO_PNOT4_PNOT49                       (0x0200u)
+#define GPIO_PNOT4_PNOT410                      (0x0400u)
+#define GPIO_PNOT4_PNOT411                      (0x0800u)
+#define GPIO_PNOT4_PNOT412                      (0x1000u)
+#define GPIO_PNOT4_PNOT413                      (0x2000u)
+#define GPIO_PNOT4_PNOT414                      (0x4000u)
+#define GPIO_PNOT4_PNOT415                      (0x8000u)
+
+#define GPIO_PMSR4_PMSR40                       (0x00000001uL)
+#define GPIO_PMSR4_PMSR41                       (0x00000002uL)
+#define GPIO_PMSR4_PMSR42                       (0x00000004uL)
+#define GPIO_PMSR4_PMSR43                       (0x00000008uL)
+#define GPIO_PMSR4_PMSR44                       (0x00000010uL)
+#define GPIO_PMSR4_PMSR45                       (0x00000020uL)
+#define GPIO_PMSR4_PMSR46                       (0x00000040uL)
+#define GPIO_PMSR4_PMSR47                       (0x00000080uL)
+#define GPIO_PMSR4_PMSR48                       (0x00000100uL)
+#define GPIO_PMSR4_PMSR49                       (0x00000200uL)
+#define GPIO_PMSR4_PMSR410                      (0x00000400uL)
+#define GPIO_PMSR4_PMSR411                      (0x00000800uL)
+#define GPIO_PMSR4_PMSR412                      (0x00001000uL)
+#define GPIO_PMSR4_PMSR413                      (0x00002000uL)
+#define GPIO_PMSR4_PMSR414                      (0x00004000uL)
+#define GPIO_PMSR4_PMSR415                      (0x00008000uL)
+#define GPIO_PMSR4_PMSR416                      (0x00010000uL)
+#define GPIO_PMSR4_PMSR417                      (0x00020000uL)
+#define GPIO_PMSR4_PMSR418                      (0x00040000uL)
+#define GPIO_PMSR4_PMSR419                      (0x00080000uL)
+#define GPIO_PMSR4_PMSR420                      (0x00100000uL)
+#define GPIO_PMSR4_PMSR421                      (0x00200000uL)
+#define GPIO_PMSR4_PMSR422                      (0x00400000uL)
+#define GPIO_PMSR4_PMSR423                      (0x00800000uL)
+#define GPIO_PMSR4_PMSR424                      (0x01000000uL)
+#define GPIO_PMSR4_PMSR425                      (0x02000000uL)
+#define GPIO_PMSR4_PMSR426                      (0x04000000uL)
+#define GPIO_PMSR4_PMSR427                      (0x08000000uL)
+#define GPIO_PMSR4_PMSR428                      (0x10000000uL)
+#define GPIO_PMSR4_PMSR429                      (0x20000000uL)
+#define GPIO_PMSR4_PMSR430                      (0x40000000uL)
+#define GPIO_PMSR4_PMSR431                      (0x80000000uL)
+
+#define GPIO_PMCSR4_PMCSR40                     (0x00000001uL)
+#define GPIO_PMCSR4_PMCSR41                     (0x00000002uL)
+#define GPIO_PMCSR4_PMCSR42                     (0x00000004uL)
+#define GPIO_PMCSR4_PMCSR43                     (0x00000008uL)
+#define GPIO_PMCSR4_PMCSR44                     (0x00000010uL)
+#define GPIO_PMCSR4_PMCSR45                     (0x00000020uL)
+#define GPIO_PMCSR4_PMCSR46                     (0x00000040uL)
+#define GPIO_PMCSR4_PMCSR47                     (0x00000080uL)
+#define GPIO_PMCSR4_PMCSR48                     (0x00000100uL)
+#define GPIO_PMCSR4_PMCSR49                     (0x00000200uL)
+#define GPIO_PMCSR4_PMCSR410                    (0x00000400uL)
+#define GPIO_PMCSR4_PMCSR411                    (0x00000800uL)
+#define GPIO_PMCSR4_PMCSR412                    (0x00001000uL)
+#define GPIO_PMCSR4_PMCSR413                    (0x00002000uL)
+#define GPIO_PMCSR4_PMCSR414                    (0x00004000uL)
+#define GPIO_PMCSR4_PMCSR415                    (0x00008000uL)
+#define GPIO_PMCSR4_PMCSR416                    (0x00010000uL)
+#define GPIO_PMCSR4_PMCSR417                    (0x00020000uL)
+#define GPIO_PMCSR4_PMCSR418                    (0x00040000uL)
+#define GPIO_PMCSR4_PMCSR419                    (0x00080000uL)
+#define GPIO_PMCSR4_PMCSR420                    (0x00100000uL)
+#define GPIO_PMCSR4_PMCSR421                    (0x00200000uL)
+#define GPIO_PMCSR4_PMCSR422                    (0x00400000uL)
+#define GPIO_PMCSR4_PMCSR423                    (0x00800000uL)
+#define GPIO_PMCSR4_PMCSR424                    (0x01000000uL)
+#define GPIO_PMCSR4_PMCSR425                    (0x02000000uL)
+#define GPIO_PMCSR4_PMCSR426                    (0x04000000uL)
+#define GPIO_PMCSR4_PMCSR427                    (0x08000000uL)
+#define GPIO_PMCSR4_PMCSR428                    (0x10000000uL)
+#define GPIO_PMCSR4_PMCSR429                    (0x20000000uL)
+#define GPIO_PMCSR4_PMCSR430                    (0x40000000uL)
+#define GPIO_PMCSR4_PMCSR431                    (0x80000000uL)
+
+#define GPIO_PFCAE4_PFCAE40                     (0x0001u)
+#define GPIO_PFCAE4_PFCAE41                     (0x0002u)
+#define GPIO_PFCAE4_PFCAE42                     (0x0004u)
+#define GPIO_PFCAE4_PFCAE43                     (0x0008u)
+#define GPIO_PFCAE4_PFCAE44                     (0x0010u)
+#define GPIO_PFCAE4_PFCAE45                     (0x0020u)
+#define GPIO_PFCAE4_PFCAE46                     (0x0040u)
+#define GPIO_PFCAE4_PFCAE47                     (0x0080u)
+#define GPIO_PFCAE4_PFCAE48                     (0x0100u)
+#define GPIO_PFCAE4_PFCAE49                     (0x0200u)
+#define GPIO_PFCAE4_PFCAE410                    (0x0400u)
+#define GPIO_PFCAE4_PFCAE411                    (0x0800u)
+#define GPIO_PFCAE4_PFCAE412                    (0x1000u)
+#define GPIO_PFCAE4_PFCAE413                    (0x2000u)
+#define GPIO_PFCAE4_PFCAE414                    (0x4000u)
+#define GPIO_PFCAE4_PFCAE415                    (0x8000u)
+
+#define GPIO_PIBC4_PIBC40                       (0x0001u)
+#define GPIO_PIBC4_PIBC41                       (0x0002u)
+#define GPIO_PIBC4_PIBC42                       (0x0004u)
+#define GPIO_PIBC4_PIBC43                       (0x0008u)
+#define GPIO_PIBC4_PIBC44                       (0x0010u)
+#define GPIO_PIBC4_PIBC45                       (0x0020u)
+#define GPIO_PIBC4_PIBC46                       (0x0040u)
+#define GPIO_PIBC4_PIBC47                       (0x0080u)
+#define GPIO_PIBC4_PIBC48                       (0x0100u)
+#define GPIO_PIBC4_PIBC49                       (0x0200u)
+#define GPIO_PIBC4_PIBC410                      (0x0400u)
+#define GPIO_PIBC4_PIBC411                      (0x0800u)
+#define GPIO_PIBC4_PIBC412                      (0x1000u)
+#define GPIO_PIBC4_PIBC413                      (0x2000u)
+#define GPIO_PIBC4_PIBC414                      (0x4000u)
+#define GPIO_PIBC4_PIBC415                      (0x8000u)
+
+#define GPIO_PBDC4_PBDC40                       (0x0001u)
+#define GPIO_PBDC4_PBDC41                       (0x0002u)
+#define GPIO_PBDC4_PBDC42                       (0x0004u)
+#define GPIO_PBDC4_PBDC43                       (0x0008u)
+#define GPIO_PBDC4_PBDC44                       (0x0010u)
+#define GPIO_PBDC4_PBDC45                       (0x0020u)
+#define GPIO_PBDC4_PBDC46                       (0x0040u)
+#define GPIO_PBDC4_PBDC47                       (0x0080u)
+#define GPIO_PBDC4_PBDC48                       (0x0100u)
+#define GPIO_PBDC4_PBDC49                       (0x0200u)
+#define GPIO_PBDC4_PBDC410                      (0x0400u)
+#define GPIO_PBDC4_PBDC411                      (0x0800u)
+#define GPIO_PBDC4_PBDC412                      (0x1000u)
+#define GPIO_PBDC4_PBDC413                      (0x2000u)
+#define GPIO_PBDC4_PBDC414                      (0x4000u)
+#define GPIO_PBDC4_PBDC415                      (0x8000u)
+
+#define GPIO_PIPC4_PIPC40                       (0x0001u)
+#define GPIO_PIPC4_PIPC41                       (0x0002u)
+#define GPIO_PIPC4_PIPC42                       (0x0004u)
+#define GPIO_PIPC4_PIPC43                       (0x0008u)
+#define GPIO_PIPC4_PIPC44                       (0x0010u)
+#define GPIO_PIPC4_PIPC45                       (0x0020u)
+#define GPIO_PIPC4_PIPC46                       (0x0040u)
+#define GPIO_PIPC4_PIPC47                       (0x0080u)
+#define GPIO_PIPC4_PIPC48                       (0x0100u)
+#define GPIO_PIPC4_PIPC49                       (0x0200u)
+#define GPIO_PIPC4_PIPC410                      (0x0400u)
+#define GPIO_PIPC4_PIPC411                      (0x0800u)
+#define GPIO_PIPC4_PIPC412                      (0x1000u)
+#define GPIO_PIPC4_PIPC413                      (0x2000u)
+#define GPIO_PIPC4_PIPC414                      (0x4000u)
+#define GPIO_PIPC4_PIPC415                      (0x8000u)
+
+/* ---- P5 ---- */
+#define GPIO_P5_P50                             (0x0001u)
+#define GPIO_P5_P51                             (0x0002u)
+#define GPIO_P5_P52                             (0x0004u)
+#define GPIO_P5_P53                             (0x0008u)
+#define GPIO_P5_P54                             (0x0010u)
+#define GPIO_P5_P55                             (0x0020u)
+#define GPIO_P5_P56                             (0x0040u)
+#define GPIO_P5_P57                             (0x0080u)
+#define GPIO_P5_P58                             (0x0100u)
+#define GPIO_P5_P59                             (0x0200u)
+#define GPIO_P5_P510                            (0x0400u)
+
+#define GPIO_PSR5_PSR50                         (0x00000001uL)
+#define GPIO_PSR5_PSR51                         (0x00000002uL)
+#define GPIO_PSR5_PSR52                         (0x00000004uL)
+#define GPIO_PSR5_PSR53                         (0x00000008uL)
+#define GPIO_PSR5_PSR54                         (0x00000010uL)
+#define GPIO_PSR5_PSR55                         (0x00000020uL)
+#define GPIO_PSR5_PSR56                         (0x00000040uL)
+#define GPIO_PSR5_PSR57                         (0x00000080uL)
+#define GPIO_PSR5_PSR58                         (0x00000100uL)
+#define GPIO_PSR5_PSR59                         (0x00000200uL)
+#define GPIO_PSR5_PSR510                        (0x00000400uL)
+#define GPIO_PSR5_PSR516                        (0x00010000uL)
+#define GPIO_PSR5_PSR517                        (0x00020000uL)
+#define GPIO_PSR5_PSR518                        (0x00040000uL)
+#define GPIO_PSR5_PSR519                        (0x00080000uL)
+#define GPIO_PSR5_PSR520                        (0x00100000uL)
+#define GPIO_PSR5_PSR521                        (0x00200000uL)
+#define GPIO_PSR5_PSR522                        (0x00400000uL)
+#define GPIO_PSR5_PSR523                        (0x00800000uL)
+#define GPIO_PSR5_PSR524                        (0x01000000uL)
+#define GPIO_PSR5_PSR525                        (0x02000000uL)
+#define GPIO_PSR5_PSR526                        (0x04000000uL)
+
+#define GPIO_PPR5_PPR50                         (0x0001u)
+#define GPIO_PPR5_PPR51                         (0x0002u)
+#define GPIO_PPR5_PPR52                         (0x0004u)
+#define GPIO_PPR5_PPR53                         (0x0008u)
+#define GPIO_PPR5_PPR54                         (0x0010u)
+#define GPIO_PPR5_PPR55                         (0x0020u)
+#define GPIO_PPR5_PPR56                         (0x0040u)
+#define GPIO_PPR5_PPR57                         (0x0080u)
+#define GPIO_PPR5_PPR58                         (0x0100u)
+#define GPIO_PPR5_PPR59                         (0x0200u)
+#define GPIO_PPR5_PPR510                        (0x0400u)
+
+#define GPIO_PM5_PM50                           (0x0001u)
+#define GPIO_PM5_PM51                           (0x0002u)
+#define GPIO_PM5_PM52                           (0x0004u)
+#define GPIO_PM5_PM53                           (0x0008u)
+#define GPIO_PM5_PM54                           (0x0010u)
+#define GPIO_PM5_PM55                           (0x0020u)
+#define GPIO_PM5_PM56                           (0x0040u)
+#define GPIO_PM5_PM57                           (0x0080u)
+#define GPIO_PM5_PM58                           (0x0100u)
+#define GPIO_PM5_PM59                           (0x0200u)
+#define GPIO_PM5_PM510                          (0x0400u)
+
+#define GPIO_PMC5_PMC50                         (0x0001u)
+#define GPIO_PMC5_PMC51                         (0x0002u)
+#define GPIO_PMC5_PMC52                         (0x0004u)
+#define GPIO_PMC5_PMC53                         (0x0008u)
+#define GPIO_PMC5_PMC54                         (0x0010u)
+#define GPIO_PMC5_PMC55                         (0x0020u)
+#define GPIO_PMC5_PMC56                         (0x0040u)
+#define GPIO_PMC5_PMC57                         (0x0080u)
+#define GPIO_PMC5_PMC58                         (0x0100u)
+#define GPIO_PMC5_PMC59                         (0x0200u)
+#define GPIO_PMC5_PMC510                        (0x0400u)
+
+#define GPIO_PFC5_PFC50                         (0x0001u)
+#define GPIO_PFC5_PFC51                         (0x0002u)
+#define GPIO_PFC5_PFC52                         (0x0004u)
+#define GPIO_PFC5_PFC53                         (0x0008u)
+#define GPIO_PFC5_PFC54                         (0x0010u)
+#define GPIO_PFC5_PFC55                         (0x0020u)
+#define GPIO_PFC5_PFC56                         (0x0040u)
+#define GPIO_PFC5_PFC57                         (0x0080u)
+#define GPIO_PFC5_PFC58                         (0x0100u)
+#define GPIO_PFC5_PFC59                         (0x0200u)
+#define GPIO_PFC5_PFC510                        (0x0400u)
+
+#define GPIO_PFCE5_PFCE50                       (0x0001u)
+#define GPIO_PFCE5_PFCE51                       (0x0002u)
+#define GPIO_PFCE5_PFCE52                       (0x0004u)
+#define GPIO_PFCE5_PFCE53                       (0x0008u)
+#define GPIO_PFCE5_PFCE54                       (0x0010u)
+#define GPIO_PFCE5_PFCE55                       (0x0020u)
+#define GPIO_PFCE5_PFCE56                       (0x0040u)
+#define GPIO_PFCE5_PFCE57                       (0x0080u)
+#define GPIO_PFCE5_PFCE58                       (0x0100u)
+#define GPIO_PFCE5_PFCE59                       (0x0200u)
+#define GPIO_PFCE5_PFCE510                      (0x0400u)
+
+#define GPIO_PNOT5_PNOT50                       (0x0001u)
+#define GPIO_PNOT5_PNOT51                       (0x0002u)
+#define GPIO_PNOT5_PNOT52                       (0x0004u)
+#define GPIO_PNOT5_PNOT53                       (0x0008u)
+#define GPIO_PNOT5_PNOT54                       (0x0010u)
+#define GPIO_PNOT5_PNOT55                       (0x0020u)
+#define GPIO_PNOT5_PNOT56                       (0x0040u)
+#define GPIO_PNOT5_PNOT57                       (0x0080u)
+#define GPIO_PNOT5_PNOT58                       (0x0100u)
+#define GPIO_PNOT5_PNOT59                       (0x0200u)
+#define GPIO_PNOT5_PNOT510                      (0x0400u)
+
+#define GPIO_PMSR5_PMSR50                       (0x00000001uL)
+#define GPIO_PMSR5_PMSR51                       (0x00000002uL)
+#define GPIO_PMSR5_PMSR52                       (0x00000004uL)
+#define GPIO_PMSR5_PMSR53                       (0x00000008uL)
+#define GPIO_PMSR5_PMSR54                       (0x00000010uL)
+#define GPIO_PMSR5_PMSR55                       (0x00000020uL)
+#define GPIO_PMSR5_PMSR56                       (0x00000040uL)
+#define GPIO_PMSR5_PMSR57                       (0x00000080uL)
+#define GPIO_PMSR5_PMSR58                       (0x00000100uL)
+#define GPIO_PMSR5_PMSR59                       (0x00000200uL)
+#define GPIO_PMSR5_PMSR510                      (0x00000400uL)
+#define GPIO_PMSR5_PMSR516                      (0x00010000uL)
+#define GPIO_PMSR5_PMSR517                      (0x00020000uL)
+#define GPIO_PMSR5_PMSR518                      (0x00040000uL)
+#define GPIO_PMSR5_PMSR519                      (0x00080000uL)
+#define GPIO_PMSR5_PMSR520                      (0x00100000uL)
+#define GPIO_PMSR5_PMSR521                      (0x00200000uL)
+#define GPIO_PMSR5_PMSR522                      (0x00400000uL)
+#define GPIO_PMSR5_PMSR523                      (0x00800000uL)
+#define GPIO_PMSR5_PMSR524                      (0x01000000uL)
+#define GPIO_PMSR5_PMSR525                      (0x02000000uL)
+#define GPIO_PMSR5_PMSR526                      (0x04000000uL)
+
+#define GPIO_PMCSR5_PMCSR50                     (0x00000001uL)
+#define GPIO_PMCSR5_PMCSR51                     (0x00000002uL)
+#define GPIO_PMCSR5_PMCSR52                     (0x00000004uL)
+#define GPIO_PMCSR5_PMCSR53                     (0x00000008uL)
+#define GPIO_PMCSR5_PMCSR54                     (0x00000010uL)
+#define GPIO_PMCSR5_PMCSR55                     (0x00000020uL)
+#define GPIO_PMCSR5_PMCSR56                     (0x00000040uL)
+#define GPIO_PMCSR5_PMCSR57                     (0x00000080uL)
+#define GPIO_PMCSR5_PMCSR58                     (0x00000100uL)
+#define GPIO_PMCSR5_PMCSR59                     (0x00000200uL)
+#define GPIO_PMCSR5_PMCSR510                    (0x00000400uL)
+#define GPIO_PMCSR5_PMCSR516                    (0x00010000uL)
+#define GPIO_PMCSR5_PMCSR517                    (0x00020000uL)
+#define GPIO_PMCSR5_PMCSR518                    (0x00040000uL)
+#define GPIO_PMCSR5_PMCSR519                    (0x00080000uL)
+#define GPIO_PMCSR5_PMCSR520                    (0x00100000uL)
+#define GPIO_PMCSR5_PMCSR521                    (0x00200000uL)
+#define GPIO_PMCSR5_PMCSR522                    (0x00400000uL)
+#define GPIO_PMCSR5_PMCSR523                    (0x00800000uL)
+#define GPIO_PMCSR5_PMCSR524                    (0x01000000uL)
+#define GPIO_PMCSR5_PMCSR525                    (0x02000000uL)
+#define GPIO_PMCSR5_PMCSR526                    (0x04000000uL)
+
+#define GPIO_PFCAE5_PFCAE50                     (0x0001u)
+#define GPIO_PFCAE5_PFCAE51                     (0x0002u)
+#define GPIO_PFCAE5_PFCAE52                     (0x0004u)
+#define GPIO_PFCAE5_PFCAE53                     (0x0008u)
+#define GPIO_PFCAE5_PFCAE54                     (0x0010u)
+#define GPIO_PFCAE5_PFCAE55                     (0x0020u)
+#define GPIO_PFCAE5_PFCAE56                     (0x0040u)
+#define GPIO_PFCAE5_PFCAE57                     (0x0080u)
+#define GPIO_PFCAE5_PFCAE58                     (0x0100u)
+#define GPIO_PFCAE5_PFCAE59                     (0x0200u)
+#define GPIO_PFCAE5_PFCAE510                    (0x0400u)
+
+#define GPIO_PIBC5_PIBC50                       (0x0001u)
+#define GPIO_PIBC5_PIBC51                       (0x0002u)
+#define GPIO_PIBC5_PIBC52                       (0x0004u)
+#define GPIO_PIBC5_PIBC53                       (0x0008u)
+#define GPIO_PIBC5_PIBC54                       (0x0010u)
+#define GPIO_PIBC5_PIBC55                       (0x0020u)
+#define GPIO_PIBC5_PIBC56                       (0x0040u)
+#define GPIO_PIBC5_PIBC57                       (0x0080u)
+#define GPIO_PIBC5_PIBC58                       (0x0100u)
+#define GPIO_PIBC5_PIBC59                       (0x0200u)
+#define GPIO_PIBC5_PIBC510                      (0x0400u)
+
+#define GPIO_PBDC5_PBDC50                       (0x0001u)
+#define GPIO_PBDC5_PBDC51                       (0x0002u)
+#define GPIO_PBDC5_PBDC52                       (0x0004u)
+#define GPIO_PBDC5_PBDC53                       (0x0008u)
+#define GPIO_PBDC5_PBDC54                       (0x0010u)
+#define GPIO_PBDC5_PBDC55                       (0x0020u)
+#define GPIO_PBDC5_PBDC56                       (0x0040u)
+#define GPIO_PBDC5_PBDC57                       (0x0080u)
+#define GPIO_PBDC5_PBDC58                       (0x0100u)
+#define GPIO_PBDC5_PBDC59                       (0x0200u)
+#define GPIO_PBDC5_PBDC510                      (0x0400u)
+
+#define GPIO_PIPC5_PIPC50                       (0x0001u)
+#define GPIO_PIPC5_PIPC51                       (0x0002u)
+#define GPIO_PIPC5_PIPC52                       (0x0004u)
+#define GPIO_PIPC5_PIPC53                       (0x0008u)
+#define GPIO_PIPC5_PIPC54                       (0x0010u)
+#define GPIO_PIPC5_PIPC55                       (0x0020u)
+#define GPIO_PIPC5_PIPC56                       (0x0040u)
+#define GPIO_PIPC5_PIPC57                       (0x0080u)
+#define GPIO_PIPC5_PIPC58                       (0x0100u)
+#define GPIO_PIPC5_PIPC59                       (0x0200u)
+#define GPIO_PIPC5_PIPC510                      (0x0400u)
+
+/* ---- P6 ---- */
+#define GPIO_P6_P60                             (0x0001u)
+#define GPIO_P6_P61                             (0x0002u)
+#define GPIO_P6_P62                             (0x0004u)
+#define GPIO_P6_P63                             (0x0008u)
+#define GPIO_P6_P64                             (0x0010u)
+#define GPIO_P6_P65                             (0x0020u)
+#define GPIO_P6_P66                             (0x0040u)
+#define GPIO_P6_P67                             (0x0080u)
+#define GPIO_P6_P68                             (0x0100u)
+#define GPIO_P6_P69                             (0x0200u)
+#define GPIO_P6_P610                            (0x0400u)
+#define GPIO_P6_P611                            (0x0800u)
+#define GPIO_P6_P612                            (0x1000u)
+#define GPIO_P6_P613                            (0x2000u)
+#define GPIO_P6_P614                            (0x4000u)
+#define GPIO_P6_P615                            (0x8000u)
+
+#define GPIO_PSR6_PSR60                         (0x00000001uL)
+#define GPIO_PSR6_PSR61                         (0x00000002uL)
+#define GPIO_PSR6_PSR62                         (0x00000004uL)
+#define GPIO_PSR6_PSR63                         (0x00000008uL)
+#define GPIO_PSR6_PSR64                         (0x00000010uL)
+#define GPIO_PSR6_PSR65                         (0x00000020uL)
+#define GPIO_PSR6_PSR66                         (0x00000040uL)
+#define GPIO_PSR6_PSR67                         (0x00000080uL)
+#define GPIO_PSR6_PSR68                         (0x00000100uL)
+#define GPIO_PSR6_PSR69                         (0x00000200uL)
+#define GPIO_PSR6_PSR610                        (0x00000400uL)
+#define GPIO_PSR6_PSR611                        (0x00000800uL)
+#define GPIO_PSR6_PSR612                        (0x00001000uL)
+#define GPIO_PSR6_PSR613                        (0x00002000uL)
+#define GPIO_PSR6_PSR614                        (0x00004000uL)
+#define GPIO_PSR6_PSR615                        (0x00008000uL)
+#define GPIO_PSR6_PSR616                        (0x00010000uL)
+#define GPIO_PSR6_PSR617                        (0x00020000uL)
+#define GPIO_PSR6_PSR618                        (0x00040000uL)
+#define GPIO_PSR6_PSR619                        (0x00080000uL)
+#define GPIO_PSR6_PSR620                        (0x00100000uL)
+#define GPIO_PSR6_PSR621                        (0x00200000uL)
+#define GPIO_PSR6_PSR622                        (0x00400000uL)
+#define GPIO_PSR6_PSR623                        (0x00800000uL)
+#define GPIO_PSR6_PSR624                        (0x01000000uL)
+#define GPIO_PSR6_PSR625                        (0x02000000uL)
+#define GPIO_PSR6_PSR626                        (0x04000000uL)
+#define GPIO_PSR6_PSR627                        (0x08000000uL)
+#define GPIO_PSR6_PSR628                        (0x10000000uL)
+#define GPIO_PSR6_PSR629                        (0x20000000uL)
+#define GPIO_PSR6_PSR630                        (0x40000000uL)
+#define GPIO_PSR6_PSR631                        (0x80000000uL)
+
+#define GPIO_PPR6_PPR60                         (0x0001u)
+#define GPIO_PPR6_PPR61                         (0x0002u)
+#define GPIO_PPR6_PPR62                         (0x0004u)
+#define GPIO_PPR6_PPR63                         (0x0008u)
+#define GPIO_PPR6_PPR64                         (0x0010u)
+#define GPIO_PPR6_PPR65                         (0x0020u)
+#define GPIO_PPR6_PPR66                         (0x0040u)
+#define GPIO_PPR6_PPR67                         (0x0080u)
+#define GPIO_PPR6_PPR68                         (0x0100u)
+#define GPIO_PPR6_PPR69                         (0x0200u)
+#define GPIO_PPR6_PPR610                        (0x0400u)
+#define GPIO_PPR6_PPR611                        (0x0800u)
+#define GPIO_PPR6_PPR612                        (0x1000u)
+#define GPIO_PPR6_PPR613                        (0x2000u)
+#define GPIO_PPR6_PPR614                        (0x4000u)
+#define GPIO_PPR6_PPR615                        (0x8000u)
+
+#define GPIO_PM6_PM60                           (0x0001u)
+#define GPIO_PM6_PM61                           (0x0002u)
+#define GPIO_PM6_PM62                           (0x0004u)
+#define GPIO_PM6_PM63                           (0x0008u)
+#define GPIO_PM6_PM64                           (0x0010u)
+#define GPIO_PM6_PM65                           (0x0020u)
+#define GPIO_PM6_PM66                           (0x0040u)
+#define GPIO_PM6_PM67                           (0x0080u)
+#define GPIO_PM6_PM68                           (0x0100u)
+#define GPIO_PM6_PM69                           (0x0200u)
+#define GPIO_PM6_PM610                          (0x0400u)
+#define GPIO_PM6_PM611                          (0x0800u)
+#define GPIO_PM6_PM612                          (0x1000u)
+#define GPIO_PM6_PM613                          (0x2000u)
+#define GPIO_PM6_PM614                          (0x4000u)
+#define GPIO_PM6_PM615                          (0x8000u)
+
+#define GPIO_PMC6_PMC60                         (0x0001u)
+#define GPIO_PMC6_PMC61                         (0x0002u)
+#define GPIO_PMC6_PMC62                         (0x0004u)
+#define GPIO_PMC6_PMC63                         (0x0008u)
+#define GPIO_PMC6_PMC64                         (0x0010u)
+#define GPIO_PMC6_PMC65                         (0x0020u)
+#define GPIO_PMC6_PMC66                         (0x0040u)
+#define GPIO_PMC6_PMC67                         (0x0080u)
+#define GPIO_PMC6_PMC68                         (0x0100u)
+#define GPIO_PMC6_PMC69                         (0x0200u)
+#define GPIO_PMC6_PMC610                        (0x0400u)
+#define GPIO_PMC6_PMC611                        (0x0800u)
+#define GPIO_PMC6_PMC612                        (0x1000u)
+#define GPIO_PMC6_PMC613                        (0x2000u)
+#define GPIO_PMC6_PMC614                        (0x4000u)
+#define GPIO_PMC6_PMC615                        (0x8000u)
+
+#define GPIO_PFC6_PFC60                         (0x0001u)
+#define GPIO_PFC6_PFC61                         (0x0002u)
+#define GPIO_PFC6_PFC62                         (0x0004u)
+#define GPIO_PFC6_PFC63                         (0x0008u)
+#define GPIO_PFC6_PFC64                         (0x0010u)
+#define GPIO_PFC6_PFC65                         (0x0020u)
+#define GPIO_PFC6_PFC66                         (0x0040u)
+#define GPIO_PFC6_PFC67                         (0x0080u)
+#define GPIO_PFC6_PFC68                         (0x0100u)
+#define GPIO_PFC6_PFC69                         (0x0200u)
+#define GPIO_PFC6_PFC610                        (0x0400u)
+#define GPIO_PFC6_PFC611                        (0x0800u)
+#define GPIO_PFC6_PFC612                        (0x1000u)
+#define GPIO_PFC6_PFC613                        (0x2000u)
+#define GPIO_PFC6_PFC614                        (0x4000u)
+#define GPIO_PFC6_PFC615                        (0x8000u)
+
+#define GPIO_PFCE6_PFCE60                       (0x0001u)
+#define GPIO_PFCE6_PFCE61                       (0x0002u)
+#define GPIO_PFCE6_PFCE62                       (0x0004u)
+#define GPIO_PFCE6_PFCE63                       (0x0008u)
+#define GPIO_PFCE6_PFCE64                       (0x0010u)
+#define GPIO_PFCE6_PFCE65                       (0x0020u)
+#define GPIO_PFCE6_PFCE66                       (0x0040u)
+#define GPIO_PFCE6_PFCE67                       (0x0080u)
+#define GPIO_PFCE6_PFCE68                       (0x0100u)
+#define GPIO_PFCE6_PFCE69                       (0x0200u)
+#define GPIO_PFCE6_PFCE610                      (0x0400u)
+#define GPIO_PFCE6_PFCE611                      (0x0800u)
+#define GPIO_PFCE6_PFCE612                      (0x1000u)
+#define GPIO_PFCE6_PFCE613                      (0x2000u)
+#define GPIO_PFCE6_PFCE614                      (0x4000u)
+#define GPIO_PFCE6_PFCE615                      (0x8000u)
+
+#define GPIO_PNOT6_PNOT60                       (0x0001u)
+#define GPIO_PNOT6_PNOT61                       (0x0002u)
+#define GPIO_PNOT6_PNOT62                       (0x0004u)
+#define GPIO_PNOT6_PNOT63                       (0x0008u)
+#define GPIO_PNOT6_PNOT64                       (0x0010u)
+#define GPIO_PNOT6_PNOT65                       (0x0020u)
+#define GPIO_PNOT6_PNOT66                       (0x0040u)
+#define GPIO_PNOT6_PNOT67                       (0x0080u)
+#define GPIO_PNOT6_PNOT68                       (0x0100u)
+#define GPIO_PNOT6_PNOT69                       (0x0200u)
+#define GPIO_PNOT6_PNOT610                      (0x0400u)
+#define GPIO_PNOT6_PNOT611                      (0x0800u)
+#define GPIO_PNOT6_PNOT612                      (0x1000u)
+#define GPIO_PNOT6_PNOT613                      (0x2000u)
+#define GPIO_PNOT6_PNOT614                      (0x4000u)
+#define GPIO_PNOT6_PNOT615                      (0x8000u)
+
+#define GPIO_PMSR6_PMSR60                       (0x00000001uL)
+#define GPIO_PMSR6_PMSR61                       (0x00000002uL)
+#define GPIO_PMSR6_PMSR62                       (0x00000004uL)
+#define GPIO_PMSR6_PMSR63                       (0x00000008uL)
+#define GPIO_PMSR6_PMSR64                       (0x00000010uL)
+#define GPIO_PMSR6_PMSR65                       (0x00000020uL)
+#define GPIO_PMSR6_PMSR66                       (0x00000040uL)
+#define GPIO_PMSR6_PMSR67                       (0x00000080uL)
+#define GPIO_PMSR6_PMSR68                       (0x00000100uL)
+#define GPIO_PMSR6_PMSR69                       (0x00000200uL)
+#define GPIO_PMSR6_PMSR610                      (0x00000400uL)
+#define GPIO_PMSR6_PMSR611                      (0x00000800uL)
+#define GPIO_PMSR6_PMSR612                      (0x00001000uL)
+#define GPIO_PMSR6_PMSR613                      (0x00002000uL)
+#define GPIO_PMSR6_PMSR614                      (0x00004000uL)
+#define GPIO_PMSR6_PMSR615                      (0x00008000uL)
+#define GPIO_PMSR6_PMSR616                      (0x00010000uL)
+#define GPIO_PMSR6_PMSR617                      (0x00020000uL)
+#define GPIO_PMSR6_PMSR618                      (0x00040000uL)
+#define GPIO_PMSR6_PMSR619                      (0x00080000uL)
+#define GPIO_PMSR6_PMSR620                      (0x00100000uL)
+#define GPIO_PMSR6_PMSR621                      (0x00200000uL)
+#define GPIO_PMSR6_PMSR622                      (0x00400000uL)
+#define GPIO_PMSR6_PMSR623                      (0x00800000uL)
+#define GPIO_PMSR6_PMSR624                      (0x01000000uL)
+#define GPIO_PMSR6_PMSR625                      (0x02000000uL)
+#define GPIO_PMSR6_PMSR626                      (0x04000000uL)
+#define GPIO_PMSR6_PMSR627                      (0x08000000uL)
+#define GPIO_PMSR6_PMSR628                      (0x10000000uL)
+#define GPIO_PMSR6_PMSR629                      (0x20000000uL)
+#define GPIO_PMSR6_PMSR630                      (0x40000000uL)
+#define GPIO_PMSR6_PMSR631                      (0x80000000uL)
+
+#define GPIO_PMCSR6_PMCSR60                     (0x00000001uL)
+#define GPIO_PMCSR6_PMCSR61                     (0x00000002uL)
+#define GPIO_PMCSR6_PMCSR62                     (0x00000004uL)
+#define GPIO_PMCSR6_PMCSR63                     (0x00000008uL)
+#define GPIO_PMCSR6_PMCSR64                     (0x00000010uL)
+#define GPIO_PMCSR6_PMCSR65                     (0x00000020uL)
+#define GPIO_PMCSR6_PMCSR66                     (0x00000040uL)
+#define GPIO_PMCSR6_PMCSR67                     (0x00000080uL)
+#define GPIO_PMCSR6_PMCSR68                     (0x00000100uL)
+#define GPIO_PMCSR6_PMCSR69                     (0x00000200uL)
+#define GPIO_PMCSR6_PMCSR610                    (0x00000400uL)
+#define GPIO_PMCSR6_PMCSR611                    (0x00000800uL)
+#define GPIO_PMCSR6_PMCSR612                    (0x00001000uL)
+#define GPIO_PMCSR6_PMCSR613                    (0x00002000uL)
+#define GPIO_PMCSR6_PMCSR614                    (0x00004000uL)
+#define GPIO_PMCSR6_PMCSR615                    (0x00008000uL)
+#define GPIO_PMCSR6_PMCSR616                    (0x00010000uL)
+#define GPIO_PMCSR6_PMCSR617                    (0x00020000uL)
+#define GPIO_PMCSR6_PMCSR618                    (0x00040000uL)
+#define GPIO_PMCSR6_PMCSR619                    (0x00080000uL)
+#define GPIO_PMCSR6_PMCSR620                    (0x00100000uL)
+#define GPIO_PMCSR6_PMCSR621                    (0x00200000uL)
+#define GPIO_PMCSR6_PMCSR622                    (0x00400000uL)
+#define GPIO_PMCSR6_PMCSR623                    (0x00800000uL)
+#define GPIO_PMCSR6_PMCSR624                    (0x01000000uL)
+#define GPIO_PMCSR6_PMCSR625                    (0x02000000uL)
+#define GPIO_PMCSR6_PMCSR626                    (0x04000000uL)
+#define GPIO_PMCSR6_PMCSR627                    (0x08000000uL)
+#define GPIO_PMCSR6_PMCSR628                    (0x10000000uL)
+#define GPIO_PMCSR6_PMCSR629                    (0x20000000uL)
+#define GPIO_PMCSR6_PMCSR630                    (0x40000000uL)
+#define GPIO_PMCSR6_PMCSR631                    (0x80000000uL)
+
+#define GPIO_PFCAE6_PFCAE60                     (0x0001u)
+#define GPIO_PFCAE6_PFCAE61                     (0x0002u)
+#define GPIO_PFCAE6_PFCAE62                     (0x0004u)
+#define GPIO_PFCAE6_PFCAE63                     (0x0008u)
+#define GPIO_PFCAE6_PFCAE64                     (0x0010u)
+#define GPIO_PFCAE6_PFCAE65                     (0x0020u)
+#define GPIO_PFCAE6_PFCAE66                     (0x0040u)
+#define GPIO_PFCAE6_PFCAE67                     (0x0080u)
+#define GPIO_PFCAE6_PFCAE68                     (0x0100u)
+#define GPIO_PFCAE6_PFCAE69                     (0x0200u)
+#define GPIO_PFCAE6_PFCAE610                    (0x0400u)
+#define GPIO_PFCAE6_PFCAE611                    (0x0800u)
+#define GPIO_PFCAE6_PFCAE612                    (0x1000u)
+#define GPIO_PFCAE6_PFCAE613                    (0x2000u)
+#define GPIO_PFCAE6_PFCAE614                    (0x4000u)
+#define GPIO_PFCAE6_PFCAE615                    (0x8000u)
+
+#define GPIO_PIBC6_PIBC60                       (0x0001u)
+#define GPIO_PIBC6_PIBC61                       (0x0002u)
+#define GPIO_PIBC6_PIBC62                       (0x0004u)
+#define GPIO_PIBC6_PIBC63                       (0x0008u)
+#define GPIO_PIBC6_PIBC64                       (0x0010u)
+#define GPIO_PIBC6_PIBC65                       (0x0020u)
+#define GPIO_PIBC6_PIBC66                       (0x0040u)
+#define GPIO_PIBC6_PIBC67                       (0x0080u)
+#define GPIO_PIBC6_PIBC68                       (0x0100u)
+#define GPIO_PIBC6_PIBC69                       (0x0200u)
+#define GPIO_PIBC6_PIBC610                      (0x0400u)
+#define GPIO_PIBC6_PIBC611                      (0x0800u)
+#define GPIO_PIBC6_PIBC612                      (0x1000u)
+#define GPIO_PIBC6_PIBC613                      (0x2000u)
+#define GPIO_PIBC6_PIBC614                      (0x4000u)
+#define GPIO_PIBC6_PIBC615                      (0x8000u)
+
+#define GPIO_PBDC6_PBDC60                       (0x0001u)
+#define GPIO_PBDC6_PBDC61                       (0x0002u)
+#define GPIO_PBDC6_PBDC62                       (0x0004u)
+#define GPIO_PBDC6_PBDC63                       (0x0008u)
+#define GPIO_PBDC6_PBDC64                       (0x0010u)
+#define GPIO_PBDC6_PBDC65                       (0x0020u)
+#define GPIO_PBDC6_PBDC66                       (0x0040u)
+#define GPIO_PBDC6_PBDC67                       (0x0080u)
+#define GPIO_PBDC6_PBDC68                       (0x0100u)
+#define GPIO_PBDC6_PBDC69                       (0x0200u)
+#define GPIO_PBDC6_PBDC610                      (0x0400u)
+#define GPIO_PBDC6_PBDC611                      (0x0800u)
+#define GPIO_PBDC6_PBDC612                      (0x1000u)
+#define GPIO_PBDC6_PBDC613                      (0x2000u)
+#define GPIO_PBDC6_PBDC614                      (0x4000u)
+#define GPIO_PBDC6_PBDC615                      (0x8000u)
+
+#define GPIO_PIPC6_PIPC60                       (0x0001u)
+#define GPIO_PIPC6_PIPC61                       (0x0002u)
+#define GPIO_PIPC6_PIPC62                       (0x0004u)
+#define GPIO_PIPC6_PIPC63                       (0x0008u)
+#define GPIO_PIPC6_PIPC64                       (0x0010u)
+#define GPIO_PIPC6_PIPC65                       (0x0020u)
+#define GPIO_PIPC6_PIPC66                       (0x0040u)
+#define GPIO_PIPC6_PIPC67                       (0x0080u)
+#define GPIO_PIPC6_PIPC68                       (0x0100u)
+#define GPIO_PIPC6_PIPC69                       (0x0200u)
+#define GPIO_PIPC6_PIPC610                      (0x0400u)
+#define GPIO_PIPC6_PIPC611                      (0x0800u)
+#define GPIO_PIPC6_PIPC612                      (0x1000u)
+#define GPIO_PIPC6_PIPC613                      (0x2000u)
+#define GPIO_PIPC6_PIPC614                      (0x4000u)
+#define GPIO_PIPC6_PIPC615                      (0x8000u)
+
+/* ---- P7 ---- */
+#define GPIO_P7_P70                             (0x0001u)
+#define GPIO_P7_P71                             (0x0002u)
+#define GPIO_P7_P72                             (0x0004u)
+#define GPIO_P7_P73                             (0x0008u)
+#define GPIO_P7_P74                             (0x0010u)
+#define GPIO_P7_P75                             (0x0020u)
+#define GPIO_P7_P76                             (0x0040u)
+#define GPIO_P7_P77                             (0x0080u)
+#define GPIO_P7_P78                             (0x0100u)
+#define GPIO_P7_P79                             (0x0200u)
+#define GPIO_P7_P710                            (0x0400u)
+#define GPIO_P7_P711                            (0x0800u)
+#define GPIO_P7_P712                            (0x1000u)
+#define GPIO_P7_P713                            (0x2000u)
+#define GPIO_P7_P714                            (0x4000u)
+#define GPIO_P7_P715                            (0x8000u)
+
+#define GPIO_PSR7_PSR70                         (0x00000001uL)
+#define GPIO_PSR7_PSR71                         (0x00000002uL)
+#define GPIO_PSR7_PSR72                         (0x00000004uL)
+#define GPIO_PSR7_PSR73                         (0x00000008uL)
+#define GPIO_PSR7_PSR74                         (0x00000010uL)
+#define GPIO_PSR7_PSR75                         (0x00000020uL)
+#define GPIO_PSR7_PSR76                         (0x00000040uL)
+#define GPIO_PSR7_PSR77                         (0x00000080uL)
+#define GPIO_PSR7_PSR78                         (0x00000100uL)
+#define GPIO_PSR7_PSR79                         (0x00000200uL)
+#define GPIO_PSR7_PSR710                        (0x00000400uL)
+#define GPIO_PSR7_PSR711                        (0x00000800uL)
+#define GPIO_PSR7_PSR712                        (0x00001000uL)
+#define GPIO_PSR7_PSR713                        (0x00002000uL)
+#define GPIO_PSR7_PSR714                        (0x00004000uL)
+#define GPIO_PSR7_PSR715                        (0x00008000uL)
+#define GPIO_PSR7_PSR716                        (0x00010000uL)
+#define GPIO_PSR7_PSR717                        (0x00020000uL)
+#define GPIO_PSR7_PSR718                        (0x00040000uL)
+#define GPIO_PSR7_PSR719                        (0x00080000uL)
+#define GPIO_PSR7_PSR720                        (0x00100000uL)
+#define GPIO_PSR7_PSR721                        (0x00200000uL)
+#define GPIO_PSR7_PSR722                        (0x00400000uL)
+#define GPIO_PSR7_PSR723                        (0x00800000uL)
+#define GPIO_PSR7_PSR724                        (0x01000000uL)
+#define GPIO_PSR7_PSR725                        (0x02000000uL)
+#define GPIO_PSR7_PSR726                        (0x04000000uL)
+#define GPIO_PSR7_PSR727                        (0x08000000uL)
+#define GPIO_PSR7_PSR728                        (0x10000000uL)
+#define GPIO_PSR7_PSR729                        (0x20000000uL)
+#define GPIO_PSR7_PSR730                        (0x40000000uL)
+#define GPIO_PSR7_PSR731                        (0x80000000uL)
+
+#define GPIO_PPR7_PPR70                         (0x0001u)
+#define GPIO_PPR7_PPR71                         (0x0002u)
+#define GPIO_PPR7_PPR72                         (0x0004u)
+#define GPIO_PPR7_PPR73                         (0x0008u)
+#define GPIO_PPR7_PPR74                         (0x0010u)
+#define GPIO_PPR7_PPR75                         (0x0020u)
+#define GPIO_PPR7_PPR76                         (0x0040u)
+#define GPIO_PPR7_PPR77                         (0x0080u)
+#define GPIO_PPR7_PPR78                         (0x0100u)
+#define GPIO_PPR7_PPR79                         (0x0200u)
+#define GPIO_PPR7_PPR710                        (0x0400u)
+#define GPIO_PPR7_PPR711                        (0x0800u)
+#define GPIO_PPR7_PPR712                        (0x1000u)
+#define GPIO_PPR7_PPR713                        (0x2000u)
+#define GPIO_PPR7_PPR714                        (0x4000u)
+#define GPIO_PPR7_PPR715                        (0x8000u)
+
+#define GPIO_PM7_PM70                           (0x0001u)
+#define GPIO_PM7_PM71                           (0x0002u)
+#define GPIO_PM7_PM72                           (0x0004u)
+#define GPIO_PM7_PM73                           (0x0008u)
+#define GPIO_PM7_PM74                           (0x0010u)
+#define GPIO_PM7_PM75                           (0x0020u)
+#define GPIO_PM7_PM76                           (0x0040u)
+#define GPIO_PM7_PM77                           (0x0080u)
+#define GPIO_PM7_PM78                           (0x0100u)
+#define GPIO_PM7_PM79                           (0x0200u)
+#define GPIO_PM7_PM710                          (0x0400u)
+#define GPIO_PM7_PM711                          (0x0800u)
+#define GPIO_PM7_PM712                          (0x1000u)
+#define GPIO_PM7_PM713                          (0x2000u)
+#define GPIO_PM7_PM714                          (0x4000u)
+#define GPIO_PM7_PM715                          (0x8000u)
+
+#define GPIO_PMC7_PMC70                         (0x0001u)
+#define GPIO_PMC7_PMC71                         (0x0002u)
+#define GPIO_PMC7_PMC72                         (0x0004u)
+#define GPIO_PMC7_PMC73                         (0x0008u)
+#define GPIO_PMC7_PMC74                         (0x0010u)
+#define GPIO_PMC7_PMC75                         (0x0020u)
+#define GPIO_PMC7_PMC76                         (0x0040u)
+#define GPIO_PMC7_PMC77                         (0x0080u)
+#define GPIO_PMC7_PMC78                         (0x0100u)
+#define GPIO_PMC7_PMC79                         (0x0200u)
+#define GPIO_PMC7_PMC710                        (0x0400u)
+#define GPIO_PMC7_PMC711                        (0x0800u)
+#define GPIO_PMC7_PMC712                        (0x1000u)
+#define GPIO_PMC7_PMC713                        (0x2000u)
+#define GPIO_PMC7_PMC714                        (0x4000u)
+#define GPIO_PMC7_PMC715                        (0x8000u)
+
+#define GPIO_PFC7_PFC70                         (0x0001u)
+#define GPIO_PFC7_PFC71                         (0x0002u)
+#define GPIO_PFC7_PFC72                         (0x0004u)
+#define GPIO_PFC7_PFC73                         (0x0008u)
+#define GPIO_PFC7_PFC74                         (0x0010u)
+#define GPIO_PFC7_PFC75                         (0x0020u)
+#define GPIO_PFC7_PFC76                         (0x0040u)
+#define GPIO_PFC7_PFC77                         (0x0080u)
+#define GPIO_PFC7_PFC78                         (0x0100u)
+#define GPIO_PFC7_PFC79                         (0x0200u)
+#define GPIO_PFC7_PFC710                        (0x0400u)
+#define GPIO_PFC7_PFC711                        (0x0800u)
+#define GPIO_PFC7_PFC712                        (0x1000u)
+#define GPIO_PFC7_PFC713                        (0x2000u)
+#define GPIO_PFC7_PFC714                        (0x4000u)
+#define GPIO_PFC7_PFC715                        (0x8000u)
+
+#define GPIO_PFCE7_PFCE70                       (0x0001u)
+#define GPIO_PFCE7_PFCE71                       (0x0002u)
+#define GPIO_PFCE7_PFCE72                       (0x0004u)
+#define GPIO_PFCE7_PFCE73                       (0x0008u)
+#define GPIO_PFCE7_PFCE74                       (0x0010u)
+#define GPIO_PFCE7_PFCE75                       (0x0020u)
+#define GPIO_PFCE7_PFCE76                       (0x0040u)
+#define GPIO_PFCE7_PFCE77                       (0x0080u)
+#define GPIO_PFCE7_PFCE78                       (0x0100u)
+#define GPIO_PFCE7_PFCE79                       (0x0200u)
+#define GPIO_PFCE7_PFCE710                      (0x0400u)
+#define GPIO_PFCE7_PFCE711                      (0x0800u)
+#define GPIO_PFCE7_PFCE712                      (0x1000u)
+#define GPIO_PFCE7_PFCE713                      (0x2000u)
+#define GPIO_PFCE7_PFCE714                      (0x4000u)
+#define GPIO_PFCE7_PFCE715                      (0x8000u)
+
+#define GPIO_PNOT7_PNOT70                       (0x0001u)
+#define GPIO_PNOT7_PNOT71                       (0x0002u)
+#define GPIO_PNOT7_PNOT72                       (0x0004u)
+#define GPIO_PNOT7_PNOT73                       (0x0008u)
+#define GPIO_PNOT7_PNOT74                       (0x0010u)
+#define GPIO_PNOT7_PNOT75                       (0x0020u)
+#define GPIO_PNOT7_PNOT76                       (0x0040u)
+#define GPIO_PNOT7_PNOT77                       (0x0080u)
+#define GPIO_PNOT7_PNOT78                       (0x0100u)
+#define GPIO_PNOT7_PNOT79                       (0x0200u)
+#define GPIO_PNOT7_PNOT710                      (0x0400u)
+#define GPIO_PNOT7_PNOT711                      (0x0800u)
+#define GPIO_PNOT7_PNOT712                      (0x1000u)
+#define GPIO_PNOT7_PNOT713                      (0x2000u)
+#define GPIO_PNOT7_PNOT714                      (0x4000u)
+#define GPIO_PNOT7_PNOT715                      (0x8000u)
+
+#define GPIO_PMSR7_PMSR70                       (0x00000001uL)
+#define GPIO_PMSR7_PMSR71                       (0x00000002uL)
+#define GPIO_PMSR7_PMSR72                       (0x00000004uL)
+#define GPIO_PMSR7_PMSR73                       (0x00000008uL)
+#define GPIO_PMSR7_PMSR74                       (0x00000010uL)
+#define GPIO_PMSR7_PMSR75                       (0x00000020uL)
+#define GPIO_PMSR7_PMSR76                       (0x00000040uL)
+#define GPIO_PMSR7_PMSR77                       (0x00000080uL)
+#define GPIO_PMSR7_PMSR78                       (0x00000100uL)
+#define GPIO_PMSR7_PMSR79                       (0x00000200uL)
+#define GPIO_PMSR7_PMSR710                      (0x00000400uL)
+#define GPIO_PMSR7_PMSR711                      (0x00000800uL)
+#define GPIO_PMSR7_PMSR712                      (0x00001000uL)
+#define GPIO_PMSR7_PMSR713                      (0x00002000uL)
+#define GPIO_PMSR7_PMSR714                      (0x00004000uL)
+#define GPIO_PMSR7_PMSR715                      (0x00008000uL)
+#define GPIO_PMSR7_PMSR716                      (0x00010000uL)
+#define GPIO_PMSR7_PMSR717                      (0x00020000uL)
+#define GPIO_PMSR7_PMSR718                      (0x00040000uL)
+#define GPIO_PMSR7_PMSR719                      (0x00080000uL)
+#define GPIO_PMSR7_PMSR720                      (0x00100000uL)
+#define GPIO_PMSR7_PMSR721                      (0x00200000uL)
+#define GPIO_PMSR7_PMSR722                      (0x00400000uL)
+#define GPIO_PMSR7_PMSR723                      (0x00800000uL)
+#define GPIO_PMSR7_PMSR724                      (0x01000000uL)
+#define GPIO_PMSR7_PMSR725                      (0x02000000uL)
+#define GPIO_PMSR7_PMSR726                      (0x04000000uL)
+#define GPIO_PMSR7_PMSR727                      (0x08000000uL)
+#define GPIO_PMSR7_PMSR728                      (0x10000000uL)
+#define GPIO_PMSR7_PMSR729                      (0x20000000uL)
+#define GPIO_PMSR7_PMSR730                      (0x40000000uL)
+#define GPIO_PMSR7_PMSR731                      (0x80000000uL)
+
+#define GPIO_PMCSR7_PMCSR70                     (0x00000001uL)
+#define GPIO_PMCSR7_PMCSR71                     (0x00000002uL)
+#define GPIO_PMCSR7_PMCSR72                     (0x00000004uL)
+#define GPIO_PMCSR7_PMCSR73                     (0x00000008uL)
+#define GPIO_PMCSR7_PMCSR74                     (0x00000010uL)
+#define GPIO_PMCSR7_PMCSR75                     (0x00000020uL)
+#define GPIO_PMCSR7_PMCSR76                     (0x00000040uL)
+#define GPIO_PMCSR7_PMCSR77                     (0x00000080uL)
+#define GPIO_PMCSR7_PMCSR78                     (0x00000100uL)
+#define GPIO_PMCSR7_PMCSR79                     (0x00000200uL)
+#define GPIO_PMCSR7_PMCSR710                    (0x00000400uL)
+#define GPIO_PMCSR7_PMCSR711                    (0x00000800uL)
+#define GPIO_PMCSR7_PMCSR712                    (0x00001000uL)
+#define GPIO_PMCSR7_PMCSR713                    (0x00002000uL)
+#define GPIO_PMCSR7_PMCSR714                    (0x00004000uL)
+#define GPIO_PMCSR7_PMCSR715                    (0x00008000uL)
+#define GPIO_PMCSR7_PMCSR716                    (0x00010000uL)
+#define GPIO_PMCSR7_PMCSR717                    (0x00020000uL)
+#define GPIO_PMCSR7_PMCSR718                    (0x00040000uL)
+#define GPIO_PMCSR7_PMCSR719                    (0x00080000uL)
+#define GPIO_PMCSR7_PMCSR720                    (0x00100000uL)
+#define GPIO_PMCSR7_PMCSR721                    (0x00200000uL)
+#define GPIO_PMCSR7_PMCSR722                    (0x00400000uL)
+#define GPIO_PMCSR7_PMCSR723                    (0x00800000uL)
+#define GPIO_PMCSR7_PMCSR724                    (0x01000000uL)
+#define GPIO_PMCSR7_PMCSR725                    (0x02000000uL)
+#define GPIO_PMCSR7_PMCSR726                    (0x04000000uL)
+#define GPIO_PMCSR7_PMCSR727                    (0x08000000uL)
+#define GPIO_PMCSR7_PMCSR728                    (0x10000000uL)
+#define GPIO_PMCSR7_PMCSR729                    (0x20000000uL)
+#define GPIO_PMCSR7_PMCSR730                    (0x40000000uL)
+#define GPIO_PMCSR7_PMCSR731                    (0x80000000uL)
+
+#define GPIO_PFCAE7_PFCAE70                     (0x0001u)
+#define GPIO_PFCAE7_PFCAE71                     (0x0002u)
+#define GPIO_PFCAE7_PFCAE72                     (0x0004u)
+#define GPIO_PFCAE7_PFCAE73                     (0x0008u)
+#define GPIO_PFCAE7_PFCAE74                     (0x0010u)
+#define GPIO_PFCAE7_PFCAE75                     (0x0020u)
+#define GPIO_PFCAE7_PFCAE76                     (0x0040u)
+#define GPIO_PFCAE7_PFCAE77                     (0x0080u)
+#define GPIO_PFCAE7_PFCAE78                     (0x0100u)
+#define GPIO_PFCAE7_PFCAE79                     (0x0200u)
+#define GPIO_PFCAE7_PFCAE710                    (0x0400u)
+#define GPIO_PFCAE7_PFCAE711                    (0x0800u)
+#define GPIO_PFCAE7_PFCAE712                    (0x1000u)
+#define GPIO_PFCAE7_PFCAE713                    (0x2000u)
+#define GPIO_PFCAE7_PFCAE714                    (0x4000u)
+#define GPIO_PFCAE7_PFCAE715                    (0x8000u)
+
+#define GPIO_PIBC7_PIBC70                       (0x0001u)
+#define GPIO_PIBC7_PIBC71                       (0x0002u)
+#define GPIO_PIBC7_PIBC72                       (0x0004u)
+#define GPIO_PIBC7_PIBC73                       (0x0008u)
+#define GPIO_PIBC7_PIBC74                       (0x0010u)
+#define GPIO_PIBC7_PIBC75                       (0x0020u)
+#define GPIO_PIBC7_PIBC76                       (0x0040u)
+#define GPIO_PIBC7_PIBC77                       (0x0080u)
+#define GPIO_PIBC7_PIBC78                       (0x0100u)
+#define GPIO_PIBC7_PIBC79                       (0x0200u)
+#define GPIO_PIBC7_PIBC710                      (0x0400u)
+#define GPIO_PIBC7_PIBC711                      (0x0800u)
+#define GPIO_PIBC7_PIBC712                      (0x1000u)
+#define GPIO_PIBC7_PIBC713                      (0x2000u)
+#define GPIO_PIBC7_PIBC714                      (0x4000u)
+#define GPIO_PIBC7_PIBC715                      (0x8000u)
+
+#define GPIO_PBDC7_PBDC70                       (0x0001u)
+#define GPIO_PBDC7_PBDC71                       (0x0002u)
+#define GPIO_PBDC7_PBDC72                       (0x0004u)
+#define GPIO_PBDC7_PBDC73                       (0x0008u)
+#define GPIO_PBDC7_PBDC74                       (0x0010u)
+#define GPIO_PBDC7_PBDC75                       (0x0020u)
+#define GPIO_PBDC7_PBDC76                       (0x0040u)
+#define GPIO_PBDC7_PBDC77                       (0x0080u)
+#define GPIO_PBDC7_PBDC78                       (0x0100u)
+#define GPIO_PBDC7_PBDC79                       (0x0200u)
+#define GPIO_PBDC7_PBDC710                      (0x0400u)
+#define GPIO_PBDC7_PBDC711                      (0x0800u)
+#define GPIO_PBDC7_PBDC712                      (0x1000u)
+#define GPIO_PBDC7_PBDC713                      (0x2000u)
+#define GPIO_PBDC7_PBDC714                      (0x4000u)
+#define GPIO_PBDC7_PBDC715                      (0x8000u)
+
+#define GPIO_PIPC7_PIPC70                       (0x0001u)
+#define GPIO_PIPC7_PIPC71                       (0x0002u)
+#define GPIO_PIPC7_PIPC72                       (0x0004u)
+#define GPIO_PIPC7_PIPC73                       (0x0008u)
+#define GPIO_PIPC7_PIPC74                       (0x0010u)
+#define GPIO_PIPC7_PIPC75                       (0x0020u)
+#define GPIO_PIPC7_PIPC76                       (0x0040u)
+#define GPIO_PIPC7_PIPC77                       (0x0080u)
+#define GPIO_PIPC7_PIPC78                       (0x0100u)
+#define GPIO_PIPC7_PIPC79                       (0x0200u)
+#define GPIO_PIPC7_PIPC710                      (0x0400u)
+#define GPIO_PIPC7_PIPC711                      (0x0800u)
+#define GPIO_PIPC7_PIPC712                      (0x1000u)
+#define GPIO_PIPC7_PIPC713                      (0x2000u)
+#define GPIO_PIPC7_PIPC714                      (0x4000u)
+#define GPIO_PIPC7_PIPC715                      (0x8000u)
+
+/* ---- P8 ---- */
+#define GPIO_P8_P80                             (0x0001u)
+#define GPIO_P8_P81                             (0x0002u)
+#define GPIO_P8_P82                             (0x0004u)
+#define GPIO_P8_P83                             (0x0008u)
+#define GPIO_P8_P84                             (0x0010u)
+#define GPIO_P8_P85                             (0x0020u)
+#define GPIO_P8_P86                             (0x0040u)
+#define GPIO_P8_P87                             (0x0080u)
+#define GPIO_P8_P88                             (0x0100u)
+#define GPIO_P8_P89                             (0x0200u)
+#define GPIO_P8_P810                            (0x0400u)
+#define GPIO_P8_P811                            (0x0800u)
+#define GPIO_P8_P812                            (0x1000u)
+#define GPIO_P8_P813                            (0x2000u)
+#define GPIO_P8_P814                            (0x4000u)
+#define GPIO_P8_P815                            (0x8000u)
+
+#define GPIO_PSR8_PSR80                         (0x00000001uL)
+#define GPIO_PSR8_PSR81                         (0x00000002uL)
+#define GPIO_PSR8_PSR82                         (0x00000004uL)
+#define GPIO_PSR8_PSR83                         (0x00000008uL)
+#define GPIO_PSR8_PSR84                         (0x00000010uL)
+#define GPIO_PSR8_PSR85                         (0x00000020uL)
+#define GPIO_PSR8_PSR86                         (0x00000040uL)
+#define GPIO_PSR8_PSR87                         (0x00000080uL)
+#define GPIO_PSR8_PSR88                         (0x00000100uL)
+#define GPIO_PSR8_PSR89                         (0x00000200uL)
+#define GPIO_PSR8_PSR810                        (0x00000400uL)
+#define GPIO_PSR8_PSR811                        (0x00000800uL)
+#define GPIO_PSR8_PSR812                        (0x00001000uL)
+#define GPIO_PSR8_PSR813                        (0x00002000uL)
+#define GPIO_PSR8_PSR814                        (0x00004000uL)
+#define GPIO_PSR8_PSR815                        (0x00008000uL)
+#define GPIO_PSR8_PSR816                        (0x00010000uL)
+#define GPIO_PSR8_PSR817                        (0x00020000uL)
+#define GPIO_PSR8_PSR818                        (0x00040000uL)
+#define GPIO_PSR8_PSR819                        (0x00080000uL)
+#define GPIO_PSR8_PSR820                        (0x00100000uL)
+#define GPIO_PSR8_PSR821                        (0x00200000uL)
+#define GPIO_PSR8_PSR822                        (0x00400000uL)
+#define GPIO_PSR8_PSR823                        (0x00800000uL)
+#define GPIO_PSR8_PSR824                        (0x01000000uL)
+#define GPIO_PSR8_PSR825                        (0x02000000uL)
+#define GPIO_PSR8_PSR826                        (0x04000000uL)
+#define GPIO_PSR8_PSR827                        (0x08000000uL)
+#define GPIO_PSR8_PSR828                        (0x10000000uL)
+#define GPIO_PSR8_PSR829                        (0x20000000uL)
+#define GPIO_PSR8_PSR830                        (0x40000000uL)
+#define GPIO_PSR8_PSR831                        (0x80000000uL)
+
+#define GPIO_PPR8_PPR80                         (0x0001u)
+#define GPIO_PPR8_PPR81                         (0x0002u)
+#define GPIO_PPR8_PPR82                         (0x0004u)
+#define GPIO_PPR8_PPR83                         (0x0008u)
+#define GPIO_PPR8_PPR84                         (0x0010u)
+#define GPIO_PPR8_PPR85                         (0x0020u)
+#define GPIO_PPR8_PPR86                         (0x0040u)
+#define GPIO_PPR8_PPR87                         (0x0080u)
+#define GPIO_PPR8_PPR88                         (0x0100u)
+#define GPIO_PPR8_PPR89                         (0x0200u)
+#define GPIO_PPR8_PPR810                        (0x0400u)
+#define GPIO_PPR8_PPR811                        (0x0800u)
+#define GPIO_PPR8_PPR812                        (0x1000u)
+#define GPIO_PPR8_PPR813                        (0x2000u)
+#define GPIO_PPR8_PPR814                        (0x4000u)
+#define GPIO_PPR8_PPR815                        (0x8000u)
+
+#define GPIO_PM8_PM80                           (0x0001u)
+#define GPIO_PM8_PM81                           (0x0002u)
+#define GPIO_PM8_PM82                           (0x0004u)
+#define GPIO_PM8_PM83                           (0x0008u)
+#define GPIO_PM8_PM84                           (0x0010u)
+#define GPIO_PM8_PM85                           (0x0020u)
+#define GPIO_PM8_PM86                           (0x0040u)
+#define GPIO_PM8_PM87                           (0x0080u)
+#define GPIO_PM8_PM88                           (0x0100u)
+#define GPIO_PM8_PM89                           (0x0200u)
+#define GPIO_PM8_PM810                          (0x0400u)
+#define GPIO_PM8_PM811                          (0x0800u)
+#define GPIO_PM8_PM812                          (0x1000u)
+#define GPIO_PM8_PM813                          (0x2000u)
+#define GPIO_PM8_PM814                          (0x4000u)
+#define GPIO_PM8_PM815                          (0x8000u)
+
+#define GPIO_PMC8_PMC80                         (0x0001u)
+#define GPIO_PMC8_PMC81                         (0x0002u)
+#define GPIO_PMC8_PMC82                         (0x0004u)
+#define GPIO_PMC8_PMC83                         (0x0008u)
+#define GPIO_PMC8_PMC84                         (0x0010u)
+#define GPIO_PMC8_PMC85                         (0x0020u)
+#define GPIO_PMC8_PMC86                         (0x0040u)
+#define GPIO_PMC8_PMC87                         (0x0080u)
+#define GPIO_PMC8_PMC88                         (0x0100u)
+#define GPIO_PMC8_PMC89                         (0x0200u)
+#define GPIO_PMC8_PMC810                        (0x0400u)
+#define GPIO_PMC8_PMC811                        (0x0800u)
+#define GPIO_PMC8_PMC812                        (0x1000u)
+#define GPIO_PMC8_PMC813                        (0x2000u)
+#define GPIO_PMC8_PMC814                        (0x4000u)
+#define GPIO_PMC8_PMC815                        (0x8000u)
+
+#define GPIO_PFC8_PFC80                         (0x0001u)
+#define GPIO_PFC8_PFC81                         (0x0002u)
+#define GPIO_PFC8_PFC82                         (0x0004u)
+#define GPIO_PFC8_PFC83                         (0x0008u)
+#define GPIO_PFC8_PFC84                         (0x0010u)
+#define GPIO_PFC8_PFC85                         (0x0020u)
+#define GPIO_PFC8_PFC86                         (0x0040u)
+#define GPIO_PFC8_PFC87                         (0x0080u)
+#define GPIO_PFC8_PFC88                         (0x0100u)
+#define GPIO_PFC8_PFC89                         (0x0200u)
+#define GPIO_PFC8_PFC810                        (0x0400u)
+#define GPIO_PFC8_PFC811                        (0x0800u)
+#define GPIO_PFC8_PFC812                        (0x1000u)
+#define GPIO_PFC8_PFC813                        (0x2000u)
+#define GPIO_PFC8_PFC814                        (0x4000u)
+#define GPIO_PFC8_PFC815                        (0x8000u)
+
+#define GPIO_PFCE8_PFCE80                       (0x0001u)
+#define GPIO_PFCE8_PFCE81                       (0x0002u)
+#define GPIO_PFCE8_PFCE82                       (0x0004u)
+#define GPIO_PFCE8_PFCE83                       (0x0008u)
+#define GPIO_PFCE8_PFCE84                       (0x0010u)
+#define GPIO_PFCE8_PFCE85                       (0x0020u)
+#define GPIO_PFCE8_PFCE86                       (0x0040u)
+#define GPIO_PFCE8_PFCE87                       (0x0080u)
+#define GPIO_PFCE8_PFCE88                       (0x0100u)
+#define GPIO_PFCE8_PFCE89                       (0x0200u)
+#define GPIO_PFCE8_PFCE810                      (0x0400u)
+#define GPIO_PFCE8_PFCE811                      (0x0800u)
+#define GPIO_PFCE8_PFCE812                      (0x1000u)
+#define GPIO_PFCE8_PFCE813                      (0x2000u)
+#define GPIO_PFCE8_PFCE814                      (0x4000u)
+#define GPIO_PFCE8_PFCE815                      (0x8000u)
+
+#define GPIO_PNOT8_PNOT80                       (0x0001u)
+#define GPIO_PNOT8_PNOT81                       (0x0002u)
+#define GPIO_PNOT8_PNOT82                       (0x0004u)
+#define GPIO_PNOT8_PNOT83                       (0x0008u)
+#define GPIO_PNOT8_PNOT84                       (0x0010u)
+#define GPIO_PNOT8_PNOT85                       (0x0020u)
+#define GPIO_PNOT8_PNOT86                       (0x0040u)
+#define GPIO_PNOT8_PNOT87                       (0x0080u)
+#define GPIO_PNOT8_PNOT88                       (0x0100u)
+#define GPIO_PNOT8_PNOT89                       (0x0200u)
+#define GPIO_PNOT8_PNOT810                      (0x0400u)
+#define GPIO_PNOT8_PNOT811                      (0x0800u)
+#define GPIO_PNOT8_PNOT812                      (0x1000u)
+#define GPIO_PNOT8_PNOT813                      (0x2000u)
+#define GPIO_PNOT8_PNOT814                      (0x4000u)
+#define GPIO_PNOT8_PNOT815                      (0x8000u)
+
+#define GPIO_PMSR8_PMSR80                       (0x00000001uL)
+#define GPIO_PMSR8_PMSR81                       (0x00000002uL)
+#define GPIO_PMSR8_PMSR82                       (0x00000004uL)
+#define GPIO_PMSR8_PMSR83                       (0x00000008uL)
+#define GPIO_PMSR8_PMSR84                       (0x00000010uL)
+#define GPIO_PMSR8_PMSR85                       (0x00000020uL)
+#define GPIO_PMSR8_PMSR86                       (0x00000040uL)
+#define GPIO_PMSR8_PMSR87                       (0x00000080uL)
+#define GPIO_PMSR8_PMSR88                       (0x00000100uL)
+#define GPIO_PMSR8_PMSR89                       (0x00000200uL)
+#define GPIO_PMSR8_PMSR810                      (0x00000400uL)
+#define GPIO_PMSR8_PMSR811                      (0x00000800uL)
+#define GPIO_PMSR8_PMSR812                      (0x00001000uL)
+#define GPIO_PMSR8_PMSR813                      (0x00002000uL)
+#define GPIO_PMSR8_PMSR814                      (0x00004000uL)
+#define GPIO_PMSR8_PMSR815                      (0x00008000uL)
+#define GPIO_PMSR8_PMSR816                      (0x00010000uL)
+#define GPIO_PMSR8_PMSR817                      (0x00020000uL)
+#define GPIO_PMSR8_PMSR818                      (0x00040000uL)
+#define GPIO_PMSR8_PMSR819                      (0x00080000uL)
+#define GPIO_PMSR8_PMSR820                      (0x00100000uL)
+#define GPIO_PMSR8_PMSR821                      (0x00200000uL)
+#define GPIO_PMSR8_PMSR822                      (0x00400000uL)
+#define GPIO_PMSR8_PMSR823                      (0x00800000uL)
+#define GPIO_PMSR8_PMSR824                      (0x01000000uL)
+#define GPIO_PMSR8_PMSR825                      (0x02000000uL)
+#define GPIO_PMSR8_PMSR826                      (0x04000000uL)
+#define GPIO_PMSR8_PMSR827                      (0x08000000uL)
+#define GPIO_PMSR8_PMSR828                      (0x10000000uL)
+#define GPIO_PMSR8_PMSR829                      (0x20000000uL)
+#define GPIO_PMSR8_PMSR830                      (0x40000000uL)
+#define GPIO_PMSR8_PMSR831                      (0x80000000uL)
+
+#define GPIO_PMCSR8_PMCSR80                     (0x00000001uL)
+#define GPIO_PMCSR8_PMCSR81                     (0x00000002uL)
+#define GPIO_PMCSR8_PMCSR82                     (0x00000004uL)
+#define GPIO_PMCSR8_PMCSR83                     (0x00000008uL)
+#define GPIO_PMCSR8_PMCSR84                     (0x00000010uL)
+#define GPIO_PMCSR8_PMCSR85                     (0x00000020uL)
+#define GPIO_PMCSR8_PMCSR86                     (0x00000040uL)
+#define GPIO_PMCSR8_PMCSR87                     (0x00000080uL)
+#define GPIO_PMCSR8_PMCSR88                     (0x00000100uL)
+#define GPIO_PMCSR8_PMCSR89                     (0x00000200uL)
+#define GPIO_PMCSR8_PMCSR810                    (0x00000400uL)
+#define GPIO_PMCSR8_PMCSR811                    (0x00000800uL)
+#define GPIO_PMCSR8_PMCSR812                    (0x00001000uL)
+#define GPIO_PMCSR8_PMCSR813                    (0x00002000uL)
+#define GPIO_PMCSR8_PMCSR814                    (0x00004000uL)
+#define GPIO_PMCSR8_PMCSR815                    (0x00008000uL)
+#define GPIO_PMCSR8_PMCSR816                    (0x00010000uL)
+#define GPIO_PMCSR8_PMCSR817                    (0x00020000uL)
+#define GPIO_PMCSR8_PMCSR818                    (0x00040000uL)
+#define GPIO_PMCSR8_PMCSR819                    (0x00080000uL)
+#define GPIO_PMCSR8_PMCSR820                    (0x00100000uL)
+#define GPIO_PMCSR8_PMCSR821                    (0x00200000uL)
+#define GPIO_PMCSR8_PMCSR822                    (0x00400000uL)
+#define GPIO_PMCSR8_PMCSR823                    (0x00800000uL)
+#define GPIO_PMCSR8_PMCSR824                    (0x01000000uL)
+#define GPIO_PMCSR8_PMCSR825                    (0x02000000uL)
+#define GPIO_PMCSR8_PMCSR826                    (0x04000000uL)
+#define GPIO_PMCSR8_PMCSR827                    (0x08000000uL)
+#define GPIO_PMCSR8_PMCSR828                    (0x10000000uL)
+#define GPIO_PMCSR8_PMCSR829                    (0x20000000uL)
+#define GPIO_PMCSR8_PMCSR830                    (0x40000000uL)
+#define GPIO_PMCSR8_PMCSR831                    (0x80000000uL)
+
+#define GPIO_PFCAE8_PFCAE80                     (0x0001u)
+#define GPIO_PFCAE8_PFCAE81                     (0x0002u)
+#define GPIO_PFCAE8_PFCAE82                     (0x0004u)
+#define GPIO_PFCAE8_PFCAE83                     (0x0008u)
+#define GPIO_PFCAE8_PFCAE84                     (0x0010u)
+#define GPIO_PFCAE8_PFCAE85                     (0x0020u)
+#define GPIO_PFCAE8_PFCAE86                     (0x0040u)
+#define GPIO_PFCAE8_PFCAE87                     (0x0080u)
+#define GPIO_PFCAE8_PFCAE88                     (0x0100u)
+#define GPIO_PFCAE8_PFCAE89                     (0x0200u)
+#define GPIO_PFCAE8_PFCAE810                    (0x0400u)
+#define GPIO_PFCAE8_PFCAE811                    (0x0800u)
+#define GPIO_PFCAE8_PFCAE812                    (0x1000u)
+#define GPIO_PFCAE8_PFCAE813                    (0x2000u)
+#define GPIO_PFCAE8_PFCAE814                    (0x4000u)
+#define GPIO_PFCAE8_PFCAE815                    (0x8000u)
+
+#define GPIO_PIBC8_PIBC80                       (0x0001u)
+#define GPIO_PIBC8_PIBC81                       (0x0002u)
+#define GPIO_PIBC8_PIBC82                       (0x0004u)
+#define GPIO_PIBC8_PIBC83                       (0x0008u)
+#define GPIO_PIBC8_PIBC84                       (0x0010u)
+#define GPIO_PIBC8_PIBC85                       (0x0020u)
+#define GPIO_PIBC8_PIBC86                       (0x0040u)
+#define GPIO_PIBC8_PIBC87                       (0x0080u)
+#define GPIO_PIBC8_PIBC88                       (0x0100u)
+#define GPIO_PIBC8_PIBC89                       (0x0200u)
+#define GPIO_PIBC8_PIBC810                      (0x0400u)
+#define GPIO_PIBC8_PIBC811                      (0x0800u)
+#define GPIO_PIBC8_PIBC812                      (0x1000u)
+#define GPIO_PIBC8_PIBC813                      (0x2000u)
+#define GPIO_PIBC8_PIBC814                      (0x4000u)
+#define GPIO_PIBC8_PIBC815                      (0x8000u)
+
+#define GPIO_PBDC8_PBDC80                       (0x0001u)
+#define GPIO_PBDC8_PBDC81                       (0x0002u)
+#define GPIO_PBDC8_PBDC82                       (0x0004u)
+#define GPIO_PBDC8_PBDC83                       (0x0008u)
+#define GPIO_PBDC8_PBDC84                       (0x0010u)
+#define GPIO_PBDC8_PBDC85                       (0x0020u)
+#define GPIO_PBDC8_PBDC86                       (0x0040u)
+#define GPIO_PBDC8_PBDC87                       (0x0080u)
+#define GPIO_PBDC8_PBDC88                       (0x0100u)
+#define GPIO_PBDC8_PBDC89                       (0x0200u)
+#define GPIO_PBDC8_PBDC810                      (0x0400u)
+#define GPIO_PBDC8_PBDC811                      (0x0800u)
+#define GPIO_PBDC8_PBDC812                      (0x1000u)
+#define GPIO_PBDC8_PBDC813                      (0x2000u)
+#define GPIO_PBDC8_PBDC814                      (0x4000u)
+#define GPIO_PBDC8_PBDC815                      (0x8000u)
+
+#define GPIO_PIPC8_PIPC80                       (0x0001u)
+#define GPIO_PIPC8_PIPC81                       (0x0002u)
+#define GPIO_PIPC8_PIPC82                       (0x0004u)
+#define GPIO_PIPC8_PIPC83                       (0x0008u)
+#define GPIO_PIPC8_PIPC84                       (0x0010u)
+#define GPIO_PIPC8_PIPC85                       (0x0020u)
+#define GPIO_PIPC8_PIPC86                       (0x0040u)
+#define GPIO_PIPC8_PIPC87                       (0x0080u)
+#define GPIO_PIPC8_PIPC88                       (0x0100u)
+#define GPIO_PIPC8_PIPC89                       (0x0200u)
+#define GPIO_PIPC8_PIPC810                      (0x0400u)
+#define GPIO_PIPC8_PIPC811                      (0x0800u)
+#define GPIO_PIPC8_PIPC812                      (0x1000u)
+#define GPIO_PIPC8_PIPC813                      (0x2000u)
+#define GPIO_PIPC8_PIPC814                      (0x4000u)
+#define GPIO_PIPC8_PIPC815                      (0x8000u)
+
+/* ---- P9 ---- */
+#define GPIO_P9_P90                             (0x0001u)
+#define GPIO_P9_P91                             (0x0002u)
+#define GPIO_P9_P92                             (0x0004u)
+#define GPIO_P9_P93                             (0x0008u)
+#define GPIO_P9_P94                             (0x0010u)
+#define GPIO_P9_P95                             (0x0020u)
+#define GPIO_P9_P96                             (0x0040u)
+#define GPIO_P9_P97                             (0x0080u)
+
+#define GPIO_PSR9_PSR90                         (0x00000001uL)
+#define GPIO_PSR9_PSR91                         (0x00000002uL)
+#define GPIO_PSR9_PSR92                         (0x00000004uL)
+#define GPIO_PSR9_PSR93                         (0x00000008uL)
+#define GPIO_PSR9_PSR94                         (0x00000010uL)
+#define GPIO_PSR9_PSR95                         (0x00000020uL)
+#define GPIO_PSR9_PSR96                         (0x00000040uL)
+#define GPIO_PSR9_PSR97                         (0x00000080uL)
+#define GPIO_PSR9_PSR916                        (0x00010000uL)
+#define GPIO_PSR9_PSR917                        (0x00020000uL)
+#define GPIO_PSR9_PSR918                        (0x00040000uL)
+#define GPIO_PSR9_PSR919                        (0x00080000uL)
+#define GPIO_PSR9_PSR920                        (0x00100000uL)
+#define GPIO_PSR9_PSR921                        (0x00200000uL)
+#define GPIO_PSR9_PSR922                        (0x00400000uL)
+#define GPIO_PSR9_PSR923                        (0x00800000uL)
+
+#define GPIO_PPR9_PPR90                         (0x0001u)
+#define GPIO_PPR9_PPR91                         (0x0002u)
+#define GPIO_PPR9_PPR92                         (0x0004u)
+#define GPIO_PPR9_PPR93                         (0x0008u)
+#define GPIO_PPR9_PPR94                         (0x0010u)
+#define GPIO_PPR9_PPR95                         (0x0020u)
+#define GPIO_PPR9_PPR96                         (0x0040u)
+#define GPIO_PPR9_PPR97                         (0x0080u)
+
+#define GPIO_PM9_PM90                           (0x0001u)
+#define GPIO_PM9_PM91                           (0x0002u)
+#define GPIO_PM9_PM92                           (0x0004u)
+#define GPIO_PM9_PM93                           (0x0008u)
+#define GPIO_PM9_PM94                           (0x0010u)
+#define GPIO_PM9_PM95                           (0x0020u)
+#define GPIO_PM9_PM96                           (0x0040u)
+#define GPIO_PM9_PM97                           (0x0080u)
+
+#define GPIO_PMC9_PMC90                         (0x0001u)
+#define GPIO_PMC9_PMC91                         (0x0002u)
+#define GPIO_PMC9_PMC92                         (0x0004u)
+#define GPIO_PMC9_PMC93                         (0x0008u)
+#define GPIO_PMC9_PMC94                         (0x0010u)
+#define GPIO_PMC9_PMC95                         (0x0020u)
+#define GPIO_PMC9_PMC96                         (0x0040u)
+#define GPIO_PMC9_PMC97                         (0x0080u)
+
+#define GPIO_PFC9_PFC90                         (0x0001u)
+#define GPIO_PFC9_PFC91                         (0x0002u)
+#define GPIO_PFC9_PFC92                         (0x0004u)
+#define GPIO_PFC9_PFC93                         (0x0008u)
+#define GPIO_PFC9_PFC94                         (0x0010u)
+#define GPIO_PFC9_PFC95                         (0x0020u)
+#define GPIO_PFC9_PFC96                         (0x0040u)
+#define GPIO_PFC9_PFC97                         (0x0080u)
+
+#define GPIO_PFCE9_PFCE90                       (0x0001u)
+#define GPIO_PFCE9_PFCE91                       (0x0002u)
+#define GPIO_PFCE9_PFCE92                       (0x0004u)
+#define GPIO_PFCE9_PFCE93                       (0x0008u)
+#define GPIO_PFCE9_PFCE94                       (0x0010u)
+#define GPIO_PFCE9_PFCE95                       (0x0020u)
+#define GPIO_PFCE9_PFCE96                       (0x0040u)
+#define GPIO_PFCE9_PFCE97                       (0x0080u)
+
+#define GPIO_PNOT9_PNOT90                       (0x0001u)
+#define GPIO_PNOT9_PNOT91                       (0x0002u)
+#define GPIO_PNOT9_PNOT92                       (0x0004u)
+#define GPIO_PNOT9_PNOT93                       (0x0008u)
+#define GPIO_PNOT9_PNOT94                       (0x0010u)
+#define GPIO_PNOT9_PNOT95                       (0x0020u)
+#define GPIO_PNOT9_PNOT96                       (0x0040u)
+#define GPIO_PNOT9_PNOT97                       (0x0080u)
+
+#define GPIO_PMSR9_PMSR90                       (0x00000001uL)
+#define GPIO_PMSR9_PMSR91                       (0x00000002uL)
+#define GPIO_PMSR9_PMSR92                       (0x00000004uL)
+#define GPIO_PMSR9_PMSR93                       (0x00000008uL)
+#define GPIO_PMSR9_PMSR94                       (0x00000010uL)
+#define GPIO_PMSR9_PMSR95                       (0x00000020uL)
+#define GPIO_PMSR9_PMSR96                       (0x00000040uL)
+#define GPIO_PMSR9_PMSR97                       (0x00000080uL)
+#define GPIO_PMSR9_PMSR916                      (0x00010000uL)
+#define GPIO_PMSR9_PMSR917                      (0x00020000uL)
+#define GPIO_PMSR9_PMSR918                      (0x00040000uL)
+#define GPIO_PMSR9_PMSR919                      (0x00080000uL)
+#define GPIO_PMSR9_PMSR920                      (0x00100000uL)
+#define GPIO_PMSR9_PMSR921                      (0x00200000uL)
+#define GPIO_PMSR9_PMSR922                      (0x00400000uL)
+#define GPIO_PMSR9_PMSR923                      (0x00800000uL)
+
+#define GPIO_PMCSR9_PMCSR90                     (0x00000001uL)
+#define GPIO_PMCSR9_PMCSR91                     (0x00000002uL)
+#define GPIO_PMCSR9_PMCSR92                     (0x00000004uL)
+#define GPIO_PMCSR9_PMCSR93                     (0x00000008uL)
+#define GPIO_PMCSR9_PMCSR94                     (0x00000010uL)
+#define GPIO_PMCSR9_PMCSR95                     (0x00000020uL)
+#define GPIO_PMCSR9_PMCSR96                     (0x00000040uL)
+#define GPIO_PMCSR9_PMCSR97                     (0x00000080uL)
+#define GPIO_PMCSR9_PMCSR916                    (0x00010000uL)
+#define GPIO_PMCSR9_PMCSR917                    (0x00020000uL)
+#define GPIO_PMCSR9_PMCSR918                    (0x00040000uL)
+#define GPIO_PMCSR9_PMCSR919                    (0x00080000uL)
+#define GPIO_PMCSR9_PMCSR920                    (0x00100000uL)
+#define GPIO_PMCSR9_PMCSR921                    (0x00200000uL)
+#define GPIO_PMCSR9_PMCSR922                    (0x00400000uL)
+#define GPIO_PMCSR9_PMCSR923                    (0x00800000uL)
+
+#define GPIO_PFCAE9_PFCAE90                     (0x0001u)
+#define GPIO_PFCAE9_PFCAE91                     (0x0002u)
+#define GPIO_PFCAE9_PFCAE92                     (0x0004u)
+#define GPIO_PFCAE9_PFCAE93                     (0x0008u)
+#define GPIO_PFCAE9_PFCAE94                     (0x0010u)
+#define GPIO_PFCAE9_PFCAE95                     (0x0020u)
+#define GPIO_PFCAE9_PFCAE96                     (0x0040u)
+#define GPIO_PFCAE9_PFCAE97                     (0x0080u)
+
+#define GPIO_PIBC9_PIBC90                       (0x0001u)
+#define GPIO_PIBC9_PIBC91                       (0x0002u)
+#define GPIO_PIBC9_PIBC92                       (0x0004u)
+#define GPIO_PIBC9_PIBC93                       (0x0008u)
+#define GPIO_PIBC9_PIBC94                       (0x0010u)
+#define GPIO_PIBC9_PIBC95                       (0x0020u)
+#define GPIO_PIBC9_PIBC96                       (0x0040u)
+#define GPIO_PIBC9_PIBC97                       (0x0080u)
+
+#define GPIO_PBDC9_PBDC90                       (0x0001u)
+#define GPIO_PBDC9_PBDC91                       (0x0002u)
+#define GPIO_PBDC9_PBDC92                       (0x0004u)
+#define GPIO_PBDC9_PBDC93                       (0x0008u)
+#define GPIO_PBDC9_PBDC94                       (0x0010u)
+#define GPIO_PBDC9_PBDC95                       (0x0020u)
+#define GPIO_PBDC9_PBDC96                       (0x0040u)
+#define GPIO_PBDC9_PBDC97                       (0x0080u)
+
+#define GPIO_PIPC9_PIPC90                       (0x0001u)
+#define GPIO_PIPC9_PIPC91                       (0x0002u)
+#define GPIO_PIPC9_PIPC92                       (0x0004u)
+#define GPIO_PIPC9_PIPC93                       (0x0008u)
+#define GPIO_PIPC9_PIPC94                       (0x0010u)
+#define GPIO_PIPC9_PIPC95                       (0x0020u)
+#define GPIO_PIPC9_PIPC96                       (0x0040u)
+#define GPIO_PIPC9_PIPC97                       (0x0080u)
+
+/* ---- P10 ---- */
+#define GPIO_P10_P100                           (0x0001u)
+#define GPIO_P10_P101                           (0x0002u)
+#define GPIO_P10_P102                           (0x0004u)
+#define GPIO_P10_P103                           (0x0008u)
+#define GPIO_P10_P104                           (0x0010u)
+#define GPIO_P10_P105                           (0x0020u)
+#define GPIO_P10_P106                           (0x0040u)
+#define GPIO_P10_P107                           (0x0080u)
+#define GPIO_P10_P108                           (0x0100u)
+#define GPIO_P10_P109                           (0x0200u)
+#define GPIO_P10_P1010                          (0x0400u)
+#define GPIO_P10_P1011                          (0x0800u)
+#define GPIO_P10_P1012                          (0x1000u)
+#define GPIO_P10_P1013                          (0x2000u)
+#define GPIO_P10_P1014                          (0x4000u)
+#define GPIO_P10_P1015                          (0x8000u)
+
+#define GPIO_PSR10_PSR100                       (0x00000001uL)
+#define GPIO_PSR10_PSR101                       (0x00000002uL)
+#define GPIO_PSR10_PSR102                       (0x00000004uL)
+#define GPIO_PSR10_PSR103                       (0x00000008uL)
+#define GPIO_PSR10_PSR104                       (0x00000010uL)
+#define GPIO_PSR10_PSR105                       (0x00000020uL)
+#define GPIO_PSR10_PSR106                       (0x00000040uL)
+#define GPIO_PSR10_PSR107                       (0x00000080uL)
+#define GPIO_PSR10_PSR108                       (0x00000100uL)
+#define GPIO_PSR10_PSR109                       (0x00000200uL)
+#define GPIO_PSR10_PSR1010                      (0x00000400uL)
+#define GPIO_PSR10_PSR1011                      (0x00000800uL)
+#define GPIO_PSR10_PSR1012                      (0x00001000uL)
+#define GPIO_PSR10_PSR1013                      (0x00002000uL)
+#define GPIO_PSR10_PSR1014                      (0x00004000uL)
+#define GPIO_PSR10_PSR1015                      (0x00008000uL)
+#define GPIO_PSR10_PSR1016                      (0x00010000uL)
+#define GPIO_PSR10_PSR1017                      (0x00020000uL)
+#define GPIO_PSR10_PSR1018                      (0x00040000uL)
+#define GPIO_PSR10_PSR1019                      (0x00080000uL)
+#define GPIO_PSR10_PSR1020                      (0x00100000uL)
+#define GPIO_PSR10_PSR1021                      (0x00200000uL)
+#define GPIO_PSR10_PSR1022                      (0x00400000uL)
+#define GPIO_PSR10_PSR1023                      (0x00800000uL)
+#define GPIO_PSR10_PSR1024                      (0x01000000uL)
+#define GPIO_PSR10_PSR1025                      (0x02000000uL)
+#define GPIO_PSR10_PSR1026                      (0x04000000uL)
+#define GPIO_PSR10_PSR1027                      (0x08000000uL)
+#define GPIO_PSR10_PSR1028                      (0x10000000uL)
+#define GPIO_PSR10_PSR1029                      (0x20000000uL)
+#define GPIO_PSR10_PSR1030                      (0x40000000uL)
+#define GPIO_PSR10_PSR1031                      (0x80000000uL)
+
+#define GPIO_PPR10_PPR100                       (0x0001u)
+#define GPIO_PPR10_PPR101                       (0x0002u)
+#define GPIO_PPR10_PPR102                       (0x0004u)
+#define GPIO_PPR10_PPR103                       (0x0008u)
+#define GPIO_PPR10_PPR104                       (0x0010u)
+#define GPIO_PPR10_PPR105                       (0x0020u)
+#define GPIO_PPR10_PPR106                       (0x0040u)
+#define GPIO_PPR10_PPR107                       (0x0080u)
+#define GPIO_PPR10_PPR108                       (0x0100u)
+#define GPIO_PPR10_PPR109                       (0x0200u)
+#define GPIO_PPR10_PPR1010                      (0x0400u)
+#define GPIO_PPR10_PPR1011                      (0x0800u)
+#define GPIO_PPR10_PPR1012                      (0x1000u)
+#define GPIO_PPR10_PPR1013                      (0x2000u)
+#define GPIO_PPR10_PPR1014                      (0x4000u)
+#define GPIO_PPR10_PPR1015                      (0x8000u)
+
+#define GPIO_PM10_PM100                         (0x0001u)
+#define GPIO_PM10_PM101                         (0x0002u)
+#define GPIO_PM10_PM102                         (0x0004u)
+#define GPIO_PM10_PM103                         (0x0008u)
+#define GPIO_PM10_PM104                         (0x0010u)
+#define GPIO_PM10_PM105                         (0x0020u)
+#define GPIO_PM10_PM106                         (0x0040u)
+#define GPIO_PM10_PM107                         (0x0080u)
+#define GPIO_PM10_PM108                         (0x0100u)
+#define GPIO_PM10_PM109                         (0x0200u)
+#define GPIO_PM10_PM1010                        (0x0400u)
+#define GPIO_PM10_PM1011                        (0x0800u)
+#define GPIO_PM10_PM1012                        (0x1000u)
+#define GPIO_PM10_PM1013                        (0x2000u)
+#define GPIO_PM10_PM1014                        (0x4000u)
+#define GPIO_PM10_PM1015                        (0x8000u)
+
+#define GPIO_PMC10_PMC100                       (0x0001u)
+#define GPIO_PMC10_PMC101                       (0x0002u)
+#define GPIO_PMC10_PMC102                       (0x0004u)
+#define GPIO_PMC10_PMC103                       (0x0008u)
+#define GPIO_PMC10_PMC104                       (0x0010u)
+#define GPIO_PMC10_PMC105                       (0x0020u)
+#define GPIO_PMC10_PMC106                       (0x0040u)
+#define GPIO_PMC10_PMC107                       (0x0080u)
+#define GPIO_PMC10_PMC108                       (0x0100u)
+#define GPIO_PMC10_PMC109                       (0x0200u)
+#define GPIO_PMC10_PMC1010                      (0x0400u)
+#define GPIO_PMC10_PMC1011                      (0x0800u)
+#define GPIO_PMC10_PMC1012                      (0x1000u)
+#define GPIO_PMC10_PMC1013                      (0x2000u)
+#define GPIO_PMC10_PMC1014                      (0x4000u)
+#define GPIO_PMC10_PMC1015                      (0x8000u)
+
+#define GPIO_PFC10_PFC100                       (0x0001u)
+#define GPIO_PFC10_PFC101                       (0x0002u)
+#define GPIO_PFC10_PFC102                       (0x0004u)
+#define GPIO_PFC10_PFC103                       (0x0008u)
+#define GPIO_PFC10_PFC104                       (0x0010u)
+#define GPIO_PFC10_PFC105                       (0x0020u)
+#define GPIO_PFC10_PFC106                       (0x0040u)
+#define GPIO_PFC10_PFC107                       (0x0080u)
+#define GPIO_PFC10_PFC108                       (0x0100u)
+#define GPIO_PFC10_PFC109                       (0x0200u)
+#define GPIO_PFC10_PFC1010                      (0x0400u)
+#define GPIO_PFC10_PFC1011                      (0x0800u)
+#define GPIO_PFC10_PFC1012                      (0x1000u)
+#define GPIO_PFC10_PFC1013                      (0x2000u)
+#define GPIO_PFC10_PFC1014                      (0x4000u)
+#define GPIO_PFC10_PFC1015                      (0x8000u)
+
+#define GPIO_PFCE10_PFCE100                     (0x0001u)
+#define GPIO_PFCE10_PFCE101                     (0x0002u)
+#define GPIO_PFCE10_PFCE102                     (0x0004u)
+#define GPIO_PFCE10_PFCE103                     (0x0008u)
+#define GPIO_PFCE10_PFCE104                     (0x0010u)
+#define GPIO_PFCE10_PFCE105                     (0x0020u)
+#define GPIO_PFCE10_PFCE106                     (0x0040u)
+#define GPIO_PFCE10_PFCE107                     (0x0080u)
+#define GPIO_PFCE10_PFCE108                     (0x0100u)
+#define GPIO_PFCE10_PFCE109                     (0x0200u)
+#define GPIO_PFCE10_PFCE1010                    (0x0400u)
+#define GPIO_PFCE10_PFCE1011                    (0x0800u)
+#define GPIO_PFCE10_PFCE1012                    (0x1000u)
+#define GPIO_PFCE10_PFCE1013                    (0x2000u)
+#define GPIO_PFCE10_PFCE1014                    (0x4000u)
+#define GPIO_PFCE10_PFCE1015                    (0x8000u)
+
+#define GPIO_PNOT10_PNOT100                     (0x0001u)
+#define GPIO_PNOT10_PNOT101                     (0x0002u)
+#define GPIO_PNOT10_PNOT102                     (0x0004u)
+#define GPIO_PNOT10_PNOT103                     (0x0008u)
+#define GPIO_PNOT10_PNOT104                     (0x0010u)
+#define GPIO_PNOT10_PNOT105                     (0x0020u)
+#define GPIO_PNOT10_PNOT106                     (0x0040u)
+#define GPIO_PNOT10_PNOT107                     (0x0080u)
+#define GPIO_PNOT10_PNOT108                     (0x0100u)
+#define GPIO_PNOT10_PNOT109                     (0x0200u)
+#define GPIO_PNOT10_PNOT1010                    (0x0400u)
+#define GPIO_PNOT10_PNOT1011                    (0x0800u)
+#define GPIO_PNOT10_PNOT1012                    (0x1000u)
+#define GPIO_PNOT10_PNOT1013                    (0x2000u)
+#define GPIO_PNOT10_PNOT1014                    (0x4000u)
+#define GPIO_PNOT10_PNOT1015                    (0x8000u)
+
+#define GPIO_PMSR10_PMSR100                     (0x00000001uL)
+#define GPIO_PMSR10_PMSR101                     (0x00000002uL)
+#define GPIO_PMSR10_PMSR102                     (0x00000004uL)
+#define GPIO_PMSR10_PMSR103                     (0x00000008uL)
+#define GPIO_PMSR10_PMSR104                     (0x00000010uL)
+#define GPIO_PMSR10_PMSR105                     (0x00000020uL)
+#define GPIO_PMSR10_PMSR106                     (0x00000040uL)
+#define GPIO_PMSR10_PMSR107                     (0x00000080uL)
+#define GPIO_PMSR10_PMSR108                     (0x00000100uL)
+#define GPIO_PMSR10_PMSR109                     (0x00000200uL)
+#define GPIO_PMSR10_PMSR1010                    (0x00000400uL)
+#define GPIO_PMSR10_PMSR1011                    (0x00000800uL)
+#define GPIO_PMSR10_PMSR1012                    (0x00001000uL)
+#define GPIO_PMSR10_PMSR1013                    (0x00002000uL)
+#define GPIO_PMSR10_PMSR1014                    (0x00004000uL)
+#define GPIO_PMSR10_PMSR1015                    (0x00008000uL)
+#define GPIO_PMSR10_PMSR1016                    (0x00010000uL)
+#define GPIO_PMSR10_PMSR1017                    (0x00020000uL)
+#define GPIO_PMSR10_PMSR1018                    (0x00040000uL)
+#define GPIO_PMSR10_PMSR1019                    (0x00080000uL)
+#define GPIO_PMSR10_PMSR1020                    (0x00100000uL)
+#define GPIO_PMSR10_PMSR1021                    (0x00200000uL)
+#define GPIO_PMSR10_PMSR1022                    (0x00400000uL)
+#define GPIO_PMSR10_PMSR1023                    (0x00800000uL)
+#define GPIO_PMSR10_PMSR1024                    (0x01000000uL)
+#define GPIO_PMSR10_PMSR1025                    (0x02000000uL)
+#define GPIO_PMSR10_PMSR1026                    (0x04000000uL)
+#define GPIO_PMSR10_PMSR1027                    (0x08000000uL)
+#define GPIO_PMSR10_PMSR1028                    (0x10000000uL)
+#define GPIO_PMSR10_PMSR1029                    (0x20000000uL)
+#define GPIO_PMSR10_PMSR1030                    (0x40000000uL)
+#define GPIO_PMSR10_PMSR1031                    (0x80000000uL)
+
+#define GPIO_PMCSR10_PMCSR100                   (0x00000001uL)
+#define GPIO_PMCSR10_PMCSR101                   (0x00000002uL)
+#define GPIO_PMCSR10_PMCSR102                   (0x00000004uL)
+#define GPIO_PMCSR10_PMCSR103                   (0x00000008uL)
+#define GPIO_PMCSR10_PMCSR104                   (0x00000010uL)
+#define GPIO_PMCSR10_PMCSR105                   (0x00000020uL)
+#define GPIO_PMCSR10_PMCSR106                   (0x00000040uL)
+#define GPIO_PMCSR10_PMCSR107                   (0x00000080uL)
+#define GPIO_PMCSR10_PMCSR108                   (0x00000100uL)
+#define GPIO_PMCSR10_PMCSR109                   (0x00000200uL)
+#define GPIO_PMCSR10_PMCSR1010                  (0x00000400uL)
+#define GPIO_PMCSR10_PMCSR1011                  (0x00000800uL)
+#define GPIO_PMCSR10_PMCSR1012                  (0x00001000uL)
+#define GPIO_PMCSR10_PMCSR1013                  (0x00002000uL)
+#define GPIO_PMCSR10_PMCSR1014                  (0x00004000uL)
+#define GPIO_PMCSR10_PMCSR1015                  (0x00008000uL)
+#define GPIO_PMCSR10_PMCSR1016                  (0x00010000uL)
+#define GPIO_PMCSR10_PMCSR1017                  (0x00020000uL)
+#define GPIO_PMCSR10_PMCSR1018                  (0x00040000uL)
+#define GPIO_PMCSR10_PMCSR1019                  (0x00080000uL)
+#define GPIO_PMCSR10_PMCSR1020                  (0x00100000uL)
+#define GPIO_PMCSR10_PMCSR1021                  (0x00200000uL)
+#define GPIO_PMCSR10_PMCSR1022                  (0x00400000uL)
+#define GPIO_PMCSR10_PMCSR1023                  (0x00800000uL)
+#define GPIO_PMCSR10_PMCSR1024                  (0x01000000uL)
+#define GPIO_PMCSR10_PMCSR1025                  (0x02000000uL)
+#define GPIO_PMCSR10_PMCSR1026                  (0x04000000uL)
+#define GPIO_PMCSR10_PMCSR1027                  (0x08000000uL)
+#define GPIO_PMCSR10_PMCSR1028                  (0x10000000uL)
+#define GPIO_PMCSR10_PMCSR1029                  (0x20000000uL)
+#define GPIO_PMCSR10_PMCSR1030                  (0x40000000uL)
+#define GPIO_PMCSR10_PMCSR1031                  (0x80000000uL)
+
+#define GPIO_PFCAE10_PFCAE100                   (0x0001u)
+#define GPIO_PFCAE10_PFCAE101                   (0x0002u)
+#define GPIO_PFCAE10_PFCAE102                   (0x0004u)
+#define GPIO_PFCAE10_PFCAE103                   (0x0008u)
+#define GPIO_PFCAE10_PFCAE104                   (0x0010u)
+#define GPIO_PFCAE10_PFCAE105                   (0x0020u)
+#define GPIO_PFCAE10_PFCAE106                   (0x0040u)
+#define GPIO_PFCAE10_PFCAE107                   (0x0080u)
+#define GPIO_PFCAE10_PFCAE108                   (0x0100u)
+#define GPIO_PFCAE10_PFCAE109                   (0x0200u)
+#define GPIO_PFCAE10_PFCAE1010                  (0x0400u)
+#define GPIO_PFCAE10_PFCAE1011                  (0x0800u)
+#define GPIO_PFCAE10_PFCAE1012                  (0x1000u)
+#define GPIO_PFCAE10_PFCAE1013                  (0x2000u)
+#define GPIO_PFCAE10_PFCAE1014                  (0x4000u)
+#define GPIO_PFCAE10_PFCAE1015                  (0x8000u)
+
+#define GPIO_PIBC10_PIBC100                     (0x0001u)
+#define GPIO_PIBC10_PIBC101                     (0x0002u)
+#define GPIO_PIBC10_PIBC102                     (0x0004u)
+#define GPIO_PIBC10_PIBC103                     (0x0008u)
+#define GPIO_PIBC10_PIBC104                     (0x0010u)
+#define GPIO_PIBC10_PIBC105                     (0x0020u)
+#define GPIO_PIBC10_PIBC106                     (0x0040u)
+#define GPIO_PIBC10_PIBC107                     (0x0080u)
+#define GPIO_PIBC10_PIBC108                     (0x0100u)
+#define GPIO_PIBC10_PIBC109                     (0x0200u)
+#define GPIO_PIBC10_PIBC1010                    (0x0400u)
+#define GPIO_PIBC10_PIBC1011                    (0x0800u)
+#define GPIO_PIBC10_PIBC1012                    (0x1000u)
+#define GPIO_PIBC10_PIBC1013                    (0x2000u)
+#define GPIO_PIBC10_PIBC1014                    (0x4000u)
+#define GPIO_PIBC10_PIBC1015                    (0x8000u)
+
+#define GPIO_PBDC10_PBDC100                     (0x0001u)
+#define GPIO_PBDC10_PBDC101                     (0x0002u)
+#define GPIO_PBDC10_PBDC102                     (0x0004u)
+#define GPIO_PBDC10_PBDC103                     (0x0008u)
+#define GPIO_PBDC10_PBDC104                     (0x0010u)
+#define GPIO_PBDC10_PBDC105                     (0x0020u)
+#define GPIO_PBDC10_PBDC106                     (0x0040u)
+#define GPIO_PBDC10_PBDC107                     (0x0080u)
+#define GPIO_PBDC10_PBDC108                     (0x0100u)
+#define GPIO_PBDC10_PBDC109                     (0x0200u)
+#define GPIO_PBDC10_PBDC1010                    (0x0400u)
+#define GPIO_PBDC10_PBDC1011                    (0x0800u)
+#define GPIO_PBDC10_PBDC1012                    (0x1000u)
+#define GPIO_PBDC10_PBDC1013                    (0x2000u)
+#define GPIO_PBDC10_PBDC1014                    (0x4000u)
+#define GPIO_PBDC10_PBDC1015                    (0x8000u)
+
+#define GPIO_PIPC10_PIPC100                     (0x0001u)
+#define GPIO_PIPC10_PIPC101                     (0x0002u)
+#define GPIO_PIPC10_PIPC102                     (0x0004u)
+#define GPIO_PIPC10_PIPC103                     (0x0008u)
+#define GPIO_PIPC10_PIPC104                     (0x0010u)
+#define GPIO_PIPC10_PIPC105                     (0x0020u)
+#define GPIO_PIPC10_PIPC106                     (0x0040u)
+#define GPIO_PIPC10_PIPC107                     (0x0080u)
+#define GPIO_PIPC10_PIPC108                     (0x0100u)
+#define GPIO_PIPC10_PIPC109                     (0x0200u)
+#define GPIO_PIPC10_PIPC1010                    (0x0400u)
+#define GPIO_PIPC10_PIPC1011                    (0x0800u)
+#define GPIO_PIPC10_PIPC1012                    (0x1000u)
+#define GPIO_PIPC10_PIPC1013                    (0x2000u)
+#define GPIO_PIPC10_PIPC1014                    (0x4000u)
+#define GPIO_PIPC10_PIPC1015                    (0x8000u)
+
+/* ---- P11 ---- */
+#define GPIO_P11_P110                           (0x0001u)
+#define GPIO_P11_P111                           (0x0002u)
+#define GPIO_P11_P112                           (0x0004u)
+#define GPIO_P11_P113                           (0x0008u)
+#define GPIO_P11_P114                           (0x0010u)
+#define GPIO_P11_P115                           (0x0020u)
+#define GPIO_P11_P116                           (0x0040u)
+#define GPIO_P11_P117                           (0x0080u)
+#define GPIO_P11_P118                           (0x0100u)
+#define GPIO_P11_P119                           (0x0200u)
+#define GPIO_P11_P1110                          (0x0400u)
+#define GPIO_P11_P1111                          (0x0800u)
+#define GPIO_P11_P1112                          (0x1000u)
+#define GPIO_P11_P1113                          (0x2000u)
+#define GPIO_P11_P1114                          (0x4000u)
+#define GPIO_P11_P1115                          (0x8000u)
+
+#define GPIO_PSR11_PSR110                       (0x00000001uL)
+#define GPIO_PSR11_PSR111                       (0x00000002uL)
+#define GPIO_PSR11_PSR112                       (0x00000004uL)
+#define GPIO_PSR11_PSR113                       (0x00000008uL)
+#define GPIO_PSR11_PSR114                       (0x00000010uL)
+#define GPIO_PSR11_PSR115                       (0x00000020uL)
+#define GPIO_PSR11_PSR116                       (0x00000040uL)
+#define GPIO_PSR11_PSR117                       (0x00000080uL)
+#define GPIO_PSR11_PSR118                       (0x00000100uL)
+#define GPIO_PSR11_PSR119                       (0x00000200uL)
+#define GPIO_PSR11_PSR1110                      (0x00000400uL)
+#define GPIO_PSR11_PSR1111                      (0x00000800uL)
+#define GPIO_PSR11_PSR1112                      (0x00001000uL)
+#define GPIO_PSR11_PSR1113                      (0x00002000uL)
+#define GPIO_PSR11_PSR1114                      (0x00004000uL)
+#define GPIO_PSR11_PSR1115                      (0x00008000uL)
+#define GPIO_PSR11_PSR1116                      (0x00010000uL)
+#define GPIO_PSR11_PSR1117                      (0x00020000uL)
+#define GPIO_PSR11_PSR1118                      (0x00040000uL)
+#define GPIO_PSR11_PSR1119                      (0x00080000uL)
+#define GPIO_PSR11_PSR1120                      (0x00100000uL)
+#define GPIO_PSR11_PSR1121                      (0x00200000uL)
+#define GPIO_PSR11_PSR1122                      (0x00400000uL)
+#define GPIO_PSR11_PSR1123                      (0x00800000uL)
+#define GPIO_PSR11_PSR1124                      (0x01000000uL)
+#define GPIO_PSR11_PSR1125                      (0x02000000uL)
+#define GPIO_PSR11_PSR1126                      (0x04000000uL)
+#define GPIO_PSR11_PSR1127                      (0x08000000uL)
+#define GPIO_PSR11_PSR1128                      (0x10000000uL)
+#define GPIO_PSR11_PSR1129                      (0x20000000uL)
+#define GPIO_PSR11_PSR1130                      (0x40000000uL)
+#define GPIO_PSR11_PSR1131                      (0x80000000uL)
+
+#define GPIO_PPR11_PPR110                       (0x0001u)
+#define GPIO_PPR11_PPR111                       (0x0002u)
+#define GPIO_PPR11_PPR112                       (0x0004u)
+#define GPIO_PPR11_PPR113                       (0x0008u)
+#define GPIO_PPR11_PPR114                       (0x0010u)
+#define GPIO_PPR11_PPR115                       (0x0020u)
+#define GPIO_PPR11_PPR116                       (0x0040u)
+#define GPIO_PPR11_PPR117                       (0x0080u)
+#define GPIO_PPR11_PPR118                       (0x0100u)
+#define GPIO_PPR11_PPR119                       (0x0200u)
+#define GPIO_PPR11_PPR1110                      (0x0400u)
+#define GPIO_PPR11_PPR1111                      (0x0800u)
+#define GPIO_PPR11_PPR1112                      (0x1000u)
+#define GPIO_PPR11_PPR1113                      (0x2000u)
+#define GPIO_PPR11_PPR1114                      (0x4000u)
+#define GPIO_PPR11_PPR1115                      (0x8000u)
+
+#define GPIO_PM11_PM110                         (0x0001u)
+#define GPIO_PM11_PM111                         (0x0002u)
+#define GPIO_PM11_PM112                         (0x0004u)
+#define GPIO_PM11_PM113                         (0x0008u)
+#define GPIO_PM11_PM114                         (0x0010u)
+#define GPIO_PM11_PM115                         (0x0020u)
+#define GPIO_PM11_PM116                         (0x0040u)
+#define GPIO_PM11_PM117                         (0x0080u)
+#define GPIO_PM11_PM118                         (0x0100u)
+#define GPIO_PM11_PM119                         (0x0200u)
+#define GPIO_PM11_PM1110                        (0x0400u)
+#define GPIO_PM11_PM1111                        (0x0800u)
+#define GPIO_PM11_PM1112                        (0x1000u)
+#define GPIO_PM11_PM1113                        (0x2000u)
+#define GPIO_PM11_PM1114                        (0x4000u)
+#define GPIO_PM11_PM1115                        (0x8000u)
+
+#define GPIO_PMC11_PMC110                       (0x0001u)
+#define GPIO_PMC11_PMC111                       (0x0002u)
+#define GPIO_PMC11_PMC112                       (0x0004u)
+#define GPIO_PMC11_PMC113                       (0x0008u)
+#define GPIO_PMC11_PMC114                       (0x0010u)
+#define GPIO_PMC11_PMC115                       (0x0020u)
+#define GPIO_PMC11_PMC116                       (0x0040u)
+#define GPIO_PMC11_PMC117                       (0x0080u)
+#define GPIO_PMC11_PMC118                       (0x0100u)
+#define GPIO_PMC11_PMC119                       (0x0200u)
+#define GPIO_PMC11_PMC1110                      (0x0400u)
+#define GPIO_PMC11_PMC1111                      (0x0800u)
+#define GPIO_PMC11_PMC1112                      (0x1000u)
+#define GPIO_PMC11_PMC1113                      (0x2000u)
+#define GPIO_PMC11_PMC1114                      (0x4000u)
+#define GPIO_PMC11_PMC1115                      (0x8000u)
+
+#define GPIO_PFC11_PFC110                       (0x0001u)
+#define GPIO_PFC11_PFC111                       (0x0002u)
+#define GPIO_PFC11_PFC112                       (0x0004u)
+#define GPIO_PFC11_PFC113                       (0x0008u)
+#define GPIO_PFC11_PFC114                       (0x0010u)
+#define GPIO_PFC11_PFC115                       (0x0020u)
+#define GPIO_PFC11_PFC116                       (0x0040u)
+#define GPIO_PFC11_PFC117                       (0x0080u)
+#define GPIO_PFC11_PFC118                       (0x0100u)
+#define GPIO_PFC11_PFC119                       (0x0200u)
+#define GPIO_PFC11_PFC1110                      (0x0400u)
+#define GPIO_PFC11_PFC1111                      (0x0800u)
+#define GPIO_PFC11_PFC1112                      (0x1000u)
+#define GPIO_PFC11_PFC1113                      (0x2000u)
+#define GPIO_PFC11_PFC1114                      (0x4000u)
+#define GPIO_PFC11_PFC1115                      (0x8000u)
+
+#define GPIO_PFCE11_PFCE110                     (0x0001u)
+#define GPIO_PFCE11_PFCE111                     (0x0002u)
+#define GPIO_PFCE11_PFCE112                     (0x0004u)
+#define GPIO_PFCE11_PFCE113                     (0x0008u)
+#define GPIO_PFCE11_PFCE114                     (0x0010u)
+#define GPIO_PFCE11_PFCE115                     (0x0020u)
+#define GPIO_PFCE11_PFCE116                     (0x0040u)
+#define GPIO_PFCE11_PFCE117                     (0x0080u)
+#define GPIO_PFCE11_PFCE118                     (0x0100u)
+#define GPIO_PFCE11_PFCE119                     (0x0200u)
+#define GPIO_PFCE11_PFCE1110                    (0x0400u)
+#define GPIO_PFCE11_PFCE1111                    (0x0800u)
+#define GPIO_PFCE11_PFCE1112                    (0x1000u)
+#define GPIO_PFCE11_PFCE1113                    (0x2000u)
+#define GPIO_PFCE11_PFCE1114                    (0x4000u)
+#define GPIO_PFCE11_PFCE1115                    (0x8000u)
+
+#define GPIO_PNOT11_PNOT110                     (0x0001u)
+#define GPIO_PNOT11_PNOT111                     (0x0002u)
+#define GPIO_PNOT11_PNOT112                     (0x0004u)
+#define GPIO_PNOT11_PNOT113                     (0x0008u)
+#define GPIO_PNOT11_PNOT114                     (0x0010u)
+#define GPIO_PNOT11_PNOT115                     (0x0020u)
+#define GPIO_PNOT11_PNOT116                     (0x0040u)
+#define GPIO_PNOT11_PNOT117                     (0x0080u)
+#define GPIO_PNOT11_PNOT118                     (0x0100u)
+#define GPIO_PNOT11_PNOT119                     (0x0200u)
+#define GPIO_PNOT11_PNOT1110                    (0x0400u)
+#define GPIO_PNOT11_PNOT1111                    (0x0800u)
+#define GPIO_PNOT11_PNOT1112                    (0x1000u)
+#define GPIO_PNOT11_PNOT1113                    (0x2000u)
+#define GPIO_PNOT11_PNOT1114                    (0x4000u)
+#define GPIO_PNOT11_PNOT1115                    (0x8000u)
+
+#define GPIO_PMSR11_PMSR110                     (0x00000001uL)
+#define GPIO_PMSR11_PMSR111                     (0x00000002uL)
+#define GPIO_PMSR11_PMSR112                     (0x00000004uL)
+#define GPIO_PMSR11_PMSR113                     (0x00000008uL)
+#define GPIO_PMSR11_PMSR114                     (0x00000010uL)
+#define GPIO_PMSR11_PMSR115                     (0x00000020uL)
+#define GPIO_PMSR11_PMSR116                     (0x00000040uL)
+#define GPIO_PMSR11_PMSR117                     (0x00000080uL)
+#define GPIO_PMSR11_PMSR118                     (0x00000100uL)
+#define GPIO_PMSR11_PMSR119                     (0x00000200uL)
+#define GPIO_PMSR11_PMSR1110                    (0x00000400uL)
+#define GPIO_PMSR11_PMSR1111                    (0x00000800uL)
+#define GPIO_PMSR11_PMSR1112                    (0x00001000uL)
+#define GPIO_PMSR11_PMSR1113                    (0x00002000uL)
+#define GPIO_PMSR11_PMSR1114                    (0x00004000uL)
+#define GPIO_PMSR11_PMSR1115                    (0x00008000uL)
+#define GPIO_PMSR11_PMSR1116                    (0x00010000uL)
+#define GPIO_PMSR11_PMSR1117                    (0x00020000uL)
+#define GPIO_PMSR11_PMSR1118                    (0x00040000uL)
+#define GPIO_PMSR11_PMSR1119                    (0x00080000uL)
+#define GPIO_PMSR11_PMSR1120                    (0x00100000uL)
+#define GPIO_PMSR11_PMSR1121                    (0x00200000uL)
+#define GPIO_PMSR11_PMSR1122                    (0x00400000uL)
+#define GPIO_PMSR11_PMSR1123                    (0x00800000uL)
+#define GPIO_PMSR11_PMSR1124                    (0x01000000uL)
+#define GPIO_PMSR11_PMSR1125                    (0x02000000uL)
+#define GPIO_PMSR11_PMSR1126                    (0x04000000uL)
+#define GPIO_PMSR11_PMSR1127                    (0x08000000uL)
+#define GPIO_PMSR11_PMSR1128                    (0x10000000uL)
+#define GPIO_PMSR11_PMSR1129                    (0x20000000uL)
+#define GPIO_PMSR11_PMSR1130                    (0x40000000uL)
+#define GPIO_PMSR11_PMSR1131                    (0x80000000uL)
+
+#define GPIO_PMCSR11_PMCSR110                   (0x00000001uL)
+#define GPIO_PMCSR11_PMCSR111                   (0x00000002uL)
+#define GPIO_PMCSR11_PMCSR112                   (0x00000004uL)
+#define GPIO_PMCSR11_PMCSR113                   (0x00000008uL)
+#define GPIO_PMCSR11_PMCSR114                   (0x00000010uL)
+#define GPIO_PMCSR11_PMCSR115                   (0x00000020uL)
+#define GPIO_PMCSR11_PMCSR116                   (0x00000040uL)
+#define GPIO_PMCSR11_PMCSR117                   (0x00000080uL)
+#define GPIO_PMCSR11_PMCSR118                   (0x00000100uL)
+#define GPIO_PMCSR11_PMCSR119                   (0x00000200uL)
+#define GPIO_PMCSR11_PMCSR1110                  (0x00000400uL)
+#define GPIO_PMCSR11_PMCSR1111                  (0x00000800uL)
+#define GPIO_PMCSR11_PMCSR1112                  (0x00001000uL)
+#define GPIO_PMCSR11_PMCSR1113                  (0x00002000uL)
+#define GPIO_PMCSR11_PMCSR1114                  (0x00004000uL)
+#define GPIO_PMCSR11_PMCSR1115                  (0x00008000uL)
+#define GPIO_PMCSR11_PMCSR1116                  (0x00010000uL)
+#define GPIO_PMCSR11_PMCSR1117                  (0x00020000uL)
+#define GPIO_PMCSR11_PMCSR1118                  (0x00040000uL)
+#define GPIO_PMCSR11_PMCSR1119                  (0x00080000uL)
+#define GPIO_PMCSR11_PMCSR1120                  (0x00100000uL)
+#define GPIO_PMCSR11_PMCSR1121                  (0x00200000uL)
+#define GPIO_PMCSR11_PMCSR1122                  (0x00400000uL)
+#define GPIO_PMCSR11_PMCSR1123                  (0x00800000uL)
+#define GPIO_PMCSR11_PMCSR1124                  (0x01000000uL)
+#define GPIO_PMCSR11_PMCSR1125                  (0x02000000uL)
+#define GPIO_PMCSR11_PMCSR1126                  (0x04000000uL)
+#define GPIO_PMCSR11_PMCSR1127                  (0x08000000uL)
+#define GPIO_PMCSR11_PMCSR1128                  (0x10000000uL)
+#define GPIO_PMCSR11_PMCSR1129                  (0x20000000uL)
+#define GPIO_PMCSR11_PMCSR1130                  (0x40000000uL)
+#define GPIO_PMCSR11_PMCSR1131                  (0x80000000uL)
+
+#define GPIO_PFCAE11_PFCAE110                   (0x0001u)
+#define GPIO_PFCAE11_PFCAE111                   (0x0002u)
+#define GPIO_PFCAE11_PFCAE112                   (0x0004u)
+#define GPIO_PFCAE11_PFCAE113                   (0x0008u)
+#define GPIO_PFCAE11_PFCAE114                   (0x0010u)
+#define GPIO_PFCAE11_PFCAE115                   (0x0020u)
+#define GPIO_PFCAE11_PFCAE116                   (0x0040u)
+#define GPIO_PFCAE11_PFCAE117                   (0x0080u)
+#define GPIO_PFCAE11_PFCAE118                   (0x0100u)
+#define GPIO_PFCAE11_PFCAE119                   (0x0200u)
+#define GPIO_PFCAE11_PFCAE1110                  (0x0400u)
+#define GPIO_PFCAE11_PFCAE1111                  (0x0800u)
+#define GPIO_PFCAE11_PFCAE1112                  (0x1000u)
+#define GPIO_PFCAE11_PFCAE1113                  (0x2000u)
+#define GPIO_PFCAE11_PFCAE1114                  (0x4000u)
+#define GPIO_PFCAE11_PFCAE1115                  (0x8000u)
+
+#define GPIO_PIBC11_PIBC110                     (0x0001u)
+#define GPIO_PIBC11_PIBC111                     (0x0002u)
+#define GPIO_PIBC11_PIBC112                     (0x0004u)
+#define GPIO_PIBC11_PIBC113                     (0x0008u)
+#define GPIO_PIBC11_PIBC114                     (0x0010u)
+#define GPIO_PIBC11_PIBC115                     (0x0020u)
+#define GPIO_PIBC11_PIBC116                     (0x0040u)
+#define GPIO_PIBC11_PIBC117                     (0x0080u)
+#define GPIO_PIBC11_PIBC118                     (0x0100u)
+#define GPIO_PIBC11_PIBC119                     (0x0200u)
+#define GPIO_PIBC11_PIBC1110                    (0x0400u)
+#define GPIO_PIBC11_PIBC1111                    (0x0800u)
+#define GPIO_PIBC11_PIBC1112                    (0x1000u)
+#define GPIO_PIBC11_PIBC1113                    (0x2000u)
+#define GPIO_PIBC11_PIBC1114                    (0x4000u)
+#define GPIO_PIBC11_PIBC1115                    (0x8000u)
+
+#define GPIO_PBDC11_PBDC110                     (0x0001u)
+#define GPIO_PBDC11_PBDC111                     (0x0002u)
+#define GPIO_PBDC11_PBDC112                     (0x0004u)
+#define GPIO_PBDC11_PBDC113                     (0x0008u)
+#define GPIO_PBDC11_PBDC114                     (0x0010u)
+#define GPIO_PBDC11_PBDC115                     (0x0020u)
+#define GPIO_PBDC11_PBDC116                     (0x0040u)
+#define GPIO_PBDC11_PBDC117                     (0x0080u)
+#define GPIO_PBDC11_PBDC118                     (0x0100u)
+#define GPIO_PBDC11_PBDC119                     (0x0200u)
+#define GPIO_PBDC11_PBDC1110                    (0x0400u)
+#define GPIO_PBDC11_PBDC1111                    (0x0800u)
+#define GPIO_PBDC11_PBDC1112                    (0x1000u)
+#define GPIO_PBDC11_PBDC1113                    (0x2000u)
+#define GPIO_PBDC11_PBDC1114                    (0x4000u)
+#define GPIO_PBDC11_PBDC1115                    (0x8000u)
+
+#define GPIO_PIPC11_PIPC110                     (0x0001u)
+#define GPIO_PIPC11_PIPC111                     (0x0002u)
+#define GPIO_PIPC11_PIPC112                     (0x0004u)
+#define GPIO_PIPC11_PIPC113                     (0x0008u)
+#define GPIO_PIPC11_PIPC114                     (0x0010u)
+#define GPIO_PIPC11_PIPC115                     (0x0020u)
+#define GPIO_PIPC11_PIPC116                     (0x0040u)
+#define GPIO_PIPC11_PIPC117                     (0x0080u)
+#define GPIO_PIPC11_PIPC118                     (0x0100u)
+#define GPIO_PIPC11_PIPC119                     (0x0200u)
+#define GPIO_PIPC11_PIPC1110                    (0x0400u)
+#define GPIO_PIPC11_PIPC1111                    (0x0800u)
+#define GPIO_PIPC11_PIPC1112                    (0x1000u)
+#define GPIO_PIPC11_PIPC1113                    (0x2000u)
+#define GPIO_PIPC11_PIPC1114                    (0x4000u)
+#define GPIO_PIPC11_PIPC1115                    (0x8000u)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- P0 ---- */
+#define GPIO_PPR0_PPR00_SHIFT                   (0u)
+#define GPIO_PPR0_PPR01_SHIFT                   (1u)
+#define GPIO_PPR0_PPR02_SHIFT                   (2u)
+#define GPIO_PPR0_PPR03_SHIFT                   (3u)
+#define GPIO_PPR0_PPR04_SHIFT                   (4u)
+#define GPIO_PPR0_PPR05_SHIFT                   (5u)
+
+#define GPIO_PMC0_PMC04_SHIFT                   (4u)
+#define GPIO_PMC0_PMC05_SHIFT                   (5u)
+
+#define GPIO_PMCSR0_PMCSR04_SHIFT               (4u)
+#define GPIO_PMCSR0_PMCSR05_SHIFT               (5u)
+
+#define GPIO_PIBC0_PIBC00_SHIFT                 (0u)
+#define GPIO_PIBC0_PIBC01_SHIFT                 (1u)
+#define GPIO_PIBC0_PIBC02_SHIFT                 (2u)
+#define GPIO_PIBC0_PIBC03_SHIFT                 (3u)
+#define GPIO_PIBC0_PIBC04_SHIFT                 (4u)
+#define GPIO_PIBC0_PIBC05_SHIFT                 (5u)
+
+/* ---- P1 ---- */
+#define GPIO_P1_P10_SHIFT                       (0u)
+#define GPIO_P1_P11_SHIFT                       (1u)
+#define GPIO_P1_P12_SHIFT                       (2u)
+#define GPIO_P1_P13_SHIFT                       (3u)
+#define GPIO_P1_P14_SHIFT                       (4u)
+#define GPIO_P1_P15_SHIFT                       (5u)
+#define GPIO_P1_P16_SHIFT                       (6u)
+#define GPIO_P1_P17_SHIFT                       (7u)
+
+#define GPIO_PSR1_PSR10_SHIFT                   (0u)
+#define GPIO_PSR1_PSR11_SHIFT                   (1u)
+#define GPIO_PSR1_PSR12_SHIFT                   (2u)
+#define GPIO_PSR1_PSR13_SHIFT                   (3u)
+#define GPIO_PSR1_PSR14_SHIFT                   (4u)
+#define GPIO_PSR1_PSR15_SHIFT                   (5u)
+#define GPIO_PSR1_PSR16_SHIFT                   (6u)
+#define GPIO_PSR1_PSR17_SHIFT                   (7u)
+#define GPIO_PSR1_PSR116_SHIFT                  (16u)
+#define GPIO_PSR1_PSR117_SHIFT                  (17u)
+#define GPIO_PSR1_PSR118_SHIFT                  (18u)
+#define GPIO_PSR1_PSR119_SHIFT                  (19u)
+#define GPIO_PSR1_PSR120_SHIFT                  (20u)
+#define GPIO_PSR1_PSR121_SHIFT                  (21u)
+#define GPIO_PSR1_PSR122_SHIFT                  (22u)
+#define GPIO_PSR1_PSR123_SHIFT                  (23u)
+
+#define GPIO_PPR1_PPR10_SHIFT                   (0u)
+#define GPIO_PPR1_PPR11_SHIFT                   (1u)
+#define GPIO_PPR1_PPR12_SHIFT                   (2u)
+#define GPIO_PPR1_PPR13_SHIFT                   (3u)
+#define GPIO_PPR1_PPR14_SHIFT                   (4u)
+#define GPIO_PPR1_PPR15_SHIFT                   (5u)
+#define GPIO_PPR1_PPR16_SHIFT                   (6u)
+#define GPIO_PPR1_PPR17_SHIFT                   (7u)
+#define GPIO_PPR1_PPR18_SHIFT                   (8u)
+#define GPIO_PPR1_PPR19_SHIFT                   (9u)
+#define GPIO_PPR1_PPR110_SHIFT                  (10u)
+#define GPIO_PPR1_PPR111_SHIFT                  (11u)
+#define GPIO_PPR1_PPR112_SHIFT                  (12u)
+#define GPIO_PPR1_PPR113_SHIFT                  (13u)
+#define GPIO_PPR1_PPR114_SHIFT                  (14u)
+#define GPIO_PPR1_PPR115_SHIFT                  (15u)
+
+#define GPIO_PM1_PM10_SHIFT                     (0u)
+#define GPIO_PM1_PM11_SHIFT                     (1u)
+#define GPIO_PM1_PM12_SHIFT                     (2u)
+#define GPIO_PM1_PM13_SHIFT                     (3u)
+#define GPIO_PM1_PM14_SHIFT                     (4u)
+#define GPIO_PM1_PM15_SHIFT                     (5u)
+#define GPIO_PM1_PM16_SHIFT                     (6u)
+#define GPIO_PM1_PM17_SHIFT                     (7u)
+
+#define GPIO_PMC1_PMC10_SHIFT                   (0u)
+#define GPIO_PMC1_PMC11_SHIFT                   (1u)
+#define GPIO_PMC1_PMC12_SHIFT                   (2u)
+#define GPIO_PMC1_PMC13_SHIFT                   (3u)
+#define GPIO_PMC1_PMC14_SHIFT                   (4u)
+#define GPIO_PMC1_PMC15_SHIFT                   (5u)
+#define GPIO_PMC1_PMC16_SHIFT                   (6u)
+#define GPIO_PMC1_PMC17_SHIFT                   (7u)
+#define GPIO_PMC1_PMC18_SHIFT                   (8u)
+#define GPIO_PMC1_PMC19_SHIFT                   (9u)
+#define GPIO_PMC1_PMC110_SHIFT                  (10u)
+#define GPIO_PMC1_PMC111_SHIFT                  (11u)
+#define GPIO_PMC1_PMC112_SHIFT                  (12u)
+#define GPIO_PMC1_PMC113_SHIFT                  (13u)
+#define GPIO_PMC1_PMC114_SHIFT                  (14u)
+#define GPIO_PMC1_PMC115_SHIFT                  (15u)
+
+#define GPIO_PFC1_PFC10_SHIFT                   (0u)
+#define GPIO_PFC1_PFC11_SHIFT                   (1u)
+#define GPIO_PFC1_PFC12_SHIFT                   (2u)
+#define GPIO_PFC1_PFC13_SHIFT                   (3u)
+#define GPIO_PFC1_PFC14_SHIFT                   (4u)
+#define GPIO_PFC1_PFC15_SHIFT                   (5u)
+#define GPIO_PFC1_PFC16_SHIFT                   (6u)
+#define GPIO_PFC1_PFC17_SHIFT                   (7u)
+#define GPIO_PFC1_PFC18_SHIFT                   (8u)
+#define GPIO_PFC1_PFC19_SHIFT                   (9u)
+#define GPIO_PFC1_PFC110_SHIFT                  (10u)
+#define GPIO_PFC1_PFC111_SHIFT                  (11u)
+#define GPIO_PFC1_PFC112_SHIFT                  (12u)
+#define GPIO_PFC1_PFC113_SHIFT                  (13u)
+#define GPIO_PFC1_PFC114_SHIFT                  (14u)
+#define GPIO_PFC1_PFC115_SHIFT                  (15u)
+
+#define GPIO_PFCE1_PFCE10_SHIFT                 (0u)
+#define GPIO_PFCE1_PFCE11_SHIFT                 (1u)
+#define GPIO_PFCE1_PFCE12_SHIFT                 (2u)
+#define GPIO_PFCE1_PFCE13_SHIFT                 (3u)
+#define GPIO_PFCE1_PFCE14_SHIFT                 (4u)
+#define GPIO_PFCE1_PFCE15_SHIFT                 (5u)
+#define GPIO_PFCE1_PFCE16_SHIFT                 (6u)
+#define GPIO_PFCE1_PFCE17_SHIFT                 (7u)
+#define GPIO_PFCE1_PFCE18_SHIFT                 (8u)
+#define GPIO_PFCE1_PFCE19_SHIFT                 (9u)
+#define GPIO_PFCE1_PFCE110_SHIFT                (10u)
+#define GPIO_PFCE1_PFCE111_SHIFT                (11u)
+#define GPIO_PFCE1_PFCE112_SHIFT                (12u)
+#define GPIO_PFCE1_PFCE113_SHIFT                (13u)
+#define GPIO_PFCE1_PFCE114_SHIFT                (14u)
+#define GPIO_PFCE1_PFCE115_SHIFT                (15u)
+
+#define GPIO_PNOT1_PNOT10_SHIFT                 (0u)
+#define GPIO_PNOT1_PNOT11_SHIFT                 (1u)
+#define GPIO_PNOT1_PNOT12_SHIFT                 (2u)
+#define GPIO_PNOT1_PNOT13_SHIFT                 (3u)
+#define GPIO_PNOT1_PNOT14_SHIFT                 (4u)
+#define GPIO_PNOT1_PNOT15_SHIFT                 (5u)
+#define GPIO_PNOT1_PNOT16_SHIFT                 (6u)
+#define GPIO_PNOT1_PNOT17_SHIFT                 (7u)
+
+#define GPIO_PMSR1_PMSR10_SHIFT                 (0u)
+#define GPIO_PMSR1_PMSR11_SHIFT                 (1u)
+#define GPIO_PMSR1_PMSR12_SHIFT                 (2u)
+#define GPIO_PMSR1_PMSR13_SHIFT                 (3u)
+#define GPIO_PMSR1_PMSR14_SHIFT                 (4u)
+#define GPIO_PMSR1_PMSR15_SHIFT                 (5u)
+#define GPIO_PMSR1_PMSR16_SHIFT                 (6u)
+#define GPIO_PMSR1_PMSR17_SHIFT                 (7u)
+#define GPIO_PMSR1_PMSR116_SHIFT                (16u)
+#define GPIO_PMSR1_PMSR117_SHIFT                (17u)
+#define GPIO_PMSR1_PMSR118_SHIFT                (18u)
+#define GPIO_PMSR1_PMSR119_SHIFT                (19u)
+#define GPIO_PMSR1_PMSR120_SHIFT                (20u)
+#define GPIO_PMSR1_PMSR121_SHIFT                (21u)
+#define GPIO_PMSR1_PMSR122_SHIFT                (22u)
+#define GPIO_PMSR1_PMSR123_SHIFT                (23u)
+
+#define GPIO_PMCSR1_PMCSR10_SHIFT               (0u)
+#define GPIO_PMCSR1_PMCSR11_SHIFT               (1u)
+#define GPIO_PMCSR1_PMCSR12_SHIFT               (2u)
+#define GPIO_PMCSR1_PMCSR13_SHIFT               (3u)
+#define GPIO_PMCSR1_PMCSR14_SHIFT               (4u)
+#define GPIO_PMCSR1_PMCSR15_SHIFT               (5u)
+#define GPIO_PMCSR1_PMCSR16_SHIFT               (6u)
+#define GPIO_PMCSR1_PMCSR17_SHIFT               (7u)
+#define GPIO_PMCSR1_PMCSR116_SHIFT              (16u)
+#define GPIO_PMCSR1_PMCSR117_SHIFT              (17u)
+#define GPIO_PMCSR1_PMCSR118_SHIFT              (18u)
+#define GPIO_PMCSR1_PMCSR119_SHIFT              (19u)
+#define GPIO_PMCSR1_PMCSR120_SHIFT              (20u)
+#define GPIO_PMCSR1_PMCSR121_SHIFT              (21u)
+#define GPIO_PMCSR1_PMCSR122_SHIFT              (22u)
+#define GPIO_PMCSR1_PMCSR123_SHIFT              (23u)
+
+#define GPIO_PFCAE1_PFCAE10_SHIFT               (0u)
+#define GPIO_PFCAE1_PFCAE11_SHIFT               (1u)
+#define GPIO_PFCAE1_PFCAE12_SHIFT               (2u)
+#define GPIO_PFCAE1_PFCAE13_SHIFT               (3u)
+#define GPIO_PFCAE1_PFCAE14_SHIFT               (4u)
+#define GPIO_PFCAE1_PFCAE15_SHIFT               (5u)
+#define GPIO_PFCAE1_PFCAE16_SHIFT               (6u)
+#define GPIO_PFCAE1_PFCAE17_SHIFT               (7u)
+#define GPIO_PFCAE1_PFCAE18_SHIFT               (8u)
+#define GPIO_PFCAE1_PFCAE19_SHIFT               (9u)
+#define GPIO_PFCAE1_PFCAE110_SHIFT              (10u)
+#define GPIO_PFCAE1_PFCAE111_SHIFT              (11u)
+#define GPIO_PFCAE1_PFCAE112_SHIFT              (12u)
+#define GPIO_PFCAE1_PFCAE113_SHIFT              (13u)
+#define GPIO_PFCAE1_PFCAE114_SHIFT              (14u)
+#define GPIO_PFCAE1_PFCAE115_SHIFT              (15u)
+
+#define GPIO_PIBC1_PIBC10_SHIFT                 (0u)
+#define GPIO_PIBC1_PIBC11_SHIFT                 (1u)
+#define GPIO_PIBC1_PIBC12_SHIFT                 (2u)
+#define GPIO_PIBC1_PIBC13_SHIFT                 (3u)
+#define GPIO_PIBC1_PIBC14_SHIFT                 (4u)
+#define GPIO_PIBC1_PIBC15_SHIFT                 (5u)
+#define GPIO_PIBC1_PIBC16_SHIFT                 (6u)
+#define GPIO_PIBC1_PIBC17_SHIFT                 (7u)
+#define GPIO_PIBC1_PIBC18_SHIFT                 (8u)
+#define GPIO_PIBC1_PIBC19_SHIFT                 (9u)
+#define GPIO_PIBC1_PIBC110_SHIFT                (10u)
+#define GPIO_PIBC1_PIBC111_SHIFT                (11u)
+#define GPIO_PIBC1_PIBC112_SHIFT                (12u)
+#define GPIO_PIBC1_PIBC113_SHIFT                (13u)
+#define GPIO_PIBC1_PIBC114_SHIFT                (14u)
+#define GPIO_PIBC1_PIBC115_SHIFT                (15u)
+
+#define GPIO_PBDC1_PBDC10_SHIFT                 (0u)
+#define GPIO_PBDC1_PBDC11_SHIFT                 (1u)
+#define GPIO_PBDC1_PBDC12_SHIFT                 (2u)
+#define GPIO_PBDC1_PBDC13_SHIFT                 (3u)
+#define GPIO_PBDC1_PBDC14_SHIFT                 (4u)
+#define GPIO_PBDC1_PBDC15_SHIFT                 (5u)
+#define GPIO_PBDC1_PBDC16_SHIFT                 (6u)
+#define GPIO_PBDC1_PBDC17_SHIFT                 (7u)
+#define GPIO_PBDC1_PBDC18_SHIFT                 (8u)
+#define GPIO_PBDC1_PBDC19_SHIFT                 (9u)
+#define GPIO_PBDC1_PBDC110_SHIFT                (10u)
+#define GPIO_PBDC1_PBDC111_SHIFT                (11u)
+#define GPIO_PBDC1_PBDC112_SHIFT                (12u)
+#define GPIO_PBDC1_PBDC113_SHIFT                (13u)
+#define GPIO_PBDC1_PBDC114_SHIFT                (14u)
+#define GPIO_PBDC1_PBDC115_SHIFT                (15u)
+
+#define GPIO_PIPC1_PIPC10_SHIFT                 (0u)
+#define GPIO_PIPC1_PIPC11_SHIFT                 (1u)
+#define GPIO_PIPC1_PIPC12_SHIFT                 (2u)
+#define GPIO_PIPC1_PIPC13_SHIFT                 (3u)
+#define GPIO_PIPC1_PIPC14_SHIFT                 (4u)
+#define GPIO_PIPC1_PIPC15_SHIFT                 (5u)
+#define GPIO_PIPC1_PIPC16_SHIFT                 (6u)
+#define GPIO_PIPC1_PIPC17_SHIFT                 (7u)
+
+/* ---- P2 ---- */
+#define GPIO_P2_P20_SHIFT                       (0u)
+#define GPIO_P2_P21_SHIFT                       (1u)
+#define GPIO_P2_P22_SHIFT                       (2u)
+#define GPIO_P2_P23_SHIFT                       (3u)
+#define GPIO_P2_P24_SHIFT                       (4u)
+#define GPIO_P2_P25_SHIFT                       (5u)
+#define GPIO_P2_P26_SHIFT                       (6u)
+#define GPIO_P2_P27_SHIFT                       (7u)
+#define GPIO_P2_P28_SHIFT                       (8u)
+#define GPIO_P2_P29_SHIFT                       (9u)
+#define GPIO_P2_P210_SHIFT                      (10u)
+#define GPIO_P2_P211_SHIFT                      (11u)
+#define GPIO_P2_P212_SHIFT                      (12u)
+#define GPIO_P2_P213_SHIFT                      (13u)
+#define GPIO_P2_P214_SHIFT                      (14u)
+#define GPIO_P2_P215_SHIFT                      (15u)
+
+#define GPIO_PSR2_PSR20_SHIFT                   (0u)
+#define GPIO_PSR2_PSR21_SHIFT                   (1u)
+#define GPIO_PSR2_PSR22_SHIFT                   (2u)
+#define GPIO_PSR2_PSR23_SHIFT                   (3u)
+#define GPIO_PSR2_PSR24_SHIFT                   (4u)
+#define GPIO_PSR2_PSR25_SHIFT                   (5u)
+#define GPIO_PSR2_PSR26_SHIFT                   (6u)
+#define GPIO_PSR2_PSR27_SHIFT                   (7u)
+#define GPIO_PSR2_PSR28_SHIFT                   (8u)
+#define GPIO_PSR2_PSR29_SHIFT                   (9u)
+#define GPIO_PSR2_PSR210_SHIFT                  (10u)
+#define GPIO_PSR2_PSR211_SHIFT                  (11u)
+#define GPIO_PSR2_PSR212_SHIFT                  (12u)
+#define GPIO_PSR2_PSR213_SHIFT                  (13u)
+#define GPIO_PSR2_PSR214_SHIFT                  (14u)
+#define GPIO_PSR2_PSR215_SHIFT                  (15u)
+#define GPIO_PSR2_PSR216_SHIFT                  (16u)
+#define GPIO_PSR2_PSR217_SHIFT                  (17u)
+#define GPIO_PSR2_PSR218_SHIFT                  (18u)
+#define GPIO_PSR2_PSR219_SHIFT                  (19u)
+#define GPIO_PSR2_PSR220_SHIFT                  (20u)
+#define GPIO_PSR2_PSR221_SHIFT                  (21u)
+#define GPIO_PSR2_PSR222_SHIFT                  (22u)
+#define GPIO_PSR2_PSR223_SHIFT                  (23u)
+#define GPIO_PSR2_PSR224_SHIFT                  (24u)
+#define GPIO_PSR2_PSR225_SHIFT                  (25u)
+#define GPIO_PSR2_PSR226_SHIFT                  (26u)
+#define GPIO_PSR2_PSR227_SHIFT                  (27u)
+#define GPIO_PSR2_PSR228_SHIFT                  (28u)
+#define GPIO_PSR2_PSR229_SHIFT                  (29u)
+#define GPIO_PSR2_PSR230_SHIFT                  (30u)
+#define GPIO_PSR2_PSR231_SHIFT                  (31u)
+
+#define GPIO_PPR2_PPR20_SHIFT                   (0u)
+#define GPIO_PPR2_PPR21_SHIFT                   (1u)
+#define GPIO_PPR2_PPR22_SHIFT                   (2u)
+#define GPIO_PPR2_PPR23_SHIFT                   (3u)
+#define GPIO_PPR2_PPR24_SHIFT                   (4u)
+#define GPIO_PPR2_PPR25_SHIFT                   (5u)
+#define GPIO_PPR2_PPR26_SHIFT                   (6u)
+#define GPIO_PPR2_PPR27_SHIFT                   (7u)
+#define GPIO_PPR2_PPR28_SHIFT                   (8u)
+#define GPIO_PPR2_PPR29_SHIFT                   (9u)
+#define GPIO_PPR2_PPR210_SHIFT                  (10u)
+#define GPIO_PPR2_PPR211_SHIFT                  (11u)
+#define GPIO_PPR2_PPR212_SHIFT                  (12u)
+#define GPIO_PPR2_PPR213_SHIFT                  (13u)
+#define GPIO_PPR2_PPR214_SHIFT                  (14u)
+#define GPIO_PPR2_PPR215_SHIFT                  (15u)
+
+#define GPIO_PM2_PM20_SHIFT                     (0u)
+#define GPIO_PM2_PM21_SHIFT                     (1u)
+#define GPIO_PM2_PM22_SHIFT                     (2u)
+#define GPIO_PM2_PM23_SHIFT                     (3u)
+#define GPIO_PM2_PM24_SHIFT                     (4u)
+#define GPIO_PM2_PM25_SHIFT                     (5u)
+#define GPIO_PM2_PM26_SHIFT                     (6u)
+#define GPIO_PM2_PM27_SHIFT                     (7u)
+#define GPIO_PM2_PM28_SHIFT                     (8u)
+#define GPIO_PM2_PM29_SHIFT                     (9u)
+#define GPIO_PM2_PM210_SHIFT                    (10u)
+#define GPIO_PM2_PM211_SHIFT                    (11u)
+#define GPIO_PM2_PM212_SHIFT                    (12u)
+#define GPIO_PM2_PM213_SHIFT                    (13u)
+#define GPIO_PM2_PM214_SHIFT                    (14u)
+#define GPIO_PM2_PM215_SHIFT                    (15u)
+
+#define GPIO_PMC2_PMC20_SHIFT                   (0u)
+#define GPIO_PMC2_PMC21_SHIFT                   (1u)
+#define GPIO_PMC2_PMC22_SHIFT                   (2u)
+#define GPIO_PMC2_PMC23_SHIFT                   (3u)
+#define GPIO_PMC2_PMC24_SHIFT                   (4u)
+#define GPIO_PMC2_PMC25_SHIFT                   (5u)
+#define GPIO_PMC2_PMC26_SHIFT                   (6u)
+#define GPIO_PMC2_PMC27_SHIFT                   (7u)
+#define GPIO_PMC2_PMC28_SHIFT                   (8u)
+#define GPIO_PMC2_PMC29_SHIFT                   (9u)
+#define GPIO_PMC2_PMC210_SHIFT                  (10u)
+#define GPIO_PMC2_PMC211_SHIFT                  (11u)
+#define GPIO_PMC2_PMC212_SHIFT                  (12u)
+#define GPIO_PMC2_PMC213_SHIFT                  (13u)
+#define GPIO_PMC2_PMC214_SHIFT                  (14u)
+#define GPIO_PMC2_PMC215_SHIFT                  (15u)
+
+#define GPIO_PFC2_PFC20_SHIFT                   (0u)
+#define GPIO_PFC2_PFC21_SHIFT                   (1u)
+#define GPIO_PFC2_PFC22_SHIFT                   (2u)
+#define GPIO_PFC2_PFC23_SHIFT                   (3u)
+#define GPIO_PFC2_PFC24_SHIFT                   (4u)
+#define GPIO_PFC2_PFC25_SHIFT                   (5u)
+#define GPIO_PFC2_PFC26_SHIFT                   (6u)
+#define GPIO_PFC2_PFC27_SHIFT                   (7u)
+#define GPIO_PFC2_PFC28_SHIFT                   (8u)
+#define GPIO_PFC2_PFC29_SHIFT                   (9u)
+#define GPIO_PFC2_PFC210_SHIFT                  (10u)
+#define GPIO_PFC2_PFC211_SHIFT                  (11u)
+#define GPIO_PFC2_PFC212_SHIFT                  (12u)
+#define GPIO_PFC2_PFC213_SHIFT                  (13u)
+#define GPIO_PFC2_PFC214_SHIFT                  (14u)
+#define GPIO_PFC2_PFC215_SHIFT                  (15u)
+
+#define GPIO_PFCE2_PFCE20_SHIFT                 (0u)
+#define GPIO_PFCE2_PFCE21_SHIFT                 (1u)
+#define GPIO_PFCE2_PFCE22_SHIFT                 (2u)
+#define GPIO_PFCE2_PFCE23_SHIFT                 (3u)
+#define GPIO_PFCE2_PFCE24_SHIFT                 (4u)
+#define GPIO_PFCE2_PFCE25_SHIFT                 (5u)
+#define GPIO_PFCE2_PFCE26_SHIFT                 (6u)
+#define GPIO_PFCE2_PFCE27_SHIFT                 (7u)
+#define GPIO_PFCE2_PFCE28_SHIFT                 (8u)
+#define GPIO_PFCE2_PFCE29_SHIFT                 (9u)
+#define GPIO_PFCE2_PFCE210_SHIFT                (10u)
+#define GPIO_PFCE2_PFCE211_SHIFT                (11u)
+#define GPIO_PFCE2_PFCE212_SHIFT                (12u)
+#define GPIO_PFCE2_PFCE213_SHIFT                (13u)
+#define GPIO_PFCE2_PFCE214_SHIFT                (14u)
+#define GPIO_PFCE2_PFCE215_SHIFT                (15u)
+
+#define GPIO_PNOT2_PNOT20_SHIFT                 (0u)
+#define GPIO_PNOT2_PNOT21_SHIFT                 (1u)
+#define GPIO_PNOT2_PNOT22_SHIFT                 (2u)
+#define GPIO_PNOT2_PNOT23_SHIFT                 (3u)
+#define GPIO_PNOT2_PNOT24_SHIFT                 (4u)
+#define GPIO_PNOT2_PNOT25_SHIFT                 (5u)
+#define GPIO_PNOT2_PNOT26_SHIFT                 (6u)
+#define GPIO_PNOT2_PNOT27_SHIFT                 (7u)
+#define GPIO_PNOT2_PNOT28_SHIFT                 (8u)
+#define GPIO_PNOT2_PNOT29_SHIFT                 (9u)
+#define GPIO_PNOT2_PNOT210_SHIFT                (10u)
+#define GPIO_PNOT2_PNOT211_SHIFT                (11u)
+#define GPIO_PNOT2_PNOT212_SHIFT                (12u)
+#define GPIO_PNOT2_PNOT213_SHIFT                (13u)
+#define GPIO_PNOT2_PNOT214_SHIFT                (14u)
+#define GPIO_PNOT2_PNOT215_SHIFT                (15u)
+
+#define GPIO_PMSR2_PMSR20_SHIFT                 (0u)
+#define GPIO_PMSR2_PMSR21_SHIFT                 (1u)
+#define GPIO_PMSR2_PMSR22_SHIFT                 (2u)
+#define GPIO_PMSR2_PMSR23_SHIFT                 (3u)
+#define GPIO_PMSR2_PMSR24_SHIFT                 (4u)
+#define GPIO_PMSR2_PMSR25_SHIFT                 (5u)
+#define GPIO_PMSR2_PMSR26_SHIFT                 (6u)
+#define GPIO_PMSR2_PMSR27_SHIFT                 (7u)
+#define GPIO_PMSR2_PMSR28_SHIFT                 (8u)
+#define GPIO_PMSR2_PMSR29_SHIFT                 (9u)
+#define GPIO_PMSR2_PMSR210_SHIFT                (10u)
+#define GPIO_PMSR2_PMSR211_SHIFT                (11u)
+#define GPIO_PMSR2_PMSR212_SHIFT                (12u)
+#define GPIO_PMSR2_PMSR213_SHIFT                (13u)
+#define GPIO_PMSR2_PMSR214_SHIFT                (14u)
+#define GPIO_PMSR2_PMSR215_SHIFT                (15u)
+#define GPIO_PMSR2_PMSR216_SHIFT                (16u)
+#define GPIO_PMSR2_PMSR217_SHIFT                (17u)
+#define GPIO_PMSR2_PMSR218_SHIFT                (18u)
+#define GPIO_PMSR2_PMSR219_SHIFT                (19u)
+#define GPIO_PMSR2_PMSR220_SHIFT                (20u)
+#define GPIO_PMSR2_PMSR221_SHIFT                (21u)
+#define GPIO_PMSR2_PMSR222_SHIFT                (22u)
+#define GPIO_PMSR2_PMSR223_SHIFT                (23u)
+#define GPIO_PMSR2_PMSR224_SHIFT                (24u)
+#define GPIO_PMSR2_PMSR225_SHIFT                (25u)
+#define GPIO_PMSR2_PMSR226_SHIFT                (26u)
+#define GPIO_PMSR2_PMSR227_SHIFT                (27u)
+#define GPIO_PMSR2_PMSR228_SHIFT                (28u)
+#define GPIO_PMSR2_PMSR229_SHIFT                (29u)
+#define GPIO_PMSR2_PMSR230_SHIFT                (30u)
+#define GPIO_PMSR2_PMSR231_SHIFT                (31u)
+
+#define GPIO_PMCSR2_PMCSR20_SHIFT               (0u)
+#define GPIO_PMCSR2_PMCSR21_SHIFT               (1u)
+#define GPIO_PMCSR2_PMCSR22_SHIFT               (2u)
+#define GPIO_PMCSR2_PMCSR23_SHIFT               (3u)
+#define GPIO_PMCSR2_PMCSR24_SHIFT               (4u)
+#define GPIO_PMCSR2_PMCSR25_SHIFT               (5u)
+#define GPIO_PMCSR2_PMCSR26_SHIFT               (6u)
+#define GPIO_PMCSR2_PMCSR27_SHIFT               (7u)
+#define GPIO_PMCSR2_PMCSR28_SHIFT               (8u)
+#define GPIO_PMCSR2_PMCSR29_SHIFT               (9u)
+#define GPIO_PMCSR2_PMCSR210_SHIFT              (10u)
+#define GPIO_PMCSR2_PMCSR211_SHIFT              (11u)
+#define GPIO_PMCSR2_PMCSR212_SHIFT              (12u)
+#define GPIO_PMCSR2_PMCSR213_SHIFT              (13u)
+#define GPIO_PMCSR2_PMCSR214_SHIFT              (14u)
+#define GPIO_PMCSR2_PMCSR215_SHIFT              (15u)
+#define GPIO_PMCSR2_PMCSR216_SHIFT              (16u)
+#define GPIO_PMCSR2_PMCSR217_SHIFT              (17u)
+#define GPIO_PMCSR2_PMCSR218_SHIFT              (18u)
+#define GPIO_PMCSR2_PMCSR219_SHIFT              (19u)
+#define GPIO_PMCSR2_PMCSR220_SHIFT              (20u)
+#define GPIO_PMCSR2_PMCSR221_SHIFT              (21u)
+#define GPIO_PMCSR2_PMCSR222_SHIFT              (22u)
+#define GPIO_PMCSR2_PMCSR223_SHIFT              (23u)
+#define GPIO_PMCSR2_PMCSR224_SHIFT              (24u)
+#define GPIO_PMCSR2_PMCSR225_SHIFT              (25u)
+#define GPIO_PMCSR2_PMCSR226_SHIFT              (26u)
+#define GPIO_PMCSR2_PMCSR227_SHIFT              (27u)
+#define GPIO_PMCSR2_PMCSR228_SHIFT              (28u)
+#define GPIO_PMCSR2_PMCSR229_SHIFT              (29u)
+#define GPIO_PMCSR2_PMCSR230_SHIFT              (30u)
+#define GPIO_PMCSR2_PMCSR231_SHIFT              (31u)
+
+#define GPIO_PFCAE2_PFCAE20_SHIFT               (0u)
+#define GPIO_PFCAE2_PFCAE21_SHIFT               (1u)
+#define GPIO_PFCAE2_PFCAE22_SHIFT               (2u)
+#define GPIO_PFCAE2_PFCAE23_SHIFT               (3u)
+#define GPIO_PFCAE2_PFCAE24_SHIFT               (4u)
+#define GPIO_PFCAE2_PFCAE25_SHIFT               (5u)
+#define GPIO_PFCAE2_PFCAE26_SHIFT               (6u)
+#define GPIO_PFCAE2_PFCAE27_SHIFT               (7u)
+#define GPIO_PFCAE2_PFCAE28_SHIFT               (8u)
+#define GPIO_PFCAE2_PFCAE29_SHIFT               (9u)
+#define GPIO_PFCAE2_PFCAE210_SHIFT              (10u)
+#define GPIO_PFCAE2_PFCAE211_SHIFT              (11u)
+#define GPIO_PFCAE2_PFCAE212_SHIFT              (12u)
+#define GPIO_PFCAE2_PFCAE213_SHIFT              (13u)
+#define GPIO_PFCAE2_PFCAE214_SHIFT              (14u)
+#define GPIO_PFCAE2_PFCAE215_SHIFT              (15u)
+
+#define GPIO_PIBC2_PIBC20_SHIFT                 (0u)
+#define GPIO_PIBC2_PIBC21_SHIFT                 (1u)
+#define GPIO_PIBC2_PIBC22_SHIFT                 (2u)
+#define GPIO_PIBC2_PIBC23_SHIFT                 (3u)
+#define GPIO_PIBC2_PIBC24_SHIFT                 (4u)
+#define GPIO_PIBC2_PIBC25_SHIFT                 (5u)
+#define GPIO_PIBC2_PIBC26_SHIFT                 (6u)
+#define GPIO_PIBC2_PIBC27_SHIFT                 (7u)
+#define GPIO_PIBC2_PIBC28_SHIFT                 (8u)
+#define GPIO_PIBC2_PIBC29_SHIFT                 (9u)
+#define GPIO_PIBC2_PIBC210_SHIFT                (10u)
+#define GPIO_PIBC2_PIBC211_SHIFT                (11u)
+#define GPIO_PIBC2_PIBC212_SHIFT                (12u)
+#define GPIO_PIBC2_PIBC213_SHIFT                (13u)
+#define GPIO_PIBC2_PIBC214_SHIFT                (14u)
+#define GPIO_PIBC2_PIBC215_SHIFT                (15u)
+
+#define GPIO_PBDC2_PBDC20_SHIFT                 (0u)
+#define GPIO_PBDC2_PBDC21_SHIFT                 (1u)
+#define GPIO_PBDC2_PBDC22_SHIFT                 (2u)
+#define GPIO_PBDC2_PBDC23_SHIFT                 (3u)
+#define GPIO_PBDC2_PBDC24_SHIFT                 (4u)
+#define GPIO_PBDC2_PBDC25_SHIFT                 (5u)
+#define GPIO_PBDC2_PBDC26_SHIFT                 (6u)
+#define GPIO_PBDC2_PBDC27_SHIFT                 (7u)
+#define GPIO_PBDC2_PBDC28_SHIFT                 (8u)
+#define GPIO_PBDC2_PBDC29_SHIFT                 (9u)
+#define GPIO_PBDC2_PBDC210_SHIFT                (10u)
+#define GPIO_PBDC2_PBDC211_SHIFT                (11u)
+#define GPIO_PBDC2_PBDC212_SHIFT                (12u)
+#define GPIO_PBDC2_PBDC213_SHIFT                (13u)
+#define GPIO_PBDC2_PBDC214_SHIFT                (14u)
+#define GPIO_PBDC2_PBDC215_SHIFT                (15u)
+
+#define GPIO_PIPC2_PIPC20_SHIFT                 (0u)
+#define GPIO_PIPC2_PIPC21_SHIFT                 (1u)
+#define GPIO_PIPC2_PIPC22_SHIFT                 (2u)
+#define GPIO_PIPC2_PIPC23_SHIFT                 (3u)
+#define GPIO_PIPC2_PIPC24_SHIFT                 (4u)
+#define GPIO_PIPC2_PIPC25_SHIFT                 (5u)
+#define GPIO_PIPC2_PIPC26_SHIFT                 (6u)
+#define GPIO_PIPC2_PIPC27_SHIFT                 (7u)
+#define GPIO_PIPC2_PIPC28_SHIFT                 (8u)
+#define GPIO_PIPC2_PIPC29_SHIFT                 (9u)
+#define GPIO_PIPC2_PIPC210_SHIFT                (10u)
+#define GPIO_PIPC2_PIPC211_SHIFT                (11u)
+#define GPIO_PIPC2_PIPC212_SHIFT                (12u)
+#define GPIO_PIPC2_PIPC213_SHIFT                (13u)
+#define GPIO_PIPC2_PIPC214_SHIFT                (14u)
+#define GPIO_PIPC2_PIPC215_SHIFT                (15u)
+
+/* ---- P3 ---- */
+#define GPIO_P3_P30_SHIFT                       (0u)
+#define GPIO_P3_P31_SHIFT                       (1u)
+#define GPIO_P3_P32_SHIFT                       (2u)
+#define GPIO_P3_P33_SHIFT                       (3u)
+#define GPIO_P3_P34_SHIFT                       (4u)
+#define GPIO_P3_P35_SHIFT                       (5u)
+#define GPIO_P3_P36_SHIFT                       (6u)
+#define GPIO_P3_P37_SHIFT                       (7u)
+#define GPIO_P3_P38_SHIFT                       (8u)
+#define GPIO_P3_P39_SHIFT                       (9u)
+#define GPIO_P3_P310_SHIFT                      (10u)
+#define GPIO_P3_P311_SHIFT                      (11u)
+#define GPIO_P3_P312_SHIFT                      (12u)
+#define GPIO_P3_P313_SHIFT                      (13u)
+#define GPIO_P3_P314_SHIFT                      (14u)
+#define GPIO_P3_P315_SHIFT                      (15u)
+
+#define GPIO_PSR3_PSR30_SHIFT                   (0u)
+#define GPIO_PSR3_PSR31_SHIFT                   (1u)
+#define GPIO_PSR3_PSR32_SHIFT                   (2u)
+#define GPIO_PSR3_PSR33_SHIFT                   (3u)
+#define GPIO_PSR3_PSR34_SHIFT                   (4u)
+#define GPIO_PSR3_PSR35_SHIFT                   (5u)
+#define GPIO_PSR3_PSR36_SHIFT                   (6u)
+#define GPIO_PSR3_PSR37_SHIFT                   (7u)
+#define GPIO_PSR3_PSR38_SHIFT                   (8u)
+#define GPIO_PSR3_PSR39_SHIFT                   (9u)
+#define GPIO_PSR3_PSR310_SHIFT                  (10u)
+#define GPIO_PSR3_PSR311_SHIFT                  (11u)
+#define GPIO_PSR3_PSR312_SHIFT                  (12u)
+#define GPIO_PSR3_PSR313_SHIFT                  (13u)
+#define GPIO_PSR3_PSR314_SHIFT                  (14u)
+#define GPIO_PSR3_PSR315_SHIFT                  (15u)
+#define GPIO_PSR3_PSR316_SHIFT                  (16u)
+#define GPIO_PSR3_PSR317_SHIFT                  (17u)
+#define GPIO_PSR3_PSR318_SHIFT                  (18u)
+#define GPIO_PSR3_PSR319_SHIFT                  (19u)
+#define GPIO_PSR3_PSR320_SHIFT                  (20u)
+#define GPIO_PSR3_PSR321_SHIFT                  (21u)
+#define GPIO_PSR3_PSR322_SHIFT                  (22u)
+#define GPIO_PSR3_PSR323_SHIFT                  (23u)
+#define GPIO_PSR3_PSR324_SHIFT                  (24u)
+#define GPIO_PSR3_PSR325_SHIFT                  (25u)
+#define GPIO_PSR3_PSR326_SHIFT                  (26u)
+#define GPIO_PSR3_PSR327_SHIFT                  (27u)
+#define GPIO_PSR3_PSR328_SHIFT                  (28u)
+#define GPIO_PSR3_PSR329_SHIFT                  (29u)
+#define GPIO_PSR3_PSR330_SHIFT                  (30u)
+#define GPIO_PSR3_PSR331_SHIFT                  (31u)
+
+#define GPIO_PPR3_PPR30_SHIFT                   (0u)
+#define GPIO_PPR3_PPR31_SHIFT                   (1u)
+#define GPIO_PPR3_PPR32_SHIFT                   (2u)
+#define GPIO_PPR3_PPR33_SHIFT                   (3u)
+#define GPIO_PPR3_PPR34_SHIFT                   (4u)
+#define GPIO_PPR3_PPR35_SHIFT                   (5u)
+#define GPIO_PPR3_PPR36_SHIFT                   (6u)
+#define GPIO_PPR3_PPR37_SHIFT                   (7u)
+#define GPIO_PPR3_PPR38_SHIFT                   (8u)
+#define GPIO_PPR3_PPR39_SHIFT                   (9u)
+#define GPIO_PPR3_PPR310_SHIFT                  (10u)
+#define GPIO_PPR3_PPR311_SHIFT                  (11u)
+#define GPIO_PPR3_PPR312_SHIFT                  (12u)
+#define GPIO_PPR3_PPR313_SHIFT                  (13u)
+#define GPIO_PPR3_PPR314_SHIFT                  (14u)
+#define GPIO_PPR3_PPR315_SHIFT                  (15u)
+
+#define GPIO_PM3_PM30_SHIFT                     (0u)
+#define GPIO_PM3_PM31_SHIFT                     (1u)
+#define GPIO_PM3_PM32_SHIFT                     (2u)
+#define GPIO_PM3_PM33_SHIFT                     (3u)
+#define GPIO_PM3_PM34_SHIFT                     (4u)
+#define GPIO_PM3_PM35_SHIFT                     (5u)
+#define GPIO_PM3_PM36_SHIFT                     (6u)
+#define GPIO_PM3_PM37_SHIFT                     (7u)
+#define GPIO_PM3_PM38_SHIFT                     (8u)
+#define GPIO_PM3_PM39_SHIFT                     (9u)
+#define GPIO_PM3_PM310_SHIFT                    (10u)
+#define GPIO_PM3_PM311_SHIFT                    (11u)
+#define GPIO_PM3_PM312_SHIFT                    (12u)
+#define GPIO_PM3_PM313_SHIFT                    (13u)
+#define GPIO_PM3_PM314_SHIFT                    (14u)
+#define GPIO_PM3_PM315_SHIFT                    (15u)
+
+#define GPIO_PMC3_PMC30_SHIFT                   (0u)
+#define GPIO_PMC3_PMC31_SHIFT                   (1u)
+#define GPIO_PMC3_PMC32_SHIFT                   (2u)
+#define GPIO_PMC3_PMC33_SHIFT                   (3u)
+#define GPIO_PMC3_PMC34_SHIFT                   (4u)
+#define GPIO_PMC3_PMC35_SHIFT                   (5u)
+#define GPIO_PMC3_PMC36_SHIFT                   (6u)
+#define GPIO_PMC3_PMC37_SHIFT                   (7u)
+#define GPIO_PMC3_PMC38_SHIFT                   (8u)
+#define GPIO_PMC3_PMC39_SHIFT                   (9u)
+#define GPIO_PMC3_PMC310_SHIFT                  (10u)
+#define GPIO_PMC3_PMC311_SHIFT                  (11u)
+#define GPIO_PMC3_PMC312_SHIFT                  (12u)
+#define GPIO_PMC3_PMC313_SHIFT                  (13u)
+#define GPIO_PMC3_PMC314_SHIFT                  (14u)
+#define GPIO_PMC3_PMC315_SHIFT                  (15u)
+
+#define GPIO_PFC3_PFC30_SHIFT                   (0u)
+#define GPIO_PFC3_PFC31_SHIFT                   (1u)
+#define GPIO_PFC3_PFC32_SHIFT                   (2u)
+#define GPIO_PFC3_PFC33_SHIFT                   (3u)
+#define GPIO_PFC3_PFC34_SHIFT                   (4u)
+#define GPIO_PFC3_PFC35_SHIFT                   (5u)
+#define GPIO_PFC3_PFC36_SHIFT                   (6u)
+#define GPIO_PFC3_PFC37_SHIFT                   (7u)
+#define GPIO_PFC3_PFC38_SHIFT                   (8u)
+#define GPIO_PFC3_PFC39_SHIFT                   (9u)
+#define GPIO_PFC3_PFC310_SHIFT                  (10u)
+#define GPIO_PFC3_PFC311_SHIFT                  (11u)
+#define GPIO_PFC3_PFC312_SHIFT                  (12u)
+#define GPIO_PFC3_PFC313_SHIFT                  (13u)
+#define GPIO_PFC3_PFC314_SHIFT                  (14u)
+#define GPIO_PFC3_PFC315_SHIFT                  (15u)
+
+#define GPIO_PFCE3_PFCE30_SHIFT                 (0u)
+#define GPIO_PFCE3_PFCE31_SHIFT                 (1u)
+#define GPIO_PFCE3_PFCE32_SHIFT                 (2u)
+#define GPIO_PFCE3_PFCE33_SHIFT                 (3u)
+#define GPIO_PFCE3_PFCE34_SHIFT                 (4u)
+#define GPIO_PFCE3_PFCE35_SHIFT                 (5u)
+#define GPIO_PFCE3_PFCE36_SHIFT                 (6u)
+#define GPIO_PFCE3_PFCE37_SHIFT                 (7u)
+#define GPIO_PFCE3_PFCE38_SHIFT                 (8u)
+#define GPIO_PFCE3_PFCE39_SHIFT                 (9u)
+#define GPIO_PFCE3_PFCE310_SHIFT                (10u)
+#define GPIO_PFCE3_PFCE311_SHIFT                (11u)
+#define GPIO_PFCE3_PFCE312_SHIFT                (12u)
+#define GPIO_PFCE3_PFCE313_SHIFT                (13u)
+#define GPIO_PFCE3_PFCE314_SHIFT                (14u)
+#define GPIO_PFCE3_PFCE315_SHIFT                (15u)
+
+#define GPIO_PNOT3_PNOT30_SHIFT                 (0u)
+#define GPIO_PNOT3_PNOT31_SHIFT                 (1u)
+#define GPIO_PNOT3_PNOT32_SHIFT                 (2u)
+#define GPIO_PNOT3_PNOT33_SHIFT                 (3u)
+#define GPIO_PNOT3_PNOT34_SHIFT                 (4u)
+#define GPIO_PNOT3_PNOT35_SHIFT                 (5u)
+#define GPIO_PNOT3_PNOT36_SHIFT                 (6u)
+#define GPIO_PNOT3_PNOT37_SHIFT                 (7u)
+#define GPIO_PNOT3_PNOT38_SHIFT                 (8u)
+#define GPIO_PNOT3_PNOT39_SHIFT                 (9u)
+#define GPIO_PNOT3_PNOT310_SHIFT                (10u)
+#define GPIO_PNOT3_PNOT311_SHIFT                (11u)
+#define GPIO_PNOT3_PNOT312_SHIFT                (12u)
+#define GPIO_PNOT3_PNOT313_SHIFT                (13u)
+#define GPIO_PNOT3_PNOT314_SHIFT                (14u)
+#define GPIO_PNOT3_PNOT315_SHIFT                (15u)
+
+#define GPIO_PMSR3_PMSR30_SHIFT                 (0u)
+#define GPIO_PMSR3_PMSR31_SHIFT                 (1u)
+#define GPIO_PMSR3_PMSR32_SHIFT                 (2u)
+#define GPIO_PMSR3_PMSR33_SHIFT                 (3u)
+#define GPIO_PMSR3_PMSR34_SHIFT                 (4u)
+#define GPIO_PMSR3_PMSR35_SHIFT                 (5u)
+#define GPIO_PMSR3_PMSR36_SHIFT                 (6u)
+#define GPIO_PMSR3_PMSR37_SHIFT                 (7u)
+#define GPIO_PMSR3_PMSR38_SHIFT                 (8u)
+#define GPIO_PMSR3_PMSR39_SHIFT                 (9u)
+#define GPIO_PMSR3_PMSR310_SHIFT                (10u)
+#define GPIO_PMSR3_PMSR311_SHIFT                (11u)
+#define GPIO_PMSR3_PMSR312_SHIFT                (12u)
+#define GPIO_PMSR3_PMSR313_SHIFT                (13u)
+#define GPIO_PMSR3_PMSR314_SHIFT                (14u)
+#define GPIO_PMSR3_PMSR315_SHIFT                (15u)
+#define GPIO_PMSR3_PMSR316_SHIFT                (16u)
+#define GPIO_PMSR3_PMSR317_SHIFT                (17u)
+#define GPIO_PMSR3_PMSR318_SHIFT                (18u)
+#define GPIO_PMSR3_PMSR319_SHIFT                (19u)
+#define GPIO_PMSR3_PMSR320_SHIFT                (20u)
+#define GPIO_PMSR3_PMSR321_SHIFT                (21u)
+#define GPIO_PMSR3_PMSR322_SHIFT                (22u)
+#define GPIO_PMSR3_PMSR323_SHIFT                (23u)
+#define GPIO_PMSR3_PMSR324_SHIFT                (24u)
+#define GPIO_PMSR3_PMSR325_SHIFT                (25u)
+#define GPIO_PMSR3_PMSR326_SHIFT                (26u)
+#define GPIO_PMSR3_PMSR327_SHIFT                (27u)
+#define GPIO_PMSR3_PMSR328_SHIFT                (28u)
+#define GPIO_PMSR3_PMSR329_SHIFT                (29u)
+#define GPIO_PMSR3_PMSR330_SHIFT                (30u)
+#define GPIO_PMSR3_PMSR331_SHIFT                (31u)
+
+#define GPIO_PMCSR3_PMCSR30_SHIFT               (0u)
+#define GPIO_PMCSR3_PMCSR31_SHIFT               (1u)
+#define GPIO_PMCSR3_PMCSR32_SHIFT               (2u)
+#define GPIO_PMCSR3_PMCSR33_SHIFT               (3u)
+#define GPIO_PMCSR3_PMCSR34_SHIFT               (4u)
+#define GPIO_PMCSR3_PMCSR35_SHIFT               (5u)
+#define GPIO_PMCSR3_PMCSR36_SHIFT               (6u)
+#define GPIO_PMCSR3_PMCSR37_SHIFT               (7u)
+#define GPIO_PMCSR3_PMCSR38_SHIFT               (8u)
+#define GPIO_PMCSR3_PMCSR39_SHIFT               (9u)
+#define GPIO_PMCSR3_PMCSR310_SHIFT              (10u)
+#define GPIO_PMCSR3_PMCSR311_SHIFT              (11u)
+#define GPIO_PMCSR3_PMCSR312_SHIFT              (12u)
+#define GPIO_PMCSR3_PMCSR313_SHIFT              (13u)
+#define GPIO_PMCSR3_PMCSR314_SHIFT              (14u)
+#define GPIO_PMCSR3_PMCSR315_SHIFT              (15u)
+#define GPIO_PMCSR3_PMCSR316_SHIFT              (16u)
+#define GPIO_PMCSR3_PMCSR317_SHIFT              (17u)
+#define GPIO_PMCSR3_PMCSR318_SHIFT              (18u)
+#define GPIO_PMCSR3_PMCSR319_SHIFT              (19u)
+#define GPIO_PMCSR3_PMCSR320_SHIFT              (20u)
+#define GPIO_PMCSR3_PMCSR321_SHIFT              (21u)
+#define GPIO_PMCSR3_PMCSR322_SHIFT              (22u)
+#define GPIO_PMCSR3_PMCSR323_SHIFT              (23u)
+#define GPIO_PMCSR3_PMCSR324_SHIFT              (24u)
+#define GPIO_PMCSR3_PMCSR325_SHIFT              (25u)
+#define GPIO_PMCSR3_PMCSR326_SHIFT              (26u)
+#define GPIO_PMCSR3_PMCSR327_SHIFT              (27u)
+#define GPIO_PMCSR3_PMCSR328_SHIFT              (28u)
+#define GPIO_PMCSR3_PMCSR329_SHIFT              (29u)
+#define GPIO_PMCSR3_PMCSR330_SHIFT              (30u)
+#define GPIO_PMCSR3_PMCSR331_SHIFT              (31u)
+
+#define GPIO_PFCAE3_PFCAE30_SHIFT               (0u)
+#define GPIO_PFCAE3_PFCAE31_SHIFT               (1u)
+#define GPIO_PFCAE3_PFCAE32_SHIFT               (2u)
+#define GPIO_PFCAE3_PFCAE33_SHIFT               (3u)
+#define GPIO_PFCAE3_PFCAE34_SHIFT               (4u)
+#define GPIO_PFCAE3_PFCAE35_SHIFT               (5u)
+#define GPIO_PFCAE3_PFCAE36_SHIFT               (6u)
+#define GPIO_PFCAE3_PFCAE37_SHIFT               (7u)
+#define GPIO_PFCAE3_PFCAE38_SHIFT               (8u)
+#define GPIO_PFCAE3_PFCAE39_SHIFT               (9u)
+#define GPIO_PFCAE3_PFCAE310_SHIFT              (10u)
+#define GPIO_PFCAE3_PFCAE311_SHIFT              (11u)
+#define GPIO_PFCAE3_PFCAE312_SHIFT              (12u)
+#define GPIO_PFCAE3_PFCAE313_SHIFT              (13u)
+#define GPIO_PFCAE3_PFCAE314_SHIFT              (14u)
+#define GPIO_PFCAE3_PFCAE315_SHIFT              (15u)
+
+#define GPIO_PIBC3_PIBC30_SHIFT                 (0u)
+#define GPIO_PIBC3_PIBC31_SHIFT                 (1u)
+#define GPIO_PIBC3_PIBC32_SHIFT                 (2u)
+#define GPIO_PIBC3_PIBC33_SHIFT                 (3u)
+#define GPIO_PIBC3_PIBC34_SHIFT                 (4u)
+#define GPIO_PIBC3_PIBC35_SHIFT                 (5u)
+#define GPIO_PIBC3_PIBC36_SHIFT                 (6u)
+#define GPIO_PIBC3_PIBC37_SHIFT                 (7u)
+#define GPIO_PIBC3_PIBC38_SHIFT                 (8u)
+#define GPIO_PIBC3_PIBC39_SHIFT                 (9u)
+#define GPIO_PIBC3_PIBC310_SHIFT                (10u)
+#define GPIO_PIBC3_PIBC311_SHIFT                (11u)
+#define GPIO_PIBC3_PIBC312_SHIFT                (12u)
+#define GPIO_PIBC3_PIBC313_SHIFT                (13u)
+#define GPIO_PIBC3_PIBC314_SHIFT                (14u)
+#define GPIO_PIBC3_PIBC315_SHIFT                (15u)
+
+#define GPIO_PBDC3_PBDC30_SHIFT                 (0u)
+#define GPIO_PBDC3_PBDC31_SHIFT                 (1u)
+#define GPIO_PBDC3_PBDC32_SHIFT                 (2u)
+#define GPIO_PBDC3_PBDC33_SHIFT                 (3u)
+#define GPIO_PBDC3_PBDC34_SHIFT                 (4u)
+#define GPIO_PBDC3_PBDC35_SHIFT                 (5u)
+#define GPIO_PBDC3_PBDC36_SHIFT                 (6u)
+#define GPIO_PBDC3_PBDC37_SHIFT                 (7u)
+#define GPIO_PBDC3_PBDC38_SHIFT                 (8u)
+#define GPIO_PBDC3_PBDC39_SHIFT                 (9u)
+#define GPIO_PBDC3_PBDC310_SHIFT                (10u)
+#define GPIO_PBDC3_PBDC311_SHIFT                (11u)
+#define GPIO_PBDC3_PBDC312_SHIFT                (12u)
+#define GPIO_PBDC3_PBDC313_SHIFT                (13u)
+#define GPIO_PBDC3_PBDC314_SHIFT                (14u)
+#define GPIO_PBDC3_PBDC315_SHIFT                (15u)
+
+#define GPIO_PIPC3_PIPC30_SHIFT                 (0u)
+#define GPIO_PIPC3_PIPC31_SHIFT                 (1u)
+#define GPIO_PIPC3_PIPC32_SHIFT                 (2u)
+#define GPIO_PIPC3_PIPC33_SHIFT                 (3u)
+#define GPIO_PIPC3_PIPC34_SHIFT                 (4u)
+#define GPIO_PIPC3_PIPC35_SHIFT                 (5u)
+#define GPIO_PIPC3_PIPC36_SHIFT                 (6u)
+#define GPIO_PIPC3_PIPC37_SHIFT                 (7u)
+#define GPIO_PIPC3_PIPC38_SHIFT                 (8u)
+#define GPIO_PIPC3_PIPC39_SHIFT                 (9u)
+#define GPIO_PIPC3_PIPC310_SHIFT                (10u)
+#define GPIO_PIPC3_PIPC311_SHIFT                (11u)
+#define GPIO_PIPC3_PIPC312_SHIFT                (12u)
+#define GPIO_PIPC3_PIPC313_SHIFT                (13u)
+#define GPIO_PIPC3_PIPC314_SHIFT                (14u)
+#define GPIO_PIPC3_PIPC315_SHIFT                (15u)
+
+/* ---- P4 ---- */
+#define GPIO_P4_P40_SHIFT                       (0u)
+#define GPIO_P4_P41_SHIFT                       (1u)
+#define GPIO_P4_P42_SHIFT                       (2u)
+#define GPIO_P4_P43_SHIFT                       (3u)
+#define GPIO_P4_P44_SHIFT                       (4u)
+#define GPIO_P4_P45_SHIFT                       (5u)
+#define GPIO_P4_P46_SHIFT                       (6u)
+#define GPIO_P4_P47_SHIFT                       (7u)
+#define GPIO_P4_P48_SHIFT                       (8u)
+#define GPIO_P4_P49_SHIFT                       (9u)
+#define GPIO_P4_P410_SHIFT                      (10u)
+#define GPIO_P4_P411_SHIFT                      (11u)
+#define GPIO_P4_P412_SHIFT                      (12u)
+#define GPIO_P4_P413_SHIFT                      (13u)
+#define GPIO_P4_P414_SHIFT                      (14u)
+#define GPIO_P4_P415_SHIFT                      (15u)
+
+#define GPIO_PSR4_PSR40_SHIFT                   (0u)
+#define GPIO_PSR4_PSR41_SHIFT                   (1u)
+#define GPIO_PSR4_PSR42_SHIFT                   (2u)
+#define GPIO_PSR4_PSR43_SHIFT                   (3u)
+#define GPIO_PSR4_PSR44_SHIFT                   (4u)
+#define GPIO_PSR4_PSR45_SHIFT                   (5u)
+#define GPIO_PSR4_PSR46_SHIFT                   (6u)
+#define GPIO_PSR4_PSR47_SHIFT                   (7u)
+#define GPIO_PSR4_PSR48_SHIFT                   (8u)
+#define GPIO_PSR4_PSR49_SHIFT                   (9u)
+#define GPIO_PSR4_PSR410_SHIFT                  (10u)
+#define GPIO_PSR4_PSR411_SHIFT                  (11u)
+#define GPIO_PSR4_PSR412_SHIFT                  (12u)
+#define GPIO_PSR4_PSR413_SHIFT                  (13u)
+#define GPIO_PSR4_PSR414_SHIFT                  (14u)
+#define GPIO_PSR4_PSR415_SHIFT                  (15u)
+#define GPIO_PSR4_PSR416_SHIFT                  (16u)
+#define GPIO_PSR4_PSR417_SHIFT                  (17u)
+#define GPIO_PSR4_PSR418_SHIFT                  (18u)
+#define GPIO_PSR4_PSR419_SHIFT                  (19u)
+#define GPIO_PSR4_PSR420_SHIFT                  (20u)
+#define GPIO_PSR4_PSR421_SHIFT                  (21u)
+#define GPIO_PSR4_PSR422_SHIFT                  (22u)
+#define GPIO_PSR4_PSR423_SHIFT                  (23u)
+#define GPIO_PSR4_PSR424_SHIFT                  (24u)
+#define GPIO_PSR4_PSR425_SHIFT                  (25u)
+#define GPIO_PSR4_PSR426_SHIFT                  (26u)
+#define GPIO_PSR4_PSR427_SHIFT                  (27u)
+#define GPIO_PSR4_PSR428_SHIFT                  (28u)
+#define GPIO_PSR4_PSR429_SHIFT                  (29u)
+#define GPIO_PSR4_PSR430_SHIFT                  (30u)
+#define GPIO_PSR4_PSR431_SHIFT                  (31u)
+
+#define GPIO_PPR4_PPR40_SHIFT                   (0u)
+#define GPIO_PPR4_PPR41_SHIFT                   (1u)
+#define GPIO_PPR4_PPR42_SHIFT                   (2u)
+#define GPIO_PPR4_PPR43_SHIFT                   (3u)
+#define GPIO_PPR4_PPR44_SHIFT                   (4u)
+#define GPIO_PPR4_PPR45_SHIFT                   (5u)
+#define GPIO_PPR4_PPR46_SHIFT                   (6u)
+#define GPIO_PPR4_PPR47_SHIFT                   (7u)
+#define GPIO_PPR4_PPR48_SHIFT                   (8u)
+#define GPIO_PPR4_PPR49_SHIFT                   (9u)
+#define GPIO_PPR4_PPR410_SHIFT                  (10u)
+#define GPIO_PPR4_PPR411_SHIFT                  (11u)
+#define GPIO_PPR4_PPR412_SHIFT                  (12u)
+#define GPIO_PPR4_PPR413_SHIFT                  (13u)
+#define GPIO_PPR4_PPR414_SHIFT                  (14u)
+#define GPIO_PPR4_PPR415_SHIFT                  (15u)
+
+#define GPIO_PM4_PM40_SHIFT                     (0u)
+#define GPIO_PM4_PM41_SHIFT                     (1u)
+#define GPIO_PM4_PM42_SHIFT                     (2u)
+#define GPIO_PM4_PM43_SHIFT                     (3u)
+#define GPIO_PM4_PM44_SHIFT                     (4u)
+#define GPIO_PM4_PM45_SHIFT                     (5u)
+#define GPIO_PM4_PM46_SHIFT                     (6u)
+#define GPIO_PM4_PM47_SHIFT                     (7u)
+#define GPIO_PM4_PM48_SHIFT                     (8u)
+#define GPIO_PM4_PM49_SHIFT                     (9u)
+#define GPIO_PM4_PM410_SHIFT                    (10u)
+#define GPIO_PM4_PM411_SHIFT                    (11u)
+#define GPIO_PM4_PM412_SHIFT                    (12u)
+#define GPIO_PM4_PM413_SHIFT                    (13u)
+#define GPIO_PM4_PM414_SHIFT                    (14u)
+#define GPIO_PM4_PM415_SHIFT                    (15u)
+
+#define GPIO_PMC4_PMC40_SHIFT                   (0u)
+#define GPIO_PMC4_PMC41_SHIFT                   (1u)
+#define GPIO_PMC4_PMC42_SHIFT                   (2u)
+#define GPIO_PMC4_PMC43_SHIFT                   (3u)
+#define GPIO_PMC4_PMC44_SHIFT                   (4u)
+#define GPIO_PMC4_PMC45_SHIFT                   (5u)
+#define GPIO_PMC4_PMC46_SHIFT                   (6u)
+#define GPIO_PMC4_PMC47_SHIFT                   (7u)
+#define GPIO_PMC4_PMC48_SHIFT                   (8u)
+#define GPIO_PMC4_PMC49_SHIFT                   (9u)
+#define GPIO_PMC4_PMC410_SHIFT                  (10u)
+#define GPIO_PMC4_PMC411_SHIFT                  (11u)
+#define GPIO_PMC4_PMC412_SHIFT                  (12u)
+#define GPIO_PMC4_PMC413_SHIFT                  (13u)
+#define GPIO_PMC4_PMC414_SHIFT                  (14u)
+#define GPIO_PMC4_PMC415_SHIFT                  (15u)
+
+#define GPIO_PFC4_PFC40_SHIFT                   (0u)
+#define GPIO_PFC4_PFC41_SHIFT                   (1u)
+#define GPIO_PFC4_PFC42_SHIFT                   (2u)
+#define GPIO_PFC4_PFC43_SHIFT                   (3u)
+#define GPIO_PFC4_PFC44_SHIFT                   (4u)
+#define GPIO_PFC4_PFC45_SHIFT                   (5u)
+#define GPIO_PFC4_PFC46_SHIFT                   (6u)
+#define GPIO_PFC4_PFC47_SHIFT                   (7u)
+#define GPIO_PFC4_PFC48_SHIFT                   (8u)
+#define GPIO_PFC4_PFC49_SHIFT                   (9u)
+#define GPIO_PFC4_PFC410_SHIFT                  (10u)
+#define GPIO_PFC4_PFC411_SHIFT                  (11u)
+#define GPIO_PFC4_PFC412_SHIFT                  (12u)
+#define GPIO_PFC4_PFC413_SHIFT                  (13u)
+#define GPIO_PFC4_PFC414_SHIFT                  (14u)
+#define GPIO_PFC4_PFC415_SHIFT                  (15u)
+
+#define GPIO_PFCE4_PFCE40_SHIFT                 (0u)
+#define GPIO_PFCE4_PFCE41_SHIFT                 (1u)
+#define GPIO_PFCE4_PFCE42_SHIFT                 (2u)
+#define GPIO_PFCE4_PFCE43_SHIFT                 (3u)
+#define GPIO_PFCE4_PFCE44_SHIFT                 (4u)
+#define GPIO_PFCE4_PFCE45_SHIFT                 (5u)
+#define GPIO_PFCE4_PFCE46_SHIFT                 (6u)
+#define GPIO_PFCE4_PFCE47_SHIFT                 (7u)
+#define GPIO_PFCE4_PFCE48_SHIFT                 (8u)
+#define GPIO_PFCE4_PFCE49_SHIFT                 (9u)
+#define GPIO_PFCE4_PFCE410_SHIFT                (10u)
+#define GPIO_PFCE4_PFCE411_SHIFT                (11u)
+#define GPIO_PFCE4_PFCE412_SHIFT                (12u)
+#define GPIO_PFCE4_PFCE413_SHIFT                (13u)
+#define GPIO_PFCE4_PFCE414_SHIFT                (14u)
+#define GPIO_PFCE4_PFCE415_SHIFT                (15u)
+
+#define GPIO_PNOT4_PNOT40_SHIFT                 (0u)
+#define GPIO_PNOT4_PNOT41_SHIFT                 (1u)
+#define GPIO_PNOT4_PNOT42_SHIFT                 (2u)
+#define GPIO_PNOT4_PNOT43_SHIFT                 (3u)
+#define GPIO_PNOT4_PNOT44_SHIFT                 (4u)
+#define GPIO_PNOT4_PNOT45_SHIFT                 (5u)
+#define GPIO_PNOT4_PNOT46_SHIFT                 (6u)
+#define GPIO_PNOT4_PNOT47_SHIFT                 (7u)
+#define GPIO_PNOT4_PNOT48_SHIFT                 (8u)
+#define GPIO_PNOT4_PNOT49_SHIFT                 (9u)
+#define GPIO_PNOT4_PNOT410_SHIFT                (10u)
+#define GPIO_PNOT4_PNOT411_SHIFT                (11u)
+#define GPIO_PNOT4_PNOT412_SHIFT                (12u)
+#define GPIO_PNOT4_PNOT413_SHIFT                (13u)
+#define GPIO_PNOT4_PNOT414_SHIFT                (14u)
+#define GPIO_PNOT4_PNOT415_SHIFT                (15u)
+
+#define GPIO_PMSR4_PMSR40_SHIFT                 (0u)
+#define GPIO_PMSR4_PMSR41_SHIFT                 (1u)
+#define GPIO_PMSR4_PMSR42_SHIFT                 (2u)
+#define GPIO_PMSR4_PMSR43_SHIFT                 (3u)
+#define GPIO_PMSR4_PMSR44_SHIFT                 (4u)
+#define GPIO_PMSR4_PMSR45_SHIFT                 (5u)
+#define GPIO_PMSR4_PMSR46_SHIFT                 (6u)
+#define GPIO_PMSR4_PMSR47_SHIFT                 (7u)
+#define GPIO_PMSR4_PMSR48_SHIFT                 (8u)
+#define GPIO_PMSR4_PMSR49_SHIFT                 (9u)
+#define GPIO_PMSR4_PMSR410_SHIFT                (10u)
+#define GPIO_PMSR4_PMSR411_SHIFT                (11u)
+#define GPIO_PMSR4_PMSR412_SHIFT                (12u)
+#define GPIO_PMSR4_PMSR413_SHIFT                (13u)
+#define GPIO_PMSR4_PMSR414_SHIFT                (14u)
+#define GPIO_PMSR4_PMSR415_SHIFT                (15u)
+#define GPIO_PMSR4_PMSR416_SHIFT                (16u)
+#define GPIO_PMSR4_PMSR417_SHIFT                (17u)
+#define GPIO_PMSR4_PMSR418_SHIFT                (18u)
+#define GPIO_PMSR4_PMSR419_SHIFT                (19u)
+#define GPIO_PMSR4_PMSR420_SHIFT                (20u)
+#define GPIO_PMSR4_PMSR421_SHIFT                (21u)
+#define GPIO_PMSR4_PMSR422_SHIFT                (22u)
+#define GPIO_PMSR4_PMSR423_SHIFT                (23u)
+#define GPIO_PMSR4_PMSR424_SHIFT                (24u)
+#define GPIO_PMSR4_PMSR425_SHIFT                (25u)
+#define GPIO_PMSR4_PMSR426_SHIFT                (26u)
+#define GPIO_PMSR4_PMSR427_SHIFT                (27u)
+#define GPIO_PMSR4_PMSR428_SHIFT                (28u)
+#define GPIO_PMSR4_PMSR429_SHIFT                (29u)
+#define GPIO_PMSR4_PMSR430_SHIFT                (30u)
+#define GPIO_PMSR4_PMSR431_SHIFT                (31u)
+
+#define GPIO_PMCSR4_PMCSR40_SHIFT               (0u)
+#define GPIO_PMCSR4_PMCSR41_SHIFT               (1u)
+#define GPIO_PMCSR4_PMCSR42_SHIFT               (2u)
+#define GPIO_PMCSR4_PMCSR43_SHIFT               (3u)
+#define GPIO_PMCSR4_PMCSR44_SHIFT               (4u)
+#define GPIO_PMCSR4_PMCSR45_SHIFT               (5u)
+#define GPIO_PMCSR4_PMCSR46_SHIFT               (6u)
+#define GPIO_PMCSR4_PMCSR47_SHIFT               (7u)
+#define GPIO_PMCSR4_PMCSR48_SHIFT               (8u)
+#define GPIO_PMCSR4_PMCSR49_SHIFT               (9u)
+#define GPIO_PMCSR4_PMCSR410_SHIFT              (10u)
+#define GPIO_PMCSR4_PMCSR411_SHIFT              (11u)
+#define GPIO_PMCSR4_PMCSR412_SHIFT              (12u)
+#define GPIO_PMCSR4_PMCSR413_SHIFT              (13u)
+#define GPIO_PMCSR4_PMCSR414_SHIFT              (14u)
+#define GPIO_PMCSR4_PMCSR415_SHIFT              (15u)
+#define GPIO_PMCSR4_PMCSR416_SHIFT              (16u)
+#define GPIO_PMCSR4_PMCSR417_SHIFT              (17u)
+#define GPIO_PMCSR4_PMCSR418_SHIFT              (18u)
+#define GPIO_PMCSR4_PMCSR419_SHIFT              (19u)
+#define GPIO_PMCSR4_PMCSR420_SHIFT              (20u)
+#define GPIO_PMCSR4_PMCSR421_SHIFT              (21u)
+#define GPIO_PMCSR4_PMCSR422_SHIFT              (22u)
+#define GPIO_PMCSR4_PMCSR423_SHIFT              (23u)
+#define GPIO_PMCSR4_PMCSR424_SHIFT              (24u)
+#define GPIO_PMCSR4_PMCSR425_SHIFT              (25u)
+#define GPIO_PMCSR4_PMCSR426_SHIFT              (26u)
+#define GPIO_PMCSR4_PMCSR427_SHIFT              (27u)
+#define GPIO_PMCSR4_PMCSR428_SHIFT              (28u)
+#define GPIO_PMCSR4_PMCSR429_SHIFT              (29u)
+#define GPIO_PMCSR4_PMCSR430_SHIFT              (30u)
+#define GPIO_PMCSR4_PMCSR431_SHIFT              (31u)
+
+#define GPIO_PFCAE4_PFCAE40_SHIFT               (0u)
+#define GPIO_PFCAE4_PFCAE41_SHIFT               (1u)
+#define GPIO_PFCAE4_PFCAE42_SHIFT               (2u)
+#define GPIO_PFCAE4_PFCAE43_SHIFT               (3u)
+#define GPIO_PFCAE4_PFCAE44_SHIFT               (4u)
+#define GPIO_PFCAE4_PFCAE45_SHIFT               (5u)
+#define GPIO_PFCAE4_PFCAE46_SHIFT               (6u)
+#define GPIO_PFCAE4_PFCAE47_SHIFT               (7u)
+#define GPIO_PFCAE4_PFCAE48_SHIFT               (8u)
+#define GPIO_PFCAE4_PFCAE49_SHIFT               (9u)
+#define GPIO_PFCAE4_PFCAE410_SHIFT              (10u)
+#define GPIO_PFCAE4_PFCAE411_SHIFT              (11u)
+#define GPIO_PFCAE4_PFCAE412_SHIFT              (12u)
+#define GPIO_PFCAE4_PFCAE413_SHIFT              (13u)
+#define GPIO_PFCAE4_PFCAE414_SHIFT              (14u)
+#define GPIO_PFCAE4_PFCAE415_SHIFT              (15u)
+
+#define GPIO_PIBC4_PIBC40_SHIFT                 (0u)
+#define GPIO_PIBC4_PIBC41_SHIFT                 (1u)
+#define GPIO_PIBC4_PIBC42_SHIFT                 (2u)
+#define GPIO_PIBC4_PIBC43_SHIFT                 (3u)
+#define GPIO_PIBC4_PIBC44_SHIFT                 (4u)
+#define GPIO_PIBC4_PIBC45_SHIFT                 (5u)
+#define GPIO_PIBC4_PIBC46_SHIFT                 (6u)
+#define GPIO_PIBC4_PIBC47_SHIFT                 (7u)
+#define GPIO_PIBC4_PIBC48_SHIFT                 (8u)
+#define GPIO_PIBC4_PIBC49_SHIFT                 (9u)
+#define GPIO_PIBC4_PIBC410_SHIFT                (10u)
+#define GPIO_PIBC4_PIBC411_SHIFT                (11u)
+#define GPIO_PIBC4_PIBC412_SHIFT                (12u)
+#define GPIO_PIBC4_PIBC413_SHIFT                (13u)
+#define GPIO_PIBC4_PIBC414_SHIFT                (14u)
+#define GPIO_PIBC4_PIBC415_SHIFT                (15u)
+
+#define GPIO_PBDC4_PBDC40_SHIFT                 (0u)
+#define GPIO_PBDC4_PBDC41_SHIFT                 (1u)
+#define GPIO_PBDC4_PBDC42_SHIFT                 (2u)
+#define GPIO_PBDC4_PBDC43_SHIFT                 (3u)
+#define GPIO_PBDC4_PBDC44_SHIFT                 (4u)
+#define GPIO_PBDC4_PBDC45_SHIFT                 (5u)
+#define GPIO_PBDC4_PBDC46_SHIFT                 (6u)
+#define GPIO_PBDC4_PBDC47_SHIFT                 (7u)
+#define GPIO_PBDC4_PBDC48_SHIFT                 (8u)
+#define GPIO_PBDC4_PBDC49_SHIFT                 (9u)
+#define GPIO_PBDC4_PBDC410_SHIFT                (10u)
+#define GPIO_PBDC4_PBDC411_SHIFT                (11u)
+#define GPIO_PBDC4_PBDC412_SHIFT                (12u)
+#define GPIO_PBDC4_PBDC413_SHIFT                (13u)
+#define GPIO_PBDC4_PBDC414_SHIFT                (14u)
+#define GPIO_PBDC4_PBDC415_SHIFT                (15u)
+
+#define GPIO_PIPC4_PIPC40_SHIFT                 (0u)
+#define GPIO_PIPC4_PIPC41_SHIFT                 (1u)
+#define GPIO_PIPC4_PIPC42_SHIFT                 (2u)
+#define GPIO_PIPC4_PIPC43_SHIFT                 (3u)
+#define GPIO_PIPC4_PIPC44_SHIFT                 (4u)
+#define GPIO_PIPC4_PIPC45_SHIFT                 (5u)
+#define GPIO_PIPC4_PIPC46_SHIFT                 (6u)
+#define GPIO_PIPC4_PIPC47_SHIFT                 (7u)
+#define GPIO_PIPC4_PIPC48_SHIFT                 (8u)
+#define GPIO_PIPC4_PIPC49_SHIFT                 (9u)
+#define GPIO_PIPC4_PIPC410_SHIFT                (10u)
+#define GPIO_PIPC4_PIPC411_SHIFT                (11u)
+#define GPIO_PIPC4_PIPC412_SHIFT                (12u)
+#define GPIO_PIPC4_PIPC413_SHIFT                (13u)
+#define GPIO_PIPC4_PIPC414_SHIFT                (14u)
+#define GPIO_PIPC4_PIPC415_SHIFT                (15u)
+
+/* ---- P5 ---- */
+#define GPIO_P5_P50_SHIFT                       (0u)
+#define GPIO_P5_P51_SHIFT                       (1u)
+#define GPIO_P5_P52_SHIFT                       (2u)
+#define GPIO_P5_P53_SHIFT                       (3u)
+#define GPIO_P5_P54_SHIFT                       (4u)
+#define GPIO_P5_P55_SHIFT                       (5u)
+#define GPIO_P5_P56_SHIFT                       (6u)
+#define GPIO_P5_P57_SHIFT                       (7u)
+#define GPIO_P5_P58_SHIFT                       (8u)
+#define GPIO_P5_P59_SHIFT                       (9u)
+#define GPIO_P5_P510_SHIFT                      (10u)
+
+#define GPIO_PSR5_PSR50_SHIFT                   (0u)
+#define GPIO_PSR5_PSR51_SHIFT                   (1u)
+#define GPIO_PSR5_PSR52_SHIFT                   (2u)
+#define GPIO_PSR5_PSR53_SHIFT                   (3u)
+#define GPIO_PSR5_PSR54_SHIFT                   (4u)
+#define GPIO_PSR5_PSR55_SHIFT                   (5u)
+#define GPIO_PSR5_PSR56_SHIFT                   (6u)
+#define GPIO_PSR5_PSR57_SHIFT                   (7u)
+#define GPIO_PSR5_PSR58_SHIFT                   (8u)
+#define GPIO_PSR5_PSR59_SHIFT                   (9u)
+#define GPIO_PSR5_PSR510_SHIFT                  (10u)
+#define GPIO_PSR5_PSR516_SHIFT                  (16u)
+#define GPIO_PSR5_PSR517_SHIFT                  (17u)
+#define GPIO_PSR5_PSR518_SHIFT                  (18u)
+#define GPIO_PSR5_PSR519_SHIFT                  (19u)
+#define GPIO_PSR5_PSR520_SHIFT                  (20u)
+#define GPIO_PSR5_PSR521_SHIFT                  (21u)
+#define GPIO_PSR5_PSR522_SHIFT                  (22u)
+#define GPIO_PSR5_PSR523_SHIFT                  (23u)
+#define GPIO_PSR5_PSR524_SHIFT                  (24u)
+#define GPIO_PSR5_PSR525_SHIFT                  (25u)
+#define GPIO_PSR5_PSR526_SHIFT                  (26u)
+
+#define GPIO_PPR5_PPR50_SHIFT                   (0u)
+#define GPIO_PPR5_PPR51_SHIFT                   (1u)
+#define GPIO_PPR5_PPR52_SHIFT                   (2u)
+#define GPIO_PPR5_PPR53_SHIFT                   (3u)
+#define GPIO_PPR5_PPR54_SHIFT                   (4u)
+#define GPIO_PPR5_PPR55_SHIFT                   (5u)
+#define GPIO_PPR5_PPR56_SHIFT                   (6u)
+#define GPIO_PPR5_PPR57_SHIFT                   (7u)
+#define GPIO_PPR5_PPR58_SHIFT                   (8u)
+#define GPIO_PPR5_PPR59_SHIFT                   (9u)
+#define GPIO_PPR5_PPR510_SHIFT                  (10u)
+
+#define GPIO_PM5_PM50_SHIFT                     (0u)
+#define GPIO_PM5_PM51_SHIFT                     (1u)
+#define GPIO_PM5_PM52_SHIFT                     (2u)
+#define GPIO_PM5_PM53_SHIFT                     (3u)
+#define GPIO_PM5_PM54_SHIFT                     (4u)
+#define GPIO_PM5_PM55_SHIFT                     (5u)
+#define GPIO_PM5_PM56_SHIFT                     (6u)
+#define GPIO_PM5_PM57_SHIFT                     (7u)
+#define GPIO_PM5_PM58_SHIFT                     (8u)
+#define GPIO_PM5_PM59_SHIFT                     (9u)
+#define GPIO_PM5_PM510_SHIFT                    (10u)
+
+#define GPIO_PMC5_PMC50_SHIFT                   (0u)
+#define GPIO_PMC5_PMC51_SHIFT                   (1u)
+#define GPIO_PMC5_PMC52_SHIFT                   (2u)
+#define GPIO_PMC5_PMC53_SHIFT                   (3u)
+#define GPIO_PMC5_PMC54_SHIFT                   (4u)
+#define GPIO_PMC5_PMC55_SHIFT                   (5u)
+#define GPIO_PMC5_PMC56_SHIFT                   (6u)
+#define GPIO_PMC5_PMC57_SHIFT                   (7u)
+#define GPIO_PMC5_PMC58_SHIFT                   (8u)
+#define GPIO_PMC5_PMC59_SHIFT                   (9u)
+#define GPIO_PMC5_PMC510_SHIFT                  (10u)
+
+#define GPIO_PFC5_PFC50_SHIFT                   (0u)
+#define GPIO_PFC5_PFC51_SHIFT                   (1u)
+#define GPIO_PFC5_PFC52_SHIFT                   (2u)
+#define GPIO_PFC5_PFC53_SHIFT                   (3u)
+#define GPIO_PFC5_PFC54_SHIFT                   (4u)
+#define GPIO_PFC5_PFC55_SHIFT                   (5u)
+#define GPIO_PFC5_PFC56_SHIFT                   (6u)
+#define GPIO_PFC5_PFC57_SHIFT                   (7u)
+#define GPIO_PFC5_PFC58_SHIFT                   (8u)
+#define GPIO_PFC5_PFC59_SHIFT                   (9u)
+#define GPIO_PFC5_PFC510_SHIFT                  (10u)
+
+#define GPIO_PFCE5_PFCE50_SHIFT                 (0u)
+#define GPIO_PFCE5_PFCE51_SHIFT                 (1u)
+#define GPIO_PFCE5_PFCE52_SHIFT                 (2u)
+#define GPIO_PFCE5_PFCE53_SHIFT                 (3u)
+#define GPIO_PFCE5_PFCE54_SHIFT                 (4u)
+#define GPIO_PFCE5_PFCE55_SHIFT                 (5u)
+#define GPIO_PFCE5_PFCE56_SHIFT                 (6u)
+#define GPIO_PFCE5_PFCE57_SHIFT                 (7u)
+#define GPIO_PFCE5_PFCE58_SHIFT                 (8u)
+#define GPIO_PFCE5_PFCE59_SHIFT                 (9u)
+#define GPIO_PFCE5_PFCE510_SHIFT                (10u)
+
+#define GPIO_PNOT5_PNOT50_SHIFT                 (0u)
+#define GPIO_PNOT5_PNOT51_SHIFT                 (1u)
+#define GPIO_PNOT5_PNOT52_SHIFT                 (2u)
+#define GPIO_PNOT5_PNOT53_SHIFT                 (3u)
+#define GPIO_PNOT5_PNOT54_SHIFT                 (4u)
+#define GPIO_PNOT5_PNOT55_SHIFT                 (5u)
+#define GPIO_PNOT5_PNOT56_SHIFT                 (6u)
+#define GPIO_PNOT5_PNOT57_SHIFT                 (7u)
+#define GPIO_PNOT5_PNOT58_SHIFT                 (8u)
+#define GPIO_PNOT5_PNOT59_SHIFT                 (9u)
+#define GPIO_PNOT5_PNOT510_SHIFT                (10u)
+
+#define GPIO_PMSR5_PMSR50_SHIFT                 (0u)
+#define GPIO_PMSR5_PMSR51_SHIFT                 (1u)
+#define GPIO_PMSR5_PMSR52_SHIFT                 (2u)
+#define GPIO_PMSR5_PMSR53_SHIFT                 (3u)
+#define GPIO_PMSR5_PMSR54_SHIFT                 (4u)
+#define GPIO_PMSR5_PMSR55_SHIFT                 (5u)
+#define GPIO_PMSR5_PMSR56_SHIFT                 (6u)
+#define GPIO_PMSR5_PMSR57_SHIFT                 (7u)
+#define GPIO_PMSR5_PMSR58_SHIFT                 (8u)
+#define GPIO_PMSR5_PMSR59_SHIFT                 (9u)
+#define GPIO_PMSR5_PMSR510_SHIFT                (10u)
+#define GPIO_PMSR5_PMSR516_SHIFT                (16u)
+#define GPIO_PMSR5_PMSR517_SHIFT                (17u)
+#define GPIO_PMSR5_PMSR518_SHIFT                (18u)
+#define GPIO_PMSR5_PMSR519_SHIFT                (19u)
+#define GPIO_PMSR5_PMSR520_SHIFT                (20u)
+#define GPIO_PMSR5_PMSR521_SHIFT                (21u)
+#define GPIO_PMSR5_PMSR522_SHIFT                (22u)
+#define GPIO_PMSR5_PMSR523_SHIFT                (23u)
+#define GPIO_PMSR5_PMSR524_SHIFT                (24u)
+#define GPIO_PMSR5_PMSR525_SHIFT                (25u)
+#define GPIO_PMSR5_PMSR526_SHIFT                (26u)
+
+#define GPIO_PMCSR5_PMCSR50_SHIFT               (0u)
+#define GPIO_PMCSR5_PMCSR51_SHIFT               (1u)
+#define GPIO_PMCSR5_PMCSR52_SHIFT               (2u)
+#define GPIO_PMCSR5_PMCSR53_SHIFT               (3u)
+#define GPIO_PMCSR5_PMCSR54_SHIFT               (4u)
+#define GPIO_PMCSR5_PMCSR55_SHIFT               (5u)
+#define GPIO_PMCSR5_PMCSR56_SHIFT               (6u)
+#define GPIO_PMCSR5_PMCSR57_SHIFT               (7u)
+#define GPIO_PMCSR5_PMCSR58_SHIFT               (8u)
+#define GPIO_PMCSR5_PMCSR59_SHIFT               (9u)
+#define GPIO_PMCSR5_PMCSR510_SHIFT              (10u)
+#define GPIO_PMCSR5_PMCSR516_SHIFT              (16u)
+#define GPIO_PMCSR5_PMCSR517_SHIFT              (17u)
+#define GPIO_PMCSR5_PMCSR518_SHIFT              (18u)
+#define GPIO_PMCSR5_PMCSR519_SHIFT              (19u)
+#define GPIO_PMCSR5_PMCSR520_SHIFT              (20u)
+#define GPIO_PMCSR5_PMCSR521_SHIFT              (21u)
+#define GPIO_PMCSR5_PMCSR522_SHIFT              (22u)
+#define GPIO_PMCSR5_PMCSR523_SHIFT              (23u)
+#define GPIO_PMCSR5_PMCSR524_SHIFT              (24u)
+#define GPIO_PMCSR5_PMCSR525_SHIFT              (25u)
+#define GPIO_PMCSR5_PMCSR526_SHIFT              (26u)
+
+#define GPIO_PFCAE5_PFCAE50_SHIFT               (0u)
+#define GPIO_PFCAE5_PFCAE51_SHIFT               (1u)
+#define GPIO_PFCAE5_PFCAE52_SHIFT               (2u)
+#define GPIO_PFCAE5_PFCAE53_SHIFT               (3u)
+#define GPIO_PFCAE5_PFCAE54_SHIFT               (4u)
+#define GPIO_PFCAE5_PFCAE55_SHIFT               (5u)
+#define GPIO_PFCAE5_PFCAE56_SHIFT               (6u)
+#define GPIO_PFCAE5_PFCAE57_SHIFT               (7u)
+#define GPIO_PFCAE5_PFCAE58_SHIFT               (8u)
+#define GPIO_PFCAE5_PFCAE59_SHIFT               (9u)
+#define GPIO_PFCAE5_PFCAE510_SHIFT              (10u)
+
+#define GPIO_PIBC5_PIBC50_SHIFT                 (0u)
+#define GPIO_PIBC5_PIBC51_SHIFT                 (1u)
+#define GPIO_PIBC5_PIBC52_SHIFT                 (2u)
+#define GPIO_PIBC5_PIBC53_SHIFT                 (3u)
+#define GPIO_PIBC5_PIBC54_SHIFT                 (4u)
+#define GPIO_PIBC5_PIBC55_SHIFT                 (5u)
+#define GPIO_PIBC5_PIBC56_SHIFT                 (6u)
+#define GPIO_PIBC5_PIBC57_SHIFT                 (7u)
+#define GPIO_PIBC5_PIBC58_SHIFT                 (8u)
+#define GPIO_PIBC5_PIBC59_SHIFT                 (9u)
+#define GPIO_PIBC5_PIBC510_SHIFT                (10u)
+
+#define GPIO_PBDC5_PBDC50_SHIFT                 (0u)
+#define GPIO_PBDC5_PBDC51_SHIFT                 (1u)
+#define GPIO_PBDC5_PBDC52_SHIFT                 (2u)
+#define GPIO_PBDC5_PBDC53_SHIFT                 (3u)
+#define GPIO_PBDC5_PBDC54_SHIFT                 (4u)
+#define GPIO_PBDC5_PBDC55_SHIFT                 (5u)
+#define GPIO_PBDC5_PBDC56_SHIFT                 (6u)
+#define GPIO_PBDC5_PBDC57_SHIFT                 (7u)
+#define GPIO_PBDC5_PBDC58_SHIFT                 (8u)
+#define GPIO_PBDC5_PBDC59_SHIFT                 (9u)
+#define GPIO_PBDC5_PBDC510_SHIFT                (10u)
+
+#define GPIO_PIPC5_PIPC50_SHIFT                 (0u)
+#define GPIO_PIPC5_PIPC51_SHIFT                 (1u)
+#define GPIO_PIPC5_PIPC52_SHIFT                 (2u)
+#define GPIO_PIPC5_PIPC53_SHIFT                 (3u)
+#define GPIO_PIPC5_PIPC54_SHIFT                 (4u)
+#define GPIO_PIPC5_PIPC55_SHIFT                 (5u)
+#define GPIO_PIPC5_PIPC56_SHIFT                 (6u)
+#define GPIO_PIPC5_PIPC57_SHIFT                 (7u)
+#define GPIO_PIPC5_PIPC58_SHIFT                 (8u)
+#define GPIO_PIPC5_PIPC59_SHIFT                 (9u)
+#define GPIO_PIPC5_PIPC510_SHIFT                (10u)
+
+/* ---- P6 ---- */
+#define GPIO_P6_P60_SHIFT                       (0u)
+#define GPIO_P6_P61_SHIFT                       (1u)
+#define GPIO_P6_P62_SHIFT                       (2u)
+#define GPIO_P6_P63_SHIFT                       (3u)
+#define GPIO_P6_P64_SHIFT                       (4u)
+#define GPIO_P6_P65_SHIFT                       (5u)
+#define GPIO_P6_P66_SHIFT                       (6u)
+#define GPIO_P6_P67_SHIFT                       (7u)
+#define GPIO_P6_P68_SHIFT                       (8u)
+#define GPIO_P6_P69_SHIFT                       (9u)
+#define GPIO_P6_P610_SHIFT                      (10u)
+#define GPIO_P6_P611_SHIFT                      (11u)
+#define GPIO_P6_P612_SHIFT                      (12u)
+#define GPIO_P6_P613_SHIFT                      (13u)
+#define GPIO_P6_P614_SHIFT                      (14u)
+#define GPIO_P6_P615_SHIFT                      (15u)
+
+#define GPIO_PSR6_PSR60_SHIFT                   (0u)
+#define GPIO_PSR6_PSR61_SHIFT                   (1u)
+#define GPIO_PSR6_PSR62_SHIFT                   (2u)
+#define GPIO_PSR6_PSR63_SHIFT                   (3u)
+#define GPIO_PSR6_PSR64_SHIFT                   (4u)
+#define GPIO_PSR6_PSR65_SHIFT                   (5u)
+#define GPIO_PSR6_PSR66_SHIFT                   (6u)
+#define GPIO_PSR6_PSR67_SHIFT                   (7u)
+#define GPIO_PSR6_PSR68_SHIFT                   (8u)
+#define GPIO_PSR6_PSR69_SHIFT                   (9u)
+#define GPIO_PSR6_PSR610_SHIFT                  (10u)
+#define GPIO_PSR6_PSR611_SHIFT                  (11u)
+#define GPIO_PSR6_PSR612_SHIFT                  (12u)
+#define GPIO_PSR6_PSR613_SHIFT                  (13u)
+#define GPIO_PSR6_PSR614_SHIFT                  (14u)
+#define GPIO_PSR6_PSR615_SHIFT                  (15u)
+#define GPIO_PSR6_PSR616_SHIFT                  (16u)
+#define GPIO_PSR6_PSR617_SHIFT                  (17u)
+#define GPIO_PSR6_PSR618_SHIFT                  (18u)
+#define GPIO_PSR6_PSR619_SHIFT                  (19u)
+#define GPIO_PSR6_PSR620_SHIFT                  (20u)
+#define GPIO_PSR6_PSR621_SHIFT                  (21u)
+#define GPIO_PSR6_PSR622_SHIFT                  (22u)
+#define GPIO_PSR6_PSR623_SHIFT                  (23u)
+#define GPIO_PSR6_PSR624_SHIFT                  (24u)
+#define GPIO_PSR6_PSR625_SHIFT                  (25u)
+#define GPIO_PSR6_PSR626_SHIFT                  (26u)
+#define GPIO_PSR6_PSR627_SHIFT                  (27u)
+#define GPIO_PSR6_PSR628_SHIFT                  (28u)
+#define GPIO_PSR6_PSR629_SHIFT                  (29u)
+#define GPIO_PSR6_PSR630_SHIFT                  (30u)
+#define GPIO_PSR6_PSR631_SHIFT                  (31u)
+
+#define GPIO_PPR6_PPR60_SHIFT                   (0u)
+#define GPIO_PPR6_PPR61_SHIFT                   (1u)
+#define GPIO_PPR6_PPR62_SHIFT                   (2u)
+#define GPIO_PPR6_PPR63_SHIFT                   (3u)
+#define GPIO_PPR6_PPR64_SHIFT                   (4u)
+#define GPIO_PPR6_PPR65_SHIFT                   (5u)
+#define GPIO_PPR6_PPR66_SHIFT                   (6u)
+#define GPIO_PPR6_PPR67_SHIFT                   (7u)
+#define GPIO_PPR6_PPR68_SHIFT                   (8u)
+#define GPIO_PPR6_PPR69_SHIFT                   (9u)
+#define GPIO_PPR6_PPR610_SHIFT                  (10u)
+#define GPIO_PPR6_PPR611_SHIFT                  (11u)
+#define GPIO_PPR6_PPR612_SHIFT                  (12u)
+#define GPIO_PPR6_PPR613_SHIFT                  (13u)
+#define GPIO_PPR6_PPR614_SHIFT                  (14u)
+#define GPIO_PPR6_PPR615_SHIFT                  (15u)
+
+#define GPIO_PM6_PM60_SHIFT                     (0u)
+#define GPIO_PM6_PM61_SHIFT                     (1u)
+#define GPIO_PM6_PM62_SHIFT                     (2u)
+#define GPIO_PM6_PM63_SHIFT                     (3u)
+#define GPIO_PM6_PM64_SHIFT                     (4u)
+#define GPIO_PM6_PM65_SHIFT                     (5u)
+#define GPIO_PM6_PM66_SHIFT                     (6u)
+#define GPIO_PM6_PM67_SHIFT                     (7u)
+#define GPIO_PM6_PM68_SHIFT                     (8u)
+#define GPIO_PM6_PM69_SHIFT                     (9u)
+#define GPIO_PM6_PM610_SHIFT                    (10u)
+#define GPIO_PM6_PM611_SHIFT                    (11u)
+#define GPIO_PM6_PM612_SHIFT                    (12u)
+#define GPIO_PM6_PM613_SHIFT                    (13u)
+#define GPIO_PM6_PM614_SHIFT                    (14u)
+#define GPIO_PM6_PM615_SHIFT                    (15u)
+
+#define GPIO_PMC6_PMC60_SHIFT                   (0u)
+#define GPIO_PMC6_PMC61_SHIFT                   (1u)
+#define GPIO_PMC6_PMC62_SHIFT                   (2u)
+#define GPIO_PMC6_PMC63_SHIFT                   (3u)
+#define GPIO_PMC6_PMC64_SHIFT                   (4u)
+#define GPIO_PMC6_PMC65_SHIFT                   (5u)
+#define GPIO_PMC6_PMC66_SHIFT                   (6u)
+#define GPIO_PMC6_PMC67_SHIFT                   (7u)
+#define GPIO_PMC6_PMC68_SHIFT                   (8u)
+#define GPIO_PMC6_PMC69_SHIFT                   (9u)
+#define GPIO_PMC6_PMC610_SHIFT                  (10u)
+#define GPIO_PMC6_PMC611_SHIFT                  (11u)
+#define GPIO_PMC6_PMC612_SHIFT                  (12u)
+#define GPIO_PMC6_PMC613_SHIFT                  (13u)
+#define GPIO_PMC6_PMC614_SHIFT                  (14u)
+#define GPIO_PMC6_PMC615_SHIFT                  (15u)
+
+#define GPIO_PFC6_PFC60_SHIFT                   (0u)
+#define GPIO_PFC6_PFC61_SHIFT                   (1u)
+#define GPIO_PFC6_PFC62_SHIFT                   (2u)
+#define GPIO_PFC6_PFC63_SHIFT                   (3u)
+#define GPIO_PFC6_PFC64_SHIFT                   (4u)
+#define GPIO_PFC6_PFC65_SHIFT                   (5u)
+#define GPIO_PFC6_PFC66_SHIFT                   (6u)
+#define GPIO_PFC6_PFC67_SHIFT                   (7u)
+#define GPIO_PFC6_PFC68_SHIFT                   (8u)
+#define GPIO_PFC6_PFC69_SHIFT                   (9u)
+#define GPIO_PFC6_PFC610_SHIFT                  (10u)
+#define GPIO_PFC6_PFC611_SHIFT                  (11u)
+#define GPIO_PFC6_PFC612_SHIFT                  (12u)
+#define GPIO_PFC6_PFC613_SHIFT                  (13u)
+#define GPIO_PFC6_PFC614_SHIFT                  (14u)
+#define GPIO_PFC6_PFC615_SHIFT                  (15u)
+
+#define GPIO_PFCE6_PFCE60_SHIFT                 (0u)
+#define GPIO_PFCE6_PFCE61_SHIFT                 (1u)
+#define GPIO_PFCE6_PFCE62_SHIFT                 (2u)
+#define GPIO_PFCE6_PFCE63_SHIFT                 (3u)
+#define GPIO_PFCE6_PFCE64_SHIFT                 (4u)
+#define GPIO_PFCE6_PFCE65_SHIFT                 (5u)
+#define GPIO_PFCE6_PFCE66_SHIFT                 (6u)
+#define GPIO_PFCE6_PFCE67_SHIFT                 (7u)
+#define GPIO_PFCE6_PFCE68_SHIFT                 (8u)
+#define GPIO_PFCE6_PFCE69_SHIFT                 (9u)
+#define GPIO_PFCE6_PFCE610_SHIFT                (10u)
+#define GPIO_PFCE6_PFCE611_SHIFT                (11u)
+#define GPIO_PFCE6_PFCE612_SHIFT                (12u)
+#define GPIO_PFCE6_PFCE613_SHIFT                (13u)
+#define GPIO_PFCE6_PFCE614_SHIFT                (14u)
+#define GPIO_PFCE6_PFCE615_SHIFT                (15u)
+
+#define GPIO_PNOT6_PNOT60_SHIFT                 (0u)
+#define GPIO_PNOT6_PNOT61_SHIFT                 (1u)
+#define GPIO_PNOT6_PNOT62_SHIFT                 (2u)
+#define GPIO_PNOT6_PNOT63_SHIFT                 (3u)
+#define GPIO_PNOT6_PNOT64_SHIFT                 (4u)
+#define GPIO_PNOT6_PNOT65_SHIFT                 (5u)
+#define GPIO_PNOT6_PNOT66_SHIFT                 (6u)
+#define GPIO_PNOT6_PNOT67_SHIFT                 (7u)
+#define GPIO_PNOT6_PNOT68_SHIFT                 (8u)
+#define GPIO_PNOT6_PNOT69_SHIFT                 (9u)
+#define GPIO_PNOT6_PNOT610_SHIFT                (10u)
+#define GPIO_PNOT6_PNOT611_SHIFT                (11u)
+#define GPIO_PNOT6_PNOT612_SHIFT                (12u)
+#define GPIO_PNOT6_PNOT613_SHIFT                (13u)
+#define GPIO_PNOT6_PNOT614_SHIFT                (14u)
+#define GPIO_PNOT6_PNOT615_SHIFT                (15u)
+
+#define GPIO_PMSR6_PMSR60_SHIFT                 (0u)
+#define GPIO_PMSR6_PMSR61_SHIFT                 (1u)
+#define GPIO_PMSR6_PMSR62_SHIFT                 (2u)
+#define GPIO_PMSR6_PMSR63_SHIFT                 (3u)
+#define GPIO_PMSR6_PMSR64_SHIFT                 (4u)
+#define GPIO_PMSR6_PMSR65_SHIFT                 (5u)
+#define GPIO_PMSR6_PMSR66_SHIFT                 (6u)
+#define GPIO_PMSR6_PMSR67_SHIFT                 (7u)
+#define GPIO_PMSR6_PMSR68_SHIFT                 (8u)
+#define GPIO_PMSR6_PMSR69_SHIFT                 (9u)
+#define GPIO_PMSR6_PMSR610_SHIFT                (10u)
+#define GPIO_PMSR6_PMSR611_SHIFT                (11u)
+#define GPIO_PMSR6_PMSR612_SHIFT                (12u)
+#define GPIO_PMSR6_PMSR613_SHIFT                (13u)
+#define GPIO_PMSR6_PMSR614_SHIFT                (14u)
+#define GPIO_PMSR6_PMSR615_SHIFT                (15u)
+#define GPIO_PMSR6_PMSR616_SHIFT                (16u)
+#define GPIO_PMSR6_PMSR617_SHIFT                (17u)
+#define GPIO_PMSR6_PMSR618_SHIFT                (18u)
+#define GPIO_PMSR6_PMSR619_SHIFT                (19u)
+#define GPIO_PMSR6_PMSR620_SHIFT                (20u)
+#define GPIO_PMSR6_PMSR621_SHIFT                (21u)
+#define GPIO_PMSR6_PMSR622_SHIFT                (22u)
+#define GPIO_PMSR6_PMSR623_SHIFT                (23u)
+#define GPIO_PMSR6_PMSR624_SHIFT                (24u)
+#define GPIO_PMSR6_PMSR625_SHIFT                (25u)
+#define GPIO_PMSR6_PMSR626_SHIFT                (26u)
+#define GPIO_PMSR6_PMSR627_SHIFT                (27u)
+#define GPIO_PMSR6_PMSR628_SHIFT                (28u)
+#define GPIO_PMSR6_PMSR629_SHIFT                (29u)
+#define GPIO_PMSR6_PMSR630_SHIFT                (30u)
+#define GPIO_PMSR6_PMSR631_SHIFT                (31u)
+
+#define GPIO_PMCSR6_PMCSR60_SHIFT               (0u)
+#define GPIO_PMCSR6_PMCSR61_SHIFT               (1u)
+#define GPIO_PMCSR6_PMCSR62_SHIFT               (2u)
+#define GPIO_PMCSR6_PMCSR63_SHIFT               (3u)
+#define GPIO_PMCSR6_PMCSR64_SHIFT               (4u)
+#define GPIO_PMCSR6_PMCSR65_SHIFT               (5u)
+#define GPIO_PMCSR6_PMCSR66_SHIFT               (6u)
+#define GPIO_PMCSR6_PMCSR67_SHIFT               (7u)
+#define GPIO_PMCSR6_PMCSR68_SHIFT               (8u)
+#define GPIO_PMCSR6_PMCSR69_SHIFT               (9u)
+#define GPIO_PMCSR6_PMCSR610_SHIFT              (10u)
+#define GPIO_PMCSR6_PMCSR611_SHIFT              (11u)
+#define GPIO_PMCSR6_PMCSR612_SHIFT              (12u)
+#define GPIO_PMCSR6_PMCSR613_SHIFT              (13u)
+#define GPIO_PMCSR6_PMCSR614_SHIFT              (14u)
+#define GPIO_PMCSR6_PMCSR615_SHIFT              (15u)
+#define GPIO_PMCSR6_PMCSR616_SHIFT              (16u)
+#define GPIO_PMCSR6_PMCSR617_SHIFT              (17u)
+#define GPIO_PMCSR6_PMCSR618_SHIFT              (18u)
+#define GPIO_PMCSR6_PMCSR619_SHIFT              (19u)
+#define GPIO_PMCSR6_PMCSR620_SHIFT              (20u)
+#define GPIO_PMCSR6_PMCSR621_SHIFT              (21u)
+#define GPIO_PMCSR6_PMCSR622_SHIFT              (22u)
+#define GPIO_PMCSR6_PMCSR623_SHIFT              (23u)
+#define GPIO_PMCSR6_PMCSR624_SHIFT              (24u)
+#define GPIO_PMCSR6_PMCSR625_SHIFT              (25u)
+#define GPIO_PMCSR6_PMCSR626_SHIFT              (26u)
+#define GPIO_PMCSR6_PMCSR627_SHIFT              (27u)
+#define GPIO_PMCSR6_PMCSR628_SHIFT              (28u)
+#define GPIO_PMCSR6_PMCSR629_SHIFT              (29u)
+#define GPIO_PMCSR6_PMCSR630_SHIFT              (30u)
+#define GPIO_PMCSR6_PMCSR631_SHIFT              (31u)
+
+#define GPIO_PFCAE6_PFCAE60_SHIFT               (0u)
+#define GPIO_PFCAE6_PFCAE61_SHIFT               (1u)
+#define GPIO_PFCAE6_PFCAE62_SHIFT               (2u)
+#define GPIO_PFCAE6_PFCAE63_SHIFT               (3u)
+#define GPIO_PFCAE6_PFCAE64_SHIFT               (4u)
+#define GPIO_PFCAE6_PFCAE65_SHIFT               (5u)
+#define GPIO_PFCAE6_PFCAE66_SHIFT               (6u)
+#define GPIO_PFCAE6_PFCAE67_SHIFT               (7u)
+#define GPIO_PFCAE6_PFCAE68_SHIFT               (8u)
+#define GPIO_PFCAE6_PFCAE69_SHIFT               (9u)
+#define GPIO_PFCAE6_PFCAE610_SHIFT              (10u)
+#define GPIO_PFCAE6_PFCAE611_SHIFT              (11u)
+#define GPIO_PFCAE6_PFCAE612_SHIFT              (12u)
+#define GPIO_PFCAE6_PFCAE613_SHIFT              (13u)
+#define GPIO_PFCAE6_PFCAE614_SHIFT              (14u)
+#define GPIO_PFCAE6_PFCAE615_SHIFT              (15u)
+
+#define GPIO_PIBC6_PIBC60_SHIFT                 (0u)
+#define GPIO_PIBC6_PIBC61_SHIFT                 (1u)
+#define GPIO_PIBC6_PIBC62_SHIFT                 (2u)
+#define GPIO_PIBC6_PIBC63_SHIFT                 (3u)
+#define GPIO_PIBC6_PIBC64_SHIFT                 (4u)
+#define GPIO_PIBC6_PIBC65_SHIFT                 (5u)
+#define GPIO_PIBC6_PIBC66_SHIFT                 (6u)
+#define GPIO_PIBC6_PIBC67_SHIFT                 (7u)
+#define GPIO_PIBC6_PIBC68_SHIFT                 (8u)
+#define GPIO_PIBC6_PIBC69_SHIFT                 (9u)
+#define GPIO_PIBC6_PIBC610_SHIFT                (10u)
+#define GPIO_PIBC6_PIBC611_SHIFT                (11u)
+#define GPIO_PIBC6_PIBC612_SHIFT                (12u)
+#define GPIO_PIBC6_PIBC613_SHIFT                (13u)
+#define GPIO_PIBC6_PIBC614_SHIFT                (14u)
+#define GPIO_PIBC6_PIBC615_SHIFT                (15u)
+
+#define GPIO_PBDC6_PBDC60_SHIFT                 (0u)
+#define GPIO_PBDC6_PBDC61_SHIFT                 (1u)
+#define GPIO_PBDC6_PBDC62_SHIFT                 (2u)
+#define GPIO_PBDC6_PBDC63_SHIFT                 (3u)
+#define GPIO_PBDC6_PBDC64_SHIFT                 (4u)
+#define GPIO_PBDC6_PBDC65_SHIFT                 (5u)
+#define GPIO_PBDC6_PBDC66_SHIFT                 (6u)
+#define GPIO_PBDC6_PBDC67_SHIFT                 (7u)
+#define GPIO_PBDC6_PBDC68_SHIFT                 (8u)
+#define GPIO_PBDC6_PBDC69_SHIFT                 (9u)
+#define GPIO_PBDC6_PBDC610_SHIFT                (10u)
+#define GPIO_PBDC6_PBDC611_SHIFT                (11u)
+#define GPIO_PBDC6_PBDC612_SHIFT                (12u)
+#define GPIO_PBDC6_PBDC613_SHIFT                (13u)
+#define GPIO_PBDC6_PBDC614_SHIFT                (14u)
+#define GPIO_PBDC6_PBDC615_SHIFT                (15u)
+
+#define GPIO_PIPC6_PIPC60_SHIFT                 (0u)
+#define GPIO_PIPC6_PIPC61_SHIFT                 (1u)
+#define GPIO_PIPC6_PIPC62_SHIFT                 (2u)
+#define GPIO_PIPC6_PIPC63_SHIFT                 (3u)
+#define GPIO_PIPC6_PIPC64_SHIFT                 (4u)
+#define GPIO_PIPC6_PIPC65_SHIFT                 (5u)
+#define GPIO_PIPC6_PIPC66_SHIFT                 (6u)
+#define GPIO_PIPC6_PIPC67_SHIFT                 (7u)
+#define GPIO_PIPC6_PIPC68_SHIFT                 (8u)
+#define GPIO_PIPC6_PIPC69_SHIFT                 (9u)
+#define GPIO_PIPC6_PIPC610_SHIFT                (10u)
+#define GPIO_PIPC6_PIPC611_SHIFT                (11u)
+#define GPIO_PIPC6_PIPC612_SHIFT                (12u)
+#define GPIO_PIPC6_PIPC613_SHIFT                (13u)
+#define GPIO_PIPC6_PIPC614_SHIFT                (14u)
+#define GPIO_PIPC6_PIPC615_SHIFT                (15u)
+
+/* ---- P7 ---- */
+#define GPIO_P7_P70_SHIFT                       (0u)
+#define GPIO_P7_P71_SHIFT                       (1u)
+#define GPIO_P7_P72_SHIFT                       (2u)
+#define GPIO_P7_P73_SHIFT                       (3u)
+#define GPIO_P7_P74_SHIFT                       (4u)
+#define GPIO_P7_P75_SHIFT                       (5u)
+#define GPIO_P7_P76_SHIFT                       (6u)
+#define GPIO_P7_P77_SHIFT                       (7u)
+#define GPIO_P7_P78_SHIFT                       (8u)
+#define GPIO_P7_P79_SHIFT                       (9u)
+#define GPIO_P7_P710_SHIFT                      (10u)
+#define GPIO_P7_P711_SHIFT                      (11u)
+#define GPIO_P7_P712_SHIFT                      (12u)
+#define GPIO_P7_P713_SHIFT                      (13u)
+#define GPIO_P7_P714_SHIFT                      (14u)
+#define GPIO_P7_P715_SHIFT                      (15u)
+
+#define GPIO_PSR7_PSR70_SHIFT                   (0u)
+#define GPIO_PSR7_PSR71_SHIFT                   (1u)
+#define GPIO_PSR7_PSR72_SHIFT                   (2u)
+#define GPIO_PSR7_PSR73_SHIFT                   (3u)
+#define GPIO_PSR7_PSR74_SHIFT                   (4u)
+#define GPIO_PSR7_PSR75_SHIFT                   (5u)
+#define GPIO_PSR7_PSR76_SHIFT                   (6u)
+#define GPIO_PSR7_PSR77_SHIFT                   (7u)
+#define GPIO_PSR7_PSR78_SHIFT                   (8u)
+#define GPIO_PSR7_PSR79_SHIFT                   (9u)
+#define GPIO_PSR7_PSR710_SHIFT                  (10u)
+#define GPIO_PSR7_PSR711_SHIFT                  (11u)
+#define GPIO_PSR7_PSR712_SHIFT                  (12u)
+#define GPIO_PSR7_PSR713_SHIFT                  (13u)
+#define GPIO_PSR7_PSR714_SHIFT                  (14u)
+#define GPIO_PSR7_PSR715_SHIFT                  (15u)
+#define GPIO_PSR7_PSR716_SHIFT                  (16u)
+#define GPIO_PSR7_PSR717_SHIFT                  (17u)
+#define GPIO_PSR7_PSR718_SHIFT                  (18u)
+#define GPIO_PSR7_PSR719_SHIFT                  (19u)
+#define GPIO_PSR7_PSR720_SHIFT                  (20u)
+#define GPIO_PSR7_PSR721_SHIFT                  (21u)
+#define GPIO_PSR7_PSR722_SHIFT                  (22u)
+#define GPIO_PSR7_PSR723_SHIFT                  (23u)
+#define GPIO_PSR7_PSR724_SHIFT                  (24u)
+#define GPIO_PSR7_PSR725_SHIFT                  (25u)
+#define GPIO_PSR7_PSR726_SHIFT                  (26u)
+#define GPIO_PSR7_PSR727_SHIFT                  (27u)
+#define GPIO_PSR7_PSR728_SHIFT                  (28u)
+#define GPIO_PSR7_PSR729_SHIFT                  (29u)
+#define GPIO_PSR7_PSR730_SHIFT                  (30u)
+#define GPIO_PSR7_PSR731_SHIFT                  (31u)
+
+#define GPIO_PPR7_PPR70_SHIFT                   (0u)
+#define GPIO_PPR7_PPR71_SHIFT                   (1u)
+#define GPIO_PPR7_PPR72_SHIFT                   (2u)
+#define GPIO_PPR7_PPR73_SHIFT                   (3u)
+#define GPIO_PPR7_PPR74_SHIFT                   (4u)
+#define GPIO_PPR7_PPR75_SHIFT                   (5u)
+#define GPIO_PPR7_PPR76_SHIFT                   (6u)
+#define GPIO_PPR7_PPR77_SHIFT                   (7u)
+#define GPIO_PPR7_PPR78_SHIFT                   (8u)
+#define GPIO_PPR7_PPR79_SHIFT                   (9u)
+#define GPIO_PPR7_PPR710_SHIFT                  (10u)
+#define GPIO_PPR7_PPR711_SHIFT                  (11u)
+#define GPIO_PPR7_PPR712_SHIFT                  (12u)
+#define GPIO_PPR7_PPR713_SHIFT                  (13u)
+#define GPIO_PPR7_PPR714_SHIFT                  (14u)
+#define GPIO_PPR7_PPR715_SHIFT                  (15u)
+
+#define GPIO_PM7_PM70_SHIFT                     (0u)
+#define GPIO_PM7_PM71_SHIFT                     (1u)
+#define GPIO_PM7_PM72_SHIFT                     (2u)
+#define GPIO_PM7_PM73_SHIFT                     (3u)
+#define GPIO_PM7_PM74_SHIFT                     (4u)
+#define GPIO_PM7_PM75_SHIFT                     (5u)
+#define GPIO_PM7_PM76_SHIFT                     (6u)
+#define GPIO_PM7_PM77_SHIFT                     (7u)
+#define GPIO_PM7_PM78_SHIFT                     (8u)
+#define GPIO_PM7_PM79_SHIFT                     (9u)
+#define GPIO_PM7_PM710_SHIFT                    (10u)
+#define GPIO_PM7_PM711_SHIFT                    (11u)
+#define GPIO_PM7_PM712_SHIFT                    (12u)
+#define GPIO_PM7_PM713_SHIFT                    (13u)
+#define GPIO_PM7_PM714_SHIFT                    (14u)
+#define GPIO_PM7_PM715_SHIFT                    (15u)
+
+#define GPIO_PMC7_PMC70_SHIFT                   (0u)
+#define GPIO_PMC7_PMC71_SHIFT                   (1u)
+#define GPIO_PMC7_PMC72_SHIFT                   (2u)
+#define GPIO_PMC7_PMC73_SHIFT                   (3u)
+#define GPIO_PMC7_PMC74_SHIFT                   (4u)
+#define GPIO_PMC7_PMC75_SHIFT                   (5u)
+#define GPIO_PMC7_PMC76_SHIFT                   (6u)
+#define GPIO_PMC7_PMC77_SHIFT                   (7u)
+#define GPIO_PMC7_PMC78_SHIFT                   (8u)
+#define GPIO_PMC7_PMC79_SHIFT                   (9u)
+#define GPIO_PMC7_PMC710_SHIFT                  (10u)
+#define GPIO_PMC7_PMC711_SHIFT                  (11u)
+#define GPIO_PMC7_PMC712_SHIFT                  (12u)
+#define GPIO_PMC7_PMC713_SHIFT                  (13u)
+#define GPIO_PMC7_PMC714_SHIFT                  (14u)
+#define GPIO_PMC7_PMC715_SHIFT                  (15u)
+
+#define GPIO_PFC7_PFC70_SHIFT                   (0u)
+#define GPIO_PFC7_PFC71_SHIFT                   (1u)
+#define GPIO_PFC7_PFC72_SHIFT                   (2u)
+#define GPIO_PFC7_PFC73_SHIFT                   (3u)
+#define GPIO_PFC7_PFC74_SHIFT                   (4u)
+#define GPIO_PFC7_PFC75_SHIFT                   (5u)
+#define GPIO_PFC7_PFC76_SHIFT                   (6u)
+#define GPIO_PFC7_PFC77_SHIFT                   (7u)
+#define GPIO_PFC7_PFC78_SHIFT                   (8u)
+#define GPIO_PFC7_PFC79_SHIFT                   (9u)
+#define GPIO_PFC7_PFC710_SHIFT                  (10u)
+#define GPIO_PFC7_PFC711_SHIFT                  (11u)
+#define GPIO_PFC7_PFC712_SHIFT                  (12u)
+#define GPIO_PFC7_PFC713_SHIFT                  (13u)
+#define GPIO_PFC7_PFC714_SHIFT                  (14u)
+#define GPIO_PFC7_PFC715_SHIFT                  (15u)
+
+#define GPIO_PFCE7_PFCE70_SHIFT                 (0u)
+#define GPIO_PFCE7_PFCE71_SHIFT                 (1u)
+#define GPIO_PFCE7_PFCE72_SHIFT                 (2u)
+#define GPIO_PFCE7_PFCE73_SHIFT                 (3u)
+#define GPIO_PFCE7_PFCE74_SHIFT                 (4u)
+#define GPIO_PFCE7_PFCE75_SHIFT                 (5u)
+#define GPIO_PFCE7_PFCE76_SHIFT                 (6u)
+#define GPIO_PFCE7_PFCE77_SHIFT                 (7u)
+#define GPIO_PFCE7_PFCE78_SHIFT                 (8u)
+#define GPIO_PFCE7_PFCE79_SHIFT                 (9u)
+#define GPIO_PFCE7_PFCE710_SHIFT                (10u)
+#define GPIO_PFCE7_PFCE711_SHIFT                (11u)
+#define GPIO_PFCE7_PFCE712_SHIFT                (12u)
+#define GPIO_PFCE7_PFCE713_SHIFT                (13u)
+#define GPIO_PFCE7_PFCE714_SHIFT                (14u)
+#define GPIO_PFCE7_PFCE715_SHIFT                (15u)
+
+#define GPIO_PNOT7_PNOT70_SHIFT                 (0u)
+#define GPIO_PNOT7_PNOT71_SHIFT                 (1u)
+#define GPIO_PNOT7_PNOT72_SHIFT                 (2u)
+#define GPIO_PNOT7_PNOT73_SHIFT                 (3u)
+#define GPIO_PNOT7_PNOT74_SHIFT                 (4u)
+#define GPIO_PNOT7_PNOT75_SHIFT                 (5u)
+#define GPIO_PNOT7_PNOT76_SHIFT                 (6u)
+#define GPIO_PNOT7_PNOT77_SHIFT                 (7u)
+#define GPIO_PNOT7_PNOT78_SHIFT                 (8u)
+#define GPIO_PNOT7_PNOT79_SHIFT                 (9u)
+#define GPIO_PNOT7_PNOT710_SHIFT                (10u)
+#define GPIO_PNOT7_PNOT711_SHIFT                (11u)
+#define GPIO_PNOT7_PNOT712_SHIFT                (12u)
+#define GPIO_PNOT7_PNOT713_SHIFT                (13u)
+#define GPIO_PNOT7_PNOT714_SHIFT                (14u)
+#define GPIO_PNOT7_PNOT715_SHIFT                (15u)
+
+#define GPIO_PMSR7_PMSR70_SHIFT                 (0u)
+#define GPIO_PMSR7_PMSR71_SHIFT                 (1u)
+#define GPIO_PMSR7_PMSR72_SHIFT                 (2u)
+#define GPIO_PMSR7_PMSR73_SHIFT                 (3u)
+#define GPIO_PMSR7_PMSR74_SHIFT                 (4u)
+#define GPIO_PMSR7_PMSR75_SHIFT                 (5u)
+#define GPIO_PMSR7_PMSR76_SHIFT                 (6u)
+#define GPIO_PMSR7_PMSR77_SHIFT                 (7u)
+#define GPIO_PMSR7_PMSR78_SHIFT                 (8u)
+#define GPIO_PMSR7_PMSR79_SHIFT                 (9u)
+#define GPIO_PMSR7_PMSR710_SHIFT                (10u)
+#define GPIO_PMSR7_PMSR711_SHIFT                (11u)
+#define GPIO_PMSR7_PMSR712_SHIFT                (12u)
+#define GPIO_PMSR7_PMSR713_SHIFT                (13u)
+#define GPIO_PMSR7_PMSR714_SHIFT                (14u)
+#define GPIO_PMSR7_PMSR715_SHIFT                (15u)
+#define GPIO_PMSR7_PMSR716_SHIFT                (16u)
+#define GPIO_PMSR7_PMSR717_SHIFT                (17u)
+#define GPIO_PMSR7_PMSR718_SHIFT                (18u)
+#define GPIO_PMSR7_PMSR719_SHIFT                (19u)
+#define GPIO_PMSR7_PMSR720_SHIFT                (20u)
+#define GPIO_PMSR7_PMSR721_SHIFT                (21u)
+#define GPIO_PMSR7_PMSR722_SHIFT                (22u)
+#define GPIO_PMSR7_PMSR723_SHIFT                (23u)
+#define GPIO_PMSR7_PMSR724_SHIFT                (24u)
+#define GPIO_PMSR7_PMSR725_SHIFT                (25u)
+#define GPIO_PMSR7_PMSR726_SHIFT                (26u)
+#define GPIO_PMSR7_PMSR727_SHIFT                (27u)
+#define GPIO_PMSR7_PMSR728_SHIFT                (28u)
+#define GPIO_PMSR7_PMSR729_SHIFT                (29u)
+#define GPIO_PMSR7_PMSR730_SHIFT                (30u)
+#define GPIO_PMSR7_PMSR731_SHIFT                (31u)
+
+#define GPIO_PMCSR7_PMCSR70_SHIFT               (0u)
+#define GPIO_PMCSR7_PMCSR71_SHIFT               (1u)
+#define GPIO_PMCSR7_PMCSR72_SHIFT               (2u)
+#define GPIO_PMCSR7_PMCSR73_SHIFT               (3u)
+#define GPIO_PMCSR7_PMCSR74_SHIFT               (4u)
+#define GPIO_PMCSR7_PMCSR75_SHIFT               (5u)
+#define GPIO_PMCSR7_PMCSR76_SHIFT               (6u)
+#define GPIO_PMCSR7_PMCSR77_SHIFT               (7u)
+#define GPIO_PMCSR7_PMCSR78_SHIFT               (8u)
+#define GPIO_PMCSR7_PMCSR79_SHIFT               (9u)
+#define GPIO_PMCSR7_PMCSR710_SHIFT              (10u)
+#define GPIO_PMCSR7_PMCSR711_SHIFT              (11u)
+#define GPIO_PMCSR7_PMCSR712_SHIFT              (12u)
+#define GPIO_PMCSR7_PMCSR713_SHIFT              (13u)
+#define GPIO_PMCSR7_PMCSR714_SHIFT              (14u)
+#define GPIO_PMCSR7_PMCSR715_SHIFT              (15u)
+#define GPIO_PMCSR7_PMCSR716_SHIFT              (16u)
+#define GPIO_PMCSR7_PMCSR717_SHIFT              (17u)
+#define GPIO_PMCSR7_PMCSR718_SHIFT              (18u)
+#define GPIO_PMCSR7_PMCSR719_SHIFT              (19u)
+#define GPIO_PMCSR7_PMCSR720_SHIFT              (20u)
+#define GPIO_PMCSR7_PMCSR721_SHIFT              (21u)
+#define GPIO_PMCSR7_PMCSR722_SHIFT              (22u)
+#define GPIO_PMCSR7_PMCSR723_SHIFT              (23u)
+#define GPIO_PMCSR7_PMCSR724_SHIFT              (24u)
+#define GPIO_PMCSR7_PMCSR725_SHIFT              (25u)
+#define GPIO_PMCSR7_PMCSR726_SHIFT              (26u)
+#define GPIO_PMCSR7_PMCSR727_SHIFT              (27u)
+#define GPIO_PMCSR7_PMCSR728_SHIFT              (28u)
+#define GPIO_PMCSR7_PMCSR729_SHIFT              (29u)
+#define GPIO_PMCSR7_PMCSR730_SHIFT              (30u)
+#define GPIO_PMCSR7_PMCSR731_SHIFT              (31u)
+
+#define GPIO_PFCAE7_PFCAE70_SHIFT               (0u)
+#define GPIO_PFCAE7_PFCAE71_SHIFT               (1u)
+#define GPIO_PFCAE7_PFCAE72_SHIFT               (2u)
+#define GPIO_PFCAE7_PFCAE73_SHIFT               (3u)
+#define GPIO_PFCAE7_PFCAE74_SHIFT               (4u)
+#define GPIO_PFCAE7_PFCAE75_SHIFT               (5u)
+#define GPIO_PFCAE7_PFCAE76_SHIFT               (6u)
+#define GPIO_PFCAE7_PFCAE77_SHIFT               (7u)
+#define GPIO_PFCAE7_PFCAE78_SHIFT               (8u)
+#define GPIO_PFCAE7_PFCAE79_SHIFT               (9u)
+#define GPIO_PFCAE7_PFCAE710_SHIFT              (10u)
+#define GPIO_PFCAE7_PFCAE711_SHIFT              (11u)
+#define GPIO_PFCAE7_PFCAE712_SHIFT              (12u)
+#define GPIO_PFCAE7_PFCAE713_SHIFT              (13u)
+#define GPIO_PFCAE7_PFCAE714_SHIFT              (14u)
+#define GPIO_PFCAE7_PFCAE715_SHIFT              (15u)
+
+#define GPIO_PIBC7_PIBC70_SHIFT                 (0u)
+#define GPIO_PIBC7_PIBC71_SHIFT                 (1u)
+#define GPIO_PIBC7_PIBC72_SHIFT                 (2u)
+#define GPIO_PIBC7_PIBC73_SHIFT                 (3u)
+#define GPIO_PIBC7_PIBC74_SHIFT                 (4u)
+#define GPIO_PIBC7_PIBC75_SHIFT                 (5u)
+#define GPIO_PIBC7_PIBC76_SHIFT                 (6u)
+#define GPIO_PIBC7_PIBC77_SHIFT                 (7u)
+#define GPIO_PIBC7_PIBC78_SHIFT                 (8u)
+#define GPIO_PIBC7_PIBC79_SHIFT                 (9u)
+#define GPIO_PIBC7_PIBC710_SHIFT                (10u)
+#define GPIO_PIBC7_PIBC711_SHIFT                (11u)
+#define GPIO_PIBC7_PIBC712_SHIFT                (12u)
+#define GPIO_PIBC7_PIBC713_SHIFT                (13u)
+#define GPIO_PIBC7_PIBC714_SHIFT                (14u)
+#define GPIO_PIBC7_PIBC715_SHIFT                (15u)
+
+#define GPIO_PBDC7_PBDC70_SHIFT                 (0u)
+#define GPIO_PBDC7_PBDC71_SHIFT                 (1u)
+#define GPIO_PBDC7_PBDC72_SHIFT                 (2u)
+#define GPIO_PBDC7_PBDC73_SHIFT                 (3u)
+#define GPIO_PBDC7_PBDC74_SHIFT                 (4u)
+#define GPIO_PBDC7_PBDC75_SHIFT                 (5u)
+#define GPIO_PBDC7_PBDC76_SHIFT                 (6u)
+#define GPIO_PBDC7_PBDC77_SHIFT                 (7u)
+#define GPIO_PBDC7_PBDC78_SHIFT                 (8u)
+#define GPIO_PBDC7_PBDC79_SHIFT                 (9u)
+#define GPIO_PBDC7_PBDC710_SHIFT                (10u)
+#define GPIO_PBDC7_PBDC711_SHIFT                (11u)
+#define GPIO_PBDC7_PBDC712_SHIFT                (12u)
+#define GPIO_PBDC7_PBDC713_SHIFT                (13u)
+#define GPIO_PBDC7_PBDC714_SHIFT                (14u)
+#define GPIO_PBDC7_PBDC715_SHIFT                (15u)
+
+#define GPIO_PIPC7_PIPC70_SHIFT                 (0u)
+#define GPIO_PIPC7_PIPC71_SHIFT                 (1u)
+#define GPIO_PIPC7_PIPC72_SHIFT                 (2u)
+#define GPIO_PIPC7_PIPC73_SHIFT                 (3u)
+#define GPIO_PIPC7_PIPC74_SHIFT                 (4u)
+#define GPIO_PIPC7_PIPC75_SHIFT                 (5u)
+#define GPIO_PIPC7_PIPC76_SHIFT                 (6u)
+#define GPIO_PIPC7_PIPC77_SHIFT                 (7u)
+#define GPIO_PIPC7_PIPC78_SHIFT                 (8u)
+#define GPIO_PIPC7_PIPC79_SHIFT                 (9u)
+#define GPIO_PIPC7_PIPC710_SHIFT                (10u)
+#define GPIO_PIPC7_PIPC711_SHIFT                (11u)
+#define GPIO_PIPC7_PIPC712_SHIFT                (12u)
+#define GPIO_PIPC7_PIPC713_SHIFT                (13u)
+#define GPIO_PIPC7_PIPC714_SHIFT                (14u)
+#define GPIO_PIPC7_PIPC715_SHIFT                (15u)
+
+/* ---- P8 ---- */
+#define GPIO_P8_P80_SHIFT                       (0u)
+#define GPIO_P8_P81_SHIFT                       (1u)
+#define GPIO_P8_P82_SHIFT                       (2u)
+#define GPIO_P8_P83_SHIFT                       (3u)
+#define GPIO_P8_P84_SHIFT                       (4u)
+#define GPIO_P8_P85_SHIFT                       (5u)
+#define GPIO_P8_P86_SHIFT                       (6u)
+#define GPIO_P8_P87_SHIFT                       (7u)
+#define GPIO_P8_P88_SHIFT                       (8u)
+#define GPIO_P8_P89_SHIFT                       (9u)
+#define GPIO_P8_P810_SHIFT                      (10u)
+#define GPIO_P8_P811_SHIFT                      (11u)
+#define GPIO_P8_P812_SHIFT                      (12u)
+#define GPIO_P8_P813_SHIFT                      (13u)
+#define GPIO_P8_P814_SHIFT                      (14u)
+#define GPIO_P8_P815_SHIFT                      (15u)
+
+#define GPIO_PSR8_PSR80_SHIFT                   (0u)
+#define GPIO_PSR8_PSR81_SHIFT                   (1u)
+#define GPIO_PSR8_PSR82_SHIFT                   (2u)
+#define GPIO_PSR8_PSR83_SHIFT                   (3u)
+#define GPIO_PSR8_PSR84_SHIFT                   (4u)
+#define GPIO_PSR8_PSR85_SHIFT                   (5u)
+#define GPIO_PSR8_PSR86_SHIFT                   (6u)
+#define GPIO_PSR8_PSR87_SHIFT                   (7u)
+#define GPIO_PSR8_PSR88_SHIFT                   (8u)
+#define GPIO_PSR8_PSR89_SHIFT                   (9u)
+#define GPIO_PSR8_PSR810_SHIFT                  (10u)
+#define GPIO_PSR8_PSR811_SHIFT                  (11u)
+#define GPIO_PSR8_PSR812_SHIFT                  (12u)
+#define GPIO_PSR8_PSR813_SHIFT                  (13u)
+#define GPIO_PSR8_PSR814_SHIFT                  (14u)
+#define GPIO_PSR8_PSR815_SHIFT                  (15u)
+#define GPIO_PSR8_PSR816_SHIFT                  (16u)
+#define GPIO_PSR8_PSR817_SHIFT                  (17u)
+#define GPIO_PSR8_PSR818_SHIFT                  (18u)
+#define GPIO_PSR8_PSR819_SHIFT                  (19u)
+#define GPIO_PSR8_PSR820_SHIFT                  (20u)
+#define GPIO_PSR8_PSR821_SHIFT                  (21u)
+#define GPIO_PSR8_PSR822_SHIFT                  (22u)
+#define GPIO_PSR8_PSR823_SHIFT                  (23u)
+#define GPIO_PSR8_PSR824_SHIFT                  (24u)
+#define GPIO_PSR8_PSR825_SHIFT                  (25u)
+#define GPIO_PSR8_PSR826_SHIFT                  (26u)
+#define GPIO_PSR8_PSR827_SHIFT                  (27u)
+#define GPIO_PSR8_PSR828_SHIFT                  (28u)
+#define GPIO_PSR8_PSR829_SHIFT                  (29u)
+#define GPIO_PSR8_PSR830_SHIFT                  (30u)
+#define GPIO_PSR8_PSR831_SHIFT                  (31u)
+
+#define GPIO_PPR8_PPR80_SHIFT                   (0u)
+#define GPIO_PPR8_PPR81_SHIFT                   (1u)
+#define GPIO_PPR8_PPR82_SHIFT                   (2u)
+#define GPIO_PPR8_PPR83_SHIFT                   (3u)
+#define GPIO_PPR8_PPR84_SHIFT                   (4u)
+#define GPIO_PPR8_PPR85_SHIFT                   (5u)
+#define GPIO_PPR8_PPR86_SHIFT                   (6u)
+#define GPIO_PPR8_PPR87_SHIFT                   (7u)
+#define GPIO_PPR8_PPR88_SHIFT                   (8u)
+#define GPIO_PPR8_PPR89_SHIFT                   (9u)
+#define GPIO_PPR8_PPR810_SHIFT                  (10u)
+#define GPIO_PPR8_PPR811_SHIFT                  (11u)
+#define GPIO_PPR8_PPR812_SHIFT                  (12u)
+#define GPIO_PPR8_PPR813_SHIFT                  (13u)
+#define GPIO_PPR8_PPR814_SHIFT                  (14u)
+#define GPIO_PPR8_PPR815_SHIFT                  (15u)
+
+#define GPIO_PM8_PM80_SHIFT                     (0u)
+#define GPIO_PM8_PM81_SHIFT                     (1u)
+#define GPIO_PM8_PM82_SHIFT                     (2u)
+#define GPIO_PM8_PM83_SHIFT                     (3u)
+#define GPIO_PM8_PM84_SHIFT                     (4u)
+#define GPIO_PM8_PM85_SHIFT                     (5u)
+#define GPIO_PM8_PM86_SHIFT                     (6u)
+#define GPIO_PM8_PM87_SHIFT                     (7u)
+#define GPIO_PM8_PM88_SHIFT                     (8u)
+#define GPIO_PM8_PM89_SHIFT                     (9u)
+#define GPIO_PM8_PM810_SHIFT                    (10u)
+#define GPIO_PM8_PM811_SHIFT                    (11u)
+#define GPIO_PM8_PM812_SHIFT                    (12u)
+#define GPIO_PM8_PM813_SHIFT                    (13u)
+#define GPIO_PM8_PM814_SHIFT                    (14u)
+#define GPIO_PM8_PM815_SHIFT                    (15u)
+
+#define GPIO_PMC8_PMC80_SHIFT                   (0u)
+#define GPIO_PMC8_PMC81_SHIFT                   (1u)
+#define GPIO_PMC8_PMC82_SHIFT                   (2u)
+#define GPIO_PMC8_PMC83_SHIFT                   (3u)
+#define GPIO_PMC8_PMC84_SHIFT                   (4u)
+#define GPIO_PMC8_PMC85_SHIFT                   (5u)
+#define GPIO_PMC8_PMC86_SHIFT                   (6u)
+#define GPIO_PMC8_PMC87_SHIFT                   (7u)
+#define GPIO_PMC8_PMC88_SHIFT                   (8u)
+#define GPIO_PMC8_PMC89_SHIFT                   (9u)
+#define GPIO_PMC8_PMC810_SHIFT                  (10u)
+#define GPIO_PMC8_PMC811_SHIFT                  (11u)
+#define GPIO_PMC8_PMC812_SHIFT                  (12u)
+#define GPIO_PMC8_PMC813_SHIFT                  (13u)
+#define GPIO_PMC8_PMC814_SHIFT                  (14u)
+#define GPIO_PMC8_PMC815_SHIFT                  (15u)
+
+#define GPIO_PFC8_PFC80_SHIFT                   (0u)
+#define GPIO_PFC8_PFC81_SHIFT                   (1u)
+#define GPIO_PFC8_PFC82_SHIFT                   (2u)
+#define GPIO_PFC8_PFC83_SHIFT                   (3u)
+#define GPIO_PFC8_PFC84_SHIFT                   (4u)
+#define GPIO_PFC8_PFC85_SHIFT                   (5u)
+#define GPIO_PFC8_PFC86_SHIFT                   (6u)
+#define GPIO_PFC8_PFC87_SHIFT                   (7u)
+#define GPIO_PFC8_PFC88_SHIFT                   (8u)
+#define GPIO_PFC8_PFC89_SHIFT                   (9u)
+#define GPIO_PFC8_PFC810_SHIFT                  (10u)
+#define GPIO_PFC8_PFC811_SHIFT                  (11u)
+#define GPIO_PFC8_PFC812_SHIFT                  (12u)
+#define GPIO_PFC8_PFC813_SHIFT                  (13u)
+#define GPIO_PFC8_PFC814_SHIFT                  (14u)
+#define GPIO_PFC8_PFC815_SHIFT                  (15u)
+
+#define GPIO_PFCE8_PFCE80_SHIFT                 (0u)
+#define GPIO_PFCE8_PFCE81_SHIFT                 (1u)
+#define GPIO_PFCE8_PFCE82_SHIFT                 (2u)
+#define GPIO_PFCE8_PFCE83_SHIFT                 (3u)
+#define GPIO_PFCE8_PFCE84_SHIFT                 (4u)
+#define GPIO_PFCE8_PFCE85_SHIFT                 (5u)
+#define GPIO_PFCE8_PFCE86_SHIFT                 (6u)
+#define GPIO_PFCE8_PFCE87_SHIFT                 (7u)
+#define GPIO_PFCE8_PFCE88_SHIFT                 (8u)
+#define GPIO_PFCE8_PFCE89_SHIFT                 (9u)
+#define GPIO_PFCE8_PFCE810_SHIFT                (10u)
+#define GPIO_PFCE8_PFCE811_SHIFT                (11u)
+#define GPIO_PFCE8_PFCE812_SHIFT                (12u)
+#define GPIO_PFCE8_PFCE813_SHIFT                (13u)
+#define GPIO_PFCE8_PFCE814_SHIFT                (14u)
+#define GPIO_PFCE8_PFCE815_SHIFT                (15u)
+
+#define GPIO_PNOT8_PNOT80_SHIFT                 (0u)
+#define GPIO_PNOT8_PNOT81_SHIFT                 (1u)
+#define GPIO_PNOT8_PNOT82_SHIFT                 (2u)
+#define GPIO_PNOT8_PNOT83_SHIFT                 (3u)
+#define GPIO_PNOT8_PNOT84_SHIFT                 (4u)
+#define GPIO_PNOT8_PNOT85_SHIFT                 (5u)
+#define GPIO_PNOT8_PNOT86_SHIFT                 (6u)
+#define GPIO_PNOT8_PNOT87_SHIFT                 (7u)
+#define GPIO_PNOT8_PNOT88_SHIFT                 (8u)
+#define GPIO_PNOT8_PNOT89_SHIFT                 (9u)
+#define GPIO_PNOT8_PNOT810_SHIFT                (10u)
+#define GPIO_PNOT8_PNOT811_SHIFT                (11u)
+#define GPIO_PNOT8_PNOT812_SHIFT                (12u)
+#define GPIO_PNOT8_PNOT813_SHIFT                (13u)
+#define GPIO_PNOT8_PNOT814_SHIFT                (14u)
+#define GPIO_PNOT8_PNOT815_SHIFT                (15u)
+
+#define GPIO_PMSR8_PMSR80_SHIFT                 (0u)
+#define GPIO_PMSR8_PMSR81_SHIFT                 (1u)
+#define GPIO_PMSR8_PMSR82_SHIFT                 (2u)
+#define GPIO_PMSR8_PMSR83_SHIFT                 (3u)
+#define GPIO_PMSR8_PMSR84_SHIFT                 (4u)
+#define GPIO_PMSR8_PMSR85_SHIFT                 (5u)
+#define GPIO_PMSR8_PMSR86_SHIFT                 (6u)
+#define GPIO_PMSR8_PMSR87_SHIFT                 (7u)
+#define GPIO_PMSR8_PMSR88_SHIFT                 (8u)
+#define GPIO_PMSR8_PMSR89_SHIFT                 (9u)
+#define GPIO_PMSR8_PMSR810_SHIFT                (10u)
+#define GPIO_PMSR8_PMSR811_SHIFT                (11u)
+#define GPIO_PMSR8_PMSR812_SHIFT                (12u)
+#define GPIO_PMSR8_PMSR813_SHIFT                (13u)
+#define GPIO_PMSR8_PMSR814_SHIFT                (14u)
+#define GPIO_PMSR8_PMSR815_SHIFT                (15u)
+#define GPIO_PMSR8_PMSR816_SHIFT                (16u)
+#define GPIO_PMSR8_PMSR817_SHIFT                (17u)
+#define GPIO_PMSR8_PMSR818_SHIFT                (18u)
+#define GPIO_PMSR8_PMSR819_SHIFT                (19u)
+#define GPIO_PMSR8_PMSR820_SHIFT                (20u)
+#define GPIO_PMSR8_PMSR821_SHIFT                (21u)
+#define GPIO_PMSR8_PMSR822_SHIFT                (22u)
+#define GPIO_PMSR8_PMSR823_SHIFT                (23u)
+#define GPIO_PMSR8_PMSR824_SHIFT                (24u)
+#define GPIO_PMSR8_PMSR825_SHIFT                (25u)
+#define GPIO_PMSR8_PMSR826_SHIFT                (26u)
+#define GPIO_PMSR8_PMSR827_SHIFT                (27u)
+#define GPIO_PMSR8_PMSR828_SHIFT                (28u)
+#define GPIO_PMSR8_PMSR829_SHIFT                (29u)
+#define GPIO_PMSR8_PMSR830_SHIFT                (30u)
+#define GPIO_PMSR8_PMSR831_SHIFT                (31u)
+
+#define GPIO_PMCSR8_PMCSR80_SHIFT               (0u)
+#define GPIO_PMCSR8_PMCSR81_SHIFT               (1u)
+#define GPIO_PMCSR8_PMCSR82_SHIFT               (2u)
+#define GPIO_PMCSR8_PMCSR83_SHIFT               (3u)
+#define GPIO_PMCSR8_PMCSR84_SHIFT               (4u)
+#define GPIO_PMCSR8_PMCSR85_SHIFT               (5u)
+#define GPIO_PMCSR8_PMCSR86_SHIFT               (6u)
+#define GPIO_PMCSR8_PMCSR87_SHIFT               (7u)
+#define GPIO_PMCSR8_PMCSR88_SHIFT               (8u)
+#define GPIO_PMCSR8_PMCSR89_SHIFT               (9u)
+#define GPIO_PMCSR8_PMCSR810_SHIFT              (10u)
+#define GPIO_PMCSR8_PMCSR811_SHIFT              (11u)
+#define GPIO_PMCSR8_PMCSR812_SHIFT              (12u)
+#define GPIO_PMCSR8_PMCSR813_SHIFT              (13u)
+#define GPIO_PMCSR8_PMCSR814_SHIFT              (14u)
+#define GPIO_PMCSR8_PMCSR815_SHIFT              (15u)
+#define GPIO_PMCSR8_PMCSR816_SHIFT              (16u)
+#define GPIO_PMCSR8_PMCSR817_SHIFT              (17u)
+#define GPIO_PMCSR8_PMCSR818_SHIFT              (18u)
+#define GPIO_PMCSR8_PMCSR819_SHIFT              (19u)
+#define GPIO_PMCSR8_PMCSR820_SHIFT              (20u)
+#define GPIO_PMCSR8_PMCSR821_SHIFT              (21u)
+#define GPIO_PMCSR8_PMCSR822_SHIFT              (22u)
+#define GPIO_PMCSR8_PMCSR823_SHIFT              (23u)
+#define GPIO_PMCSR8_PMCSR824_SHIFT              (24u)
+#define GPIO_PMCSR8_PMCSR825_SHIFT              (25u)
+#define GPIO_PMCSR8_PMCSR826_SHIFT              (26u)
+#define GPIO_PMCSR8_PMCSR827_SHIFT              (27u)
+#define GPIO_PMCSR8_PMCSR828_SHIFT              (28u)
+#define GPIO_PMCSR8_PMCSR829_SHIFT              (29u)
+#define GPIO_PMCSR8_PMCSR830_SHIFT              (30u)
+#define GPIO_PMCSR8_PMCSR831_SHIFT              (31u)
+
+#define GPIO_PFCAE8_PFCAE80_SHIFT               (0u)
+#define GPIO_PFCAE8_PFCAE81_SHIFT               (1u)
+#define GPIO_PFCAE8_PFCAE82_SHIFT               (2u)
+#define GPIO_PFCAE8_PFCAE83_SHIFT               (3u)
+#define GPIO_PFCAE8_PFCAE84_SHIFT               (4u)
+#define GPIO_PFCAE8_PFCAE85_SHIFT               (5u)
+#define GPIO_PFCAE8_PFCAE86_SHIFT               (6u)
+#define GPIO_PFCAE8_PFCAE87_SHIFT               (7u)
+#define GPIO_PFCAE8_PFCAE88_SHIFT               (8u)
+#define GPIO_PFCAE8_PFCAE89_SHIFT               (9u)
+#define GPIO_PFCAE8_PFCAE810_SHIFT              (10u)
+#define GPIO_PFCAE8_PFCAE811_SHIFT              (11u)
+#define GPIO_PFCAE8_PFCAE812_SHIFT              (12u)
+#define GPIO_PFCAE8_PFCAE813_SHIFT              (13u)
+#define GPIO_PFCAE8_PFCAE814_SHIFT              (14u)
+#define GPIO_PFCAE8_PFCAE815_SHIFT              (15u)
+
+#define GPIO_PIBC8_PIBC80_SHIFT                 (0u)
+#define GPIO_PIBC8_PIBC81_SHIFT                 (1u)
+#define GPIO_PIBC8_PIBC82_SHIFT                 (2u)
+#define GPIO_PIBC8_PIBC83_SHIFT                 (3u)
+#define GPIO_PIBC8_PIBC84_SHIFT                 (4u)
+#define GPIO_PIBC8_PIBC85_SHIFT                 (5u)
+#define GPIO_PIBC8_PIBC86_SHIFT                 (6u)
+#define GPIO_PIBC8_PIBC87_SHIFT                 (7u)
+#define GPIO_PIBC8_PIBC88_SHIFT                 (8u)
+#define GPIO_PIBC8_PIBC89_SHIFT                 (9u)
+#define GPIO_PIBC8_PIBC810_SHIFT                (10u)
+#define GPIO_PIBC8_PIBC811_SHIFT                (11u)
+#define GPIO_PIBC8_PIBC812_SHIFT                (12u)
+#define GPIO_PIBC8_PIBC813_SHIFT                (13u)
+#define GPIO_PIBC8_PIBC814_SHIFT                (14u)
+#define GPIO_PIBC8_PIBC815_SHIFT                (15u)
+
+#define GPIO_PBDC8_PBDC80_SHIFT                 (0u)
+#define GPIO_PBDC8_PBDC81_SHIFT                 (1u)
+#define GPIO_PBDC8_PBDC82_SHIFT                 (2u)
+#define GPIO_PBDC8_PBDC83_SHIFT                 (3u)
+#define GPIO_PBDC8_PBDC84_SHIFT                 (4u)
+#define GPIO_PBDC8_PBDC85_SHIFT                 (5u)
+#define GPIO_PBDC8_PBDC86_SHIFT                 (6u)
+#define GPIO_PBDC8_PBDC87_SHIFT                 (7u)
+#define GPIO_PBDC8_PBDC88_SHIFT                 (8u)
+#define GPIO_PBDC8_PBDC89_SHIFT                 (9u)
+#define GPIO_PBDC8_PBDC810_SHIFT                (10u)
+#define GPIO_PBDC8_PBDC811_SHIFT                (11u)
+#define GPIO_PBDC8_PBDC812_SHIFT                (12u)
+#define GPIO_PBDC8_PBDC813_SHIFT                (13u)
+#define GPIO_PBDC8_PBDC814_SHIFT                (14u)
+#define GPIO_PBDC8_PBDC815_SHIFT                (15u)
+
+#define GPIO_PIPC8_PIPC80_SHIFT                 (0u)
+#define GPIO_PIPC8_PIPC81_SHIFT                 (1u)
+#define GPIO_PIPC8_PIPC82_SHIFT                 (2u)
+#define GPIO_PIPC8_PIPC83_SHIFT                 (3u)
+#define GPIO_PIPC8_PIPC84_SHIFT                 (4u)
+#define GPIO_PIPC8_PIPC85_SHIFT                 (5u)
+#define GPIO_PIPC8_PIPC86_SHIFT                 (6u)
+#define GPIO_PIPC8_PIPC87_SHIFT                 (7u)
+#define GPIO_PIPC8_PIPC88_SHIFT                 (8u)
+#define GPIO_PIPC8_PIPC89_SHIFT                 (9u)
+#define GPIO_PIPC8_PIPC810_SHIFT                (10u)
+#define GPIO_PIPC8_PIPC811_SHIFT                (11u)
+#define GPIO_PIPC8_PIPC812_SHIFT                (12u)
+#define GPIO_PIPC8_PIPC813_SHIFT                (13u)
+#define GPIO_PIPC8_PIPC814_SHIFT                (14u)
+#define GPIO_PIPC8_PIPC815_SHIFT                (15u)
+
+/* ---- P9 ---- */
+#define GPIO_P9_P90_SHIFT                       (0u)
+#define GPIO_P9_P91_SHIFT                       (1u)
+#define GPIO_P9_P92_SHIFT                       (2u)
+#define GPIO_P9_P93_SHIFT                       (3u)
+#define GPIO_P9_P94_SHIFT                       (4u)
+#define GPIO_P9_P95_SHIFT                       (5u)
+#define GPIO_P9_P96_SHIFT                       (6u)
+#define GPIO_P9_P97_SHIFT                       (7u)
+
+#define GPIO_PSR9_PSR90_SHIFT                   (0u)
+#define GPIO_PSR9_PSR91_SHIFT                   (1u)
+#define GPIO_PSR9_PSR92_SHIFT                   (2u)
+#define GPIO_PSR9_PSR93_SHIFT                   (3u)
+#define GPIO_PSR9_PSR94_SHIFT                   (4u)
+#define GPIO_PSR9_PSR95_SHIFT                   (5u)
+#define GPIO_PSR9_PSR96_SHIFT                   (6u)
+#define GPIO_PSR9_PSR97_SHIFT                   (7u)
+#define GPIO_PSR9_PSR916_SHIFT                  (16u)
+#define GPIO_PSR9_PSR917_SHIFT                  (17u)
+#define GPIO_PSR9_PSR918_SHIFT                  (18u)
+#define GPIO_PSR9_PSR919_SHIFT                  (19u)
+#define GPIO_PSR9_PSR920_SHIFT                  (20u)
+#define GPIO_PSR9_PSR921_SHIFT                  (21u)
+#define GPIO_PSR9_PSR922_SHIFT                  (22u)
+#define GPIO_PSR9_PSR923_SHIFT                  (23u)
+
+#define GPIO_PPR9_PPR90_SHIFT                   (0u)
+#define GPIO_PPR9_PPR91_SHIFT                   (1u)
+#define GPIO_PPR9_PPR92_SHIFT                   (2u)
+#define GPIO_PPR9_PPR93_SHIFT                   (3u)
+#define GPIO_PPR9_PPR94_SHIFT                   (4u)
+#define GPIO_PPR9_PPR95_SHIFT                   (5u)
+#define GPIO_PPR9_PPR96_SHIFT                   (6u)
+#define GPIO_PPR9_PPR97_SHIFT                   (7u)
+
+#define GPIO_PM9_PM90_SHIFT                     (0u)
+#define GPIO_PM9_PM91_SHIFT                     (1u)
+#define GPIO_PM9_PM92_SHIFT                     (2u)
+#define GPIO_PM9_PM93_SHIFT                     (3u)
+#define GPIO_PM9_PM94_SHIFT                     (4u)
+#define GPIO_PM9_PM95_SHIFT                     (5u)
+#define GPIO_PM9_PM96_SHIFT                     (6u)
+#define GPIO_PM9_PM97_SHIFT                     (7u)
+
+#define GPIO_PMC9_PMC90_SHIFT                   (0u)
+#define GPIO_PMC9_PMC91_SHIFT                   (1u)
+#define GPIO_PMC9_PMC92_SHIFT                   (2u)
+#define GPIO_PMC9_PMC93_SHIFT                   (3u)
+#define GPIO_PMC9_PMC94_SHIFT                   (4u)
+#define GPIO_PMC9_PMC95_SHIFT                   (5u)
+#define GPIO_PMC9_PMC96_SHIFT                   (6u)
+#define GPIO_PMC9_PMC97_SHIFT                   (7u)
+
+#define GPIO_PFC9_PFC90_SHIFT                   (0u)
+#define GPIO_PFC9_PFC91_SHIFT                   (1u)
+#define GPIO_PFC9_PFC92_SHIFT                   (2u)
+#define GPIO_PFC9_PFC93_SHIFT                   (3u)
+#define GPIO_PFC9_PFC94_SHIFT                   (4u)
+#define GPIO_PFC9_PFC95_SHIFT                   (5u)
+#define GPIO_PFC9_PFC96_SHIFT                   (6u)
+#define GPIO_PFC9_PFC97_SHIFT                   (7u)
+
+#define GPIO_PFCE9_PFCE90_SHIFT                 (0u)
+#define GPIO_PFCE9_PFCE91_SHIFT                 (1u)
+#define GPIO_PFCE9_PFCE92_SHIFT                 (2u)
+#define GPIO_PFCE9_PFCE93_SHIFT                 (3u)
+#define GPIO_PFCE9_PFCE94_SHIFT                 (4u)
+#define GPIO_PFCE9_PFCE95_SHIFT                 (5u)
+#define GPIO_PFCE9_PFCE96_SHIFT                 (6u)
+#define GPIO_PFCE9_PFCE97_SHIFT                 (7u)
+
+#define GPIO_PNOT9_PNOT90_SHIFT                 (0u)
+#define GPIO_PNOT9_PNOT91_SHIFT                 (1u)
+#define GPIO_PNOT9_PNOT92_SHIFT                 (2u)
+#define GPIO_PNOT9_PNOT93_SHIFT                 (3u)
+#define GPIO_PNOT9_PNOT94_SHIFT                 (4u)
+#define GPIO_PNOT9_PNOT95_SHIFT                 (5u)
+#define GPIO_PNOT9_PNOT96_SHIFT                 (6u)
+#define GPIO_PNOT9_PNOT97_SHIFT                 (7u)
+
+#define GPIO_PMSR9_PMSR90_SHIFT                 (0u)
+#define GPIO_PMSR9_PMSR91_SHIFT                 (1u)
+#define GPIO_PMSR9_PMSR92_SHIFT                 (2u)
+#define GPIO_PMSR9_PMSR93_SHIFT                 (3u)
+#define GPIO_PMSR9_PMSR94_SHIFT                 (4u)
+#define GPIO_PMSR9_PMSR95_SHIFT                 (5u)
+#define GPIO_PMSR9_PMSR96_SHIFT                 (6u)
+#define GPIO_PMSR9_PMSR97_SHIFT                 (7u)
+#define GPIO_PMSR9_PMSR916_SHIFT                (16u)
+#define GPIO_PMSR9_PMSR917_SHIFT                (17u)
+#define GPIO_PMSR9_PMSR918_SHIFT                (18u)
+#define GPIO_PMSR9_PMSR919_SHIFT                (19u)
+#define GPIO_PMSR9_PMSR920_SHIFT                (20u)
+#define GPIO_PMSR9_PMSR921_SHIFT                (21u)
+#define GPIO_PMSR9_PMSR922_SHIFT                (22u)
+#define GPIO_PMSR9_PMSR923_SHIFT                (23u)
+
+#define GPIO_PMCSR9_PMCSR90_SHIFT               (0u)
+#define GPIO_PMCSR9_PMCSR91_SHIFT               (1u)
+#define GPIO_PMCSR9_PMCSR92_SHIFT               (2u)
+#define GPIO_PMCSR9_PMCSR93_SHIFT               (3u)
+#define GPIO_PMCSR9_PMCSR94_SHIFT               (4u)
+#define GPIO_PMCSR9_PMCSR95_SHIFT               (5u)
+#define GPIO_PMCSR9_PMCSR96_SHIFT               (6u)
+#define GPIO_PMCSR9_PMCSR97_SHIFT               (7u)
+#define GPIO_PMCSR9_PMCSR916_SHIFT              (16u)
+#define GPIO_PMCSR9_PMCSR917_SHIFT              (17u)
+#define GPIO_PMCSR9_PMCSR918_SHIFT              (18u)
+#define GPIO_PMCSR9_PMCSR919_SHIFT              (19u)
+#define GPIO_PMCSR9_PMCSR920_SHIFT              (20u)
+#define GPIO_PMCSR9_PMCSR921_SHIFT              (21u)
+#define GPIO_PMCSR9_PMCSR922_SHIFT              (22u)
+#define GPIO_PMCSR9_PMCSR923_SHIFT              (23u)
+
+#define GPIO_PFCAE9_PFCAE90_SHIFT               (0u)
+#define GPIO_PFCAE9_PFCAE91_SHIFT               (1u)
+#define GPIO_PFCAE9_PFCAE92_SHIFT               (2u)
+#define GPIO_PFCAE9_PFCAE93_SHIFT               (3u)
+#define GPIO_PFCAE9_PFCAE94_SHIFT               (4u)
+#define GPIO_PFCAE9_PFCAE95_SHIFT               (5u)
+#define GPIO_PFCAE9_PFCAE96_SHIFT               (6u)
+#define GPIO_PFCAE9_PFCAE97_SHIFT               (7u)
+
+#define GPIO_PIBC9_PIBC90_SHIFT                 (0u)
+#define GPIO_PIBC9_PIBC91_SHIFT                 (1u)
+#define GPIO_PIBC9_PIBC92_SHIFT                 (2u)
+#define GPIO_PIBC9_PIBC93_SHIFT                 (3u)
+#define GPIO_PIBC9_PIBC94_SHIFT                 (4u)
+#define GPIO_PIBC9_PIBC95_SHIFT                 (5u)
+#define GPIO_PIBC9_PIBC96_SHIFT                 (6u)
+#define GPIO_PIBC9_PIBC97_SHIFT                 (7u)
+
+#define GPIO_PBDC9_PBDC90_SHIFT                 (0u)
+#define GPIO_PBDC9_PBDC91_SHIFT                 (1u)
+#define GPIO_PBDC9_PBDC92_SHIFT                 (2u)
+#define GPIO_PBDC9_PBDC93_SHIFT                 (3u)
+#define GPIO_PBDC9_PBDC94_SHIFT                 (4u)
+#define GPIO_PBDC9_PBDC95_SHIFT                 (5u)
+#define GPIO_PBDC9_PBDC96_SHIFT                 (6u)
+#define GPIO_PBDC9_PBDC97_SHIFT                 (7u)
+
+#define GPIO_PIPC9_PIPC90_SHIFT                 (0u)
+#define GPIO_PIPC9_PIPC91_SHIFT                 (1u)
+#define GPIO_PIPC9_PIPC92_SHIFT                 (2u)
+#define GPIO_PIPC9_PIPC93_SHIFT                 (3u)
+#define GPIO_PIPC9_PIPC94_SHIFT                 (4u)
+#define GPIO_PIPC9_PIPC95_SHIFT                 (5u)
+#define GPIO_PIPC9_PIPC96_SHIFT                 (6u)
+#define GPIO_PIPC9_PIPC97_SHIFT                 (7u)
+
+/* ---- P10 ---- */
+#define GPIO_P10_P100_SHIFT                     (0u)
+#define GPIO_P10_P101_SHIFT                     (1u)
+#define GPIO_P10_P102_SHIFT                     (2u)
+#define GPIO_P10_P103_SHIFT                     (3u)
+#define GPIO_P10_P104_SHIFT                     (4u)
+#define GPIO_P10_P105_SHIFT                     (5u)
+#define GPIO_P10_P106_SHIFT                     (6u)
+#define GPIO_P10_P107_SHIFT                     (7u)
+#define GPIO_P10_P108_SHIFT                     (8u)
+#define GPIO_P10_P109_SHIFT                     (9u)
+#define GPIO_P10_P1010_SHIFT                    (10u)
+#define GPIO_P10_P1011_SHIFT                    (11u)
+#define GPIO_P10_P1012_SHIFT                    (12u)
+#define GPIO_P10_P1013_SHIFT                    (13u)
+#define GPIO_P10_P1014_SHIFT                    (14u)
+#define GPIO_P10_P1015_SHIFT                    (15u)
+
+#define GPIO_PSR10_PSR100_SHIFT                 (0u)
+#define GPIO_PSR10_PSR101_SHIFT                 (1u)
+#define GPIO_PSR10_PSR102_SHIFT                 (2u)
+#define GPIO_PSR10_PSR103_SHIFT                 (3u)
+#define GPIO_PSR10_PSR104_SHIFT                 (4u)
+#define GPIO_PSR10_PSR105_SHIFT                 (5u)
+#define GPIO_PSR10_PSR106_SHIFT                 (6u)
+#define GPIO_PSR10_PSR107_SHIFT                 (7u)
+#define GPIO_PSR10_PSR108_SHIFT                 (8u)
+#define GPIO_PSR10_PSR109_SHIFT                 (9u)
+#define GPIO_PSR10_PSR1010_SHIFT                (10u)
+#define GPIO_PSR10_PSR1011_SHIFT                (11u)
+#define GPIO_PSR10_PSR1012_SHIFT                (12u)
+#define GPIO_PSR10_PSR1013_SHIFT                (13u)
+#define GPIO_PSR10_PSR1014_SHIFT                (14u)
+#define GPIO_PSR10_PSR1015_SHIFT                (15u)
+#define GPIO_PSR10_PSR1016_SHIFT                (16u)
+#define GPIO_PSR10_PSR1017_SHIFT                (17u)
+#define GPIO_PSR10_PSR1018_SHIFT                (18u)
+#define GPIO_PSR10_PSR1019_SHIFT                (19u)
+#define GPIO_PSR10_PSR1020_SHIFT                (20u)
+#define GPIO_PSR10_PSR1021_SHIFT                (21u)
+#define GPIO_PSR10_PSR1022_SHIFT                (22u)
+#define GPIO_PSR10_PSR1023_SHIFT                (23u)
+#define GPIO_PSR10_PSR1024_SHIFT                (24u)
+#define GPIO_PSR10_PSR1025_SHIFT                (25u)
+#define GPIO_PSR10_PSR1026_SHIFT                (26u)
+#define GPIO_PSR10_PSR1027_SHIFT                (27u)
+#define GPIO_PSR10_PSR1028_SHIFT                (28u)
+#define GPIO_PSR10_PSR1029_SHIFT                (29u)
+#define GPIO_PSR10_PSR1030_SHIFT                (30u)
+#define GPIO_PSR10_PSR1031_SHIFT                (31u)
+
+#define GPIO_PPR10_PPR100_SHIFT                 (0u)
+#define GPIO_PPR10_PPR101_SHIFT                 (1u)
+#define GPIO_PPR10_PPR102_SHIFT                 (2u)
+#define GPIO_PPR10_PPR103_SHIFT                 (3u)
+#define GPIO_PPR10_PPR104_SHIFT                 (4u)
+#define GPIO_PPR10_PPR105_SHIFT                 (5u)
+#define GPIO_PPR10_PPR106_SHIFT                 (6u)
+#define GPIO_PPR10_PPR107_SHIFT                 (7u)
+#define GPIO_PPR10_PPR108_SHIFT                 (8u)
+#define GPIO_PPR10_PPR109_SHIFT                 (9u)
+#define GPIO_PPR10_PPR1010_SHIFT                (10u)
+#define GPIO_PPR10_PPR1011_SHIFT                (11u)
+#define GPIO_PPR10_PPR1012_SHIFT                (12u)
+#define GPIO_PPR10_PPR1013_SHIFT                (13u)
+#define GPIO_PPR10_PPR1014_SHIFT                (14u)
+#define GPIO_PPR10_PPR1015_SHIFT                (15u)
+
+#define GPIO_PM10_PM100_SHIFT                   (0u)
+#define GPIO_PM10_PM101_SHIFT                   (1u)
+#define GPIO_PM10_PM102_SHIFT                   (2u)
+#define GPIO_PM10_PM103_SHIFT                   (3u)
+#define GPIO_PM10_PM104_SHIFT                   (4u)
+#define GPIO_PM10_PM105_SHIFT                   (5u)
+#define GPIO_PM10_PM106_SHIFT                   (6u)
+#define GPIO_PM10_PM107_SHIFT                   (7u)
+#define GPIO_PM10_PM108_SHIFT                   (8u)
+#define GPIO_PM10_PM109_SHIFT                   (9u)
+#define GPIO_PM10_PM1010_SHIFT                  (10u)
+#define GPIO_PM10_PM1011_SHIFT                  (11u)
+#define GPIO_PM10_PM1012_SHIFT                  (12u)
+#define GPIO_PM10_PM1013_SHIFT                  (13u)
+#define GPIO_PM10_PM1014_SHIFT                  (14u)
+#define GPIO_PM10_PM1015_SHIFT                  (15u)
+
+#define GPIO_PMC10_PMC100_SHIFT                 (0u)
+#define GPIO_PMC10_PMC101_SHIFT                 (1u)
+#define GPIO_PMC10_PMC102_SHIFT                 (2u)
+#define GPIO_PMC10_PMC103_SHIFT                 (3u)
+#define GPIO_PMC10_PMC104_SHIFT                 (4u)
+#define GPIO_PMC10_PMC105_SHIFT                 (5u)
+#define GPIO_PMC10_PMC106_SHIFT                 (6u)
+#define GPIO_PMC10_PMC107_SHIFT                 (7u)
+#define GPIO_PMC10_PMC108_SHIFT                 (8u)
+#define GPIO_PMC10_PMC109_SHIFT                 (9u)
+#define GPIO_PMC10_PMC1010_SHIFT                (10u)
+#define GPIO_PMC10_PMC1011_SHIFT                (11u)
+#define GPIO_PMC10_PMC1012_SHIFT                (12u)
+#define GPIO_PMC10_PMC1013_SHIFT                (13u)
+#define GPIO_PMC10_PMC1014_SHIFT                (14u)
+#define GPIO_PMC10_PMC1015_SHIFT                (15u)
+
+#define GPIO_PFC10_PFC100_SHIFT                 (0u)
+#define GPIO_PFC10_PFC101_SHIFT                 (1u)
+#define GPIO_PFC10_PFC102_SHIFT                 (2u)
+#define GPIO_PFC10_PFC103_SHIFT                 (3u)
+#define GPIO_PFC10_PFC104_SHIFT                 (4u)
+#define GPIO_PFC10_PFC105_SHIFT                 (5u)
+#define GPIO_PFC10_PFC106_SHIFT                 (6u)
+#define GPIO_PFC10_PFC107_SHIFT                 (7u)
+#define GPIO_PFC10_PFC108_SHIFT                 (8u)
+#define GPIO_PFC10_PFC109_SHIFT                 (9u)
+#define GPIO_PFC10_PFC1010_SHIFT                (10u)
+#define GPIO_PFC10_PFC1011_SHIFT                (11u)
+#define GPIO_PFC10_PFC1012_SHIFT                (12u)
+#define GPIO_PFC10_PFC1013_SHIFT                (13u)
+#define GPIO_PFC10_PFC1014_SHIFT                (14u)
+#define GPIO_PFC10_PFC1015_SHIFT                (15u)
+
+#define GPIO_PFCE10_PFCE100_SHIFT               (0u)
+#define GPIO_PFCE10_PFCE101_SHIFT               (1u)
+#define GPIO_PFCE10_PFCE102_SHIFT               (2u)
+#define GPIO_PFCE10_PFCE103_SHIFT               (3u)
+#define GPIO_PFCE10_PFCE104_SHIFT               (4u)
+#define GPIO_PFCE10_PFCE105_SHIFT               (5u)
+#define GPIO_PFCE10_PFCE106_SHIFT               (6u)
+#define GPIO_PFCE10_PFCE107_SHIFT               (7u)
+#define GPIO_PFCE10_PFCE108_SHIFT               (8u)
+#define GPIO_PFCE10_PFCE109_SHIFT               (9u)
+#define GPIO_PFCE10_PFCE1010_SHIFT              (10u)
+#define GPIO_PFCE10_PFCE1011_SHIFT              (11u)
+#define GPIO_PFCE10_PFCE1012_SHIFT              (12u)
+#define GPIO_PFCE10_PFCE1013_SHIFT              (13u)
+#define GPIO_PFCE10_PFCE1014_SHIFT              (14u)
+#define GPIO_PFCE10_PFCE1015_SHIFT              (15u)
+
+#define GPIO_PNOT10_PNOT100_SHIFT               (0u)
+#define GPIO_PNOT10_PNOT101_SHIFT               (1u)
+#define GPIO_PNOT10_PNOT102_SHIFT               (2u)
+#define GPIO_PNOT10_PNOT103_SHIFT               (3u)
+#define GPIO_PNOT10_PNOT104_SHIFT               (4u)
+#define GPIO_PNOT10_PNOT105_SHIFT               (5u)
+#define GPIO_PNOT10_PNOT106_SHIFT               (6u)
+#define GPIO_PNOT10_PNOT107_SHIFT               (7u)
+#define GPIO_PNOT10_PNOT108_SHIFT               (8u)
+#define GPIO_PNOT10_PNOT109_SHIFT               (9u)
+#define GPIO_PNOT10_PNOT1010_SHIFT              (10u)
+#define GPIO_PNOT10_PNOT1011_SHIFT              (11u)
+#define GPIO_PNOT10_PNOT1012_SHIFT              (12u)
+#define GPIO_PNOT10_PNOT1013_SHIFT              (13u)
+#define GPIO_PNOT10_PNOT1014_SHIFT              (14u)
+#define GPIO_PNOT10_PNOT1015_SHIFT              (15u)
+
+#define GPIO_PMSR10_PMSR100_SHIFT               (0u)
+#define GPIO_PMSR10_PMSR101_SHIFT               (1u)
+#define GPIO_PMSR10_PMSR102_SHIFT               (2u)
+#define GPIO_PMSR10_PMSR103_SHIFT               (3u)
+#define GPIO_PMSR10_PMSR104_SHIFT               (4u)
+#define GPIO_PMSR10_PMSR105_SHIFT               (5u)
+#define GPIO_PMSR10_PMSR106_SHIFT               (6u)
+#define GPIO_PMSR10_PMSR107_SHIFT               (7u)
+#define GPIO_PMSR10_PMSR108_SHIFT               (8u)
+#define GPIO_PMSR10_PMSR109_SHIFT               (9u)
+#define GPIO_PMSR10_PMSR1010_SHIFT              (10u)
+#define GPIO_PMSR10_PMSR1011_SHIFT              (11u)
+#define GPIO_PMSR10_PMSR1012_SHIFT              (12u)
+#define GPIO_PMSR10_PMSR1013_SHIFT              (13u)
+#define GPIO_PMSR10_PMSR1014_SHIFT              (14u)
+#define GPIO_PMSR10_PMSR1015_SHIFT              (15u)
+#define GPIO_PMSR10_PMSR1016_SHIFT              (16u)
+#define GPIO_PMSR10_PMSR1017_SHIFT              (17u)
+#define GPIO_PMSR10_PMSR1018_SHIFT              (18u)
+#define GPIO_PMSR10_PMSR1019_SHIFT              (19u)
+#define GPIO_PMSR10_PMSR1020_SHIFT              (20u)
+#define GPIO_PMSR10_PMSR1021_SHIFT              (21u)
+#define GPIO_PMSR10_PMSR1022_SHIFT              (22u)
+#define GPIO_PMSR10_PMSR1023_SHIFT              (23u)
+#define GPIO_PMSR10_PMSR1024_SHIFT              (24u)
+#define GPIO_PMSR10_PMSR1025_SHIFT              (25u)
+#define GPIO_PMSR10_PMSR1026_SHIFT              (26u)
+#define GPIO_PMSR10_PMSR1027_SHIFT              (27u)
+#define GPIO_PMSR10_PMSR1028_SHIFT              (28u)
+#define GPIO_PMSR10_PMSR1029_SHIFT              (29u)
+#define GPIO_PMSR10_PMSR1030_SHIFT              (30u)
+#define GPIO_PMSR10_PMSR1031_SHIFT              (31u)
+
+#define GPIO_PMCSR10_PMCSR100_SHIFT             (0u)
+#define GPIO_PMCSR10_PMCSR101_SHIFT             (1u)
+#define GPIO_PMCSR10_PMCSR102_SHIFT             (2u)
+#define GPIO_PMCSR10_PMCSR103_SHIFT             (3u)
+#define GPIO_PMCSR10_PMCSR104_SHIFT             (4u)
+#define GPIO_PMCSR10_PMCSR105_SHIFT             (5u)
+#define GPIO_PMCSR10_PMCSR106_SHIFT             (6u)
+#define GPIO_PMCSR10_PMCSR107_SHIFT             (7u)
+#define GPIO_PMCSR10_PMCSR108_SHIFT             (8u)
+#define GPIO_PMCSR10_PMCSR109_SHIFT             (9u)
+#define GPIO_PMCSR10_PMCSR1010_SHIFT            (10u)
+#define GPIO_PMCSR10_PMCSR1011_SHIFT            (11u)
+#define GPIO_PMCSR10_PMCSR1012_SHIFT            (12u)
+#define GPIO_PMCSR10_PMCSR1013_SHIFT            (13u)
+#define GPIO_PMCSR10_PMCSR1014_SHIFT            (14u)
+#define GPIO_PMCSR10_PMCSR1015_SHIFT            (15u)
+#define GPIO_PMCSR10_PMCSR1016_SHIFT            (16u)
+#define GPIO_PMCSR10_PMCSR1017_SHIFT            (17u)
+#define GPIO_PMCSR10_PMCSR1018_SHIFT            (18u)
+#define GPIO_PMCSR10_PMCSR1019_SHIFT            (19u)
+#define GPIO_PMCSR10_PMCSR1020_SHIFT            (20u)
+#define GPIO_PMCSR10_PMCSR1021_SHIFT            (21u)
+#define GPIO_PMCSR10_PMCSR1022_SHIFT            (22u)
+#define GPIO_PMCSR10_PMCSR1023_SHIFT            (23u)
+#define GPIO_PMCSR10_PMCSR1024_SHIFT            (24u)
+#define GPIO_PMCSR10_PMCSR1025_SHIFT            (25u)
+#define GPIO_PMCSR10_PMCSR1026_SHIFT            (26u)
+#define GPIO_PMCSR10_PMCSR1027_SHIFT            (27u)
+#define GPIO_PMCSR10_PMCSR1028_SHIFT            (28u)
+#define GPIO_PMCSR10_PMCSR1029_SHIFT            (29u)
+#define GPIO_PMCSR10_PMCSR1030_SHIFT            (30u)
+#define GPIO_PMCSR10_PMCSR1031_SHIFT            (31u)
+
+#define GPIO_PFCAE10_PFCAE100_SHIFT             (0u)
+#define GPIO_PFCAE10_PFCAE101_SHIFT             (1u)
+#define GPIO_PFCAE10_PFCAE102_SHIFT             (2u)
+#define GPIO_PFCAE10_PFCAE103_SHIFT             (3u)
+#define GPIO_PFCAE10_PFCAE104_SHIFT             (4u)
+#define GPIO_PFCAE10_PFCAE105_SHIFT             (5u)
+#define GPIO_PFCAE10_PFCAE106_SHIFT             (6u)
+#define GPIO_PFCAE10_PFCAE107_SHIFT             (7u)
+#define GPIO_PFCAE10_PFCAE108_SHIFT             (8u)
+#define GPIO_PFCAE10_PFCAE109_SHIFT             (9u)
+#define GPIO_PFCAE10_PFCAE1010_SHIFT            (10u)
+#define GPIO_PFCAE10_PFCAE1011_SHIFT            (11u)
+#define GPIO_PFCAE10_PFCAE1012_SHIFT            (12u)
+#define GPIO_PFCAE10_PFCAE1013_SHIFT            (13u)
+#define GPIO_PFCAE10_PFCAE1014_SHIFT            (14u)
+#define GPIO_PFCAE10_PFCAE1015_SHIFT            (15u)
+
+#define GPIO_PIBC10_PIBC100_SHIFT               (0u)
+#define GPIO_PIBC10_PIBC101_SHIFT               (1u)
+#define GPIO_PIBC10_PIBC102_SHIFT               (2u)
+#define GPIO_PIBC10_PIBC103_SHIFT               (3u)
+#define GPIO_PIBC10_PIBC104_SHIFT               (4u)
+#define GPIO_PIBC10_PIBC105_SHIFT               (5u)
+#define GPIO_PIBC10_PIBC106_SHIFT               (6u)
+#define GPIO_PIBC10_PIBC107_SHIFT               (7u)
+#define GPIO_PIBC10_PIBC108_SHIFT               (8u)
+#define GPIO_PIBC10_PIBC109_SHIFT               (9u)
+#define GPIO_PIBC10_PIBC1010_SHIFT              (10u)
+#define GPIO_PIBC10_PIBC1011_SHIFT              (11u)
+#define GPIO_PIBC10_PIBC1012_SHIFT              (12u)
+#define GPIO_PIBC10_PIBC1013_SHIFT              (13u)
+#define GPIO_PIBC10_PIBC1014_SHIFT              (14u)
+#define GPIO_PIBC10_PIBC1015_SHIFT              (15u)
+
+#define GPIO_PBDC10_PBDC100_SHIFT               (0u)
+#define GPIO_PBDC10_PBDC101_SHIFT               (1u)
+#define GPIO_PBDC10_PBDC102_SHIFT               (2u)
+#define GPIO_PBDC10_PBDC103_SHIFT               (3u)
+#define GPIO_PBDC10_PBDC104_SHIFT               (4u)
+#define GPIO_PBDC10_PBDC105_SHIFT               (5u)
+#define GPIO_PBDC10_PBDC106_SHIFT               (6u)
+#define GPIO_PBDC10_PBDC107_SHIFT               (7u)
+#define GPIO_PBDC10_PBDC108_SHIFT               (8u)
+#define GPIO_PBDC10_PBDC109_SHIFT               (9u)
+#define GPIO_PBDC10_PBDC1010_SHIFT              (10u)
+#define GPIO_PBDC10_PBDC1011_SHIFT              (11u)
+#define GPIO_PBDC10_PBDC1012_SHIFT              (12u)
+#define GPIO_PBDC10_PBDC1013_SHIFT              (13u)
+#define GPIO_PBDC10_PBDC1014_SHIFT              (14u)
+#define GPIO_PBDC10_PBDC1015_SHIFT              (15u)
+
+#define GPIO_PIPC10_PIPC100_SHIFT               (0u)
+#define GPIO_PIPC10_PIPC101_SHIFT               (1u)
+#define GPIO_PIPC10_PIPC102_SHIFT               (2u)
+#define GPIO_PIPC10_PIPC103_SHIFT               (3u)
+#define GPIO_PIPC10_PIPC104_SHIFT               (4u)
+#define GPIO_PIPC10_PIPC105_SHIFT               (5u)
+#define GPIO_PIPC10_PIPC106_SHIFT               (6u)
+#define GPIO_PIPC10_PIPC107_SHIFT               (7u)
+#define GPIO_PIPC10_PIPC108_SHIFT               (8u)
+#define GPIO_PIPC10_PIPC109_SHIFT               (9u)
+#define GPIO_PIPC10_PIPC1010_SHIFT              (10u)
+#define GPIO_PIPC10_PIPC1011_SHIFT              (11u)
+#define GPIO_PIPC10_PIPC1012_SHIFT              (12u)
+#define GPIO_PIPC10_PIPC1013_SHIFT              (13u)
+#define GPIO_PIPC10_PIPC1014_SHIFT              (14u)
+#define GPIO_PIPC10_PIPC1015_SHIFT              (15u)
+
+/* ---- P11 ---- */
+#define GPIO_P11_P110_SHIFT                     (0u)
+#define GPIO_P11_P111_SHIFT                     (1u)
+#define GPIO_P11_P112_SHIFT                     (2u)
+#define GPIO_P11_P113_SHIFT                     (3u)
+#define GPIO_P11_P114_SHIFT                     (4u)
+#define GPIO_P11_P115_SHIFT                     (5u)
+#define GPIO_P11_P116_SHIFT                     (6u)
+#define GPIO_P11_P117_SHIFT                     (7u)
+#define GPIO_P11_P118_SHIFT                     (8u)
+#define GPIO_P11_P119_SHIFT                     (9u)
+#define GPIO_P11_P1110_SHIFT                    (10u)
+#define GPIO_P11_P1111_SHIFT                    (11u)
+#define GPIO_P11_P1112_SHIFT                    (12u)
+#define GPIO_P11_P1113_SHIFT                    (13u)
+#define GPIO_P11_P1114_SHIFT                    (14u)
+#define GPIO_P11_P1115_SHIFT                    (15u)
+
+#define GPIO_PSR11_PSR110_SHIFT                 (0u)
+#define GPIO_PSR11_PSR111_SHIFT                 (1u)
+#define GPIO_PSR11_PSR112_SHIFT                 (2u)
+#define GPIO_PSR11_PSR113_SHIFT                 (3u)
+#define GPIO_PSR11_PSR114_SHIFT                 (4u)
+#define GPIO_PSR11_PSR115_SHIFT                 (5u)
+#define GPIO_PSR11_PSR116_SHIFT                 (6u)
+#define GPIO_PSR11_PSR117_SHIFT                 (7u)
+#define GPIO_PSR11_PSR118_SHIFT                 (8u)
+#define GPIO_PSR11_PSR119_SHIFT                 (9u)
+#define GPIO_PSR11_PSR1110_SHIFT                (10u)
+#define GPIO_PSR11_PSR1111_SHIFT                (11u)
+#define GPIO_PSR11_PSR1112_SHIFT                (12u)
+#define GPIO_PSR11_PSR1113_SHIFT                (13u)
+#define GPIO_PSR11_PSR1114_SHIFT                (14u)
+#define GPIO_PSR11_PSR1115_SHIFT                (15u)
+#define GPIO_PSR11_PSR1116_SHIFT                (16u)
+#define GPIO_PSR11_PSR1117_SHIFT                (17u)
+#define GPIO_PSR11_PSR1118_SHIFT                (18u)
+#define GPIO_PSR11_PSR1119_SHIFT                (19u)
+#define GPIO_PSR11_PSR1120_SHIFT                (20u)
+#define GPIO_PSR11_PSR1121_SHIFT                (21u)
+#define GPIO_PSR11_PSR1122_SHIFT                (22u)
+#define GPIO_PSR11_PSR1123_SHIFT                (23u)
+#define GPIO_PSR11_PSR1124_SHIFT                (24u)
+#define GPIO_PSR11_PSR1125_SHIFT                (25u)
+#define GPIO_PSR11_PSR1126_SHIFT                (26u)
+#define GPIO_PSR11_PSR1127_SHIFT                (27u)
+#define GPIO_PSR11_PSR1128_SHIFT                (28u)
+#define GPIO_PSR11_PSR1129_SHIFT                (29u)
+#define GPIO_PSR11_PSR1130_SHIFT                (30u)
+#define GPIO_PSR11_PSR1131_SHIFT                (31u)
+
+#define GPIO_PPR11_PPR110_SHIFT                 (0u)
+#define GPIO_PPR11_PPR111_SHIFT                 (1u)
+#define GPIO_PPR11_PPR112_SHIFT                 (2u)
+#define GPIO_PPR11_PPR113_SHIFT                 (3u)
+#define GPIO_PPR11_PPR114_SHIFT                 (4u)
+#define GPIO_PPR11_PPR115_SHIFT                 (5u)
+#define GPIO_PPR11_PPR116_SHIFT                 (6u)
+#define GPIO_PPR11_PPR117_SHIFT                 (7u)
+#define GPIO_PPR11_PPR118_SHIFT                 (8u)
+#define GPIO_PPR11_PPR119_SHIFT                 (9u)
+#define GPIO_PPR11_PPR1110_SHIFT                (10u)
+#define GPIO_PPR11_PPR1111_SHIFT                (11u)
+#define GPIO_PPR11_PPR1112_SHIFT                (12u)
+#define GPIO_PPR11_PPR1113_SHIFT                (13u)
+#define GPIO_PPR11_PPR1114_SHIFT                (14u)
+#define GPIO_PPR11_PPR1115_SHIFT                (15u)
+
+#define GPIO_PM11_PM110_SHIFT                   (0u)
+#define GPIO_PM11_PM111_SHIFT                   (1u)
+#define GPIO_PM11_PM112_SHIFT                   (2u)
+#define GPIO_PM11_PM113_SHIFT                   (3u)
+#define GPIO_PM11_PM114_SHIFT                   (4u)
+#define GPIO_PM11_PM115_SHIFT                   (5u)
+#define GPIO_PM11_PM116_SHIFT                   (6u)
+#define GPIO_PM11_PM117_SHIFT                   (7u)
+#define GPIO_PM11_PM118_SHIFT                   (8u)
+#define GPIO_PM11_PM119_SHIFT                   (9u)
+#define GPIO_PM11_PM1110_SHIFT                  (10u)
+#define GPIO_PM11_PM1111_SHIFT                  (11u)
+#define GPIO_PM11_PM1112_SHIFT                  (12u)
+#define GPIO_PM11_PM1113_SHIFT                  (13u)
+#define GPIO_PM11_PM1114_SHIFT                  (14u)
+#define GPIO_PM11_PM1115_SHIFT                  (15u)
+
+#define GPIO_PMC11_PMC110_SHIFT                 (0u)
+#define GPIO_PMC11_PMC111_SHIFT                 (1u)
+#define GPIO_PMC11_PMC112_SHIFT                 (2u)
+#define GPIO_PMC11_PMC113_SHIFT                 (3u)
+#define GPIO_PMC11_PMC114_SHIFT                 (4u)
+#define GPIO_PMC11_PMC115_SHIFT                 (5u)
+#define GPIO_PMC11_PMC116_SHIFT                 (6u)
+#define GPIO_PMC11_PMC117_SHIFT                 (7u)
+#define GPIO_PMC11_PMC118_SHIFT                 (8u)
+#define GPIO_PMC11_PMC119_SHIFT                 (9u)
+#define GPIO_PMC11_PMC1110_SHIFT                (10u)
+#define GPIO_PMC11_PMC1111_SHIFT                (11u)
+#define GPIO_PMC11_PMC1112_SHIFT                (12u)
+#define GPIO_PMC11_PMC1113_SHIFT                (13u)
+#define GPIO_PMC11_PMC1114_SHIFT                (14u)
+#define GPIO_PMC11_PMC1115_SHIFT                (15u)
+
+#define GPIO_PFC11_PFC110_SHIFT                 (0u)
+#define GPIO_PFC11_PFC111_SHIFT                 (1u)
+#define GPIO_PFC11_PFC112_SHIFT                 (2u)
+#define GPIO_PFC11_PFC113_SHIFT                 (3u)
+#define GPIO_PFC11_PFC114_SHIFT                 (4u)
+#define GPIO_PFC11_PFC115_SHIFT                 (5u)
+#define GPIO_PFC11_PFC116_SHIFT                 (6u)
+#define GPIO_PFC11_PFC117_SHIFT                 (7u)
+#define GPIO_PFC11_PFC118_SHIFT                 (8u)
+#define GPIO_PFC11_PFC119_SHIFT                 (9u)
+#define GPIO_PFC11_PFC1110_SHIFT                (10u)
+#define GPIO_PFC11_PFC1111_SHIFT                (11u)
+#define GPIO_PFC11_PFC1112_SHIFT                (12u)
+#define GPIO_PFC11_PFC1113_SHIFT                (13u)
+#define GPIO_PFC11_PFC1114_SHIFT                (14u)
+#define GPIO_PFC11_PFC1115_SHIFT                (15u)
+
+#define GPIO_PFCE11_PFCE110_SHIFT               (0u)
+#define GPIO_PFCE11_PFCE111_SHIFT               (1u)
+#define GPIO_PFCE11_PFCE112_SHIFT               (2u)
+#define GPIO_PFCE11_PFCE113_SHIFT               (3u)
+#define GPIO_PFCE11_PFCE114_SHIFT               (4u)
+#define GPIO_PFCE11_PFCE115_SHIFT               (5u)
+#define GPIO_PFCE11_PFCE116_SHIFT               (6u)
+#define GPIO_PFCE11_PFCE117_SHIFT               (7u)
+#define GPIO_PFCE11_PFCE118_SHIFT               (8u)
+#define GPIO_PFCE11_PFCE119_SHIFT               (9u)
+#define GPIO_PFCE11_PFCE1110_SHIFT              (10u)
+#define GPIO_PFCE11_PFCE1111_SHIFT              (11u)
+#define GPIO_PFCE11_PFCE1112_SHIFT              (12u)
+#define GPIO_PFCE11_PFCE1113_SHIFT              (13u)
+#define GPIO_PFCE11_PFCE1114_SHIFT              (14u)
+#define GPIO_PFCE11_PFCE1115_SHIFT              (15u)
+
+#define GPIO_PNOT11_PNOT110_SHIFT               (0u)
+#define GPIO_PNOT11_PNOT111_SHIFT               (1u)
+#define GPIO_PNOT11_PNOT112_SHIFT               (2u)
+#define GPIO_PNOT11_PNOT113_SHIFT               (3u)
+#define GPIO_PNOT11_PNOT114_SHIFT               (4u)
+#define GPIO_PNOT11_PNOT115_SHIFT               (5u)
+#define GPIO_PNOT11_PNOT116_SHIFT               (6u)
+#define GPIO_PNOT11_PNOT117_SHIFT               (7u)
+#define GPIO_PNOT11_PNOT118_SHIFT               (8u)
+#define GPIO_PNOT11_PNOT119_SHIFT               (9u)
+#define GPIO_PNOT11_PNOT1110_SHIFT              (10u)
+#define GPIO_PNOT11_PNOT1111_SHIFT              (11u)
+#define GPIO_PNOT11_PNOT1112_SHIFT              (12u)
+#define GPIO_PNOT11_PNOT1113_SHIFT              (13u)
+#define GPIO_PNOT11_PNOT1114_SHIFT              (14u)
+#define GPIO_PNOT11_PNOT1115_SHIFT              (15u)
+
+#define GPIO_PMSR11_PMSR110_SHIFT               (0u)
+#define GPIO_PMSR11_PMSR111_SHIFT               (1u)
+#define GPIO_PMSR11_PMSR112_SHIFT               (2u)
+#define GPIO_PMSR11_PMSR113_SHIFT               (3u)
+#define GPIO_PMSR11_PMSR114_SHIFT               (4u)
+#define GPIO_PMSR11_PMSR115_SHIFT               (5u)
+#define GPIO_PMSR11_PMSR116_SHIFT               (6u)
+#define GPIO_PMSR11_PMSR117_SHIFT               (7u)
+#define GPIO_PMSR11_PMSR118_SHIFT               (8u)
+#define GPIO_PMSR11_PMSR119_SHIFT               (9u)
+#define GPIO_PMSR11_PMSR1110_SHIFT              (10u)
+#define GPIO_PMSR11_PMSR1111_SHIFT              (11u)
+#define GPIO_PMSR11_PMSR1112_SHIFT              (12u)
+#define GPIO_PMSR11_PMSR1113_SHIFT              (13u)
+#define GPIO_PMSR11_PMSR1114_SHIFT              (14u)
+#define GPIO_PMSR11_PMSR1115_SHIFT              (15u)
+#define GPIO_PMSR11_PMSR1116_SHIFT              (16u)
+#define GPIO_PMSR11_PMSR1117_SHIFT              (17u)
+#define GPIO_PMSR11_PMSR1118_SHIFT              (18u)
+#define GPIO_PMSR11_PMSR1119_SHIFT              (19u)
+#define GPIO_PMSR11_PMSR1120_SHIFT              (20u)
+#define GPIO_PMSR11_PMSR1121_SHIFT              (21u)
+#define GPIO_PMSR11_PMSR1122_SHIFT              (22u)
+#define GPIO_PMSR11_PMSR1123_SHIFT              (23u)
+#define GPIO_PMSR11_PMSR1124_SHIFT              (24u)
+#define GPIO_PMSR11_PMSR1125_SHIFT              (25u)
+#define GPIO_PMSR11_PMSR1126_SHIFT              (26u)
+#define GPIO_PMSR11_PMSR1127_SHIFT              (27u)
+#define GPIO_PMSR11_PMSR1128_SHIFT              (28u)
+#define GPIO_PMSR11_PMSR1129_SHIFT              (29u)
+#define GPIO_PMSR11_PMSR1130_SHIFT              (30u)
+#define GPIO_PMSR11_PMSR1131_SHIFT              (31u)
+
+#define GPIO_PMCSR11_PMCSR110_SHIFT             (0u)
+#define GPIO_PMCSR11_PMCSR111_SHIFT             (1u)
+#define GPIO_PMCSR11_PMCSR112_SHIFT             (2u)
+#define GPIO_PMCSR11_PMCSR113_SHIFT             (3u)
+#define GPIO_PMCSR11_PMCSR114_SHIFT             (4u)
+#define GPIO_PMCSR11_PMCSR115_SHIFT             (5u)
+#define GPIO_PMCSR11_PMCSR116_SHIFT             (6u)
+#define GPIO_PMCSR11_PMCSR117_SHIFT             (7u)
+#define GPIO_PMCSR11_PMCSR118_SHIFT             (8u)
+#define GPIO_PMCSR11_PMCSR119_SHIFT             (9u)
+#define GPIO_PMCSR11_PMCSR1110_SHIFT            (10u)
+#define GPIO_PMCSR11_PMCSR1111_SHIFT            (11u)
+#define GPIO_PMCSR11_PMCSR1112_SHIFT            (12u)
+#define GPIO_PMCSR11_PMCSR1113_SHIFT            (13u)
+#define GPIO_PMCSR11_PMCSR1114_SHIFT            (14u)
+#define GPIO_PMCSR11_PMCSR1115_SHIFT            (15u)
+#define GPIO_PMCSR11_PMCSR1116_SHIFT            (16u)
+#define GPIO_PMCSR11_PMCSR1117_SHIFT            (17u)
+#define GPIO_PMCSR11_PMCSR1118_SHIFT            (18u)
+#define GPIO_PMCSR11_PMCSR1119_SHIFT            (19u)
+#define GPIO_PMCSR11_PMCSR1120_SHIFT            (20u)
+#define GPIO_PMCSR11_PMCSR1121_SHIFT            (21u)
+#define GPIO_PMCSR11_PMCSR1122_SHIFT            (22u)
+#define GPIO_PMCSR11_PMCSR1123_SHIFT            (23u)
+#define GPIO_PMCSR11_PMCSR1124_SHIFT            (24u)
+#define GPIO_PMCSR11_PMCSR1125_SHIFT            (25u)
+#define GPIO_PMCSR11_PMCSR1126_SHIFT            (26u)
+#define GPIO_PMCSR11_PMCSR1127_SHIFT            (27u)
+#define GPIO_PMCSR11_PMCSR1128_SHIFT            (28u)
+#define GPIO_PMCSR11_PMCSR1129_SHIFT            (29u)
+#define GPIO_PMCSR11_PMCSR1130_SHIFT            (30u)
+#define GPIO_PMCSR11_PMCSR1131_SHIFT            (31u)
+
+#define GPIO_PFCAE11_PFCAE110_SHIFT             (0u)
+#define GPIO_PFCAE11_PFCAE111_SHIFT             (1u)
+#define GPIO_PFCAE11_PFCAE112_SHIFT             (2u)
+#define GPIO_PFCAE11_PFCAE113_SHIFT             (3u)
+#define GPIO_PFCAE11_PFCAE114_SHIFT             (4u)
+#define GPIO_PFCAE11_PFCAE115_SHIFT             (5u)
+#define GPIO_PFCAE11_PFCAE116_SHIFT             (6u)
+#define GPIO_PFCAE11_PFCAE117_SHIFT             (7u)
+#define GPIO_PFCAE11_PFCAE118_SHIFT             (8u)
+#define GPIO_PFCAE11_PFCAE119_SHIFT             (9u)
+#define GPIO_PFCAE11_PFCAE1110_SHIFT            (10u)
+#define GPIO_PFCAE11_PFCAE1111_SHIFT            (11u)
+#define GPIO_PFCAE11_PFCAE1112_SHIFT            (12u)
+#define GPIO_PFCAE11_PFCAE1113_SHIFT            (13u)
+#define GPIO_PFCAE11_PFCAE1114_SHIFT            (14u)
+#define GPIO_PFCAE11_PFCAE1115_SHIFT            (15u)
+
+#define GPIO_PIBC11_PIBC110_SHIFT               (0u)
+#define GPIO_PIBC11_PIBC111_SHIFT               (1u)
+#define GPIO_PIBC11_PIBC112_SHIFT               (2u)
+#define GPIO_PIBC11_PIBC113_SHIFT               (3u)
+#define GPIO_PIBC11_PIBC114_SHIFT               (4u)
+#define GPIO_PIBC11_PIBC115_SHIFT               (5u)
+#define GPIO_PIBC11_PIBC116_SHIFT               (6u)
+#define GPIO_PIBC11_PIBC117_SHIFT               (7u)
+#define GPIO_PIBC11_PIBC118_SHIFT               (8u)
+#define GPIO_PIBC11_PIBC119_SHIFT               (9u)
+#define GPIO_PIBC11_PIBC1110_SHIFT              (10u)
+#define GPIO_PIBC11_PIBC1111_SHIFT              (11u)
+#define GPIO_PIBC11_PIBC1112_SHIFT              (12u)
+#define GPIO_PIBC11_PIBC1113_SHIFT              (13u)
+#define GPIO_PIBC11_PIBC1114_SHIFT              (14u)
+#define GPIO_PIBC11_PIBC1115_SHIFT              (15u)
+
+#define GPIO_PBDC11_PBDC110_SHIFT               (0u)
+#define GPIO_PBDC11_PBDC111_SHIFT               (1u)
+#define GPIO_PBDC11_PBDC112_SHIFT               (2u)
+#define GPIO_PBDC11_PBDC113_SHIFT               (3u)
+#define GPIO_PBDC11_PBDC114_SHIFT               (4u)
+#define GPIO_PBDC11_PBDC115_SHIFT               (5u)
+#define GPIO_PBDC11_PBDC116_SHIFT               (6u)
+#define GPIO_PBDC11_PBDC117_SHIFT               (7u)
+#define GPIO_PBDC11_PBDC118_SHIFT               (8u)
+#define GPIO_PBDC11_PBDC119_SHIFT               (9u)
+#define GPIO_PBDC11_PBDC1110_SHIFT              (10u)
+#define GPIO_PBDC11_PBDC1111_SHIFT              (11u)
+#define GPIO_PBDC11_PBDC1112_SHIFT              (12u)
+#define GPIO_PBDC11_PBDC1113_SHIFT              (13u)
+#define GPIO_PBDC11_PBDC1114_SHIFT              (14u)
+#define GPIO_PBDC11_PBDC1115_SHIFT              (15u)
+
+#define GPIO_PIPC11_PIPC110_SHIFT               (0u)
+#define GPIO_PIPC11_PIPC111_SHIFT               (1u)
+#define GPIO_PIPC11_PIPC112_SHIFT               (2u)
+#define GPIO_PIPC11_PIPC113_SHIFT               (3u)
+#define GPIO_PIPC11_PIPC114_SHIFT               (4u)
+#define GPIO_PIPC11_PIPC115_SHIFT               (5u)
+#define GPIO_PIPC11_PIPC116_SHIFT               (6u)
+#define GPIO_PIPC11_PIPC117_SHIFT               (7u)
+#define GPIO_PIPC11_PIPC118_SHIFT               (8u)
+#define GPIO_PIPC11_PIPC119_SHIFT               (9u)
+#define GPIO_PIPC11_PIPC1110_SHIFT              (10u)
+#define GPIO_PIPC11_PIPC1111_SHIFT              (11u)
+#define GPIO_PIPC11_PIPC1112_SHIFT              (12u)
+#define GPIO_PIPC11_PIPC1113_SHIFT              (13u)
+#define GPIO_PIPC11_PIPC1114_SHIFT              (14u)
+#define GPIO_PIPC11_PIPC1115_SHIFT              (15u)
+
+
+#endif /* GPIO_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h	(revision 374)
@@ -0,0 +1,11236 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : intc_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : INTC register define header
+*******************************************************************************/
+#ifndef INTC_IOBITMASK_H
+#define INTC_IOBITMASK_H
+
+/* ==== Mask values for IO registers ==== */
+#define INTC_ICDDCR_Enable                      (0x00000001uL)
+
+#define INTC_ICDICTR_ITLinesNumber              (0x0000001FuL)
+#define INTC_ICDICTR_CPUNumber                  (0x000000E0uL)
+#define INTC_ICDICTR_SecurityExtn               (0x00000400uL)
+#define INTC_ICDICTR_LSPI                       (0x0000F800uL)
+
+#define INTC_ICDIIDR_Implementer                (0x00000FFFuL)
+#define INTC_ICDIIDR_Revision                   (0x0000F000uL)
+#define INTC_ICDIIDR_Variant                    (0x000F0000uL)
+#define INTC_ICDIIDR_ProductID                  (0xFF000000uL)
+
+#define INTC_ICDISR0_SW0                        (0x00000001uL)
+#define INTC_ICDISR0_SW1                        (0x00000002uL)
+#define INTC_ICDISR0_SW2                        (0x00000004uL)
+#define INTC_ICDISR0_SW3                        (0x00000008uL)
+#define INTC_ICDISR0_SW4                        (0x00000010uL)
+#define INTC_ICDISR0_SW5                        (0x00000020uL)
+#define INTC_ICDISR0_SW6                        (0x00000040uL)
+#define INTC_ICDISR0_SW7                        (0x00000080uL)
+#define INTC_ICDISR0_SW8                        (0x00000100uL)
+#define INTC_ICDISR0_SW9                        (0x00000200uL)
+#define INTC_ICDISR0_SW10                       (0x00000400uL)
+#define INTC_ICDISR0_SW11                       (0x00000800uL)
+#define INTC_ICDISR0_SW12                       (0x00001000uL)
+#define INTC_ICDISR0_SW13                       (0x00002000uL)
+#define INTC_ICDISR0_SW14                       (0x00004000uL)
+#define INTC_ICDISR0_SW15                       (0x00008000uL)
+#define INTC_ICDISR0_PMUIRQ0                    (0x00010000uL)
+#define INTC_ICDISR0_COMMRX0                    (0x00020000uL)
+#define INTC_ICDISR0_COMMTX0                    (0x00040000uL)
+#define INTC_ICDISR0_CTIIRQ0                    (0x00080000uL)
+
+#define INTC_ICDISR1_IRQ0                       (0x00000001uL)
+#define INTC_ICDISR1_IRQ1                       (0x00000002uL)
+#define INTC_ICDISR1_IRQ2                       (0x00000004uL)
+#define INTC_ICDISR1_IRQ3                       (0x00000008uL)
+#define INTC_ICDISR1_IRQ4                       (0x00000010uL)
+#define INTC_ICDISR1_IRQ5                       (0x00000020uL)
+#define INTC_ICDISR1_IRQ6                       (0x00000040uL)
+#define INTC_ICDISR1_IRQ7                       (0x00000080uL)
+#define INTC_ICDISR1_PL310ERR                   (0x00000100uL)
+#define INTC_ICDISR1_DMAINT0                    (0x00000200uL)
+#define INTC_ICDISR1_DMAINT1                    (0x00000400uL)
+#define INTC_ICDISR1_DMAINT2                    (0x00000800uL)
+#define INTC_ICDISR1_DMAINT3                    (0x00001000uL)
+#define INTC_ICDISR1_DMAINT4                    (0x00002000uL)
+#define INTC_ICDISR1_DMAINT5                    (0x00004000uL)
+#define INTC_ICDISR1_DMAINT6                    (0x00008000uL)
+#define INTC_ICDISR1_DMAINT7                    (0x00010000uL)
+#define INTC_ICDISR1_DMAINT8                    (0x00020000uL)
+#define INTC_ICDISR1_DMAINT9                    (0x00040000uL)
+#define INTC_ICDISR1_DMAINT10                   (0x00080000uL)
+#define INTC_ICDISR1_DMAINT11                   (0x00100000uL)
+#define INTC_ICDISR1_DMAINT12                   (0x00200000uL)
+#define INTC_ICDISR1_DMAINT13                   (0x00400000uL)
+#define INTC_ICDISR1_DMAINT14                   (0x00800000uL)
+#define INTC_ICDISR1_DMAINT15                   (0x01000000uL)
+#define INTC_ICDISR1_DMAERR                     (0x02000000uL)
+
+#define INTC_ICDISR2_USBI0                      (0x00000200uL)
+#define INTC_ICDISR2_USBI1                      (0x00000400uL)
+#define INTC_ICDISR2_S0_VI_VSYNC0               (0x00000800uL)
+#define INTC_ICDISR2_S0_LO_VSYNC0               (0x00001000uL)
+#define INTC_ICDISR2_S0_VSYNCERR0               (0x00002000uL)
+#define INTC_ICDISR2_GR3_VLINE0                 (0x00004000uL)
+#define INTC_ICDISR2_S0_VFIELD0                 (0x00008000uL)
+#define INTC_ICDISR2_IV1_VBUFERR0               (0x00010000uL)
+#define INTC_ICDISR2_IV3_VBUFERR0               (0x00020000uL)
+#define INTC_ICDISR2_IV5_VBUFERR0               (0x00040000uL)
+#define INTC_ICDISR2_IV6_VBUFERR0               (0x00080000uL)
+#define INTC_ICDISR2_S0_WLINE0                  (0x00100000uL)
+#define INTC_ICDISR2_S1_VI_VSYNC0               (0x00200000uL)
+#define INTC_ICDISR2_S1_LO_VSYNC0               (0x00400000uL)
+#define INTC_ICDISR2_S1_VSYNCERR0               (0x00800000uL)
+#define INTC_ICDISR2_S1_VFIELD0                 (0x01000000uL)
+#define INTC_ICDISR2_IV2_VBUFERR0               (0x02000000uL)
+#define INTC_ICDISR2_IV4_VBUFERR0               (0x04000000uL)
+#define INTC_ICDISR2_S1_WLINE0                  (0x08000000uL)
+#define INTC_ICDISR2_OIR_VI_VSYNC0              (0x10000000uL)
+#define INTC_ICDISR2_OIR_LO_VSYNC0              (0x20000000uL)
+#define INTC_ICDISR2_OIR_VSYNCERR0              (0x40000000uL)
+#define INTC_ICDISR2_OIR_VFIELD0                (0x80000000uL)
+
+#define INTC_ICDISR3_IV7_VBUFERR0               (0x00000001uL)
+#define INTC_ICDISR3_IV8_VBUFERR0               (0x00000002uL)
+#define INTC_ICDISR3_S0_VI_VSYNC1               (0x00000008uL)
+#define INTC_ICDISR3_S0_LO_VSYNC1               (0x00000010uL)
+#define INTC_ICDISR3_S0_VSYNCERR1               (0x00000020uL)
+#define INTC_ICDISR3_GR3_VLINE1                 (0x00000040uL)
+#define INTC_ICDISR3_S0_VFIELD1                 (0x00000080uL)
+#define INTC_ICDISR3_IV1_VBUFERR1               (0x00000100uL)
+#define INTC_ICDISR3_IV3_VBUFERR1               (0x00000200uL)
+#define INTC_ICDISR3_IV5_VBUFERR1               (0x00000400uL)
+#define INTC_ICDISR3_IV6_VBUFERR1               (0x00000800uL)
+#define INTC_ICDISR3_S0_WLINE1                  (0x00001000uL)
+#define INTC_ICDISR3_S1_VI_VSYNC1               (0x00002000uL)
+#define INTC_ICDISR3_S1_LO_VSYNC1               (0x00004000uL)
+#define INTC_ICDISR3_S1_VSYNCERR1               (0x00008000uL)
+#define INTC_ICDISR3_S1_VFIELD1                 (0x00010000uL)
+#define INTC_ICDISR3_IV2_VBUFERR1               (0x00020000uL)
+#define INTC_ICDISR3_IV4_VBUFERR1               (0x00040000uL)
+#define INTC_ICDISR3_S1_WLINE1                  (0x00080000uL)
+#define INTC_ICDISR3_OIR_VI_VSYNC1              (0x00100000uL)
+#define INTC_ICDISR3_OIR_LO_VSYNC1              (0x00200000uL)
+#define INTC_ICDISR3_OIR_VLINE1                 (0x00400000uL)
+#define INTC_ICDISR3_OIR_VFIELD1                (0x00800000uL)
+#define INTC_ICDISR3_IV7_VBUFERR1               (0x01000000uL)
+#define INTC_ICDISR3_IV8_VBUFERR1               (0x02000000uL)
+#define INTC_ICDISR3_IMRDI                      (0x08000000uL)
+#define INTC_ICDISR3_IMR2I0                     (0x10000000uL)
+#define INTC_ICDISR3_IMR2I1                     (0x20000000uL)
+#define INTC_ICDISR3_JEDI                       (0x40000000uL)
+#define INTC_ICDISR3_JDTI                       (0x80000000uL)
+
+#define INTC_ICDISR4_CMP0                       (0x00000001uL)
+#define INTC_ICDISR4_CMP1                       (0x00000002uL)
+#define INTC_ICDISR4_INT0                       (0x00000004uL)
+#define INTC_ICDISR4_INT1                       (0x00000008uL)
+#define INTC_ICDISR4_INT2                       (0x00000010uL)
+#define INTC_ICDISR4_INT3                       (0x00000020uL)
+#define INTC_ICDISR4_OSTM0TINT                  (0x00000040uL)
+#define INTC_ICDISR4_OSTM1TINT                  (0x00000080uL)
+#define INTC_ICDISR4_CMI                        (0x00000100uL)
+#define INTC_ICDISR4_WTOUT                      (0x00000200uL)
+#define INTC_ICDISR4_ITI                        (0x00000400uL)
+#define INTC_ICDISR4_TGI0A                      (0x00000800uL)
+#define INTC_ICDISR4_TGI0B                      (0x00001000uL)
+#define INTC_ICDISR4_TGI0C                      (0x00002000uL)
+#define INTC_ICDISR4_TGI0D                      (0x00004000uL)
+#define INTC_ICDISR4_TGI0V                      (0x00008000uL)
+#define INTC_ICDISR4_TGI0E                      (0x00010000uL)
+#define INTC_ICDISR4_TGI0F                      (0x00020000uL)
+#define INTC_ICDISR4_TGI1A                      (0x00040000uL)
+#define INTC_ICDISR4_TGI1B                      (0x00080000uL)
+#define INTC_ICDISR4_TGI1V                      (0x00100000uL)
+#define INTC_ICDISR4_TGI1U                      (0x00200000uL)
+#define INTC_ICDISR4_TGI2A                      (0x00400000uL)
+#define INTC_ICDISR4_TGI2B                      (0x00800000uL)
+#define INTC_ICDISR4_TGI2V                      (0x01000000uL)
+#define INTC_ICDISR4_TGI2U                      (0x02000000uL)
+#define INTC_ICDISR4_TGI3A                      (0x04000000uL)
+#define INTC_ICDISR4_TGI3B                      (0x08000000uL)
+#define INTC_ICDISR4_TGI3C                      (0x10000000uL)
+#define INTC_ICDISR4_TGI3D                      (0x20000000uL)
+#define INTC_ICDISR4_TGI3V                      (0x40000000uL)
+#define INTC_ICDISR4_TGI4A                      (0x80000000uL)
+
+#define INTC_ICDISR5_TGI4B                      (0x00000001uL)
+#define INTC_ICDISR5_TGI4C                      (0x00000002uL)
+#define INTC_ICDISR5_TGI4D                      (0x00000004uL)
+#define INTC_ICDISR5_TGI4V                      (0x00000008uL)
+#define INTC_ICDISR5_CMI1                       (0x00000010uL)
+#define INTC_ICDISR5_CMI2                       (0x00000020uL)
+#define INTC_ICDISR5_SGDEI0                     (0x00000040uL)
+#define INTC_ICDISR5_SGDEI1                     (0x00000080uL)
+#define INTC_ICDISR5_SGDEI2                     (0x00000100uL)
+#define INTC_ICDISR5_SGDEI3                     (0x00000200uL)
+#define INTC_ICDISR5_ADI                        (0x00000400uL)
+#define INTC_ICDISR5_LMTI                       (0x00000800uL)
+#define INTC_ICDISR5_SSII0                      (0x00001000uL)
+#define INTC_ICDISR5_SSIRXI0                    (0x00002000uL)
+#define INTC_ICDISR5_SSITXI0                    (0x00004000uL)
+#define INTC_ICDISR5_SSII1                      (0x00008000uL)
+#define INTC_ICDISR5_SSIRXI1                    (0x00010000uL)
+#define INTC_ICDISR5_SSITXI1                    (0x00020000uL)
+#define INTC_ICDISR5_SSII2                      (0x00040000uL)
+#define INTC_ICDISR5_SSIRTI2                    (0x00080000uL)
+#define INTC_ICDISR5_SSII3                      (0x00100000uL)
+#define INTC_ICDISR5_SSIRXI3                    (0x00200000uL)
+#define INTC_ICDISR5_SSITXI3                    (0x00400000uL)
+#define INTC_ICDISR5_SSII4                      (0x00800000uL)
+#define INTC_ICDISR5_SSIRTI4                    (0x01000000uL)
+#define INTC_ICDISR5_SSII5                      (0x02000000uL)
+#define INTC_ICDISR5_SSIRXI5                    (0x04000000uL)
+#define INTC_ICDISR5_SSITXI5                    (0x08000000uL)
+#define INTC_ICDISR5_SPDIFI                     (0x10000000uL)
+#define INTC_ICDISR5_INTIICTEI0                 (0x20000000uL)
+#define INTC_ICDISR5_INTIICRI0                  (0x40000000uL)
+#define INTC_ICDISR5_INTIICTI0                  (0x80000000uL)
+
+#define INTC_ICDISR6_INTIICSPI0                 (0x00000001uL)
+#define INTC_ICDISR6_INTIICSTI0                 (0x00000002uL)
+#define INTC_ICDISR6_INTIICNAKI0                (0x00000004uL)
+#define INTC_ICDISR6_INTIICALI0                 (0x00000008uL)
+#define INTC_ICDISR6_INTIICTMOI0                (0x00000010uL)
+#define INTC_ICDISR6_INTIICTEI1                 (0x00000020uL)
+#define INTC_ICDISR6_INTIICRI1                  (0x00000040uL)
+#define INTC_ICDISR6_INTIICTI1                  (0x00000080uL)
+#define INTC_ICDISR6_INTIICSPI1                 (0x00000100uL)
+#define INTC_ICDISR6_INTIICSTI1                 (0x00000200uL)
+#define INTC_ICDISR6_INTIICNAKI1                (0x00000400uL)
+#define INTC_ICDISR6_INTIICALI1                 (0x00000800uL)
+#define INTC_ICDISR6_INTIICTMOI1                (0x00001000uL)
+#define INTC_ICDISR6_INTIICTEI2                 (0x00002000uL)
+#define INTC_ICDISR6_INTIICRI2                  (0x00004000uL)
+#define INTC_ICDISR6_INTIICTI2                  (0x00008000uL)
+#define INTC_ICDISR6_INTIICSPI2                 (0x00010000uL)
+#define INTC_ICDISR6_INTIICSTI2                 (0x00020000uL)
+#define INTC_ICDISR6_INTIICNAKI2                (0x00040000uL)
+#define INTC_ICDISR6_INTIICALI2                 (0x00080000uL)
+#define INTC_ICDISR6_INTIICTMOI2                (0x00100000uL)
+#define INTC_ICDISR6_INTIICTEI3                 (0x00200000uL)
+#define INTC_ICDISR6_INTIICRI3                  (0x00400000uL)
+#define INTC_ICDISR6_INTIICTI3                  (0x00800000uL)
+#define INTC_ICDISR6_INTIICSPI3                 (0x01000000uL)
+#define INTC_ICDISR6_INTIICSTI3                 (0x02000000uL)
+#define INTC_ICDISR6_INTIICNAKI3                (0x04000000uL)
+#define INTC_ICDISR6_INTIICALI3                 (0x08000000uL)
+#define INTC_ICDISR6_INTIICTMOI3                (0x10000000uL)
+#define INTC_ICDISR6_BRI0                       (0x20000000uL)
+#define INTC_ICDISR6_ERI0                       (0x40000000uL)
+#define INTC_ICDISR6_RXI0                       (0x80000000uL)
+
+#define INTC_ICDISR7_TXI0                       (0x00000001uL)
+#define INTC_ICDISR7_BRI1                       (0x00000002uL)
+#define INTC_ICDISR7_ERI1                       (0x00000004uL)
+#define INTC_ICDISR7_RXI1                       (0x00000008uL)
+#define INTC_ICDISR7_TXI1                       (0x00000010uL)
+#define INTC_ICDISR7_BRI2                       (0x00000020uL)
+#define INTC_ICDISR7_ERI2                       (0x00000040uL)
+#define INTC_ICDISR7_RXI2                       (0x00000080uL)
+#define INTC_ICDISR7_TXI2                       (0x00000100uL)
+#define INTC_ICDISR7_BRI3                       (0x00000200uL)
+#define INTC_ICDISR7_ERI3                       (0x00000400uL)
+#define INTC_ICDISR7_RXI3                       (0x00000800uL)
+#define INTC_ICDISR7_TXI3                       (0x00001000uL)
+#define INTC_ICDISR7_BRI4                       (0x00002000uL)
+#define INTC_ICDISR7_ERI4                       (0x00004000uL)
+#define INTC_ICDISR7_RXI4                       (0x00008000uL)
+#define INTC_ICDISR7_TXI4                       (0x00010000uL)
+#define INTC_ICDISR7_BRI5                       (0x00020000uL)
+#define INTC_ICDISR7_ERI5                       (0x00040000uL)
+#define INTC_ICDISR7_RXI5                       (0x00080000uL)
+#define INTC_ICDISR7_TXI5                       (0x00100000uL)
+#define INTC_ICDISR7_BRI6                       (0x00200000uL)
+#define INTC_ICDISR7_ERI6                       (0x00400000uL)
+#define INTC_ICDISR7_RXI6                       (0x00800000uL)
+#define INTC_ICDISR7_TXI6                       (0x01000000uL)
+#define INTC_ICDISR7_BRI7                       (0x02000000uL)
+#define INTC_ICDISR7_ERI7                       (0x04000000uL)
+#define INTC_ICDISR7_RXI7                       (0x08000000uL)
+#define INTC_ICDISR7_TXI7                       (0x10000000uL)
+#define INTC_ICDISR7_INTRCANGERR                (0x20000000uL)
+#define INTC_ICDISR7_INTRCANGRECC               (0x40000000uL)
+#define INTC_ICDISR7_INTRCAN0REC                (0x80000000uL)
+
+#define INTC_ICDISR8_INTRCAN0ERR                (0x00000001uL)
+#define INTC_ICDISR8_INTRCAN0TRX                (0x00000002uL)
+#define INTC_ICDISR8_INTRCAN1REC                (0x00000004uL)
+#define INTC_ICDISR8_INTRCAN1ERR                (0x00000008uL)
+#define INTC_ICDISR8_INTRCAN1TRX                (0x00000010uL)
+#define INTC_ICDISR8_INTRCAN2REC                (0x00000020uL)
+#define INTC_ICDISR8_INTRCAN2ERR                (0x00000040uL)
+#define INTC_ICDISR8_INTRCAN2TRX                (0x00000080uL)
+#define INTC_ICDISR8_INTRCAN3REC                (0x00000100uL)
+#define INTC_ICDISR8_INTRCAN3ERR                (0x00000200uL)
+#define INTC_ICDISR8_INTRCAN3TRX                (0x00000400uL)
+#define INTC_ICDISR8_INTRCAN4REC                (0x00000800uL)
+#define INTC_ICDISR8_INTRCAN4ERR                (0x00001000uL)
+#define INTC_ICDISR8_INTRCAN4TRX                (0x00002000uL)
+#define INTC_ICDISR8_SPEI0                      (0x00004000uL)
+#define INTC_ICDISR8_SPRI0                      (0x00008000uL)
+#define INTC_ICDISR8_SPTI0                      (0x00010000uL)
+#define INTC_ICDISR8_SPEI1                      (0x00020000uL)
+#define INTC_ICDISR8_SPRI1                      (0x00040000uL)
+#define INTC_ICDISR8_SPTI1                      (0x00080000uL)
+#define INTC_ICDISR8_SPEI2                      (0x00100000uL)
+#define INTC_ICDISR8_SPRI2                      (0x00200000uL)
+#define INTC_ICDISR8_SPTI2                      (0x00400000uL)
+#define INTC_ICDISR8_SPEI3                      (0x00800000uL)
+#define INTC_ICDISR8_SPRI3                      (0x01000000uL)
+#define INTC_ICDISR8_SPTI3                      (0x02000000uL)
+#define INTC_ICDISR8_SPEI4                      (0x04000000uL)
+#define INTC_ICDISR8_SPRI4                      (0x08000000uL)
+#define INTC_ICDISR8_SPTI4                      (0x10000000uL)
+#define INTC_ICDISR8_IEBBTD                     (0x20000000uL)
+#define INTC_ICDISR8_IEBBTERR                   (0x40000000uL)
+#define INTC_ICDISR8_IEBBTSTA                   (0x80000000uL)
+
+#define INTC_ICDISR9_IEBBTV                     (0x00000001uL)
+#define INTC_ICDISR9_ISY                        (0x00000002uL)
+#define INTC_ICDISR9_IERR                       (0x00000004uL)
+#define INTC_ICDISR9_ITARG                      (0x00000008uL)
+#define INTC_ICDISR9_ISEC                       (0x00000010uL)
+#define INTC_ICDISR9_IBUF                       (0x00000020uL)
+#define INTC_ICDISR9_IREADY                     (0x00000040uL)
+#define INTC_ICDISR9_FLSTE                      (0x00000080uL)
+#define INTC_ICDISR9_FLTENDI                    (0x00000100uL)
+#define INTC_ICDISR9_FLTREQ0I                   (0x00000200uL)
+#define INTC_ICDISR9_FLTREQ1I                   (0x00000400uL)
+#define INTC_ICDISR9_MMC0                       (0x00000800uL)
+#define INTC_ICDISR9_MMC1                       (0x00001000uL)
+#define INTC_ICDISR9_MMC2                       (0x00002000uL)
+#define INTC_ICDISR9_SDHI0_3                    (0x00004000uL)
+#define INTC_ICDISR9_SDHI0_0                    (0x00008000uL)
+#define INTC_ICDISR9_SDHI0_1                    (0x00010000uL)
+#define INTC_ICDISR9_SDHI1_3                    (0x00020000uL)
+#define INTC_ICDISR9_SDHI1_0                    (0x00040000uL)
+#define INTC_ICDISR9_SDHI1_1                    (0x00080000uL)
+#define INTC_ICDISR9_ARM                        (0x00100000uL)
+#define INTC_ICDISR9_PRD                        (0x00200000uL)
+#define INTC_ICDISR9_CUP                        (0x00400000uL)
+#define INTC_ICDISR9_SCUAI0                     (0x00800000uL)
+#define INTC_ICDISR9_SCUAI1                     (0x01000000uL)
+#define INTC_ICDISR9_SCUFDI0                    (0x02000000uL)
+#define INTC_ICDISR9_SCUFDI1                    (0x04000000uL)
+#define INTC_ICDISR9_SCUFDI2                    (0x08000000uL)
+#define INTC_ICDISR9_SCUFDI3                    (0x10000000uL)
+#define INTC_ICDISR9_SCUFUI0                    (0x20000000uL)
+#define INTC_ICDISR9_SCUFUI1                    (0x40000000uL)
+#define INTC_ICDISR9_SCUFUI2                    (0x80000000uL)
+
+#define INTC_ICDISR10_SCUFUI3                   (0x00000001uL)
+#define INTC_ICDISR10_SCUDVI0                   (0x00000002uL)
+#define INTC_ICDISR10_SCUDVI1                   (0x00000004uL)
+#define INTC_ICDISR10_SCUDVI2                   (0x00000008uL)
+#define INTC_ICDISR10_SCUDVI3                   (0x00000010uL)
+#define INTC_ICDISR10_MLB_CINT                  (0x00000020uL)
+#define INTC_ICDISR10_MLB_SINT                  (0x00000040uL)
+#define INTC_ICDISR10_DRC0                      (0x00000080uL)
+#define INTC_ICDISR10_DRC1                      (0x00000100uL)
+#define INTC_ICDISR10_LINI0_INT_T               (0x00000800uL)
+#define INTC_ICDISR10_LINI0_INT_R               (0x00001000uL)
+#define INTC_ICDISR10_LINI0_INT_S               (0x00002000uL)
+#define INTC_ICDISR10_LINI0_INT_M               (0x00004000uL)
+#define INTC_ICDISR10_LINI1_INT_T               (0x00008000uL)
+#define INTC_ICDISR10_LINI1_INT_R               (0x00010000uL)
+#define INTC_ICDISR10_LINI1_INT_S               (0x00020000uL)
+#define INTC_ICDISR10_LINI1_INT_M               (0x00040000uL)
+#define INTC_ICDISR10_ERI0                      (0x08000000uL)
+#define INTC_ICDISR10_RXI0                      (0x10000000uL)
+#define INTC_ICDISR10_TXI0                      (0x20000000uL)
+#define INTC_ICDISR10_TEI0                      (0x40000000uL)
+#define INTC_ICDISR10_ERI1                      (0x80000000uL)
+
+#define INTC_ICDISR11_RXI1                      (0x00000001uL)
+#define INTC_ICDISR11_TXI1                      (0x00000002uL)
+#define INTC_ICDISR11_TEI1                      (0x00000004uL)
+#define INTC_ICDISR11_AVBI_DATA                 (0x00000008uL)
+#define INTC_ICDISR11_AVBI_ERROR                (0x00000010uL)
+#define INTC_ICDISR11_AVBI_MANAGE               (0x00000020uL)
+#define INTC_ICDISR11_AVBI_MAC                  (0x00000040uL)
+#define INTC_ICDISR11_ETHERI                    (0x00000080uL)
+#define INTC_ICDISR11_CEUI                      (0x00001000uL)
+#define INTC_ICDISR11_H2XMLB_ERRINT             (0x20000000uL)
+#define INTC_ICDISR11_H2XIC1_ERRINT             (0x40000000uL)
+#define INTC_ICDISR11_X2HPERI1_ERRINT           (0x80000000uL)
+
+#define INTC_ICDISR12_X2HPERI2_ERRINT           (0x00000001uL)
+#define INTC_ICDISR12_X2HPERI34_ERRINT          (0x00000002uL)
+#define INTC_ICDISR12_X2HPERI5_ERRINT           (0x00000004uL)
+#define INTC_ICDISR12_X2HPERI67_ERRINT          (0x00000008uL)
+#define INTC_ICDISR12_X2HDBGR_ERRINT            (0x00000010uL)
+#define INTC_ICDISR12_X2HBSC_ERRINT             (0x00000020uL)
+#define INTC_ICDISR12_X2HSPI1_ERRINT            (0x00000040uL)
+#define INTC_ICDISR12_X2HSPI2_ERRINT            (0x00000080uL)
+#define INTC_ICDISR12_PRRI                      (0x00000100uL)
+#define INTC_ICDISR12_IFEI0                     (0x00000200uL)
+#define INTC_ICDISR12_OFFI0                     (0x00000400uL)
+#define INTC_ICDISR12_PFVEI0                    (0x00000800uL)
+#define INTC_ICDISR12_IFEI1                     (0x00001000uL)
+#define INTC_ICDISR12_OFFI1                     (0x00002000uL)
+#define INTC_ICDISR12_PFVEI1                    (0x00004000uL)
+
+#define INTC_ICDISR13_TINT0                     (0x00000001uL)
+#define INTC_ICDISR13_TINT1                     (0x00000002uL)
+#define INTC_ICDISR13_TINT2                     (0x00000004uL)
+#define INTC_ICDISR13_TINT3                     (0x00000008uL)
+#define INTC_ICDISR13_TINT4                     (0x00000010uL)
+#define INTC_ICDISR13_TINT5                     (0x00000020uL)
+#define INTC_ICDISR13_TINT6                     (0x00000040uL)
+#define INTC_ICDISR13_TINT7                     (0x00000080uL)
+#define INTC_ICDISR13_TINT8                     (0x00000100uL)
+#define INTC_ICDISR13_TINT9                     (0x00000200uL)
+#define INTC_ICDISR13_TINT10                    (0x00000400uL)
+#define INTC_ICDISR13_TINT11                    (0x00000800uL)
+#define INTC_ICDISR13_TINT12                    (0x00001000uL)
+#define INTC_ICDISR13_TINT13                    (0x00002000uL)
+#define INTC_ICDISR13_TINT14                    (0x00004000uL)
+#define INTC_ICDISR13_TINT15                    (0x00008000uL)
+#define INTC_ICDISR13_TINT16                    (0x00010000uL)
+#define INTC_ICDISR13_TINT17                    (0x00020000uL)
+#define INTC_ICDISR13_TINT18                    (0x00040000uL)
+#define INTC_ICDISR13_TINT19                    (0x00080000uL)
+#define INTC_ICDISR13_TINT20                    (0x00100000uL)
+#define INTC_ICDISR13_TINT21                    (0x00200000uL)
+#define INTC_ICDISR13_TINT22                    (0x00400000uL)
+#define INTC_ICDISR13_TINT23                    (0x00800000uL)
+#define INTC_ICDISR13_TINT24                    (0x01000000uL)
+#define INTC_ICDISR13_TINT25                    (0x02000000uL)
+#define INTC_ICDISR13_TINT26                    (0x04000000uL)
+#define INTC_ICDISR13_TINT27                    (0x08000000uL)
+#define INTC_ICDISR13_TINT28                    (0x10000000uL)
+#define INTC_ICDISR13_TINT29                    (0x20000000uL)
+#define INTC_ICDISR13_TINT30                    (0x40000000uL)
+#define INTC_ICDISR13_TINT31                    (0x80000000uL)
+
+#define INTC_ICDISR14_TINT32                    (0x00000001uL)
+#define INTC_ICDISR14_TINT33                    (0x00000002uL)
+#define INTC_ICDISR14_TINT34                    (0x00000004uL)
+#define INTC_ICDISR14_TINT35                    (0x00000008uL)
+#define INTC_ICDISR14_TINT36                    (0x00000010uL)
+#define INTC_ICDISR14_TINT37                    (0x00000020uL)
+#define INTC_ICDISR14_TINT38                    (0x00000040uL)
+#define INTC_ICDISR14_TINT39                    (0x00000080uL)
+#define INTC_ICDISR14_TINT40                    (0x00000100uL)
+#define INTC_ICDISR14_TINT41                    (0x00000200uL)
+#define INTC_ICDISR14_TINT42                    (0x00000400uL)
+#define INTC_ICDISR14_TINT43                    (0x00000800uL)
+#define INTC_ICDISR14_TINT44                    (0x00001000uL)
+#define INTC_ICDISR14_TINT45                    (0x00002000uL)
+#define INTC_ICDISR14_TINT46                    (0x00004000uL)
+#define INTC_ICDISR14_TINT47                    (0x00008000uL)
+#define INTC_ICDISR14_TINT48                    (0x00010000uL)
+#define INTC_ICDISR14_TINT49                    (0x00020000uL)
+#define INTC_ICDISR14_TINT50                    (0x00040000uL)
+#define INTC_ICDISR14_TINT51                    (0x00080000uL)
+#define INTC_ICDISR14_TINT52                    (0x00100000uL)
+#define INTC_ICDISR14_TINT53                    (0x00200000uL)
+#define INTC_ICDISR14_TINT54                    (0x00400000uL)
+#define INTC_ICDISR14_TINT55                    (0x00800000uL)
+#define INTC_ICDISR14_TINT56                    (0x01000000uL)
+#define INTC_ICDISR14_TINT57                    (0x02000000uL)
+#define INTC_ICDISR14_TINT58                    (0x04000000uL)
+#define INTC_ICDISR14_TINT59                    (0x08000000uL)
+#define INTC_ICDISR14_TINT60                    (0x10000000uL)
+#define INTC_ICDISR14_TINT61                    (0x20000000uL)
+#define INTC_ICDISR14_TINT62                    (0x40000000uL)
+#define INTC_ICDISR14_TINT63                    (0x80000000uL)
+
+#define INTC_ICDISR15_TINT64                    (0x00000001uL)
+#define INTC_ICDISR15_TINT65                    (0x00000002uL)
+#define INTC_ICDISR15_TINT66                    (0x00000004uL)
+#define INTC_ICDISR15_TINT67                    (0x00000008uL)
+#define INTC_ICDISR15_TINT68                    (0x00000010uL)
+#define INTC_ICDISR15_TINT69                    (0x00000020uL)
+#define INTC_ICDISR15_TINT70                    (0x00000040uL)
+#define INTC_ICDISR15_TINT71                    (0x00000080uL)
+#define INTC_ICDISR15_TINT72                    (0x00000100uL)
+#define INTC_ICDISR15_TINT73                    (0x00000200uL)
+#define INTC_ICDISR15_TINT74                    (0x00000400uL)
+#define INTC_ICDISR15_TINT75                    (0x00000800uL)
+#define INTC_ICDISR15_TINT76                    (0x00001000uL)
+#define INTC_ICDISR15_TINT77                    (0x00002000uL)
+#define INTC_ICDISR15_TINT78                    (0x00004000uL)
+#define INTC_ICDISR15_TINT79                    (0x00008000uL)
+#define INTC_ICDISR15_TINT80                    (0x00010000uL)
+#define INTC_ICDISR15_TINT81                    (0x00020000uL)
+#define INTC_ICDISR15_TINT82                    (0x00040000uL)
+#define INTC_ICDISR15_TINT83                    (0x00080000uL)
+#define INTC_ICDISR15_TINT84                    (0x00100000uL)
+#define INTC_ICDISR15_TINT85                    (0x00200000uL)
+#define INTC_ICDISR15_TINT86                    (0x00400000uL)
+#define INTC_ICDISR15_TINT87                    (0x00800000uL)
+#define INTC_ICDISR15_TINT88                    (0x01000000uL)
+#define INTC_ICDISR15_TINT89                    (0x02000000uL)
+#define INTC_ICDISR15_TINT90                    (0x04000000uL)
+#define INTC_ICDISR15_TINT91                    (0x08000000uL)
+#define INTC_ICDISR15_TINT92                    (0x10000000uL)
+#define INTC_ICDISR15_TINT93                    (0x20000000uL)
+#define INTC_ICDISR15_TINT94                    (0x40000000uL)
+#define INTC_ICDISR15_TINT95                    (0x80000000uL)
+
+#define INTC_ICDISR16_TINT96                    (0x00000001uL)
+#define INTC_ICDISR16_TINT97                    (0x00000002uL)
+#define INTC_ICDISR16_TINT98                    (0x00000004uL)
+#define INTC_ICDISR16_TINT99                    (0x00000008uL)
+#define INTC_ICDISR16_TINT100                   (0x00000010uL)
+#define INTC_ICDISR16_TINT101                   (0x00000020uL)
+#define INTC_ICDISR16_TINT102                   (0x00000040uL)
+#define INTC_ICDISR16_TINT103                   (0x00000080uL)
+#define INTC_ICDISR16_TINT104                   (0x00000100uL)
+#define INTC_ICDISR16_TINT105                   (0x00000200uL)
+#define INTC_ICDISR16_TINT106                   (0x00000400uL)
+#define INTC_ICDISR16_TINT107                   (0x00000800uL)
+#define INTC_ICDISR16_TINT108                   (0x00001000uL)
+#define INTC_ICDISR16_TINT109                   (0x00002000uL)
+#define INTC_ICDISR16_TINT110                   (0x00004000uL)
+#define INTC_ICDISR16_TINT111                   (0x00008000uL)
+#define INTC_ICDISR16_TINT112                   (0x00010000uL)
+#define INTC_ICDISR16_TINT113                   (0x00020000uL)
+#define INTC_ICDISR16_TINT114                   (0x00040000uL)
+#define INTC_ICDISR16_TINT115                   (0x00080000uL)
+#define INTC_ICDISR16_TINT116                   (0x00100000uL)
+#define INTC_ICDISR16_TINT117                   (0x00200000uL)
+#define INTC_ICDISR16_TINT118                   (0x00400000uL)
+#define INTC_ICDISR16_TINT119                   (0x00800000uL)
+#define INTC_ICDISR16_TINT120                   (0x01000000uL)
+#define INTC_ICDISR16_TINT121                   (0x02000000uL)
+#define INTC_ICDISR16_TINT122                   (0x04000000uL)
+#define INTC_ICDISR16_TINT123                   (0x08000000uL)
+#define INTC_ICDISR16_TINT124                   (0x10000000uL)
+#define INTC_ICDISR16_TINT125                   (0x20000000uL)
+#define INTC_ICDISR16_TINT126                   (0x40000000uL)
+#define INTC_ICDISR16_TINT127                   (0x80000000uL)
+
+#define INTC_ICDISR17_TINT128                   (0x00000001uL)
+#define INTC_ICDISR17_TINT129                   (0x00000002uL)
+#define INTC_ICDISR17_TINT130                   (0x00000004uL)
+#define INTC_ICDISR17_TINT131                   (0x00000008uL)
+#define INTC_ICDISR17_TINT132                   (0x00000010uL)
+#define INTC_ICDISR17_TINT133                   (0x00000020uL)
+#define INTC_ICDISR17_TINT134                   (0x00000040uL)
+#define INTC_ICDISR17_TINT135                   (0x00000080uL)
+#define INTC_ICDISR17_TINT136                   (0x00000100uL)
+#define INTC_ICDISR17_TINT137                   (0x00000200uL)
+#define INTC_ICDISR17_TINT138                   (0x00000400uL)
+#define INTC_ICDISR17_TINT139                   (0x00000800uL)
+#define INTC_ICDISR17_TINT140                   (0x00001000uL)
+#define INTC_ICDISR17_TINT141                   (0x00002000uL)
+#define INTC_ICDISR17_TINT142                   (0x00004000uL)
+#define INTC_ICDISR17_TINT143                   (0x00008000uL)
+#define INTC_ICDISR17_TINT144                   (0x00010000uL)
+#define INTC_ICDISR17_TINT145                   (0x00020000uL)
+#define INTC_ICDISR17_TINT146                   (0x00040000uL)
+#define INTC_ICDISR17_TINT147                   (0x00080000uL)
+#define INTC_ICDISR17_TINT148                   (0x00100000uL)
+#define INTC_ICDISR17_TINT149                   (0x00200000uL)
+#define INTC_ICDISR17_TINT150                   (0x00400000uL)
+#define INTC_ICDISR17_TINT151                   (0x00800000uL)
+#define INTC_ICDISR17_TINT152                   (0x01000000uL)
+#define INTC_ICDISR17_TINT153                   (0x02000000uL)
+#define INTC_ICDISR17_TINT154                   (0x04000000uL)
+#define INTC_ICDISR17_TINT155                   (0x08000000uL)
+#define INTC_ICDISR17_TINT156                   (0x10000000uL)
+#define INTC_ICDISR17_TINT157                   (0x20000000uL)
+#define INTC_ICDISR17_TINT158                   (0x40000000uL)
+#define INTC_ICDISR17_TINT159                   (0x80000000uL)
+
+#define INTC_ICDISR18_TINT160                   (0x00000001uL)
+#define INTC_ICDISR18_TINT161                   (0x00000002uL)
+#define INTC_ICDISR18_TINT162                   (0x00000004uL)
+#define INTC_ICDISR18_TINT163                   (0x00000008uL)
+#define INTC_ICDISR18_TINT164                   (0x00000010uL)
+#define INTC_ICDISR18_TINT165                   (0x00000020uL)
+#define INTC_ICDISR18_TINT166                   (0x00000040uL)
+#define INTC_ICDISR18_TINT167                   (0x00000080uL)
+#define INTC_ICDISR18_TINT168                   (0x00000100uL)
+#define INTC_ICDISR18_TINT169                   (0x00000200uL)
+#define INTC_ICDISR18_TINT170                   (0x00000400uL)
+
+#define INTC_ICDISER0_SW0                       (0x00000001uL)
+#define INTC_ICDISER0_SW1                       (0x00000002uL)
+#define INTC_ICDISER0_SW2                       (0x00000004uL)
+#define INTC_ICDISER0_SW3                       (0x00000008uL)
+#define INTC_ICDISER0_SW4                       (0x00000010uL)
+#define INTC_ICDISER0_SW5                       (0x00000020uL)
+#define INTC_ICDISER0_SW6                       (0x00000040uL)
+#define INTC_ICDISER0_SW7                       (0x00000080uL)
+#define INTC_ICDISER0_SW8                       (0x00000100uL)
+#define INTC_ICDISER0_SW9                       (0x00000200uL)
+#define INTC_ICDISER0_SW10                      (0x00000400uL)
+#define INTC_ICDISER0_SW11                      (0x00000800uL)
+#define INTC_ICDISER0_SW12                      (0x00001000uL)
+#define INTC_ICDISER0_SW13                      (0x00002000uL)
+#define INTC_ICDISER0_SW14                      (0x00004000uL)
+#define INTC_ICDISER0_SW15                      (0x00008000uL)
+#define INTC_ICDISER0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDISER0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDISER0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDISER0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDISER1_IRQ0                      (0x00000001uL)
+#define INTC_ICDISER1_IRQ1                      (0x00000002uL)
+#define INTC_ICDISER1_IRQ2                      (0x00000004uL)
+#define INTC_ICDISER1_IRQ3                      (0x00000008uL)
+#define INTC_ICDISER1_IRQ4                      (0x00000010uL)
+#define INTC_ICDISER1_IRQ5                      (0x00000020uL)
+#define INTC_ICDISER1_IRQ6                      (0x00000040uL)
+#define INTC_ICDISER1_IRQ7                      (0x00000080uL)
+#define INTC_ICDISER1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDISER1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDISER1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDISER1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDISER1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDISER1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDISER1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDISER1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDISER1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDISER1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDISER1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDISER1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDISER1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDISER1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDISER1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDISER1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDISER1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDISER1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDISER2_USBI0                     (0x00000200uL)
+#define INTC_ICDISER2_USBI1                     (0x00000400uL)
+#define INTC_ICDISER2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDISER2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDISER2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDISER2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDISER2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDISER2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDISER2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDISER2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDISER2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDISER2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDISER2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDISER2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDISER2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDISER2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDISER2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDISER2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDISER2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDISER2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDISER2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDISER2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDISER2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDISER3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDISER3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDISER3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDISER3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDISER3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDISER3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDISER3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDISER3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDISER3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDISER3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDISER3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDISER3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDISER3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDISER3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDISER3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDISER3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDISER3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDISER3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDISER3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDISER3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDISER3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDISER3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDISER3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDISER3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDISER3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDISER3_IMRDI                     (0x08000000uL)
+#define INTC_ICDISER3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDISER3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDISER3_JEDI                      (0x40000000uL)
+#define INTC_ICDISER3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDISER4_CMP0                      (0x00000001uL)
+#define INTC_ICDISER4_CMP1                      (0x00000002uL)
+#define INTC_ICDISER4_INT0                      (0x00000004uL)
+#define INTC_ICDISER4_INT1                      (0x00000008uL)
+#define INTC_ICDISER4_INT2                      (0x00000010uL)
+#define INTC_ICDISER4_INT3                      (0x00000020uL)
+#define INTC_ICDISER4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDISER4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDISER4_CMI                       (0x00000100uL)
+#define INTC_ICDISER4_WTOUT                     (0x00000200uL)
+#define INTC_ICDISER4_ITI                       (0x00000400uL)
+#define INTC_ICDISER4_TGI0A                     (0x00000800uL)
+#define INTC_ICDISER4_TGI0B                     (0x00001000uL)
+#define INTC_ICDISER4_TGI0C                     (0x00002000uL)
+#define INTC_ICDISER4_TGI0D                     (0x00004000uL)
+#define INTC_ICDISER4_TGI0V                     (0x00008000uL)
+#define INTC_ICDISER4_TGI0E                     (0x00010000uL)
+#define INTC_ICDISER4_TGI0F                     (0x00020000uL)
+#define INTC_ICDISER4_TGI1A                     (0x00040000uL)
+#define INTC_ICDISER4_TGI1B                     (0x00080000uL)
+#define INTC_ICDISER4_TGI1V                     (0x00100000uL)
+#define INTC_ICDISER4_TGI1U                     (0x00200000uL)
+#define INTC_ICDISER4_TGI2A                     (0x00400000uL)
+#define INTC_ICDISER4_TGI2B                     (0x00800000uL)
+#define INTC_ICDISER4_TGI2V                     (0x01000000uL)
+#define INTC_ICDISER4_TGI2U                     (0x02000000uL)
+#define INTC_ICDISER4_TGI3A                     (0x04000000uL)
+#define INTC_ICDISER4_TGI3B                     (0x08000000uL)
+#define INTC_ICDISER4_TGI3C                     (0x10000000uL)
+#define INTC_ICDISER4_TGI3D                     (0x20000000uL)
+#define INTC_ICDISER4_TGI3V                     (0x40000000uL)
+#define INTC_ICDISER4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDISER5_TGI4B                     (0x00000001uL)
+#define INTC_ICDISER5_TGI4C                     (0x00000002uL)
+#define INTC_ICDISER5_TGI4D                     (0x00000004uL)
+#define INTC_ICDISER5_TGI4V                     (0x00000008uL)
+#define INTC_ICDISER5_CMI1                      (0x00000010uL)
+#define INTC_ICDISER5_CMI2                      (0x00000020uL)
+#define INTC_ICDISER5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDISER5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDISER5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDISER5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDISER5_ADI                       (0x00000400uL)
+#define INTC_ICDISER5_LMTI                      (0x00000800uL)
+#define INTC_ICDISER5_SSII0                     (0x00001000uL)
+#define INTC_ICDISER5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDISER5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDISER5_SSII1                     (0x00008000uL)
+#define INTC_ICDISER5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDISER5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDISER5_SSII2                     (0x00040000uL)
+#define INTC_ICDISER5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDISER5_SSII3                     (0x00100000uL)
+#define INTC_ICDISER5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDISER5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDISER5_SSII4                     (0x00800000uL)
+#define INTC_ICDISER5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDISER5_SSII5                     (0x02000000uL)
+#define INTC_ICDISER5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDISER5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDISER5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDISER5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDISER5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDISER5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDISER6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDISER6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDISER6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDISER6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDISER6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDISER6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDISER6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDISER6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDISER6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDISER6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDISER6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDISER6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDISER6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDISER6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDISER6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDISER6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDISER6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDISER6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDISER6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDISER6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDISER6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDISER6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDISER6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDISER6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDISER6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDISER6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDISER6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDISER6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDISER6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDISER6_BRI0                      (0x20000000uL)
+#define INTC_ICDISER6_ERI0                      (0x40000000uL)
+#define INTC_ICDISER6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDISER7_TXI0                      (0x00000001uL)
+#define INTC_ICDISER7_BRI1                      (0x00000002uL)
+#define INTC_ICDISER7_ERI1                      (0x00000004uL)
+#define INTC_ICDISER7_RXI1                      (0x00000008uL)
+#define INTC_ICDISER7_TXI1                      (0x00000010uL)
+#define INTC_ICDISER7_BRI2                      (0x00000020uL)
+#define INTC_ICDISER7_ERI2                      (0x00000040uL)
+#define INTC_ICDISER7_RXI2                      (0x00000080uL)
+#define INTC_ICDISER7_TXI2                      (0x00000100uL)
+#define INTC_ICDISER7_BRI3                      (0x00000200uL)
+#define INTC_ICDISER7_ERI3                      (0x00000400uL)
+#define INTC_ICDISER7_RXI3                      (0x00000800uL)
+#define INTC_ICDISER7_TXI3                      (0x00001000uL)
+#define INTC_ICDISER7_BRI4                      (0x00002000uL)
+#define INTC_ICDISER7_ERI4                      (0x00004000uL)
+#define INTC_ICDISER7_RXI4                      (0x00008000uL)
+#define INTC_ICDISER7_TXI4                      (0x00010000uL)
+#define INTC_ICDISER7_BRI5                      (0x00020000uL)
+#define INTC_ICDISER7_ERI5                      (0x00040000uL)
+#define INTC_ICDISER7_RXI5                      (0x00080000uL)
+#define INTC_ICDISER7_TXI5                      (0x00100000uL)
+#define INTC_ICDISER7_BRI6                      (0x00200000uL)
+#define INTC_ICDISER7_ERI6                      (0x00400000uL)
+#define INTC_ICDISER7_RXI6                      (0x00800000uL)
+#define INTC_ICDISER7_TXI6                      (0x01000000uL)
+#define INTC_ICDISER7_BRI7                      (0x02000000uL)
+#define INTC_ICDISER7_ERI7                      (0x04000000uL)
+#define INTC_ICDISER7_RXI7                      (0x08000000uL)
+#define INTC_ICDISER7_TXI7                      (0x10000000uL)
+#define INTC_ICDISER7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDISER7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDISER7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDISER8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDISER8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDISER8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDISER8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDISER8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDISER8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDISER8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDISER8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDISER8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDISER8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDISER8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDISER8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDISER8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDISER8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDISER8_SPEI0                     (0x00004000uL)
+#define INTC_ICDISER8_SPRI0                     (0x00008000uL)
+#define INTC_ICDISER8_SPTI0                     (0x00010000uL)
+#define INTC_ICDISER8_SPEI1                     (0x00020000uL)
+#define INTC_ICDISER8_SPRI1                     (0x00040000uL)
+#define INTC_ICDISER8_SPTI1                     (0x00080000uL)
+#define INTC_ICDISER8_SPEI2                     (0x00100000uL)
+#define INTC_ICDISER8_SPRI2                     (0x00200000uL)
+#define INTC_ICDISER8_SPTI2                     (0x00400000uL)
+#define INTC_ICDISER8_SPEI3                     (0x00800000uL)
+#define INTC_ICDISER8_SPRI3                     (0x01000000uL)
+#define INTC_ICDISER8_SPTI3                     (0x02000000uL)
+#define INTC_ICDISER8_SPEI4                     (0x04000000uL)
+#define INTC_ICDISER8_SPRI4                     (0x08000000uL)
+#define INTC_ICDISER8_SPTI4                     (0x10000000uL)
+#define INTC_ICDISER8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDISER8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDISER8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDISER9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDISER9_ISY                       (0x00000002uL)
+#define INTC_ICDISER9_IERR                      (0x00000004uL)
+#define INTC_ICDISER9_ITARG                     (0x00000008uL)
+#define INTC_ICDISER9_ISEC                      (0x00000010uL)
+#define INTC_ICDISER9_IBUF                      (0x00000020uL)
+#define INTC_ICDISER9_IREADY                    (0x00000040uL)
+#define INTC_ICDISER9_FLSTE                     (0x00000080uL)
+#define INTC_ICDISER9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDISER9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDISER9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDISER9_MMC0                      (0x00000800uL)
+#define INTC_ICDISER9_MMC1                      (0x00001000uL)
+#define INTC_ICDISER9_MMC2                      (0x00002000uL)
+#define INTC_ICDISER9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDISER9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDISER9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDISER9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDISER9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDISER9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDISER9_ARM                       (0x00100000uL)
+#define INTC_ICDISER9_PRD                       (0x00200000uL)
+#define INTC_ICDISER9_CUP                       (0x00400000uL)
+#define INTC_ICDISER9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDISER9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDISER9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDISER9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDISER9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDISER9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDISER9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDISER9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDISER9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDISER10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDISER10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDISER10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDISER10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDISER10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDISER10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDISER10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDISER10_DRC0                     (0x00000080uL)
+#define INTC_ICDISER10_DRC1                     (0x00000100uL)
+#define INTC_ICDISER10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDISER10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDISER10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDISER10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDISER10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDISER10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDISER10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDISER10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDISER10_ERI0                     (0x08000000uL)
+#define INTC_ICDISER10_RXI0                     (0x10000000uL)
+#define INTC_ICDISER10_TXI0                     (0x20000000uL)
+#define INTC_ICDISER10_TEI0                     (0x40000000uL)
+#define INTC_ICDISER10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDISER11_RXI1                     (0x00000001uL)
+#define INTC_ICDISER11_TXI1                     (0x00000002uL)
+#define INTC_ICDISER11_TEI1                     (0x00000004uL)
+#define INTC_ICDISER11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDISER11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDISER11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDISER11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDISER11_ETHERI                   (0x00000080uL)
+#define INTC_ICDISER11_CEUI                     (0x00001000uL)
+#define INTC_ICDISER11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDISER11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDISER11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDISER12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDISER12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDISER12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDISER12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDISER12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDISER12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDISER12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDISER12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDISER12_PRRI                     (0x00000100uL)
+#define INTC_ICDISER12_IFEI0                    (0x00000200uL)
+#define INTC_ICDISER12_OFFI0                    (0x00000400uL)
+#define INTC_ICDISER12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDISER12_IFEI1                    (0x00001000uL)
+#define INTC_ICDISER12_OFFI1                    (0x00002000uL)
+#define INTC_ICDISER12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDISER13_TINT0                    (0x00000001uL)
+#define INTC_ICDISER13_TINT1                    (0x00000002uL)
+#define INTC_ICDISER13_TINT2                    (0x00000004uL)
+#define INTC_ICDISER13_TINT3                    (0x00000008uL)
+#define INTC_ICDISER13_TINT4                    (0x00000010uL)
+#define INTC_ICDISER13_TINT5                    (0x00000020uL)
+#define INTC_ICDISER13_TINT6                    (0x00000040uL)
+#define INTC_ICDISER13_TINT7                    (0x00000080uL)
+#define INTC_ICDISER13_TINT8                    (0x00000100uL)
+#define INTC_ICDISER13_TINT9                    (0x00000200uL)
+#define INTC_ICDISER13_TINT10                   (0x00000400uL)
+#define INTC_ICDISER13_TINT11                   (0x00000800uL)
+#define INTC_ICDISER13_TINT12                   (0x00001000uL)
+#define INTC_ICDISER13_TINT13                   (0x00002000uL)
+#define INTC_ICDISER13_TINT14                   (0x00004000uL)
+#define INTC_ICDISER13_TINT15                   (0x00008000uL)
+#define INTC_ICDISER13_TINT16                   (0x00010000uL)
+#define INTC_ICDISER13_TINT17                   (0x00020000uL)
+#define INTC_ICDISER13_TINT18                   (0x00040000uL)
+#define INTC_ICDISER13_TINT19                   (0x00080000uL)
+#define INTC_ICDISER13_TINT20                   (0x00100000uL)
+#define INTC_ICDISER13_TINT21                   (0x00200000uL)
+#define INTC_ICDISER13_TINT22                   (0x00400000uL)
+#define INTC_ICDISER13_TINT23                   (0x00800000uL)
+#define INTC_ICDISER13_TINT24                   (0x01000000uL)
+#define INTC_ICDISER13_TINT25                   (0x02000000uL)
+#define INTC_ICDISER13_TINT26                   (0x04000000uL)
+#define INTC_ICDISER13_TINT27                   (0x08000000uL)
+#define INTC_ICDISER13_TINT28                   (0x10000000uL)
+#define INTC_ICDISER13_TINT29                   (0x20000000uL)
+#define INTC_ICDISER13_TINT30                   (0x40000000uL)
+#define INTC_ICDISER13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDISER14_TINT32                   (0x00000001uL)
+#define INTC_ICDISER14_TINT33                   (0x00000002uL)
+#define INTC_ICDISER14_TINT34                   (0x00000004uL)
+#define INTC_ICDISER14_TINT35                   (0x00000008uL)
+#define INTC_ICDISER14_TINT36                   (0x00000010uL)
+#define INTC_ICDISER14_TINT37                   (0x00000020uL)
+#define INTC_ICDISER14_TINT38                   (0x00000040uL)
+#define INTC_ICDISER14_TINT39                   (0x00000080uL)
+#define INTC_ICDISER14_TINT40                   (0x00000100uL)
+#define INTC_ICDISER14_TINT41                   (0x00000200uL)
+#define INTC_ICDISER14_TINT42                   (0x00000400uL)
+#define INTC_ICDISER14_TINT43                   (0x00000800uL)
+#define INTC_ICDISER14_TINT44                   (0x00001000uL)
+#define INTC_ICDISER14_TINT45                   (0x00002000uL)
+#define INTC_ICDISER14_TINT46                   (0x00004000uL)
+#define INTC_ICDISER14_TINT47                   (0x00008000uL)
+#define INTC_ICDISER14_TINT48                   (0x00010000uL)
+#define INTC_ICDISER14_TINT49                   (0x00020000uL)
+#define INTC_ICDISER14_TINT50                   (0x00040000uL)
+#define INTC_ICDISER14_TINT51                   (0x00080000uL)
+#define INTC_ICDISER14_TINT52                   (0x00100000uL)
+#define INTC_ICDISER14_TINT53                   (0x00200000uL)
+#define INTC_ICDISER14_TINT54                   (0x00400000uL)
+#define INTC_ICDISER14_TINT55                   (0x00800000uL)
+#define INTC_ICDISER14_TINT56                   (0x01000000uL)
+#define INTC_ICDISER14_TINT57                   (0x02000000uL)
+#define INTC_ICDISER14_TINT58                   (0x04000000uL)
+#define INTC_ICDISER14_TINT59                   (0x08000000uL)
+#define INTC_ICDISER14_TINT60                   (0x10000000uL)
+#define INTC_ICDISER14_TINT61                   (0x20000000uL)
+#define INTC_ICDISER14_TINT62                   (0x40000000uL)
+#define INTC_ICDISER14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDISER15_TINT64                   (0x00000001uL)
+#define INTC_ICDISER15_TINT65                   (0x00000002uL)
+#define INTC_ICDISER15_TINT66                   (0x00000004uL)
+#define INTC_ICDISER15_TINT67                   (0x00000008uL)
+#define INTC_ICDISER15_TINT68                   (0x00000010uL)
+#define INTC_ICDISER15_TINT69                   (0x00000020uL)
+#define INTC_ICDISER15_TINT70                   (0x00000040uL)
+#define INTC_ICDISER15_TINT71                   (0x00000080uL)
+#define INTC_ICDISER15_TINT72                   (0x00000100uL)
+#define INTC_ICDISER15_TINT73                   (0x00000200uL)
+#define INTC_ICDISER15_TINT74                   (0x00000400uL)
+#define INTC_ICDISER15_TINT75                   (0x00000800uL)
+#define INTC_ICDISER15_TINT76                   (0x00001000uL)
+#define INTC_ICDISER15_TINT77                   (0x00002000uL)
+#define INTC_ICDISER15_TINT78                   (0x00004000uL)
+#define INTC_ICDISER15_TINT79                   (0x00008000uL)
+#define INTC_ICDISER15_TINT80                   (0x00010000uL)
+#define INTC_ICDISER15_TINT81                   (0x00020000uL)
+#define INTC_ICDISER15_TINT82                   (0x00040000uL)
+#define INTC_ICDISER15_TINT83                   (0x00080000uL)
+#define INTC_ICDISER15_TINT84                   (0x00100000uL)
+#define INTC_ICDISER15_TINT85                   (0x00200000uL)
+#define INTC_ICDISER15_TINT86                   (0x00400000uL)
+#define INTC_ICDISER15_TINT87                   (0x00800000uL)
+#define INTC_ICDISER15_TINT88                   (0x01000000uL)
+#define INTC_ICDISER15_TINT89                   (0x02000000uL)
+#define INTC_ICDISER15_TINT90                   (0x04000000uL)
+#define INTC_ICDISER15_TINT91                   (0x08000000uL)
+#define INTC_ICDISER15_TINT92                   (0x10000000uL)
+#define INTC_ICDISER15_TINT93                   (0x20000000uL)
+#define INTC_ICDISER15_TINT94                   (0x40000000uL)
+#define INTC_ICDISER15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDISER16_TINT96                   (0x00000001uL)
+#define INTC_ICDISER16_TINT97                   (0x00000002uL)
+#define INTC_ICDISER16_TINT98                   (0x00000004uL)
+#define INTC_ICDISER16_TINT99                   (0x00000008uL)
+#define INTC_ICDISER16_TINT100                  (0x00000010uL)
+#define INTC_ICDISER16_TINT101                  (0x00000020uL)
+#define INTC_ICDISER16_TINT102                  (0x00000040uL)
+#define INTC_ICDISER16_TINT103                  (0x00000080uL)
+#define INTC_ICDISER16_TINT104                  (0x00000100uL)
+#define INTC_ICDISER16_TINT105                  (0x00000200uL)
+#define INTC_ICDISER16_TINT106                  (0x00000400uL)
+#define INTC_ICDISER16_TINT107                  (0x00000800uL)
+#define INTC_ICDISER16_TINT108                  (0x00001000uL)
+#define INTC_ICDISER16_TINT109                  (0x00002000uL)
+#define INTC_ICDISER16_TINT110                  (0x00004000uL)
+#define INTC_ICDISER16_TINT111                  (0x00008000uL)
+#define INTC_ICDISER16_TINT112                  (0x00010000uL)
+#define INTC_ICDISER16_TINT113                  (0x00020000uL)
+#define INTC_ICDISER16_TINT114                  (0x00040000uL)
+#define INTC_ICDISER16_TINT115                  (0x00080000uL)
+#define INTC_ICDISER16_TINT116                  (0x00100000uL)
+#define INTC_ICDISER16_TINT117                  (0x00200000uL)
+#define INTC_ICDISER16_TINT118                  (0x00400000uL)
+#define INTC_ICDISER16_TINT119                  (0x00800000uL)
+#define INTC_ICDISER16_TINT120                  (0x01000000uL)
+#define INTC_ICDISER16_TINT121                  (0x02000000uL)
+#define INTC_ICDISER16_TINT122                  (0x04000000uL)
+#define INTC_ICDISER16_TINT123                  (0x08000000uL)
+#define INTC_ICDISER16_TINT124                  (0x10000000uL)
+#define INTC_ICDISER16_TINT125                  (0x20000000uL)
+#define INTC_ICDISER16_TINT126                  (0x40000000uL)
+#define INTC_ICDISER16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDISER17_TINT128                  (0x00000001uL)
+#define INTC_ICDISER17_TINT129                  (0x00000002uL)
+#define INTC_ICDISER17_TINT130                  (0x00000004uL)
+#define INTC_ICDISER17_TINT131                  (0x00000008uL)
+#define INTC_ICDISER17_TINT132                  (0x00000010uL)
+#define INTC_ICDISER17_TINT133                  (0x00000020uL)
+#define INTC_ICDISER17_TINT134                  (0x00000040uL)
+#define INTC_ICDISER17_TINT135                  (0x00000080uL)
+#define INTC_ICDISER17_TINT136                  (0x00000100uL)
+#define INTC_ICDISER17_TINT137                  (0x00000200uL)
+#define INTC_ICDISER17_TINT138                  (0x00000400uL)
+#define INTC_ICDISER17_TINT139                  (0x00000800uL)
+#define INTC_ICDISER17_TINT140                  (0x00001000uL)
+#define INTC_ICDISER17_TINT141                  (0x00002000uL)
+#define INTC_ICDISER17_TINT142                  (0x00004000uL)
+#define INTC_ICDISER17_TINT143                  (0x00008000uL)
+#define INTC_ICDISER17_TINT144                  (0x00010000uL)
+#define INTC_ICDISER17_TINT145                  (0x00020000uL)
+#define INTC_ICDISER17_TINT146                  (0x00040000uL)
+#define INTC_ICDISER17_TINT147                  (0x00080000uL)
+#define INTC_ICDISER17_TINT148                  (0x00100000uL)
+#define INTC_ICDISER17_TINT149                  (0x00200000uL)
+#define INTC_ICDISER17_TINT150                  (0x00400000uL)
+#define INTC_ICDISER17_TINT151                  (0x00800000uL)
+#define INTC_ICDISER17_TINT152                  (0x01000000uL)
+#define INTC_ICDISER17_TINT153                  (0x02000000uL)
+#define INTC_ICDISER17_TINT154                  (0x04000000uL)
+#define INTC_ICDISER17_TINT155                  (0x08000000uL)
+#define INTC_ICDISER17_TINT156                  (0x10000000uL)
+#define INTC_ICDISER17_TINT157                  (0x20000000uL)
+#define INTC_ICDISER17_TINT158                  (0x40000000uL)
+#define INTC_ICDISER17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDISER18_TINT160                  (0x00000001uL)
+#define INTC_ICDISER18_TINT161                  (0x00000002uL)
+#define INTC_ICDISER18_TINT162                  (0x00000004uL)
+#define INTC_ICDISER18_TINT163                  (0x00000008uL)
+#define INTC_ICDISER18_TINT164                  (0x00000010uL)
+#define INTC_ICDISER18_TINT165                  (0x00000020uL)
+#define INTC_ICDISER18_TINT166                  (0x00000040uL)
+#define INTC_ICDISER18_TINT167                  (0x00000080uL)
+#define INTC_ICDISER18_TINT168                  (0x00000100uL)
+#define INTC_ICDISER18_TINT169                  (0x00000200uL)
+#define INTC_ICDISER18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDICER0_SW0                       (0x00000001uL)
+#define INTC_ICDICER0_SW1                       (0x00000002uL)
+#define INTC_ICDICER0_SW2                       (0x00000004uL)
+#define INTC_ICDICER0_SW3                       (0x00000008uL)
+#define INTC_ICDICER0_SW4                       (0x00000010uL)
+#define INTC_ICDICER0_SW5                       (0x00000020uL)
+#define INTC_ICDICER0_SW6                       (0x00000040uL)
+#define INTC_ICDICER0_SW7                       (0x00000080uL)
+#define INTC_ICDICER0_SW8                       (0x00000100uL)
+#define INTC_ICDICER0_SW9                       (0x00000200uL)
+#define INTC_ICDICER0_SW10                      (0x00000400uL)
+#define INTC_ICDICER0_SW11                      (0x00000800uL)
+#define INTC_ICDICER0_SW12                      (0x00001000uL)
+#define INTC_ICDICER0_SW13                      (0x00002000uL)
+#define INTC_ICDICER0_SW14                      (0x00004000uL)
+#define INTC_ICDICER0_SW15                      (0x00008000uL)
+#define INTC_ICDICER0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDICER0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDICER0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDICER0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDICER1_IRQ0                      (0x00000001uL)
+#define INTC_ICDICER1_IRQ1                      (0x00000002uL)
+#define INTC_ICDICER1_IRQ2                      (0x00000004uL)
+#define INTC_ICDICER1_IRQ3                      (0x00000008uL)
+#define INTC_ICDICER1_IRQ4                      (0x00000010uL)
+#define INTC_ICDICER1_IRQ5                      (0x00000020uL)
+#define INTC_ICDICER1_IRQ6                      (0x00000040uL)
+#define INTC_ICDICER1_IRQ7                      (0x00000080uL)
+#define INTC_ICDICER1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDICER1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDICER1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDICER1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDICER1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDICER1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDICER1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDICER1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDICER1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDICER1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDICER1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDICER1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDICER1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDICER1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDICER1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDICER1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDICER1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDICER1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDICER2_USBI0                     (0x00000200uL)
+#define INTC_ICDICER2_USBI1                     (0x00000400uL)
+#define INTC_ICDICER2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDICER2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDICER2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDICER2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDICER2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDICER2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDICER2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDICER2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDICER2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDICER2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDICER2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDICER2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDICER2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDICER2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDICER2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDICER2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDICER2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDICER2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDICER2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDICER2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDICER2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDICER3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDICER3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDICER3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDICER3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDICER3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDICER3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDICER3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDICER3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDICER3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDICER3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDICER3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDICER3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDICER3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDICER3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDICER3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDICER3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDICER3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDICER3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDICER3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDICER3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDICER3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDICER3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDICER3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDICER3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDICER3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDICER3_IMRDI                     (0x08000000uL)
+#define INTC_ICDICER3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDICER3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDICER3_JEDI                      (0x40000000uL)
+#define INTC_ICDICER3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDICER4_CMP0                      (0x00000001uL)
+#define INTC_ICDICER4_CMP1                      (0x00000002uL)
+#define INTC_ICDICER4_INT0                      (0x00000004uL)
+#define INTC_ICDICER4_INT1                      (0x00000008uL)
+#define INTC_ICDICER4_INT2                      (0x00000010uL)
+#define INTC_ICDICER4_INT3                      (0x00000020uL)
+#define INTC_ICDICER4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDICER4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDICER4_CMI                       (0x00000100uL)
+#define INTC_ICDICER4_WTOUT                     (0x00000200uL)
+#define INTC_ICDICER4_ITI                       (0x00000400uL)
+#define INTC_ICDICER4_TGI0A                     (0x00000800uL)
+#define INTC_ICDICER4_TGI0B                     (0x00001000uL)
+#define INTC_ICDICER4_TGI0C                     (0x00002000uL)
+#define INTC_ICDICER4_TGI0D                     (0x00004000uL)
+#define INTC_ICDICER4_TGI0V                     (0x00008000uL)
+#define INTC_ICDICER4_TGI0E                     (0x00010000uL)
+#define INTC_ICDICER4_TGI0F                     (0x00020000uL)
+#define INTC_ICDICER4_TGI1A                     (0x00040000uL)
+#define INTC_ICDICER4_TGI1B                     (0x00080000uL)
+#define INTC_ICDICER4_TGI1V                     (0x00100000uL)
+#define INTC_ICDICER4_TGI1U                     (0x00200000uL)
+#define INTC_ICDICER4_TGI2A                     (0x00400000uL)
+#define INTC_ICDICER4_TGI2B                     (0x00800000uL)
+#define INTC_ICDICER4_TGI2V                     (0x01000000uL)
+#define INTC_ICDICER4_TGI2U                     (0x02000000uL)
+#define INTC_ICDICER4_TGI3A                     (0x04000000uL)
+#define INTC_ICDICER4_TGI3B                     (0x08000000uL)
+#define INTC_ICDICER4_TGI3C                     (0x10000000uL)
+#define INTC_ICDICER4_TGI3D                     (0x20000000uL)
+#define INTC_ICDICER4_TGI3V                     (0x40000000uL)
+#define INTC_ICDICER4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDICER5_TGI4B                     (0x00000001uL)
+#define INTC_ICDICER5_TGI4C                     (0x00000002uL)
+#define INTC_ICDICER5_TGI4D                     (0x00000004uL)
+#define INTC_ICDICER5_TGI4V                     (0x00000008uL)
+#define INTC_ICDICER5_CMI1                      (0x00000010uL)
+#define INTC_ICDICER5_CMI2                      (0x00000020uL)
+#define INTC_ICDICER5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDICER5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDICER5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDICER5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDICER5_ADI                       (0x00000400uL)
+#define INTC_ICDICER5_LMTI                      (0x00000800uL)
+#define INTC_ICDICER5_SSII0                     (0x00001000uL)
+#define INTC_ICDICER5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDICER5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDICER5_SSII1                     (0x00008000uL)
+#define INTC_ICDICER5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDICER5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDICER5_SSII2                     (0x00040000uL)
+#define INTC_ICDICER5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDICER5_SSII3                     (0x00100000uL)
+#define INTC_ICDICER5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDICER5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDICER5_SSII4                     (0x00800000uL)
+#define INTC_ICDICER5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDICER5_SSII5                     (0x02000000uL)
+#define INTC_ICDICER5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDICER5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDICER5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDICER5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDICER5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDICER5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDICER6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDICER6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDICER6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDICER6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDICER6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDICER6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDICER6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDICER6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDICER6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDICER6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDICER6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDICER6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDICER6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDICER6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDICER6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDICER6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDICER6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDICER6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDICER6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDICER6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDICER6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDICER6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDICER6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDICER6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDICER6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDICER6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDICER6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDICER6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDICER6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDICER6_BRI0                      (0x20000000uL)
+#define INTC_ICDICER6_ERI0                      (0x40000000uL)
+#define INTC_ICDICER6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDICER7_TXI0                      (0x00000001uL)
+#define INTC_ICDICER7_BRI1                      (0x00000002uL)
+#define INTC_ICDICER7_ERI1                      (0x00000004uL)
+#define INTC_ICDICER7_RXI1                      (0x00000008uL)
+#define INTC_ICDICER7_TXI1                      (0x00000010uL)
+#define INTC_ICDICER7_BRI2                      (0x00000020uL)
+#define INTC_ICDICER7_ERI2                      (0x00000040uL)
+#define INTC_ICDICER7_RXI2                      (0x00000080uL)
+#define INTC_ICDICER7_TXI2                      (0x00000100uL)
+#define INTC_ICDICER7_BRI3                      (0x00000200uL)
+#define INTC_ICDICER7_ERI3                      (0x00000400uL)
+#define INTC_ICDICER7_RXI3                      (0x00000800uL)
+#define INTC_ICDICER7_TXI3                      (0x00001000uL)
+#define INTC_ICDICER7_BRI4                      (0x00002000uL)
+#define INTC_ICDICER7_ERI4                      (0x00004000uL)
+#define INTC_ICDICER7_RXI4                      (0x00008000uL)
+#define INTC_ICDICER7_TXI4                      (0x00010000uL)
+#define INTC_ICDICER7_BRI5                      (0x00020000uL)
+#define INTC_ICDICER7_ERI5                      (0x00040000uL)
+#define INTC_ICDICER7_RXI5                      (0x00080000uL)
+#define INTC_ICDICER7_TXI5                      (0x00100000uL)
+#define INTC_ICDICER7_BRI6                      (0x00200000uL)
+#define INTC_ICDICER7_ERI6                      (0x00400000uL)
+#define INTC_ICDICER7_RXI6                      (0x00800000uL)
+#define INTC_ICDICER7_TXI6                      (0x01000000uL)
+#define INTC_ICDICER7_BRI7                      (0x02000000uL)
+#define INTC_ICDICER7_ERI7                      (0x04000000uL)
+#define INTC_ICDICER7_RXI7                      (0x08000000uL)
+#define INTC_ICDICER7_TXI7                      (0x10000000uL)
+#define INTC_ICDICER7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDICER7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDICER7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDICER8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDICER8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDICER8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDICER8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDICER8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDICER8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDICER8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDICER8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDICER8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDICER8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDICER8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDICER8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDICER8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDICER8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDICER8_SPEI0                     (0x00004000uL)
+#define INTC_ICDICER8_SPRI0                     (0x00008000uL)
+#define INTC_ICDICER8_SPTI0                     (0x00010000uL)
+#define INTC_ICDICER8_SPEI1                     (0x00020000uL)
+#define INTC_ICDICER8_SPRI1                     (0x00040000uL)
+#define INTC_ICDICER8_SPTI1                     (0x00080000uL)
+#define INTC_ICDICER8_SPEI2                     (0x00100000uL)
+#define INTC_ICDICER8_SPRI2                     (0x00200000uL)
+#define INTC_ICDICER8_SPTI2                     (0x00400000uL)
+#define INTC_ICDICER8_SPEI3                     (0x00800000uL)
+#define INTC_ICDICER8_SPRI3                     (0x01000000uL)
+#define INTC_ICDICER8_SPTI3                     (0x02000000uL)
+#define INTC_ICDICER8_SPEI4                     (0x04000000uL)
+#define INTC_ICDICER8_SPRI4                     (0x08000000uL)
+#define INTC_ICDICER8_SPTI4                     (0x10000000uL)
+#define INTC_ICDICER8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDICER8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDICER8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDICER9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDICER9_ISY                       (0x00000002uL)
+#define INTC_ICDICER9_IERR                      (0x00000004uL)
+#define INTC_ICDICER9_ITARG                     (0x00000008uL)
+#define INTC_ICDICER9_ISEC                      (0x00000010uL)
+#define INTC_ICDICER9_IBUF                      (0x00000020uL)
+#define INTC_ICDICER9_IREADY                    (0x00000040uL)
+#define INTC_ICDICER9_FLSTE                     (0x00000080uL)
+#define INTC_ICDICER9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDICER9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDICER9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDICER9_MMC0                      (0x00000800uL)
+#define INTC_ICDICER9_MMC1                      (0x00001000uL)
+#define INTC_ICDICER9_MMC2                      (0x00002000uL)
+#define INTC_ICDICER9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDICER9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDICER9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDICER9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDICER9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDICER9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDICER9_ARM                       (0x00100000uL)
+#define INTC_ICDICER9_PRD                       (0x00200000uL)
+#define INTC_ICDICER9_CUP                       (0x00400000uL)
+#define INTC_ICDICER9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDICER9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDICER9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDICER9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDICER9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDICER9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDICER9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDICER9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDICER9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDICER10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDICER10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDICER10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDICER10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDICER10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDICER10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDICER10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDICER10_DRC0                     (0x00000080uL)
+#define INTC_ICDICER10_DRC1                     (0x00000100uL)
+#define INTC_ICDICER10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDICER10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDICER10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDICER10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDICER10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDICER10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDICER10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDICER10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDICER10_ERI0                     (0x08000000uL)
+#define INTC_ICDICER10_RXI0                     (0x10000000uL)
+#define INTC_ICDICER10_TXI0                     (0x20000000uL)
+#define INTC_ICDICER10_TEI0                     (0x40000000uL)
+#define INTC_ICDICER10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDICER11_RXI1                     (0x00000001uL)
+#define INTC_ICDICER11_TXI1                     (0x00000002uL)
+#define INTC_ICDICER11_TEI1                     (0x00000004uL)
+#define INTC_ICDICER11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDICER11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDICER11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDICER11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDICER11_ETHERI                   (0x00000080uL)
+#define INTC_ICDICER11_CEUI                     (0x00001000uL)
+#define INTC_ICDICER11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDICER11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDICER11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDICER12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDICER12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDICER12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDICER12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDICER12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDICER12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDICER12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDICER12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDICER12_PRRI                     (0x00000100uL)
+#define INTC_ICDICER12_IFEI0                    (0x00000200uL)
+#define INTC_ICDICER12_OFFI0                    (0x00000400uL)
+#define INTC_ICDICER12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDICER12_IFEI1                    (0x00001000uL)
+#define INTC_ICDICER12_OFFI1                    (0x00002000uL)
+#define INTC_ICDICER12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDICER13_TINT0                    (0x00000001uL)
+#define INTC_ICDICER13_TINT1                    (0x00000002uL)
+#define INTC_ICDICER13_TINT2                    (0x00000004uL)
+#define INTC_ICDICER13_TINT3                    (0x00000008uL)
+#define INTC_ICDICER13_TINT4                    (0x00000010uL)
+#define INTC_ICDICER13_TINT5                    (0x00000020uL)
+#define INTC_ICDICER13_TINT6                    (0x00000040uL)
+#define INTC_ICDICER13_TINT7                    (0x00000080uL)
+#define INTC_ICDICER13_TINT8                    (0x00000100uL)
+#define INTC_ICDICER13_TINT9                    (0x00000200uL)
+#define INTC_ICDICER13_TINT10                   (0x00000400uL)
+#define INTC_ICDICER13_TINT11                   (0x00000800uL)
+#define INTC_ICDICER13_TINT12                   (0x00001000uL)
+#define INTC_ICDICER13_TINT13                   (0x00002000uL)
+#define INTC_ICDICER13_TINT14                   (0x00004000uL)
+#define INTC_ICDICER13_TINT15                   (0x00008000uL)
+#define INTC_ICDICER13_TINT16                   (0x00010000uL)
+#define INTC_ICDICER13_TINT17                   (0x00020000uL)
+#define INTC_ICDICER13_TINT18                   (0x00040000uL)
+#define INTC_ICDICER13_TINT19                   (0x00080000uL)
+#define INTC_ICDICER13_TINT20                   (0x00100000uL)
+#define INTC_ICDICER13_TINT21                   (0x00200000uL)
+#define INTC_ICDICER13_TINT22                   (0x00400000uL)
+#define INTC_ICDICER13_TINT23                   (0x00800000uL)
+#define INTC_ICDICER13_TINT24                   (0x01000000uL)
+#define INTC_ICDICER13_TINT25                   (0x02000000uL)
+#define INTC_ICDICER13_TINT26                   (0x04000000uL)
+#define INTC_ICDICER13_TINT27                   (0x08000000uL)
+#define INTC_ICDICER13_TINT28                   (0x10000000uL)
+#define INTC_ICDICER13_TINT29                   (0x20000000uL)
+#define INTC_ICDICER13_TINT30                   (0x40000000uL)
+#define INTC_ICDICER13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDICER14_TINT32                   (0x00000001uL)
+#define INTC_ICDICER14_TINT33                   (0x00000002uL)
+#define INTC_ICDICER14_TINT34                   (0x00000004uL)
+#define INTC_ICDICER14_TINT35                   (0x00000008uL)
+#define INTC_ICDICER14_TINT36                   (0x00000010uL)
+#define INTC_ICDICER14_TINT37                   (0x00000020uL)
+#define INTC_ICDICER14_TINT38                   (0x00000040uL)
+#define INTC_ICDICER14_TINT39                   (0x00000080uL)
+#define INTC_ICDICER14_TINT40                   (0x00000100uL)
+#define INTC_ICDICER14_TINT41                   (0x00000200uL)
+#define INTC_ICDICER14_TINT42                   (0x00000400uL)
+#define INTC_ICDICER14_TINT43                   (0x00000800uL)
+#define INTC_ICDICER14_TINT44                   (0x00001000uL)
+#define INTC_ICDICER14_TINT45                   (0x00002000uL)
+#define INTC_ICDICER14_TINT46                   (0x00004000uL)
+#define INTC_ICDICER14_TINT47                   (0x00008000uL)
+#define INTC_ICDICER14_TINT48                   (0x00010000uL)
+#define INTC_ICDICER14_TINT49                   (0x00020000uL)
+#define INTC_ICDICER14_TINT50                   (0x00040000uL)
+#define INTC_ICDICER14_TINT51                   (0x00080000uL)
+#define INTC_ICDICER14_TINT52                   (0x00100000uL)
+#define INTC_ICDICER14_TINT53                   (0x00200000uL)
+#define INTC_ICDICER14_TINT54                   (0x00400000uL)
+#define INTC_ICDICER14_TINT55                   (0x00800000uL)
+#define INTC_ICDICER14_TINT56                   (0x01000000uL)
+#define INTC_ICDICER14_TINT57                   (0x02000000uL)
+#define INTC_ICDICER14_TINT58                   (0x04000000uL)
+#define INTC_ICDICER14_TINT59                   (0x08000000uL)
+#define INTC_ICDICER14_TINT60                   (0x10000000uL)
+#define INTC_ICDICER14_TINT61                   (0x20000000uL)
+#define INTC_ICDICER14_TINT62                   (0x40000000uL)
+#define INTC_ICDICER14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDICER15_TINT64                   (0x00000001uL)
+#define INTC_ICDICER15_TINT65                   (0x00000002uL)
+#define INTC_ICDICER15_TINT66                   (0x00000004uL)
+#define INTC_ICDICER15_TINT67                   (0x00000008uL)
+#define INTC_ICDICER15_TINT68                   (0x00000010uL)
+#define INTC_ICDICER15_TINT69                   (0x00000020uL)
+#define INTC_ICDICER15_TINT70                   (0x00000040uL)
+#define INTC_ICDICER15_TINT71                   (0x00000080uL)
+#define INTC_ICDICER15_TINT72                   (0x00000100uL)
+#define INTC_ICDICER15_TINT73                   (0x00000200uL)
+#define INTC_ICDICER15_TINT74                   (0x00000400uL)
+#define INTC_ICDICER15_TINT75                   (0x00000800uL)
+#define INTC_ICDICER15_TINT76                   (0x00001000uL)
+#define INTC_ICDICER15_TINT77                   (0x00002000uL)
+#define INTC_ICDICER15_TINT78                   (0x00004000uL)
+#define INTC_ICDICER15_TINT79                   (0x00008000uL)
+#define INTC_ICDICER15_TINT80                   (0x00010000uL)
+#define INTC_ICDICER15_TINT81                   (0x00020000uL)
+#define INTC_ICDICER15_TINT82                   (0x00040000uL)
+#define INTC_ICDICER15_TINT83                   (0x00080000uL)
+#define INTC_ICDICER15_TINT84                   (0x00100000uL)
+#define INTC_ICDICER15_TINT85                   (0x00200000uL)
+#define INTC_ICDICER15_TINT86                   (0x00400000uL)
+#define INTC_ICDICER15_TINT87                   (0x00800000uL)
+#define INTC_ICDICER15_TINT88                   (0x01000000uL)
+#define INTC_ICDICER15_TINT89                   (0x02000000uL)
+#define INTC_ICDICER15_TINT90                   (0x04000000uL)
+#define INTC_ICDICER15_TINT91                   (0x08000000uL)
+#define INTC_ICDICER15_TINT92                   (0x10000000uL)
+#define INTC_ICDICER15_TINT93                   (0x20000000uL)
+#define INTC_ICDICER15_TINT94                   (0x40000000uL)
+#define INTC_ICDICER15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDICER16_TINT96                   (0x00000001uL)
+#define INTC_ICDICER16_TINT97                   (0x00000002uL)
+#define INTC_ICDICER16_TINT98                   (0x00000004uL)
+#define INTC_ICDICER16_TINT99                   (0x00000008uL)
+#define INTC_ICDICER16_TINT100                  (0x00000010uL)
+#define INTC_ICDICER16_TINT101                  (0x00000020uL)
+#define INTC_ICDICER16_TINT102                  (0x00000040uL)
+#define INTC_ICDICER16_TINT103                  (0x00000080uL)
+#define INTC_ICDICER16_TINT104                  (0x00000100uL)
+#define INTC_ICDICER16_TINT105                  (0x00000200uL)
+#define INTC_ICDICER16_TINT106                  (0x00000400uL)
+#define INTC_ICDICER16_TINT107                  (0x00000800uL)
+#define INTC_ICDICER16_TINT108                  (0x00001000uL)
+#define INTC_ICDICER16_TINT109                  (0x00002000uL)
+#define INTC_ICDICER16_TINT110                  (0x00004000uL)
+#define INTC_ICDICER16_TINT111                  (0x00008000uL)
+#define INTC_ICDICER16_TINT112                  (0x00010000uL)
+#define INTC_ICDICER16_TINT113                  (0x00020000uL)
+#define INTC_ICDICER16_TINT114                  (0x00040000uL)
+#define INTC_ICDICER16_TINT115                  (0x00080000uL)
+#define INTC_ICDICER16_TINT116                  (0x00100000uL)
+#define INTC_ICDICER16_TINT117                  (0x00200000uL)
+#define INTC_ICDICER16_TINT118                  (0x00400000uL)
+#define INTC_ICDICER16_TINT119                  (0x00800000uL)
+#define INTC_ICDICER16_TINT120                  (0x01000000uL)
+#define INTC_ICDICER16_TINT121                  (0x02000000uL)
+#define INTC_ICDICER16_TINT122                  (0x04000000uL)
+#define INTC_ICDICER16_TINT123                  (0x08000000uL)
+#define INTC_ICDICER16_TINT124                  (0x10000000uL)
+#define INTC_ICDICER16_TINT125                  (0x20000000uL)
+#define INTC_ICDICER16_TINT126                  (0x40000000uL)
+#define INTC_ICDICER16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDICER17_TINT128                  (0x00000001uL)
+#define INTC_ICDICER17_TINT129                  (0x00000002uL)
+#define INTC_ICDICER17_TINT130                  (0x00000004uL)
+#define INTC_ICDICER17_TINT131                  (0x00000008uL)
+#define INTC_ICDICER17_TINT132                  (0x00000010uL)
+#define INTC_ICDICER17_TINT133                  (0x00000020uL)
+#define INTC_ICDICER17_TINT134                  (0x00000040uL)
+#define INTC_ICDICER17_TINT135                  (0x00000080uL)
+#define INTC_ICDICER17_TINT136                  (0x00000100uL)
+#define INTC_ICDICER17_TINT137                  (0x00000200uL)
+#define INTC_ICDICER17_TINT138                  (0x00000400uL)
+#define INTC_ICDICER17_TINT139                  (0x00000800uL)
+#define INTC_ICDICER17_TINT140                  (0x00001000uL)
+#define INTC_ICDICER17_TINT141                  (0x00002000uL)
+#define INTC_ICDICER17_TINT142                  (0x00004000uL)
+#define INTC_ICDICER17_TINT143                  (0x00008000uL)
+#define INTC_ICDICER17_TINT144                  (0x00010000uL)
+#define INTC_ICDICER17_TINT145                  (0x00020000uL)
+#define INTC_ICDICER17_TINT146                  (0x00040000uL)
+#define INTC_ICDICER17_TINT147                  (0x00080000uL)
+#define INTC_ICDICER17_TINT148                  (0x00100000uL)
+#define INTC_ICDICER17_TINT149                  (0x00200000uL)
+#define INTC_ICDICER17_TINT150                  (0x00400000uL)
+#define INTC_ICDICER17_TINT151                  (0x00800000uL)
+#define INTC_ICDICER17_TINT152                  (0x01000000uL)
+#define INTC_ICDICER17_TINT153                  (0x02000000uL)
+#define INTC_ICDICER17_TINT154                  (0x04000000uL)
+#define INTC_ICDICER17_TINT155                  (0x08000000uL)
+#define INTC_ICDICER17_TINT156                  (0x10000000uL)
+#define INTC_ICDICER17_TINT157                  (0x20000000uL)
+#define INTC_ICDICER17_TINT158                  (0x40000000uL)
+#define INTC_ICDICER17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDICER18_TINT160                  (0x00000001uL)
+#define INTC_ICDICER18_TINT161                  (0x00000002uL)
+#define INTC_ICDICER18_TINT162                  (0x00000004uL)
+#define INTC_ICDICER18_TINT163                  (0x00000008uL)
+#define INTC_ICDICER18_TINT164                  (0x00000010uL)
+#define INTC_ICDICER18_TINT165                  (0x00000020uL)
+#define INTC_ICDICER18_TINT166                  (0x00000040uL)
+#define INTC_ICDICER18_TINT167                  (0x00000080uL)
+#define INTC_ICDICER18_TINT168                  (0x00000100uL)
+#define INTC_ICDICER18_TINT169                  (0x00000200uL)
+#define INTC_ICDICER18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDISPR0_SW0                       (0x00000001uL)
+#define INTC_ICDISPR0_SW1                       (0x00000002uL)
+#define INTC_ICDISPR0_SW2                       (0x00000004uL)
+#define INTC_ICDISPR0_SW3                       (0x00000008uL)
+#define INTC_ICDISPR0_SW4                       (0x00000010uL)
+#define INTC_ICDISPR0_SW5                       (0x00000020uL)
+#define INTC_ICDISPR0_SW6                       (0x00000040uL)
+#define INTC_ICDISPR0_SW7                       (0x00000080uL)
+#define INTC_ICDISPR0_SW8                       (0x00000100uL)
+#define INTC_ICDISPR0_SW9                       (0x00000200uL)
+#define INTC_ICDISPR0_SW10                      (0x00000400uL)
+#define INTC_ICDISPR0_SW11                      (0x00000800uL)
+#define INTC_ICDISPR0_SW12                      (0x00001000uL)
+#define INTC_ICDISPR0_SW13                      (0x00002000uL)
+#define INTC_ICDISPR0_SW14                      (0x00004000uL)
+#define INTC_ICDISPR0_SW15                      (0x00008000uL)
+#define INTC_ICDISPR0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDISPR0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDISPR0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDISPR0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDISPR1_IRQ0                      (0x00000001uL)
+#define INTC_ICDISPR1_IRQ1                      (0x00000002uL)
+#define INTC_ICDISPR1_IRQ2                      (0x00000004uL)
+#define INTC_ICDISPR1_IRQ3                      (0x00000008uL)
+#define INTC_ICDISPR1_IRQ4                      (0x00000010uL)
+#define INTC_ICDISPR1_IRQ5                      (0x00000020uL)
+#define INTC_ICDISPR1_IRQ6                      (0x00000040uL)
+#define INTC_ICDISPR1_IRQ7                      (0x00000080uL)
+#define INTC_ICDISPR1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDISPR1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDISPR1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDISPR1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDISPR1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDISPR1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDISPR1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDISPR1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDISPR1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDISPR1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDISPR1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDISPR1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDISPR1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDISPR1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDISPR1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDISPR1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDISPR1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDISPR1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDISPR2_USBI0                     (0x00000200uL)
+#define INTC_ICDISPR2_USBI1                     (0x00000400uL)
+#define INTC_ICDISPR2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDISPR2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDISPR2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDISPR2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDISPR2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDISPR2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDISPR2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDISPR2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDISPR2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDISPR2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDISPR2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDISPR2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDISPR2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDISPR2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDISPR2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDISPR2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDISPR2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDISPR2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDISPR2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDISPR2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDISPR2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDISPR3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDISPR3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDISPR3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDISPR3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDISPR3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDISPR3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDISPR3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDISPR3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDISPR3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDISPR3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDISPR3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDISPR3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDISPR3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDISPR3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDISPR3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDISPR3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDISPR3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDISPR3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDISPR3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDISPR3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDISPR3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDISPR3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDISPR3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDISPR3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDISPR3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDISPR3_IMRDI                     (0x08000000uL)
+#define INTC_ICDISPR3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDISPR3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDISPR3_JEDI                      (0x40000000uL)
+#define INTC_ICDISPR3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDISPR4_CMP0                      (0x00000001uL)
+#define INTC_ICDISPR4_CMP1                      (0x00000002uL)
+#define INTC_ICDISPR4_INT0                      (0x00000004uL)
+#define INTC_ICDISPR4_INT1                      (0x00000008uL)
+#define INTC_ICDISPR4_INT2                      (0x00000010uL)
+#define INTC_ICDISPR4_INT3                      (0x00000020uL)
+#define INTC_ICDISPR4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDISPR4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDISPR4_CMI                       (0x00000100uL)
+#define INTC_ICDISPR4_WTOUT                     (0x00000200uL)
+#define INTC_ICDISPR4_ITI                       (0x00000400uL)
+#define INTC_ICDISPR4_TGI0A                     (0x00000800uL)
+#define INTC_ICDISPR4_TGI0B                     (0x00001000uL)
+#define INTC_ICDISPR4_TGI0C                     (0x00002000uL)
+#define INTC_ICDISPR4_TGI0D                     (0x00004000uL)
+#define INTC_ICDISPR4_TGI0V                     (0x00008000uL)
+#define INTC_ICDISPR4_TGI0E                     (0x00010000uL)
+#define INTC_ICDISPR4_TGI0F                     (0x00020000uL)
+#define INTC_ICDISPR4_TGI1A                     (0x00040000uL)
+#define INTC_ICDISPR4_TGI1B                     (0x00080000uL)
+#define INTC_ICDISPR4_TGI1V                     (0x00100000uL)
+#define INTC_ICDISPR4_TGI1U                     (0x00200000uL)
+#define INTC_ICDISPR4_TGI2A                     (0x00400000uL)
+#define INTC_ICDISPR4_TGI2B                     (0x00800000uL)
+#define INTC_ICDISPR4_TGI2V                     (0x01000000uL)
+#define INTC_ICDISPR4_TGI2U                     (0x02000000uL)
+#define INTC_ICDISPR4_TGI3A                     (0x04000000uL)
+#define INTC_ICDISPR4_TGI3B                     (0x08000000uL)
+#define INTC_ICDISPR4_TGI3C                     (0x10000000uL)
+#define INTC_ICDISPR4_TGI3D                     (0x20000000uL)
+#define INTC_ICDISPR4_TGI3V                     (0x40000000uL)
+#define INTC_ICDISPR4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDISPR5_TGI4B                     (0x00000001uL)
+#define INTC_ICDISPR5_TGI4C                     (0x00000002uL)
+#define INTC_ICDISPR5_TGI4D                     (0x00000004uL)
+#define INTC_ICDISPR5_TGI4V                     (0x00000008uL)
+#define INTC_ICDISPR5_CMI1                      (0x00000010uL)
+#define INTC_ICDISPR5_CMI2                      (0x00000020uL)
+#define INTC_ICDISPR5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDISPR5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDISPR5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDISPR5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDISPR5_ADI                       (0x00000400uL)
+#define INTC_ICDISPR5_LMTI                      (0x00000800uL)
+#define INTC_ICDISPR5_SSII0                     (0x00001000uL)
+#define INTC_ICDISPR5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDISPR5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDISPR5_SSII1                     (0x00008000uL)
+#define INTC_ICDISPR5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDISPR5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDISPR5_SSII2                     (0x00040000uL)
+#define INTC_ICDISPR5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDISPR5_SSII3                     (0x00100000uL)
+#define INTC_ICDISPR5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDISPR5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDISPR5_SSII4                     (0x00800000uL)
+#define INTC_ICDISPR5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDISPR5_SSII5                     (0x02000000uL)
+#define INTC_ICDISPR5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDISPR5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDISPR5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDISPR5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDISPR5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDISPR5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDISPR6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDISPR6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDISPR6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDISPR6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDISPR6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDISPR6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDISPR6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDISPR6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDISPR6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDISPR6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDISPR6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDISPR6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDISPR6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDISPR6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDISPR6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDISPR6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDISPR6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDISPR6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDISPR6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDISPR6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDISPR6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDISPR6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDISPR6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDISPR6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDISPR6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDISPR6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDISPR6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDISPR6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDISPR6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDISPR6_BRI0                      (0x20000000uL)
+#define INTC_ICDISPR6_ERI0                      (0x40000000uL)
+#define INTC_ICDISPR6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDISPR7_TXI0                      (0x00000001uL)
+#define INTC_ICDISPR7_BRI1                      (0x00000002uL)
+#define INTC_ICDISPR7_ERI1                      (0x00000004uL)
+#define INTC_ICDISPR7_RXI1                      (0x00000008uL)
+#define INTC_ICDISPR7_TXI1                      (0x00000010uL)
+#define INTC_ICDISPR7_BRI2                      (0x00000020uL)
+#define INTC_ICDISPR7_ERI2                      (0x00000040uL)
+#define INTC_ICDISPR7_RXI2                      (0x00000080uL)
+#define INTC_ICDISPR7_TXI2                      (0x00000100uL)
+#define INTC_ICDISPR7_BRI3                      (0x00000200uL)
+#define INTC_ICDISPR7_ERI3                      (0x00000400uL)
+#define INTC_ICDISPR7_RXI3                      (0x00000800uL)
+#define INTC_ICDISPR7_TXI3                      (0x00001000uL)
+#define INTC_ICDISPR7_BRI4                      (0x00002000uL)
+#define INTC_ICDISPR7_ERI4                      (0x00004000uL)
+#define INTC_ICDISPR7_RXI4                      (0x00008000uL)
+#define INTC_ICDISPR7_TXI4                      (0x00010000uL)
+#define INTC_ICDISPR7_BRI5                      (0x00020000uL)
+#define INTC_ICDISPR7_ERI5                      (0x00040000uL)
+#define INTC_ICDISPR7_RXI5                      (0x00080000uL)
+#define INTC_ICDISPR7_TXI5                      (0x00100000uL)
+#define INTC_ICDISPR7_BRI6                      (0x00200000uL)
+#define INTC_ICDISPR7_ERI6                      (0x00400000uL)
+#define INTC_ICDISPR7_RXI6                      (0x00800000uL)
+#define INTC_ICDISPR7_TXI6                      (0x01000000uL)
+#define INTC_ICDISPR7_BRI7                      (0x02000000uL)
+#define INTC_ICDISPR7_ERI7                      (0x04000000uL)
+#define INTC_ICDISPR7_RXI7                      (0x08000000uL)
+#define INTC_ICDISPR7_TXI7                      (0x10000000uL)
+#define INTC_ICDISPR7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDISPR7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDISPR7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDISPR8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDISPR8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDISPR8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDISPR8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDISPR8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDISPR8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDISPR8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDISPR8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDISPR8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDISPR8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDISPR8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDISPR8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDISPR8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDISPR8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDISPR8_SPEI0                     (0x00004000uL)
+#define INTC_ICDISPR8_SPRI0                     (0x00008000uL)
+#define INTC_ICDISPR8_SPTI0                     (0x00010000uL)
+#define INTC_ICDISPR8_SPEI1                     (0x00020000uL)
+#define INTC_ICDISPR8_SPRI1                     (0x00040000uL)
+#define INTC_ICDISPR8_SPTI1                     (0x00080000uL)
+#define INTC_ICDISPR8_SPEI2                     (0x00100000uL)
+#define INTC_ICDISPR8_SPRI2                     (0x00200000uL)
+#define INTC_ICDISPR8_SPTI2                     (0x00400000uL)
+#define INTC_ICDISPR8_SPEI3                     (0x00800000uL)
+#define INTC_ICDISPR8_SPRI3                     (0x01000000uL)
+#define INTC_ICDISPR8_SPTI3                     (0x02000000uL)
+#define INTC_ICDISPR8_SPEI4                     (0x04000000uL)
+#define INTC_ICDISPR8_SPRI4                     (0x08000000uL)
+#define INTC_ICDISPR8_SPTI4                     (0x10000000uL)
+#define INTC_ICDISPR8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDISPR8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDISPR8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDISPR9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDISPR9_ISY                       (0x00000002uL)
+#define INTC_ICDISPR9_IERR                      (0x00000004uL)
+#define INTC_ICDISPR9_ITARG                     (0x00000008uL)
+#define INTC_ICDISPR9_ISEC                      (0x00000010uL)
+#define INTC_ICDISPR9_IBUF                      (0x00000020uL)
+#define INTC_ICDISPR9_IREADY                    (0x00000040uL)
+#define INTC_ICDISPR9_FLSTE                     (0x00000080uL)
+#define INTC_ICDISPR9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDISPR9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDISPR9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDISPR9_MMC0                      (0x00000800uL)
+#define INTC_ICDISPR9_MMC1                      (0x00001000uL)
+#define INTC_ICDISPR9_MMC2                      (0x00002000uL)
+#define INTC_ICDISPR9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDISPR9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDISPR9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDISPR9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDISPR9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDISPR9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDISPR9_ARM                       (0x00100000uL)
+#define INTC_ICDISPR9_PRD                       (0x00200000uL)
+#define INTC_ICDISPR9_CUP                       (0x00400000uL)
+#define INTC_ICDISPR9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDISPR9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDISPR9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDISPR9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDISPR9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDISPR9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDISPR9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDISPR9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDISPR9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDISPR10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDISPR10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDISPR10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDISPR10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDISPR10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDISPR10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDISPR10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDISPR10_DRC0                     (0x00000080uL)
+#define INTC_ICDISPR10_DRC1                     (0x00000100uL)
+#define INTC_ICDISPR10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDISPR10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDISPR10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDISPR10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDISPR10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDISPR10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDISPR10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDISPR10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDISPR10_ERI0                     (0x08000000uL)
+#define INTC_ICDISPR10_RXI0                     (0x10000000uL)
+#define INTC_ICDISPR10_TXI0                     (0x20000000uL)
+#define INTC_ICDISPR10_TEI0                     (0x40000000uL)
+#define INTC_ICDISPR10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDISPR11_RXI1                     (0x00000001uL)
+#define INTC_ICDISPR11_TXI1                     (0x00000002uL)
+#define INTC_ICDISPR11_TEI1                     (0x00000004uL)
+#define INTC_ICDISPR11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDISPR11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDISPR11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDISPR11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDISPR11_ETHERI                   (0x00000080uL)
+#define INTC_ICDISPR11_CEUI                     (0x00001000uL)
+#define INTC_ICDISPR11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDISPR11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDISPR11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDISPR12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDISPR12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDISPR12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDISPR12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDISPR12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDISPR12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDISPR12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDISPR12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDISPR12_PRRI                     (0x00000100uL)
+#define INTC_ICDISPR12_IFEI0                    (0x00000200uL)
+#define INTC_ICDISPR12_OFFI0                    (0x00000400uL)
+#define INTC_ICDISPR12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDISPR12_IFEI1                    (0x00001000uL)
+#define INTC_ICDISPR12_OFFI1                    (0x00002000uL)
+#define INTC_ICDISPR12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDISPR13_TINT0                    (0x00000001uL)
+#define INTC_ICDISPR13_TINT1                    (0x00000002uL)
+#define INTC_ICDISPR13_TINT2                    (0x00000004uL)
+#define INTC_ICDISPR13_TINT3                    (0x00000008uL)
+#define INTC_ICDISPR13_TINT4                    (0x00000010uL)
+#define INTC_ICDISPR13_TINT5                    (0x00000020uL)
+#define INTC_ICDISPR13_TINT6                    (0x00000040uL)
+#define INTC_ICDISPR13_TINT7                    (0x00000080uL)
+#define INTC_ICDISPR13_TINT8                    (0x00000100uL)
+#define INTC_ICDISPR13_TINT9                    (0x00000200uL)
+#define INTC_ICDISPR13_TINT10                   (0x00000400uL)
+#define INTC_ICDISPR13_TINT11                   (0x00000800uL)
+#define INTC_ICDISPR13_TINT12                   (0x00001000uL)
+#define INTC_ICDISPR13_TINT13                   (0x00002000uL)
+#define INTC_ICDISPR13_TINT14                   (0x00004000uL)
+#define INTC_ICDISPR13_TINT15                   (0x00008000uL)
+#define INTC_ICDISPR13_TINT16                   (0x00010000uL)
+#define INTC_ICDISPR13_TINT17                   (0x00020000uL)
+#define INTC_ICDISPR13_TINT18                   (0x00040000uL)
+#define INTC_ICDISPR13_TINT19                   (0x00080000uL)
+#define INTC_ICDISPR13_TINT20                   (0x00100000uL)
+#define INTC_ICDISPR13_TINT21                   (0x00200000uL)
+#define INTC_ICDISPR13_TINT22                   (0x00400000uL)
+#define INTC_ICDISPR13_TINT23                   (0x00800000uL)
+#define INTC_ICDISPR13_TINT24                   (0x01000000uL)
+#define INTC_ICDISPR13_TINT25                   (0x02000000uL)
+#define INTC_ICDISPR13_TINT26                   (0x04000000uL)
+#define INTC_ICDISPR13_TINT27                   (0x08000000uL)
+#define INTC_ICDISPR13_TINT28                   (0x10000000uL)
+#define INTC_ICDISPR13_TINT29                   (0x20000000uL)
+#define INTC_ICDISPR13_TINT30                   (0x40000000uL)
+#define INTC_ICDISPR13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDISPR14_TINT32                   (0x00000001uL)
+#define INTC_ICDISPR14_TINT33                   (0x00000002uL)
+#define INTC_ICDISPR14_TINT34                   (0x00000004uL)
+#define INTC_ICDISPR14_TINT35                   (0x00000008uL)
+#define INTC_ICDISPR14_TINT36                   (0x00000010uL)
+#define INTC_ICDISPR14_TINT37                   (0x00000020uL)
+#define INTC_ICDISPR14_TINT38                   (0x00000040uL)
+#define INTC_ICDISPR14_TINT39                   (0x00000080uL)
+#define INTC_ICDISPR14_TINT40                   (0x00000100uL)
+#define INTC_ICDISPR14_TINT41                   (0x00000200uL)
+#define INTC_ICDISPR14_TINT42                   (0x00000400uL)
+#define INTC_ICDISPR14_TINT43                   (0x00000800uL)
+#define INTC_ICDISPR14_TINT44                   (0x00001000uL)
+#define INTC_ICDISPR14_TINT45                   (0x00002000uL)
+#define INTC_ICDISPR14_TINT46                   (0x00004000uL)
+#define INTC_ICDISPR14_TINT47                   (0x00008000uL)
+#define INTC_ICDISPR14_TINT48                   (0x00010000uL)
+#define INTC_ICDISPR14_TINT49                   (0x00020000uL)
+#define INTC_ICDISPR14_TINT50                   (0x00040000uL)
+#define INTC_ICDISPR14_TINT51                   (0x00080000uL)
+#define INTC_ICDISPR14_TINT52                   (0x00100000uL)
+#define INTC_ICDISPR14_TINT53                   (0x00200000uL)
+#define INTC_ICDISPR14_TINT54                   (0x00400000uL)
+#define INTC_ICDISPR14_TINT55                   (0x00800000uL)
+#define INTC_ICDISPR14_TINT56                   (0x01000000uL)
+#define INTC_ICDISPR14_TINT57                   (0x02000000uL)
+#define INTC_ICDISPR14_TINT58                   (0x04000000uL)
+#define INTC_ICDISPR14_TINT59                   (0x08000000uL)
+#define INTC_ICDISPR14_TINT60                   (0x10000000uL)
+#define INTC_ICDISPR14_TINT61                   (0x20000000uL)
+#define INTC_ICDISPR14_TINT62                   (0x40000000uL)
+#define INTC_ICDISPR14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDISPR15_TINT64                   (0x00000001uL)
+#define INTC_ICDISPR15_TINT65                   (0x00000002uL)
+#define INTC_ICDISPR15_TINT66                   (0x00000004uL)
+#define INTC_ICDISPR15_TINT67                   (0x00000008uL)
+#define INTC_ICDISPR15_TINT68                   (0x00000010uL)
+#define INTC_ICDISPR15_TINT69                   (0x00000020uL)
+#define INTC_ICDISPR15_TINT70                   (0x00000040uL)
+#define INTC_ICDISPR15_TINT71                   (0x00000080uL)
+#define INTC_ICDISPR15_TINT72                   (0x00000100uL)
+#define INTC_ICDISPR15_TINT73                   (0x00000200uL)
+#define INTC_ICDISPR15_TINT74                   (0x00000400uL)
+#define INTC_ICDISPR15_TINT75                   (0x00000800uL)
+#define INTC_ICDISPR15_TINT76                   (0x00001000uL)
+#define INTC_ICDISPR15_TINT77                   (0x00002000uL)
+#define INTC_ICDISPR15_TINT78                   (0x00004000uL)
+#define INTC_ICDISPR15_TINT79                   (0x00008000uL)
+#define INTC_ICDISPR15_TINT80                   (0x00010000uL)
+#define INTC_ICDISPR15_TINT81                   (0x00020000uL)
+#define INTC_ICDISPR15_TINT82                   (0x00040000uL)
+#define INTC_ICDISPR15_TINT83                   (0x00080000uL)
+#define INTC_ICDISPR15_TINT84                   (0x00100000uL)
+#define INTC_ICDISPR15_TINT85                   (0x00200000uL)
+#define INTC_ICDISPR15_TINT86                   (0x00400000uL)
+#define INTC_ICDISPR15_TINT87                   (0x00800000uL)
+#define INTC_ICDISPR15_TINT88                   (0x01000000uL)
+#define INTC_ICDISPR15_TINT89                   (0x02000000uL)
+#define INTC_ICDISPR15_TINT90                   (0x04000000uL)
+#define INTC_ICDISPR15_TINT91                   (0x08000000uL)
+#define INTC_ICDISPR15_TINT92                   (0x10000000uL)
+#define INTC_ICDISPR15_TINT93                   (0x20000000uL)
+#define INTC_ICDISPR15_TINT94                   (0x40000000uL)
+#define INTC_ICDISPR15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDISPR16_TINT96                   (0x00000001uL)
+#define INTC_ICDISPR16_TINT97                   (0x00000002uL)
+#define INTC_ICDISPR16_TINT98                   (0x00000004uL)
+#define INTC_ICDISPR16_TINT99                   (0x00000008uL)
+#define INTC_ICDISPR16_TINT100                  (0x00000010uL)
+#define INTC_ICDISPR16_TINT101                  (0x00000020uL)
+#define INTC_ICDISPR16_TINT102                  (0x00000040uL)
+#define INTC_ICDISPR16_TINT103                  (0x00000080uL)
+#define INTC_ICDISPR16_TINT104                  (0x00000100uL)
+#define INTC_ICDISPR16_TINT105                  (0x00000200uL)
+#define INTC_ICDISPR16_TINT106                  (0x00000400uL)
+#define INTC_ICDISPR16_TINT107                  (0x00000800uL)
+#define INTC_ICDISPR16_TINT108                  (0x00001000uL)
+#define INTC_ICDISPR16_TINT109                  (0x00002000uL)
+#define INTC_ICDISPR16_TINT110                  (0x00004000uL)
+#define INTC_ICDISPR16_TINT111                  (0x00008000uL)
+#define INTC_ICDISPR16_TINT112                  (0x00010000uL)
+#define INTC_ICDISPR16_TINT113                  (0x00020000uL)
+#define INTC_ICDISPR16_TINT114                  (0x00040000uL)
+#define INTC_ICDISPR16_TINT115                  (0x00080000uL)
+#define INTC_ICDISPR16_TINT116                  (0x00100000uL)
+#define INTC_ICDISPR16_TINT117                  (0x00200000uL)
+#define INTC_ICDISPR16_TINT118                  (0x00400000uL)
+#define INTC_ICDISPR16_TINT119                  (0x00800000uL)
+#define INTC_ICDISPR16_TINT120                  (0x01000000uL)
+#define INTC_ICDISPR16_TINT121                  (0x02000000uL)
+#define INTC_ICDISPR16_TINT122                  (0x04000000uL)
+#define INTC_ICDISPR16_TINT123                  (0x08000000uL)
+#define INTC_ICDISPR16_TINT124                  (0x10000000uL)
+#define INTC_ICDISPR16_TINT125                  (0x20000000uL)
+#define INTC_ICDISPR16_TINT126                  (0x40000000uL)
+#define INTC_ICDISPR16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDISPR17_TINT128                  (0x00000001uL)
+#define INTC_ICDISPR17_TINT129                  (0x00000002uL)
+#define INTC_ICDISPR17_TINT130                  (0x00000004uL)
+#define INTC_ICDISPR17_TINT131                  (0x00000008uL)
+#define INTC_ICDISPR17_TINT132                  (0x00000010uL)
+#define INTC_ICDISPR17_TINT133                  (0x00000020uL)
+#define INTC_ICDISPR17_TINT134                  (0x00000040uL)
+#define INTC_ICDISPR17_TINT135                  (0x00000080uL)
+#define INTC_ICDISPR17_TINT136                  (0x00000100uL)
+#define INTC_ICDISPR17_TINT137                  (0x00000200uL)
+#define INTC_ICDISPR17_TINT138                  (0x00000400uL)
+#define INTC_ICDISPR17_TINT139                  (0x00000800uL)
+#define INTC_ICDISPR17_TINT140                  (0x00001000uL)
+#define INTC_ICDISPR17_TINT141                  (0x00002000uL)
+#define INTC_ICDISPR17_TINT142                  (0x00004000uL)
+#define INTC_ICDISPR17_TINT143                  (0x00008000uL)
+#define INTC_ICDISPR17_TINT144                  (0x00010000uL)
+#define INTC_ICDISPR17_TINT145                  (0x00020000uL)
+#define INTC_ICDISPR17_TINT146                  (0x00040000uL)
+#define INTC_ICDISPR17_TINT147                  (0x00080000uL)
+#define INTC_ICDISPR17_TINT148                  (0x00100000uL)
+#define INTC_ICDISPR17_TINT149                  (0x00200000uL)
+#define INTC_ICDISPR17_TINT150                  (0x00400000uL)
+#define INTC_ICDISPR17_TINT151                  (0x00800000uL)
+#define INTC_ICDISPR17_TINT152                  (0x01000000uL)
+#define INTC_ICDISPR17_TINT153                  (0x02000000uL)
+#define INTC_ICDISPR17_TINT154                  (0x04000000uL)
+#define INTC_ICDISPR17_TINT155                  (0x08000000uL)
+#define INTC_ICDISPR17_TINT156                  (0x10000000uL)
+#define INTC_ICDISPR17_TINT157                  (0x20000000uL)
+#define INTC_ICDISPR17_TINT158                  (0x40000000uL)
+#define INTC_ICDISPR17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDISPR18_TINT160                  (0x00000001uL)
+#define INTC_ICDISPR18_TINT161                  (0x00000002uL)
+#define INTC_ICDISPR18_TINT162                  (0x00000004uL)
+#define INTC_ICDISPR18_TINT163                  (0x00000008uL)
+#define INTC_ICDISPR18_TINT164                  (0x00000010uL)
+#define INTC_ICDISPR18_TINT165                  (0x00000020uL)
+#define INTC_ICDISPR18_TINT166                  (0x00000040uL)
+#define INTC_ICDISPR18_TINT167                  (0x00000080uL)
+#define INTC_ICDISPR18_TINT168                  (0x00000100uL)
+#define INTC_ICDISPR18_TINT169                  (0x00000200uL)
+#define INTC_ICDISPR18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDICPR0_SW0                       (0x00000001uL)
+#define INTC_ICDICPR0_SW1                       (0x00000002uL)
+#define INTC_ICDICPR0_SW2                       (0x00000004uL)
+#define INTC_ICDICPR0_SW3                       (0x00000008uL)
+#define INTC_ICDICPR0_SW4                       (0x00000010uL)
+#define INTC_ICDICPR0_SW5                       (0x00000020uL)
+#define INTC_ICDICPR0_SW6                       (0x00000040uL)
+#define INTC_ICDICPR0_SW7                       (0x00000080uL)
+#define INTC_ICDICPR0_SW8                       (0x00000100uL)
+#define INTC_ICDICPR0_SW9                       (0x00000200uL)
+#define INTC_ICDICPR0_SW10                      (0x00000400uL)
+#define INTC_ICDICPR0_SW11                      (0x00000800uL)
+#define INTC_ICDICPR0_SW12                      (0x00001000uL)
+#define INTC_ICDICPR0_SW13                      (0x00002000uL)
+#define INTC_ICDICPR0_SW14                      (0x00004000uL)
+#define INTC_ICDICPR0_SW15                      (0x00008000uL)
+#define INTC_ICDICPR0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDICPR0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDICPR0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDICPR0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDICPR1_IRQ0                      (0x00000001uL)
+#define INTC_ICDICPR1_IRQ1                      (0x00000002uL)
+#define INTC_ICDICPR1_IRQ2                      (0x00000004uL)
+#define INTC_ICDICPR1_IRQ3                      (0x00000008uL)
+#define INTC_ICDICPR1_IRQ4                      (0x00000010uL)
+#define INTC_ICDICPR1_IRQ5                      (0x00000020uL)
+#define INTC_ICDICPR1_IRQ6                      (0x00000040uL)
+#define INTC_ICDICPR1_IRQ7                      (0x00000080uL)
+#define INTC_ICDICPR1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDICPR1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDICPR1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDICPR1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDICPR1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDICPR1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDICPR1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDICPR1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDICPR1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDICPR1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDICPR1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDICPR1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDICPR1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDICPR1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDICPR1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDICPR1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDICPR1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDICPR1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDICPR2_USBI0                     (0x00000200uL)
+#define INTC_ICDICPR2_USBI1                     (0x00000400uL)
+#define INTC_ICDICPR2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDICPR2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDICPR2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDICPR2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDICPR2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDICPR2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDICPR2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDICPR2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDICPR2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDICPR2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDICPR2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDICPR2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDICPR2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDICPR2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDICPR2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDICPR2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDICPR2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDICPR2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDICPR2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDICPR2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDICPR2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDICPR3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDICPR3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDICPR3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDICPR3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDICPR3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDICPR3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDICPR3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDICPR3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDICPR3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDICPR3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDICPR3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDICPR3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDICPR3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDICPR3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDICPR3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDICPR3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDICPR3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDICPR3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDICPR3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDICPR3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDICPR3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDICPR3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDICPR3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDICPR3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDICPR3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDICPR3_IMRDI                     (0x08000000uL)
+#define INTC_ICDICPR3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDICPR3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDICPR3_JEDI                      (0x40000000uL)
+#define INTC_ICDICPR3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDICPR4_CMP0                      (0x00000001uL)
+#define INTC_ICDICPR4_CMP1                      (0x00000002uL)
+#define INTC_ICDICPR4_INT0                      (0x00000004uL)
+#define INTC_ICDICPR4_INT1                      (0x00000008uL)
+#define INTC_ICDICPR4_INT2                      (0x00000010uL)
+#define INTC_ICDICPR4_INT3                      (0x00000020uL)
+#define INTC_ICDICPR4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDICPR4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDICPR4_CMI                       (0x00000100uL)
+#define INTC_ICDICPR4_WTOUT                     (0x00000200uL)
+#define INTC_ICDICPR4_ITI                       (0x00000400uL)
+#define INTC_ICDICPR4_TGI0A                     (0x00000800uL)
+#define INTC_ICDICPR4_TGI0B                     (0x00001000uL)
+#define INTC_ICDICPR4_TGI0C                     (0x00002000uL)
+#define INTC_ICDICPR4_TGI0D                     (0x00004000uL)
+#define INTC_ICDICPR4_TGI0V                     (0x00008000uL)
+#define INTC_ICDICPR4_TGI0E                     (0x00010000uL)
+#define INTC_ICDICPR4_TGI0F                     (0x00020000uL)
+#define INTC_ICDICPR4_TGI1A                     (0x00040000uL)
+#define INTC_ICDICPR4_TGI1B                     (0x00080000uL)
+#define INTC_ICDICPR4_TGI1V                     (0x00100000uL)
+#define INTC_ICDICPR4_TGI1U                     (0x00200000uL)
+#define INTC_ICDICPR4_TGI2A                     (0x00400000uL)
+#define INTC_ICDICPR4_TGI2B                     (0x00800000uL)
+#define INTC_ICDICPR4_TGI2V                     (0x01000000uL)
+#define INTC_ICDICPR4_TGI2U                     (0x02000000uL)
+#define INTC_ICDICPR4_TGI3A                     (0x04000000uL)
+#define INTC_ICDICPR4_TGI3B                     (0x08000000uL)
+#define INTC_ICDICPR4_TGI3C                     (0x10000000uL)
+#define INTC_ICDICPR4_TGI3D                     (0x20000000uL)
+#define INTC_ICDICPR4_TGI3V                     (0x40000000uL)
+#define INTC_ICDICPR4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDICPR5_TGI4B                     (0x00000001uL)
+#define INTC_ICDICPR5_TGI4C                     (0x00000002uL)
+#define INTC_ICDICPR5_TGI4D                     (0x00000004uL)
+#define INTC_ICDICPR5_TGI4V                     (0x00000008uL)
+#define INTC_ICDICPR5_CMI1                      (0x00000010uL)
+#define INTC_ICDICPR5_CMI2                      (0x00000020uL)
+#define INTC_ICDICPR5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDICPR5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDICPR5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDICPR5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDICPR5_ADI                       (0x00000400uL)
+#define INTC_ICDICPR5_LMTI                      (0x00000800uL)
+#define INTC_ICDICPR5_SSII0                     (0x00001000uL)
+#define INTC_ICDICPR5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDICPR5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDICPR5_SSII1                     (0x00008000uL)
+#define INTC_ICDICPR5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDICPR5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDICPR5_SSII2                     (0x00040000uL)
+#define INTC_ICDICPR5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDICPR5_SSII3                     (0x00100000uL)
+#define INTC_ICDICPR5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDICPR5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDICPR5_SSII4                     (0x00800000uL)
+#define INTC_ICDICPR5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDICPR5_SSII5                     (0x02000000uL)
+#define INTC_ICDICPR5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDICPR5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDICPR5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDICPR5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDICPR5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDICPR5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDICPR6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDICPR6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDICPR6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDICPR6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDICPR6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDICPR6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDICPR6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDICPR6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDICPR6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDICPR6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDICPR6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDICPR6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDICPR6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDICPR6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDICPR6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDICPR6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDICPR6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDICPR6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDICPR6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDICPR6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDICPR6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDICPR6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDICPR6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDICPR6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDICPR6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDICPR6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDICPR6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDICPR6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDICPR6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDICPR6_BRI0                      (0x20000000uL)
+#define INTC_ICDICPR6_ERI0                      (0x40000000uL)
+#define INTC_ICDICPR6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDICPR7_TXI0                      (0x00000001uL)
+#define INTC_ICDICPR7_BRI1                      (0x00000002uL)
+#define INTC_ICDICPR7_ERI1                      (0x00000004uL)
+#define INTC_ICDICPR7_RXI1                      (0x00000008uL)
+#define INTC_ICDICPR7_TXI1                      (0x00000010uL)
+#define INTC_ICDICPR7_BRI2                      (0x00000020uL)
+#define INTC_ICDICPR7_ERI2                      (0x00000040uL)
+#define INTC_ICDICPR7_RXI2                      (0x00000080uL)
+#define INTC_ICDICPR7_TXI2                      (0x00000100uL)
+#define INTC_ICDICPR7_BRI3                      (0x00000200uL)
+#define INTC_ICDICPR7_ERI3                      (0x00000400uL)
+#define INTC_ICDICPR7_RXI3                      (0x00000800uL)
+#define INTC_ICDICPR7_TXI3                      (0x00001000uL)
+#define INTC_ICDICPR7_BRI4                      (0x00002000uL)
+#define INTC_ICDICPR7_ERI4                      (0x00004000uL)
+#define INTC_ICDICPR7_RXI4                      (0x00008000uL)
+#define INTC_ICDICPR7_TXI4                      (0x00010000uL)
+#define INTC_ICDICPR7_BRI5                      (0x00020000uL)
+#define INTC_ICDICPR7_ERI5                      (0x00040000uL)
+#define INTC_ICDICPR7_RXI5                      (0x00080000uL)
+#define INTC_ICDICPR7_TXI5                      (0x00100000uL)
+#define INTC_ICDICPR7_BRI6                      (0x00200000uL)
+#define INTC_ICDICPR7_ERI6                      (0x00400000uL)
+#define INTC_ICDICPR7_RXI6                      (0x00800000uL)
+#define INTC_ICDICPR7_TXI6                      (0x01000000uL)
+#define INTC_ICDICPR7_BRI7                      (0x02000000uL)
+#define INTC_ICDICPR7_ERI7                      (0x04000000uL)
+#define INTC_ICDICPR7_RXI7                      (0x08000000uL)
+#define INTC_ICDICPR7_TXI7                      (0x10000000uL)
+#define INTC_ICDICPR7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDICPR7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDICPR7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDICPR8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDICPR8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDICPR8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDICPR8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDICPR8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDICPR8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDICPR8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDICPR8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDICPR8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDICPR8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDICPR8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDICPR8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDICPR8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDICPR8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDICPR8_SPEI0                     (0x00004000uL)
+#define INTC_ICDICPR8_SPRI0                     (0x00008000uL)
+#define INTC_ICDICPR8_SPTI0                     (0x00010000uL)
+#define INTC_ICDICPR8_SPEI1                     (0x00020000uL)
+#define INTC_ICDICPR8_SPRI1                     (0x00040000uL)
+#define INTC_ICDICPR8_SPTI1                     (0x00080000uL)
+#define INTC_ICDICPR8_SPEI2                     (0x00100000uL)
+#define INTC_ICDICPR8_SPRI2                     (0x00200000uL)
+#define INTC_ICDICPR8_SPTI2                     (0x00400000uL)
+#define INTC_ICDICPR8_SPEI3                     (0x00800000uL)
+#define INTC_ICDICPR8_SPRI3                     (0x01000000uL)
+#define INTC_ICDICPR8_SPTI3                     (0x02000000uL)
+#define INTC_ICDICPR8_SPEI4                     (0x04000000uL)
+#define INTC_ICDICPR8_SPRI4                     (0x08000000uL)
+#define INTC_ICDICPR8_SPTI4                     (0x10000000uL)
+#define INTC_ICDICPR8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDICPR8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDICPR8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDICPR9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDICPR9_ISY                       (0x00000002uL)
+#define INTC_ICDICPR9_IERR                      (0x00000004uL)
+#define INTC_ICDICPR9_ITARG                     (0x00000008uL)
+#define INTC_ICDICPR9_ISEC                      (0x00000010uL)
+#define INTC_ICDICPR9_IBUF                      (0x00000020uL)
+#define INTC_ICDICPR9_IREADY                    (0x00000040uL)
+#define INTC_ICDICPR9_FLSTE                     (0x00000080uL)
+#define INTC_ICDICPR9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDICPR9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDICPR9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDICPR9_MMC0                      (0x00000800uL)
+#define INTC_ICDICPR9_MMC1                      (0x00001000uL)
+#define INTC_ICDICPR9_MMC2                      (0x00002000uL)
+#define INTC_ICDICPR9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDICPR9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDICPR9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDICPR9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDICPR9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDICPR9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDICPR9_ARM                       (0x00100000uL)
+#define INTC_ICDICPR9_PRD                       (0x00200000uL)
+#define INTC_ICDICPR9_CUP                       (0x00400000uL)
+#define INTC_ICDICPR9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDICPR9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDICPR9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDICPR9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDICPR9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDICPR9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDICPR9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDICPR9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDICPR9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDICPR10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDICPR10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDICPR10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDICPR10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDICPR10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDICPR10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDICPR10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDICPR10_DRC0                     (0x00000080uL)
+#define INTC_ICDICPR10_DRC1                     (0x00000100uL)
+#define INTC_ICDICPR10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDICPR10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDICPR10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDICPR10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDICPR10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDICPR10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDICPR10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDICPR10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDICPR10_ERI0                     (0x08000000uL)
+#define INTC_ICDICPR10_RXI0                     (0x10000000uL)
+#define INTC_ICDICPR10_TXI0                     (0x20000000uL)
+#define INTC_ICDICPR10_TEI0                     (0x40000000uL)
+#define INTC_ICDICPR10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDICPR11_RXI1                     (0x00000001uL)
+#define INTC_ICDICPR11_TXI1                     (0x00000002uL)
+#define INTC_ICDICPR11_TEI1                     (0x00000004uL)
+#define INTC_ICDICPR11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDICPR11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDICPR11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDICPR11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDICPR11_ETHERI                   (0x00000080uL)
+#define INTC_ICDICPR11_CEUI                     (0x00001000uL)
+#define INTC_ICDICPR11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDICPR11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDICPR11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDICPR12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDICPR12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDICPR12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDICPR12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDICPR12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDICPR12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDICPR12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDICPR12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDICPR12_PRRI                     (0x00000100uL)
+#define INTC_ICDICPR12_IFEI0                    (0x00000200uL)
+#define INTC_ICDICPR12_OFFI0                    (0x00000400uL)
+#define INTC_ICDICPR12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDICPR12_IFEI1                    (0x00001000uL)
+#define INTC_ICDICPR12_OFFI1                    (0x00002000uL)
+#define INTC_ICDICPR12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDICPR13_TINT0                    (0x00000001uL)
+#define INTC_ICDICPR13_TINT1                    (0x00000002uL)
+#define INTC_ICDICPR13_TINT2                    (0x00000004uL)
+#define INTC_ICDICPR13_TINT3                    (0x00000008uL)
+#define INTC_ICDICPR13_TINT4                    (0x00000010uL)
+#define INTC_ICDICPR13_TINT5                    (0x00000020uL)
+#define INTC_ICDICPR13_TINT6                    (0x00000040uL)
+#define INTC_ICDICPR13_TINT7                    (0x00000080uL)
+#define INTC_ICDICPR13_TINT8                    (0x00000100uL)
+#define INTC_ICDICPR13_TINT9                    (0x00000200uL)
+#define INTC_ICDICPR13_TINT10                   (0x00000400uL)
+#define INTC_ICDICPR13_TINT11                   (0x00000800uL)
+#define INTC_ICDICPR13_TINT12                   (0x00001000uL)
+#define INTC_ICDICPR13_TINT13                   (0x00002000uL)
+#define INTC_ICDICPR13_TINT14                   (0x00004000uL)
+#define INTC_ICDICPR13_TINT15                   (0x00008000uL)
+#define INTC_ICDICPR13_TINT16                   (0x00010000uL)
+#define INTC_ICDICPR13_TINT17                   (0x00020000uL)
+#define INTC_ICDICPR13_TINT18                   (0x00040000uL)
+#define INTC_ICDICPR13_TINT19                   (0x00080000uL)
+#define INTC_ICDICPR13_TINT20                   (0x00100000uL)
+#define INTC_ICDICPR13_TINT21                   (0x00200000uL)
+#define INTC_ICDICPR13_TINT22                   (0x00400000uL)
+#define INTC_ICDICPR13_TINT23                   (0x00800000uL)
+#define INTC_ICDICPR13_TINT24                   (0x01000000uL)
+#define INTC_ICDICPR13_TINT25                   (0x02000000uL)
+#define INTC_ICDICPR13_TINT26                   (0x04000000uL)
+#define INTC_ICDICPR13_TINT27                   (0x08000000uL)
+#define INTC_ICDICPR13_TINT28                   (0x10000000uL)
+#define INTC_ICDICPR13_TINT29                   (0x20000000uL)
+#define INTC_ICDICPR13_TINT30                   (0x40000000uL)
+#define INTC_ICDICPR13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDICPR14_TINT32                   (0x00000001uL)
+#define INTC_ICDICPR14_TINT33                   (0x00000002uL)
+#define INTC_ICDICPR14_TINT34                   (0x00000004uL)
+#define INTC_ICDICPR14_TINT35                   (0x00000008uL)
+#define INTC_ICDICPR14_TINT36                   (0x00000010uL)
+#define INTC_ICDICPR14_TINT37                   (0x00000020uL)
+#define INTC_ICDICPR14_TINT38                   (0x00000040uL)
+#define INTC_ICDICPR14_TINT39                   (0x00000080uL)
+#define INTC_ICDICPR14_TINT40                   (0x00000100uL)
+#define INTC_ICDICPR14_TINT41                   (0x00000200uL)
+#define INTC_ICDICPR14_TINT42                   (0x00000400uL)
+#define INTC_ICDICPR14_TINT43                   (0x00000800uL)
+#define INTC_ICDICPR14_TINT44                   (0x00001000uL)
+#define INTC_ICDICPR14_TINT45                   (0x00002000uL)
+#define INTC_ICDICPR14_TINT46                   (0x00004000uL)
+#define INTC_ICDICPR14_TINT47                   (0x00008000uL)
+#define INTC_ICDICPR14_TINT48                   (0x00010000uL)
+#define INTC_ICDICPR14_TINT49                   (0x00020000uL)
+#define INTC_ICDICPR14_TINT50                   (0x00040000uL)
+#define INTC_ICDICPR14_TINT51                   (0x00080000uL)
+#define INTC_ICDICPR14_TINT52                   (0x00100000uL)
+#define INTC_ICDICPR14_TINT53                   (0x00200000uL)
+#define INTC_ICDICPR14_TINT54                   (0x00400000uL)
+#define INTC_ICDICPR14_TINT55                   (0x00800000uL)
+#define INTC_ICDICPR14_TINT56                   (0x01000000uL)
+#define INTC_ICDICPR14_TINT57                   (0x02000000uL)
+#define INTC_ICDICPR14_TINT58                   (0x04000000uL)
+#define INTC_ICDICPR14_TINT59                   (0x08000000uL)
+#define INTC_ICDICPR14_TINT60                   (0x10000000uL)
+#define INTC_ICDICPR14_TINT61                   (0x20000000uL)
+#define INTC_ICDICPR14_TINT62                   (0x40000000uL)
+#define INTC_ICDICPR14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDICPR15_TINT64                   (0x00000001uL)
+#define INTC_ICDICPR15_TINT65                   (0x00000002uL)
+#define INTC_ICDICPR15_TINT66                   (0x00000004uL)
+#define INTC_ICDICPR15_TINT67                   (0x00000008uL)
+#define INTC_ICDICPR15_TINT68                   (0x00000010uL)
+#define INTC_ICDICPR15_TINT69                   (0x00000020uL)
+#define INTC_ICDICPR15_TINT70                   (0x00000040uL)
+#define INTC_ICDICPR15_TINT71                   (0x00000080uL)
+#define INTC_ICDICPR15_TINT72                   (0x00000100uL)
+#define INTC_ICDICPR15_TINT73                   (0x00000200uL)
+#define INTC_ICDICPR15_TINT74                   (0x00000400uL)
+#define INTC_ICDICPR15_TINT75                   (0x00000800uL)
+#define INTC_ICDICPR15_TINT76                   (0x00001000uL)
+#define INTC_ICDICPR15_TINT77                   (0x00002000uL)
+#define INTC_ICDICPR15_TINT78                   (0x00004000uL)
+#define INTC_ICDICPR15_TINT79                   (0x00008000uL)
+#define INTC_ICDICPR15_TINT80                   (0x00010000uL)
+#define INTC_ICDICPR15_TINT81                   (0x00020000uL)
+#define INTC_ICDICPR15_TINT82                   (0x00040000uL)
+#define INTC_ICDICPR15_TINT83                   (0x00080000uL)
+#define INTC_ICDICPR15_TINT84                   (0x00100000uL)
+#define INTC_ICDICPR15_TINT85                   (0x00200000uL)
+#define INTC_ICDICPR15_TINT86                   (0x00400000uL)
+#define INTC_ICDICPR15_TINT87                   (0x00800000uL)
+#define INTC_ICDICPR15_TINT88                   (0x01000000uL)
+#define INTC_ICDICPR15_TINT89                   (0x02000000uL)
+#define INTC_ICDICPR15_TINT90                   (0x04000000uL)
+#define INTC_ICDICPR15_TINT91                   (0x08000000uL)
+#define INTC_ICDICPR15_TINT92                   (0x10000000uL)
+#define INTC_ICDICPR15_TINT93                   (0x20000000uL)
+#define INTC_ICDICPR15_TINT94                   (0x40000000uL)
+#define INTC_ICDICPR15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDICPR16_TINT96                   (0x00000001uL)
+#define INTC_ICDICPR16_TINT97                   (0x00000002uL)
+#define INTC_ICDICPR16_TINT98                   (0x00000004uL)
+#define INTC_ICDICPR16_TINT99                   (0x00000008uL)
+#define INTC_ICDICPR16_TINT100                  (0x00000010uL)
+#define INTC_ICDICPR16_TINT101                  (0x00000020uL)
+#define INTC_ICDICPR16_TINT102                  (0x00000040uL)
+#define INTC_ICDICPR16_TINT103                  (0x00000080uL)
+#define INTC_ICDICPR16_TINT104                  (0x00000100uL)
+#define INTC_ICDICPR16_TINT105                  (0x00000200uL)
+#define INTC_ICDICPR16_TINT106                  (0x00000400uL)
+#define INTC_ICDICPR16_TINT107                  (0x00000800uL)
+#define INTC_ICDICPR16_TINT108                  (0x00001000uL)
+#define INTC_ICDICPR16_TINT109                  (0x00002000uL)
+#define INTC_ICDICPR16_TINT110                  (0x00004000uL)
+#define INTC_ICDICPR16_TINT111                  (0x00008000uL)
+#define INTC_ICDICPR16_TINT112                  (0x00010000uL)
+#define INTC_ICDICPR16_TINT113                  (0x00020000uL)
+#define INTC_ICDICPR16_TINT114                  (0x00040000uL)
+#define INTC_ICDICPR16_TINT115                  (0x00080000uL)
+#define INTC_ICDICPR16_TINT116                  (0x00100000uL)
+#define INTC_ICDICPR16_TINT117                  (0x00200000uL)
+#define INTC_ICDICPR16_TINT118                  (0x00400000uL)
+#define INTC_ICDICPR16_TINT119                  (0x00800000uL)
+#define INTC_ICDICPR16_TINT120                  (0x01000000uL)
+#define INTC_ICDICPR16_TINT121                  (0x02000000uL)
+#define INTC_ICDICPR16_TINT122                  (0x04000000uL)
+#define INTC_ICDICPR16_TINT123                  (0x08000000uL)
+#define INTC_ICDICPR16_TINT124                  (0x10000000uL)
+#define INTC_ICDICPR16_TINT125                  (0x20000000uL)
+#define INTC_ICDICPR16_TINT126                  (0x40000000uL)
+#define INTC_ICDICPR16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDICPR17_TINT128                  (0x00000001uL)
+#define INTC_ICDICPR17_TINT129                  (0x00000002uL)
+#define INTC_ICDICPR17_TINT130                  (0x00000004uL)
+#define INTC_ICDICPR17_TINT131                  (0x00000008uL)
+#define INTC_ICDICPR17_TINT132                  (0x00000010uL)
+#define INTC_ICDICPR17_TINT133                  (0x00000020uL)
+#define INTC_ICDICPR17_TINT134                  (0x00000040uL)
+#define INTC_ICDICPR17_TINT135                  (0x00000080uL)
+#define INTC_ICDICPR17_TINT136                  (0x00000100uL)
+#define INTC_ICDICPR17_TINT137                  (0x00000200uL)
+#define INTC_ICDICPR17_TINT138                  (0x00000400uL)
+#define INTC_ICDICPR17_TINT139                  (0x00000800uL)
+#define INTC_ICDICPR17_TINT140                  (0x00001000uL)
+#define INTC_ICDICPR17_TINT141                  (0x00002000uL)
+#define INTC_ICDICPR17_TINT142                  (0x00004000uL)
+#define INTC_ICDICPR17_TINT143                  (0x00008000uL)
+#define INTC_ICDICPR17_TINT144                  (0x00010000uL)
+#define INTC_ICDICPR17_TINT145                  (0x00020000uL)
+#define INTC_ICDICPR17_TINT146                  (0x00040000uL)
+#define INTC_ICDICPR17_TINT147                  (0x00080000uL)
+#define INTC_ICDICPR17_TINT148                  (0x00100000uL)
+#define INTC_ICDICPR17_TINT149                  (0x00200000uL)
+#define INTC_ICDICPR17_TINT150                  (0x00400000uL)
+#define INTC_ICDICPR17_TINT151                  (0x00800000uL)
+#define INTC_ICDICPR17_TINT152                  (0x01000000uL)
+#define INTC_ICDICPR17_TINT153                  (0x02000000uL)
+#define INTC_ICDICPR17_TINT154                  (0x04000000uL)
+#define INTC_ICDICPR17_TINT155                  (0x08000000uL)
+#define INTC_ICDICPR17_TINT156                  (0x10000000uL)
+#define INTC_ICDICPR17_TINT157                  (0x20000000uL)
+#define INTC_ICDICPR17_TINT158                  (0x40000000uL)
+#define INTC_ICDICPR17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDICPR18_TINT160                  (0x00000001uL)
+#define INTC_ICDICPR18_TINT161                  (0x00000002uL)
+#define INTC_ICDICPR18_TINT162                  (0x00000004uL)
+#define INTC_ICDICPR18_TINT163                  (0x00000008uL)
+#define INTC_ICDICPR18_TINT164                  (0x00000010uL)
+#define INTC_ICDICPR18_TINT165                  (0x00000020uL)
+#define INTC_ICDICPR18_TINT166                  (0x00000040uL)
+#define INTC_ICDICPR18_TINT167                  (0x00000080uL)
+#define INTC_ICDICPR18_TINT168                  (0x00000100uL)
+#define INTC_ICDICPR18_TINT169                  (0x00000200uL)
+#define INTC_ICDICPR18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDABR0_SW0                        (0x00000001uL)
+#define INTC_ICDABR0_SW1                        (0x00000002uL)
+#define INTC_ICDABR0_SW2                        (0x00000004uL)
+#define INTC_ICDABR0_SW3                        (0x00000008uL)
+#define INTC_ICDABR0_SW4                        (0x00000010uL)
+#define INTC_ICDABR0_SW5                        (0x00000020uL)
+#define INTC_ICDABR0_SW6                        (0x00000040uL)
+#define INTC_ICDABR0_SW7                        (0x00000080uL)
+#define INTC_ICDABR0_SW8                        (0x00000100uL)
+#define INTC_ICDABR0_SW9                        (0x00000200uL)
+#define INTC_ICDABR0_SW10                       (0x00000400uL)
+#define INTC_ICDABR0_SW11                       (0x00000800uL)
+#define INTC_ICDABR0_SW12                       (0x00001000uL)
+#define INTC_ICDABR0_SW13                       (0x00002000uL)
+#define INTC_ICDABR0_SW14                       (0x00004000uL)
+#define INTC_ICDABR0_SW15                       (0x00008000uL)
+#define INTC_ICDABR0_PMUIRQ0                    (0x00010000uL)
+#define INTC_ICDABR0_COMMRX0                    (0x00020000uL)
+#define INTC_ICDABR0_COMMTX0                    (0x00040000uL)
+#define INTC_ICDABR0_CTIIRQ0                    (0x00080000uL)
+
+#define INTC_ICDABR1_IRQ0                       (0x00000001uL)
+#define INTC_ICDABR1_IRQ1                       (0x00000002uL)
+#define INTC_ICDABR1_IRQ2                       (0x00000004uL)
+#define INTC_ICDABR1_IRQ3                       (0x00000008uL)
+#define INTC_ICDABR1_IRQ4                       (0x00000010uL)
+#define INTC_ICDABR1_IRQ5                       (0x00000020uL)
+#define INTC_ICDABR1_IRQ6                       (0x00000040uL)
+#define INTC_ICDABR1_IRQ7                       (0x00000080uL)
+#define INTC_ICDABR1_PL310ERR                   (0x00000100uL)
+#define INTC_ICDABR1_DMAINT0                    (0x00000200uL)
+#define INTC_ICDABR1_DMAINT1                    (0x00000400uL)
+#define INTC_ICDABR1_DMAINT2                    (0x00000800uL)
+#define INTC_ICDABR1_DMAINT3                    (0x00001000uL)
+#define INTC_ICDABR1_DMAINT4                    (0x00002000uL)
+#define INTC_ICDABR1_DMAINT5                    (0x00004000uL)
+#define INTC_ICDABR1_DMAINT6                    (0x00008000uL)
+#define INTC_ICDABR1_DMAINT7                    (0x00010000uL)
+#define INTC_ICDABR1_DMAINT8                    (0x00020000uL)
+#define INTC_ICDABR1_DMAINT9                    (0x00040000uL)
+#define INTC_ICDABR1_DMAINT10                   (0x00080000uL)
+#define INTC_ICDABR1_DMAINT11                   (0x00100000uL)
+#define INTC_ICDABR1_DMAINT12                   (0x00200000uL)
+#define INTC_ICDABR1_DMAINT13                   (0x00400000uL)
+#define INTC_ICDABR1_DMAINT14                   (0x00800000uL)
+#define INTC_ICDABR1_DMAINT15                   (0x01000000uL)
+#define INTC_ICDABR1_DMAERR                     (0x02000000uL)
+
+#define INTC_ICDABR2_USBI0                      (0x00000200uL)
+#define INTC_ICDABR2_USBI1                      (0x00000400uL)
+#define INTC_ICDABR2_S0_VI_VSYNC0               (0x00000800uL)
+#define INTC_ICDABR2_S0_LO_VSYNC0               (0x00001000uL)
+#define INTC_ICDABR2_S0_VSYNCERR0               (0x00002000uL)
+#define INTC_ICDABR2_GR3_VLINE0                 (0x00004000uL)
+#define INTC_ICDABR2_S0_VFIELD0                 (0x00008000uL)
+#define INTC_ICDABR2_IV1_VBUFERR0               (0x00010000uL)
+#define INTC_ICDABR2_IV3_VBUFERR0               (0x00020000uL)
+#define INTC_ICDABR2_IV5_VBUFERR0               (0x00040000uL)
+#define INTC_ICDABR2_IV6_VBUFERR0               (0x00080000uL)
+#define INTC_ICDABR2_S0_WLINE0                  (0x00100000uL)
+#define INTC_ICDABR2_S1_VI_VSYNC0               (0x00200000uL)
+#define INTC_ICDABR2_S1_LO_VSYNC0               (0x00400000uL)
+#define INTC_ICDABR2_S1_VSYNCERR0               (0x00800000uL)
+#define INTC_ICDABR2_S1_VFIELD0                 (0x01000000uL)
+#define INTC_ICDABR2_IV2_VBUFERR0               (0x02000000uL)
+#define INTC_ICDABR2_IV4_VBUFERR0               (0x04000000uL)
+#define INTC_ICDABR2_S1_WLINE0                  (0x08000000uL)
+#define INTC_ICDABR2_OIR_VI_VSYNC0              (0x10000000uL)
+#define INTC_ICDABR2_OIR_LO_VSYNC0              (0x20000000uL)
+#define INTC_ICDABR2_OIR_VSYNCERR0              (0x40000000uL)
+#define INTC_ICDABR2_OIR_VFIELD0                (0x80000000uL)
+
+#define INTC_ICDABR3_IV7_VBUFERR0               (0x00000001uL)
+#define INTC_ICDABR3_IV8_VBUFERR0               (0x00000002uL)
+#define INTC_ICDABR3_S0_VI_VSYNC1               (0x00000008uL)
+#define INTC_ICDABR3_S0_LO_VSYNC1               (0x00000010uL)
+#define INTC_ICDABR3_S0_VSYNCERR1               (0x00000020uL)
+#define INTC_ICDABR3_GR3_VLINE1                 (0x00000040uL)
+#define INTC_ICDABR3_S0_VFIELD1                 (0x00000080uL)
+#define INTC_ICDABR3_IV1_VBUFERR1               (0x00000100uL)
+#define INTC_ICDABR3_IV3_VBUFERR1               (0x00000200uL)
+#define INTC_ICDABR3_IV5_VBUFERR1               (0x00000400uL)
+#define INTC_ICDABR3_IV6_VBUFERR1               (0x00000800uL)
+#define INTC_ICDABR3_S0_WLINE1                  (0x00001000uL)
+#define INTC_ICDABR3_S1_VI_VSYNC1               (0x00002000uL)
+#define INTC_ICDABR3_S1_LO_VSYNC1               (0x00004000uL)
+#define INTC_ICDABR3_S1_VSYNCERR1               (0x00008000uL)
+#define INTC_ICDABR3_S1_VFIELD1                 (0x00010000uL)
+#define INTC_ICDABR3_IV2_VBUFERR1               (0x00020000uL)
+#define INTC_ICDABR3_IV4_VBUFERR1               (0x00040000uL)
+#define INTC_ICDABR3_S1_WLINE1                  (0x00080000uL)
+#define INTC_ICDABR3_OIR_VI_VSYNC1              (0x00100000uL)
+#define INTC_ICDABR3_OIR_LO_VSYNC1              (0x00200000uL)
+#define INTC_ICDABR3_OIR_VLINE1                 (0x00400000uL)
+#define INTC_ICDABR3_OIR_VFIELD1                (0x00800000uL)
+#define INTC_ICDABR3_IV7_VBUFERR1               (0x01000000uL)
+#define INTC_ICDABR3_IV8_VBUFERR1               (0x02000000uL)
+#define INTC_ICDABR3_IMRDI                      (0x08000000uL)
+#define INTC_ICDABR3_IMR2I0                     (0x10000000uL)
+#define INTC_ICDABR3_IMR2I1                     (0x20000000uL)
+#define INTC_ICDABR3_JEDI                       (0x40000000uL)
+#define INTC_ICDABR3_JDTI                       (0x80000000uL)
+
+#define INTC_ICDABR4_CMP0                       (0x00000001uL)
+#define INTC_ICDABR4_CMP1                       (0x00000002uL)
+#define INTC_ICDABR4_INT0                       (0x00000004uL)
+#define INTC_ICDABR4_INT1                       (0x00000008uL)
+#define INTC_ICDABR4_INT2                       (0x00000010uL)
+#define INTC_ICDABR4_INT3                       (0x00000020uL)
+#define INTC_ICDABR4_OSTM0TINT                  (0x00000040uL)
+#define INTC_ICDABR4_OSTM1TINT                  (0x00000080uL)
+#define INTC_ICDABR4_CMI                        (0x00000100uL)
+#define INTC_ICDABR4_WTOUT                      (0x00000200uL)
+#define INTC_ICDABR4_ITI                        (0x00000400uL)
+#define INTC_ICDABR4_TGI0A                      (0x00000800uL)
+#define INTC_ICDABR4_TGI0B                      (0x00001000uL)
+#define INTC_ICDABR4_TGI0C                      (0x00002000uL)
+#define INTC_ICDABR4_TGI0D                      (0x00004000uL)
+#define INTC_ICDABR4_TGI0V                      (0x00008000uL)
+#define INTC_ICDABR4_TGI0E                      (0x00010000uL)
+#define INTC_ICDABR4_TGI0F                      (0x00020000uL)
+#define INTC_ICDABR4_TGI1A                      (0x00040000uL)
+#define INTC_ICDABR4_TGI1B                      (0x00080000uL)
+#define INTC_ICDABR4_TGI1V                      (0x00100000uL)
+#define INTC_ICDABR4_TGI1U                      (0x00200000uL)
+#define INTC_ICDABR4_TGI2A                      (0x00400000uL)
+#define INTC_ICDABR4_TGI2B                      (0x00800000uL)
+#define INTC_ICDABR4_TGI2V                      (0x01000000uL)
+#define INTC_ICDABR4_TGI2U                      (0x02000000uL)
+#define INTC_ICDABR4_TGI3A                      (0x04000000uL)
+#define INTC_ICDABR4_TGI3B                      (0x08000000uL)
+#define INTC_ICDABR4_TGI3C                      (0x10000000uL)
+#define INTC_ICDABR4_TGI3D                      (0x20000000uL)
+#define INTC_ICDABR4_TGI3V                      (0x40000000uL)
+#define INTC_ICDABR4_TGI4A                      (0x80000000uL)
+
+#define INTC_ICDABR5_TGI4B                      (0x00000001uL)
+#define INTC_ICDABR5_TGI4C                      (0x00000002uL)
+#define INTC_ICDABR5_TGI4D                      (0x00000004uL)
+#define INTC_ICDABR5_TGI4V                      (0x00000008uL)
+#define INTC_ICDABR5_CMI1                       (0x00000010uL)
+#define INTC_ICDABR5_CMI2                       (0x00000020uL)
+#define INTC_ICDABR5_SGDEI0                     (0x00000040uL)
+#define INTC_ICDABR5_SGDEI1                     (0x00000080uL)
+#define INTC_ICDABR5_SGDEI2                     (0x00000100uL)
+#define INTC_ICDABR5_SGDEI3                     (0x00000200uL)
+#define INTC_ICDABR5_ADI                        (0x00000400uL)
+#define INTC_ICDABR5_LMTI                       (0x00000800uL)
+#define INTC_ICDABR5_SSII0                      (0x00001000uL)
+#define INTC_ICDABR5_SSIRXI0                    (0x00002000uL)
+#define INTC_ICDABR5_SSITXI0                    (0x00004000uL)
+#define INTC_ICDABR5_SSII1                      (0x00008000uL)
+#define INTC_ICDABR5_SSIRXI1                    (0x00010000uL)
+#define INTC_ICDABR5_SSITXI1                    (0x00020000uL)
+#define INTC_ICDABR5_SSII2                      (0x00040000uL)
+#define INTC_ICDABR5_SSIRTI2                    (0x00080000uL)
+#define INTC_ICDABR5_SSII3                      (0x00100000uL)
+#define INTC_ICDABR5_SSIRXI3                    (0x00200000uL)
+#define INTC_ICDABR5_SSITXI3                    (0x00400000uL)
+#define INTC_ICDABR5_SSII4                      (0x00800000uL)
+#define INTC_ICDABR5_SSIRTI4                    (0x01000000uL)
+#define INTC_ICDABR5_SSII5                      (0x02000000uL)
+#define INTC_ICDABR5_SSIRXI5                    (0x04000000uL)
+#define INTC_ICDABR5_SSITXI5                    (0x08000000uL)
+#define INTC_ICDABR5_SPDIFI                     (0x10000000uL)
+#define INTC_ICDABR5_INTIICTEI0                 (0x20000000uL)
+#define INTC_ICDABR5_INTIICRI0                  (0x40000000uL)
+#define INTC_ICDABR5_INTIICTI0                  (0x80000000uL)
+
+#define INTC_ICDABR6_INTIICSPI0                 (0x00000001uL)
+#define INTC_ICDABR6_INTIICSTI0                 (0x00000002uL)
+#define INTC_ICDABR6_INTIICNAKI0                (0x00000004uL)
+#define INTC_ICDABR6_INTIICALI0                 (0x00000008uL)
+#define INTC_ICDABR6_INTIICTMOI0                (0x00000010uL)
+#define INTC_ICDABR6_INTIICTEI1                 (0x00000020uL)
+#define INTC_ICDABR6_INTIICRI1                  (0x00000040uL)
+#define INTC_ICDABR6_INTIICTI1                  (0x00000080uL)
+#define INTC_ICDABR6_INTIICSPI1                 (0x00000100uL)
+#define INTC_ICDABR6_INTIICSTI1                 (0x00000200uL)
+#define INTC_ICDABR6_INTIICNAKI1                (0x00000400uL)
+#define INTC_ICDABR6_INTIICALI1                 (0x00000800uL)
+#define INTC_ICDABR6_INTIICTMOI1                (0x00001000uL)
+#define INTC_ICDABR6_INTIICTEI2                 (0x00002000uL)
+#define INTC_ICDABR6_INTIICRI2                  (0x00004000uL)
+#define INTC_ICDABR6_INTIICTI2                  (0x00008000uL)
+#define INTC_ICDABR6_INTIICSPI2                 (0x00010000uL)
+#define INTC_ICDABR6_INTIICSTI2                 (0x00020000uL)
+#define INTC_ICDABR6_INTIICNAKI2                (0x00040000uL)
+#define INTC_ICDABR6_INTIICALI2                 (0x00080000uL)
+#define INTC_ICDABR6_INTIICTMOI2                (0x00100000uL)
+#define INTC_ICDABR6_INTIICTEI3                 (0x00200000uL)
+#define INTC_ICDABR6_INTIICRI3                  (0x00400000uL)
+#define INTC_ICDABR6_INTIICTI3                  (0x00800000uL)
+#define INTC_ICDABR6_INTIICSPI3                 (0x01000000uL)
+#define INTC_ICDABR6_INTIICSTI3                 (0x02000000uL)
+#define INTC_ICDABR6_INTIICNAKI3                (0x04000000uL)
+#define INTC_ICDABR6_INTIICALI3                 (0x08000000uL)
+#define INTC_ICDABR6_INTIICTMOI3                (0x10000000uL)
+#define INTC_ICDABR6_BRI0                       (0x20000000uL)
+#define INTC_ICDABR6_ERI0                       (0x40000000uL)
+#define INTC_ICDABR6_RXI0                       (0x80000000uL)
+
+#define INTC_ICDABR7_TXI0                       (0x00000001uL)
+#define INTC_ICDABR7_BRI1                       (0x00000002uL)
+#define INTC_ICDABR7_ERI1                       (0x00000004uL)
+#define INTC_ICDABR7_RXI1                       (0x00000008uL)
+#define INTC_ICDABR7_TXI1                       (0x00000010uL)
+#define INTC_ICDABR7_BRI2                       (0x00000020uL)
+#define INTC_ICDABR7_ERI2                       (0x00000040uL)
+#define INTC_ICDABR7_RXI2                       (0x00000080uL)
+#define INTC_ICDABR7_TXI2                       (0x00000100uL)
+#define INTC_ICDABR7_BRI3                       (0x00000200uL)
+#define INTC_ICDABR7_ERI3                       (0x00000400uL)
+#define INTC_ICDABR7_RXI3                       (0x00000800uL)
+#define INTC_ICDABR7_TXI3                       (0x00001000uL)
+#define INTC_ICDABR7_BRI4                       (0x00002000uL)
+#define INTC_ICDABR7_ERI4                       (0x00004000uL)
+#define INTC_ICDABR7_RXI4                       (0x00008000uL)
+#define INTC_ICDABR7_TXI4                       (0x00010000uL)
+#define INTC_ICDABR7_BRI5                       (0x00020000uL)
+#define INTC_ICDABR7_ERI5                       (0x00040000uL)
+#define INTC_ICDABR7_RXI5                       (0x00080000uL)
+#define INTC_ICDABR7_TXI5                       (0x00100000uL)
+#define INTC_ICDABR7_BRI6                       (0x00200000uL)
+#define INTC_ICDABR7_ERI6                       (0x00400000uL)
+#define INTC_ICDABR7_RXI6                       (0x00800000uL)
+#define INTC_ICDABR7_TXI6                       (0x01000000uL)
+#define INTC_ICDABR7_BRI7                       (0x02000000uL)
+#define INTC_ICDABR7_ERI7                       (0x04000000uL)
+#define INTC_ICDABR7_RXI7                       (0x08000000uL)
+#define INTC_ICDABR7_TXI7                       (0x10000000uL)
+#define INTC_ICDABR7_INTRCANGERR                (0x20000000uL)
+#define INTC_ICDABR7_INTRCANGRECC               (0x40000000uL)
+#define INTC_ICDABR7_INTRCAN0REC                (0x80000000uL)
+
+#define INTC_ICDABR8_INTRCAN0ERR                (0x00000001uL)
+#define INTC_ICDABR8_INTRCAN0TRX                (0x00000002uL)
+#define INTC_ICDABR8_INTRCAN1REC                (0x00000004uL)
+#define INTC_ICDABR8_INTRCAN1ERR                (0x00000008uL)
+#define INTC_ICDABR8_INTRCAN1TRX                (0x00000010uL)
+#define INTC_ICDABR8_INTRCAN2REC                (0x00000020uL)
+#define INTC_ICDABR8_INTRCAN2ERR                (0x00000040uL)
+#define INTC_ICDABR8_INTRCAN2TRX                (0x00000080uL)
+#define INTC_ICDABR8_INTRCAN3REC                (0x00000100uL)
+#define INTC_ICDABR8_INTRCAN3ERR                (0x00000200uL)
+#define INTC_ICDABR8_INTRCAN3TRX                (0x00000400uL)
+#define INTC_ICDABR8_INTRCAN4REC                (0x00000800uL)
+#define INTC_ICDABR8_INTRCAN4ERR                (0x00001000uL)
+#define INTC_ICDABR8_INTRCAN4TRX                (0x00002000uL)
+#define INTC_ICDABR8_SPEI0                      (0x00004000uL)
+#define INTC_ICDABR8_SPRI0                      (0x00008000uL)
+#define INTC_ICDABR8_SPTI0                      (0x00010000uL)
+#define INTC_ICDABR8_SPEI1                      (0x00020000uL)
+#define INTC_ICDABR8_SPRI1                      (0x00040000uL)
+#define INTC_ICDABR8_SPTI1                      (0x00080000uL)
+#define INTC_ICDABR8_SPEI2                      (0x00100000uL)
+#define INTC_ICDABR8_SPRI2                      (0x00200000uL)
+#define INTC_ICDABR8_SPTI2                      (0x00400000uL)
+#define INTC_ICDABR8_SPEI3                      (0x00800000uL)
+#define INTC_ICDABR8_SPRI3                      (0x01000000uL)
+#define INTC_ICDABR8_SPTI3                      (0x02000000uL)
+#define INTC_ICDABR8_SPEI4                      (0x04000000uL)
+#define INTC_ICDABR8_SPRI4                      (0x08000000uL)
+#define INTC_ICDABR8_SPTI4                      (0x10000000uL)
+#define INTC_ICDABR8_IEBBTD                     (0x20000000uL)
+#define INTC_ICDABR8_IEBBTERR                   (0x40000000uL)
+#define INTC_ICDABR8_IEBBTSTA                   (0x80000000uL)
+
+#define INTC_ICDABR9_IEBBTV                     (0x00000001uL)
+#define INTC_ICDABR9_ISY                        (0x00000002uL)
+#define INTC_ICDABR9_IERR                       (0x00000004uL)
+#define INTC_ICDABR9_ITARG                      (0x00000008uL)
+#define INTC_ICDABR9_ISEC                       (0x00000010uL)
+#define INTC_ICDABR9_IBUF                       (0x00000020uL)
+#define INTC_ICDABR9_IREADY                     (0x00000040uL)
+#define INTC_ICDABR9_FLSTE                      (0x00000080uL)
+#define INTC_ICDABR9_FLTENDI                    (0x00000100uL)
+#define INTC_ICDABR9_FLTREQ0I                   (0x00000200uL)
+#define INTC_ICDABR9_FLTREQ1I                   (0x00000400uL)
+#define INTC_ICDABR9_MMC0                       (0x00000800uL)
+#define INTC_ICDABR9_MMC1                       (0x00001000uL)
+#define INTC_ICDABR9_MMC2                       (0x00002000uL)
+#define INTC_ICDABR9_SDHI0_3                    (0x00004000uL)
+#define INTC_ICDABR9_SDHI0_0                    (0x00008000uL)
+#define INTC_ICDABR9_SDHI0_1                    (0x00010000uL)
+#define INTC_ICDABR9_SDHI1_3                    (0x00020000uL)
+#define INTC_ICDABR9_SDHI1_0                    (0x00040000uL)
+#define INTC_ICDABR9_SDHI1_1                    (0x00080000uL)
+#define INTC_ICDABR9_ARM                        (0x00100000uL)
+#define INTC_ICDABR9_PRD                        (0x00200000uL)
+#define INTC_ICDABR9_CUP                        (0x00400000uL)
+#define INTC_ICDABR9_SCUAI0                     (0x00800000uL)
+#define INTC_ICDABR9_SCUAI1                     (0x01000000uL)
+#define INTC_ICDABR9_SCUFDI0                    (0x02000000uL)
+#define INTC_ICDABR9_SCUFDI1                    (0x04000000uL)
+#define INTC_ICDABR9_SCUFDI2                    (0x08000000uL)
+#define INTC_ICDABR9_SCUFDI3                    (0x10000000uL)
+#define INTC_ICDABR9_SCUFUI0                    (0x20000000uL)
+#define INTC_ICDABR9_SCUFUI1                    (0x40000000uL)
+#define INTC_ICDABR9_SCUFUI2                    (0x80000000uL)
+
+#define INTC_ICDABR10_SCUFUI3                   (0x00000001uL)
+#define INTC_ICDABR10_SCUDVI0                   (0x00000002uL)
+#define INTC_ICDABR10_SCUDVI1                   (0x00000004uL)
+#define INTC_ICDABR10_SCUDVI2                   (0x00000008uL)
+#define INTC_ICDABR10_SCUDVI3                   (0x00000010uL)
+#define INTC_ICDABR10_MLB_CINT                  (0x00000020uL)
+#define INTC_ICDABR10_MLB_SINT                  (0x00000040uL)
+#define INTC_ICDABR10_DRC0                      (0x00000080uL)
+#define INTC_ICDABR10_DRC1                      (0x00000100uL)
+#define INTC_ICDABR10_LINI0_INT_T               (0x00000800uL)
+#define INTC_ICDABR10_LINI0_INT_R               (0x00001000uL)
+#define INTC_ICDABR10_LINI0_INT_S               (0x00002000uL)
+#define INTC_ICDABR10_LINI0_INT_M               (0x00004000uL)
+#define INTC_ICDABR10_LINI1_INT_T               (0x00008000uL)
+#define INTC_ICDABR10_LINI1_INT_R               (0x00010000uL)
+#define INTC_ICDABR10_LINI1_INT_S               (0x00020000uL)
+#define INTC_ICDABR10_LINI1_INT_M               (0x00040000uL)
+#define INTC_ICDABR10_ERI0                      (0x08000000uL)
+#define INTC_ICDABR10_RXI0                      (0x10000000uL)
+#define INTC_ICDABR10_TXI0                      (0x20000000uL)
+#define INTC_ICDABR10_TEI0                      (0x40000000uL)
+#define INTC_ICDABR10_ERI1                      (0x80000000uL)
+
+#define INTC_ICDABR11_RXI1                      (0x00000001uL)
+#define INTC_ICDABR11_TXI1                      (0x00000002uL)
+#define INTC_ICDABR11_TEI1                      (0x00000004uL)
+#define INTC_ICDABR11_AVBI_DATA                 (0x00000008uL)
+#define INTC_ICDABR11_AVBI_ERROR                (0x00000010uL)
+#define INTC_ICDABR11_AVBI_MANAGE               (0x00000020uL)
+#define INTC_ICDABR11_AVBI_MAC                  (0x00000040uL)
+#define INTC_ICDABR11_ETHERI                    (0x00000080uL)
+#define INTC_ICDABR11_CEUI                      (0x00001000uL)
+#define INTC_ICDABR11_H2XMLB_ERRINT             (0x20000000uL)
+#define INTC_ICDABR11_H2XIC1_ERRINT             (0x40000000uL)
+#define INTC_ICDABR11_X2HPERI1_ERRINT           (0x80000000uL)
+
+#define INTC_ICDABR12_X2HPERI2_ERRINT           (0x00000001uL)
+#define INTC_ICDABR12_X2HPERI34_ERRINT          (0x00000002uL)
+#define INTC_ICDABR12_X2HPERI5_ERRINT           (0x00000004uL)
+#define INTC_ICDABR12_X2HPERI67_ERRINT          (0x00000008uL)
+#define INTC_ICDABR12_X2HDBGR_ERRINT            (0x00000010uL)
+#define INTC_ICDABR12_X2HBSC_ERRINT             (0x00000020uL)
+#define INTC_ICDABR12_X2HSPI1_ERRINT            (0x00000040uL)
+#define INTC_ICDABR12_X2HSPI2_ERRINT            (0x00000080uL)
+#define INTC_ICDABR12_PRRI                      (0x00000100uL)
+#define INTC_ICDABR12_IFEI0                     (0x00000200uL)
+#define INTC_ICDABR12_OFFI0                     (0x00000400uL)
+#define INTC_ICDABR12_PFVEI0                    (0x00000800uL)
+#define INTC_ICDABR12_IFEI1                     (0x00001000uL)
+#define INTC_ICDABR12_OFFI1                     (0x00002000uL)
+#define INTC_ICDABR12_PFVEI1                    (0x00004000uL)
+
+#define INTC_ICDABR13_TINT0                     (0x00000001uL)
+#define INTC_ICDABR13_TINT1                     (0x00000002uL)
+#define INTC_ICDABR13_TINT2                     (0x00000004uL)
+#define INTC_ICDABR13_TINT3                     (0x00000008uL)
+#define INTC_ICDABR13_TINT4                     (0x00000010uL)
+#define INTC_ICDABR13_TINT5                     (0x00000020uL)
+#define INTC_ICDABR13_TINT6                     (0x00000040uL)
+#define INTC_ICDABR13_TINT7                     (0x00000080uL)
+#define INTC_ICDABR13_TINT8                     (0x00000100uL)
+#define INTC_ICDABR13_TINT9                     (0x00000200uL)
+#define INTC_ICDABR13_TINT10                    (0x00000400uL)
+#define INTC_ICDABR13_TINT11                    (0x00000800uL)
+#define INTC_ICDABR13_TINT12                    (0x00001000uL)
+#define INTC_ICDABR13_TINT13                    (0x00002000uL)
+#define INTC_ICDABR13_TINT14                    (0x00004000uL)
+#define INTC_ICDABR13_TINT15                    (0x00008000uL)
+#define INTC_ICDABR13_TINT16                    (0x00010000uL)
+#define INTC_ICDABR13_TINT17                    (0x00020000uL)
+#define INTC_ICDABR13_TINT18                    (0x00040000uL)
+#define INTC_ICDABR13_TINT19                    (0x00080000uL)
+#define INTC_ICDABR13_TINT20                    (0x00100000uL)
+#define INTC_ICDABR13_TINT21                    (0x00200000uL)
+#define INTC_ICDABR13_TINT22                    (0x00400000uL)
+#define INTC_ICDABR13_TINT23                    (0x00800000uL)
+#define INTC_ICDABR13_TINT24                    (0x01000000uL)
+#define INTC_ICDABR13_TINT25                    (0x02000000uL)
+#define INTC_ICDABR13_TINT26                    (0x04000000uL)
+#define INTC_ICDABR13_TINT27                    (0x08000000uL)
+#define INTC_ICDABR13_TINT28                    (0x10000000uL)
+#define INTC_ICDABR13_TINT29                    (0x20000000uL)
+#define INTC_ICDABR13_TINT30                    (0x40000000uL)
+#define INTC_ICDABR13_TINT31                    (0x80000000uL)
+
+#define INTC_ICDABR14_TINT32                    (0x00000001uL)
+#define INTC_ICDABR14_TINT33                    (0x00000002uL)
+#define INTC_ICDABR14_TINT34                    (0x00000004uL)
+#define INTC_ICDABR14_TINT35                    (0x00000008uL)
+#define INTC_ICDABR14_TINT36                    (0x00000010uL)
+#define INTC_ICDABR14_TINT37                    (0x00000020uL)
+#define INTC_ICDABR14_TINT38                    (0x00000040uL)
+#define INTC_ICDABR14_TINT39                    (0x00000080uL)
+#define INTC_ICDABR14_TINT40                    (0x00000100uL)
+#define INTC_ICDABR14_TINT41                    (0x00000200uL)
+#define INTC_ICDABR14_TINT42                    (0x00000400uL)
+#define INTC_ICDABR14_TINT43                    (0x00000800uL)
+#define INTC_ICDABR14_TINT44                    (0x00001000uL)
+#define INTC_ICDABR14_TINT45                    (0x00002000uL)
+#define INTC_ICDABR14_TINT46                    (0x00004000uL)
+#define INTC_ICDABR14_TINT47                    (0x00008000uL)
+#define INTC_ICDABR14_TINT48                    (0x00010000uL)
+#define INTC_ICDABR14_TINT49                    (0x00020000uL)
+#define INTC_ICDABR14_TINT50                    (0x00040000uL)
+#define INTC_ICDABR14_TINT51                    (0x00080000uL)
+#define INTC_ICDABR14_TINT52                    (0x00100000uL)
+#define INTC_ICDABR14_TINT53                    (0x00200000uL)
+#define INTC_ICDABR14_TINT54                    (0x00400000uL)
+#define INTC_ICDABR14_TINT55                    (0x00800000uL)
+#define INTC_ICDABR14_TINT56                    (0x01000000uL)
+#define INTC_ICDABR14_TINT57                    (0x02000000uL)
+#define INTC_ICDABR14_TINT58                    (0x04000000uL)
+#define INTC_ICDABR14_TINT59                    (0x08000000uL)
+#define INTC_ICDABR14_TINT60                    (0x10000000uL)
+#define INTC_ICDABR14_TINT61                    (0x20000000uL)
+#define INTC_ICDABR14_TINT62                    (0x40000000uL)
+#define INTC_ICDABR14_TINT63                    (0x80000000uL)
+
+#define INTC_ICDABR15_TINT64                    (0x00000001uL)
+#define INTC_ICDABR15_TINT65                    (0x00000002uL)
+#define INTC_ICDABR15_TINT66                    (0x00000004uL)
+#define INTC_ICDABR15_TINT67                    (0x00000008uL)
+#define INTC_ICDABR15_TINT68                    (0x00000010uL)
+#define INTC_ICDABR15_TINT69                    (0x00000020uL)
+#define INTC_ICDABR15_TINT70                    (0x00000040uL)
+#define INTC_ICDABR15_TINT71                    (0x00000080uL)
+#define INTC_ICDABR15_TINT72                    (0x00000100uL)
+#define INTC_ICDABR15_TINT73                    (0x00000200uL)
+#define INTC_ICDABR15_TINT74                    (0x00000400uL)
+#define INTC_ICDABR15_TINT75                    (0x00000800uL)
+#define INTC_ICDABR15_TINT76                    (0x00001000uL)
+#define INTC_ICDABR15_TINT77                    (0x00002000uL)
+#define INTC_ICDABR15_TINT78                    (0x00004000uL)
+#define INTC_ICDABR15_TINT79                    (0x00008000uL)
+#define INTC_ICDABR15_TINT80                    (0x00010000uL)
+#define INTC_ICDABR15_TINT81                    (0x00020000uL)
+#define INTC_ICDABR15_TINT82                    (0x00040000uL)
+#define INTC_ICDABR15_TINT83                    (0x00080000uL)
+#define INTC_ICDABR15_TINT84                    (0x00100000uL)
+#define INTC_ICDABR15_TINT85                    (0x00200000uL)
+#define INTC_ICDABR15_TINT86                    (0x00400000uL)
+#define INTC_ICDABR15_TINT87                    (0x00800000uL)
+#define INTC_ICDABR15_TINT88                    (0x01000000uL)
+#define INTC_ICDABR15_TINT89                    (0x02000000uL)
+#define INTC_ICDABR15_TINT90                    (0x04000000uL)
+#define INTC_ICDABR15_TINT91                    (0x08000000uL)
+#define INTC_ICDABR15_TINT92                    (0x10000000uL)
+#define INTC_ICDABR15_TINT93                    (0x20000000uL)
+#define INTC_ICDABR15_TINT94                    (0x40000000uL)
+#define INTC_ICDABR15_TINT95                    (0x80000000uL)
+
+#define INTC_ICDABR16_TINT96                    (0x00000001uL)
+#define INTC_ICDABR16_TINT97                    (0x00000002uL)
+#define INTC_ICDABR16_TINT98                    (0x00000004uL)
+#define INTC_ICDABR16_TINT99                    (0x00000008uL)
+#define INTC_ICDABR16_TINT100                   (0x00000010uL)
+#define INTC_ICDABR16_TINT101                   (0x00000020uL)
+#define INTC_ICDABR16_TINT102                   (0x00000040uL)
+#define INTC_ICDABR16_TINT103                   (0x00000080uL)
+#define INTC_ICDABR16_TINT104                   (0x00000100uL)
+#define INTC_ICDABR16_TINT105                   (0x00000200uL)
+#define INTC_ICDABR16_TINT106                   (0x00000400uL)
+#define INTC_ICDABR16_TINT107                   (0x00000800uL)
+#define INTC_ICDABR16_TINT108                   (0x00001000uL)
+#define INTC_ICDABR16_TINT109                   (0x00002000uL)
+#define INTC_ICDABR16_TINT110                   (0x00004000uL)
+#define INTC_ICDABR16_TINT111                   (0x00008000uL)
+#define INTC_ICDABR16_TINT112                   (0x00010000uL)
+#define INTC_ICDABR16_TINT113                   (0x00020000uL)
+#define INTC_ICDABR16_TINT114                   (0x00040000uL)
+#define INTC_ICDABR16_TINT115                   (0x00080000uL)
+#define INTC_ICDABR16_TINT116                   (0x00100000uL)
+#define INTC_ICDABR16_TINT117                   (0x00200000uL)
+#define INTC_ICDABR16_TINT118                   (0x00400000uL)
+#define INTC_ICDABR16_TINT119                   (0x00800000uL)
+#define INTC_ICDABR16_TINT120                   (0x01000000uL)
+#define INTC_ICDABR16_TINT121                   (0x02000000uL)
+#define INTC_ICDABR16_TINT122                   (0x04000000uL)
+#define INTC_ICDABR16_TINT123                   (0x08000000uL)
+#define INTC_ICDABR16_TINT124                   (0x10000000uL)
+#define INTC_ICDABR16_TINT125                   (0x20000000uL)
+#define INTC_ICDABR16_TINT126                   (0x40000000uL)
+#define INTC_ICDABR16_TINT127                   (0x80000000uL)
+
+#define INTC_ICDABR17_TINT128                   (0x00000001uL)
+#define INTC_ICDABR17_TINT129                   (0x00000002uL)
+#define INTC_ICDABR17_TINT130                   (0x00000004uL)
+#define INTC_ICDABR17_TINT131                   (0x00000008uL)
+#define INTC_ICDABR17_TINT132                   (0x00000010uL)
+#define INTC_ICDABR17_TINT133                   (0x00000020uL)
+#define INTC_ICDABR17_TINT134                   (0x00000040uL)
+#define INTC_ICDABR17_TINT135                   (0x00000080uL)
+#define INTC_ICDABR17_TINT136                   (0x00000100uL)
+#define INTC_ICDABR17_TINT137                   (0x00000200uL)
+#define INTC_ICDABR17_TINT138                   (0x00000400uL)
+#define INTC_ICDABR17_TINT139                   (0x00000800uL)
+#define INTC_ICDABR17_TINT140                   (0x00001000uL)
+#define INTC_ICDABR17_TINT141                   (0x00002000uL)
+#define INTC_ICDABR17_TINT142                   (0x00004000uL)
+#define INTC_ICDABR17_TINT143                   (0x00008000uL)
+#define INTC_ICDABR17_TINT144                   (0x00010000uL)
+#define INTC_ICDABR17_TINT145                   (0x00020000uL)
+#define INTC_ICDABR17_TINT146                   (0x00040000uL)
+#define INTC_ICDABR17_TINT147                   (0x00080000uL)
+#define INTC_ICDABR17_TINT148                   (0x00100000uL)
+#define INTC_ICDABR17_TINT149                   (0x00200000uL)
+#define INTC_ICDABR17_TINT150                   (0x00400000uL)
+#define INTC_ICDABR17_TINT151                   (0x00800000uL)
+#define INTC_ICDABR17_TINT152                   (0x01000000uL)
+#define INTC_ICDABR17_TINT153                   (0x02000000uL)
+#define INTC_ICDABR17_TINT154                   (0x04000000uL)
+#define INTC_ICDABR17_TINT155                   (0x08000000uL)
+#define INTC_ICDABR17_TINT156                   (0x10000000uL)
+#define INTC_ICDABR17_TINT157                   (0x20000000uL)
+#define INTC_ICDABR17_TINT158                   (0x40000000uL)
+#define INTC_ICDABR17_TINT159                   (0x80000000uL)
+
+#define INTC_ICDABR18_TINT160                   (0x00000001uL)
+#define INTC_ICDABR18_TINT161                   (0x00000002uL)
+#define INTC_ICDABR18_TINT162                   (0x00000004uL)
+#define INTC_ICDABR18_TINT163                   (0x00000008uL)
+#define INTC_ICDABR18_TINT164                   (0x00000010uL)
+#define INTC_ICDABR18_TINT165                   (0x00000020uL)
+#define INTC_ICDABR18_TINT166                   (0x00000040uL)
+#define INTC_ICDABR18_TINT167                   (0x00000080uL)
+#define INTC_ICDABR18_TINT168                   (0x00000100uL)
+#define INTC_ICDABR18_TINT169                   (0x00000200uL)
+#define INTC_ICDABR18_TINT170                   (0x00000400uL)
+
+#define INTC_ICDIPR0_SW0                        (0x000000FFuL)
+#define INTC_ICDIPR0_SW1                        (0x0000FF00uL)
+#define INTC_ICDIPR0_SW2                        (0x00FF0000uL)
+#define INTC_ICDIPR0_SW3                        (0xFF000000uL)
+
+#define INTC_ICDIPR1_SW4                        (0x000000FFuL)
+#define INTC_ICDIPR1_SW5                        (0x0000FF00uL)
+#define INTC_ICDIPR1_SW6                        (0x00FF0000uL)
+#define INTC_ICDIPR1_SW7                        (0xFF000000uL)
+
+#define INTC_ICDIPR2_SW8                        (0x000000FFuL)
+#define INTC_ICDIPR2_SW9                        (0x0000FF00uL)
+#define INTC_ICDIPR2_SW10                       (0x00FF0000uL)
+#define INTC_ICDIPR2_SW11                       (0xFF000000uL)
+
+#define INTC_ICDIPR3_SW12                       (0x000000FFuL)
+#define INTC_ICDIPR3_SW13                       (0x0000FF00uL)
+#define INTC_ICDIPR3_SW14                       (0x00FF0000uL)
+#define INTC_ICDIPR3_SW15                       (0xFF000000uL)
+
+#define INTC_ICDIPR4_PMUIRQ0                    (0x000000FFuL)
+#define INTC_ICDIPR4_COMMRX0                    (0x0000FF00uL)
+#define INTC_ICDIPR4_COMMTX0                    (0x00FF0000uL)
+#define INTC_ICDIPR4_CTIIRQ0                    (0xFF000000uL)
+
+#define INTC_ICDIPR8_IRQ0                       (0x000000FFuL)
+#define INTC_ICDIPR8_IRQ1                       (0x0000FF00uL)
+#define INTC_ICDIPR8_IRQ2                       (0x00FF0000uL)
+#define INTC_ICDIPR8_IRQ3                       (0xFF000000uL)
+
+#define INTC_ICDIPR9_IRQ4                       (0x000000FFuL)
+#define INTC_ICDIPR9_IRQ5                       (0x0000FF00uL)
+#define INTC_ICDIPR9_IRQ6                       (0x00FF0000uL)
+#define INTC_ICDIPR9_IRQ7                       (0xFF000000uL)
+
+#define INTC_ICDIPR10_PL310ERR                  (0x000000FFuL)
+#define INTC_ICDIPR10_DMAINT0                   (0x0000FF00uL)
+#define INTC_ICDIPR10_DMAINT1                   (0x00FF0000uL)
+#define INTC_ICDIPR10_DMAINT2                   (0xFF000000uL)
+
+#define INTC_ICDIPR11_DMAINT3                   (0x000000FFuL)
+#define INTC_ICDIPR11_DMAINT4                   (0x0000FF00uL)
+#define INTC_ICDIPR11_DMAINT5                   (0x00FF0000uL)
+#define INTC_ICDIPR11_DMAINT6                   (0xFF000000uL)
+
+#define INTC_ICDIPR12_DMAINT7                   (0x000000FFuL)
+#define INTC_ICDIPR12_DMAINT8                   (0x0000FF00uL)
+#define INTC_ICDIPR12_DMAINT9                   (0x00FF0000uL)
+#define INTC_ICDIPR12_DMAINT10                  (0xFF000000uL)
+
+#define INTC_ICDIPR13_DMAINT11                  (0x000000FFuL)
+#define INTC_ICDIPR13_DMAINT12                  (0x0000FF00uL)
+#define INTC_ICDIPR13_DMAINT13                  (0x00FF0000uL)
+#define INTC_ICDIPR13_DMAINT14                  (0xFF000000uL)
+
+#define INTC_ICDIPR14_DMAINT15                  (0x000000FFuL)
+#define INTC_ICDIPR14_DMAERR                    (0x0000FF00uL)
+
+#define INTC_ICDIPR18_USBI0                     (0x0000FF00uL)
+#define INTC_ICDIPR18_USBI1                     (0x00FF0000uL)
+#define INTC_ICDIPR18_S0_VI_VSYNC0              (0xFF000000uL)
+
+#define INTC_ICDIPR19_S0_LO_VSYNC0              (0x000000FFuL)
+#define INTC_ICDIPR19_S0_VSYNCERR0              (0x0000FF00uL)
+#define INTC_ICDIPR19_GR3_VLINE0                (0x00FF0000uL)
+#define INTC_ICDIPR19_S0_VFIELD0                (0xFF000000uL)
+
+#define INTC_ICDIPR20_IV1_VBUFERR0              (0x000000FFuL)
+#define INTC_ICDIPR20_IV3_VBUFERR0              (0x0000FF00uL)
+#define INTC_ICDIPR20_IV5_VBUFERR0              (0x00FF0000uL)
+#define INTC_ICDIPR20_IV6_VBUFERR0              (0xFF000000uL)
+
+#define INTC_ICDIPR21_S0_WLINE0                 (0x000000FFuL)
+#define INTC_ICDIPR21_S1_VI_VSYNC0              (0x0000FF00uL)
+#define INTC_ICDIPR21_S1_LO_VSYNC0              (0x00FF0000uL)
+#define INTC_ICDIPR21_S1_VSYNCERR0              (0xFF000000uL)
+
+#define INTC_ICDIPR22_S1_VFIELD0                (0x000000FFuL)
+#define INTC_ICDIPR22_IV2_VBUFERR0              (0x0000FF00uL)
+#define INTC_ICDIPR22_IV4_VBUFERR0              (0x00FF0000uL)
+#define INTC_ICDIPR22_S1_WLINE0                 (0xFF000000uL)
+
+#define INTC_ICDIPR23_OIR_VI_VSYNC0             (0x000000FFuL)
+#define INTC_ICDIPR23_OIR_LO_VSYNC0             (0x0000FF00uL)
+#define INTC_ICDIPR23_OIR_VSYNCERR0             (0x00FF0000uL)
+#define INTC_ICDIPR23_OIR_VFIELD0               (0xFF000000uL)
+
+#define INTC_ICDIPR24_IV7_VBUFERR0              (0x000000FFuL)
+#define INTC_ICDIPR24_IV8_VBUFERR0              (0x0000FF00uL)
+#define INTC_ICDIPR24_S0_VI_VSYNC1              (0xFF000000uL)
+
+#define INTC_ICDIPR25_S0_LO_VSYNC1              (0x000000FFuL)
+#define INTC_ICDIPR25_S0_VSYNCERR1              (0x0000FF00uL)
+#define INTC_ICDIPR25_GR3_VLINE1                (0x00FF0000uL)
+#define INTC_ICDIPR25_S0_VFIELD1                (0xFF000000uL)
+
+#define INTC_ICDIPR26_IV1_VBUFERR1              (0x000000FFuL)
+#define INTC_ICDIPR26_IV3_VBUFERR1              (0x0000FF00uL)
+#define INTC_ICDIPR26_IV5_VBUFERR1              (0x00FF0000uL)
+#define INTC_ICDIPR26_IV6_VBUFERR1              (0xFF000000uL)
+
+#define INTC_ICDIPR27_S0_WLINE1                 (0x000000FFuL)
+#define INTC_ICDIPR27_S1_VI_VSYNC1              (0x0000FF00uL)
+#define INTC_ICDIPR27_S1_LO_VSYNC1              (0x00FF0000uL)
+#define INTC_ICDIPR27_S1_VSYNCERR1              (0xFF000000uL)
+
+#define INTC_ICDIPR28_S1_VFIELD1                (0x000000FFuL)
+#define INTC_ICDIPR28_IV2_VBUFERR1              (0x0000FF00uL)
+#define INTC_ICDIPR28_IV4_VBUFERR1              (0x00FF0000uL)
+#define INTC_ICDIPR28_S1_WLINE1                 (0xFF000000uL)
+
+#define INTC_ICDIPR29_OIR_VI_VSYNC1             (0x000000FFuL)
+#define INTC_ICDIPR29_OIR_LO_VSYNC1             (0x0000FF00uL)
+#define INTC_ICDIPR29_OIR_VLINE1                (0x00FF0000uL)
+#define INTC_ICDIPR29_OIR_VFIELD1               (0xFF000000uL)
+
+#define INTC_ICDIPR30_IV7_VBUFERR1              (0x000000FFuL)
+#define INTC_ICDIPR30_IV8_VBUFERR1              (0x0000FF00uL)
+#define INTC_ICDIPR30_IMRDI                     (0xFF000000uL)
+
+#define INTC_ICDIPR31_IMR2I0                    (0x000000FFuL)
+#define INTC_ICDIPR31_IMR2I1                    (0x0000FF00uL)
+#define INTC_ICDIPR31_JEDI                      (0x00FF0000uL)
+#define INTC_ICDIPR31_JDTI                      (0xFF000000uL)
+
+#define INTC_ICDIPR32_CMP0                      (0x000000FFuL)
+#define INTC_ICDIPR32_CMP1                      (0x0000FF00uL)
+#define INTC_ICDIPR32_INT0                      (0x00FF0000uL)
+#define INTC_ICDIPR32_INT1                      (0xFF000000uL)
+
+#define INTC_ICDIPR33_INT2                      (0x000000FFuL)
+#define INTC_ICDIPR33_INT3                      (0x0000FF00uL)
+#define INTC_ICDIPR33_OSTM0TINT                 (0x00FF0000uL)
+#define INTC_ICDIPR33_OSTM1TINT                 (0xFF000000uL)
+
+#define INTC_ICDIPR34_CMI                       (0x000000FFuL)
+#define INTC_ICDIPR34_WTOUT                     (0x0000FF00uL)
+#define INTC_ICDIPR34_ITI                       (0x00FF0000uL)
+#define INTC_ICDIPR34_TGI0A                     (0xFF000000uL)
+
+#define INTC_ICDIPR35_TGI0B                     (0x000000FFuL)
+#define INTC_ICDIPR35_TGI0C                     (0x0000FF00uL)
+#define INTC_ICDIPR35_TGI0D                     (0x00FF0000uL)
+#define INTC_ICDIPR35_TGI0V                     (0xFF000000uL)
+
+#define INTC_ICDIPR36_TGI0E                     (0x000000FFuL)
+#define INTC_ICDIPR36_TGI0F                     (0x0000FF00uL)
+#define INTC_ICDIPR36_TGI1A                     (0x00FF0000uL)
+#define INTC_ICDIPR36_TGI1B                     (0xFF000000uL)
+
+#define INTC_ICDIPR37_TGI1V                     (0x000000FFuL)
+#define INTC_ICDIPR37_TGI1U                     (0x0000FF00uL)
+#define INTC_ICDIPR37_TGI2A                     (0x00FF0000uL)
+#define INTC_ICDIPR37_TGI2B                     (0xFF000000uL)
+
+#define INTC_ICDIPR38_TGI2V                     (0x000000FFuL)
+#define INTC_ICDIPR38_TGI2U                     (0x0000FF00uL)
+#define INTC_ICDIPR38_TGI3A                     (0x00FF0000uL)
+#define INTC_ICDIPR38_TGI3B                     (0xFF000000uL)
+
+#define INTC_ICDIPR39_TGI3C                     (0x000000FFuL)
+#define INTC_ICDIPR39_TGI3D                     (0x0000FF00uL)
+#define INTC_ICDIPR39_TGI3V                     (0x00FF0000uL)
+#define INTC_ICDIPR39_TGI4A                     (0xFF000000uL)
+
+#define INTC_ICDIPR40_TGI4B                     (0x000000FFuL)
+#define INTC_ICDIPR40_TGI4C                     (0x0000FF00uL)
+#define INTC_ICDIPR40_TGI4D                     (0x00FF0000uL)
+#define INTC_ICDIPR40_TGI4V                     (0xFF000000uL)
+
+#define INTC_ICDIPR41_CMI1                      (0x000000FFuL)
+#define INTC_ICDIPR41_CMI2                      (0x0000FF00uL)
+#define INTC_ICDIPR41_SGDEI0                    (0x00FF0000uL)
+#define INTC_ICDIPR41_SGDEI1                    (0xFF000000uL)
+
+#define INTC_ICDIPR42_SGDEI2                    (0x000000FFuL)
+#define INTC_ICDIPR42_SGDEI3                    (0x0000FF00uL)
+#define INTC_ICDIPR42_ADI                       (0x00FF0000uL)
+#define INTC_ICDIPR42_LMTI                      (0xFF000000uL)
+
+#define INTC_ICDIPR43_SSII0                     (0x000000FFuL)
+#define INTC_ICDIPR43_SSIRXI0                   (0x0000FF00uL)
+#define INTC_ICDIPR43_SSITXI0                   (0x00FF0000uL)
+#define INTC_ICDIPR43_SSII1                     (0xFF000000uL)
+
+#define INTC_ICDIPR44_SSIRXI1                   (0x000000FFuL)
+#define INTC_ICDIPR44_SSITXI1                   (0x0000FF00uL)
+#define INTC_ICDIPR44_SSII2                     (0x00FF0000uL)
+#define INTC_ICDIPR44_SSIRTI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR45_SSII3                     (0x000000FFuL)
+#define INTC_ICDIPR45_SSIRXI3                   (0x0000FF00uL)
+#define INTC_ICDIPR45_SSITXI3                   (0x00FF0000uL)
+#define INTC_ICDIPR45_SSII4                     (0xFF000000uL)
+
+#define INTC_ICDIPR46_SSIRTI4                   (0x000000FFuL)
+#define INTC_ICDIPR46_SSII5                     (0x0000FF00uL)
+#define INTC_ICDIPR46_SSIRXI5                   (0x00FF0000uL)
+#define INTC_ICDIPR46_SSITXI5                   (0xFF000000uL)
+
+#define INTC_ICDIPR47_SPDIFI                    (0x000000FFuL)
+#define INTC_ICDIPR47_INTIICTEI0                (0x0000FF00uL)
+#define INTC_ICDIPR47_INTIICRI0                 (0x00FF0000uL)
+#define INTC_ICDIPR47_INTIICTI0                 (0xFF000000uL)
+
+#define INTC_ICDIPR48_INTIICSPI0                (0x000000FFuL)
+#define INTC_ICDIPR48_INTIICSTI0                (0x0000FF00uL)
+#define INTC_ICDIPR48_INTIICNAKI0               (0x00FF0000uL)
+#define INTC_ICDIPR48_INTIICALI0                (0xFF000000uL)
+
+#define INTC_ICDIPR49_INTIICTMOI0               (0x000000FFuL)
+#define INTC_ICDIPR49_INTIICTEI1                (0x0000FF00uL)
+#define INTC_ICDIPR49_INTIICRI1                 (0x00FF0000uL)
+#define INTC_ICDIPR49_INTIICTI1                 (0xFF000000uL)
+
+#define INTC_ICDIPR50_INTIICSPI1                (0x000000FFuL)
+#define INTC_ICDIPR50_INTIICSTI1                (0x0000FF00uL)
+#define INTC_ICDIPR50_INTIICNAKI1               (0x00FF0000uL)
+#define INTC_ICDIPR50_INTIICALI1                (0xFF000000uL)
+
+#define INTC_ICDIPR51_INTIICTMOI1               (0x000000FFuL)
+#define INTC_ICDIPR51_INTIICTEI2                (0x0000FF00uL)
+#define INTC_ICDIPR51_INTIICRI2                 (0x00FF0000uL)
+#define INTC_ICDIPR51_INTIICTI2                 (0xFF000000uL)
+
+#define INTC_ICDIPR52_INTIICSPI2                (0x000000FFuL)
+#define INTC_ICDIPR52_INTIICSTI2                (0x0000FF00uL)
+#define INTC_ICDIPR52_INTIICNAKI2               (0x00FF0000uL)
+#define INTC_ICDIPR52_INTIICALI2                (0xFF000000uL)
+
+#define INTC_ICDIPR53_INTIICTMOI2               (0x000000FFuL)
+#define INTC_ICDIPR53_INTIICTEI3                (0x0000FF00uL)
+#define INTC_ICDIPR53_INTIICRI3                 (0x00FF0000uL)
+#define INTC_ICDIPR53_INTIICTI3                 (0xFF000000uL)
+
+#define INTC_ICDIPR54_INTIICSPI3                (0x000000FFuL)
+#define INTC_ICDIPR54_INTIICSTI3                (0x0000FF00uL)
+#define INTC_ICDIPR54_INTIICNAKI3               (0x00FF0000uL)
+#define INTC_ICDIPR54_INTIICALI3                (0xFF000000uL)
+
+#define INTC_ICDIPR55_INTIICTMOI3               (0x000000FFuL)
+#define INTC_ICDIPR55_BRI0                      (0x0000FF00uL)
+#define INTC_ICDIPR55_ERI0                      (0x00FF0000uL)
+#define INTC_ICDIPR55_RXI0                      (0xFF000000uL)
+
+#define INTC_ICDIPR56_TXI0                      (0x000000FFuL)
+#define INTC_ICDIPR56_BRI1                      (0x0000FF00uL)
+#define INTC_ICDIPR56_ERI1                      (0x00FF0000uL)
+#define INTC_ICDIPR56_RXI1                      (0xFF000000uL)
+
+#define INTC_ICDIPR57_TXI1                      (0x000000FFuL)
+#define INTC_ICDIPR57_BRI2                      (0x0000FF00uL)
+#define INTC_ICDIPR57_ERI2                      (0x00FF0000uL)
+#define INTC_ICDIPR57_RXI2                      (0xFF000000uL)
+
+#define INTC_ICDIPR58_TXI2                      (0x000000FFuL)
+#define INTC_ICDIPR58_BRI3                      (0x0000FF00uL)
+#define INTC_ICDIPR58_ERI3                      (0x00FF0000uL)
+#define INTC_ICDIPR58_RXI3                      (0xFF000000uL)
+
+#define INTC_ICDIPR59_TXI3                      (0x000000FFuL)
+#define INTC_ICDIPR59_BRI4                      (0x0000FF00uL)
+#define INTC_ICDIPR59_ERI4                      (0x00FF0000uL)
+#define INTC_ICDIPR59_RXI4                      (0xFF000000uL)
+
+#define INTC_ICDIPR60_TXI4                      (0x000000FFuL)
+#define INTC_ICDIPR60_BRI5                      (0x0000FF00uL)
+#define INTC_ICDIPR60_ERI5                      (0x00FF0000uL)
+#define INTC_ICDIPR60_RXI5                      (0xFF000000uL)
+
+#define INTC_ICDIPR61_TXI5                      (0x000000FFuL)
+#define INTC_ICDIPR61_BRI6                      (0x0000FF00uL)
+#define INTC_ICDIPR61_ERI6                      (0x00FF0000uL)
+#define INTC_ICDIPR61_RXI6                      (0xFF000000uL)
+
+#define INTC_ICDIPR62_TXI6                      (0x000000FFuL)
+#define INTC_ICDIPR62_BRI7                      (0x0000FF00uL)
+#define INTC_ICDIPR62_ERI7                      (0x00FF0000uL)
+#define INTC_ICDIPR62_RXI7                      (0xFF000000uL)
+
+#define INTC_ICDIPR63_TXI7                      (0x000000FFuL)
+#define INTC_ICDIPR63_INTRCANGERR               (0x0000FF00uL)
+#define INTC_ICDIPR63_INTRCANGRECC              (0x00FF0000uL)
+#define INTC_ICDIPR63_INTRCAN0REC               (0xFF000000uL)
+
+#define INTC_ICDIPR64_INTRCAN0ERR               (0x000000FFuL)
+#define INTC_ICDIPR64_INTRCAN0TRX               (0x0000FF00uL)
+#define INTC_ICDIPR64_INTRCAN1REC               (0x00FF0000uL)
+#define INTC_ICDIPR64_INTRCAN1ERR               (0xFF000000uL)
+
+#define INTC_ICDIPR65_INTRCAN1TRX               (0x000000FFuL)
+#define INTC_ICDIPR65_INTRCAN2REC               (0x0000FF00uL)
+#define INTC_ICDIPR65_INTRCAN2ERR               (0x00FF0000uL)
+#define INTC_ICDIPR65_INTRCAN2TRX               (0xFF000000uL)
+
+#define INTC_ICDIPR66_INTRCAN3REC               (0x000000FFuL)
+#define INTC_ICDIPR66_INTRCAN3ERR               (0x0000FF00uL)
+#define INTC_ICDIPR66_INTRCAN3TRX               (0x00FF0000uL)
+#define INTC_ICDIPR66_INTRCAN4REC               (0xFF000000uL)
+
+#define INTC_ICDIPR67_INTRCAN4ERR               (0x000000FFuL)
+#define INTC_ICDIPR67_INTRCAN4TRX               (0x0000FF00uL)
+#define INTC_ICDIPR67_SPEI0                     (0x00FF0000uL)
+#define INTC_ICDIPR67_SPRI0                     (0xFF000000uL)
+
+#define INTC_ICDIPR68_SPTI0                     (0x000000FFuL)
+#define INTC_ICDIPR68_SPEI1                     (0x0000FF00uL)
+#define INTC_ICDIPR68_SPRI1                     (0x00FF0000uL)
+#define INTC_ICDIPR68_SPTI1                     (0xFF000000uL)
+
+#define INTC_ICDIPR69_SPEI2                     (0x000000FFuL)
+#define INTC_ICDIPR69_SPRI2                     (0x0000FF00uL)
+#define INTC_ICDIPR69_SPTI2                     (0x00FF0000uL)
+#define INTC_ICDIPR69_SPEI3                     (0xFF000000uL)
+
+#define INTC_ICDIPR70_SPRI3                     (0x000000FFuL)
+#define INTC_ICDIPR70_SPTI3                     (0x0000FF00uL)
+#define INTC_ICDIPR70_SPEI4                     (0x00FF0000uL)
+#define INTC_ICDIPR70_SPRI4                     (0xFF000000uL)
+
+#define INTC_ICDIPR71_SPTI4                     (0x000000FFuL)
+#define INTC_ICDIPR71_IEBBTD                    (0x0000FF00uL)
+#define INTC_ICDIPR71_IEBBTERR                  (0x00FF0000uL)
+#define INTC_ICDIPR71_IEBBTSTA                  (0xFF000000uL)
+
+#define INTC_ICDIPR72_IEBBTV                    (0x000000FFuL)
+#define INTC_ICDIPR72_ISY                       (0x0000FF00uL)
+#define INTC_ICDIPR72_IERR                      (0x00FF0000uL)
+#define INTC_ICDIPR72_ITARG                     (0xFF000000uL)
+
+#define INTC_ICDIPR73_ISEC                      (0x000000FFuL)
+#define INTC_ICDIPR73_IBUF                      (0x0000FF00uL)
+#define INTC_ICDIPR73_IREADY                    (0x00FF0000uL)
+#define INTC_ICDIPR73_FLSTE                     (0xFF000000uL)
+
+#define INTC_ICDIPR74_FLTENDI                   (0x000000FFuL)
+#define INTC_ICDIPR74_FLTREQ0I                  (0x0000FF00uL)
+#define INTC_ICDIPR74_FLTREQ1I                  (0x00FF0000uL)
+#define INTC_ICDIPR74_MMC0                      (0xFF000000uL)
+
+#define INTC_ICDIPR75_MMC1                      (0x000000FFuL)
+#define INTC_ICDIPR75_MMC2                      (0x0000FF00uL)
+#define INTC_ICDIPR75_SDHI0_3                   (0x00FF0000uL)
+#define INTC_ICDIPR75_SDHI0_0                   (0xFF000000uL)
+
+#define INTC_ICDIPR76_SDHI0_1                   (0x000000FFuL)
+#define INTC_ICDIPR76_SDHI1_3                   (0x0000FF00uL)
+#define INTC_ICDIPR76_SDHI1_0                   (0x00FF0000uL)
+#define INTC_ICDIPR76_SDHI1_1                   (0xFF000000uL)
+
+#define INTC_ICDIPR77_ARM                       (0x000000FFuL)
+#define INTC_ICDIPR77_PRD                       (0x0000FF00uL)
+#define INTC_ICDIPR77_CUP                       (0x00FF0000uL)
+#define INTC_ICDIPR77_SCUAI0                    (0xFF000000uL)
+
+#define INTC_ICDIPR78_SCUAI1                    (0x000000FFuL)
+#define INTC_ICDIPR78_SCUFDI0                   (0x0000FF00uL)
+#define INTC_ICDIPR78_SCUFDI1                   (0x00FF0000uL)
+#define INTC_ICDIPR78_SCUFDI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR79_SCUFDI3                   (0x000000FFuL)
+#define INTC_ICDIPR79_SCUFUI0                   (0x0000FF00uL)
+#define INTC_ICDIPR79_SCUFUI1                   (0x00FF0000uL)
+#define INTC_ICDIPR79_SCUFUI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR80_SCUFUI3                   (0x000000FFuL)
+#define INTC_ICDIPR80_SCUDVI0                   (0x0000FF00uL)
+#define INTC_ICDIPR80_SCUDVI1                   (0x00FF0000uL)
+#define INTC_ICDIPR80_SCUDVI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR81_SCUDVI3                   (0x000000FFuL)
+#define INTC_ICDIPR81_MLB_CINT                  (0x0000FF00uL)
+#define INTC_ICDIPR81_MLB_SINT                  (0x00FF0000uL)
+#define INTC_ICDIPR81_DRC0                      (0xFF000000uL)
+
+#define INTC_ICDIPR82_DRC1                      (0x000000FFuL)
+#define INTC_ICDIPR82_LINI0_INT_T               (0xFF000000uL)
+
+#define INTC_ICDIPR83_LINI0_INT_R               (0x000000FFuL)
+#define INTC_ICDIPR83_LINI0_INT_S               (0x0000FF00uL)
+#define INTC_ICDIPR83_LINI0_INT_M               (0x00FF0000uL)
+#define INTC_ICDIPR83_LINI1_INT_T               (0xFF000000uL)
+
+#define INTC_ICDIPR84_LINI1_INT_R               (0x000000FFuL)
+#define INTC_ICDIPR84_LINI1_INT_S               (0x0000FF00uL)
+#define INTC_ICDIPR84_LINI1_INT_M               (0x00FF0000uL)
+
+#define INTC_ICDIPR86_ERI0                      (0xFF000000uL)
+
+#define INTC_ICDIPR87_RXI0                      (0x000000FFuL)
+#define INTC_ICDIPR87_TXI0                      (0x0000FF00uL)
+#define INTC_ICDIPR87_TEI0                      (0x00FF0000uL)
+#define INTC_ICDIPR87_ERI1                      (0xFF000000uL)
+
+#define INTC_ICDIPR88_RXI1                      (0x000000FFuL)
+#define INTC_ICDIPR88_TXI1                      (0x0000FF00uL)
+#define INTC_ICDIPR88_TEI1                      (0x00FF0000uL)
+#define INTC_ICDIPR88_AVBI_DATA                 (0xFF000000uL)
+
+#define INTC_ICDIPR89_AVBI_ERROR                (0x000000FFuL)
+#define INTC_ICDIPR89_AVBI_MANAGE               (0x0000FF00uL)
+#define INTC_ICDIPR89_AVBI_MAC                  (0x00FF0000uL)
+#define INTC_ICDIPR89_ETHERI                    (0xFF000000uL)
+
+#define INTC_ICDIPR91_CEUI                      (0x000000FFuL)
+
+#define INTC_ICDIPR95_H2XMLB_ERRINT             (0x0000FF00uL)
+#define INTC_ICDIPR95_H2XIC1_ERRINT             (0x00FF0000uL)
+#define INTC_ICDIPR95_X2HPERI1_ERRINT           (0xFF000000uL)
+
+#define INTC_ICDIPR96_X2HPERI2_ERRINT           (0x000000FFuL)
+#define INTC_ICDIPR96_X2HPERI34_ERRINT          (0x0000FF00uL)
+#define INTC_ICDIPR96_X2HPERI5_ERRINT           (0x00FF0000uL)
+#define INTC_ICDIPR96_X2HPERI67_ERRINT          (0xFF000000uL)
+
+#define INTC_ICDIPR97_X2HDBGR_ERRINT            (0x000000FFuL)
+#define INTC_ICDIPR97_X2HBSC_ERRINT             (0x0000FF00uL)
+#define INTC_ICDIPR97_X2HSPI1_ERRINT            (0x00FF0000uL)
+#define INTC_ICDIPR97_X2HSPI2_ERRINT            (0xFF000000uL)
+
+#define INTC_ICDIPR98_PRRI                      (0x000000FFuL)
+#define INTC_ICDIPR98_IFEI0                     (0x0000FF00uL)
+#define INTC_ICDIPR98_OFFI0                     (0x00FF0000uL)
+#define INTC_ICDIPR98_PFVEI0                    (0xFF000000uL)
+
+#define INTC_ICDIPR99_IFEI1                     (0x000000FFuL)
+#define INTC_ICDIPR99_OFFI1                     (0x0000FF00uL)
+#define INTC_ICDIPR99_PFVEI1                    (0x00FF0000uL)
+
+#define INTC_ICDIPR104_TINT0                    (0x000000FFuL)
+#define INTC_ICDIPR104_TINT1                    (0x0000FF00uL)
+#define INTC_ICDIPR104_TINT2                    (0x00FF0000uL)
+#define INTC_ICDIPR104_TINT3                    (0xFF000000uL)
+
+#define INTC_ICDIPR105_TINT4                    (0x000000FFuL)
+#define INTC_ICDIPR105_TINT5                    (0x0000FF00uL)
+#define INTC_ICDIPR105_TINT6                    (0x00FF0000uL)
+#define INTC_ICDIPR105_TINT7                    (0xFF000000uL)
+
+#define INTC_ICDIPR106_TINT8                    (0x000000FFuL)
+#define INTC_ICDIPR106_TINT9                    (0x0000FF00uL)
+#define INTC_ICDIPR106_TINT10                   (0x00FF0000uL)
+#define INTC_ICDIPR106_TINT11                   (0xFF000000uL)
+
+#define INTC_ICDIPR107_TINT12                   (0x000000FFuL)
+#define INTC_ICDIPR107_TINT13                   (0x0000FF00uL)
+#define INTC_ICDIPR107_TINT14                   (0x00FF0000uL)
+#define INTC_ICDIPR107_TINT15                   (0xFF000000uL)
+
+#define INTC_ICDIPR108_TINT16                   (0x000000FFuL)
+#define INTC_ICDIPR108_TINT17                   (0x0000FF00uL)
+#define INTC_ICDIPR108_TINT18                   (0x00FF0000uL)
+#define INTC_ICDIPR108_TINT19                   (0xFF000000uL)
+
+#define INTC_ICDIPR109_TINT20                   (0x000000FFuL)
+#define INTC_ICDIPR109_TINT21                   (0x0000FF00uL)
+#define INTC_ICDIPR109_TINT22                   (0x00FF0000uL)
+#define INTC_ICDIPR109_TINT23                   (0xFF000000uL)
+
+#define INTC_ICDIPR110_TINT24                   (0x000000FFuL)
+#define INTC_ICDIPR110_TINT25                   (0x0000FF00uL)
+#define INTC_ICDIPR110_TINT26                   (0x00FF0000uL)
+#define INTC_ICDIPR110_TINT27                   (0xFF000000uL)
+
+#define INTC_ICDIPR111_TINT28                   (0x000000FFuL)
+#define INTC_ICDIPR111_TINT29                   (0x0000FF00uL)
+#define INTC_ICDIPR111_TINT30                   (0x00FF0000uL)
+#define INTC_ICDIPR111_TINT31                   (0xFF000000uL)
+
+#define INTC_ICDIPR112_TINT32                   (0x000000FFuL)
+#define INTC_ICDIPR112_TINT33                   (0x0000FF00uL)
+#define INTC_ICDIPR112_TINT34                   (0x00FF0000uL)
+#define INTC_ICDIPR112_TINT35                   (0xFF000000uL)
+
+#define INTC_ICDIPR113_TINT36                   (0x000000FFuL)
+#define INTC_ICDIPR113_TINT37                   (0x0000FF00uL)
+#define INTC_ICDIPR113_TINT38                   (0x00FF0000uL)
+#define INTC_ICDIPR113_TINT39                   (0xFF000000uL)
+
+#define INTC_ICDIPR114_TINT40                   (0x000000FFuL)
+#define INTC_ICDIPR114_TINT41                   (0x0000FF00uL)
+#define INTC_ICDIPR114_TINT42                   (0x00FF0000uL)
+#define INTC_ICDIPR114_TINT43                   (0xFF000000uL)
+
+#define INTC_ICDIPR115_TINT44                   (0x000000FFuL)
+#define INTC_ICDIPR115_TINT45                   (0x0000FF00uL)
+#define INTC_ICDIPR115_TINT46                   (0x00FF0000uL)
+#define INTC_ICDIPR115_TINT47                   (0xFF000000uL)
+
+#define INTC_ICDIPR116_TINT48                   (0x000000FFuL)
+#define INTC_ICDIPR116_TINT49                   (0x0000FF00uL)
+#define INTC_ICDIPR116_TINT50                   (0x00FF0000uL)
+#define INTC_ICDIPR116_TINT51                   (0xFF000000uL)
+
+#define INTC_ICDIPR117_TINT52                   (0x000000FFuL)
+#define INTC_ICDIPR117_TINT53                   (0x0000FF00uL)
+#define INTC_ICDIPR117_TINT54                   (0x00FF0000uL)
+#define INTC_ICDIPR117_TINT55                   (0xFF000000uL)
+
+#define INTC_ICDIPR118_TINT56                   (0x000000FFuL)
+#define INTC_ICDIPR118_TINT57                   (0x0000FF00uL)
+#define INTC_ICDIPR118_TINT58                   (0x00FF0000uL)
+#define INTC_ICDIPR118_TINT59                   (0xFF000000uL)
+
+#define INTC_ICDIPR119_TINT60                   (0x000000FFuL)
+#define INTC_ICDIPR119_TINT61                   (0x0000FF00uL)
+#define INTC_ICDIPR119_TINT62                   (0x00FF0000uL)
+#define INTC_ICDIPR119_TINT63                   (0xFF000000uL)
+
+#define INTC_ICDIPR120_TINT64                   (0x000000FFuL)
+#define INTC_ICDIPR120_TINT65                   (0x0000FF00uL)
+#define INTC_ICDIPR120_TINT66                   (0x00FF0000uL)
+#define INTC_ICDIPR120_TINT67                   (0xFF000000uL)
+
+#define INTC_ICDIPR121_TINT68                   (0x000000FFuL)
+#define INTC_ICDIPR121_TINT69                   (0x0000FF00uL)
+#define INTC_ICDIPR121_TINT70                   (0x00FF0000uL)
+#define INTC_ICDIPR121_TINT71                   (0xFF000000uL)
+
+#define INTC_ICDIPR122_TINT72                   (0x000000FFuL)
+#define INTC_ICDIPR122_TINT73                   (0x0000FF00uL)
+#define INTC_ICDIPR122_TINT74                   (0x00FF0000uL)
+#define INTC_ICDIPR122_TINT75                   (0xFF000000uL)
+
+#define INTC_ICDIPR123_TINT76                   (0x000000FFuL)
+#define INTC_ICDIPR123_TINT77                   (0x0000FF00uL)
+#define INTC_ICDIPR123_TINT78                   (0x00FF0000uL)
+#define INTC_ICDIPR123_TINT79                   (0xFF000000uL)
+
+#define INTC_ICDIPR124_TINT80                   (0x000000FFuL)
+#define INTC_ICDIPR124_TINT81                   (0x0000FF00uL)
+#define INTC_ICDIPR124_TINT82                   (0x00FF0000uL)
+#define INTC_ICDIPR124_TINT83                   (0xFF000000uL)
+
+#define INTC_ICDIPR125_TINT84                   (0x000000FFuL)
+#define INTC_ICDIPR125_TINT85                   (0x0000FF00uL)
+#define INTC_ICDIPR125_TINT86                   (0x00FF0000uL)
+#define INTC_ICDIPR125_TINT87                   (0xFF000000uL)
+
+#define INTC_ICDIPR126_TINT88                   (0x000000FFuL)
+#define INTC_ICDIPR126_TINT89                   (0x0000FF00uL)
+#define INTC_ICDIPR126_TINT90                   (0x00FF0000uL)
+#define INTC_ICDIPR126_TINT91                   (0xFF000000uL)
+
+#define INTC_ICDIPR127_TINT92                   (0x000000FFuL)
+#define INTC_ICDIPR127_TINT93                   (0x0000FF00uL)
+#define INTC_ICDIPR127_TINT94                   (0x00FF0000uL)
+#define INTC_ICDIPR127_TINT95                   (0xFF000000uL)
+
+#define INTC_ICDIPR128_TINT96                   (0x000000FFuL)
+#define INTC_ICDIPR128_TINT97                   (0x0000FF00uL)
+#define INTC_ICDIPR128_TINT98                   (0x00FF0000uL)
+#define INTC_ICDIPR128_TINT99                   (0xFF000000uL)
+
+#define INTC_ICDIPR129_TINT100                  (0x000000FFuL)
+#define INTC_ICDIPR129_TINT101                  (0x0000FF00uL)
+#define INTC_ICDIPR129_TINT102                  (0x00FF0000uL)
+#define INTC_ICDIPR129_TINT103                  (0xFF000000uL)
+
+#define INTC_ICDIPR130_TINT104                  (0x000000FFuL)
+#define INTC_ICDIPR130_TINT105                  (0x0000FF00uL)
+#define INTC_ICDIPR130_TINT106                  (0x00FF0000uL)
+#define INTC_ICDIPR130_TINT107                  (0xFF000000uL)
+
+#define INTC_ICDIPR131_TINT108                  (0x000000FFuL)
+#define INTC_ICDIPR131_TINT109                  (0x0000FF00uL)
+#define INTC_ICDIPR131_TINT110                  (0x00FF0000uL)
+#define INTC_ICDIPR131_TINT111                  (0xFF000000uL)
+
+#define INTC_ICDIPR132_TINT112                  (0x000000FFuL)
+#define INTC_ICDIPR132_TINT113                  (0x0000FF00uL)
+#define INTC_ICDIPR132_TINT114                  (0x00FF0000uL)
+#define INTC_ICDIPR132_TINT115                  (0xFF000000uL)
+
+#define INTC_ICDIPR133_TINT116                  (0x000000FFuL)
+#define INTC_ICDIPR133_TINT117                  (0x0000FF00uL)
+#define INTC_ICDIPR133_TINT118                  (0x00FF0000uL)
+#define INTC_ICDIPR133_TINT119                  (0xFF000000uL)
+
+#define INTC_ICDIPR134_TINT120                  (0x000000FFuL)
+#define INTC_ICDIPR134_TINT121                  (0x0000FF00uL)
+#define INTC_ICDIPR134_TINT122                  (0x00FF0000uL)
+#define INTC_ICDIPR134_TINT123                  (0xFF000000uL)
+
+#define INTC_ICDIPR135_TINT124                  (0x000000FFuL)
+#define INTC_ICDIPR135_TINT125                  (0x0000FF00uL)
+#define INTC_ICDIPR135_TINT126                  (0x00FF0000uL)
+#define INTC_ICDIPR135_TINT127                  (0xFF000000uL)
+
+#define INTC_ICDIPR136_TINT128                  (0x000000FFuL)
+#define INTC_ICDIPR136_TINT129                  (0x0000FF00uL)
+#define INTC_ICDIPR136_TINT130                  (0x00FF0000uL)
+#define INTC_ICDIPR136_TINT131                  (0xFF000000uL)
+
+#define INTC_ICDIPR137_TINT132                  (0x000000FFuL)
+#define INTC_ICDIPR137_TINT133                  (0x0000FF00uL)
+#define INTC_ICDIPR137_TINT134                  (0x00FF0000uL)
+#define INTC_ICDIPR137_TINT135                  (0xFF000000uL)
+
+#define INTC_ICDIPR138_TINT136                  (0x000000FFuL)
+#define INTC_ICDIPR138_TINT137                  (0x0000FF00uL)
+#define INTC_ICDIPR138_TINT138                  (0x00FF0000uL)
+#define INTC_ICDIPR138_TINT139                  (0xFF000000uL)
+
+#define INTC_ICDIPR139_TINT140                  (0x000000FFuL)
+#define INTC_ICDIPR139_TINT141                  (0x0000FF00uL)
+#define INTC_ICDIPR139_TINT142                  (0x00FF0000uL)
+#define INTC_ICDIPR139_TINT143                  (0xFF000000uL)
+
+#define INTC_ICDIPR140_TINT144                  (0x000000FFuL)
+#define INTC_ICDIPR140_TINT145                  (0x0000FF00uL)
+#define INTC_ICDIPR140_TINT146                  (0x00FF0000uL)
+#define INTC_ICDIPR140_TINT147                  (0xFF000000uL)
+
+#define INTC_ICDIPR141_TINT148                  (0x000000FFuL)
+#define INTC_ICDIPR141_TINT149                  (0x0000FF00uL)
+#define INTC_ICDIPR141_TINT150                  (0x00FF0000uL)
+#define INTC_ICDIPR141_TINT151                  (0xFF000000uL)
+
+#define INTC_ICDIPR142_TINT152                  (0x000000FFuL)
+#define INTC_ICDIPR142_TINT153                  (0x0000FF00uL)
+#define INTC_ICDIPR142_TINT154                  (0x00FF0000uL)
+#define INTC_ICDIPR142_TINT155                  (0xFF000000uL)
+
+#define INTC_ICDIPR143_TINT156                  (0x000000FFuL)
+#define INTC_ICDIPR143_TINT157                  (0x0000FF00uL)
+#define INTC_ICDIPR143_TINT158                  (0x00FF0000uL)
+#define INTC_ICDIPR143_TINT159                  (0xFF000000uL)
+
+#define INTC_ICDIPR144_TINT160                  (0x000000FFuL)
+#define INTC_ICDIPR144_TINT161                  (0x0000FF00uL)
+#define INTC_ICDIPR144_TINT162                  (0x00FF0000uL)
+#define INTC_ICDIPR144_TINT163                  (0xFF000000uL)
+
+#define INTC_ICDIPR145_TINT164                  (0x000000FFuL)
+#define INTC_ICDIPR145_TINT165                  (0x0000FF00uL)
+#define INTC_ICDIPR145_TINT166                  (0x00FF0000uL)
+#define INTC_ICDIPR145_TINT167                  (0xFF000000uL)
+
+#define INTC_ICDIPR146_TINT168                  (0x000000FFuL)
+#define INTC_ICDIPR146_TINT169                  (0x0000FF00uL)
+#define INTC_ICDIPR146_TINT170                  (0x00FF0000uL)
+
+#define INTC_ICDIPTR0_SW0                       (0x000000FFuL)
+#define INTC_ICDIPTR0_SW1                       (0x0000FF00uL)
+#define INTC_ICDIPTR0_SW2                       (0x00FF0000uL)
+#define INTC_ICDIPTR0_SW3                       (0xFF000000uL)
+
+#define INTC_ICDIPTR1_SW4                       (0x000000FFuL)
+#define INTC_ICDIPTR1_SW5                       (0x0000FF00uL)
+#define INTC_ICDIPTR1_SW6                       (0x00FF0000uL)
+#define INTC_ICDIPTR1_SW7                       (0xFF000000uL)
+
+#define INTC_ICDIPTR2_SW8                       (0x000000FFuL)
+#define INTC_ICDIPTR2_SW9                       (0x0000FF00uL)
+#define INTC_ICDIPTR2_SW10                      (0x00FF0000uL)
+#define INTC_ICDIPTR2_SW11                      (0xFF000000uL)
+
+#define INTC_ICDIPTR3_SW12                      (0x000000FFuL)
+#define INTC_ICDIPTR3_SW13                      (0x0000FF00uL)
+#define INTC_ICDIPTR3_SW14                      (0x00FF0000uL)
+#define INTC_ICDIPTR3_SW15                      (0xFF000000uL)
+
+#define INTC_ICDIPTR4_PMUIRQ0                   (0x000000FFuL)
+#define INTC_ICDIPTR4_COMMRX0                   (0x0000FF00uL)
+#define INTC_ICDIPTR4_COMMTX0                   (0x00FF0000uL)
+#define INTC_ICDIPTR4_CTIIRQ0                   (0xFF000000uL)
+
+#define INTC_ICDIPTR8_IRQ0                      (0x000000FFuL)
+#define INTC_ICDIPTR8_IRQ1                      (0x0000FF00uL)
+#define INTC_ICDIPTR8_IRQ2                      (0x00FF0000uL)
+#define INTC_ICDIPTR8_IRQ3                      (0xFF000000uL)
+
+#define INTC_ICDIPTR9_IRQ4                      (0x000000FFuL)
+#define INTC_ICDIPTR9_IRQ5                      (0x0000FF00uL)
+#define INTC_ICDIPTR9_IRQ6                      (0x00FF0000uL)
+#define INTC_ICDIPTR9_IRQ7                      (0xFF000000uL)
+
+#define INTC_ICDIPTR10_PL310ERR                 (0x000000FFuL)
+#define INTC_ICDIPTR10_DMAINT0                  (0x0000FF00uL)
+#define INTC_ICDIPTR10_DMAINT1                  (0x00FF0000uL)
+#define INTC_ICDIPTR10_DMAINT2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR11_DMAINT3                  (0x000000FFuL)
+#define INTC_ICDIPTR11_DMAINT4                  (0x0000FF00uL)
+#define INTC_ICDIPTR11_DMAINT5                  (0x00FF0000uL)
+#define INTC_ICDIPTR11_DMAINT6                  (0xFF000000uL)
+
+#define INTC_ICDIPTR12_DMAINT7                  (0x000000FFuL)
+#define INTC_ICDIPTR12_DMAINT8                  (0x0000FF00uL)
+#define INTC_ICDIPTR12_DMAINT9                  (0x00FF0000uL)
+#define INTC_ICDIPTR12_DMAINT10                 (0xFF000000uL)
+
+#define INTC_ICDIPTR13_DMAINT11                 (0x000000FFuL)
+#define INTC_ICDIPTR13_DMAINT12                 (0x0000FF00uL)
+#define INTC_ICDIPTR13_DMAINT13                 (0x00FF0000uL)
+#define INTC_ICDIPTR13_DMAINT14                 (0xFF000000uL)
+
+#define INTC_ICDIPTR14_DMAINT15                 (0x000000FFuL)
+#define INTC_ICDIPTR14_DMAERR                   (0x0000FF00uL)
+
+#define INTC_ICDIPTR18_USBI0                    (0x0000FF00uL)
+#define INTC_ICDIPTR18_USBI1                    (0x00FF0000uL)
+#define INTC_ICDIPTR18_S0_VI_VSYNC0             (0xFF000000uL)
+
+#define INTC_ICDIPTR19_S0_LO_VSYNC0             (0x000000FFuL)
+#define INTC_ICDIPTR19_S0_VSYNCERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR19_GR3_VLINE0               (0x00FF0000uL)
+#define INTC_ICDIPTR19_S0_VFIELD0               (0xFF000000uL)
+
+#define INTC_ICDIPTR20_IV1_VBUFERR0             (0x000000FFuL)
+#define INTC_ICDIPTR20_IV3_VBUFERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR20_IV5_VBUFERR0             (0x00FF0000uL)
+#define INTC_ICDIPTR20_IV6_VBUFERR0             (0xFF000000uL)
+
+#define INTC_ICDIPTR21_S0_WLINE0                (0x000000FFuL)
+#define INTC_ICDIPTR21_S1_VI_VSYNC0             (0x0000FF00uL)
+#define INTC_ICDIPTR21_S1_LO_VSYNC0             (0x00FF0000uL)
+#define INTC_ICDIPTR21_S1_VSYNCERR0             (0xFF000000uL)
+
+#define INTC_ICDIPTR22_S1_VFIELD0               (0x000000FFuL)
+#define INTC_ICDIPTR22_IV2_VBUFERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR22_IV4_VBUFERR0             (0x00FF0000uL)
+#define INTC_ICDIPTR22_S1_WLINE0                (0xFF000000uL)
+
+#define INTC_ICDIPTR23_OIR_VI_VSYNC0            (0x000000FFuL)
+#define INTC_ICDIPTR23_OIR_LO_VSYNC0            (0x0000FF00uL)
+#define INTC_ICDIPTR23_OIR_VSYNCERR0            (0x00FF0000uL)
+#define INTC_ICDIPTR23_OIR_VFIELD0              (0xFF000000uL)
+
+#define INTC_ICDIPTR24_IV7_VBUFERR0             (0x000000FFuL)
+#define INTC_ICDIPTR24_IV8_VBUFERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR24_S0_VI_VSYNC1             (0xFF000000uL)
+
+#define INTC_ICDIPTR25_S0_LO_VSYNC1             (0x000000FFuL)
+#define INTC_ICDIPTR25_S0_VSYNCERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR25_GR3_VLINE1               (0x00FF0000uL)
+#define INTC_ICDIPTR25_S0_VFIELD1               (0xFF000000uL)
+
+#define INTC_ICDIPTR26_IV1_VBUFERR1             (0x000000FFuL)
+#define INTC_ICDIPTR26_IV3_VBUFERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR26_IV5_VBUFERR1             (0x00FF0000uL)
+#define INTC_ICDIPTR26_IV6_VBUFERR1             (0xFF000000uL)
+
+#define INTC_ICDIPTR27_S0_WLINE1                (0x000000FFuL)
+#define INTC_ICDIPTR27_S1_VI_VSYNC1             (0x0000FF00uL)
+#define INTC_ICDIPTR27_S1_LO_VSYNC1             (0x00FF0000uL)
+#define INTC_ICDIPTR27_S1_VSYNCERR1             (0xFF000000uL)
+
+#define INTC_ICDIPTR28_S1_VFIELD1               (0x000000FFuL)
+#define INTC_ICDIPTR28_IV2_VBUFERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR28_IV4_VBUFERR1             (0x00FF0000uL)
+#define INTC_ICDIPTR28_S1_WLINE1                (0xFF000000uL)
+
+#define INTC_ICDIPTR29_OIR_VI_VSYNC1            (0x000000FFuL)
+#define INTC_ICDIPTR29_OIR_LO_VSYNC1            (0x0000FF00uL)
+#define INTC_ICDIPTR29_OIR_VLINE1               (0x00FF0000uL)
+#define INTC_ICDIPTR29_OIR_VFIELD1              (0xFF000000uL)
+
+#define INTC_ICDIPTR30_IV7_VBUFERR1             (0x000000FFuL)
+#define INTC_ICDIPTR30_IV8_VBUFERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR30_IMRDI                    (0xFF000000uL)
+
+#define INTC_ICDIPTR31_IMR2I0                   (0x000000FFuL)
+#define INTC_ICDIPTR31_IMR2I1                   (0x0000FF00uL)
+#define INTC_ICDIPTR31_JEDI                     (0x00FF0000uL)
+#define INTC_ICDIPTR31_JDTI                     (0xFF000000uL)
+
+#define INTC_ICDIPTR32_CMP0                     (0x000000FFuL)
+#define INTC_ICDIPTR32_CMP1                     (0x0000FF00uL)
+#define INTC_ICDIPTR32_INT0                     (0x00FF0000uL)
+#define INTC_ICDIPTR32_INT1                     (0xFF000000uL)
+
+#define INTC_ICDIPTR33_INT2                     (0x000000FFuL)
+#define INTC_ICDIPTR33_INT3                     (0x0000FF00uL)
+#define INTC_ICDIPTR33_OSTM0TINT                (0x00FF0000uL)
+#define INTC_ICDIPTR33_OSTM1TINT                (0xFF000000uL)
+
+#define INTC_ICDIPTR34_CMI                      (0x000000FFuL)
+#define INTC_ICDIPTR34_WTOUT                    (0x0000FF00uL)
+#define INTC_ICDIPTR34_ITI                      (0x00FF0000uL)
+#define INTC_ICDIPTR34_TGI0A                    (0xFF000000uL)
+
+#define INTC_ICDIPTR35_TGI0B                    (0x000000FFuL)
+#define INTC_ICDIPTR35_TGI0C                    (0x0000FF00uL)
+#define INTC_ICDIPTR35_TGI0D                    (0x00FF0000uL)
+#define INTC_ICDIPTR35_TGI0V                    (0xFF000000uL)
+
+#define INTC_ICDIPTR36_TGI0E                    (0x000000FFuL)
+#define INTC_ICDIPTR36_TGI0F                    (0x0000FF00uL)
+#define INTC_ICDIPTR36_TGI1A                    (0x00FF0000uL)
+#define INTC_ICDIPTR36_TGI1B                    (0xFF000000uL)
+
+#define INTC_ICDIPTR37_TGI1V                    (0x000000FFuL)
+#define INTC_ICDIPTR37_TGI1U                    (0x0000FF00uL)
+#define INTC_ICDIPTR37_TGI2A                    (0x00FF0000uL)
+#define INTC_ICDIPTR37_TGI2B                    (0xFF000000uL)
+
+#define INTC_ICDIPTR38_TGI2V                    (0x000000FFuL)
+#define INTC_ICDIPTR38_TGI2U                    (0x0000FF00uL)
+#define INTC_ICDIPTR38_TGI3A                    (0x00FF0000uL)
+#define INTC_ICDIPTR38_TGI3B                    (0xFF000000uL)
+
+#define INTC_ICDIPTR39_TGI3C                    (0x000000FFuL)
+#define INTC_ICDIPTR39_TGI3D                    (0x0000FF00uL)
+#define INTC_ICDIPTR39_TGI3V                    (0x00FF0000uL)
+#define INTC_ICDIPTR39_TGI4A                    (0xFF000000uL)
+
+#define INTC_ICDIPTR40_TGI4B                    (0x000000FFuL)
+#define INTC_ICDIPTR40_TGI4C                    (0x0000FF00uL)
+#define INTC_ICDIPTR40_TGI4D                    (0x00FF0000uL)
+#define INTC_ICDIPTR40_TGI4V                    (0xFF000000uL)
+
+#define INTC_ICDIPTR41_CMI1                     (0x000000FFuL)
+#define INTC_ICDIPTR41_CMI2                     (0x0000FF00uL)
+#define INTC_ICDIPTR41_SGDEI0                   (0x00FF0000uL)
+#define INTC_ICDIPTR41_SGDEI1                   (0xFF000000uL)
+
+#define INTC_ICDIPTR42_SGDEI2                   (0x000000FFuL)
+#define INTC_ICDIPTR42_SGDEI3                   (0x0000FF00uL)
+#define INTC_ICDIPTR42_ADI                      (0x00FF0000uL)
+#define INTC_ICDIPTR42_LMTI                     (0xFF000000uL)
+
+#define INTC_ICDIPTR43_SSII0                    (0x000000FFuL)
+#define INTC_ICDIPTR43_SSIRXI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR43_SSITXI0                  (0x00FF0000uL)
+#define INTC_ICDIPTR43_SSII1                    (0xFF000000uL)
+
+#define INTC_ICDIPTR44_SSIRXI1                  (0x000000FFuL)
+#define INTC_ICDIPTR44_SSITXI1                  (0x0000FF00uL)
+#define INTC_ICDIPTR44_SSII2                    (0x00FF0000uL)
+#define INTC_ICDIPTR44_SSIRTI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR45_SSII3                    (0x000000FFuL)
+#define INTC_ICDIPTR45_SSIRXI3                  (0x0000FF00uL)
+#define INTC_ICDIPTR45_SSITXI3                  (0x00FF0000uL)
+#define INTC_ICDIPTR45_SSII4                    (0xFF000000uL)
+
+#define INTC_ICDIPTR46_SSIRTI4                  (0x000000FFuL)
+#define INTC_ICDIPTR46_SSII5                    (0x0000FF00uL)
+#define INTC_ICDIPTR46_SSIRXI5                  (0x00FF0000uL)
+#define INTC_ICDIPTR46_SSITXI5                  (0xFF000000uL)
+
+#define INTC_ICDIPTR47_SPDIFI                   (0x000000FFuL)
+#define INTC_ICDIPTR47_INTIICTEI0               (0x0000FF00uL)
+#define INTC_ICDIPTR47_INTIICRI0                (0x00FF0000uL)
+#define INTC_ICDIPTR47_INTIICTI0                (0xFF000000uL)
+
+#define INTC_ICDIPTR48_INTIICSPI0               (0x000000FFuL)
+#define INTC_ICDIPTR48_INTIICSTI0               (0x0000FF00uL)
+#define INTC_ICDIPTR48_INTIICNAKI0              (0x00FF0000uL)
+#define INTC_ICDIPTR48_INTIICALI0               (0xFF000000uL)
+
+#define INTC_ICDIPTR49_INTIICTMOI0              (0x000000FFuL)
+#define INTC_ICDIPTR49_INTIICTEI1               (0x0000FF00uL)
+#define INTC_ICDIPTR49_INTIICRI1                (0x00FF0000uL)
+#define INTC_ICDIPTR49_INTIICTI1                (0xFF000000uL)
+
+#define INTC_ICDIPTR50_INTIICSPI1               (0x000000FFuL)
+#define INTC_ICDIPTR50_INTIICSTI1               (0x0000FF00uL)
+#define INTC_ICDIPTR50_INTIICNAKI1              (0x00FF0000uL)
+#define INTC_ICDIPTR50_INTIICALI1               (0xFF000000uL)
+
+#define INTC_ICDIPTR51_INTIICTMOI1              (0x000000FFuL)
+#define INTC_ICDIPTR51_INTIICTEI2               (0x0000FF00uL)
+#define INTC_ICDIPTR51_INTIICRI2                (0x00FF0000uL)
+#define INTC_ICDIPTR51_INTIICTI2                (0xFF000000uL)
+
+#define INTC_ICDIPTR52_INTIICSPI2               (0x000000FFuL)
+#define INTC_ICDIPTR52_INTIICSTI2               (0x0000FF00uL)
+#define INTC_ICDIPTR52_INTIICNAKI2              (0x00FF0000uL)
+#define INTC_ICDIPTR52_INTIICALI2               (0xFF000000uL)
+
+#define INTC_ICDIPTR53_INTIICTMOI2              (0x000000FFuL)
+#define INTC_ICDIPTR53_INTIICTEI3               (0x0000FF00uL)
+#define INTC_ICDIPTR53_INTIICRI3                (0x00FF0000uL)
+#define INTC_ICDIPTR53_INTIICTI3                (0xFF000000uL)
+
+#define INTC_ICDIPTR54_INTIICSPI3               (0x000000FFuL)
+#define INTC_ICDIPTR54_INTIICSTI3               (0x0000FF00uL)
+#define INTC_ICDIPTR54_INTIICNAKI3              (0x00FF0000uL)
+#define INTC_ICDIPTR54_INTIICALI3               (0xFF000000uL)
+
+#define INTC_ICDIPTR55_INTIICTMOI3              (0x000000FFuL)
+#define INTC_ICDIPTR55_BRI0                     (0x0000FF00uL)
+#define INTC_ICDIPTR55_ERI0                     (0x00FF0000uL)
+#define INTC_ICDIPTR55_RXI0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR56_TXI0                     (0x000000FFuL)
+#define INTC_ICDIPTR56_BRI1                     (0x0000FF00uL)
+#define INTC_ICDIPTR56_ERI1                     (0x00FF0000uL)
+#define INTC_ICDIPTR56_RXI1                     (0xFF000000uL)
+
+#define INTC_ICDIPTR57_TXI1                     (0x000000FFuL)
+#define INTC_ICDIPTR57_BRI2                     (0x0000FF00uL)
+#define INTC_ICDIPTR57_ERI2                     (0x00FF0000uL)
+#define INTC_ICDIPTR57_RXI2                     (0xFF000000uL)
+
+#define INTC_ICDIPTR58_TXI2                     (0x000000FFuL)
+#define INTC_ICDIPTR58_BRI3                     (0x0000FF00uL)
+#define INTC_ICDIPTR58_ERI3                     (0x00FF0000uL)
+#define INTC_ICDIPTR58_RXI3                     (0xFF000000uL)
+
+#define INTC_ICDIPTR59_TXI3                     (0x000000FFuL)
+#define INTC_ICDIPTR59_BRI4                     (0x0000FF00uL)
+#define INTC_ICDIPTR59_ERI4                     (0x00FF0000uL)
+#define INTC_ICDIPTR59_RXI4                     (0xFF000000uL)
+
+#define INTC_ICDIPTR60_TXI4                     (0x000000FFuL)
+#define INTC_ICDIPTR60_BRI5                     (0x0000FF00uL)
+#define INTC_ICDIPTR60_ERI5                     (0x00FF0000uL)
+#define INTC_ICDIPTR60_RXI5                     (0xFF000000uL)
+
+#define INTC_ICDIPTR61_TXI5                     (0x000000FFuL)
+#define INTC_ICDIPTR61_BRI6                     (0x0000FF00uL)
+#define INTC_ICDIPTR61_ERI6                     (0x00FF0000uL)
+#define INTC_ICDIPTR61_RXI6                     (0xFF000000uL)
+
+#define INTC_ICDIPTR62_TXI6                     (0x000000FFuL)
+#define INTC_ICDIPTR62_BRI7                     (0x0000FF00uL)
+#define INTC_ICDIPTR62_ERI7                     (0x00FF0000uL)
+#define INTC_ICDIPTR62_RXI7                     (0xFF000000uL)
+
+#define INTC_ICDIPTR63_TXI7                     (0x000000FFuL)
+#define INTC_ICDIPTR63_INTRCANGERR              (0x0000FF00uL)
+#define INTC_ICDIPTR63_INTRCANGRECC             (0x00FF0000uL)
+#define INTC_ICDIPTR63_INTRCAN0REC              (0xFF000000uL)
+
+#define INTC_ICDIPTR64_INTRCAN0ERR              (0x000000FFuL)
+#define INTC_ICDIPTR64_INTRCAN0TRX              (0x0000FF00uL)
+#define INTC_ICDIPTR64_INTRCAN1REC              (0x00FF0000uL)
+#define INTC_ICDIPTR64_INTRCAN1ERR              (0xFF000000uL)
+
+#define INTC_ICDIPTR65_INTRCAN1TRX              (0x000000FFuL)
+#define INTC_ICDIPTR65_INTRCAN2REC              (0x0000FF00uL)
+#define INTC_ICDIPTR65_INTRCAN2ERR              (0x00FF0000uL)
+#define INTC_ICDIPTR65_INTRCAN2TRX              (0xFF000000uL)
+
+#define INTC_ICDIPTR66_INTRCAN3REC              (0x000000FFuL)
+#define INTC_ICDIPTR66_INTRCAN3ERR              (0x0000FF00uL)
+#define INTC_ICDIPTR66_INTRCAN3TRX              (0x00FF0000uL)
+#define INTC_ICDIPTR66_INTRCAN4REC              (0xFF000000uL)
+
+#define INTC_ICDIPTR67_INTRCAN4ERR              (0x000000FFuL)
+#define INTC_ICDIPTR67_INTRCAN4TRX              (0x0000FF00uL)
+#define INTC_ICDIPTR67_SPEI0                    (0x00FF0000uL)
+#define INTC_ICDIPTR67_SPRI0                    (0xFF000000uL)
+
+#define INTC_ICDIPTR68_SPTI0                    (0x000000FFuL)
+#define INTC_ICDIPTR68_SPEI1                    (0x0000FF00uL)
+#define INTC_ICDIPTR68_SPRI1                    (0x00FF0000uL)
+#define INTC_ICDIPTR68_SPTI1                    (0xFF000000uL)
+
+#define INTC_ICDIPTR69_SPEI2                    (0x000000FFuL)
+#define INTC_ICDIPTR69_SPRI2                    (0x0000FF00uL)
+#define INTC_ICDIPTR69_SPTI2                    (0x00FF0000uL)
+#define INTC_ICDIPTR69_SPEI3                    (0xFF000000uL)
+
+#define INTC_ICDIPTR70_SPRI3                    (0x000000FFuL)
+#define INTC_ICDIPTR70_SPTI3                    (0x0000FF00uL)
+#define INTC_ICDIPTR70_SPEI4                    (0x00FF0000uL)
+#define INTC_ICDIPTR70_SPRI4                    (0xFF000000uL)
+
+#define INTC_ICDIPTR71_SPTI4                    (0x000000FFuL)
+#define INTC_ICDIPTR71_IEBBTD                   (0x0000FF00uL)
+#define INTC_ICDIPTR71_IEBBTERR                 (0x00FF0000uL)
+#define INTC_ICDIPTR71_IEBBTSTA                 (0xFF000000uL)
+
+#define INTC_ICDIPTR72_IEBBTV                   (0x000000FFuL)
+#define INTC_ICDIPTR72_ISY                      (0x0000FF00uL)
+#define INTC_ICDIPTR72_IERR                     (0x00FF0000uL)
+#define INTC_ICDIPTR72_ITARG                    (0xFF000000uL)
+
+#define INTC_ICDIPTR73_ISEC                     (0x000000FFuL)
+#define INTC_ICDIPTR73_IBUF                     (0x0000FF00uL)
+#define INTC_ICDIPTR73_IREADY                   (0x00FF0000uL)
+#define INTC_ICDIPTR73_FLSTE                    (0xFF000000uL)
+
+#define INTC_ICDIPTR74_FLTENDI                  (0x000000FFuL)
+#define INTC_ICDIPTR74_FLTREQ0I                 (0x0000FF00uL)
+#define INTC_ICDIPTR74_FLTREQ1I                 (0x00FF0000uL)
+#define INTC_ICDIPTR74_MMC0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR75_MMC1                     (0x000000FFuL)
+#define INTC_ICDIPTR75_MMC2                     (0x0000FF00uL)
+#define INTC_ICDIPTR75_SDHI0_3                  (0x00FF0000uL)
+#define INTC_ICDIPTR75_SDHI0_0                  (0xFF000000uL)
+
+#define INTC_ICDIPTR76_SDHI0_1                  (0x000000FFuL)
+#define INTC_ICDIPTR76_SDHI1_3                  (0x0000FF00uL)
+#define INTC_ICDIPTR76_SDHI1_0                  (0x00FF0000uL)
+#define INTC_ICDIPTR76_SDHI1_1                  (0xFF000000uL)
+
+#define INTC_ICDIPTR77_ARM                      (0x000000FFuL)
+#define INTC_ICDIPTR77_PRD                      (0x0000FF00uL)
+#define INTC_ICDIPTR77_CUP                      (0x00FF0000uL)
+#define INTC_ICDIPTR77_SCUAI0                   (0xFF000000uL)
+
+#define INTC_ICDIPTR78_SCUAI1                   (0x000000FFuL)
+#define INTC_ICDIPTR78_SCUFDI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR78_SCUFDI1                  (0x00FF0000uL)
+#define INTC_ICDIPTR78_SCUFDI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR79_SCUFDI3                  (0x000000FFuL)
+#define INTC_ICDIPTR79_SCUFUI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR79_SCUFUI1                  (0x00FF0000uL)
+#define INTC_ICDIPTR79_SCUFUI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR80_SCUFUI3                  (0x000000FFuL)
+#define INTC_ICDIPTR80_SCUDVI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR80_SCUDVI1                  (0x00FF0000uL)
+#define INTC_ICDIPTR80_SCUDVI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR81_SCUDVI3                  (0x000000FFuL)
+#define INTC_ICDIPTR81_MLB_CINT                 (0x0000FF00uL)
+#define INTC_ICDIPTR81_MLB_SINT                 (0x00FF0000uL)
+#define INTC_ICDIPTR81_DRC0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR82_DRC1                     (0x000000FFuL)
+#define INTC_ICDIPTR82_LINI0_INT_T              (0xFF000000uL)
+
+#define INTC_ICDIPTR83_LINI0_INT_R              (0x000000FFuL)
+#define INTC_ICDIPTR83_LINI0_INT_S              (0x0000FF00uL)
+#define INTC_ICDIPTR83_LINI0_INT_M              (0x00FF0000uL)
+#define INTC_ICDIPTR83_LINI1_INT_T              (0xFF000000uL)
+
+#define INTC_ICDIPTR84_LINI1_INT_R              (0x000000FFuL)
+#define INTC_ICDIPTR84_LINI1_INT_S              (0x0000FF00uL)
+#define INTC_ICDIPTR84_LINI1_INT_M              (0x00FF0000uL)
+
+#define INTC_ICDIPTR86_ERI0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR87_RXI0                     (0x000000FFuL)
+#define INTC_ICDIPTR87_TXI0                     (0x0000FF00uL)
+#define INTC_ICDIPTR87_TEI0                     (0x00FF0000uL)
+#define INTC_ICDIPTR87_ERI1                     (0xFF000000uL)
+
+#define INTC_ICDIPTR88_RXI1                     (0x000000FFuL)
+#define INTC_ICDIPTR88_TXI1                     (0x0000FF00uL)
+#define INTC_ICDIPTR88_TEI1                     (0x00FF0000uL)
+#define INTC_ICDIPTR88_AVBI_DATA                (0xFF000000uL)
+
+#define INTC_ICDIPTR89_AVBI_ERROR               (0x000000FFuL)
+#define INTC_ICDIPTR89_AVBI_MANAGE              (0x0000FF00uL)
+#define INTC_ICDIPTR89_AVBI_MAC                 (0x00FF0000uL)
+#define INTC_ICDIPTR89_ETHERI                   (0xFF000000uL)
+
+#define INTC_ICDIPTR91_CEUI                     (0x000000FFuL)
+
+#define INTC_ICDIPTR95_H2XMLB_ERRINT            (0x0000FF00uL)
+#define INTC_ICDIPTR95_H2XIC1_ERRINT            (0x00FF0000uL)
+#define INTC_ICDIPTR95_X2HPERI1_ERRINT          (0xFF000000uL)
+
+#define INTC_ICDIPTR96_X2HPERI2_ERRINT          (0x000000FFuL)
+#define INTC_ICDIPTR96_X2HPERI34_ERRINT         (0x0000FF00uL)
+#define INTC_ICDIPTR96_X2HPERI5_ERRINT          (0x00FF0000uL)
+#define INTC_ICDIPTR96_X2HPERI67_ERRINT         (0xFF000000uL)
+
+#define INTC_ICDIPTR97_X2HDBGR_ERRINT           (0x000000FFuL)
+#define INTC_ICDIPTR97_X2HBSC_ERRINT            (0x0000FF00uL)
+#define INTC_ICDIPTR97_X2HSPI1_ERRINT           (0x00FF0000uL)
+#define INTC_ICDIPTR97_X2HSPI2_ERRINT           (0xFF000000uL)
+
+#define INTC_ICDIPTR98_PRRI                     (0x000000FFuL)
+#define INTC_ICDIPTR98_IFEI0                    (0x0000FF00uL)
+#define INTC_ICDIPTR98_OFFI0                    (0x00FF0000uL)
+#define INTC_ICDIPTR98_PFVEI0                   (0xFF000000uL)
+
+#define INTC_ICDIPTR99_IFEI1                    (0x000000FFuL)
+#define INTC_ICDIPTR99_OFFI1                    (0x0000FF00uL)
+#define INTC_ICDIPTR99_PFVEI1                   (0x00FF0000uL)
+
+#define INTC_ICDIPTR104_TINT0                   (0x000000FFuL)
+#define INTC_ICDIPTR104_TINT1                   (0x0000FF00uL)
+#define INTC_ICDIPTR104_TINT2                   (0x00FF0000uL)
+#define INTC_ICDIPTR104_TINT3                   (0xFF000000uL)
+
+#define INTC_ICDIPTR105_TINT4                   (0x000000FFuL)
+#define INTC_ICDIPTR105_TINT5                   (0x0000FF00uL)
+#define INTC_ICDIPTR105_TINT6                   (0x00FF0000uL)
+#define INTC_ICDIPTR105_TINT7                   (0xFF000000uL)
+
+#define INTC_ICDIPTR106_TINT8                   (0x000000FFuL)
+#define INTC_ICDIPTR106_TINT9                   (0x0000FF00uL)
+#define INTC_ICDIPTR106_TINT10                  (0x00FF0000uL)
+#define INTC_ICDIPTR106_TINT11                  (0xFF000000uL)
+
+#define INTC_ICDIPTR107_TINT12                  (0x000000FFuL)
+#define INTC_ICDIPTR107_TINT13                  (0x0000FF00uL)
+#define INTC_ICDIPTR107_TINT14                  (0x00FF0000uL)
+#define INTC_ICDIPTR107_TINT15                  (0xFF000000uL)
+
+#define INTC_ICDIPTR108_TINT16                  (0x000000FFuL)
+#define INTC_ICDIPTR108_TINT17                  (0x0000FF00uL)
+#define INTC_ICDIPTR108_TINT18                  (0x00FF0000uL)
+#define INTC_ICDIPTR108_TINT19                  (0xFF000000uL)
+
+#define INTC_ICDIPTR109_TINT20                  (0x000000FFuL)
+#define INTC_ICDIPTR109_TINT21                  (0x0000FF00uL)
+#define INTC_ICDIPTR109_TINT22                  (0x00FF0000uL)
+#define INTC_ICDIPTR109_TINT23                  (0xFF000000uL)
+
+#define INTC_ICDIPTR110_TINT24                  (0x000000FFuL)
+#define INTC_ICDIPTR110_TINT25                  (0x0000FF00uL)
+#define INTC_ICDIPTR110_TINT26                  (0x00FF0000uL)
+#define INTC_ICDIPTR110_TINT27                  (0xFF000000uL)
+
+#define INTC_ICDIPTR111_TINT28                  (0x000000FFuL)
+#define INTC_ICDIPTR111_TINT29                  (0x0000FF00uL)
+#define INTC_ICDIPTR111_TINT30                  (0x00FF0000uL)
+#define INTC_ICDIPTR111_TINT31                  (0xFF000000uL)
+
+#define INTC_ICDIPTR112_TINT32                  (0x000000FFuL)
+#define INTC_ICDIPTR112_TINT33                  (0x0000FF00uL)
+#define INTC_ICDIPTR112_TINT34                  (0x00FF0000uL)
+#define INTC_ICDIPTR112_TINT35                  (0xFF000000uL)
+
+#define INTC_ICDIPTR113_TINT36                  (0x000000FFuL)
+#define INTC_ICDIPTR113_TINT37                  (0x0000FF00uL)
+#define INTC_ICDIPTR113_TINT38                  (0x00FF0000uL)
+#define INTC_ICDIPTR113_TINT39                  (0xFF000000uL)
+
+#define INTC_ICDIPTR114_TINT40                  (0x000000FFuL)
+#define INTC_ICDIPTR114_TINT41                  (0x0000FF00uL)
+#define INTC_ICDIPTR114_TINT42                  (0x00FF0000uL)
+#define INTC_ICDIPTR114_TINT43                  (0xFF000000uL)
+
+#define INTC_ICDIPTR115_TINT44                  (0x000000FFuL)
+#define INTC_ICDIPTR115_TINT45                  (0x0000FF00uL)
+#define INTC_ICDIPTR115_TINT46                  (0x00FF0000uL)
+#define INTC_ICDIPTR115_TINT47                  (0xFF000000uL)
+
+#define INTC_ICDIPTR116_TINT48                  (0x000000FFuL)
+#define INTC_ICDIPTR116_TINT49                  (0x0000FF00uL)
+#define INTC_ICDIPTR116_TINT50                  (0x00FF0000uL)
+#define INTC_ICDIPTR116_TINT51                  (0xFF000000uL)
+
+#define INTC_ICDIPTR117_TINT52                  (0x000000FFuL)
+#define INTC_ICDIPTR117_TINT53                  (0x0000FF00uL)
+#define INTC_ICDIPTR117_TINT54                  (0x00FF0000uL)
+#define INTC_ICDIPTR117_TINT55                  (0xFF000000uL)
+
+#define INTC_ICDIPTR118_TINT56                  (0x000000FFuL)
+#define INTC_ICDIPTR118_TINT57                  (0x0000FF00uL)
+#define INTC_ICDIPTR118_TINT58                  (0x00FF0000uL)
+#define INTC_ICDIPTR118_TINT59                  (0xFF000000uL)
+
+#define INTC_ICDIPTR119_TINT60                  (0x000000FFuL)
+#define INTC_ICDIPTR119_TINT61                  (0x0000FF00uL)
+#define INTC_ICDIPTR119_TINT62                  (0x00FF0000uL)
+#define INTC_ICDIPTR119_TINT63                  (0xFF000000uL)
+
+#define INTC_ICDIPTR120_TINT64                  (0x000000FFuL)
+#define INTC_ICDIPTR120_TINT65                  (0x0000FF00uL)
+#define INTC_ICDIPTR120_TINT66                  (0x00FF0000uL)
+#define INTC_ICDIPTR120_TINT67                  (0xFF000000uL)
+
+#define INTC_ICDIPTR121_TINT68                  (0x000000FFuL)
+#define INTC_ICDIPTR121_TINT69                  (0x0000FF00uL)
+#define INTC_ICDIPTR121_TINT70                  (0x00FF0000uL)
+#define INTC_ICDIPTR121_TINT71                  (0xFF000000uL)
+
+#define INTC_ICDIPTR122_TINT72                  (0x000000FFuL)
+#define INTC_ICDIPTR122_TINT73                  (0x0000FF00uL)
+#define INTC_ICDIPTR122_TINT74                  (0x00FF0000uL)
+#define INTC_ICDIPTR122_TINT75                  (0xFF000000uL)
+
+#define INTC_ICDIPTR123_TINT76                  (0x000000FFuL)
+#define INTC_ICDIPTR123_TINT77                  (0x0000FF00uL)
+#define INTC_ICDIPTR123_TINT78                  (0x00FF0000uL)
+#define INTC_ICDIPTR123_TINT79                  (0xFF000000uL)
+
+#define INTC_ICDIPTR124_TINT80                  (0x000000FFuL)
+#define INTC_ICDIPTR124_TINT81                  (0x0000FF00uL)
+#define INTC_ICDIPTR124_TINT82                  (0x00FF0000uL)
+#define INTC_ICDIPTR124_TINT83                  (0xFF000000uL)
+
+#define INTC_ICDIPTR125_TINT84                  (0x000000FFuL)
+#define INTC_ICDIPTR125_TINT85                  (0x0000FF00uL)
+#define INTC_ICDIPTR125_TINT86                  (0x00FF0000uL)
+#define INTC_ICDIPTR125_TINT87                  (0xFF000000uL)
+
+#define INTC_ICDIPTR126_TINT88                  (0x000000FFuL)
+#define INTC_ICDIPTR126_TINT89                  (0x0000FF00uL)
+#define INTC_ICDIPTR126_TINT90                  (0x00FF0000uL)
+#define INTC_ICDIPTR126_TINT91                  (0xFF000000uL)
+
+#define INTC_ICDIPTR127_TINT92                  (0x000000FFuL)
+#define INTC_ICDIPTR127_TINT93                  (0x0000FF00uL)
+#define INTC_ICDIPTR127_TINT94                  (0x00FF0000uL)
+#define INTC_ICDIPTR127_TINT95                  (0xFF000000uL)
+
+#define INTC_ICDIPTR128_TINT96                  (0x000000FFuL)
+#define INTC_ICDIPTR128_TINT97                  (0x0000FF00uL)
+#define INTC_ICDIPTR128_TINT98                  (0x00FF0000uL)
+#define INTC_ICDIPTR128_TINT99                  (0xFF000000uL)
+
+#define INTC_ICDIPTR129_TINT100                 (0x000000FFuL)
+#define INTC_ICDIPTR129_TINT101                 (0x0000FF00uL)
+#define INTC_ICDIPTR129_TINT102                 (0x00FF0000uL)
+#define INTC_ICDIPTR129_TINT103                 (0xFF000000uL)
+
+#define INTC_ICDIPTR130_TINT104                 (0x000000FFuL)
+#define INTC_ICDIPTR130_TINT105                 (0x0000FF00uL)
+#define INTC_ICDIPTR130_TINT106                 (0x00FF0000uL)
+#define INTC_ICDIPTR130_TINT107                 (0xFF000000uL)
+
+#define INTC_ICDIPTR131_TINT108                 (0x000000FFuL)
+#define INTC_ICDIPTR131_TINT109                 (0x0000FF00uL)
+#define INTC_ICDIPTR131_TINT110                 (0x00FF0000uL)
+#define INTC_ICDIPTR131_TINT111                 (0xFF000000uL)
+
+#define INTC_ICDIPTR132_TINT112                 (0x000000FFuL)
+#define INTC_ICDIPTR132_TINT113                 (0x0000FF00uL)
+#define INTC_ICDIPTR132_TINT114                 (0x00FF0000uL)
+#define INTC_ICDIPTR132_TINT115                 (0xFF000000uL)
+
+#define INTC_ICDIPTR133_TINT116                 (0x000000FFuL)
+#define INTC_ICDIPTR133_TINT117                 (0x0000FF00uL)
+#define INTC_ICDIPTR133_TINT118                 (0x00FF0000uL)
+#define INTC_ICDIPTR133_TINT119                 (0xFF000000uL)
+
+#define INTC_ICDIPTR134_TINT120                 (0x000000FFuL)
+#define INTC_ICDIPTR134_TINT121                 (0x0000FF00uL)
+#define INTC_ICDIPTR134_TINT122                 (0x00FF0000uL)
+#define INTC_ICDIPTR134_TINT123                 (0xFF000000uL)
+
+#define INTC_ICDIPTR135_TINT124                 (0x000000FFuL)
+#define INTC_ICDIPTR135_TINT125                 (0x0000FF00uL)
+#define INTC_ICDIPTR135_TINT126                 (0x00FF0000uL)
+#define INTC_ICDIPTR135_TINT127                 (0xFF000000uL)
+
+#define INTC_ICDIPTR136_TINT128                 (0x000000FFuL)
+#define INTC_ICDIPTR136_TINT129                 (0x0000FF00uL)
+#define INTC_ICDIPTR136_TINT130                 (0x00FF0000uL)
+#define INTC_ICDIPTR136_TINT131                 (0xFF000000uL)
+
+#define INTC_ICDIPTR137_TINT132                 (0x000000FFuL)
+#define INTC_ICDIPTR137_TINT133                 (0x0000FF00uL)
+#define INTC_ICDIPTR137_TINT134                 (0x00FF0000uL)
+#define INTC_ICDIPTR137_TINT135                 (0xFF000000uL)
+
+#define INTC_ICDIPTR138_TINT136                 (0x000000FFuL)
+#define INTC_ICDIPTR138_TINT137                 (0x0000FF00uL)
+#define INTC_ICDIPTR138_TINT138                 (0x00FF0000uL)
+#define INTC_ICDIPTR138_TINT139                 (0xFF000000uL)
+
+#define INTC_ICDIPTR139_TINT140                 (0x000000FFuL)
+#define INTC_ICDIPTR139_TINT141                 (0x0000FF00uL)
+#define INTC_ICDIPTR139_TINT142                 (0x00FF0000uL)
+#define INTC_ICDIPTR139_TINT143                 (0xFF000000uL)
+
+#define INTC_ICDIPTR140_TINT144                 (0x000000FFuL)
+#define INTC_ICDIPTR140_TINT145                 (0x0000FF00uL)
+#define INTC_ICDIPTR140_TINT146                 (0x00FF0000uL)
+#define INTC_ICDIPTR140_TINT147                 (0xFF000000uL)
+
+#define INTC_ICDIPTR141_TINT148                 (0x000000FFuL)
+#define INTC_ICDIPTR141_TINT149                 (0x0000FF00uL)
+#define INTC_ICDIPTR141_TINT150                 (0x00FF0000uL)
+#define INTC_ICDIPTR141_TINT151                 (0xFF000000uL)
+
+#define INTC_ICDIPTR142_TINT152                 (0x000000FFuL)
+#define INTC_ICDIPTR142_TINT153                 (0x0000FF00uL)
+#define INTC_ICDIPTR142_TINT154                 (0x00FF0000uL)
+#define INTC_ICDIPTR142_TINT155                 (0xFF000000uL)
+
+#define INTC_ICDIPTR143_TINT156                 (0x000000FFuL)
+#define INTC_ICDIPTR143_TINT157                 (0x0000FF00uL)
+#define INTC_ICDIPTR143_TINT158                 (0x00FF0000uL)
+#define INTC_ICDIPTR143_TINT159                 (0xFF000000uL)
+
+#define INTC_ICDIPTR144_TINT160                 (0x000000FFuL)
+#define INTC_ICDIPTR144_TINT161                 (0x0000FF00uL)
+#define INTC_ICDIPTR144_TINT162                 (0x00FF0000uL)
+#define INTC_ICDIPTR144_TINT163                 (0xFF000000uL)
+
+#define INTC_ICDIPTR145_TINT164                 (0x000000FFuL)
+#define INTC_ICDIPTR145_TINT165                 (0x0000FF00uL)
+#define INTC_ICDIPTR145_TINT166                 (0x00FF0000uL)
+#define INTC_ICDIPTR145_TINT167                 (0xFF000000uL)
+
+#define INTC_ICDIPTR146_TINT168                 (0x000000FFuL)
+#define INTC_ICDIPTR146_TINT169                 (0x0000FF00uL)
+#define INTC_ICDIPTR146_TINT170                 (0x00FF0000uL)
+
+#define INTC_ICDICFR0_SW0_0                     (0x00000001uL)
+#define INTC_ICDICFR0_SW0_1                     (0x00000002uL)
+#define INTC_ICDICFR0_SW1_0                     (0x00000004uL)
+#define INTC_ICDICFR0_SW1_1                     (0x00000008uL)
+#define INTC_ICDICFR0_SW2_0                     (0x00000010uL)
+#define INTC_ICDICFR0_SW2_1                     (0x00000020uL)
+#define INTC_ICDICFR0_SW3_0                     (0x00000040uL)
+#define INTC_ICDICFR0_SW3_1                     (0x00000080uL)
+#define INTC_ICDICFR0_SW4_0                     (0x00000100uL)
+#define INTC_ICDICFR0_SW4_1                     (0x00000200uL)
+#define INTC_ICDICFR0_SW5_0                     (0x00000400uL)
+#define INTC_ICDICFR0_SW5_1                     (0x00000800uL)
+#define INTC_ICDICFR0_SW6_0                     (0x00001000uL)
+#define INTC_ICDICFR0_SW6_1                     (0x00002000uL)
+#define INTC_ICDICFR0_SW7_0                     (0x00004000uL)
+#define INTC_ICDICFR0_SW7_1                     (0x00008000uL)
+#define INTC_ICDICFR0_SW8_0                     (0x00010000uL)
+#define INTC_ICDICFR0_SW8_1                     (0x00020000uL)
+#define INTC_ICDICFR0_SW9_0                     (0x00040000uL)
+#define INTC_ICDICFR0_SW9_1                     (0x00080000uL)
+#define INTC_ICDICFR0_SW10_0                    (0x00100000uL)
+#define INTC_ICDICFR0_SW10_1                    (0x00200000uL)
+#define INTC_ICDICFR0_SW11_0                    (0x00400000uL)
+#define INTC_ICDICFR0_SW11_1                    (0x00800000uL)
+#define INTC_ICDICFR0_SW12_0                    (0x01000000uL)
+#define INTC_ICDICFR0_SW12_1                    (0x02000000uL)
+#define INTC_ICDICFR0_SW13_0                    (0x04000000uL)
+#define INTC_ICDICFR0_SW13_1                    (0x08000000uL)
+#define INTC_ICDICFR0_SW14_0                    (0x10000000uL)
+#define INTC_ICDICFR0_SW14_1                    (0x20000000uL)
+#define INTC_ICDICFR0_SW15_0                    (0x40000000uL)
+#define INTC_ICDICFR0_SW15_1                    (0x80000000uL)
+
+#define INTC_ICDICFR1_PMUIRQ0_0                 (0x00000001uL)
+#define INTC_ICDICFR1_PMUIRQ0_1                 (0x00000002uL)
+#define INTC_ICDICFR1_COMMRX0_0                 (0x00000004uL)
+#define INTC_ICDICFR1_COMMRX0_1                 (0x00000008uL)
+#define INTC_ICDICFR1_COMMTX0_0                 (0x00000010uL)
+#define INTC_ICDICFR1_COMMTX0_1                 (0x00000020uL)
+#define INTC_ICDICFR1_CTIIRQ0_0                 (0x00000040uL)
+#define INTC_ICDICFR1_CTIIRQ0_1                 (0x00000080uL)
+
+#define INTC_ICDICFR2_IRQ0_0                    (0x00000001uL)
+#define INTC_ICDICFR2_IRQ0_1                    (0x00000002uL)
+#define INTC_ICDICFR2_IRQ1_0                    (0x00000004uL)
+#define INTC_ICDICFR2_IRQ1_1                    (0x00000008uL)
+#define INTC_ICDICFR2_IRQ2_0                    (0x00000010uL)
+#define INTC_ICDICFR2_IRQ2_1                    (0x00000020uL)
+#define INTC_ICDICFR2_IRQ3_0                    (0x00000040uL)
+#define INTC_ICDICFR2_IRQ3_1                    (0x00000080uL)
+#define INTC_ICDICFR2_IRQ4_0                    (0x00000100uL)
+#define INTC_ICDICFR2_IRQ4_1                    (0x00000200uL)
+#define INTC_ICDICFR2_IRQ5_0                    (0x00000400uL)
+#define INTC_ICDICFR2_IRQ5_1                    (0x00000800uL)
+#define INTC_ICDICFR2_IRQ6_0                    (0x00001000uL)
+#define INTC_ICDICFR2_IRQ6_1                    (0x00002000uL)
+#define INTC_ICDICFR2_IRQ7_0                    (0x00004000uL)
+#define INTC_ICDICFR2_IRQ7_1                    (0x00008000uL)
+#define INTC_ICDICFR2_PL310ERR_0                (0x00010000uL)
+#define INTC_ICDICFR2_PL310ERR_1                (0x00020000uL)
+#define INTC_ICDICFR2_DMAINT0_0                 (0x00040000uL)
+#define INTC_ICDICFR2_DMAINT0_1                 (0x00080000uL)
+#define INTC_ICDICFR2_DMAINT1_0                 (0x00100000uL)
+#define INTC_ICDICFR2_DMAINT1_1                 (0x00200000uL)
+#define INTC_ICDICFR2_DMAINT2_0                 (0x00400000uL)
+#define INTC_ICDICFR2_DMAINT2_1                 (0x00800000uL)
+#define INTC_ICDICFR2_DMAINT3_0                 (0x01000000uL)
+#define INTC_ICDICFR2_DMAINT3_1                 (0x02000000uL)
+#define INTC_ICDICFR2_DMAINT4_0                 (0x04000000uL)
+#define INTC_ICDICFR2_DMAINT4_1                 (0x08000000uL)
+#define INTC_ICDICFR2_DMAINT5_0                 (0x10000000uL)
+#define INTC_ICDICFR2_DMAINT5_1                 (0x20000000uL)
+#define INTC_ICDICFR2_DMAINT6_0                 (0x40000000uL)
+#define INTC_ICDICFR2_DMAINT6_1                 (0x80000000uL)
+
+#define INTC_ICDICFR3_DMAINT7_0                 (0x00000001uL)
+#define INTC_ICDICFR3_DMAINT7_1                 (0x00000002uL)
+#define INTC_ICDICFR3_DMAINT8_0                 (0x00000004uL)
+#define INTC_ICDICFR3_DMAINT8_1                 (0x00000008uL)
+#define INTC_ICDICFR3_DMAINT9_0                 (0x00000010uL)
+#define INTC_ICDICFR3_DMAINT9_1                 (0x00000020uL)
+#define INTC_ICDICFR3_DMAINT10_0                (0x00000040uL)
+#define INTC_ICDICFR3_DMAINT10_1                (0x00000080uL)
+#define INTC_ICDICFR3_DMAINT11_0                (0x00000100uL)
+#define INTC_ICDICFR3_DMAINT11_1                (0x00000200uL)
+#define INTC_ICDICFR3_DMAINT12_0                (0x00000400uL)
+#define INTC_ICDICFR3_DMAINT12_1                (0x00000800uL)
+#define INTC_ICDICFR3_DMAINT13_0                (0x00001000uL)
+#define INTC_ICDICFR3_DMAINT13_1                (0x00002000uL)
+#define INTC_ICDICFR3_DMAINT14_0                (0x00004000uL)
+#define INTC_ICDICFR3_DMAINT14_1                (0x00008000uL)
+#define INTC_ICDICFR3_DMAINT15_0                (0x00010000uL)
+#define INTC_ICDICFR3_DMAINT15_1                (0x00020000uL)
+#define INTC_ICDICFR3_DMAERR_0                  (0x00040000uL)
+#define INTC_ICDICFR3_DMAERR_1                  (0x00080000uL)
+
+#define INTC_ICDICFR4_USBI0_0                   (0x00040000uL)
+#define INTC_ICDICFR4_USBI0_1                   (0x00080000uL)
+#define INTC_ICDICFR4_USBI1_0                   (0x00100000uL)
+#define INTC_ICDICFR4_USBI1_1                   (0x00200000uL)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_0            (0x00400000uL)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_1            (0x00800000uL)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_0            (0x01000000uL)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_1            (0x02000000uL)
+#define INTC_ICDICFR4_S0_VSYNCERR0_0            (0x04000000uL)
+#define INTC_ICDICFR4_S0_VSYNCERR0_1            (0x08000000uL)
+#define INTC_ICDICFR4_GR3_VLINE0_0              (0x10000000uL)
+#define INTC_ICDICFR4_GR3_VLINE0_1              (0x20000000uL)
+#define INTC_ICDICFR4_S0_VFIELD0_0              (0x40000000uL)
+#define INTC_ICDICFR4_S0_VFIELD0_1              (0x80000000uL)
+
+#define INTC_ICDICFR5_IV1_VBUFERR0_0            (0x00000001uL)
+#define INTC_ICDICFR5_IV1_VBUFERR0_1            (0x00000002uL)
+#define INTC_ICDICFR5_IV3_VBUFERR0_0            (0x00000004uL)
+#define INTC_ICDICFR5_IV3_VBUFERR0_1            (0x00000008uL)
+#define INTC_ICDICFR5_IV5_VBUFERR0_0            (0x00000010uL)
+#define INTC_ICDICFR5_IV5_VBUFERR0_1            (0x00000020uL)
+#define INTC_ICDICFR5_IV6_VBUFERR0_0            (0x00000040uL)
+#define INTC_ICDICFR5_IV6_VBUFERR0_1            (0x00000080uL)
+#define INTC_ICDICFR5_S0_WLINE0_0               (0x00000100uL)
+#define INTC_ICDICFR5_S0_WLINE0_1               (0x00000200uL)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_0            (0x00000400uL)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_1            (0x00000800uL)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_0            (0x00001000uL)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_1            (0x00002000uL)
+#define INTC_ICDICFR5_S1_VSYNCERR0_0            (0x00004000uL)
+#define INTC_ICDICFR5_S1_VSYNCERR0_1            (0x00008000uL)
+#define INTC_ICDICFR5_S1_VFIELD0_0              (0x00010000uL)
+#define INTC_ICDICFR5_S1_VFIELD0_1              (0x00020000uL)
+#define INTC_ICDICFR5_IV2_VBUFERR0_0            (0x00040000uL)
+#define INTC_ICDICFR5_IV2_VBUFERR0_1            (0x00080000uL)
+#define INTC_ICDICFR5_IV4_VBUFERR0_0            (0x00100000uL)
+#define INTC_ICDICFR5_IV4_VBUFERR0_1            (0x00200000uL)
+#define INTC_ICDICFR5_S1_WLINE0_0               (0x00400000uL)
+#define INTC_ICDICFR5_S1_WLINE0_1               (0x00800000uL)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_0           (0x01000000uL)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_1           (0x02000000uL)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_0           (0x04000000uL)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_1           (0x08000000uL)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_0           (0x10000000uL)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_1           (0x20000000uL)
+#define INTC_ICDICFR5_OIR_VFIELD0_0             (0x40000000uL)
+#define INTC_ICDICFR5_OIR_VFIELD0_1             (0x80000000uL)
+
+#define INTC_ICDICFR6_IV7_VBUFERR0_0            (0x00000001uL)
+#define INTC_ICDICFR6_IV7_VBUFERR0_1            (0x00000002uL)
+#define INTC_ICDICFR6_IV8_VBUFERR0_0            (0x00000004uL)
+#define INTC_ICDICFR6_IV8_VBUFERR0_1            (0x00000008uL)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_0            (0x00000040uL)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_1            (0x00000080uL)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_0            (0x00000100uL)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_1            (0x00000200uL)
+#define INTC_ICDICFR6_S0_VSYNCERR1_0            (0x00000400uL)
+#define INTC_ICDICFR6_S0_VSYNCERR1_1            (0x00000800uL)
+#define INTC_ICDICFR6_GR3_VLINE1_0              (0x00001000uL)
+#define INTC_ICDICFR6_GR3_VLINE1_1              (0x00002000uL)
+#define INTC_ICDICFR6_S0_VFIELD1_0              (0x00004000uL)
+#define INTC_ICDICFR6_S0_VFIELD1_1              (0x00008000uL)
+#define INTC_ICDICFR6_IV1_VBUFERR1_0            (0x00010000uL)
+#define INTC_ICDICFR6_IV1_VBUFERR1_1            (0x00020000uL)
+#define INTC_ICDICFR6_IV3_VBUFERR1_0            (0x00040000uL)
+#define INTC_ICDICFR6_IV3_VBUFERR1_1            (0x00080000uL)
+#define INTC_ICDICFR6_IV5_VBUFERR1_0            (0x00100000uL)
+#define INTC_ICDICFR6_IV5_VBUFERR1_1            (0x00200000uL)
+#define INTC_ICDICFR6_IV6_VBUFERR1_0            (0x00400000uL)
+#define INTC_ICDICFR6_IV6_VBUFERR1_1            (0x00800000uL)
+#define INTC_ICDICFR6_S0_WLINE1_0               (0x01000000uL)
+#define INTC_ICDICFR6_S0_WLINE1_1               (0x02000000uL)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_0            (0x04000000uL)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_1            (0x08000000uL)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_0            (0x10000000uL)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_1            (0x20000000uL)
+#define INTC_ICDICFR6_S1_VSYNCERR1_0            (0x40000000uL)
+#define INTC_ICDICFR6_S1_VSYNCERR1_1            (0x80000000uL)
+
+#define INTC_ICDICFR7_S1_VFIELD1_0              (0x00000001uL)
+#define INTC_ICDICFR7_S1_VFIELD1_1              (0x00000002uL)
+#define INTC_ICDICFR7_IV2_VBUFERR1_0            (0x00000004uL)
+#define INTC_ICDICFR7_IV2_VBUFERR1_1            (0x00000008uL)
+#define INTC_ICDICFR7_IV4_VBUFERR1_0            (0x00000010uL)
+#define INTC_ICDICFR7_IV4_VBUFERR1_1            (0x00000020uL)
+#define INTC_ICDICFR7_S1_WLINE1_0               (0x00000040uL)
+#define INTC_ICDICFR7_S1_WLINE1_1               (0x00000080uL)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_0           (0x00000100uL)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_1           (0x00000200uL)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_0           (0x00000400uL)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_1           (0x00000800uL)
+#define INTC_ICDICFR7_OIR_VLINE1_0              (0x00001000uL)
+#define INTC_ICDICFR7_OIR_VLINE1_1              (0x00002000uL)
+#define INTC_ICDICFR7_OIR_VFIELD1_0             (0x00004000uL)
+#define INTC_ICDICFR7_OIR_VFIELD1_1             (0x00008000uL)
+#define INTC_ICDICFR7_IV7_VBUFERR1_0            (0x00010000uL)
+#define INTC_ICDICFR7_IV7_VBUFERR1_1            (0x00020000uL)
+#define INTC_ICDICFR7_IV8_VBUFERR1_0            (0x00040000uL)
+#define INTC_ICDICFR7_IV8_VBUFERR1_1            (0x00080000uL)
+#define INTC_ICDICFR7_IMRDI_0                   (0x00400000uL)
+#define INTC_ICDICFR7_IMRDI_1                   (0x00800000uL)
+#define INTC_ICDICFR7_IMR2I0_0                  (0x01000000uL)
+#define INTC_ICDICFR7_IMR2I0_1                  (0x02000000uL)
+#define INTC_ICDICFR7_IMR2I1_0                  (0x04000000uL)
+#define INTC_ICDICFR7_IMR2I1_1                  (0x08000000uL)
+#define INTC_ICDICFR7_JEDI_0                    (0x10000000uL)
+#define INTC_ICDICFR7_JEDI_1                    (0x20000000uL)
+#define INTC_ICDICFR7_JDTI_0                    (0x40000000uL)
+#define INTC_ICDICFR7_JDTI_1                    (0x80000000uL)
+
+#define INTC_ICDICFR8_CMP0_0                    (0x00000001uL)
+#define INTC_ICDICFR8_CMP0_1                    (0x00000002uL)
+#define INTC_ICDICFR8_CMP1_0                    (0x00000004uL)
+#define INTC_ICDICFR8_CMP1_1                    (0x00000008uL)
+#define INTC_ICDICFR8_INT0_0                    (0x00000010uL)
+#define INTC_ICDICFR8_INT0_1                    (0x00000020uL)
+#define INTC_ICDICFR8_INT1_0                    (0x00000040uL)
+#define INTC_ICDICFR8_INT1_1                    (0x00000080uL)
+#define INTC_ICDICFR8_INT2_0                    (0x00000100uL)
+#define INTC_ICDICFR8_INT2_1                    (0x00000200uL)
+#define INTC_ICDICFR8_INT3_0                    (0x00000400uL)
+#define INTC_ICDICFR8_INT3_1                    (0x00000800uL)
+#define INTC_ICDICFR8_OSTM0TINT_0               (0x00001000uL)
+#define INTC_ICDICFR8_OSTM0TINT_1               (0x00002000uL)
+#define INTC_ICDICFR8_OSTM1TINT_0               (0x00004000uL)
+#define INTC_ICDICFR8_OSTM1TINT_1               (0x00008000uL)
+#define INTC_ICDICFR8_CMI_0                     (0x00010000uL)
+#define INTC_ICDICFR8_CMI_1                     (0x00020000uL)
+#define INTC_ICDICFR8_WTOUT_0                   (0x00040000uL)
+#define INTC_ICDICFR8_WTOUT_1                   (0x00080000uL)
+#define INTC_ICDICFR8_ITI_0                     (0x00100000uL)
+#define INTC_ICDICFR8_ITI_1                     (0x00200000uL)
+#define INTC_ICDICFR8_TGI0A_0                   (0x00400000uL)
+#define INTC_ICDICFR8_TGI0A_1                   (0x00800000uL)
+#define INTC_ICDICFR8_TGI0B_0                   (0x01000000uL)
+#define INTC_ICDICFR8_TGI0B_1                   (0x02000000uL)
+#define INTC_ICDICFR8_TGI0C_0                   (0x04000000uL)
+#define INTC_ICDICFR8_TGI0C_1                   (0x08000000uL)
+#define INTC_ICDICFR8_TGI0D_0                   (0x10000000uL)
+#define INTC_ICDICFR8_TGI0D_1                   (0x20000000uL)
+#define INTC_ICDICFR8_TGI0V_0                   (0x40000000uL)
+#define INTC_ICDICFR8_TGI0V_1                   (0x80000000uL)
+
+#define INTC_ICDICFR9_TGI0E_0                   (0x00000001uL)
+#define INTC_ICDICFR9_TGI0E_1                   (0x00000002uL)
+#define INTC_ICDICFR9_TGI0F_0                   (0x00000004uL)
+#define INTC_ICDICFR9_TGI0F_1                   (0x00000008uL)
+#define INTC_ICDICFR9_TGI1A_0                   (0x00000010uL)
+#define INTC_ICDICFR9_TGI1A_1                   (0x00000020uL)
+#define INTC_ICDICFR9_TGI1B_0                   (0x00000040uL)
+#define INTC_ICDICFR9_TGI1B_1                   (0x00000080uL)
+#define INTC_ICDICFR9_TGI1V_0                   (0x00000100uL)
+#define INTC_ICDICFR9_TGI1V_1                   (0x00000200uL)
+#define INTC_ICDICFR9_TGI1U_0                   (0x00000400uL)
+#define INTC_ICDICFR9_TGI1U_1                   (0x00000800uL)
+#define INTC_ICDICFR9_TGI2A_0                   (0x00001000uL)
+#define INTC_ICDICFR9_TGI2A_1                   (0x00002000uL)
+#define INTC_ICDICFR9_TGI2B_0                   (0x00004000uL)
+#define INTC_ICDICFR9_TGI2B_1                   (0x00008000uL)
+#define INTC_ICDICFR9_TGI2V_0                   (0x00010000uL)
+#define INTC_ICDICFR9_TGI2V_1                   (0x00020000uL)
+#define INTC_ICDICFR9_TGI2U_0                   (0x00040000uL)
+#define INTC_ICDICFR9_TGI2U_1                   (0x00080000uL)
+#define INTC_ICDICFR9_TGI3A_0                   (0x00100000uL)
+#define INTC_ICDICFR9_TGI3A_1                   (0x00200000uL)
+#define INTC_ICDICFR9_TGI3B_0                   (0x00400000uL)
+#define INTC_ICDICFR9_TGI3B_1                   (0x00800000uL)
+#define INTC_ICDICFR9_TGI3C_0                   (0x01000000uL)
+#define INTC_ICDICFR9_TGI3C_1                   (0x02000000uL)
+#define INTC_ICDICFR9_TGI3D_0                   (0x04000000uL)
+#define INTC_ICDICFR9_TGI3D_1                   (0x08000000uL)
+#define INTC_ICDICFR9_TGI3V_0                   (0x10000000uL)
+#define INTC_ICDICFR9_TGI3V_1                   (0x20000000uL)
+#define INTC_ICDICFR9_TGI4A_0                   (0x40000000uL)
+#define INTC_ICDICFR9_TGI4A_1                   (0x80000000uL)
+
+#define INTC_ICDICFR10_TGI4B_0                  (0x00000001uL)
+#define INTC_ICDICFR10_TGI4B_1                  (0x00000002uL)
+#define INTC_ICDICFR10_TGI4C_0                  (0x00000004uL)
+#define INTC_ICDICFR10_TGI4C_1                  (0x00000008uL)
+#define INTC_ICDICFR10_TGI4D_0                  (0x00000010uL)
+#define INTC_ICDICFR10_TGI4D_1                  (0x00000020uL)
+#define INTC_ICDICFR10_TGI4V_0                  (0x00000040uL)
+#define INTC_ICDICFR10_TGI4V_1                  (0x00000080uL)
+#define INTC_ICDICFR10_CMI1_0                   (0x00000100uL)
+#define INTC_ICDICFR10_CMI1_1                   (0x00000200uL)
+#define INTC_ICDICFR10_CMI2_0                   (0x00000400uL)
+#define INTC_ICDICFR10_CMI2_1                   (0x00000800uL)
+#define INTC_ICDICFR10_SGDEI0_0                 (0x00001000uL)
+#define INTC_ICDICFR10_SGDEI0_1                 (0x00002000uL)
+#define INTC_ICDICFR10_SGDEI1_0                 (0x00004000uL)
+#define INTC_ICDICFR10_SGDEI1_1                 (0x00008000uL)
+#define INTC_ICDICFR10_SGDEI2_0                 (0x00010000uL)
+#define INTC_ICDICFR10_SGDEI2_1                 (0x00020000uL)
+#define INTC_ICDICFR10_SGDEI3_0                 (0x00040000uL)
+#define INTC_ICDICFR10_SGDEI3_1                 (0x00080000uL)
+#define INTC_ICDICFR10_ADI_0                    (0x00100000uL)
+#define INTC_ICDICFR10_ADI_1                    (0x00200000uL)
+#define INTC_ICDICFR10_LMTI_0                   (0x00400000uL)
+#define INTC_ICDICFR10_LMTI_1                   (0x00800000uL)
+#define INTC_ICDICFR10_SSII0_0                  (0x01000000uL)
+#define INTC_ICDICFR10_SSII0_1                  (0x02000000uL)
+#define INTC_ICDICFR10_SSIRXI0_0                (0x04000000uL)
+#define INTC_ICDICFR10_SSIRXI0_1                (0x08000000uL)
+#define INTC_ICDICFR10_SSITXI0_0                (0x10000000uL)
+#define INTC_ICDICFR10_SSITXI0_1                (0x20000000uL)
+#define INTC_ICDICFR10_SSII1_0                  (0x40000000uL)
+#define INTC_ICDICFR10_SSII1_1                  (0x80000000uL)
+
+#define INTC_ICDICFR11_SSIRXI1_0                (0x00000001uL)
+#define INTC_ICDICFR11_SSIRXI1_1                (0x00000002uL)
+#define INTC_ICDICFR11_SSITXI1_0                (0x00000004uL)
+#define INTC_ICDICFR11_SSITXI1_1                (0x00000008uL)
+#define INTC_ICDICFR11_SSII2_0                  (0x00000010uL)
+#define INTC_ICDICFR11_SSII2_1                  (0x00000020uL)
+#define INTC_ICDICFR11_SSIRTI2_0                (0x00000040uL)
+#define INTC_ICDICFR11_SSIRTI2_1                (0x00000080uL)
+#define INTC_ICDICFR11_SSII3_0                  (0x00000100uL)
+#define INTC_ICDICFR11_SSII3_1                  (0x00000200uL)
+#define INTC_ICDICFR11_SSIRXI3_0                (0x00000400uL)
+#define INTC_ICDICFR11_SSIRXI3_1                (0x00000800uL)
+#define INTC_ICDICFR11_SSITXI3_0                (0x00001000uL)
+#define INTC_ICDICFR11_SSITXI3_1                (0x00002000uL)
+#define INTC_ICDICFR11_SSII4_0                  (0x00004000uL)
+#define INTC_ICDICFR11_SSII4_1                  (0x00008000uL)
+#define INTC_ICDICFR11_SSIRTI4_0                (0x00010000uL)
+#define INTC_ICDICFR11_SSIRTI4_1                (0x00020000uL)
+#define INTC_ICDICFR11_SSII5_0                  (0x00040000uL)
+#define INTC_ICDICFR11_SSII5_1                  (0x00080000uL)
+#define INTC_ICDICFR11_SSIRXI5_0                (0x00100000uL)
+#define INTC_ICDICFR11_SSIRXI5_1                (0x00200000uL)
+#define INTC_ICDICFR11_SSITXI5_0                (0x00400000uL)
+#define INTC_ICDICFR11_SSITXI5_1                (0x00800000uL)
+#define INTC_ICDICFR11_SPDIFI_0                 (0x01000000uL)
+#define INTC_ICDICFR11_SPDIFI_1                 (0x02000000uL)
+#define INTC_ICDICFR11_INTIICTEI0_0             (0x04000000uL)
+#define INTC_ICDICFR11_INTIICTEI0_1             (0x08000000uL)
+#define INTC_ICDICFR11_INTIICRI0_0              (0x10000000uL)
+#define INTC_ICDICFR11_INTIICRI0_1              (0x20000000uL)
+#define INTC_ICDICFR11_INTIICTI0_0              (0x40000000uL)
+#define INTC_ICDICFR11_INTIICTI0_1              (0x80000000uL)
+
+#define INTC_ICDICFR12_INTIICSPI0_0             (0x00000001uL)
+#define INTC_ICDICFR12_INTIICSPI0_1             (0x00000002uL)
+#define INTC_ICDICFR12_INTIICSTI0_0             (0x00000004uL)
+#define INTC_ICDICFR12_INTIICSTI0_1             (0x00000008uL)
+#define INTC_ICDICFR12_INTIICNAKI0_0            (0x00000010uL)
+#define INTC_ICDICFR12_INTIICNAKI0_1            (0x00000020uL)
+#define INTC_ICDICFR12_INTIICALI0_0             (0x00000040uL)
+#define INTC_ICDICFR12_INTIICALI0_1             (0x00000080uL)
+#define INTC_ICDICFR12_INTIICTMOI0_0            (0x00000100uL)
+#define INTC_ICDICFR12_INTIICTMOI0_1            (0x00000200uL)
+#define INTC_ICDICFR12_INTIICTEI1_0             (0x00000400uL)
+#define INTC_ICDICFR12_INTIICTEI1_1             (0x00000800uL)
+#define INTC_ICDICFR12_INTIICRI1_0              (0x00001000uL)
+#define INTC_ICDICFR12_INTIICRI1_1              (0x00002000uL)
+#define INTC_ICDICFR12_INTIICTI1_0              (0x00004000uL)
+#define INTC_ICDICFR12_INTIICTI1_1              (0x00008000uL)
+#define INTC_ICDICFR12_INTIICSPI1_0             (0x00010000uL)
+#define INTC_ICDICFR12_INTIICSPI1_1             (0x00020000uL)
+#define INTC_ICDICFR12_INTIICSTI1_0             (0x00040000uL)
+#define INTC_ICDICFR12_INTIICSTI1_1             (0x00080000uL)
+#define INTC_ICDICFR12_INTIICNAKI1_0            (0x00100000uL)
+#define INTC_ICDICFR12_INTIICNAKI1_1            (0x00200000uL)
+#define INTC_ICDICFR12_INTIICALI1_0             (0x00400000uL)
+#define INTC_ICDICFR12_INTIICALI1_1             (0x00800000uL)
+#define INTC_ICDICFR12_INTIICTMOI1_0            (0x01000000uL)
+#define INTC_ICDICFR12_INTIICTMOI1_1            (0x02000000uL)
+#define INTC_ICDICFR12_INTIICTEI2_0             (0x04000000uL)
+#define INTC_ICDICFR12_INTIICTEI2_1             (0x08000000uL)
+#define INTC_ICDICFR12_INTIICRI2_0              (0x10000000uL)
+#define INTC_ICDICFR12_INTIICRI2_1              (0x20000000uL)
+#define INTC_ICDICFR12_INTIICTI2_0              (0x40000000uL)
+#define INTC_ICDICFR12_INTIICTI2_1              (0x80000000uL)
+
+#define INTC_ICDICFR13_INTIICSPI2_0             (0x00000001uL)
+#define INTC_ICDICFR13_INTIICSPI2_1             (0x00000002uL)
+#define INTC_ICDICFR13_INTIICSTI2_0             (0x00000004uL)
+#define INTC_ICDICFR13_INTIICSTI2_1             (0x00000008uL)
+#define INTC_ICDICFR13_INTIICNAKI2_0            (0x00000010uL)
+#define INTC_ICDICFR13_INTIICNAKI2_1            (0x00000020uL)
+#define INTC_ICDICFR13_INTIICALI2_0             (0x00000040uL)
+#define INTC_ICDICFR13_INTIICALI2_1             (0x00000080uL)
+#define INTC_ICDICFR13_INTIICTMOI2_0            (0x00000100uL)
+#define INTC_ICDICFR13_INTIICTMOI2_1            (0x00000200uL)
+#define INTC_ICDICFR13_INTIICTEI3_0             (0x00000400uL)
+#define INTC_ICDICFR13_INTIICTEI3_1             (0x00000800uL)
+#define INTC_ICDICFR13_INTIICRI3_0              (0x00001000uL)
+#define INTC_ICDICFR13_INTIICRI3_1              (0x00002000uL)
+#define INTC_ICDICFR13_INTIICTI3_0              (0x00004000uL)
+#define INTC_ICDICFR13_INTIICTI3_1              (0x00008000uL)
+#define INTC_ICDICFR13_INTIICSPI3_0             (0x00010000uL)
+#define INTC_ICDICFR13_INTIICSPI3_1             (0x00020000uL)
+#define INTC_ICDICFR13_INTIICSTI3_0             (0x00040000uL)
+#define INTC_ICDICFR13_INTIICSTI3_1             (0x00080000uL)
+#define INTC_ICDICFR13_INTIICNAKI3_0            (0x00100000uL)
+#define INTC_ICDICFR13_INTIICNAKI3_1            (0x00200000uL)
+#define INTC_ICDICFR13_INTIICALI3_0             (0x00400000uL)
+#define INTC_ICDICFR13_INTIICALI3_1             (0x00800000uL)
+#define INTC_ICDICFR13_INTIICTMOI3_0            (0x01000000uL)
+#define INTC_ICDICFR13_INTIICTMOI3_1            (0x02000000uL)
+#define INTC_ICDICFR13_BRI0_0                   (0x04000000uL)
+#define INTC_ICDICFR13_BRI0_1                   (0x08000000uL)
+#define INTC_ICDICFR13_ERI0_0                   (0x10000000uL)
+#define INTC_ICDICFR13_ERI0_1                   (0x20000000uL)
+#define INTC_ICDICFR13_RXI0_0                   (0x40000000uL)
+#define INTC_ICDICFR13_RXI0_1                   (0x80000000uL)
+
+#define INTC_ICDICFR14_TXI0_0                   (0x00000001uL)
+#define INTC_ICDICFR14_TXI0_1                   (0x00000002uL)
+#define INTC_ICDICFR14_BRI1_0                   (0x00000004uL)
+#define INTC_ICDICFR14_BRI1_1                   (0x00000008uL)
+#define INTC_ICDICFR14_ERI1_0                   (0x00000010uL)
+#define INTC_ICDICFR14_ERI1_1                   (0x00000020uL)
+#define INTC_ICDICFR14_RXI1_0                   (0x00000040uL)
+#define INTC_ICDICFR14_RXI1_1                   (0x00000080uL)
+#define INTC_ICDICFR14_TXI1_0                   (0x00000100uL)
+#define INTC_ICDICFR14_TXI1_1                   (0x00000200uL)
+#define INTC_ICDICFR14_BRI2_0                   (0x00000400uL)
+#define INTC_ICDICFR14_BRI2_1                   (0x00000800uL)
+#define INTC_ICDICFR14_ERI2_0                   (0x00001000uL)
+#define INTC_ICDICFR14_ERI2_1                   (0x00002000uL)
+#define INTC_ICDICFR14_RXI2_0                   (0x00004000uL)
+#define INTC_ICDICFR14_RXI2_1                   (0x00008000uL)
+#define INTC_ICDICFR14_TXI2_0                   (0x00010000uL)
+#define INTC_ICDICFR14_TXI2_1                   (0x00020000uL)
+#define INTC_ICDICFR14_BRI3_0                   (0x00040000uL)
+#define INTC_ICDICFR14_BRI3_1                   (0x00080000uL)
+#define INTC_ICDICFR14_ERI3_0                   (0x00100000uL)
+#define INTC_ICDICFR14_ERI3_1                   (0x00200000uL)
+#define INTC_ICDICFR14_RXI3_0                   (0x00400000uL)
+#define INTC_ICDICFR14_RXI3_1                   (0x00800000uL)
+#define INTC_ICDICFR14_TXI3_0                   (0x01000000uL)
+#define INTC_ICDICFR14_TXI3_1                   (0x02000000uL)
+#define INTC_ICDICFR14_BRI4_0                   (0x04000000uL)
+#define INTC_ICDICFR14_BRI4_1                   (0x08000000uL)
+#define INTC_ICDICFR14_ERI4_0                   (0x10000000uL)
+#define INTC_ICDICFR14_ERI4_1                   (0x20000000uL)
+#define INTC_ICDICFR14_RXI4_0                   (0x40000000uL)
+#define INTC_ICDICFR14_RXI4_1                   (0x80000000uL)
+
+#define INTC_ICDICFR15_TXI4_0                   (0x00000001uL)
+#define INTC_ICDICFR15_TXI4_1                   (0x00000002uL)
+#define INTC_ICDICFR15_BRI5_0                   (0x00000004uL)
+#define INTC_ICDICFR15_BRI5_1                   (0x00000008uL)
+#define INTC_ICDICFR15_ERI5_0                   (0x00000010uL)
+#define INTC_ICDICFR15_ERI5_1                   (0x00000020uL)
+#define INTC_ICDICFR15_RXI5_0                   (0x00000040uL)
+#define INTC_ICDICFR15_RXI5_1                   (0x00000080uL)
+#define INTC_ICDICFR15_TXI5_0                   (0x00000100uL)
+#define INTC_ICDICFR15_TXI5_1                   (0x00000200uL)
+#define INTC_ICDICFR15_BRI6_0                   (0x00000400uL)
+#define INTC_ICDICFR15_BRI6_1                   (0x00000800uL)
+#define INTC_ICDICFR15_ERI6_0                   (0x00001000uL)
+#define INTC_ICDICFR15_ERI6_1                   (0x00002000uL)
+#define INTC_ICDICFR15_RXI6_0                   (0x00004000uL)
+#define INTC_ICDICFR15_RXI6_1                   (0x00008000uL)
+#define INTC_ICDICFR15_TXI6_0                   (0x00010000uL)
+#define INTC_ICDICFR15_TXI6_1                   (0x00020000uL)
+#define INTC_ICDICFR15_BRI7_0                   (0x00040000uL)
+#define INTC_ICDICFR15_BRI7_1                   (0x00080000uL)
+#define INTC_ICDICFR15_ERI7_0                   (0x00100000uL)
+#define INTC_ICDICFR15_ERI7_1                   (0x00200000uL)
+#define INTC_ICDICFR15_RXI7_0                   (0x00400000uL)
+#define INTC_ICDICFR15_RXI7_1                   (0x00800000uL)
+#define INTC_ICDICFR15_TXI7_0                   (0x01000000uL)
+#define INTC_ICDICFR15_TXI7_1                   (0x02000000uL)
+#define INTC_ICDICFR15_INTRCANGERR_0            (0x04000000uL)
+#define INTC_ICDICFR15_INTRCANGERR_1            (0x08000000uL)
+#define INTC_ICDICFR15_INTRCANGRECC_0           (0x10000000uL)
+#define INTC_ICDICFR15_INTRCANGRECC_1           (0x20000000uL)
+#define INTC_ICDICFR15_INTRCAN0REC_0            (0x40000000uL)
+#define INTC_ICDICFR15_INTRCAN0REC_1            (0x80000000uL)
+
+#define INTC_ICDICFR16_INTRCAN0ERR_0            (0x00000001uL)
+#define INTC_ICDICFR16_INTRCAN0ERR_1            (0x00000002uL)
+#define INTC_ICDICFR16_INTRCAN0TRX_0            (0x00000004uL)
+#define INTC_ICDICFR16_INTRCAN0TRX_1            (0x00000008uL)
+#define INTC_ICDICFR16_INTRCAN1REC_0            (0x00000010uL)
+#define INTC_ICDICFR16_INTRCAN1REC_1            (0x00000020uL)
+#define INTC_ICDICFR16_INTRCAN1ERR_0            (0x00000040uL)
+#define INTC_ICDICFR16_INTRCAN1ERR_1            (0x00000080uL)
+#define INTC_ICDICFR16_INTRCAN1TRX_0            (0x00000100uL)
+#define INTC_ICDICFR16_INTRCAN1TRX_1            (0x00000200uL)
+#define INTC_ICDICFR16_INTRCAN2REC_0            (0x00000400uL)
+#define INTC_ICDICFR16_INTRCAN2REC_1            (0x00000800uL)
+#define INTC_ICDICFR16_INTRCAN2ERR_0            (0x00001000uL)
+#define INTC_ICDICFR16_INTRCAN2ERR_1            (0x00002000uL)
+#define INTC_ICDICFR16_INTRCAN2TRX_0            (0x00004000uL)
+#define INTC_ICDICFR16_INTRCAN2TRX_1            (0x00008000uL)
+#define INTC_ICDICFR16_INTRCAN3REC_0            (0x00010000uL)
+#define INTC_ICDICFR16_INTRCAN3REC_1            (0x00020000uL)
+#define INTC_ICDICFR16_INTRCAN3ERR_0            (0x00040000uL)
+#define INTC_ICDICFR16_INTRCAN3ERR_1            (0x00080000uL)
+#define INTC_ICDICFR16_INTRCAN3TRX_0            (0x00100000uL)
+#define INTC_ICDICFR16_INTRCAN3TRX_1            (0x00200000uL)
+#define INTC_ICDICFR16_INTRCAN4REC_0            (0x00400000uL)
+#define INTC_ICDICFR16_INTRCAN4REC_1            (0x00800000uL)
+#define INTC_ICDICFR16_INTRCAN4ERR_0            (0x01000000uL)
+#define INTC_ICDICFR16_INTRCAN4ERR_1            (0x02000000uL)
+#define INTC_ICDICFR16_INTRCAN4TRX_0            (0x04000000uL)
+#define INTC_ICDICFR16_INTRCAN4TRX_1            (0x08000000uL)
+#define INTC_ICDICFR16_SPEI0_0                  (0x10000000uL)
+#define INTC_ICDICFR16_SPEI0_1                  (0x20000000uL)
+#define INTC_ICDICFR16_SPRI0_0                  (0x40000000uL)
+#define INTC_ICDICFR16_SPRI0_1                  (0x80000000uL)
+
+#define INTC_ICDICFR17_SPTI0_0                  (0x00000001uL)
+#define INTC_ICDICFR17_SPTI0_1                  (0x00000002uL)
+#define INTC_ICDICFR17_SPEI1_0                  (0x00000004uL)
+#define INTC_ICDICFR17_SPEI1_1                  (0x00000008uL)
+#define INTC_ICDICFR17_SPRI1_0                  (0x00000010uL)
+#define INTC_ICDICFR17_SPRI1_1                  (0x00000020uL)
+#define INTC_ICDICFR17_SPTI1_0                  (0x00000040uL)
+#define INTC_ICDICFR17_SPTI1_1                  (0x00000080uL)
+#define INTC_ICDICFR17_SPEI2_0                  (0x00000100uL)
+#define INTC_ICDICFR17_SPEI2_1                  (0x00000200uL)
+#define INTC_ICDICFR17_SPRI2_0                  (0x00000400uL)
+#define INTC_ICDICFR17_SPRI2_1                  (0x00000800uL)
+#define INTC_ICDICFR17_SPTI2_0                  (0x00001000uL)
+#define INTC_ICDICFR17_SPTI2_1                  (0x00002000uL)
+#define INTC_ICDICFR17_SPEI3_0                  (0x00004000uL)
+#define INTC_ICDICFR17_SPEI3_1                  (0x00008000uL)
+#define INTC_ICDICFR17_SPRI3_0                  (0x00010000uL)
+#define INTC_ICDICFR17_SPRI3_1                  (0x00020000uL)
+#define INTC_ICDICFR17_SPTI3_0                  (0x00040000uL)
+#define INTC_ICDICFR17_SPTI3_1                  (0x00080000uL)
+#define INTC_ICDICFR17_SPEI4_0                  (0x00100000uL)
+#define INTC_ICDICFR17_SPEI4_1                  (0x00200000uL)
+#define INTC_ICDICFR17_SPRI4_0                  (0x00400000uL)
+#define INTC_ICDICFR17_SPRI4_1                  (0x00800000uL)
+#define INTC_ICDICFR17_SPTI4_0                  (0x01000000uL)
+#define INTC_ICDICFR17_SPTI4_1                  (0x02000000uL)
+#define INTC_ICDICFR17_IEBBTD_0                 (0x04000000uL)
+#define INTC_ICDICFR17_IEBBTD_1                 (0x08000000uL)
+#define INTC_ICDICFR17_IEBBTERR_0               (0x10000000uL)
+#define INTC_ICDICFR17_IEBBTERR_1               (0x20000000uL)
+#define INTC_ICDICFR17_IEBBTSTA_0               (0x40000000uL)
+#define INTC_ICDICFR17_IEBBTSTA_1               (0x80000000uL)
+
+#define INTC_ICDICFR18_IEBBTV_0                 (0x00000001uL)
+#define INTC_ICDICFR18_IEBBTV_1                 (0x00000002uL)
+#define INTC_ICDICFR18_ISY_0                    (0x00000004uL)
+#define INTC_ICDICFR18_ISY_1                    (0x00000008uL)
+#define INTC_ICDICFR18_IERR_0                   (0x00000010uL)
+#define INTC_ICDICFR18_IERR_1                   (0x00000020uL)
+#define INTC_ICDICFR18_ITARG_0                  (0x00000040uL)
+#define INTC_ICDICFR18_ITARG_1                  (0x00000080uL)
+#define INTC_ICDICFR18_ISEC_0                   (0x00000100uL)
+#define INTC_ICDICFR18_ISEC_1                   (0x00000200uL)
+#define INTC_ICDICFR18_IBUF_0                   (0x00000400uL)
+#define INTC_ICDICFR18_IBUF_1                   (0x00000800uL)
+#define INTC_ICDICFR18_IREADY_0                 (0x00001000uL)
+#define INTC_ICDICFR18_IREADY_1                 (0x00002000uL)
+#define INTC_ICDICFR18_FLSTE_0                  (0x00004000uL)
+#define INTC_ICDICFR18_FLSTE_1                  (0x00008000uL)
+#define INTC_ICDICFR18_FLTENDI_0                (0x00010000uL)
+#define INTC_ICDICFR18_FLTENDI_1                (0x00020000uL)
+#define INTC_ICDICFR18_FLTREQ0I_0               (0x00040000uL)
+#define INTC_ICDICFR18_FLTREQ0I_1               (0x00080000uL)
+#define INTC_ICDICFR18_FLTREQ1I_0               (0x00100000uL)
+#define INTC_ICDICFR18_FLTREQ1I_1               (0x00200000uL)
+#define INTC_ICDICFR18_MMC0_0                   (0x00400000uL)
+#define INTC_ICDICFR18_MMC0_1                   (0x00800000uL)
+#define INTC_ICDICFR18_MMC1_0                   (0x01000000uL)
+#define INTC_ICDICFR18_MMC1_1                   (0x02000000uL)
+#define INTC_ICDICFR18_MMC2_0                   (0x04000000uL)
+#define INTC_ICDICFR18_MMC2_1                   (0x08000000uL)
+#define INTC_ICDICFR18_SDHI0_3_0                (0x10000000uL)
+#define INTC_ICDICFR18_SDHI0_3_1                (0x20000000uL)
+#define INTC_ICDICFR18_SDHI0_0_0                (0x40000000uL)
+#define INTC_ICDICFR18_SDHI0_0_1                (0x80000000uL)
+
+#define INTC_ICDICFR19_SDHI0_1_0                (0x00000001uL)
+#define INTC_ICDICFR19_SDHI0_1_1                (0x00000002uL)
+#define INTC_ICDICFR19_SDHI1_3_0                (0x00000004uL)
+#define INTC_ICDICFR19_SDHI1_3_1                (0x00000008uL)
+#define INTC_ICDICFR19_SDHI1_0_0                (0x00000010uL)
+#define INTC_ICDICFR19_SDHI1_0_1                (0x00000020uL)
+#define INTC_ICDICFR19_SDHI1_1_0                (0x00000040uL)
+#define INTC_ICDICFR19_SDHI1_1_1                (0x00000080uL)
+#define INTC_ICDICFR19_ARM_0                    (0x00000100uL)
+#define INTC_ICDICFR19_ARM_1                    (0x00000200uL)
+#define INTC_ICDICFR19_PRD_0                    (0x00000400uL)
+#define INTC_ICDICFR19_PRD_1                    (0x00000800uL)
+#define INTC_ICDICFR19_CUP_0                    (0x00001000uL)
+#define INTC_ICDICFR19_CUP_1                    (0x00002000uL)
+#define INTC_ICDICFR19_SCUAI0_0                 (0x00004000uL)
+#define INTC_ICDICFR19_SCUAI0_1                 (0x00008000uL)
+#define INTC_ICDICFR19_SCUAI1_0                 (0x00010000uL)
+#define INTC_ICDICFR19_SCUAI1_1                 (0x00020000uL)
+#define INTC_ICDICFR19_SCUFDI0_0                (0x00040000uL)
+#define INTC_ICDICFR19_SCUFDI0_1                (0x00080000uL)
+#define INTC_ICDICFR19_SCUFDI1_0                (0x00100000uL)
+#define INTC_ICDICFR19_SCUFDI1_1                (0x00200000uL)
+#define INTC_ICDICFR19_SCUFDI2_0                (0x00400000uL)
+#define INTC_ICDICFR19_SCUFDI2_1                (0x00800000uL)
+#define INTC_ICDICFR19_SCUFDI3_0                (0x01000000uL)
+#define INTC_ICDICFR19_SCUFDI3_1                (0x02000000uL)
+#define INTC_ICDICFR19_SCUFUI0_0                (0x04000000uL)
+#define INTC_ICDICFR19_SCUFUI0_1                (0x08000000uL)
+#define INTC_ICDICFR19_SCUFUI1_0                (0x10000000uL)
+#define INTC_ICDICFR19_SCUFUI1_1                (0x20000000uL)
+#define INTC_ICDICFR19_SCUFUI2_0                (0x40000000uL)
+#define INTC_ICDICFR19_SCUFUI2_1                (0x80000000uL)
+
+#define INTC_ICDICFR20_SCUFUI3_0                (0x00000001uL)
+#define INTC_ICDICFR20_SCUFUI3_1                (0x00000002uL)
+#define INTC_ICDICFR20_SCUDVI0_0                (0x00000004uL)
+#define INTC_ICDICFR20_SCUDVI0_1                (0x00000008uL)
+#define INTC_ICDICFR20_SCUDVI1_0                (0x00000010uL)
+#define INTC_ICDICFR20_SCUDVI1_1                (0x00000020uL)
+#define INTC_ICDICFR20_SCUDVI2_0                (0x00000040uL)
+#define INTC_ICDICFR20_SCUDVI2_1                (0x00000080uL)
+#define INTC_ICDICFR20_SCUDVI3_0                (0x00000100uL)
+#define INTC_ICDICFR20_SCUDVI3_1                (0x00000200uL)
+#define INTC_ICDICFR20_MLB_CINT_0               (0x00000400uL)
+#define INTC_ICDICFR20_MLB_CINT_1               (0x00000800uL)
+#define INTC_ICDICFR20_MLB_SINT_0               (0x00001000uL)
+#define INTC_ICDICFR20_MLB_SINT_1               (0x00002000uL)
+#define INTC_ICDICFR20_DRC0_0                   (0x00004000uL)
+#define INTC_ICDICFR20_DRC0_1                   (0x00008000uL)
+#define INTC_ICDICFR20_DRC1_0                   (0x00010000uL)
+#define INTC_ICDICFR20_DRC1_1                   (0x00020000uL)
+#define INTC_ICDICFR20_LINI0_INT_T_0            (0x00400000uL)
+#define INTC_ICDICFR20_LINI0_INT_T_1            (0x00800000uL)
+#define INTC_ICDICFR20_LINI0_INT_R_0            (0x01000000uL)
+#define INTC_ICDICFR20_LINI0_INT_R_1            (0x02000000uL)
+#define INTC_ICDICFR20_LINI0_INT_S_0            (0x04000000uL)
+#define INTC_ICDICFR20_LINI0_INT_S_1            (0x08000000uL)
+#define INTC_ICDICFR20_LINI0_INT_M_0            (0x10000000uL)
+#define INTC_ICDICFR20_LINI0_INT_M_1            (0x20000000uL)
+#define INTC_ICDICFR20_LINI1_INT_T_0            (0x40000000uL)
+#define INTC_ICDICFR20_LINI1_INT_T_1            (0x80000000uL)
+
+#define INTC_ICDICFR21_LINI1_INT_R_0            (0x00000001uL)
+#define INTC_ICDICFR21_LINI1_INT_R_1            (0x00000002uL)
+#define INTC_ICDICFR21_LINI1_INT_S_0            (0x00000004uL)
+#define INTC_ICDICFR21_LINI1_INT_S_1            (0x00000008uL)
+#define INTC_ICDICFR21_LINI1_INT_M_0            (0x00000010uL)
+#define INTC_ICDICFR21_LINI1_INT_M_1            (0x00000020uL)
+#define INTC_ICDICFR21_ERI0_0                   (0x00400000uL)
+#define INTC_ICDICFR21_ERI0_1                   (0x00800000uL)
+#define INTC_ICDICFR21_RXI0_0                   (0x01000000uL)
+#define INTC_ICDICFR21_RXI0_1                   (0x02000000uL)
+#define INTC_ICDICFR21_TXI0_0                   (0x04000000uL)
+#define INTC_ICDICFR21_TXI0_1                   (0x08000000uL)
+#define INTC_ICDICFR21_TEI0_0                   (0x10000000uL)
+#define INTC_ICDICFR21_TEI0_1                   (0x20000000uL)
+#define INTC_ICDICFR21_ERI1_0                   (0x40000000uL)
+#define INTC_ICDICFR21_ERI1_1                   (0x80000000uL)
+
+#define INTC_ICDICFR22_RXI1_0                   (0x00000001uL)
+#define INTC_ICDICFR22_RXI1_1                   (0x00000002uL)
+#define INTC_ICDICFR22_TXI1_0                   (0x00000004uL)
+#define INTC_ICDICFR22_TXI1_1                   (0x00000008uL)
+#define INTC_ICDICFR22_TEI1_0                   (0x00000010uL)
+#define INTC_ICDICFR22_TEI1_1                   (0x00000020uL)
+#define INTC_ICDICFR22_AVBI_DATA_0              (0x00000040uL)
+#define INTC_ICDICFR22_AVBI_DATA_1              (0x00000080uL)
+#define INTC_ICDICFR22_AVBI_ERROR_0             (0x00000100uL)
+#define INTC_ICDICFR22_AVBI_ERROR_1             (0x00000200uL)
+#define INTC_ICDICFR22_AVBI_MANAGE_0            (0x00000400uL)
+#define INTC_ICDICFR22_AVBI_MANAGE_1            (0x00000800uL)
+#define INTC_ICDICFR22_AVBI_MAC_0               (0x00001000uL)
+#define INTC_ICDICFR22_AVBI_MAC_1               (0x00002000uL)
+#define INTC_ICDICFR22_ETHERI_0                 (0x00004000uL)
+#define INTC_ICDICFR22_ETHERI_1                 (0x00008000uL)
+#define INTC_ICDICFR22_CEUI_0                   (0x01000000uL)
+#define INTC_ICDICFR22_CEUI_1                   (0x02000000uL)
+
+#define INTC_ICDICFR23_H2XMLB_ERRINT_0          (0x04000000uL)
+#define INTC_ICDICFR23_H2XMLB_ERRINT_1          (0x08000000uL)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_0          (0x10000000uL)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_1          (0x20000000uL)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_0        (0x40000000uL)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_1        (0x80000000uL)
+
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_0        (0x00000001uL)
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_1        (0x00000002uL)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_0       (0x00000004uL)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_1       (0x00000008uL)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_0        (0x00000010uL)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_1        (0x00000020uL)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_0       (0x00000040uL)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_1       (0x00000080uL)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_0         (0x00000100uL)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_1         (0x00000200uL)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_0          (0x00000400uL)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_1          (0x00000800uL)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_0         (0x00001000uL)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_1         (0x00002000uL)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_0         (0x00004000uL)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_1         (0x00008000uL)
+#define INTC_ICDICFR24_PRRI_0                   (0x00010000uL)
+#define INTC_ICDICFR24_PRRI_1                   (0x00020000uL)
+#define INTC_ICDICFR24_IFEI0_0                  (0x00040000uL)
+#define INTC_ICDICFR24_IFEI0_1                  (0x00080000uL)
+#define INTC_ICDICFR24_OFFI0_0                  (0x00100000uL)
+#define INTC_ICDICFR24_OFFI0_1                  (0x00200000uL)
+#define INTC_ICDICFR24_PFVEI0_0                 (0x00400000uL)
+#define INTC_ICDICFR24_PFVEI0_1                 (0x00800000uL)
+#define INTC_ICDICFR24_IFEI1_0                  (0x01000000uL)
+#define INTC_ICDICFR24_IFEI1_1                  (0x02000000uL)
+#define INTC_ICDICFR24_OFFI1_0                  (0x04000000uL)
+#define INTC_ICDICFR24_OFFI1_1                  (0x08000000uL)
+#define INTC_ICDICFR24_PFVEI1_0                 (0x10000000uL)
+#define INTC_ICDICFR24_PFVEI1_1                 (0x20000000uL)
+
+#define INTC_ICDICFR26_TINT0_0                  (0x00000001uL)
+#define INTC_ICDICFR26_TINT0_1                  (0x00000002uL)
+#define INTC_ICDICFR26_TINT1_0                  (0x00000004uL)
+#define INTC_ICDICFR26_TINT1_1                  (0x00000008uL)
+#define INTC_ICDICFR26_TINT2_0                  (0x00000010uL)
+#define INTC_ICDICFR26_TINT2_1                  (0x00000020uL)
+#define INTC_ICDICFR26_TINT3_0                  (0x00000040uL)
+#define INTC_ICDICFR26_TINT3_1                  (0x00000080uL)
+#define INTC_ICDICFR26_TINT4_0                  (0x00000100uL)
+#define INTC_ICDICFR26_TINT4_1                  (0x00000200uL)
+#define INTC_ICDICFR26_TINT5_0                  (0x00000400uL)
+#define INTC_ICDICFR26_TINT5_1                  (0x00000800uL)
+#define INTC_ICDICFR26_TINT6_0                  (0x00001000uL)
+#define INTC_ICDICFR26_TINT6_1                  (0x00002000uL)
+#define INTC_ICDICFR26_TINT7_0                  (0x00004000uL)
+#define INTC_ICDICFR26_TINT7_1                  (0x00008000uL)
+#define INTC_ICDICFR26_TINT8_0                  (0x00010000uL)
+#define INTC_ICDICFR26_TINT8_1                  (0x00020000uL)
+#define INTC_ICDICFR26_TINT9_0                  (0x00040000uL)
+#define INTC_ICDICFR26_TINT9_1                  (0x00080000uL)
+#define INTC_ICDICFR26_TINT10_0                 (0x00100000uL)
+#define INTC_ICDICFR26_TINT10_1                 (0x00200000uL)
+#define INTC_ICDICFR26_TINT11_0                 (0x00400000uL)
+#define INTC_ICDICFR26_TINT11_1                 (0x00800000uL)
+#define INTC_ICDICFR26_TINT12_0                 (0x01000000uL)
+#define INTC_ICDICFR26_TINT12_1                 (0x02000000uL)
+#define INTC_ICDICFR26_TINT13_0                 (0x04000000uL)
+#define INTC_ICDICFR26_TINT13_1                 (0x08000000uL)
+#define INTC_ICDICFR26_TINT14_0                 (0x10000000uL)
+#define INTC_ICDICFR26_TINT14_1                 (0x20000000uL)
+#define INTC_ICDICFR26_TINT15_0                 (0x40000000uL)
+#define INTC_ICDICFR26_TINT15_1                 (0x80000000uL)
+
+#define INTC_ICDICFR27_TINT16_0                 (0x00000001uL)
+#define INTC_ICDICFR27_TINT16_1                 (0x00000002uL)
+#define INTC_ICDICFR27_TINT17_0                 (0x00000004uL)
+#define INTC_ICDICFR27_TINT17_1                 (0x00000008uL)
+#define INTC_ICDICFR27_TINT18_0                 (0x00000010uL)
+#define INTC_ICDICFR27_TINT18_1                 (0x00000020uL)
+#define INTC_ICDICFR27_TINT19_0                 (0x00000040uL)
+#define INTC_ICDICFR27_TINT19_1                 (0x00000080uL)
+#define INTC_ICDICFR27_TINT20_0                 (0x00000100uL)
+#define INTC_ICDICFR27_TINT20_1                 (0x00000200uL)
+#define INTC_ICDICFR27_TINT21_0                 (0x00000400uL)
+#define INTC_ICDICFR27_TINT21_1                 (0x00000800uL)
+#define INTC_ICDICFR27_TINT22_0                 (0x00001000uL)
+#define INTC_ICDICFR27_TINT22_1                 (0x00002000uL)
+#define INTC_ICDICFR27_TINT23_0                 (0x00004000uL)
+#define INTC_ICDICFR27_TINT23_1                 (0x00008000uL)
+#define INTC_ICDICFR27_TINT24_0                 (0x00010000uL)
+#define INTC_ICDICFR27_TINT24_1                 (0x00020000uL)
+#define INTC_ICDICFR27_TINT25_0                 (0x00040000uL)
+#define INTC_ICDICFR27_TINT25_1                 (0x00080000uL)
+#define INTC_ICDICFR27_TINT26_0                 (0x00100000uL)
+#define INTC_ICDICFR27_TINT26_1                 (0x00200000uL)
+#define INTC_ICDICFR27_TINT27_0                 (0x00400000uL)
+#define INTC_ICDICFR27_TINT27_1                 (0x00800000uL)
+#define INTC_ICDICFR27_TINT28_0                 (0x01000000uL)
+#define INTC_ICDICFR27_TINT28_1                 (0x02000000uL)
+#define INTC_ICDICFR27_TINT29_0                 (0x04000000uL)
+#define INTC_ICDICFR27_TINT29_1                 (0x08000000uL)
+#define INTC_ICDICFR27_TINT30_0                 (0x10000000uL)
+#define INTC_ICDICFR27_TINT30_1                 (0x20000000uL)
+#define INTC_ICDICFR27_TINT31_0                 (0x40000000uL)
+#define INTC_ICDICFR27_TINT31_1                 (0x80000000uL)
+
+#define INTC_ICDICFR28_TINT32_0                 (0x00000001uL)
+#define INTC_ICDICFR28_TINT32_1                 (0x00000002uL)
+#define INTC_ICDICFR28_TINT33_0                 (0x00000004uL)
+#define INTC_ICDICFR28_TINT33_1                 (0x00000008uL)
+#define INTC_ICDICFR28_TINT34_0                 (0x00000010uL)
+#define INTC_ICDICFR28_TINT34_1                 (0x00000020uL)
+#define INTC_ICDICFR28_TINT35_0                 (0x00000040uL)
+#define INTC_ICDICFR28_TINT35_1                 (0x00000080uL)
+#define INTC_ICDICFR28_TINT36_0                 (0x00000100uL)
+#define INTC_ICDICFR28_TINT36_1                 (0x00000200uL)
+#define INTC_ICDICFR28_TINT37_0                 (0x00000400uL)
+#define INTC_ICDICFR28_TINT37_1                 (0x00000800uL)
+#define INTC_ICDICFR28_TINT38_0                 (0x00001000uL)
+#define INTC_ICDICFR28_TINT38_1                 (0x00002000uL)
+#define INTC_ICDICFR28_TINT39_0                 (0x00004000uL)
+#define INTC_ICDICFR28_TINT39_1                 (0x00008000uL)
+#define INTC_ICDICFR28_TINT40_0                 (0x00010000uL)
+#define INTC_ICDICFR28_TINT40_1                 (0x00020000uL)
+#define INTC_ICDICFR28_TINT41_0                 (0x00040000uL)
+#define INTC_ICDICFR28_TINT41_1                 (0x00080000uL)
+#define INTC_ICDICFR28_TINT42_0                 (0x00100000uL)
+#define INTC_ICDICFR28_TINT42_1                 (0x00200000uL)
+#define INTC_ICDICFR28_TINT43_0                 (0x00400000uL)
+#define INTC_ICDICFR28_TINT43_1                 (0x00800000uL)
+#define INTC_ICDICFR28_TINT44_0                 (0x01000000uL)
+#define INTC_ICDICFR28_TINT44_1                 (0x02000000uL)
+#define INTC_ICDICFR28_TINT45_0                 (0x04000000uL)
+#define INTC_ICDICFR28_TINT45_1                 (0x08000000uL)
+#define INTC_ICDICFR28_TINT46_0                 (0x10000000uL)
+#define INTC_ICDICFR28_TINT46_1                 (0x20000000uL)
+#define INTC_ICDICFR28_TINT47_0                 (0x40000000uL)
+#define INTC_ICDICFR28_TINT47_1                 (0x80000000uL)
+
+#define INTC_ICDICFR29_TINT48_0                 (0x00000001uL)
+#define INTC_ICDICFR29_TINT48_1                 (0x00000002uL)
+#define INTC_ICDICFR29_TINT49_0                 (0x00000004uL)
+#define INTC_ICDICFR29_TINT49_1                 (0x00000008uL)
+#define INTC_ICDICFR29_TINT50_0                 (0x00000010uL)
+#define INTC_ICDICFR29_TINT50_1                 (0x00000020uL)
+#define INTC_ICDICFR29_TINT51_0                 (0x00000040uL)
+#define INTC_ICDICFR29_TINT51_1                 (0x00000080uL)
+#define INTC_ICDICFR29_TINT52_0                 (0x00000100uL)
+#define INTC_ICDICFR29_TINT52_1                 (0x00000200uL)
+#define INTC_ICDICFR29_TINT53_0                 (0x00000400uL)
+#define INTC_ICDICFR29_TINT53_1                 (0x00000800uL)
+#define INTC_ICDICFR29_TINT54_0                 (0x00001000uL)
+#define INTC_ICDICFR29_TINT54_1                 (0x00002000uL)
+#define INTC_ICDICFR29_TINT55_0                 (0x00004000uL)
+#define INTC_ICDICFR29_TINT55_1                 (0x00008000uL)
+#define INTC_ICDICFR29_TINT56_0                 (0x00010000uL)
+#define INTC_ICDICFR29_TINT56_1                 (0x00020000uL)
+#define INTC_ICDICFR29_TINT57_0                 (0x00040000uL)
+#define INTC_ICDICFR29_TINT57_1                 (0x00080000uL)
+#define INTC_ICDICFR29_TINT58_0                 (0x00100000uL)
+#define INTC_ICDICFR29_TINT58_1                 (0x00200000uL)
+#define INTC_ICDICFR29_TINT59_0                 (0x00400000uL)
+#define INTC_ICDICFR29_TINT59_1                 (0x00800000uL)
+#define INTC_ICDICFR29_TINT60_0                 (0x01000000uL)
+#define INTC_ICDICFR29_TINT60_1                 (0x02000000uL)
+#define INTC_ICDICFR29_TINT61_0                 (0x04000000uL)
+#define INTC_ICDICFR29_TINT61_1                 (0x08000000uL)
+#define INTC_ICDICFR29_TINT62_0                 (0x10000000uL)
+#define INTC_ICDICFR29_TINT62_1                 (0x20000000uL)
+#define INTC_ICDICFR29_TINT63_0                 (0x40000000uL)
+#define INTC_ICDICFR29_TINT63_1                 (0x80000000uL)
+
+#define INTC_ICDICFR30_TINT64_0                 (0x00000001uL)
+#define INTC_ICDICFR30_TINT64_1                 (0x00000002uL)
+#define INTC_ICDICFR30_TINT65_0                 (0x00000004uL)
+#define INTC_ICDICFR30_TINT65_1                 (0x00000008uL)
+#define INTC_ICDICFR30_TINT66_0                 (0x00000010uL)
+#define INTC_ICDICFR30_TINT66_1                 (0x00000020uL)
+#define INTC_ICDICFR30_TINT67_0                 (0x00000040uL)
+#define INTC_ICDICFR30_TINT67_1                 (0x00000080uL)
+#define INTC_ICDICFR30_TINT68_0                 (0x00000100uL)
+#define INTC_ICDICFR30_TINT68_1                 (0x00000200uL)
+#define INTC_ICDICFR30_TINT69_0                 (0x00000400uL)
+#define INTC_ICDICFR30_TINT69_1                 (0x00000800uL)
+#define INTC_ICDICFR30_TINT70_0                 (0x00001000uL)
+#define INTC_ICDICFR30_TINT70_1                 (0x00002000uL)
+#define INTC_ICDICFR30_TINT71_0                 (0x00004000uL)
+#define INTC_ICDICFR30_TINT71_1                 (0x00008000uL)
+#define INTC_ICDICFR30_TINT72_0                 (0x00010000uL)
+#define INTC_ICDICFR30_TINT72_1                 (0x00020000uL)
+#define INTC_ICDICFR30_TINT73_0                 (0x00040000uL)
+#define INTC_ICDICFR30_TINT73_1                 (0x00080000uL)
+#define INTC_ICDICFR30_TINT74_0                 (0x00100000uL)
+#define INTC_ICDICFR30_TINT74_1                 (0x00200000uL)
+#define INTC_ICDICFR30_TINT75_0                 (0x00400000uL)
+#define INTC_ICDICFR30_TINT75_1                 (0x00800000uL)
+#define INTC_ICDICFR30_TINT76_0                 (0x01000000uL)
+#define INTC_ICDICFR30_TINT76_1                 (0x02000000uL)
+#define INTC_ICDICFR30_TINT77_0                 (0x04000000uL)
+#define INTC_ICDICFR30_TINT77_1                 (0x08000000uL)
+#define INTC_ICDICFR30_TINT78_0                 (0x10000000uL)
+#define INTC_ICDICFR30_TINT78_1                 (0x20000000uL)
+#define INTC_ICDICFR30_TINT79_0                 (0x40000000uL)
+#define INTC_ICDICFR30_TINT79_1                 (0x80000000uL)
+
+#define INTC_ICDICFR31_TINT80_0                 (0x00000001uL)
+#define INTC_ICDICFR31_TINT80_1                 (0x00000002uL)
+#define INTC_ICDICFR31_TINT81_0                 (0x00000004uL)
+#define INTC_ICDICFR31_TINT81_1                 (0x00000008uL)
+#define INTC_ICDICFR31_TINT82_0                 (0x00000010uL)
+#define INTC_ICDICFR31_TINT82_1                 (0x00000020uL)
+#define INTC_ICDICFR31_TINT83_0                 (0x00000040uL)
+#define INTC_ICDICFR31_TINT83_1                 (0x00000080uL)
+#define INTC_ICDICFR31_TINT84_0                 (0x00000100uL)
+#define INTC_ICDICFR31_TINT84_1                 (0x00000200uL)
+#define INTC_ICDICFR31_TINT85_0                 (0x00000400uL)
+#define INTC_ICDICFR31_TINT85_1                 (0x00000800uL)
+#define INTC_ICDICFR31_TINT86_0                 (0x00001000uL)
+#define INTC_ICDICFR31_TINT86_1                 (0x00002000uL)
+#define INTC_ICDICFR31_TINT87_0                 (0x00004000uL)
+#define INTC_ICDICFR31_TINT87_1                 (0x00008000uL)
+#define INTC_ICDICFR31_TINT88_0                 (0x00010000uL)
+#define INTC_ICDICFR31_TINT88_1                 (0x00020000uL)
+#define INTC_ICDICFR31_TINT89_0                 (0x00040000uL)
+#define INTC_ICDICFR31_TINT89_1                 (0x00080000uL)
+#define INTC_ICDICFR31_TINT90_0                 (0x00100000uL)
+#define INTC_ICDICFR31_TINT90_1                 (0x00200000uL)
+#define INTC_ICDICFR31_TINT91_0                 (0x00400000uL)
+#define INTC_ICDICFR31_TINT91_1                 (0x00800000uL)
+#define INTC_ICDICFR31_TINT92_0                 (0x01000000uL)
+#define INTC_ICDICFR31_TINT92_1                 (0x02000000uL)
+#define INTC_ICDICFR31_TINT93_0                 (0x04000000uL)
+#define INTC_ICDICFR31_TINT93_1                 (0x08000000uL)
+#define INTC_ICDICFR31_TINT94_0                 (0x10000000uL)
+#define INTC_ICDICFR31_TINT94_1                 (0x20000000uL)
+#define INTC_ICDICFR31_TINT95_0                 (0x40000000uL)
+#define INTC_ICDICFR31_TINT95_1                 (0x80000000uL)
+
+#define INTC_ICDICFR32_TINT96_0                 (0x00000001uL)
+#define INTC_ICDICFR32_TINT96_1                 (0x00000002uL)
+#define INTC_ICDICFR32_TINT97_0                 (0x00000004uL)
+#define INTC_ICDICFR32_TINT97_1                 (0x00000008uL)
+#define INTC_ICDICFR32_TINT98_0                 (0x00000010uL)
+#define INTC_ICDICFR32_TINT98_1                 (0x00000020uL)
+#define INTC_ICDICFR32_TINT99_0                 (0x00000040uL)
+#define INTC_ICDICFR32_TINT99_1                 (0x00000080uL)
+#define INTC_ICDICFR32_TINT100_0                (0x00000100uL)
+#define INTC_ICDICFR32_TINT100_1                (0x00000200uL)
+#define INTC_ICDICFR32_TINT101_0                (0x00000400uL)
+#define INTC_ICDICFR32_TINT101_1                (0x00000800uL)
+#define INTC_ICDICFR32_TINT102_0                (0x00001000uL)
+#define INTC_ICDICFR32_TINT102_1                (0x00002000uL)
+#define INTC_ICDICFR32_TINT103_0                (0x00004000uL)
+#define INTC_ICDICFR32_TINT103_1                (0x00008000uL)
+#define INTC_ICDICFR32_TINT104_0                (0x00010000uL)
+#define INTC_ICDICFR32_TINT104_1                (0x00020000uL)
+#define INTC_ICDICFR32_TINT105_0                (0x00040000uL)
+#define INTC_ICDICFR32_TINT105_1                (0x00080000uL)
+#define INTC_ICDICFR32_TINT106_0                (0x00100000uL)
+#define INTC_ICDICFR32_TINT106_1                (0x00200000uL)
+#define INTC_ICDICFR32_TINT107_0                (0x00400000uL)
+#define INTC_ICDICFR32_TINT107_1                (0x00800000uL)
+#define INTC_ICDICFR32_TINT108_0                (0x01000000uL)
+#define INTC_ICDICFR32_TINT108_1                (0x02000000uL)
+#define INTC_ICDICFR32_TINT109_0                (0x04000000uL)
+#define INTC_ICDICFR32_TINT109_1                (0x08000000uL)
+#define INTC_ICDICFR32_TINT110_0                (0x10000000uL)
+#define INTC_ICDICFR32_TINT110_1                (0x20000000uL)
+#define INTC_ICDICFR32_TINT111_0                (0x40000000uL)
+#define INTC_ICDICFR32_TINT111_1                (0x80000000uL)
+
+#define INTC_ICDICFR33_TINT112_0                (0x00000001uL)
+#define INTC_ICDICFR33_TINT112_1                (0x00000002uL)
+#define INTC_ICDICFR33_TINT113_0                (0x00000004uL)
+#define INTC_ICDICFR33_TINT113_1                (0x00000008uL)
+#define INTC_ICDICFR33_TINT114_0                (0x00000010uL)
+#define INTC_ICDICFR33_TINT114_1                (0x00000020uL)
+#define INTC_ICDICFR33_TINT115_0                (0x00000040uL)
+#define INTC_ICDICFR33_TINT115_1                (0x00000080uL)
+#define INTC_ICDICFR33_TINT116_0                (0x00000100uL)
+#define INTC_ICDICFR33_TINT116_1                (0x00000200uL)
+#define INTC_ICDICFR33_TINT117_0                (0x00000400uL)
+#define INTC_ICDICFR33_TINT117_1                (0x00000800uL)
+#define INTC_ICDICFR33_TINT118_0                (0x00001000uL)
+#define INTC_ICDICFR33_TINT118_1                (0x00002000uL)
+#define INTC_ICDICFR33_TINT119_0                (0x00004000uL)
+#define INTC_ICDICFR33_TINT119_1                (0x00008000uL)
+#define INTC_ICDICFR33_TINT120_0                (0x00010000uL)
+#define INTC_ICDICFR33_TINT120_1                (0x00020000uL)
+#define INTC_ICDICFR33_TINT121_0                (0x00040000uL)
+#define INTC_ICDICFR33_TINT121_1                (0x00080000uL)
+#define INTC_ICDICFR33_TINT122_0                (0x00100000uL)
+#define INTC_ICDICFR33_TINT122_1                (0x00200000uL)
+#define INTC_ICDICFR33_TINT123_0                (0x00400000uL)
+#define INTC_ICDICFR33_TINT123_1                (0x00800000uL)
+#define INTC_ICDICFR33_TINT124_0                (0x01000000uL)
+#define INTC_ICDICFR33_TINT124_1                (0x02000000uL)
+#define INTC_ICDICFR33_TINT125_0                (0x04000000uL)
+#define INTC_ICDICFR33_TINT125_1                (0x08000000uL)
+#define INTC_ICDICFR33_TINT126_0                (0x10000000uL)
+#define INTC_ICDICFR33_TINT126_1                (0x20000000uL)
+#define INTC_ICDICFR33_TINT127_0                (0x40000000uL)
+#define INTC_ICDICFR33_TINT127_1                (0x80000000uL)
+
+#define INTC_ICDICFR34_TINT128_0                (0x00000001uL)
+#define INTC_ICDICFR34_TINT128_1                (0x00000002uL)
+#define INTC_ICDICFR34_TINT129_0                (0x00000004uL)
+#define INTC_ICDICFR34_TINT129_1                (0x00000008uL)
+#define INTC_ICDICFR34_TINT130_0                (0x00000010uL)
+#define INTC_ICDICFR34_TINT130_1                (0x00000020uL)
+#define INTC_ICDICFR34_TINT131_0                (0x00000040uL)
+#define INTC_ICDICFR34_TINT131_1                (0x00000080uL)
+#define INTC_ICDICFR34_TINT132_0                (0x00000100uL)
+#define INTC_ICDICFR34_TINT132_1                (0x00000200uL)
+#define INTC_ICDICFR34_TINT133_0                (0x00000400uL)
+#define INTC_ICDICFR34_TINT133_1                (0x00000800uL)
+#define INTC_ICDICFR34_TINT134_0                (0x00001000uL)
+#define INTC_ICDICFR34_TINT134_1                (0x00002000uL)
+#define INTC_ICDICFR34_TINT135_0                (0x00004000uL)
+#define INTC_ICDICFR34_TINT135_1                (0x00008000uL)
+#define INTC_ICDICFR34_TINT136_0                (0x00010000uL)
+#define INTC_ICDICFR34_TINT136_1                (0x00020000uL)
+#define INTC_ICDICFR34_TINT137_0                (0x00040000uL)
+#define INTC_ICDICFR34_TINT137_1                (0x00080000uL)
+#define INTC_ICDICFR34_TINT138_0                (0x00100000uL)
+#define INTC_ICDICFR34_TINT138_1                (0x00200000uL)
+#define INTC_ICDICFR34_TINT139_0                (0x00400000uL)
+#define INTC_ICDICFR34_TINT139_1                (0x00800000uL)
+#define INTC_ICDICFR34_TINT140_0                (0x01000000uL)
+#define INTC_ICDICFR34_TINT140_1                (0x02000000uL)
+#define INTC_ICDICFR34_TINT141_0                (0x04000000uL)
+#define INTC_ICDICFR34_TINT141_1                (0x08000000uL)
+#define INTC_ICDICFR34_TINT142_0                (0x10000000uL)
+#define INTC_ICDICFR34_TINT142_1                (0x20000000uL)
+#define INTC_ICDICFR34_TINT143_0                (0x40000000uL)
+#define INTC_ICDICFR34_TINT143_1                (0x80000000uL)
+
+#define INTC_ICDICFR35_TINT144_0                (0x00000001uL)
+#define INTC_ICDICFR35_TINT144_1                (0x00000002uL)
+#define INTC_ICDICFR35_TINT145_0                (0x00000004uL)
+#define INTC_ICDICFR35_TINT145_1                (0x00000008uL)
+#define INTC_ICDICFR35_TINT146_0                (0x00000010uL)
+#define INTC_ICDICFR35_TINT146_1                (0x00000020uL)
+#define INTC_ICDICFR35_TINT147_0                (0x00000040uL)
+#define INTC_ICDICFR35_TINT147_1                (0x00000080uL)
+#define INTC_ICDICFR35_TINT148_0                (0x00000100uL)
+#define INTC_ICDICFR35_TINT148_1                (0x00000200uL)
+#define INTC_ICDICFR35_TINT149_0                (0x00000400uL)
+#define INTC_ICDICFR35_TINT149_1                (0x00000800uL)
+#define INTC_ICDICFR35_TINT150_0                (0x00001000uL)
+#define INTC_ICDICFR35_TINT150_1                (0x00002000uL)
+#define INTC_ICDICFR35_TINT151_0                (0x00004000uL)
+#define INTC_ICDICFR35_TINT151_1                (0x00008000uL)
+#define INTC_ICDICFR35_TINT152_0                (0x00010000uL)
+#define INTC_ICDICFR35_TINT152_1                (0x00020000uL)
+#define INTC_ICDICFR35_TINT153_0                (0x00040000uL)
+#define INTC_ICDICFR35_TINT153_1                (0x00080000uL)
+#define INTC_ICDICFR35_TINT154_0                (0x00100000uL)
+#define INTC_ICDICFR35_TINT154_1                (0x00200000uL)
+#define INTC_ICDICFR35_TINT155_0                (0x00400000uL)
+#define INTC_ICDICFR35_TINT155_1                (0x00800000uL)
+#define INTC_ICDICFR35_TINT156_0                (0x01000000uL)
+#define INTC_ICDICFR35_TINT156_1                (0x02000000uL)
+#define INTC_ICDICFR35_TINT157_0                (0x04000000uL)
+#define INTC_ICDICFR35_TINT157_1                (0x08000000uL)
+#define INTC_ICDICFR35_TINT158_0                (0x10000000uL)
+#define INTC_ICDICFR35_TINT158_1                (0x20000000uL)
+#define INTC_ICDICFR35_TINT159_0                (0x40000000uL)
+#define INTC_ICDICFR35_TINT159_1                (0x80000000uL)
+
+#define INTC_ICDICFR36_TINT160_0                (0x00000001uL)
+#define INTC_ICDICFR36_TINT160_1                (0x00000002uL)
+#define INTC_ICDICFR36_TINT161_0                (0x00000004uL)
+#define INTC_ICDICFR36_TINT161_1                (0x00000008uL)
+#define INTC_ICDICFR36_TINT162_0                (0x00000010uL)
+#define INTC_ICDICFR36_TINT162_1                (0x00000020uL)
+#define INTC_ICDICFR36_TINT163_0                (0x00000040uL)
+#define INTC_ICDICFR36_TINT163_1                (0x00000080uL)
+#define INTC_ICDICFR36_TINT164_0                (0x00000100uL)
+#define INTC_ICDICFR36_TINT164_1                (0x00000200uL)
+#define INTC_ICDICFR36_TINT165_0                (0x00000400uL)
+#define INTC_ICDICFR36_TINT165_1                (0x00000800uL)
+#define INTC_ICDICFR36_TINT166_0                (0x00001000uL)
+#define INTC_ICDICFR36_TINT166_1                (0x00002000uL)
+#define INTC_ICDICFR36_TINT167_0                (0x00004000uL)
+#define INTC_ICDICFR36_TINT167_1                (0x00008000uL)
+#define INTC_ICDICFR36_TINT168_0                (0x00010000uL)
+#define INTC_ICDICFR36_TINT168_1                (0x00020000uL)
+#define INTC_ICDICFR36_TINT169_0                (0x00040000uL)
+#define INTC_ICDICFR36_TINT169_1                (0x00080000uL)
+#define INTC_ICDICFR36_TINT170_0                (0x00100000uL)
+#define INTC_ICDICFR36_TINT170_1                (0x00200000uL)
+
+#define INTC_ICDSGIR_SGIINTID                   (0x0000000FuL)
+#define INTC_ICDSGIR_SATT                       (0x00008000uL)
+#define INTC_ICDSGIR_CPUTargetList              (0x00FF0000uL)
+#define INTC_ICDSGIR_TargetListFilter           (0x03000000uL)
+
+#define INTC_ICCICR_EnableS                     (0x00000001uL)
+#define INTC_ICCICR_EnableNS                    (0x00000002uL)
+#define INTC_ICCICR_AckCtl                      (0x00000004uL)
+#define INTC_ICCICR_FIQEn                       (0x00000008uL)
+#define INTC_ICCICR_SBPR                        (0x00000010uL)
+
+#define INTC_ICCPMR_Priority                    (0x000000FFuL)
+
+#define INTC_ICCBPR_Binarypoint                 (0x00000007uL)
+
+#define INTC_ICCIAR_ACKINTID                    (0x000003FFuL)
+#define INTC_ICCIAR_CPUID                       (0x00001C00uL)
+
+#define INTC_ICCEOIR_EOIINTID                   (0x000003FFuL)
+#define INTC_ICCEOIR_CPUID                      (0x00001C00uL)
+
+#define INTC_ICCRPR_Priority                    (0x000000FFuL)
+
+#define INTC_ICCHPIR_PENDINTID                  (0x000003FFuL)
+#define INTC_ICCHPIR_CPUID                      (0x00001C00uL)
+
+#define INTC_ICCABPR_Binarypoint                (0x00000007uL)
+
+#define INTC_ICCIIDR_Implementer                (0x00000FFFuL)
+#define INTC_ICCIIDR_Revision                   (0x0000F000uL)
+#define INTC_ICCIIDR_Architecture_version       (0x000F0000uL)
+#define INTC_ICCIIDR_ProductID                  (0xFFF00000uL)
+
+#define INTC_ICR0_NMIF                          (0x0002u)
+#define INTC_ICR0_NMIE                          (0x0100u)
+#define INTC_ICR0_NMIL                          (0x8000u)
+
+#define INTC_ICR1_IRQ00S                        (0x0001u)
+#define INTC_ICR1_IRQ01S                        (0x0002u)
+#define INTC_ICR1_IRQ10S                        (0x0004u)
+#define INTC_ICR1_IRQ11S                        (0x0008u)
+#define INTC_ICR1_IRQ20S                        (0x0010u)
+#define INTC_ICR1_IRQ21S                        (0x0020u)
+#define INTC_ICR1_IRQ30S                        (0x0040u)
+#define INTC_ICR1_IRQ31S                        (0x0080u)
+#define INTC_ICR1_IRQ40S                        (0x0100u)
+#define INTC_ICR1_IRQ41S                        (0x0200u)
+#define INTC_ICR1_IRQ50S                        (0x0400u)
+#define INTC_ICR1_IRQ51S                        (0x0800u)
+#define INTC_ICR1_IRQ60S                        (0x1000u)
+#define INTC_ICR1_IRQ61S                        (0x2000u)
+#define INTC_ICR1_IRQ70S                        (0x4000u)
+#define INTC_ICR1_IRQ71S                        (0x8000u)
+
+#define INTC_IRQRR_IRQ0F                        (0x0001u)
+#define INTC_IRQRR_IRQ1F                        (0x0002u)
+#define INTC_IRQRR_IRQ2F                        (0x0004u)
+#define INTC_IRQRR_IRQ3F                        (0x0008u)
+#define INTC_IRQRR_IRQ4F                        (0x0010u)
+#define INTC_IRQRR_IRQ5F                        (0x0020u)
+#define INTC_IRQRR_IRQ6F                        (0x0040u)
+#define INTC_IRQRR_IRQ7F                        (0x0080u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define INTC_ICDDCR_Enable_SHIFT                (0u)
+
+#define INTC_ICDICTR_ITLinesNumber_SHIFT        (0u)
+#define INTC_ICDICTR_CPUNumber_SHIFT            (5u)
+#define INTC_ICDICTR_SecurityExtn_SHIFT         (10u)
+#define INTC_ICDICTR_LSPI_SHIFT                 (11u)
+
+#define INTC_ICDIIDR_Implementer_SHIFT          (0u)
+#define INTC_ICDIIDR_Revision_SHIFT             (12u)
+#define INTC_ICDIIDR_Variant_SHIFT              (16u)
+#define INTC_ICDIIDR_ProductID_SHIFT            (24u)
+
+#define INTC_ICDISR0_SW0_SHIFT                  (0u)
+#define INTC_ICDISR0_SW1_SHIFT                  (1u)
+#define INTC_ICDISR0_SW2_SHIFT                  (2u)
+#define INTC_ICDISR0_SW3_SHIFT                  (3u)
+#define INTC_ICDISR0_SW4_SHIFT                  (4u)
+#define INTC_ICDISR0_SW5_SHIFT                  (5u)
+#define INTC_ICDISR0_SW6_SHIFT                  (6u)
+#define INTC_ICDISR0_SW7_SHIFT                  (7u)
+#define INTC_ICDISR0_SW8_SHIFT                  (8u)
+#define INTC_ICDISR0_SW9_SHIFT                  (9u)
+#define INTC_ICDISR0_SW10_SHIFT                 (10u)
+#define INTC_ICDISR0_SW11_SHIFT                 (11u)
+#define INTC_ICDISR0_SW12_SHIFT                 (12u)
+#define INTC_ICDISR0_SW13_SHIFT                 (13u)
+#define INTC_ICDISR0_SW14_SHIFT                 (14u)
+#define INTC_ICDISR0_SW15_SHIFT                 (15u)
+#define INTC_ICDISR0_PMUIRQ0_SHIFT              (16u)
+#define INTC_ICDISR0_COMMRX0_SHIFT              (17u)
+#define INTC_ICDISR0_COMMTX0_SHIFT              (18u)
+#define INTC_ICDISR0_CTIIRQ0_SHIFT              (19u)
+
+#define INTC_ICDISR1_IRQ0_SHIFT                 (0u)
+#define INTC_ICDISR1_IRQ1_SHIFT                 (1u)
+#define INTC_ICDISR1_IRQ2_SHIFT                 (2u)
+#define INTC_ICDISR1_IRQ3_SHIFT                 (3u)
+#define INTC_ICDISR1_IRQ4_SHIFT                 (4u)
+#define INTC_ICDISR1_IRQ5_SHIFT                 (5u)
+#define INTC_ICDISR1_IRQ6_SHIFT                 (6u)
+#define INTC_ICDISR1_IRQ7_SHIFT                 (7u)
+#define INTC_ICDISR1_PL310ERR_SHIFT             (8u)
+#define INTC_ICDISR1_DMAINT0_SHIFT              (9u)
+#define INTC_ICDISR1_DMAINT1_SHIFT              (10u)
+#define INTC_ICDISR1_DMAINT2_SHIFT              (11u)
+#define INTC_ICDISR1_DMAINT3_SHIFT              (12u)
+#define INTC_ICDISR1_DMAINT4_SHIFT              (13u)
+#define INTC_ICDISR1_DMAINT5_SHIFT              (14u)
+#define INTC_ICDISR1_DMAINT6_SHIFT              (15u)
+#define INTC_ICDISR1_DMAINT7_SHIFT              (16u)
+#define INTC_ICDISR1_DMAINT8_SHIFT              (17u)
+#define INTC_ICDISR1_DMAINT9_SHIFT              (18u)
+#define INTC_ICDISR1_DMAINT10_SHIFT             (19u)
+#define INTC_ICDISR1_DMAINT11_SHIFT             (20u)
+#define INTC_ICDISR1_DMAINT12_SHIFT             (21u)
+#define INTC_ICDISR1_DMAINT13_SHIFT             (22u)
+#define INTC_ICDISR1_DMAINT14_SHIFT             (23u)
+#define INTC_ICDISR1_DMAINT15_SHIFT             (24u)
+#define INTC_ICDISR1_DMAERR_SHIFT               (25u)
+
+#define INTC_ICDISR2_USBI0_SHIFT                (9u)
+#define INTC_ICDISR2_USBI1_SHIFT                (10u)
+#define INTC_ICDISR2_S0_VI_VSYNC0_SHIFT         (11u)
+#define INTC_ICDISR2_S0_LO_VSYNC0_SHIFT         (12u)
+#define INTC_ICDISR2_S0_VSYNCERR0_SHIFT         (13u)
+#define INTC_ICDISR2_GR3_VLINE0_SHIFT           (14u)
+#define INTC_ICDISR2_S0_VFIELD0_SHIFT           (15u)
+#define INTC_ICDISR2_IV1_VBUFERR0_SHIFT         (16u)
+#define INTC_ICDISR2_IV3_VBUFERR0_SHIFT         (17u)
+#define INTC_ICDISR2_IV5_VBUFERR0_SHIFT         (18u)
+#define INTC_ICDISR2_IV6_VBUFERR0_SHIFT         (19u)
+#define INTC_ICDISR2_S0_WLINE0_SHIFT            (20u)
+#define INTC_ICDISR2_S1_VI_VSYNC0_SHIFT         (21u)
+#define INTC_ICDISR2_S1_LO_VSYNC0_SHIFT         (22u)
+#define INTC_ICDISR2_S1_VSYNCERR0_SHIFT         (23u)
+#define INTC_ICDISR2_S1_VFIELD0_SHIFT           (24u)
+#define INTC_ICDISR2_IV2_VBUFERR0_SHIFT         (25u)
+#define INTC_ICDISR2_IV4_VBUFERR0_SHIFT         (26u)
+#define INTC_ICDISR2_S1_WLINE0_SHIFT            (27u)
+#define INTC_ICDISR2_OIR_VI_VSYNC0_SHIFT        (28u)
+#define INTC_ICDISR2_OIR_LO_VSYNC0_SHIFT        (29u)
+#define INTC_ICDISR2_OIR_VSYNCERR0_SHIFT        (30u)
+#define INTC_ICDISR2_OIR_VFIELD0_SHIFT          (31u)
+
+#define INTC_ICDISR3_IV7_VBUFERR0_SHIFT         (0u)
+#define INTC_ICDISR3_IV8_VBUFERR0_SHIFT         (1u)
+#define INTC_ICDISR3_S0_VI_VSYNC1_SHIFT         (3u)
+#define INTC_ICDISR3_S0_LO_VSYNC1_SHIFT         (4u)
+#define INTC_ICDISR3_S0_VSYNCERR1_SHIFT         (5u)
+#define INTC_ICDISR3_GR3_VLINE1_SHIFT           (6u)
+#define INTC_ICDISR3_S0_VFIELD1_SHIFT           (7u)
+#define INTC_ICDISR3_IV1_VBUFERR1_SHIFT         (8u)
+#define INTC_ICDISR3_IV3_VBUFERR1_SHIFT         (9u)
+#define INTC_ICDISR3_IV5_VBUFERR1_SHIFT         (10u)
+#define INTC_ICDISR3_IV6_VBUFERR1_SHIFT         (11u)
+#define INTC_ICDISR3_S0_WLINE1_SHIFT            (12u)
+#define INTC_ICDISR3_S1_VI_VSYNC1_SHIFT         (13u)
+#define INTC_ICDISR3_S1_LO_VSYNC1_SHIFT         (14u)
+#define INTC_ICDISR3_S1_VSYNCERR1_SHIFT         (15u)
+#define INTC_ICDISR3_S1_VFIELD1_SHIFT           (16u)
+#define INTC_ICDISR3_IV2_VBUFERR1_SHIFT         (17u)
+#define INTC_ICDISR3_IV4_VBUFERR1_SHIFT         (18u)
+#define INTC_ICDISR3_S1_WLINE1_SHIFT            (19u)
+#define INTC_ICDISR3_OIR_VI_VSYNC1_SHIFT        (20u)
+#define INTC_ICDISR3_OIR_LO_VSYNC1_SHIFT        (21u)
+#define INTC_ICDISR3_OIR_VLINE1_SHIFT           (22u)
+#define INTC_ICDISR3_OIR_VFIELD1_SHIFT          (23u)
+#define INTC_ICDISR3_IV7_VBUFERR1_SHIFT         (24u)
+#define INTC_ICDISR3_IV8_VBUFERR1_SHIFT         (25u)
+#define INTC_ICDISR3_IMRDI_SHIFT                (27u)
+#define INTC_ICDISR3_IMR2I0_SHIFT               (28u)
+#define INTC_ICDISR3_IMR2I1_SHIFT               (29u)
+#define INTC_ICDISR3_JEDI_SHIFT                 (30u)
+#define INTC_ICDISR3_JDTI_SHIFT                 (31u)
+
+#define INTC_ICDISR4_CMP0_SHIFT                 (0u)
+#define INTC_ICDISR4_CMP1_SHIFT                 (1u)
+#define INTC_ICDISR4_INT0_SHIFT                 (2u)
+#define INTC_ICDISR4_INT1_SHIFT                 (3u)
+#define INTC_ICDISR4_INT2_SHIFT                 (4u)
+#define INTC_ICDISR4_INT3_SHIFT                 (5u)
+#define INTC_ICDISR4_OSTM0TINT_SHIFT            (6u)
+#define INTC_ICDISR4_OSTM1TINT_SHIFT            (7u)
+#define INTC_ICDISR4_CMI_SHIFT                  (8u)
+#define INTC_ICDISR4_WTOUT_SHIFT                (9u)
+#define INTC_ICDISR4_ITI_SHIFT                  (10u)
+#define INTC_ICDISR4_TGI0A_SHIFT                (11u)
+#define INTC_ICDISR4_TGI0B_SHIFT                (12u)
+#define INTC_ICDISR4_TGI0C_SHIFT                (13u)
+#define INTC_ICDISR4_TGI0D_SHIFT                (14u)
+#define INTC_ICDISR4_TGI0V_SHIFT                (15u)
+#define INTC_ICDISR4_TGI0E_SHIFT                (16u)
+#define INTC_ICDISR4_TGI0F_SHIFT                (17u)
+#define INTC_ICDISR4_TGI1A_SHIFT                (18u)
+#define INTC_ICDISR4_TGI1B_SHIFT                (19u)
+#define INTC_ICDISR4_TGI1V_SHIFT                (20u)
+#define INTC_ICDISR4_TGI1U_SHIFT                (21u)
+#define INTC_ICDISR4_TGI2A_SHIFT                (22u)
+#define INTC_ICDISR4_TGI2B_SHIFT                (23u)
+#define INTC_ICDISR4_TGI2V_SHIFT                (24u)
+#define INTC_ICDISR4_TGI2U_SHIFT                (25u)
+#define INTC_ICDISR4_TGI3A_SHIFT                (26u)
+#define INTC_ICDISR4_TGI3B_SHIFT                (27u)
+#define INTC_ICDISR4_TGI3C_SHIFT                (28u)
+#define INTC_ICDISR4_TGI3D_SHIFT                (29u)
+#define INTC_ICDISR4_TGI3V_SHIFT                (30u)
+#define INTC_ICDISR4_TGI4A_SHIFT                (31u)
+
+#define INTC_ICDISR5_TGI4B_SHIFT                (0u)
+#define INTC_ICDISR5_TGI4C_SHIFT                (1u)
+#define INTC_ICDISR5_TGI4D_SHIFT                (2u)
+#define INTC_ICDISR5_TGI4V_SHIFT                (3u)
+#define INTC_ICDISR5_CMI1_SHIFT                 (4u)
+#define INTC_ICDISR5_CMI2_SHIFT                 (5u)
+#define INTC_ICDISR5_SGDEI0_SHIFT               (6u)
+#define INTC_ICDISR5_SGDEI1_SHIFT               (7u)
+#define INTC_ICDISR5_SGDEI2_SHIFT               (8u)
+#define INTC_ICDISR5_SGDEI3_SHIFT               (9u)
+#define INTC_ICDISR5_ADI_SHIFT                  (10u)
+#define INTC_ICDISR5_LMTI_SHIFT                 (11u)
+#define INTC_ICDISR5_SSII0_SHIFT                (12u)
+#define INTC_ICDISR5_SSIRXI0_SHIFT              (13u)
+#define INTC_ICDISR5_SSITXI0_SHIFT              (14u)
+#define INTC_ICDISR5_SSII1_SHIFT                (15u)
+#define INTC_ICDISR5_SSIRXI1_SHIFT              (16u)
+#define INTC_ICDISR5_SSITXI1_SHIFT              (17u)
+#define INTC_ICDISR5_SSII2_SHIFT                (18u)
+#define INTC_ICDISR5_SSIRTI2_SHIFT              (19u)
+#define INTC_ICDISR5_SSII3_SHIFT                (20u)
+#define INTC_ICDISR5_SSIRXI3_SHIFT              (21u)
+#define INTC_ICDISR5_SSITXI3_SHIFT              (22u)
+#define INTC_ICDISR5_SSII4_SHIFT                (23u)
+#define INTC_ICDISR5_SSIRTI4_SHIFT              (24u)
+#define INTC_ICDISR5_SSII5_SHIFT                (25u)
+#define INTC_ICDISR5_SSIRXI5_SHIFT              (26u)
+#define INTC_ICDISR5_SSITXI5_SHIFT              (27u)
+#define INTC_ICDISR5_SPDIFI_SHIFT               (28u)
+#define INTC_ICDISR5_INTIICTEI0_SHIFT           (29u)
+#define INTC_ICDISR5_INTIICRI0_SHIFT            (30u)
+#define INTC_ICDISR5_INTIICTI0_SHIFT            (31u)
+
+#define INTC_ICDISR6_INTIICSPI0_SHIFT           (0u)
+#define INTC_ICDISR6_INTIICSTI0_SHIFT           (1u)
+#define INTC_ICDISR6_INTIICNAKI0_SHIFT          (2u)
+#define INTC_ICDISR6_INTIICALI0_SHIFT           (3u)
+#define INTC_ICDISR6_INTIICTMOI0_SHIFT          (4u)
+#define INTC_ICDISR6_INTIICTEI1_SHIFT           (5u)
+#define INTC_ICDISR6_INTIICRI1_SHIFT            (6u)
+#define INTC_ICDISR6_INTIICTI1_SHIFT            (7u)
+#define INTC_ICDISR6_INTIICSPI1_SHIFT           (8u)
+#define INTC_ICDISR6_INTIICSTI1_SHIFT           (9u)
+#define INTC_ICDISR6_INTIICNAKI1_SHIFT          (10u)
+#define INTC_ICDISR6_INTIICALI1_SHIFT           (11u)
+#define INTC_ICDISR6_INTIICTMOI1_SHIFT          (12u)
+#define INTC_ICDISR6_INTIICTEI2_SHIFT           (13u)
+#define INTC_ICDISR6_INTIICRI2_SHIFT            (14u)
+#define INTC_ICDISR6_INTIICTI2_SHIFT            (15u)
+#define INTC_ICDISR6_INTIICSPI2_SHIFT           (16u)
+#define INTC_ICDISR6_INTIICSTI2_SHIFT           (17u)
+#define INTC_ICDISR6_INTIICNAKI2_SHIFT          (18u)
+#define INTC_ICDISR6_INTIICALI2_SHIFT           (19u)
+#define INTC_ICDISR6_INTIICTMOI2_SHIFT          (20u)
+#define INTC_ICDISR6_INTIICTEI3_SHIFT           (21u)
+#define INTC_ICDISR6_INTIICRI3_SHIFT            (22u)
+#define INTC_ICDISR6_INTIICTI3_SHIFT            (23u)
+#define INTC_ICDISR6_INTIICSPI3_SHIFT           (24u)
+#define INTC_ICDISR6_INTIICSTI3_SHIFT           (25u)
+#define INTC_ICDISR6_INTIICNAKI3_SHIFT          (26u)
+#define INTC_ICDISR6_INTIICALI3_SHIFT           (27u)
+#define INTC_ICDISR6_INTIICTMOI3_SHIFT          (28u)
+#define INTC_ICDISR6_BRI0_SHIFT                 (29u)
+#define INTC_ICDISR6_ERI0_SHIFT                 (30u)
+#define INTC_ICDISR6_RXI0_SHIFT                 (31u)
+
+#define INTC_ICDISR7_TXI0_SHIFT                 (0u)
+#define INTC_ICDISR7_BRI1_SHIFT                 (1u)
+#define INTC_ICDISR7_ERI1_SHIFT                 (2u)
+#define INTC_ICDISR7_RXI1_SHIFT                 (3u)
+#define INTC_ICDISR7_TXI1_SHIFT                 (4u)
+#define INTC_ICDISR7_BRI2_SHIFT                 (5u)
+#define INTC_ICDISR7_ERI2_SHIFT                 (6u)
+#define INTC_ICDISR7_RXI2_SHIFT                 (7u)
+#define INTC_ICDISR7_TXI2_SHIFT                 (8u)
+#define INTC_ICDISR7_BRI3_SHIFT                 (9u)
+#define INTC_ICDISR7_ERI3_SHIFT                 (10u)
+#define INTC_ICDISR7_RXI3_SHIFT                 (11u)
+#define INTC_ICDISR7_TXI3_SHIFT                 (12u)
+#define INTC_ICDISR7_BRI4_SHIFT                 (13u)
+#define INTC_ICDISR7_ERI4_SHIFT                 (14u)
+#define INTC_ICDISR7_RXI4_SHIFT                 (15u)
+#define INTC_ICDISR7_TXI4_SHIFT                 (16u)
+#define INTC_ICDISR7_BRI5_SHIFT                 (17u)
+#define INTC_ICDISR7_ERI5_SHIFT                 (18u)
+#define INTC_ICDISR7_RXI5_SHIFT                 (19u)
+#define INTC_ICDISR7_TXI5_SHIFT                 (20u)
+#define INTC_ICDISR7_BRI6_SHIFT                 (21u)
+#define INTC_ICDISR7_ERI6_SHIFT                 (22u)
+#define INTC_ICDISR7_RXI6_SHIFT                 (23u)
+#define INTC_ICDISR7_TXI6_SHIFT                 (24u)
+#define INTC_ICDISR7_BRI7_SHIFT                 (25u)
+#define INTC_ICDISR7_ERI7_SHIFT                 (26u)
+#define INTC_ICDISR7_RXI7_SHIFT                 (27u)
+#define INTC_ICDISR7_TXI7_SHIFT                 (28u)
+#define INTC_ICDISR7_INTRCANGERR_SHIFT          (29u)
+#define INTC_ICDISR7_INTRCANGRECC_SHIFT         (30u)
+#define INTC_ICDISR7_INTRCAN0REC_SHIFT          (31u)
+
+#define INTC_ICDISR8_INTRCAN0ERR_SHIFT          (0u)
+#define INTC_ICDISR8_INTRCAN0TRX_SHIFT          (1u)
+#define INTC_ICDISR8_INTRCAN1REC_SHIFT          (2u)
+#define INTC_ICDISR8_INTRCAN1ERR_SHIFT          (3u)
+#define INTC_ICDISR8_INTRCAN1TRX_SHIFT          (4u)
+#define INTC_ICDISR8_INTRCAN2REC_SHIFT          (5u)
+#define INTC_ICDISR8_INTRCAN2ERR_SHIFT          (6u)
+#define INTC_ICDISR8_INTRCAN2TRX_SHIFT          (7u)
+#define INTC_ICDISR8_INTRCAN3REC_SHIFT          (8u)
+#define INTC_ICDISR8_INTRCAN3ERR_SHIFT          (9u)
+#define INTC_ICDISR8_INTRCAN3TRX_SHIFT          (10u)
+#define INTC_ICDISR8_INTRCAN4REC_SHIFT          (11u)
+#define INTC_ICDISR8_INTRCAN4ERR_SHIFT          (12u)
+#define INTC_ICDISR8_INTRCAN4TRX_SHIFT          (13u)
+#define INTC_ICDISR8_SPEI0_SHIFT                (14u)
+#define INTC_ICDISR8_SPRI0_SHIFT                (15u)
+#define INTC_ICDISR8_SPTI0_SHIFT                (16u)
+#define INTC_ICDISR8_SPEI1_SHIFT                (17u)
+#define INTC_ICDISR8_SPRI1_SHIFT                (18u)
+#define INTC_ICDISR8_SPTI1_SHIFT                (19u)
+#define INTC_ICDISR8_SPEI2_SHIFT                (20u)
+#define INTC_ICDISR8_SPRI2_SHIFT                (21u)
+#define INTC_ICDISR8_SPTI2_SHIFT                (22u)
+#define INTC_ICDISR8_SPEI3_SHIFT                (23u)
+#define INTC_ICDISR8_SPRI3_SHIFT                (24u)
+#define INTC_ICDISR8_SPTI3_SHIFT                (25u)
+#define INTC_ICDISR8_SPEI4_SHIFT                (26u)
+#define INTC_ICDISR8_SPRI4_SHIFT                (27u)
+#define INTC_ICDISR8_SPTI4_SHIFT                (28u)
+#define INTC_ICDISR8_IEBBTD_SHIFT               (29u)
+#define INTC_ICDISR8_IEBBTERR_SHIFT             (30u)
+#define INTC_ICDISR8_IEBBTSTA_SHIFT             (31u)
+
+#define INTC_ICDISR9_IEBBTV_SHIFT               (0u)
+#define INTC_ICDISR9_ISY_SHIFT                  (1u)
+#define INTC_ICDISR9_IERR_SHIFT                 (2u)
+#define INTC_ICDISR9_ITARG_SHIFT                (3u)
+#define INTC_ICDISR9_ISEC_SHIFT                 (4u)
+#define INTC_ICDISR9_IBUF_SHIFT                 (5u)
+#define INTC_ICDISR9_IREADY_SHIFT               (6u)
+#define INTC_ICDISR9_FLSTE_SHIFT                (7u)
+#define INTC_ICDISR9_FLTENDI_SHIFT              (8u)
+#define INTC_ICDISR9_FLTREQ0I_SHIFT             (9u)
+#define INTC_ICDISR9_FLTREQ1I_SHIFT             (10u)
+#define INTC_ICDISR9_MMC0_SHIFT                 (11u)
+#define INTC_ICDISR9_MMC1_SHIFT                 (12u)
+#define INTC_ICDISR9_MMC2_SHIFT                 (13u)
+#define INTC_ICDISR9_SDHI0_3_SHIFT              (14u)
+#define INTC_ICDISR9_SDHI0_0_SHIFT              (15u)
+#define INTC_ICDISR9_SDHI0_1_SHIFT              (16u)
+#define INTC_ICDISR9_SDHI1_3_SHIFT              (17u)
+#define INTC_ICDISR9_SDHI1_0_SHIFT              (18u)
+#define INTC_ICDISR9_SDHI1_1_SHIFT              (19u)
+#define INTC_ICDISR9_ARM_SHIFT                  (20u)
+#define INTC_ICDISR9_PRD_SHIFT                  (21u)
+#define INTC_ICDISR9_CUP_SHIFT                  (22u)
+#define INTC_ICDISR9_SCUAI0_SHIFT               (23u)
+#define INTC_ICDISR9_SCUAI1_SHIFT               (24u)
+#define INTC_ICDISR9_SCUFDI0_SHIFT              (25u)
+#define INTC_ICDISR9_SCUFDI1_SHIFT              (26u)
+#define INTC_ICDISR9_SCUFDI2_SHIFT              (27u)
+#define INTC_ICDISR9_SCUFDI3_SHIFT              (28u)
+#define INTC_ICDISR9_SCUFUI0_SHIFT              (29u)
+#define INTC_ICDISR9_SCUFUI1_SHIFT              (30u)
+#define INTC_ICDISR9_SCUFUI2_SHIFT              (31u)
+
+#define INTC_ICDISR10_SCUFUI3_SHIFT             (0u)
+#define INTC_ICDISR10_SCUDVI0_SHIFT             (1u)
+#define INTC_ICDISR10_SCUDVI1_SHIFT             (2u)
+#define INTC_ICDISR10_SCUDVI2_SHIFT             (3u)
+#define INTC_ICDISR10_SCUDVI3_SHIFT             (4u)
+#define INTC_ICDISR10_MLB_CINT_SHIFT            (5u)
+#define INTC_ICDISR10_MLB_SINT_SHIFT            (6u)
+#define INTC_ICDISR10_DRC0_SHIFT                (7u)
+#define INTC_ICDISR10_DRC1_SHIFT                (8u)
+#define INTC_ICDISR10_LINI0_INT_T_SHIFT         (11u)
+#define INTC_ICDISR10_LINI0_INT_R_SHIFT         (12u)
+#define INTC_ICDISR10_LINI0_INT_S_SHIFT         (13u)
+#define INTC_ICDISR10_LINI0_INT_M_SHIFT         (14u)
+#define INTC_ICDISR10_LINI1_INT_T_SHIFT         (15u)
+#define INTC_ICDISR10_LINI1_INT_R_SHIFT         (16u)
+#define INTC_ICDISR10_LINI1_INT_S_SHIFT         (17u)
+#define INTC_ICDISR10_LINI1_INT_M_SHIFT         (18u)
+#define INTC_ICDISR10_ERI0_SHIFT                (27u)
+#define INTC_ICDISR10_RXI0_SHIFT                (28u)
+#define INTC_ICDISR10_TXI0_SHIFT                (29u)
+#define INTC_ICDISR10_TEI0_SHIFT                (30u)
+#define INTC_ICDISR10_ERI1_SHIFT                (31u)
+
+#define INTC_ICDISR11_RXI1_SHIFT                (0u)
+#define INTC_ICDISR11_TXI1_SHIFT                (1u)
+#define INTC_ICDISR11_TEI1_SHIFT                (2u)
+#define INTC_ICDISR11_AVBI_DATA_SHIFT           (3u)
+#define INTC_ICDISR11_AVBI_ERROR_SHIFT          (4u)
+#define INTC_ICDISR11_AVBI_MANAGE_SHIFT         (5u)
+#define INTC_ICDISR11_AVBI_MAC_SHIFT            (6u)
+#define INTC_ICDISR11_ETHERI_SHIFT              (7u)
+#define INTC_ICDISR11_CEUI_SHIFT                (12u)
+#define INTC_ICDISR11_H2XMLB_ERRINT_SHIFT       (29u)
+#define INTC_ICDISR11_H2XIC1_ERRINT_SHIFT       (30u)
+#define INTC_ICDISR11_X2HPERI1_ERRINT_SHIFT     (31u)
+
+#define INTC_ICDISR12_X2HPERI2_ERRINT_SHIFT     (0u)
+#define INTC_ICDISR12_X2HPERI34_ERRINT_SHIFT    (1u)
+#define INTC_ICDISR12_X2HPERI5_ERRINT_SHIFT     (2u)
+#define INTC_ICDISR12_X2HPERI67_ERRINT_SHIFT    (3u)
+#define INTC_ICDISR12_X2HDBGR_ERRINT_SHIFT      (4u)
+#define INTC_ICDISR12_X2HBSC_ERRINT_SHIFT       (5u)
+#define INTC_ICDISR12_X2HSPI1_ERRINT_SHIFT      (6u)
+#define INTC_ICDISR12_X2HSPI2_ERRINT_SHIFT      (7u)
+#define INTC_ICDISR12_PRRI_SHIFT                (8u)
+#define INTC_ICDISR12_IFEI0_SHIFT               (9u)
+#define INTC_ICDISR12_OFFI0_SHIFT               (10u)
+#define INTC_ICDISR12_PFVEI0_SHIFT              (11u)
+#define INTC_ICDISR12_IFEI1_SHIFT               (12u)
+#define INTC_ICDISR12_OFFI1_SHIFT               (13u)
+#define INTC_ICDISR12_PFVEI1_SHIFT              (14u)
+
+#define INTC_ICDISR13_TINT0_SHIFT               (0u)
+#define INTC_ICDISR13_TINT1_SHIFT               (1u)
+#define INTC_ICDISR13_TINT2_SHIFT               (2u)
+#define INTC_ICDISR13_TINT3_SHIFT               (3u)
+#define INTC_ICDISR13_TINT4_SHIFT               (4u)
+#define INTC_ICDISR13_TINT5_SHIFT               (5u)
+#define INTC_ICDISR13_TINT6_SHIFT               (6u)
+#define INTC_ICDISR13_TINT7_SHIFT               (7u)
+#define INTC_ICDISR13_TINT8_SHIFT               (8u)
+#define INTC_ICDISR13_TINT9_SHIFT               (9u)
+#define INTC_ICDISR13_TINT10_SHIFT              (10u)
+#define INTC_ICDISR13_TINT11_SHIFT              (11u)
+#define INTC_ICDISR13_TINT12_SHIFT              (12u)
+#define INTC_ICDISR13_TINT13_SHIFT              (13u)
+#define INTC_ICDISR13_TINT14_SHIFT              (14u)
+#define INTC_ICDISR13_TINT15_SHIFT              (15u)
+#define INTC_ICDISR13_TINT16_SHIFT              (16u)
+#define INTC_ICDISR13_TINT17_SHIFT              (17u)
+#define INTC_ICDISR13_TINT18_SHIFT              (18u)
+#define INTC_ICDISR13_TINT19_SHIFT              (19u)
+#define INTC_ICDISR13_TINT20_SHIFT              (20u)
+#define INTC_ICDISR13_TINT21_SHIFT              (21u)
+#define INTC_ICDISR13_TINT22_SHIFT              (22u)
+#define INTC_ICDISR13_TINT23_SHIFT              (23u)
+#define INTC_ICDISR13_TINT24_SHIFT              (24u)
+#define INTC_ICDISR13_TINT25_SHIFT              (25u)
+#define INTC_ICDISR13_TINT26_SHIFT              (26u)
+#define INTC_ICDISR13_TINT27_SHIFT              (27u)
+#define INTC_ICDISR13_TINT28_SHIFT              (28u)
+#define INTC_ICDISR13_TINT29_SHIFT              (29u)
+#define INTC_ICDISR13_TINT30_SHIFT              (30u)
+#define INTC_ICDISR13_TINT31_SHIFT              (31u)
+
+#define INTC_ICDISR14_TINT32_SHIFT              (0u)
+#define INTC_ICDISR14_TINT33_SHIFT              (1u)
+#define INTC_ICDISR14_TINT34_SHIFT              (2u)
+#define INTC_ICDISR14_TINT35_SHIFT              (3u)
+#define INTC_ICDISR14_TINT36_SHIFT              (4u)
+#define INTC_ICDISR14_TINT37_SHIFT              (5u)
+#define INTC_ICDISR14_TINT38_SHIFT              (6u)
+#define INTC_ICDISR14_TINT39_SHIFT              (7u)
+#define INTC_ICDISR14_TINT40_SHIFT              (8u)
+#define INTC_ICDISR14_TINT41_SHIFT              (9u)
+#define INTC_ICDISR14_TINT42_SHIFT              (10u)
+#define INTC_ICDISR14_TINT43_SHIFT              (11u)
+#define INTC_ICDISR14_TINT44_SHIFT              (12u)
+#define INTC_ICDISR14_TINT45_SHIFT              (13u)
+#define INTC_ICDISR14_TINT46_SHIFT              (14u)
+#define INTC_ICDISR14_TINT47_SHIFT              (15u)
+#define INTC_ICDISR14_TINT48_SHIFT              (16u)
+#define INTC_ICDISR14_TINT49_SHIFT              (17u)
+#define INTC_ICDISR14_TINT50_SHIFT              (18u)
+#define INTC_ICDISR14_TINT51_SHIFT              (19u)
+#define INTC_ICDISR14_TINT52_SHIFT              (20u)
+#define INTC_ICDISR14_TINT53_SHIFT              (21u)
+#define INTC_ICDISR14_TINT54_SHIFT              (22u)
+#define INTC_ICDISR14_TINT55_SHIFT              (23u)
+#define INTC_ICDISR14_TINT56_SHIFT              (24u)
+#define INTC_ICDISR14_TINT57_SHIFT              (25u)
+#define INTC_ICDISR14_TINT58_SHIFT              (26u)
+#define INTC_ICDISR14_TINT59_SHIFT              (27u)
+#define INTC_ICDISR14_TINT60_SHIFT              (28u)
+#define INTC_ICDISR14_TINT61_SHIFT              (29u)
+#define INTC_ICDISR14_TINT62_SHIFT              (30u)
+#define INTC_ICDISR14_TINT63_SHIFT              (31u)
+
+#define INTC_ICDISR15_TINT64_SHIFT              (0u)
+#define INTC_ICDISR15_TINT65_SHIFT              (1u)
+#define INTC_ICDISR15_TINT66_SHIFT              (2u)
+#define INTC_ICDISR15_TINT67_SHIFT              (3u)
+#define INTC_ICDISR15_TINT68_SHIFT              (4u)
+#define INTC_ICDISR15_TINT69_SHIFT              (5u)
+#define INTC_ICDISR15_TINT70_SHIFT              (6u)
+#define INTC_ICDISR15_TINT71_SHIFT              (7u)
+#define INTC_ICDISR15_TINT72_SHIFT              (8u)
+#define INTC_ICDISR15_TINT73_SHIFT              (9u)
+#define INTC_ICDISR15_TINT74_SHIFT              (10u)
+#define INTC_ICDISR15_TINT75_SHIFT              (11u)
+#define INTC_ICDISR15_TINT76_SHIFT              (12u)
+#define INTC_ICDISR15_TINT77_SHIFT              (13u)
+#define INTC_ICDISR15_TINT78_SHIFT              (14u)
+#define INTC_ICDISR15_TINT79_SHIFT              (15u)
+#define INTC_ICDISR15_TINT80_SHIFT              (16u)
+#define INTC_ICDISR15_TINT81_SHIFT              (17u)
+#define INTC_ICDISR15_TINT82_SHIFT              (18u)
+#define INTC_ICDISR15_TINT83_SHIFT              (19u)
+#define INTC_ICDISR15_TINT84_SHIFT              (20u)
+#define INTC_ICDISR15_TINT85_SHIFT              (21u)
+#define INTC_ICDISR15_TINT86_SHIFT              (22u)
+#define INTC_ICDISR15_TINT87_SHIFT              (23u)
+#define INTC_ICDISR15_TINT88_SHIFT              (24u)
+#define INTC_ICDISR15_TINT89_SHIFT              (25u)
+#define INTC_ICDISR15_TINT90_SHIFT              (26u)
+#define INTC_ICDISR15_TINT91_SHIFT              (27u)
+#define INTC_ICDISR15_TINT92_SHIFT              (28u)
+#define INTC_ICDISR15_TINT93_SHIFT              (29u)
+#define INTC_ICDISR15_TINT94_SHIFT              (30u)
+#define INTC_ICDISR15_TINT95_SHIFT              (31u)
+
+#define INTC_ICDISR16_TINT96_SHIFT              (0u)
+#define INTC_ICDISR16_TINT97_SHIFT              (1u)
+#define INTC_ICDISR16_TINT98_SHIFT              (2u)
+#define INTC_ICDISR16_TINT99_SHIFT              (3u)
+#define INTC_ICDISR16_TINT100_SHIFT             (4u)
+#define INTC_ICDISR16_TINT101_SHIFT             (5u)
+#define INTC_ICDISR16_TINT102_SHIFT             (6u)
+#define INTC_ICDISR16_TINT103_SHIFT             (7u)
+#define INTC_ICDISR16_TINT104_SHIFT             (8u)
+#define INTC_ICDISR16_TINT105_SHIFT             (9u)
+#define INTC_ICDISR16_TINT106_SHIFT             (10u)
+#define INTC_ICDISR16_TINT107_SHIFT             (11u)
+#define INTC_ICDISR16_TINT108_SHIFT             (12u)
+#define INTC_ICDISR16_TINT109_SHIFT             (13u)
+#define INTC_ICDISR16_TINT110_SHIFT             (14u)
+#define INTC_ICDISR16_TINT111_SHIFT             (15u)
+#define INTC_ICDISR16_TINT112_SHIFT             (16u)
+#define INTC_ICDISR16_TINT113_SHIFT             (17u)
+#define INTC_ICDISR16_TINT114_SHIFT             (18u)
+#define INTC_ICDISR16_TINT115_SHIFT             (19u)
+#define INTC_ICDISR16_TINT116_SHIFT             (20u)
+#define INTC_ICDISR16_TINT117_SHIFT             (21u)
+#define INTC_ICDISR16_TINT118_SHIFT             (22u)
+#define INTC_ICDISR16_TINT119_SHIFT             (23u)
+#define INTC_ICDISR16_TINT120_SHIFT             (24u)
+#define INTC_ICDISR16_TINT121_SHIFT             (25u)
+#define INTC_ICDISR16_TINT122_SHIFT             (26u)
+#define INTC_ICDISR16_TINT123_SHIFT             (27u)
+#define INTC_ICDISR16_TINT124_SHIFT             (28u)
+#define INTC_ICDISR16_TINT125_SHIFT             (29u)
+#define INTC_ICDISR16_TINT126_SHIFT             (30u)
+#define INTC_ICDISR16_TINT127_SHIFT             (31u)
+
+#define INTC_ICDISR17_TINT128_SHIFT             (0u)
+#define INTC_ICDISR17_TINT129_SHIFT             (1u)
+#define INTC_ICDISR17_TINT130_SHIFT             (2u)
+#define INTC_ICDISR17_TINT131_SHIFT             (3u)
+#define INTC_ICDISR17_TINT132_SHIFT             (4u)
+#define INTC_ICDISR17_TINT133_SHIFT             (5u)
+#define INTC_ICDISR17_TINT134_SHIFT             (6u)
+#define INTC_ICDISR17_TINT135_SHIFT             (7u)
+#define INTC_ICDISR17_TINT136_SHIFT             (8u)
+#define INTC_ICDISR17_TINT137_SHIFT             (9u)
+#define INTC_ICDISR17_TINT138_SHIFT             (10u)
+#define INTC_ICDISR17_TINT139_SHIFT             (11u)
+#define INTC_ICDISR17_TINT140_SHIFT             (12u)
+#define INTC_ICDISR17_TINT141_SHIFT             (13u)
+#define INTC_ICDISR17_TINT142_SHIFT             (14u)
+#define INTC_ICDISR17_TINT143_SHIFT             (15u)
+#define INTC_ICDISR17_TINT144_SHIFT             (16u)
+#define INTC_ICDISR17_TINT145_SHIFT             (17u)
+#define INTC_ICDISR17_TINT146_SHIFT             (18u)
+#define INTC_ICDISR17_TINT147_SHIFT             (19u)
+#define INTC_ICDISR17_TINT148_SHIFT             (20u)
+#define INTC_ICDISR17_TINT149_SHIFT             (21u)
+#define INTC_ICDISR17_TINT150_SHIFT             (22u)
+#define INTC_ICDISR17_TINT151_SHIFT             (23u)
+#define INTC_ICDISR17_TINT152_SHIFT             (24u)
+#define INTC_ICDISR17_TINT153_SHIFT             (25u)
+#define INTC_ICDISR17_TINT154_SHIFT             (26u)
+#define INTC_ICDISR17_TINT155_SHIFT             (27u)
+#define INTC_ICDISR17_TINT156_SHIFT             (28u)
+#define INTC_ICDISR17_TINT157_SHIFT             (29u)
+#define INTC_ICDISR17_TINT158_SHIFT             (30u)
+#define INTC_ICDISR17_TINT159_SHIFT             (31u)
+
+#define INTC_ICDISR18_TINT160_SHIFT             (0u)
+#define INTC_ICDISR18_TINT161_SHIFT             (1u)
+#define INTC_ICDISR18_TINT162_SHIFT             (2u)
+#define INTC_ICDISR18_TINT163_SHIFT             (3u)
+#define INTC_ICDISR18_TINT164_SHIFT             (4u)
+#define INTC_ICDISR18_TINT165_SHIFT             (5u)
+#define INTC_ICDISR18_TINT166_SHIFT             (6u)
+#define INTC_ICDISR18_TINT167_SHIFT             (7u)
+#define INTC_ICDISR18_TINT168_SHIFT             (8u)
+#define INTC_ICDISR18_TINT169_SHIFT             (9u)
+#define INTC_ICDISR18_TINT170_SHIFT             (10u)
+
+#define INTC_ICDISER0_SW0_SHIFT                 (0u)
+#define INTC_ICDISER0_SW1_SHIFT                 (1u)
+#define INTC_ICDISER0_SW2_SHIFT                 (2u)
+#define INTC_ICDISER0_SW3_SHIFT                 (3u)
+#define INTC_ICDISER0_SW4_SHIFT                 (4u)
+#define INTC_ICDISER0_SW5_SHIFT                 (5u)
+#define INTC_ICDISER0_SW6_SHIFT                 (6u)
+#define INTC_ICDISER0_SW7_SHIFT                 (7u)
+#define INTC_ICDISER0_SW8_SHIFT                 (8u)
+#define INTC_ICDISER0_SW9_SHIFT                 (9u)
+#define INTC_ICDISER0_SW10_SHIFT                (10u)
+#define INTC_ICDISER0_SW11_SHIFT                (11u)
+#define INTC_ICDISER0_SW12_SHIFT                (12u)
+#define INTC_ICDISER0_SW13_SHIFT                (13u)
+#define INTC_ICDISER0_SW14_SHIFT                (14u)
+#define INTC_ICDISER0_SW15_SHIFT                (15u)
+#define INTC_ICDISER0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDISER0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDISER0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDISER0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDISER1_IRQ0_SHIFT                (0u)
+#define INTC_ICDISER1_IRQ1_SHIFT                (1u)
+#define INTC_ICDISER1_IRQ2_SHIFT                (2u)
+#define INTC_ICDISER1_IRQ3_SHIFT                (3u)
+#define INTC_ICDISER1_IRQ4_SHIFT                (4u)
+#define INTC_ICDISER1_IRQ5_SHIFT                (5u)
+#define INTC_ICDISER1_IRQ6_SHIFT                (6u)
+#define INTC_ICDISER1_IRQ7_SHIFT                (7u)
+#define INTC_ICDISER1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDISER1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDISER1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDISER1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDISER1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDISER1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDISER1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDISER1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDISER1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDISER1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDISER1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDISER1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDISER1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDISER1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDISER1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDISER1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDISER1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDISER1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDISER2_USBI0_SHIFT               (9u)
+#define INTC_ICDISER2_USBI1_SHIFT               (10u)
+#define INTC_ICDISER2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDISER2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDISER2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDISER2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDISER2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDISER2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDISER2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDISER2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDISER2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDISER2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDISER2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDISER2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDISER2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDISER2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDISER2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDISER2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDISER2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDISER2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDISER2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDISER2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDISER2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDISER3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDISER3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDISER3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDISER3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDISER3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDISER3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDISER3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDISER3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDISER3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDISER3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDISER3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDISER3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDISER3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDISER3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDISER3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDISER3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDISER3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDISER3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDISER3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDISER3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDISER3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDISER3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDISER3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDISER3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDISER3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDISER3_IMRDI_SHIFT               (27u)
+#define INTC_ICDISER3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDISER3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDISER3_JEDI_SHIFT                (30u)
+#define INTC_ICDISER3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDISER4_CMP0_SHIFT                (0u)
+#define INTC_ICDISER4_CMP1_SHIFT                (1u)
+#define INTC_ICDISER4_INT0_SHIFT                (2u)
+#define INTC_ICDISER4_INT1_SHIFT                (3u)
+#define INTC_ICDISER4_INT2_SHIFT                (4u)
+#define INTC_ICDISER4_INT3_SHIFT                (5u)
+#define INTC_ICDISER4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDISER4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDISER4_CMI_SHIFT                 (8u)
+#define INTC_ICDISER4_WTOUT_SHIFT               (9u)
+#define INTC_ICDISER4_ITI_SHIFT                 (10u)
+#define INTC_ICDISER4_TGI0A_SHIFT               (11u)
+#define INTC_ICDISER4_TGI0B_SHIFT               (12u)
+#define INTC_ICDISER4_TGI0C_SHIFT               (13u)
+#define INTC_ICDISER4_TGI0D_SHIFT               (14u)
+#define INTC_ICDISER4_TGI0V_SHIFT               (15u)
+#define INTC_ICDISER4_TGI0E_SHIFT               (16u)
+#define INTC_ICDISER4_TGI0F_SHIFT               (17u)
+#define INTC_ICDISER4_TGI1A_SHIFT               (18u)
+#define INTC_ICDISER4_TGI1B_SHIFT               (19u)
+#define INTC_ICDISER4_TGI1V_SHIFT               (20u)
+#define INTC_ICDISER4_TGI1U_SHIFT               (21u)
+#define INTC_ICDISER4_TGI2A_SHIFT               (22u)
+#define INTC_ICDISER4_TGI2B_SHIFT               (23u)
+#define INTC_ICDISER4_TGI2V_SHIFT               (24u)
+#define INTC_ICDISER4_TGI2U_SHIFT               (25u)
+#define INTC_ICDISER4_TGI3A_SHIFT               (26u)
+#define INTC_ICDISER4_TGI3B_SHIFT               (27u)
+#define INTC_ICDISER4_TGI3C_SHIFT               (28u)
+#define INTC_ICDISER4_TGI3D_SHIFT               (29u)
+#define INTC_ICDISER4_TGI3V_SHIFT               (30u)
+#define INTC_ICDISER4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDISER5_TGI4B_SHIFT               (0u)
+#define INTC_ICDISER5_TGI4C_SHIFT               (1u)
+#define INTC_ICDISER5_TGI4D_SHIFT               (2u)
+#define INTC_ICDISER5_TGI4V_SHIFT               (3u)
+#define INTC_ICDISER5_CMI1_SHIFT                (4u)
+#define INTC_ICDISER5_CMI2_SHIFT                (5u)
+#define INTC_ICDISER5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDISER5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDISER5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDISER5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDISER5_ADI_SHIFT                 (10u)
+#define INTC_ICDISER5_LMTI_SHIFT                (11u)
+#define INTC_ICDISER5_SSII0_SHIFT               (12u)
+#define INTC_ICDISER5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDISER5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDISER5_SSII1_SHIFT               (15u)
+#define INTC_ICDISER5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDISER5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDISER5_SSII2_SHIFT               (18u)
+#define INTC_ICDISER5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDISER5_SSII3_SHIFT               (20u)
+#define INTC_ICDISER5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDISER5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDISER5_SSII4_SHIFT               (23u)
+#define INTC_ICDISER5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDISER5_SSII5_SHIFT               (25u)
+#define INTC_ICDISER5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDISER5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDISER5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDISER5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDISER5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDISER5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDISER6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDISER6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDISER6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDISER6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDISER6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDISER6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDISER6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDISER6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDISER6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDISER6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDISER6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDISER6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDISER6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDISER6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDISER6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDISER6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDISER6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDISER6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDISER6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDISER6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDISER6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDISER6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDISER6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDISER6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDISER6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDISER6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDISER6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDISER6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDISER6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDISER6_BRI0_SHIFT                (29u)
+#define INTC_ICDISER6_ERI0_SHIFT                (30u)
+#define INTC_ICDISER6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDISER7_TXI0_SHIFT                (0u)
+#define INTC_ICDISER7_BRI1_SHIFT                (1u)
+#define INTC_ICDISER7_ERI1_SHIFT                (2u)
+#define INTC_ICDISER7_RXI1_SHIFT                (3u)
+#define INTC_ICDISER7_TXI1_SHIFT                (4u)
+#define INTC_ICDISER7_BRI2_SHIFT                (5u)
+#define INTC_ICDISER7_ERI2_SHIFT                (6u)
+#define INTC_ICDISER7_RXI2_SHIFT                (7u)
+#define INTC_ICDISER7_TXI2_SHIFT                (8u)
+#define INTC_ICDISER7_BRI3_SHIFT                (9u)
+#define INTC_ICDISER7_ERI3_SHIFT                (10u)
+#define INTC_ICDISER7_RXI3_SHIFT                (11u)
+#define INTC_ICDISER7_TXI3_SHIFT                (12u)
+#define INTC_ICDISER7_BRI4_SHIFT                (13u)
+#define INTC_ICDISER7_ERI4_SHIFT                (14u)
+#define INTC_ICDISER7_RXI4_SHIFT                (15u)
+#define INTC_ICDISER7_TXI4_SHIFT                (16u)
+#define INTC_ICDISER7_BRI5_SHIFT                (17u)
+#define INTC_ICDISER7_ERI5_SHIFT                (18u)
+#define INTC_ICDISER7_RXI5_SHIFT                (19u)
+#define INTC_ICDISER7_TXI5_SHIFT                (20u)
+#define INTC_ICDISER7_BRI6_SHIFT                (21u)
+#define INTC_ICDISER7_ERI6_SHIFT                (22u)
+#define INTC_ICDISER7_RXI6_SHIFT                (23u)
+#define INTC_ICDISER7_TXI6_SHIFT                (24u)
+#define INTC_ICDISER7_BRI7_SHIFT                (25u)
+#define INTC_ICDISER7_ERI7_SHIFT                (26u)
+#define INTC_ICDISER7_RXI7_SHIFT                (27u)
+#define INTC_ICDISER7_TXI7_SHIFT                (28u)
+#define INTC_ICDISER7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDISER7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDISER7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDISER8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDISER8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDISER8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDISER8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDISER8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDISER8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDISER8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDISER8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDISER8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDISER8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDISER8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDISER8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDISER8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDISER8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDISER8_SPEI0_SHIFT               (14u)
+#define INTC_ICDISER8_SPRI0_SHIFT               (15u)
+#define INTC_ICDISER8_SPTI0_SHIFT               (16u)
+#define INTC_ICDISER8_SPEI1_SHIFT               (17u)
+#define INTC_ICDISER8_SPRI1_SHIFT               (18u)
+#define INTC_ICDISER8_SPTI1_SHIFT               (19u)
+#define INTC_ICDISER8_SPEI2_SHIFT               (20u)
+#define INTC_ICDISER8_SPRI2_SHIFT               (21u)
+#define INTC_ICDISER8_SPTI2_SHIFT               (22u)
+#define INTC_ICDISER8_SPEI3_SHIFT               (23u)
+#define INTC_ICDISER8_SPRI3_SHIFT               (24u)
+#define INTC_ICDISER8_SPTI3_SHIFT               (25u)
+#define INTC_ICDISER8_SPEI4_SHIFT               (26u)
+#define INTC_ICDISER8_SPRI4_SHIFT               (27u)
+#define INTC_ICDISER8_SPTI4_SHIFT               (28u)
+#define INTC_ICDISER8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDISER8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDISER8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDISER9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDISER9_ISY_SHIFT                 (1u)
+#define INTC_ICDISER9_IERR_SHIFT                (2u)
+#define INTC_ICDISER9_ITARG_SHIFT               (3u)
+#define INTC_ICDISER9_ISEC_SHIFT                (4u)
+#define INTC_ICDISER9_IBUF_SHIFT                (5u)
+#define INTC_ICDISER9_IREADY_SHIFT              (6u)
+#define INTC_ICDISER9_FLSTE_SHIFT               (7u)
+#define INTC_ICDISER9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDISER9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDISER9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDISER9_MMC0_SHIFT                (11u)
+#define INTC_ICDISER9_MMC1_SHIFT                (12u)
+#define INTC_ICDISER9_MMC2_SHIFT                (13u)
+#define INTC_ICDISER9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDISER9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDISER9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDISER9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDISER9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDISER9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDISER9_ARM_SHIFT                 (20u)
+#define INTC_ICDISER9_PRD_SHIFT                 (21u)
+#define INTC_ICDISER9_CUP_SHIFT                 (22u)
+#define INTC_ICDISER9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDISER9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDISER9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDISER9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDISER9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDISER9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDISER9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDISER9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDISER9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDISER10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDISER10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDISER10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDISER10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDISER10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDISER10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDISER10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDISER10_DRC0_SHIFT               (7u)
+#define INTC_ICDISER10_DRC1_SHIFT               (8u)
+#define INTC_ICDISER10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDISER10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDISER10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDISER10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDISER10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDISER10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDISER10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDISER10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDISER10_ERI0_SHIFT               (27u)
+#define INTC_ICDISER10_RXI0_SHIFT               (28u)
+#define INTC_ICDISER10_TXI0_SHIFT               (29u)
+#define INTC_ICDISER10_TEI0_SHIFT               (30u)
+#define INTC_ICDISER10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDISER11_RXI1_SHIFT               (0u)
+#define INTC_ICDISER11_TXI1_SHIFT               (1u)
+#define INTC_ICDISER11_TEI1_SHIFT               (2u)
+#define INTC_ICDISER11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDISER11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDISER11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDISER11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDISER11_ETHERI_SHIFT             (7u)
+#define INTC_ICDISER11_CEUI_SHIFT               (12u)
+#define INTC_ICDISER11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDISER11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDISER11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDISER12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDISER12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDISER12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDISER12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDISER12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDISER12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDISER12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDISER12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDISER12_PRRI_SHIFT               (8u)
+#define INTC_ICDISER12_IFEI0_SHIFT              (9u)
+#define INTC_ICDISER12_OFFI0_SHIFT              (10u)
+#define INTC_ICDISER12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDISER12_IFEI1_SHIFT              (12u)
+#define INTC_ICDISER12_OFFI1_SHIFT              (13u)
+#define INTC_ICDISER12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDISER13_TINT0_SHIFT              (0u)
+#define INTC_ICDISER13_TINT1_SHIFT              (1u)
+#define INTC_ICDISER13_TINT2_SHIFT              (2u)
+#define INTC_ICDISER13_TINT3_SHIFT              (3u)
+#define INTC_ICDISER13_TINT4_SHIFT              (4u)
+#define INTC_ICDISER13_TINT5_SHIFT              (5u)
+#define INTC_ICDISER13_TINT6_SHIFT              (6u)
+#define INTC_ICDISER13_TINT7_SHIFT              (7u)
+#define INTC_ICDISER13_TINT8_SHIFT              (8u)
+#define INTC_ICDISER13_TINT9_SHIFT              (9u)
+#define INTC_ICDISER13_TINT10_SHIFT             (10u)
+#define INTC_ICDISER13_TINT11_SHIFT             (11u)
+#define INTC_ICDISER13_TINT12_SHIFT             (12u)
+#define INTC_ICDISER13_TINT13_SHIFT             (13u)
+#define INTC_ICDISER13_TINT14_SHIFT             (14u)
+#define INTC_ICDISER13_TINT15_SHIFT             (15u)
+#define INTC_ICDISER13_TINT16_SHIFT             (16u)
+#define INTC_ICDISER13_TINT17_SHIFT             (17u)
+#define INTC_ICDISER13_TINT18_SHIFT             (18u)
+#define INTC_ICDISER13_TINT19_SHIFT             (19u)
+#define INTC_ICDISER13_TINT20_SHIFT             (20u)
+#define INTC_ICDISER13_TINT21_SHIFT             (21u)
+#define INTC_ICDISER13_TINT22_SHIFT             (22u)
+#define INTC_ICDISER13_TINT23_SHIFT             (23u)
+#define INTC_ICDISER13_TINT24_SHIFT             (24u)
+#define INTC_ICDISER13_TINT25_SHIFT             (25u)
+#define INTC_ICDISER13_TINT26_SHIFT             (26u)
+#define INTC_ICDISER13_TINT27_SHIFT             (27u)
+#define INTC_ICDISER13_TINT28_SHIFT             (28u)
+#define INTC_ICDISER13_TINT29_SHIFT             (29u)
+#define INTC_ICDISER13_TINT30_SHIFT             (30u)
+#define INTC_ICDISER13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDISER14_TINT32_SHIFT             (0u)
+#define INTC_ICDISER14_TINT33_SHIFT             (1u)
+#define INTC_ICDISER14_TINT34_SHIFT             (2u)
+#define INTC_ICDISER14_TINT35_SHIFT             (3u)
+#define INTC_ICDISER14_TINT36_SHIFT             (4u)
+#define INTC_ICDISER14_TINT37_SHIFT             (5u)
+#define INTC_ICDISER14_TINT38_SHIFT             (6u)
+#define INTC_ICDISER14_TINT39_SHIFT             (7u)
+#define INTC_ICDISER14_TINT40_SHIFT             (8u)
+#define INTC_ICDISER14_TINT41_SHIFT             (9u)
+#define INTC_ICDISER14_TINT42_SHIFT             (10u)
+#define INTC_ICDISER14_TINT43_SHIFT             (11u)
+#define INTC_ICDISER14_TINT44_SHIFT             (12u)
+#define INTC_ICDISER14_TINT45_SHIFT             (13u)
+#define INTC_ICDISER14_TINT46_SHIFT             (14u)
+#define INTC_ICDISER14_TINT47_SHIFT             (15u)
+#define INTC_ICDISER14_TINT48_SHIFT             (16u)
+#define INTC_ICDISER14_TINT49_SHIFT             (17u)
+#define INTC_ICDISER14_TINT50_SHIFT             (18u)
+#define INTC_ICDISER14_TINT51_SHIFT             (19u)
+#define INTC_ICDISER14_TINT52_SHIFT             (20u)
+#define INTC_ICDISER14_TINT53_SHIFT             (21u)
+#define INTC_ICDISER14_TINT54_SHIFT             (22u)
+#define INTC_ICDISER14_TINT55_SHIFT             (23u)
+#define INTC_ICDISER14_TINT56_SHIFT             (24u)
+#define INTC_ICDISER14_TINT57_SHIFT             (25u)
+#define INTC_ICDISER14_TINT58_SHIFT             (26u)
+#define INTC_ICDISER14_TINT59_SHIFT             (27u)
+#define INTC_ICDISER14_TINT60_SHIFT             (28u)
+#define INTC_ICDISER14_TINT61_SHIFT             (29u)
+#define INTC_ICDISER14_TINT62_SHIFT             (30u)
+#define INTC_ICDISER14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDISER15_TINT64_SHIFT             (0u)
+#define INTC_ICDISER15_TINT65_SHIFT             (1u)
+#define INTC_ICDISER15_TINT66_SHIFT             (2u)
+#define INTC_ICDISER15_TINT67_SHIFT             (3u)
+#define INTC_ICDISER15_TINT68_SHIFT             (4u)
+#define INTC_ICDISER15_TINT69_SHIFT             (5u)
+#define INTC_ICDISER15_TINT70_SHIFT             (6u)
+#define INTC_ICDISER15_TINT71_SHIFT             (7u)
+#define INTC_ICDISER15_TINT72_SHIFT             (8u)
+#define INTC_ICDISER15_TINT73_SHIFT             (9u)
+#define INTC_ICDISER15_TINT74_SHIFT             (10u)
+#define INTC_ICDISER15_TINT75_SHIFT             (11u)
+#define INTC_ICDISER15_TINT76_SHIFT             (12u)
+#define INTC_ICDISER15_TINT77_SHIFT             (13u)
+#define INTC_ICDISER15_TINT78_SHIFT             (14u)
+#define INTC_ICDISER15_TINT79_SHIFT             (15u)
+#define INTC_ICDISER15_TINT80_SHIFT             (16u)
+#define INTC_ICDISER15_TINT81_SHIFT             (17u)
+#define INTC_ICDISER15_TINT82_SHIFT             (18u)
+#define INTC_ICDISER15_TINT83_SHIFT             (19u)
+#define INTC_ICDISER15_TINT84_SHIFT             (20u)
+#define INTC_ICDISER15_TINT85_SHIFT             (21u)
+#define INTC_ICDISER15_TINT86_SHIFT             (22u)
+#define INTC_ICDISER15_TINT87_SHIFT             (23u)
+#define INTC_ICDISER15_TINT88_SHIFT             (24u)
+#define INTC_ICDISER15_TINT89_SHIFT             (25u)
+#define INTC_ICDISER15_TINT90_SHIFT             (26u)
+#define INTC_ICDISER15_TINT91_SHIFT             (27u)
+#define INTC_ICDISER15_TINT92_SHIFT             (28u)
+#define INTC_ICDISER15_TINT93_SHIFT             (29u)
+#define INTC_ICDISER15_TINT94_SHIFT             (30u)
+#define INTC_ICDISER15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDISER16_TINT96_SHIFT             (0u)
+#define INTC_ICDISER16_TINT97_SHIFT             (1u)
+#define INTC_ICDISER16_TINT98_SHIFT             (2u)
+#define INTC_ICDISER16_TINT99_SHIFT             (3u)
+#define INTC_ICDISER16_TINT100_SHIFT            (4u)
+#define INTC_ICDISER16_TINT101_SHIFT            (5u)
+#define INTC_ICDISER16_TINT102_SHIFT            (6u)
+#define INTC_ICDISER16_TINT103_SHIFT            (7u)
+#define INTC_ICDISER16_TINT104_SHIFT            (8u)
+#define INTC_ICDISER16_TINT105_SHIFT            (9u)
+#define INTC_ICDISER16_TINT106_SHIFT            (10u)
+#define INTC_ICDISER16_TINT107_SHIFT            (11u)
+#define INTC_ICDISER16_TINT108_SHIFT            (12u)
+#define INTC_ICDISER16_TINT109_SHIFT            (13u)
+#define INTC_ICDISER16_TINT110_SHIFT            (14u)
+#define INTC_ICDISER16_TINT111_SHIFT            (15u)
+#define INTC_ICDISER16_TINT112_SHIFT            (16u)
+#define INTC_ICDISER16_TINT113_SHIFT            (17u)
+#define INTC_ICDISER16_TINT114_SHIFT            (18u)
+#define INTC_ICDISER16_TINT115_SHIFT            (19u)
+#define INTC_ICDISER16_TINT116_SHIFT            (20u)
+#define INTC_ICDISER16_TINT117_SHIFT            (21u)
+#define INTC_ICDISER16_TINT118_SHIFT            (22u)
+#define INTC_ICDISER16_TINT119_SHIFT            (23u)
+#define INTC_ICDISER16_TINT120_SHIFT            (24u)
+#define INTC_ICDISER16_TINT121_SHIFT            (25u)
+#define INTC_ICDISER16_TINT122_SHIFT            (26u)
+#define INTC_ICDISER16_TINT123_SHIFT            (27u)
+#define INTC_ICDISER16_TINT124_SHIFT            (28u)
+#define INTC_ICDISER16_TINT125_SHIFT            (29u)
+#define INTC_ICDISER16_TINT126_SHIFT            (30u)
+#define INTC_ICDISER16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDISER17_TINT128_SHIFT            (0u)
+#define INTC_ICDISER17_TINT129_SHIFT            (1u)
+#define INTC_ICDISER17_TINT130_SHIFT            (2u)
+#define INTC_ICDISER17_TINT131_SHIFT            (3u)
+#define INTC_ICDISER17_TINT132_SHIFT            (4u)
+#define INTC_ICDISER17_TINT133_SHIFT            (5u)
+#define INTC_ICDISER17_TINT134_SHIFT            (6u)
+#define INTC_ICDISER17_TINT135_SHIFT            (7u)
+#define INTC_ICDISER17_TINT136_SHIFT            (8u)
+#define INTC_ICDISER17_TINT137_SHIFT            (9u)
+#define INTC_ICDISER17_TINT138_SHIFT            (10u)
+#define INTC_ICDISER17_TINT139_SHIFT            (11u)
+#define INTC_ICDISER17_TINT140_SHIFT            (12u)
+#define INTC_ICDISER17_TINT141_SHIFT            (13u)
+#define INTC_ICDISER17_TINT142_SHIFT            (14u)
+#define INTC_ICDISER17_TINT143_SHIFT            (15u)
+#define INTC_ICDISER17_TINT144_SHIFT            (16u)
+#define INTC_ICDISER17_TINT145_SHIFT            (17u)
+#define INTC_ICDISER17_TINT146_SHIFT            (18u)
+#define INTC_ICDISER17_TINT147_SHIFT            (19u)
+#define INTC_ICDISER17_TINT148_SHIFT            (20u)
+#define INTC_ICDISER17_TINT149_SHIFT            (21u)
+#define INTC_ICDISER17_TINT150_SHIFT            (22u)
+#define INTC_ICDISER17_TINT151_SHIFT            (23u)
+#define INTC_ICDISER17_TINT152_SHIFT            (24u)
+#define INTC_ICDISER17_TINT153_SHIFT            (25u)
+#define INTC_ICDISER17_TINT154_SHIFT            (26u)
+#define INTC_ICDISER17_TINT155_SHIFT            (27u)
+#define INTC_ICDISER17_TINT156_SHIFT            (28u)
+#define INTC_ICDISER17_TINT157_SHIFT            (29u)
+#define INTC_ICDISER17_TINT158_SHIFT            (30u)
+#define INTC_ICDISER17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDISER18_TINT160_SHIFT            (0u)
+#define INTC_ICDISER18_TINT161_SHIFT            (1u)
+#define INTC_ICDISER18_TINT162_SHIFT            (2u)
+#define INTC_ICDISER18_TINT163_SHIFT            (3u)
+#define INTC_ICDISER18_TINT164_SHIFT            (4u)
+#define INTC_ICDISER18_TINT165_SHIFT            (5u)
+#define INTC_ICDISER18_TINT166_SHIFT            (6u)
+#define INTC_ICDISER18_TINT167_SHIFT            (7u)
+#define INTC_ICDISER18_TINT168_SHIFT            (8u)
+#define INTC_ICDISER18_TINT169_SHIFT            (9u)
+#define INTC_ICDISER18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDICER0_SW0_SHIFT                 (0u)
+#define INTC_ICDICER0_SW1_SHIFT                 (1u)
+#define INTC_ICDICER0_SW2_SHIFT                 (2u)
+#define INTC_ICDICER0_SW3_SHIFT                 (3u)
+#define INTC_ICDICER0_SW4_SHIFT                 (4u)
+#define INTC_ICDICER0_SW5_SHIFT                 (5u)
+#define INTC_ICDICER0_SW6_SHIFT                 (6u)
+#define INTC_ICDICER0_SW7_SHIFT                 (7u)
+#define INTC_ICDICER0_SW8_SHIFT                 (8u)
+#define INTC_ICDICER0_SW9_SHIFT                 (9u)
+#define INTC_ICDICER0_SW10_SHIFT                (10u)
+#define INTC_ICDICER0_SW11_SHIFT                (11u)
+#define INTC_ICDICER0_SW12_SHIFT                (12u)
+#define INTC_ICDICER0_SW13_SHIFT                (13u)
+#define INTC_ICDICER0_SW14_SHIFT                (14u)
+#define INTC_ICDICER0_SW15_SHIFT                (15u)
+#define INTC_ICDICER0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDICER0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDICER0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDICER0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDICER1_IRQ0_SHIFT                (0u)
+#define INTC_ICDICER1_IRQ1_SHIFT                (1u)
+#define INTC_ICDICER1_IRQ2_SHIFT                (2u)
+#define INTC_ICDICER1_IRQ3_SHIFT                (3u)
+#define INTC_ICDICER1_IRQ4_SHIFT                (4u)
+#define INTC_ICDICER1_IRQ5_SHIFT                (5u)
+#define INTC_ICDICER1_IRQ6_SHIFT                (6u)
+#define INTC_ICDICER1_IRQ7_SHIFT                (7u)
+#define INTC_ICDICER1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDICER1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDICER1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDICER1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDICER1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDICER1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDICER1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDICER1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDICER1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDICER1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDICER1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDICER1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDICER1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDICER1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDICER1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDICER1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDICER1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDICER1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDICER2_USBI0_SHIFT               (9u)
+#define INTC_ICDICER2_USBI1_SHIFT               (10u)
+#define INTC_ICDICER2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDICER2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDICER2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDICER2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDICER2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDICER2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDICER2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDICER2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDICER2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDICER2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDICER2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDICER2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDICER2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDICER2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDICER2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDICER2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDICER2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDICER2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDICER2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDICER2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDICER2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDICER3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDICER3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDICER3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDICER3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDICER3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDICER3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDICER3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDICER3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDICER3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDICER3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDICER3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDICER3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDICER3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDICER3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDICER3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDICER3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDICER3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDICER3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDICER3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDICER3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDICER3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDICER3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDICER3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDICER3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDICER3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDICER3_IMRDI_SHIFT               (27u)
+#define INTC_ICDICER3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDICER3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDICER3_JEDI_SHIFT                (30u)
+#define INTC_ICDICER3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDICER4_CMP0_SHIFT                (0u)
+#define INTC_ICDICER4_CMP1_SHIFT                (1u)
+#define INTC_ICDICER4_INT0_SHIFT                (2u)
+#define INTC_ICDICER4_INT1_SHIFT                (3u)
+#define INTC_ICDICER4_INT2_SHIFT                (4u)
+#define INTC_ICDICER4_INT3_SHIFT                (5u)
+#define INTC_ICDICER4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDICER4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDICER4_CMI_SHIFT                 (8u)
+#define INTC_ICDICER4_WTOUT_SHIFT               (9u)
+#define INTC_ICDICER4_ITI_SHIFT                 (10u)
+#define INTC_ICDICER4_TGI0A_SHIFT               (11u)
+#define INTC_ICDICER4_TGI0B_SHIFT               (12u)
+#define INTC_ICDICER4_TGI0C_SHIFT               (13u)
+#define INTC_ICDICER4_TGI0D_SHIFT               (14u)
+#define INTC_ICDICER4_TGI0V_SHIFT               (15u)
+#define INTC_ICDICER4_TGI0E_SHIFT               (16u)
+#define INTC_ICDICER4_TGI0F_SHIFT               (17u)
+#define INTC_ICDICER4_TGI1A_SHIFT               (18u)
+#define INTC_ICDICER4_TGI1B_SHIFT               (19u)
+#define INTC_ICDICER4_TGI1V_SHIFT               (20u)
+#define INTC_ICDICER4_TGI1U_SHIFT               (21u)
+#define INTC_ICDICER4_TGI2A_SHIFT               (22u)
+#define INTC_ICDICER4_TGI2B_SHIFT               (23u)
+#define INTC_ICDICER4_TGI2V_SHIFT               (24u)
+#define INTC_ICDICER4_TGI2U_SHIFT               (25u)
+#define INTC_ICDICER4_TGI3A_SHIFT               (26u)
+#define INTC_ICDICER4_TGI3B_SHIFT               (27u)
+#define INTC_ICDICER4_TGI3C_SHIFT               (28u)
+#define INTC_ICDICER4_TGI3D_SHIFT               (29u)
+#define INTC_ICDICER4_TGI3V_SHIFT               (30u)
+#define INTC_ICDICER4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDICER5_TGI4B_SHIFT               (0u)
+#define INTC_ICDICER5_TGI4C_SHIFT               (1u)
+#define INTC_ICDICER5_TGI4D_SHIFT               (2u)
+#define INTC_ICDICER5_TGI4V_SHIFT               (3u)
+#define INTC_ICDICER5_CMI1_SHIFT                (4u)
+#define INTC_ICDICER5_CMI2_SHIFT                (5u)
+#define INTC_ICDICER5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDICER5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDICER5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDICER5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDICER5_ADI_SHIFT                 (10u)
+#define INTC_ICDICER5_LMTI_SHIFT                (11u)
+#define INTC_ICDICER5_SSII0_SHIFT               (12u)
+#define INTC_ICDICER5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDICER5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDICER5_SSII1_SHIFT               (15u)
+#define INTC_ICDICER5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDICER5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDICER5_SSII2_SHIFT               (18u)
+#define INTC_ICDICER5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDICER5_SSII3_SHIFT               (20u)
+#define INTC_ICDICER5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDICER5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDICER5_SSII4_SHIFT               (23u)
+#define INTC_ICDICER5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDICER5_SSII5_SHIFT               (25u)
+#define INTC_ICDICER5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDICER5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDICER5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDICER5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDICER5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDICER5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDICER6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDICER6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDICER6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDICER6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDICER6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDICER6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDICER6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDICER6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDICER6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDICER6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDICER6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDICER6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDICER6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDICER6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDICER6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDICER6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDICER6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDICER6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDICER6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDICER6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDICER6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDICER6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDICER6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDICER6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDICER6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDICER6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDICER6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDICER6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDICER6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDICER6_BRI0_SHIFT                (29u)
+#define INTC_ICDICER6_ERI0_SHIFT                (30u)
+#define INTC_ICDICER6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDICER7_TXI0_SHIFT                (0u)
+#define INTC_ICDICER7_BRI1_SHIFT                (1u)
+#define INTC_ICDICER7_ERI1_SHIFT                (2u)
+#define INTC_ICDICER7_RXI1_SHIFT                (3u)
+#define INTC_ICDICER7_TXI1_SHIFT                (4u)
+#define INTC_ICDICER7_BRI2_SHIFT                (5u)
+#define INTC_ICDICER7_ERI2_SHIFT                (6u)
+#define INTC_ICDICER7_RXI2_SHIFT                (7u)
+#define INTC_ICDICER7_TXI2_SHIFT                (8u)
+#define INTC_ICDICER7_BRI3_SHIFT                (9u)
+#define INTC_ICDICER7_ERI3_SHIFT                (10u)
+#define INTC_ICDICER7_RXI3_SHIFT                (11u)
+#define INTC_ICDICER7_TXI3_SHIFT                (12u)
+#define INTC_ICDICER7_BRI4_SHIFT                (13u)
+#define INTC_ICDICER7_ERI4_SHIFT                (14u)
+#define INTC_ICDICER7_RXI4_SHIFT                (15u)
+#define INTC_ICDICER7_TXI4_SHIFT                (16u)
+#define INTC_ICDICER7_BRI5_SHIFT                (17u)
+#define INTC_ICDICER7_ERI5_SHIFT                (18u)
+#define INTC_ICDICER7_RXI5_SHIFT                (19u)
+#define INTC_ICDICER7_TXI5_SHIFT                (20u)
+#define INTC_ICDICER7_BRI6_SHIFT                (21u)
+#define INTC_ICDICER7_ERI6_SHIFT                (22u)
+#define INTC_ICDICER7_RXI6_SHIFT                (23u)
+#define INTC_ICDICER7_TXI6_SHIFT                (24u)
+#define INTC_ICDICER7_BRI7_SHIFT                (25u)
+#define INTC_ICDICER7_ERI7_SHIFT                (26u)
+#define INTC_ICDICER7_RXI7_SHIFT                (27u)
+#define INTC_ICDICER7_TXI7_SHIFT                (28u)
+#define INTC_ICDICER7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDICER7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDICER7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDICER8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDICER8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDICER8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDICER8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDICER8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDICER8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDICER8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDICER8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDICER8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDICER8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDICER8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDICER8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDICER8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDICER8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDICER8_SPEI0_SHIFT               (14u)
+#define INTC_ICDICER8_SPRI0_SHIFT               (15u)
+#define INTC_ICDICER8_SPTI0_SHIFT               (16u)
+#define INTC_ICDICER8_SPEI1_SHIFT               (17u)
+#define INTC_ICDICER8_SPRI1_SHIFT               (18u)
+#define INTC_ICDICER8_SPTI1_SHIFT               (19u)
+#define INTC_ICDICER8_SPEI2_SHIFT               (20u)
+#define INTC_ICDICER8_SPRI2_SHIFT               (21u)
+#define INTC_ICDICER8_SPTI2_SHIFT               (22u)
+#define INTC_ICDICER8_SPEI3_SHIFT               (23u)
+#define INTC_ICDICER8_SPRI3_SHIFT               (24u)
+#define INTC_ICDICER8_SPTI3_SHIFT               (25u)
+#define INTC_ICDICER8_SPEI4_SHIFT               (26u)
+#define INTC_ICDICER8_SPRI4_SHIFT               (27u)
+#define INTC_ICDICER8_SPTI4_SHIFT               (28u)
+#define INTC_ICDICER8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDICER8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDICER8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDICER9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDICER9_ISY_SHIFT                 (1u)
+#define INTC_ICDICER9_IERR_SHIFT                (2u)
+#define INTC_ICDICER9_ITARG_SHIFT               (3u)
+#define INTC_ICDICER9_ISEC_SHIFT                (4u)
+#define INTC_ICDICER9_IBUF_SHIFT                (5u)
+#define INTC_ICDICER9_IREADY_SHIFT              (6u)
+#define INTC_ICDICER9_FLSTE_SHIFT               (7u)
+#define INTC_ICDICER9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDICER9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDICER9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDICER9_MMC0_SHIFT                (11u)
+#define INTC_ICDICER9_MMC1_SHIFT                (12u)
+#define INTC_ICDICER9_MMC2_SHIFT                (13u)
+#define INTC_ICDICER9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDICER9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDICER9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDICER9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDICER9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDICER9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDICER9_ARM_SHIFT                 (20u)
+#define INTC_ICDICER9_PRD_SHIFT                 (21u)
+#define INTC_ICDICER9_CUP_SHIFT                 (22u)
+#define INTC_ICDICER9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDICER9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDICER9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDICER9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDICER9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDICER9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDICER9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDICER9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDICER9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDICER10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDICER10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDICER10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDICER10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDICER10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDICER10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDICER10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDICER10_DRC0_SHIFT               (7u)
+#define INTC_ICDICER10_DRC1_SHIFT               (8u)
+#define INTC_ICDICER10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDICER10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDICER10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDICER10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDICER10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDICER10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDICER10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDICER10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDICER10_ERI0_SHIFT               (27u)
+#define INTC_ICDICER10_RXI0_SHIFT               (28u)
+#define INTC_ICDICER10_TXI0_SHIFT               (29u)
+#define INTC_ICDICER10_TEI0_SHIFT               (30u)
+#define INTC_ICDICER10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDICER11_RXI1_SHIFT               (0u)
+#define INTC_ICDICER11_TXI1_SHIFT               (1u)
+#define INTC_ICDICER11_TEI1_SHIFT               (2u)
+#define INTC_ICDICER11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDICER11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDICER11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDICER11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDICER11_ETHERI_SHIFT             (7u)
+#define INTC_ICDICER11_CEUI_SHIFT               (12u)
+#define INTC_ICDICER11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDICER11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDICER11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDICER12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDICER12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDICER12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDICER12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDICER12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDICER12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDICER12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDICER12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDICER12_PRRI_SHIFT               (8u)
+#define INTC_ICDICER12_IFEI0_SHIFT              (9u)
+#define INTC_ICDICER12_OFFI0_SHIFT              (10u)
+#define INTC_ICDICER12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDICER12_IFEI1_SHIFT              (12u)
+#define INTC_ICDICER12_OFFI1_SHIFT              (13u)
+#define INTC_ICDICER12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDICER13_TINT0_SHIFT              (0u)
+#define INTC_ICDICER13_TINT1_SHIFT              (1u)
+#define INTC_ICDICER13_TINT2_SHIFT              (2u)
+#define INTC_ICDICER13_TINT3_SHIFT              (3u)
+#define INTC_ICDICER13_TINT4_SHIFT              (4u)
+#define INTC_ICDICER13_TINT5_SHIFT              (5u)
+#define INTC_ICDICER13_TINT6_SHIFT              (6u)
+#define INTC_ICDICER13_TINT7_SHIFT              (7u)
+#define INTC_ICDICER13_TINT8_SHIFT              (8u)
+#define INTC_ICDICER13_TINT9_SHIFT              (9u)
+#define INTC_ICDICER13_TINT10_SHIFT             (10u)
+#define INTC_ICDICER13_TINT11_SHIFT             (11u)
+#define INTC_ICDICER13_TINT12_SHIFT             (12u)
+#define INTC_ICDICER13_TINT13_SHIFT             (13u)
+#define INTC_ICDICER13_TINT14_SHIFT             (14u)
+#define INTC_ICDICER13_TINT15_SHIFT             (15u)
+#define INTC_ICDICER13_TINT16_SHIFT             (16u)
+#define INTC_ICDICER13_TINT17_SHIFT             (17u)
+#define INTC_ICDICER13_TINT18_SHIFT             (18u)
+#define INTC_ICDICER13_TINT19_SHIFT             (19u)
+#define INTC_ICDICER13_TINT20_SHIFT             (20u)
+#define INTC_ICDICER13_TINT21_SHIFT             (21u)
+#define INTC_ICDICER13_TINT22_SHIFT             (22u)
+#define INTC_ICDICER13_TINT23_SHIFT             (23u)
+#define INTC_ICDICER13_TINT24_SHIFT             (24u)
+#define INTC_ICDICER13_TINT25_SHIFT             (25u)
+#define INTC_ICDICER13_TINT26_SHIFT             (26u)
+#define INTC_ICDICER13_TINT27_SHIFT             (27u)
+#define INTC_ICDICER13_TINT28_SHIFT             (28u)
+#define INTC_ICDICER13_TINT29_SHIFT             (29u)
+#define INTC_ICDICER13_TINT30_SHIFT             (30u)
+#define INTC_ICDICER13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDICER14_TINT32_SHIFT             (0u)
+#define INTC_ICDICER14_TINT33_SHIFT             (1u)
+#define INTC_ICDICER14_TINT34_SHIFT             (2u)
+#define INTC_ICDICER14_TINT35_SHIFT             (3u)
+#define INTC_ICDICER14_TINT36_SHIFT             (4u)
+#define INTC_ICDICER14_TINT37_SHIFT             (5u)
+#define INTC_ICDICER14_TINT38_SHIFT             (6u)
+#define INTC_ICDICER14_TINT39_SHIFT             (7u)
+#define INTC_ICDICER14_TINT40_SHIFT             (8u)
+#define INTC_ICDICER14_TINT41_SHIFT             (9u)
+#define INTC_ICDICER14_TINT42_SHIFT             (10u)
+#define INTC_ICDICER14_TINT43_SHIFT             (11u)
+#define INTC_ICDICER14_TINT44_SHIFT             (12u)
+#define INTC_ICDICER14_TINT45_SHIFT             (13u)
+#define INTC_ICDICER14_TINT46_SHIFT             (14u)
+#define INTC_ICDICER14_TINT47_SHIFT             (15u)
+#define INTC_ICDICER14_TINT48_SHIFT             (16u)
+#define INTC_ICDICER14_TINT49_SHIFT             (17u)
+#define INTC_ICDICER14_TINT50_SHIFT             (18u)
+#define INTC_ICDICER14_TINT51_SHIFT             (19u)
+#define INTC_ICDICER14_TINT52_SHIFT             (20u)
+#define INTC_ICDICER14_TINT53_SHIFT             (21u)
+#define INTC_ICDICER14_TINT54_SHIFT             (22u)
+#define INTC_ICDICER14_TINT55_SHIFT             (23u)
+#define INTC_ICDICER14_TINT56_SHIFT             (24u)
+#define INTC_ICDICER14_TINT57_SHIFT             (25u)
+#define INTC_ICDICER14_TINT58_SHIFT             (26u)
+#define INTC_ICDICER14_TINT59_SHIFT             (27u)
+#define INTC_ICDICER14_TINT60_SHIFT             (28u)
+#define INTC_ICDICER14_TINT61_SHIFT             (29u)
+#define INTC_ICDICER14_TINT62_SHIFT             (30u)
+#define INTC_ICDICER14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDICER15_TINT64_SHIFT             (0u)
+#define INTC_ICDICER15_TINT65_SHIFT             (1u)
+#define INTC_ICDICER15_TINT66_SHIFT             (2u)
+#define INTC_ICDICER15_TINT67_SHIFT             (3u)
+#define INTC_ICDICER15_TINT68_SHIFT             (4u)
+#define INTC_ICDICER15_TINT69_SHIFT             (5u)
+#define INTC_ICDICER15_TINT70_SHIFT             (6u)
+#define INTC_ICDICER15_TINT71_SHIFT             (7u)
+#define INTC_ICDICER15_TINT72_SHIFT             (8u)
+#define INTC_ICDICER15_TINT73_SHIFT             (9u)
+#define INTC_ICDICER15_TINT74_SHIFT             (10u)
+#define INTC_ICDICER15_TINT75_SHIFT             (11u)
+#define INTC_ICDICER15_TINT76_SHIFT             (12u)
+#define INTC_ICDICER15_TINT77_SHIFT             (13u)
+#define INTC_ICDICER15_TINT78_SHIFT             (14u)
+#define INTC_ICDICER15_TINT79_SHIFT             (15u)
+#define INTC_ICDICER15_TINT80_SHIFT             (16u)
+#define INTC_ICDICER15_TINT81_SHIFT             (17u)
+#define INTC_ICDICER15_TINT82_SHIFT             (18u)
+#define INTC_ICDICER15_TINT83_SHIFT             (19u)
+#define INTC_ICDICER15_TINT84_SHIFT             (20u)
+#define INTC_ICDICER15_TINT85_SHIFT             (21u)
+#define INTC_ICDICER15_TINT86_SHIFT             (22u)
+#define INTC_ICDICER15_TINT87_SHIFT             (23u)
+#define INTC_ICDICER15_TINT88_SHIFT             (24u)
+#define INTC_ICDICER15_TINT89_SHIFT             (25u)
+#define INTC_ICDICER15_TINT90_SHIFT             (26u)
+#define INTC_ICDICER15_TINT91_SHIFT             (27u)
+#define INTC_ICDICER15_TINT92_SHIFT             (28u)
+#define INTC_ICDICER15_TINT93_SHIFT             (29u)
+#define INTC_ICDICER15_TINT94_SHIFT             (30u)
+#define INTC_ICDICER15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDICER16_TINT96_SHIFT             (0u)
+#define INTC_ICDICER16_TINT97_SHIFT             (1u)
+#define INTC_ICDICER16_TINT98_SHIFT             (2u)
+#define INTC_ICDICER16_TINT99_SHIFT             (3u)
+#define INTC_ICDICER16_TINT100_SHIFT            (4u)
+#define INTC_ICDICER16_TINT101_SHIFT            (5u)
+#define INTC_ICDICER16_TINT102_SHIFT            (6u)
+#define INTC_ICDICER16_TINT103_SHIFT            (7u)
+#define INTC_ICDICER16_TINT104_SHIFT            (8u)
+#define INTC_ICDICER16_TINT105_SHIFT            (9u)
+#define INTC_ICDICER16_TINT106_SHIFT            (10u)
+#define INTC_ICDICER16_TINT107_SHIFT            (11u)
+#define INTC_ICDICER16_TINT108_SHIFT            (12u)
+#define INTC_ICDICER16_TINT109_SHIFT            (13u)
+#define INTC_ICDICER16_TINT110_SHIFT            (14u)
+#define INTC_ICDICER16_TINT111_SHIFT            (15u)
+#define INTC_ICDICER16_TINT112_SHIFT            (16u)
+#define INTC_ICDICER16_TINT113_SHIFT            (17u)
+#define INTC_ICDICER16_TINT114_SHIFT            (18u)
+#define INTC_ICDICER16_TINT115_SHIFT            (19u)
+#define INTC_ICDICER16_TINT116_SHIFT            (20u)
+#define INTC_ICDICER16_TINT117_SHIFT            (21u)
+#define INTC_ICDICER16_TINT118_SHIFT            (22u)
+#define INTC_ICDICER16_TINT119_SHIFT            (23u)
+#define INTC_ICDICER16_TINT120_SHIFT            (24u)
+#define INTC_ICDICER16_TINT121_SHIFT            (25u)
+#define INTC_ICDICER16_TINT122_SHIFT            (26u)
+#define INTC_ICDICER16_TINT123_SHIFT            (27u)
+#define INTC_ICDICER16_TINT124_SHIFT            (28u)
+#define INTC_ICDICER16_TINT125_SHIFT            (29u)
+#define INTC_ICDICER16_TINT126_SHIFT            (30u)
+#define INTC_ICDICER16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDICER17_TINT128_SHIFT            (0u)
+#define INTC_ICDICER17_TINT129_SHIFT            (1u)
+#define INTC_ICDICER17_TINT130_SHIFT            (2u)
+#define INTC_ICDICER17_TINT131_SHIFT            (3u)
+#define INTC_ICDICER17_TINT132_SHIFT            (4u)
+#define INTC_ICDICER17_TINT133_SHIFT            (5u)
+#define INTC_ICDICER17_TINT134_SHIFT            (6u)
+#define INTC_ICDICER17_TINT135_SHIFT            (7u)
+#define INTC_ICDICER17_TINT136_SHIFT            (8u)
+#define INTC_ICDICER17_TINT137_SHIFT            (9u)
+#define INTC_ICDICER17_TINT138_SHIFT            (10u)
+#define INTC_ICDICER17_TINT139_SHIFT            (11u)
+#define INTC_ICDICER17_TINT140_SHIFT            (12u)
+#define INTC_ICDICER17_TINT141_SHIFT            (13u)
+#define INTC_ICDICER17_TINT142_SHIFT            (14u)
+#define INTC_ICDICER17_TINT143_SHIFT            (15u)
+#define INTC_ICDICER17_TINT144_SHIFT            (16u)
+#define INTC_ICDICER17_TINT145_SHIFT            (17u)
+#define INTC_ICDICER17_TINT146_SHIFT            (18u)
+#define INTC_ICDICER17_TINT147_SHIFT            (19u)
+#define INTC_ICDICER17_TINT148_SHIFT            (20u)
+#define INTC_ICDICER17_TINT149_SHIFT            (21u)
+#define INTC_ICDICER17_TINT150_SHIFT            (22u)
+#define INTC_ICDICER17_TINT151_SHIFT            (23u)
+#define INTC_ICDICER17_TINT152_SHIFT            (24u)
+#define INTC_ICDICER17_TINT153_SHIFT            (25u)
+#define INTC_ICDICER17_TINT154_SHIFT            (26u)
+#define INTC_ICDICER17_TINT155_SHIFT            (27u)
+#define INTC_ICDICER17_TINT156_SHIFT            (28u)
+#define INTC_ICDICER17_TINT157_SHIFT            (29u)
+#define INTC_ICDICER17_TINT158_SHIFT            (30u)
+#define INTC_ICDICER17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDICER18_TINT160_SHIFT            (0u)
+#define INTC_ICDICER18_TINT161_SHIFT            (1u)
+#define INTC_ICDICER18_TINT162_SHIFT            (2u)
+#define INTC_ICDICER18_TINT163_SHIFT            (3u)
+#define INTC_ICDICER18_TINT164_SHIFT            (4u)
+#define INTC_ICDICER18_TINT165_SHIFT            (5u)
+#define INTC_ICDICER18_TINT166_SHIFT            (6u)
+#define INTC_ICDICER18_TINT167_SHIFT            (7u)
+#define INTC_ICDICER18_TINT168_SHIFT            (8u)
+#define INTC_ICDICER18_TINT169_SHIFT            (9u)
+#define INTC_ICDICER18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDISPR0_SW0_SHIFT                 (0u)
+#define INTC_ICDISPR0_SW1_SHIFT                 (1u)
+#define INTC_ICDISPR0_SW2_SHIFT                 (2u)
+#define INTC_ICDISPR0_SW3_SHIFT                 (3u)
+#define INTC_ICDISPR0_SW4_SHIFT                 (4u)
+#define INTC_ICDISPR0_SW5_SHIFT                 (5u)
+#define INTC_ICDISPR0_SW6_SHIFT                 (6u)
+#define INTC_ICDISPR0_SW7_SHIFT                 (7u)
+#define INTC_ICDISPR0_SW8_SHIFT                 (8u)
+#define INTC_ICDISPR0_SW9_SHIFT                 (9u)
+#define INTC_ICDISPR0_SW10_SHIFT                (10u)
+#define INTC_ICDISPR0_SW11_SHIFT                (11u)
+#define INTC_ICDISPR0_SW12_SHIFT                (12u)
+#define INTC_ICDISPR0_SW13_SHIFT                (13u)
+#define INTC_ICDISPR0_SW14_SHIFT                (14u)
+#define INTC_ICDISPR0_SW15_SHIFT                (15u)
+#define INTC_ICDISPR0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDISPR0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDISPR0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDISPR0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDISPR1_IRQ0_SHIFT                (0u)
+#define INTC_ICDISPR1_IRQ1_SHIFT                (1u)
+#define INTC_ICDISPR1_IRQ2_SHIFT                (2u)
+#define INTC_ICDISPR1_IRQ3_SHIFT                (3u)
+#define INTC_ICDISPR1_IRQ4_SHIFT                (4u)
+#define INTC_ICDISPR1_IRQ5_SHIFT                (5u)
+#define INTC_ICDISPR1_IRQ6_SHIFT                (6u)
+#define INTC_ICDISPR1_IRQ7_SHIFT                (7u)
+#define INTC_ICDISPR1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDISPR1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDISPR1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDISPR1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDISPR1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDISPR1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDISPR1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDISPR1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDISPR1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDISPR1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDISPR1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDISPR1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDISPR1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDISPR1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDISPR1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDISPR1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDISPR1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDISPR1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDISPR2_USBI0_SHIFT               (9u)
+#define INTC_ICDISPR2_USBI1_SHIFT               (10u)
+#define INTC_ICDISPR2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDISPR2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDISPR2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDISPR2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDISPR2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDISPR2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDISPR2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDISPR2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDISPR2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDISPR2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDISPR2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDISPR2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDISPR2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDISPR2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDISPR2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDISPR2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDISPR2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDISPR2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDISPR2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDISPR2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDISPR2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDISPR3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDISPR3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDISPR3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDISPR3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDISPR3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDISPR3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDISPR3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDISPR3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDISPR3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDISPR3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDISPR3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDISPR3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDISPR3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDISPR3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDISPR3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDISPR3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDISPR3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDISPR3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDISPR3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDISPR3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDISPR3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDISPR3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDISPR3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDISPR3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDISPR3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDISPR3_IMRDI_SHIFT               (27u)
+#define INTC_ICDISPR3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDISPR3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDISPR3_JEDI_SHIFT                (30u)
+#define INTC_ICDISPR3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDISPR4_CMP0_SHIFT                (0u)
+#define INTC_ICDISPR4_CMP1_SHIFT                (1u)
+#define INTC_ICDISPR4_INT0_SHIFT                (2u)
+#define INTC_ICDISPR4_INT1_SHIFT                (3u)
+#define INTC_ICDISPR4_INT2_SHIFT                (4u)
+#define INTC_ICDISPR4_INT3_SHIFT                (5u)
+#define INTC_ICDISPR4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDISPR4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDISPR4_CMI_SHIFT                 (8u)
+#define INTC_ICDISPR4_WTOUT_SHIFT               (9u)
+#define INTC_ICDISPR4_ITI_SHIFT                 (10u)
+#define INTC_ICDISPR4_TGI0A_SHIFT               (11u)
+#define INTC_ICDISPR4_TGI0B_SHIFT               (12u)
+#define INTC_ICDISPR4_TGI0C_SHIFT               (13u)
+#define INTC_ICDISPR4_TGI0D_SHIFT               (14u)
+#define INTC_ICDISPR4_TGI0V_SHIFT               (15u)
+#define INTC_ICDISPR4_TGI0E_SHIFT               (16u)
+#define INTC_ICDISPR4_TGI0F_SHIFT               (17u)
+#define INTC_ICDISPR4_TGI1A_SHIFT               (18u)
+#define INTC_ICDISPR4_TGI1B_SHIFT               (19u)
+#define INTC_ICDISPR4_TGI1V_SHIFT               (20u)
+#define INTC_ICDISPR4_TGI1U_SHIFT               (21u)
+#define INTC_ICDISPR4_TGI2A_SHIFT               (22u)
+#define INTC_ICDISPR4_TGI2B_SHIFT               (23u)
+#define INTC_ICDISPR4_TGI2V_SHIFT               (24u)
+#define INTC_ICDISPR4_TGI2U_SHIFT               (25u)
+#define INTC_ICDISPR4_TGI3A_SHIFT               (26u)
+#define INTC_ICDISPR4_TGI3B_SHIFT               (27u)
+#define INTC_ICDISPR4_TGI3C_SHIFT               (28u)
+#define INTC_ICDISPR4_TGI3D_SHIFT               (29u)
+#define INTC_ICDISPR4_TGI3V_SHIFT               (30u)
+#define INTC_ICDISPR4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDISPR5_TGI4B_SHIFT               (0u)
+#define INTC_ICDISPR5_TGI4C_SHIFT               (1u)
+#define INTC_ICDISPR5_TGI4D_SHIFT               (2u)
+#define INTC_ICDISPR5_TGI4V_SHIFT               (3u)
+#define INTC_ICDISPR5_CMI1_SHIFT                (4u)
+#define INTC_ICDISPR5_CMI2_SHIFT                (5u)
+#define INTC_ICDISPR5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDISPR5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDISPR5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDISPR5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDISPR5_ADI_SHIFT                 (10u)
+#define INTC_ICDISPR5_LMTI_SHIFT                (11u)
+#define INTC_ICDISPR5_SSII0_SHIFT               (12u)
+#define INTC_ICDISPR5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDISPR5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDISPR5_SSII1_SHIFT               (15u)
+#define INTC_ICDISPR5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDISPR5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDISPR5_SSII2_SHIFT               (18u)
+#define INTC_ICDISPR5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDISPR5_SSII3_SHIFT               (20u)
+#define INTC_ICDISPR5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDISPR5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDISPR5_SSII4_SHIFT               (23u)
+#define INTC_ICDISPR5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDISPR5_SSII5_SHIFT               (25u)
+#define INTC_ICDISPR5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDISPR5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDISPR5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDISPR5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDISPR5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDISPR5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDISPR6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDISPR6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDISPR6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDISPR6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDISPR6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDISPR6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDISPR6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDISPR6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDISPR6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDISPR6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDISPR6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDISPR6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDISPR6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDISPR6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDISPR6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDISPR6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDISPR6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDISPR6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDISPR6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDISPR6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDISPR6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDISPR6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDISPR6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDISPR6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDISPR6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDISPR6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDISPR6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDISPR6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDISPR6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDISPR6_BRI0_SHIFT                (29u)
+#define INTC_ICDISPR6_ERI0_SHIFT                (30u)
+#define INTC_ICDISPR6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDISPR7_TXI0_SHIFT                (0u)
+#define INTC_ICDISPR7_BRI1_SHIFT                (1u)
+#define INTC_ICDISPR7_ERI1_SHIFT                (2u)
+#define INTC_ICDISPR7_RXI1_SHIFT                (3u)
+#define INTC_ICDISPR7_TXI1_SHIFT                (4u)
+#define INTC_ICDISPR7_BRI2_SHIFT                (5u)
+#define INTC_ICDISPR7_ERI2_SHIFT                (6u)
+#define INTC_ICDISPR7_RXI2_SHIFT                (7u)
+#define INTC_ICDISPR7_TXI2_SHIFT                (8u)
+#define INTC_ICDISPR7_BRI3_SHIFT                (9u)
+#define INTC_ICDISPR7_ERI3_SHIFT                (10u)
+#define INTC_ICDISPR7_RXI3_SHIFT                (11u)
+#define INTC_ICDISPR7_TXI3_SHIFT                (12u)
+#define INTC_ICDISPR7_BRI4_SHIFT                (13u)
+#define INTC_ICDISPR7_ERI4_SHIFT                (14u)
+#define INTC_ICDISPR7_RXI4_SHIFT                (15u)
+#define INTC_ICDISPR7_TXI4_SHIFT                (16u)
+#define INTC_ICDISPR7_BRI5_SHIFT                (17u)
+#define INTC_ICDISPR7_ERI5_SHIFT                (18u)
+#define INTC_ICDISPR7_RXI5_SHIFT                (19u)
+#define INTC_ICDISPR7_TXI5_SHIFT                (20u)
+#define INTC_ICDISPR7_BRI6_SHIFT                (21u)
+#define INTC_ICDISPR7_ERI6_SHIFT                (22u)
+#define INTC_ICDISPR7_RXI6_SHIFT                (23u)
+#define INTC_ICDISPR7_TXI6_SHIFT                (24u)
+#define INTC_ICDISPR7_BRI7_SHIFT                (25u)
+#define INTC_ICDISPR7_ERI7_SHIFT                (26u)
+#define INTC_ICDISPR7_RXI7_SHIFT                (27u)
+#define INTC_ICDISPR7_TXI7_SHIFT                (28u)
+#define INTC_ICDISPR7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDISPR7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDISPR7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDISPR8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDISPR8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDISPR8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDISPR8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDISPR8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDISPR8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDISPR8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDISPR8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDISPR8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDISPR8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDISPR8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDISPR8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDISPR8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDISPR8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDISPR8_SPEI0_SHIFT               (14u)
+#define INTC_ICDISPR8_SPRI0_SHIFT               (15u)
+#define INTC_ICDISPR8_SPTI0_SHIFT               (16u)
+#define INTC_ICDISPR8_SPEI1_SHIFT               (17u)
+#define INTC_ICDISPR8_SPRI1_SHIFT               (18u)
+#define INTC_ICDISPR8_SPTI1_SHIFT               (19u)
+#define INTC_ICDISPR8_SPEI2_SHIFT               (20u)
+#define INTC_ICDISPR8_SPRI2_SHIFT               (21u)
+#define INTC_ICDISPR8_SPTI2_SHIFT               (22u)
+#define INTC_ICDISPR8_SPEI3_SHIFT               (23u)
+#define INTC_ICDISPR8_SPRI3_SHIFT               (24u)
+#define INTC_ICDISPR8_SPTI3_SHIFT               (25u)
+#define INTC_ICDISPR8_SPEI4_SHIFT               (26u)
+#define INTC_ICDISPR8_SPRI4_SHIFT               (27u)
+#define INTC_ICDISPR8_SPTI4_SHIFT               (28u)
+#define INTC_ICDISPR8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDISPR8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDISPR8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDISPR9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDISPR9_ISY_SHIFT                 (1u)
+#define INTC_ICDISPR9_IERR_SHIFT                (2u)
+#define INTC_ICDISPR9_ITARG_SHIFT               (3u)
+#define INTC_ICDISPR9_ISEC_SHIFT                (4u)
+#define INTC_ICDISPR9_IBUF_SHIFT                (5u)
+#define INTC_ICDISPR9_IREADY_SHIFT              (6u)
+#define INTC_ICDISPR9_FLSTE_SHIFT               (7u)
+#define INTC_ICDISPR9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDISPR9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDISPR9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDISPR9_MMC0_SHIFT                (11u)
+#define INTC_ICDISPR9_MMC1_SHIFT                (12u)
+#define INTC_ICDISPR9_MMC2_SHIFT                (13u)
+#define INTC_ICDISPR9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDISPR9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDISPR9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDISPR9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDISPR9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDISPR9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDISPR9_ARM_SHIFT                 (20u)
+#define INTC_ICDISPR9_PRD_SHIFT                 (21u)
+#define INTC_ICDISPR9_CUP_SHIFT                 (22u)
+#define INTC_ICDISPR9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDISPR9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDISPR9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDISPR9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDISPR9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDISPR9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDISPR9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDISPR9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDISPR9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDISPR10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDISPR10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDISPR10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDISPR10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDISPR10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDISPR10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDISPR10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDISPR10_DRC0_SHIFT               (7u)
+#define INTC_ICDISPR10_DRC1_SHIFT               (8u)
+#define INTC_ICDISPR10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDISPR10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDISPR10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDISPR10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDISPR10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDISPR10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDISPR10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDISPR10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDISPR10_ERI0_SHIFT               (27u)
+#define INTC_ICDISPR10_RXI0_SHIFT               (28u)
+#define INTC_ICDISPR10_TXI0_SHIFT               (29u)
+#define INTC_ICDISPR10_TEI0_SHIFT               (30u)
+#define INTC_ICDISPR10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDISPR11_RXI1_SHIFT               (0u)
+#define INTC_ICDISPR11_TXI1_SHIFT               (1u)
+#define INTC_ICDISPR11_TEI1_SHIFT               (2u)
+#define INTC_ICDISPR11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDISPR11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDISPR11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDISPR11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDISPR11_ETHERI_SHIFT             (7u)
+#define INTC_ICDISPR11_CEUI_SHIFT               (12u)
+#define INTC_ICDISPR11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDISPR11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDISPR11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDISPR12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDISPR12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDISPR12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDISPR12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDISPR12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDISPR12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDISPR12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDISPR12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDISPR12_PRRI_SHIFT               (8u)
+#define INTC_ICDISPR12_IFEI0_SHIFT              (9u)
+#define INTC_ICDISPR12_OFFI0_SHIFT              (10u)
+#define INTC_ICDISPR12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDISPR12_IFEI1_SHIFT              (12u)
+#define INTC_ICDISPR12_OFFI1_SHIFT              (13u)
+#define INTC_ICDISPR12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDISPR13_TINT0_SHIFT              (0u)
+#define INTC_ICDISPR13_TINT1_SHIFT              (1u)
+#define INTC_ICDISPR13_TINT2_SHIFT              (2u)
+#define INTC_ICDISPR13_TINT3_SHIFT              (3u)
+#define INTC_ICDISPR13_TINT4_SHIFT              (4u)
+#define INTC_ICDISPR13_TINT5_SHIFT              (5u)
+#define INTC_ICDISPR13_TINT6_SHIFT              (6u)
+#define INTC_ICDISPR13_TINT7_SHIFT              (7u)
+#define INTC_ICDISPR13_TINT8_SHIFT              (8u)
+#define INTC_ICDISPR13_TINT9_SHIFT              (9u)
+#define INTC_ICDISPR13_TINT10_SHIFT             (10u)
+#define INTC_ICDISPR13_TINT11_SHIFT             (11u)
+#define INTC_ICDISPR13_TINT12_SHIFT             (12u)
+#define INTC_ICDISPR13_TINT13_SHIFT             (13u)
+#define INTC_ICDISPR13_TINT14_SHIFT             (14u)
+#define INTC_ICDISPR13_TINT15_SHIFT             (15u)
+#define INTC_ICDISPR13_TINT16_SHIFT             (16u)
+#define INTC_ICDISPR13_TINT17_SHIFT             (17u)
+#define INTC_ICDISPR13_TINT18_SHIFT             (18u)
+#define INTC_ICDISPR13_TINT19_SHIFT             (19u)
+#define INTC_ICDISPR13_TINT20_SHIFT             (20u)
+#define INTC_ICDISPR13_TINT21_SHIFT             (21u)
+#define INTC_ICDISPR13_TINT22_SHIFT             (22u)
+#define INTC_ICDISPR13_TINT23_SHIFT             (23u)
+#define INTC_ICDISPR13_TINT24_SHIFT             (24u)
+#define INTC_ICDISPR13_TINT25_SHIFT             (25u)
+#define INTC_ICDISPR13_TINT26_SHIFT             (26u)
+#define INTC_ICDISPR13_TINT27_SHIFT             (27u)
+#define INTC_ICDISPR13_TINT28_SHIFT             (28u)
+#define INTC_ICDISPR13_TINT29_SHIFT             (29u)
+#define INTC_ICDISPR13_TINT30_SHIFT             (30u)
+#define INTC_ICDISPR13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDISPR14_TINT32_SHIFT             (0u)
+#define INTC_ICDISPR14_TINT33_SHIFT             (1u)
+#define INTC_ICDISPR14_TINT34_SHIFT             (2u)
+#define INTC_ICDISPR14_TINT35_SHIFT             (3u)
+#define INTC_ICDISPR14_TINT36_SHIFT             (4u)
+#define INTC_ICDISPR14_TINT37_SHIFT             (5u)
+#define INTC_ICDISPR14_TINT38_SHIFT             (6u)
+#define INTC_ICDISPR14_TINT39_SHIFT             (7u)
+#define INTC_ICDISPR14_TINT40_SHIFT             (8u)
+#define INTC_ICDISPR14_TINT41_SHIFT             (9u)
+#define INTC_ICDISPR14_TINT42_SHIFT             (10u)
+#define INTC_ICDISPR14_TINT43_SHIFT             (11u)
+#define INTC_ICDISPR14_TINT44_SHIFT             (12u)
+#define INTC_ICDISPR14_TINT45_SHIFT             (13u)
+#define INTC_ICDISPR14_TINT46_SHIFT             (14u)
+#define INTC_ICDISPR14_TINT47_SHIFT             (15u)
+#define INTC_ICDISPR14_TINT48_SHIFT             (16u)
+#define INTC_ICDISPR14_TINT49_SHIFT             (17u)
+#define INTC_ICDISPR14_TINT50_SHIFT             (18u)
+#define INTC_ICDISPR14_TINT51_SHIFT             (19u)
+#define INTC_ICDISPR14_TINT52_SHIFT             (20u)
+#define INTC_ICDISPR14_TINT53_SHIFT             (21u)
+#define INTC_ICDISPR14_TINT54_SHIFT             (22u)
+#define INTC_ICDISPR14_TINT55_SHIFT             (23u)
+#define INTC_ICDISPR14_TINT56_SHIFT             (24u)
+#define INTC_ICDISPR14_TINT57_SHIFT             (25u)
+#define INTC_ICDISPR14_TINT58_SHIFT             (26u)
+#define INTC_ICDISPR14_TINT59_SHIFT             (27u)
+#define INTC_ICDISPR14_TINT60_SHIFT             (28u)
+#define INTC_ICDISPR14_TINT61_SHIFT             (29u)
+#define INTC_ICDISPR14_TINT62_SHIFT             (30u)
+#define INTC_ICDISPR14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDISPR15_TINT64_SHIFT             (0u)
+#define INTC_ICDISPR15_TINT65_SHIFT             (1u)
+#define INTC_ICDISPR15_TINT66_SHIFT             (2u)
+#define INTC_ICDISPR15_TINT67_SHIFT             (3u)
+#define INTC_ICDISPR15_TINT68_SHIFT             (4u)
+#define INTC_ICDISPR15_TINT69_SHIFT             (5u)
+#define INTC_ICDISPR15_TINT70_SHIFT             (6u)
+#define INTC_ICDISPR15_TINT71_SHIFT             (7u)
+#define INTC_ICDISPR15_TINT72_SHIFT             (8u)
+#define INTC_ICDISPR15_TINT73_SHIFT             (9u)
+#define INTC_ICDISPR15_TINT74_SHIFT             (10u)
+#define INTC_ICDISPR15_TINT75_SHIFT             (11u)
+#define INTC_ICDISPR15_TINT76_SHIFT             (12u)
+#define INTC_ICDISPR15_TINT77_SHIFT             (13u)
+#define INTC_ICDISPR15_TINT78_SHIFT             (14u)
+#define INTC_ICDISPR15_TINT79_SHIFT             (15u)
+#define INTC_ICDISPR15_TINT80_SHIFT             (16u)
+#define INTC_ICDISPR15_TINT81_SHIFT             (17u)
+#define INTC_ICDISPR15_TINT82_SHIFT             (18u)
+#define INTC_ICDISPR15_TINT83_SHIFT             (19u)
+#define INTC_ICDISPR15_TINT84_SHIFT             (20u)
+#define INTC_ICDISPR15_TINT85_SHIFT             (21u)
+#define INTC_ICDISPR15_TINT86_SHIFT             (22u)
+#define INTC_ICDISPR15_TINT87_SHIFT             (23u)
+#define INTC_ICDISPR15_TINT88_SHIFT             (24u)
+#define INTC_ICDISPR15_TINT89_SHIFT             (25u)
+#define INTC_ICDISPR15_TINT90_SHIFT             (26u)
+#define INTC_ICDISPR15_TINT91_SHIFT             (27u)
+#define INTC_ICDISPR15_TINT92_SHIFT             (28u)
+#define INTC_ICDISPR15_TINT93_SHIFT             (29u)
+#define INTC_ICDISPR15_TINT94_SHIFT             (30u)
+#define INTC_ICDISPR15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDISPR16_TINT96_SHIFT             (0u)
+#define INTC_ICDISPR16_TINT97_SHIFT             (1u)
+#define INTC_ICDISPR16_TINT98_SHIFT             (2u)
+#define INTC_ICDISPR16_TINT99_SHIFT             (3u)
+#define INTC_ICDISPR16_TINT100_SHIFT            (4u)
+#define INTC_ICDISPR16_TINT101_SHIFT            (5u)
+#define INTC_ICDISPR16_TINT102_SHIFT            (6u)
+#define INTC_ICDISPR16_TINT103_SHIFT            (7u)
+#define INTC_ICDISPR16_TINT104_SHIFT            (8u)
+#define INTC_ICDISPR16_TINT105_SHIFT            (9u)
+#define INTC_ICDISPR16_TINT106_SHIFT            (10u)
+#define INTC_ICDISPR16_TINT107_SHIFT            (11u)
+#define INTC_ICDISPR16_TINT108_SHIFT            (12u)
+#define INTC_ICDISPR16_TINT109_SHIFT            (13u)
+#define INTC_ICDISPR16_TINT110_SHIFT            (14u)
+#define INTC_ICDISPR16_TINT111_SHIFT            (15u)
+#define INTC_ICDISPR16_TINT112_SHIFT            (16u)
+#define INTC_ICDISPR16_TINT113_SHIFT            (17u)
+#define INTC_ICDISPR16_TINT114_SHIFT            (18u)
+#define INTC_ICDISPR16_TINT115_SHIFT            (19u)
+#define INTC_ICDISPR16_TINT116_SHIFT            (20u)
+#define INTC_ICDISPR16_TINT117_SHIFT            (21u)
+#define INTC_ICDISPR16_TINT118_SHIFT            (22u)
+#define INTC_ICDISPR16_TINT119_SHIFT            (23u)
+#define INTC_ICDISPR16_TINT120_SHIFT            (24u)
+#define INTC_ICDISPR16_TINT121_SHIFT            (25u)
+#define INTC_ICDISPR16_TINT122_SHIFT            (26u)
+#define INTC_ICDISPR16_TINT123_SHIFT            (27u)
+#define INTC_ICDISPR16_TINT124_SHIFT            (28u)
+#define INTC_ICDISPR16_TINT125_SHIFT            (29u)
+#define INTC_ICDISPR16_TINT126_SHIFT            (30u)
+#define INTC_ICDISPR16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDISPR17_TINT128_SHIFT            (0u)
+#define INTC_ICDISPR17_TINT129_SHIFT            (1u)
+#define INTC_ICDISPR17_TINT130_SHIFT            (2u)
+#define INTC_ICDISPR17_TINT131_SHIFT            (3u)
+#define INTC_ICDISPR17_TINT132_SHIFT            (4u)
+#define INTC_ICDISPR17_TINT133_SHIFT            (5u)
+#define INTC_ICDISPR17_TINT134_SHIFT            (6u)
+#define INTC_ICDISPR17_TINT135_SHIFT            (7u)
+#define INTC_ICDISPR17_TINT136_SHIFT            (8u)
+#define INTC_ICDISPR17_TINT137_SHIFT            (9u)
+#define INTC_ICDISPR17_TINT138_SHIFT            (10u)
+#define INTC_ICDISPR17_TINT139_SHIFT            (11u)
+#define INTC_ICDISPR17_TINT140_SHIFT            (12u)
+#define INTC_ICDISPR17_TINT141_SHIFT            (13u)
+#define INTC_ICDISPR17_TINT142_SHIFT            (14u)
+#define INTC_ICDISPR17_TINT143_SHIFT            (15u)
+#define INTC_ICDISPR17_TINT144_SHIFT            (16u)
+#define INTC_ICDISPR17_TINT145_SHIFT            (17u)
+#define INTC_ICDISPR17_TINT146_SHIFT            (18u)
+#define INTC_ICDISPR17_TINT147_SHIFT            (19u)
+#define INTC_ICDISPR17_TINT148_SHIFT            (20u)
+#define INTC_ICDISPR17_TINT149_SHIFT            (21u)
+#define INTC_ICDISPR17_TINT150_SHIFT            (22u)
+#define INTC_ICDISPR17_TINT151_SHIFT            (23u)
+#define INTC_ICDISPR17_TINT152_SHIFT            (24u)
+#define INTC_ICDISPR17_TINT153_SHIFT            (25u)
+#define INTC_ICDISPR17_TINT154_SHIFT            (26u)
+#define INTC_ICDISPR17_TINT155_SHIFT            (27u)
+#define INTC_ICDISPR17_TINT156_SHIFT            (28u)
+#define INTC_ICDISPR17_TINT157_SHIFT            (29u)
+#define INTC_ICDISPR17_TINT158_SHIFT            (30u)
+#define INTC_ICDISPR17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDISPR18_TINT160_SHIFT            (0u)
+#define INTC_ICDISPR18_TINT161_SHIFT            (1u)
+#define INTC_ICDISPR18_TINT162_SHIFT            (2u)
+#define INTC_ICDISPR18_TINT163_SHIFT            (3u)
+#define INTC_ICDISPR18_TINT164_SHIFT            (4u)
+#define INTC_ICDISPR18_TINT165_SHIFT            (5u)
+#define INTC_ICDISPR18_TINT166_SHIFT            (6u)
+#define INTC_ICDISPR18_TINT167_SHIFT            (7u)
+#define INTC_ICDISPR18_TINT168_SHIFT            (8u)
+#define INTC_ICDISPR18_TINT169_SHIFT            (9u)
+#define INTC_ICDISPR18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDICPR0_SW0_SHIFT                 (0u)
+#define INTC_ICDICPR0_SW1_SHIFT                 (1u)
+#define INTC_ICDICPR0_SW2_SHIFT                 (2u)
+#define INTC_ICDICPR0_SW3_SHIFT                 (3u)
+#define INTC_ICDICPR0_SW4_SHIFT                 (4u)
+#define INTC_ICDICPR0_SW5_SHIFT                 (5u)
+#define INTC_ICDICPR0_SW6_SHIFT                 (6u)
+#define INTC_ICDICPR0_SW7_SHIFT                 (7u)
+#define INTC_ICDICPR0_SW8_SHIFT                 (8u)
+#define INTC_ICDICPR0_SW9_SHIFT                 (9u)
+#define INTC_ICDICPR0_SW10_SHIFT                (10u)
+#define INTC_ICDICPR0_SW11_SHIFT                (11u)
+#define INTC_ICDICPR0_SW12_SHIFT                (12u)
+#define INTC_ICDICPR0_SW13_SHIFT                (13u)
+#define INTC_ICDICPR0_SW14_SHIFT                (14u)
+#define INTC_ICDICPR0_SW15_SHIFT                (15u)
+#define INTC_ICDICPR0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDICPR0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDICPR0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDICPR0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDICPR1_IRQ0_SHIFT                (0u)
+#define INTC_ICDICPR1_IRQ1_SHIFT                (1u)
+#define INTC_ICDICPR1_IRQ2_SHIFT                (2u)
+#define INTC_ICDICPR1_IRQ3_SHIFT                (3u)
+#define INTC_ICDICPR1_IRQ4_SHIFT                (4u)
+#define INTC_ICDICPR1_IRQ5_SHIFT                (5u)
+#define INTC_ICDICPR1_IRQ6_SHIFT                (6u)
+#define INTC_ICDICPR1_IRQ7_SHIFT                (7u)
+#define INTC_ICDICPR1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDICPR1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDICPR1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDICPR1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDICPR1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDICPR1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDICPR1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDICPR1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDICPR1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDICPR1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDICPR1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDICPR1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDICPR1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDICPR1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDICPR1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDICPR1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDICPR1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDICPR1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDICPR2_USBI0_SHIFT               (9u)
+#define INTC_ICDICPR2_USBI1_SHIFT               (10u)
+#define INTC_ICDICPR2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDICPR2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDICPR2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDICPR2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDICPR2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDICPR2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDICPR2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDICPR2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDICPR2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDICPR2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDICPR2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDICPR2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDICPR2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDICPR2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDICPR2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDICPR2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDICPR2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDICPR2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDICPR2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDICPR2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDICPR2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDICPR3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDICPR3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDICPR3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDICPR3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDICPR3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDICPR3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDICPR3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDICPR3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDICPR3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDICPR3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDICPR3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDICPR3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDICPR3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDICPR3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDICPR3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDICPR3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDICPR3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDICPR3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDICPR3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDICPR3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDICPR3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDICPR3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDICPR3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDICPR3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDICPR3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDICPR3_IMRDI_SHIFT               (27u)
+#define INTC_ICDICPR3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDICPR3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDICPR3_JEDI_SHIFT                (30u)
+#define INTC_ICDICPR3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDICPR4_CMP0_SHIFT                (0u)
+#define INTC_ICDICPR4_CMP1_SHIFT                (1u)
+#define INTC_ICDICPR4_INT0_SHIFT                (2u)
+#define INTC_ICDICPR4_INT1_SHIFT                (3u)
+#define INTC_ICDICPR4_INT2_SHIFT                (4u)
+#define INTC_ICDICPR4_INT3_SHIFT                (5u)
+#define INTC_ICDICPR4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDICPR4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDICPR4_CMI_SHIFT                 (8u)
+#define INTC_ICDICPR4_WTOUT_SHIFT               (9u)
+#define INTC_ICDICPR4_ITI_SHIFT                 (10u)
+#define INTC_ICDICPR4_TGI0A_SHIFT               (11u)
+#define INTC_ICDICPR4_TGI0B_SHIFT               (12u)
+#define INTC_ICDICPR4_TGI0C_SHIFT               (13u)
+#define INTC_ICDICPR4_TGI0D_SHIFT               (14u)
+#define INTC_ICDICPR4_TGI0V_SHIFT               (15u)
+#define INTC_ICDICPR4_TGI0E_SHIFT               (16u)
+#define INTC_ICDICPR4_TGI0F_SHIFT               (17u)
+#define INTC_ICDICPR4_TGI1A_SHIFT               (18u)
+#define INTC_ICDICPR4_TGI1B_SHIFT               (19u)
+#define INTC_ICDICPR4_TGI1V_SHIFT               (20u)
+#define INTC_ICDICPR4_TGI1U_SHIFT               (21u)
+#define INTC_ICDICPR4_TGI2A_SHIFT               (22u)
+#define INTC_ICDICPR4_TGI2B_SHIFT               (23u)
+#define INTC_ICDICPR4_TGI2V_SHIFT               (24u)
+#define INTC_ICDICPR4_TGI2U_SHIFT               (25u)
+#define INTC_ICDICPR4_TGI3A_SHIFT               (26u)
+#define INTC_ICDICPR4_TGI3B_SHIFT               (27u)
+#define INTC_ICDICPR4_TGI3C_SHIFT               (28u)
+#define INTC_ICDICPR4_TGI3D_SHIFT               (29u)
+#define INTC_ICDICPR4_TGI3V_SHIFT               (30u)
+#define INTC_ICDICPR4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDICPR5_TGI4B_SHIFT               (0u)
+#define INTC_ICDICPR5_TGI4C_SHIFT               (1u)
+#define INTC_ICDICPR5_TGI4D_SHIFT               (2u)
+#define INTC_ICDICPR5_TGI4V_SHIFT               (3u)
+#define INTC_ICDICPR5_CMI1_SHIFT                (4u)
+#define INTC_ICDICPR5_CMI2_SHIFT                (5u)
+#define INTC_ICDICPR5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDICPR5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDICPR5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDICPR5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDICPR5_ADI_SHIFT                 (10u)
+#define INTC_ICDICPR5_LMTI_SHIFT                (11u)
+#define INTC_ICDICPR5_SSII0_SHIFT               (12u)
+#define INTC_ICDICPR5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDICPR5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDICPR5_SSII1_SHIFT               (15u)
+#define INTC_ICDICPR5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDICPR5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDICPR5_SSII2_SHIFT               (18u)
+#define INTC_ICDICPR5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDICPR5_SSII3_SHIFT               (20u)
+#define INTC_ICDICPR5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDICPR5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDICPR5_SSII4_SHIFT               (23u)
+#define INTC_ICDICPR5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDICPR5_SSII5_SHIFT               (25u)
+#define INTC_ICDICPR5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDICPR5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDICPR5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDICPR5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDICPR5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDICPR5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDICPR6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDICPR6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDICPR6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDICPR6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDICPR6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDICPR6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDICPR6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDICPR6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDICPR6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDICPR6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDICPR6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDICPR6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDICPR6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDICPR6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDICPR6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDICPR6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDICPR6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDICPR6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDICPR6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDICPR6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDICPR6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDICPR6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDICPR6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDICPR6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDICPR6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDICPR6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDICPR6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDICPR6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDICPR6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDICPR6_BRI0_SHIFT                (29u)
+#define INTC_ICDICPR6_ERI0_SHIFT                (30u)
+#define INTC_ICDICPR6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDICPR7_TXI0_SHIFT                (0u)
+#define INTC_ICDICPR7_BRI1_SHIFT                (1u)
+#define INTC_ICDICPR7_ERI1_SHIFT                (2u)
+#define INTC_ICDICPR7_RXI1_SHIFT                (3u)
+#define INTC_ICDICPR7_TXI1_SHIFT                (4u)
+#define INTC_ICDICPR7_BRI2_SHIFT                (5u)
+#define INTC_ICDICPR7_ERI2_SHIFT                (6u)
+#define INTC_ICDICPR7_RXI2_SHIFT                (7u)
+#define INTC_ICDICPR7_TXI2_SHIFT                (8u)
+#define INTC_ICDICPR7_BRI3_SHIFT                (9u)
+#define INTC_ICDICPR7_ERI3_SHIFT                (10u)
+#define INTC_ICDICPR7_RXI3_SHIFT                (11u)
+#define INTC_ICDICPR7_TXI3_SHIFT                (12u)
+#define INTC_ICDICPR7_BRI4_SHIFT                (13u)
+#define INTC_ICDICPR7_ERI4_SHIFT                (14u)
+#define INTC_ICDICPR7_RXI4_SHIFT                (15u)
+#define INTC_ICDICPR7_TXI4_SHIFT                (16u)
+#define INTC_ICDICPR7_BRI5_SHIFT                (17u)
+#define INTC_ICDICPR7_ERI5_SHIFT                (18u)
+#define INTC_ICDICPR7_RXI5_SHIFT                (19u)
+#define INTC_ICDICPR7_TXI5_SHIFT                (20u)
+#define INTC_ICDICPR7_BRI6_SHIFT                (21u)
+#define INTC_ICDICPR7_ERI6_SHIFT                (22u)
+#define INTC_ICDICPR7_RXI6_SHIFT                (23u)
+#define INTC_ICDICPR7_TXI6_SHIFT                (24u)
+#define INTC_ICDICPR7_BRI7_SHIFT                (25u)
+#define INTC_ICDICPR7_ERI7_SHIFT                (26u)
+#define INTC_ICDICPR7_RXI7_SHIFT                (27u)
+#define INTC_ICDICPR7_TXI7_SHIFT                (28u)
+#define INTC_ICDICPR7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDICPR7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDICPR7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDICPR8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDICPR8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDICPR8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDICPR8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDICPR8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDICPR8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDICPR8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDICPR8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDICPR8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDICPR8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDICPR8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDICPR8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDICPR8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDICPR8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDICPR8_SPEI0_SHIFT               (14u)
+#define INTC_ICDICPR8_SPRI0_SHIFT               (15u)
+#define INTC_ICDICPR8_SPTI0_SHIFT               (16u)
+#define INTC_ICDICPR8_SPEI1_SHIFT               (17u)
+#define INTC_ICDICPR8_SPRI1_SHIFT               (18u)
+#define INTC_ICDICPR8_SPTI1_SHIFT               (19u)
+#define INTC_ICDICPR8_SPEI2_SHIFT               (20u)
+#define INTC_ICDICPR8_SPRI2_SHIFT               (21u)
+#define INTC_ICDICPR8_SPTI2_SHIFT               (22u)
+#define INTC_ICDICPR8_SPEI3_SHIFT               (23u)
+#define INTC_ICDICPR8_SPRI3_SHIFT               (24u)
+#define INTC_ICDICPR8_SPTI3_SHIFT               (25u)
+#define INTC_ICDICPR8_SPEI4_SHIFT               (26u)
+#define INTC_ICDICPR8_SPRI4_SHIFT               (27u)
+#define INTC_ICDICPR8_SPTI4_SHIFT               (28u)
+#define INTC_ICDICPR8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDICPR8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDICPR8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDICPR9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDICPR9_ISY_SHIFT                 (1u)
+#define INTC_ICDICPR9_IERR_SHIFT                (2u)
+#define INTC_ICDICPR9_ITARG_SHIFT               (3u)
+#define INTC_ICDICPR9_ISEC_SHIFT                (4u)
+#define INTC_ICDICPR9_IBUF_SHIFT                (5u)
+#define INTC_ICDICPR9_IREADY_SHIFT              (6u)
+#define INTC_ICDICPR9_FLSTE_SHIFT               (7u)
+#define INTC_ICDICPR9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDICPR9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDICPR9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDICPR9_MMC0_SHIFT                (11u)
+#define INTC_ICDICPR9_MMC1_SHIFT                (12u)
+#define INTC_ICDICPR9_MMC2_SHIFT                (13u)
+#define INTC_ICDICPR9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDICPR9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDICPR9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDICPR9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDICPR9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDICPR9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDICPR9_ARM_SHIFT                 (20u)
+#define INTC_ICDICPR9_PRD_SHIFT                 (21u)
+#define INTC_ICDICPR9_CUP_SHIFT                 (22u)
+#define INTC_ICDICPR9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDICPR9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDICPR9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDICPR9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDICPR9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDICPR9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDICPR9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDICPR9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDICPR9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDICPR10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDICPR10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDICPR10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDICPR10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDICPR10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDICPR10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDICPR10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDICPR10_DRC0_SHIFT               (7u)
+#define INTC_ICDICPR10_DRC1_SHIFT               (8u)
+#define INTC_ICDICPR10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDICPR10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDICPR10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDICPR10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDICPR10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDICPR10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDICPR10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDICPR10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDICPR10_ERI0_SHIFT               (27u)
+#define INTC_ICDICPR10_RXI0_SHIFT               (28u)
+#define INTC_ICDICPR10_TXI0_SHIFT               (29u)
+#define INTC_ICDICPR10_TEI0_SHIFT               (30u)
+#define INTC_ICDICPR10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDICPR11_RXI1_SHIFT               (0u)
+#define INTC_ICDICPR11_TXI1_SHIFT               (1u)
+#define INTC_ICDICPR11_TEI1_SHIFT               (2u)
+#define INTC_ICDICPR11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDICPR11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDICPR11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDICPR11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDICPR11_ETHERI_SHIFT             (7u)
+#define INTC_ICDICPR11_CEUI_SHIFT               (12u)
+#define INTC_ICDICPR11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDICPR11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDICPR11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDICPR12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDICPR12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDICPR12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDICPR12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDICPR12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDICPR12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDICPR12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDICPR12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDICPR12_PRRI_SHIFT               (8u)
+#define INTC_ICDICPR12_IFEI0_SHIFT              (9u)
+#define INTC_ICDICPR12_OFFI0_SHIFT              (10u)
+#define INTC_ICDICPR12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDICPR12_IFEI1_SHIFT              (12u)
+#define INTC_ICDICPR12_OFFI1_SHIFT              (13u)
+#define INTC_ICDICPR12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDICPR13_TINT0_SHIFT              (0u)
+#define INTC_ICDICPR13_TINT1_SHIFT              (1u)
+#define INTC_ICDICPR13_TINT2_SHIFT              (2u)
+#define INTC_ICDICPR13_TINT3_SHIFT              (3u)
+#define INTC_ICDICPR13_TINT4_SHIFT              (4u)
+#define INTC_ICDICPR13_TINT5_SHIFT              (5u)
+#define INTC_ICDICPR13_TINT6_SHIFT              (6u)
+#define INTC_ICDICPR13_TINT7_SHIFT              (7u)
+#define INTC_ICDICPR13_TINT8_SHIFT              (8u)
+#define INTC_ICDICPR13_TINT9_SHIFT              (9u)
+#define INTC_ICDICPR13_TINT10_SHIFT             (10u)
+#define INTC_ICDICPR13_TINT11_SHIFT             (11u)
+#define INTC_ICDICPR13_TINT12_SHIFT             (12u)
+#define INTC_ICDICPR13_TINT13_SHIFT             (13u)
+#define INTC_ICDICPR13_TINT14_SHIFT             (14u)
+#define INTC_ICDICPR13_TINT15_SHIFT             (15u)
+#define INTC_ICDICPR13_TINT16_SHIFT             (16u)
+#define INTC_ICDICPR13_TINT17_SHIFT             (17u)
+#define INTC_ICDICPR13_TINT18_SHIFT             (18u)
+#define INTC_ICDICPR13_TINT19_SHIFT             (19u)
+#define INTC_ICDICPR13_TINT20_SHIFT             (20u)
+#define INTC_ICDICPR13_TINT21_SHIFT             (21u)
+#define INTC_ICDICPR13_TINT22_SHIFT             (22u)
+#define INTC_ICDICPR13_TINT23_SHIFT             (23u)
+#define INTC_ICDICPR13_TINT24_SHIFT             (24u)
+#define INTC_ICDICPR13_TINT25_SHIFT             (25u)
+#define INTC_ICDICPR13_TINT26_SHIFT             (26u)
+#define INTC_ICDICPR13_TINT27_SHIFT             (27u)
+#define INTC_ICDICPR13_TINT28_SHIFT             (28u)
+#define INTC_ICDICPR13_TINT29_SHIFT             (29u)
+#define INTC_ICDICPR13_TINT30_SHIFT             (30u)
+#define INTC_ICDICPR13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDICPR14_TINT32_SHIFT             (0u)
+#define INTC_ICDICPR14_TINT33_SHIFT             (1u)
+#define INTC_ICDICPR14_TINT34_SHIFT             (2u)
+#define INTC_ICDICPR14_TINT35_SHIFT             (3u)
+#define INTC_ICDICPR14_TINT36_SHIFT             (4u)
+#define INTC_ICDICPR14_TINT37_SHIFT             (5u)
+#define INTC_ICDICPR14_TINT38_SHIFT             (6u)
+#define INTC_ICDICPR14_TINT39_SHIFT             (7u)
+#define INTC_ICDICPR14_TINT40_SHIFT             (8u)
+#define INTC_ICDICPR14_TINT41_SHIFT             (9u)
+#define INTC_ICDICPR14_TINT42_SHIFT             (10u)
+#define INTC_ICDICPR14_TINT43_SHIFT             (11u)
+#define INTC_ICDICPR14_TINT44_SHIFT             (12u)
+#define INTC_ICDICPR14_TINT45_SHIFT             (13u)
+#define INTC_ICDICPR14_TINT46_SHIFT             (14u)
+#define INTC_ICDICPR14_TINT47_SHIFT             (15u)
+#define INTC_ICDICPR14_TINT48_SHIFT             (16u)
+#define INTC_ICDICPR14_TINT49_SHIFT             (17u)
+#define INTC_ICDICPR14_TINT50_SHIFT             (18u)
+#define INTC_ICDICPR14_TINT51_SHIFT             (19u)
+#define INTC_ICDICPR14_TINT52_SHIFT             (20u)
+#define INTC_ICDICPR14_TINT53_SHIFT             (21u)
+#define INTC_ICDICPR14_TINT54_SHIFT             (22u)
+#define INTC_ICDICPR14_TINT55_SHIFT             (23u)
+#define INTC_ICDICPR14_TINT56_SHIFT             (24u)
+#define INTC_ICDICPR14_TINT57_SHIFT             (25u)
+#define INTC_ICDICPR14_TINT58_SHIFT             (26u)
+#define INTC_ICDICPR14_TINT59_SHIFT             (27u)
+#define INTC_ICDICPR14_TINT60_SHIFT             (28u)
+#define INTC_ICDICPR14_TINT61_SHIFT             (29u)
+#define INTC_ICDICPR14_TINT62_SHIFT             (30u)
+#define INTC_ICDICPR14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDICPR15_TINT64_SHIFT             (0u)
+#define INTC_ICDICPR15_TINT65_SHIFT             (1u)
+#define INTC_ICDICPR15_TINT66_SHIFT             (2u)
+#define INTC_ICDICPR15_TINT67_SHIFT             (3u)
+#define INTC_ICDICPR15_TINT68_SHIFT             (4u)
+#define INTC_ICDICPR15_TINT69_SHIFT             (5u)
+#define INTC_ICDICPR15_TINT70_SHIFT             (6u)
+#define INTC_ICDICPR15_TINT71_SHIFT             (7u)
+#define INTC_ICDICPR15_TINT72_SHIFT             (8u)
+#define INTC_ICDICPR15_TINT73_SHIFT             (9u)
+#define INTC_ICDICPR15_TINT74_SHIFT             (10u)
+#define INTC_ICDICPR15_TINT75_SHIFT             (11u)
+#define INTC_ICDICPR15_TINT76_SHIFT             (12u)
+#define INTC_ICDICPR15_TINT77_SHIFT             (13u)
+#define INTC_ICDICPR15_TINT78_SHIFT             (14u)
+#define INTC_ICDICPR15_TINT79_SHIFT             (15u)
+#define INTC_ICDICPR15_TINT80_SHIFT             (16u)
+#define INTC_ICDICPR15_TINT81_SHIFT             (17u)
+#define INTC_ICDICPR15_TINT82_SHIFT             (18u)
+#define INTC_ICDICPR15_TINT83_SHIFT             (19u)
+#define INTC_ICDICPR15_TINT84_SHIFT             (20u)
+#define INTC_ICDICPR15_TINT85_SHIFT             (21u)
+#define INTC_ICDICPR15_TINT86_SHIFT             (22u)
+#define INTC_ICDICPR15_TINT87_SHIFT             (23u)
+#define INTC_ICDICPR15_TINT88_SHIFT             (24u)
+#define INTC_ICDICPR15_TINT89_SHIFT             (25u)
+#define INTC_ICDICPR15_TINT90_SHIFT             (26u)
+#define INTC_ICDICPR15_TINT91_SHIFT             (27u)
+#define INTC_ICDICPR15_TINT92_SHIFT             (28u)
+#define INTC_ICDICPR15_TINT93_SHIFT             (29u)
+#define INTC_ICDICPR15_TINT94_SHIFT             (30u)
+#define INTC_ICDICPR15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDICPR16_TINT96_SHIFT             (0u)
+#define INTC_ICDICPR16_TINT97_SHIFT             (1u)
+#define INTC_ICDICPR16_TINT98_SHIFT             (2u)
+#define INTC_ICDICPR16_TINT99_SHIFT             (3u)
+#define INTC_ICDICPR16_TINT100_SHIFT            (4u)
+#define INTC_ICDICPR16_TINT101_SHIFT            (5u)
+#define INTC_ICDICPR16_TINT102_SHIFT            (6u)
+#define INTC_ICDICPR16_TINT103_SHIFT            (7u)
+#define INTC_ICDICPR16_TINT104_SHIFT            (8u)
+#define INTC_ICDICPR16_TINT105_SHIFT            (9u)
+#define INTC_ICDICPR16_TINT106_SHIFT            (10u)
+#define INTC_ICDICPR16_TINT107_SHIFT            (11u)
+#define INTC_ICDICPR16_TINT108_SHIFT            (12u)
+#define INTC_ICDICPR16_TINT109_SHIFT            (13u)
+#define INTC_ICDICPR16_TINT110_SHIFT            (14u)
+#define INTC_ICDICPR16_TINT111_SHIFT            (15u)
+#define INTC_ICDICPR16_TINT112_SHIFT            (16u)
+#define INTC_ICDICPR16_TINT113_SHIFT            (17u)
+#define INTC_ICDICPR16_TINT114_SHIFT            (18u)
+#define INTC_ICDICPR16_TINT115_SHIFT            (19u)
+#define INTC_ICDICPR16_TINT116_SHIFT            (20u)
+#define INTC_ICDICPR16_TINT117_SHIFT            (21u)
+#define INTC_ICDICPR16_TINT118_SHIFT            (22u)
+#define INTC_ICDICPR16_TINT119_SHIFT            (23u)
+#define INTC_ICDICPR16_TINT120_SHIFT            (24u)
+#define INTC_ICDICPR16_TINT121_SHIFT            (25u)
+#define INTC_ICDICPR16_TINT122_SHIFT            (26u)
+#define INTC_ICDICPR16_TINT123_SHIFT            (27u)
+#define INTC_ICDICPR16_TINT124_SHIFT            (28u)
+#define INTC_ICDICPR16_TINT125_SHIFT            (29u)
+#define INTC_ICDICPR16_TINT126_SHIFT            (30u)
+#define INTC_ICDICPR16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDICPR17_TINT128_SHIFT            (0u)
+#define INTC_ICDICPR17_TINT129_SHIFT            (1u)
+#define INTC_ICDICPR17_TINT130_SHIFT            (2u)
+#define INTC_ICDICPR17_TINT131_SHIFT            (3u)
+#define INTC_ICDICPR17_TINT132_SHIFT            (4u)
+#define INTC_ICDICPR17_TINT133_SHIFT            (5u)
+#define INTC_ICDICPR17_TINT134_SHIFT            (6u)
+#define INTC_ICDICPR17_TINT135_SHIFT            (7u)
+#define INTC_ICDICPR17_TINT136_SHIFT            (8u)
+#define INTC_ICDICPR17_TINT137_SHIFT            (9u)
+#define INTC_ICDICPR17_TINT138_SHIFT            (10u)
+#define INTC_ICDICPR17_TINT139_SHIFT            (11u)
+#define INTC_ICDICPR17_TINT140_SHIFT            (12u)
+#define INTC_ICDICPR17_TINT141_SHIFT            (13u)
+#define INTC_ICDICPR17_TINT142_SHIFT            (14u)
+#define INTC_ICDICPR17_TINT143_SHIFT            (15u)
+#define INTC_ICDICPR17_TINT144_SHIFT            (16u)
+#define INTC_ICDICPR17_TINT145_SHIFT            (17u)
+#define INTC_ICDICPR17_TINT146_SHIFT            (18u)
+#define INTC_ICDICPR17_TINT147_SHIFT            (19u)
+#define INTC_ICDICPR17_TINT148_SHIFT            (20u)
+#define INTC_ICDICPR17_TINT149_SHIFT            (21u)
+#define INTC_ICDICPR17_TINT150_SHIFT            (22u)
+#define INTC_ICDICPR17_TINT151_SHIFT            (23u)
+#define INTC_ICDICPR17_TINT152_SHIFT            (24u)
+#define INTC_ICDICPR17_TINT153_SHIFT            (25u)
+#define INTC_ICDICPR17_TINT154_SHIFT            (26u)
+#define INTC_ICDICPR17_TINT155_SHIFT            (27u)
+#define INTC_ICDICPR17_TINT156_SHIFT            (28u)
+#define INTC_ICDICPR17_TINT157_SHIFT            (29u)
+#define INTC_ICDICPR17_TINT158_SHIFT            (30u)
+#define INTC_ICDICPR17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDICPR18_TINT160_SHIFT            (0u)
+#define INTC_ICDICPR18_TINT161_SHIFT            (1u)
+#define INTC_ICDICPR18_TINT162_SHIFT            (2u)
+#define INTC_ICDICPR18_TINT163_SHIFT            (3u)
+#define INTC_ICDICPR18_TINT164_SHIFT            (4u)
+#define INTC_ICDICPR18_TINT165_SHIFT            (5u)
+#define INTC_ICDICPR18_TINT166_SHIFT            (6u)
+#define INTC_ICDICPR18_TINT167_SHIFT            (7u)
+#define INTC_ICDICPR18_TINT168_SHIFT            (8u)
+#define INTC_ICDICPR18_TINT169_SHIFT            (9u)
+#define INTC_ICDICPR18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDABR0_SW0_SHIFT                  (0u)
+#define INTC_ICDABR0_SW1_SHIFT                  (1u)
+#define INTC_ICDABR0_SW2_SHIFT                  (2u)
+#define INTC_ICDABR0_SW3_SHIFT                  (3u)
+#define INTC_ICDABR0_SW4_SHIFT                  (4u)
+#define INTC_ICDABR0_SW5_SHIFT                  (5u)
+#define INTC_ICDABR0_SW6_SHIFT                  (6u)
+#define INTC_ICDABR0_SW7_SHIFT                  (7u)
+#define INTC_ICDABR0_SW8_SHIFT                  (8u)
+#define INTC_ICDABR0_SW9_SHIFT                  (9u)
+#define INTC_ICDABR0_SW10_SHIFT                 (10u)
+#define INTC_ICDABR0_SW11_SHIFT                 (11u)
+#define INTC_ICDABR0_SW12_SHIFT                 (12u)
+#define INTC_ICDABR0_SW13_SHIFT                 (13u)
+#define INTC_ICDABR0_SW14_SHIFT                 (14u)
+#define INTC_ICDABR0_SW15_SHIFT                 (15u)
+#define INTC_ICDABR0_PMUIRQ0_SHIFT              (16u)
+#define INTC_ICDABR0_COMMRX0_SHIFT              (17u)
+#define INTC_ICDABR0_COMMTX0_SHIFT              (18u)
+#define INTC_ICDABR0_CTIIRQ0_SHIFT              (19u)
+
+#define INTC_ICDABR1_IRQ0_SHIFT                 (0u)
+#define INTC_ICDABR1_IRQ1_SHIFT                 (1u)
+#define INTC_ICDABR1_IRQ2_SHIFT                 (2u)
+#define INTC_ICDABR1_IRQ3_SHIFT                 (3u)
+#define INTC_ICDABR1_IRQ4_SHIFT                 (4u)
+#define INTC_ICDABR1_IRQ5_SHIFT                 (5u)
+#define INTC_ICDABR1_IRQ6_SHIFT                 (6u)
+#define INTC_ICDABR1_IRQ7_SHIFT                 (7u)
+#define INTC_ICDABR1_PL310ERR_SHIFT             (8u)
+#define INTC_ICDABR1_DMAINT0_SHIFT              (9u)
+#define INTC_ICDABR1_DMAINT1_SHIFT              (10u)
+#define INTC_ICDABR1_DMAINT2_SHIFT              (11u)
+#define INTC_ICDABR1_DMAINT3_SHIFT              (12u)
+#define INTC_ICDABR1_DMAINT4_SHIFT              (13u)
+#define INTC_ICDABR1_DMAINT5_SHIFT              (14u)
+#define INTC_ICDABR1_DMAINT6_SHIFT              (15u)
+#define INTC_ICDABR1_DMAINT7_SHIFT              (16u)
+#define INTC_ICDABR1_DMAINT8_SHIFT              (17u)
+#define INTC_ICDABR1_DMAINT9_SHIFT              (18u)
+#define INTC_ICDABR1_DMAINT10_SHIFT             (19u)
+#define INTC_ICDABR1_DMAINT11_SHIFT             (20u)
+#define INTC_ICDABR1_DMAINT12_SHIFT             (21u)
+#define INTC_ICDABR1_DMAINT13_SHIFT             (22u)
+#define INTC_ICDABR1_DMAINT14_SHIFT             (23u)
+#define INTC_ICDABR1_DMAINT15_SHIFT             (24u)
+#define INTC_ICDABR1_DMAERR_SHIFT               (25u)
+
+#define INTC_ICDABR2_USBI0_SHIFT                (9u)
+#define INTC_ICDABR2_USBI1_SHIFT                (10u)
+#define INTC_ICDABR2_S0_VI_VSYNC0_SHIFT         (11u)
+#define INTC_ICDABR2_S0_LO_VSYNC0_SHIFT         (12u)
+#define INTC_ICDABR2_S0_VSYNCERR0_SHIFT         (13u)
+#define INTC_ICDABR2_GR3_VLINE0_SHIFT           (14u)
+#define INTC_ICDABR2_S0_VFIELD0_SHIFT           (15u)
+#define INTC_ICDABR2_IV1_VBUFERR0_SHIFT         (16u)
+#define INTC_ICDABR2_IV3_VBUFERR0_SHIFT         (17u)
+#define INTC_ICDABR2_IV5_VBUFERR0_SHIFT         (18u)
+#define INTC_ICDABR2_IV6_VBUFERR0_SHIFT         (19u)
+#define INTC_ICDABR2_S0_WLINE0_SHIFT            (20u)
+#define INTC_ICDABR2_S1_VI_VSYNC0_SHIFT         (21u)
+#define INTC_ICDABR2_S1_LO_VSYNC0_SHIFT         (22u)
+#define INTC_ICDABR2_S1_VSYNCERR0_SHIFT         (23u)
+#define INTC_ICDABR2_S1_VFIELD0_SHIFT           (24u)
+#define INTC_ICDABR2_IV2_VBUFERR0_SHIFT         (25u)
+#define INTC_ICDABR2_IV4_VBUFERR0_SHIFT         (26u)
+#define INTC_ICDABR2_S1_WLINE0_SHIFT            (27u)
+#define INTC_ICDABR2_OIR_VI_VSYNC0_SHIFT        (28u)
+#define INTC_ICDABR2_OIR_LO_VSYNC0_SHIFT        (29u)
+#define INTC_ICDABR2_OIR_VSYNCERR0_SHIFT        (30u)
+#define INTC_ICDABR2_OIR_VFIELD0_SHIFT          (31u)
+
+#define INTC_ICDABR3_IV7_VBUFERR0_SHIFT         (0u)
+#define INTC_ICDABR3_IV8_VBUFERR0_SHIFT         (1u)
+#define INTC_ICDABR3_S0_VI_VSYNC1_SHIFT         (3u)
+#define INTC_ICDABR3_S0_LO_VSYNC1_SHIFT         (4u)
+#define INTC_ICDABR3_S0_VSYNCERR1_SHIFT         (5u)
+#define INTC_ICDABR3_GR3_VLINE1_SHIFT           (6u)
+#define INTC_ICDABR3_S0_VFIELD1_SHIFT           (7u)
+#define INTC_ICDABR3_IV1_VBUFERR1_SHIFT         (8u)
+#define INTC_ICDABR3_IV3_VBUFERR1_SHIFT         (9u)
+#define INTC_ICDABR3_IV5_VBUFERR1_SHIFT         (10u)
+#define INTC_ICDABR3_IV6_VBUFERR1_SHIFT         (11u)
+#define INTC_ICDABR3_S0_WLINE1_SHIFT            (12u)
+#define INTC_ICDABR3_S1_VI_VSYNC1_SHIFT         (13u)
+#define INTC_ICDABR3_S1_LO_VSYNC1_SHIFT         (14u)
+#define INTC_ICDABR3_S1_VSYNCERR1_SHIFT         (15u)
+#define INTC_ICDABR3_S1_VFIELD1_SHIFT           (16u)
+#define INTC_ICDABR3_IV2_VBUFERR1_SHIFT         (17u)
+#define INTC_ICDABR3_IV4_VBUFERR1_SHIFT         (18u)
+#define INTC_ICDABR3_S1_WLINE1_SHIFT            (19u)
+#define INTC_ICDABR3_OIR_VI_VSYNC1_SHIFT        (20u)
+#define INTC_ICDABR3_OIR_LO_VSYNC1_SHIFT        (21u)
+#define INTC_ICDABR3_OIR_VLINE1_SHIFT           (22u)
+#define INTC_ICDABR3_OIR_VFIELD1_SHIFT          (23u)
+#define INTC_ICDABR3_IV7_VBUFERR1_SHIFT         (24u)
+#define INTC_ICDABR3_IV8_VBUFERR1_SHIFT         (25u)
+#define INTC_ICDABR3_IMRDI_SHIFT                (27u)
+#define INTC_ICDABR3_IMR2I0_SHIFT               (28u)
+#define INTC_ICDABR3_IMR2I1_SHIFT               (29u)
+#define INTC_ICDABR3_JEDI_SHIFT                 (30u)
+#define INTC_ICDABR3_JDTI_SHIFT                 (31u)
+
+#define INTC_ICDABR4_CMP0_SHIFT                 (0u)
+#define INTC_ICDABR4_CMP1_SHIFT                 (1u)
+#define INTC_ICDABR4_INT0_SHIFT                 (2u)
+#define INTC_ICDABR4_INT1_SHIFT                 (3u)
+#define INTC_ICDABR4_INT2_SHIFT                 (4u)
+#define INTC_ICDABR4_INT3_SHIFT                 (5u)
+#define INTC_ICDABR4_OSTM0TINT_SHIFT            (6u)
+#define INTC_ICDABR4_OSTM1TINT_SHIFT            (7u)
+#define INTC_ICDABR4_CMI_SHIFT                  (8u)
+#define INTC_ICDABR4_WTOUT_SHIFT                (9u)
+#define INTC_ICDABR4_ITI_SHIFT                  (10u)
+#define INTC_ICDABR4_TGI0A_SHIFT                (11u)
+#define INTC_ICDABR4_TGI0B_SHIFT                (12u)
+#define INTC_ICDABR4_TGI0C_SHIFT                (13u)
+#define INTC_ICDABR4_TGI0D_SHIFT                (14u)
+#define INTC_ICDABR4_TGI0V_SHIFT                (15u)
+#define INTC_ICDABR4_TGI0E_SHIFT                (16u)
+#define INTC_ICDABR4_TGI0F_SHIFT                (17u)
+#define INTC_ICDABR4_TGI1A_SHIFT                (18u)
+#define INTC_ICDABR4_TGI1B_SHIFT                (19u)
+#define INTC_ICDABR4_TGI1V_SHIFT                (20u)
+#define INTC_ICDABR4_TGI1U_SHIFT                (21u)
+#define INTC_ICDABR4_TGI2A_SHIFT                (22u)
+#define INTC_ICDABR4_TGI2B_SHIFT                (23u)
+#define INTC_ICDABR4_TGI2V_SHIFT                (24u)
+#define INTC_ICDABR4_TGI2U_SHIFT                (25u)
+#define INTC_ICDABR4_TGI3A_SHIFT                (26u)
+#define INTC_ICDABR4_TGI3B_SHIFT                (27u)
+#define INTC_ICDABR4_TGI3C_SHIFT                (28u)
+#define INTC_ICDABR4_TGI3D_SHIFT                (29u)
+#define INTC_ICDABR4_TGI3V_SHIFT                (30u)
+#define INTC_ICDABR4_TGI4A_SHIFT                (31u)
+
+#define INTC_ICDABR5_TGI4B_SHIFT                (0u)
+#define INTC_ICDABR5_TGI4C_SHIFT                (1u)
+#define INTC_ICDABR5_TGI4D_SHIFT                (2u)
+#define INTC_ICDABR5_TGI4V_SHIFT                (3u)
+#define INTC_ICDABR5_CMI1_SHIFT                 (4u)
+#define INTC_ICDABR5_CMI2_SHIFT                 (5u)
+#define INTC_ICDABR5_SGDEI0_SHIFT               (6u)
+#define INTC_ICDABR5_SGDEI1_SHIFT               (7u)
+#define INTC_ICDABR5_SGDEI2_SHIFT               (8u)
+#define INTC_ICDABR5_SGDEI3_SHIFT               (9u)
+#define INTC_ICDABR5_ADI_SHIFT                  (10u)
+#define INTC_ICDABR5_LMTI_SHIFT                 (11u)
+#define INTC_ICDABR5_SSII0_SHIFT                (12u)
+#define INTC_ICDABR5_SSIRXI0_SHIFT              (13u)
+#define INTC_ICDABR5_SSITXI0_SHIFT              (14u)
+#define INTC_ICDABR5_SSII1_SHIFT                (15u)
+#define INTC_ICDABR5_SSIRXI1_SHIFT              (16u)
+#define INTC_ICDABR5_SSITXI1_SHIFT              (17u)
+#define INTC_ICDABR5_SSII2_SHIFT                (18u)
+#define INTC_ICDABR5_SSIRTI2_SHIFT              (19u)
+#define INTC_ICDABR5_SSII3_SHIFT                (20u)
+#define INTC_ICDABR5_SSIRXI3_SHIFT              (21u)
+#define INTC_ICDABR5_SSITXI3_SHIFT              (22u)
+#define INTC_ICDABR5_SSII4_SHIFT                (23u)
+#define INTC_ICDABR5_SSIRTI4_SHIFT              (24u)
+#define INTC_ICDABR5_SSII5_SHIFT                (25u)
+#define INTC_ICDABR5_SSIRXI5_SHIFT              (26u)
+#define INTC_ICDABR5_SSITXI5_SHIFT              (27u)
+#define INTC_ICDABR5_SPDIFI_SHIFT               (28u)
+#define INTC_ICDABR5_INTIICTEI0_SHIFT           (29u)
+#define INTC_ICDABR5_INTIICRI0_SHIFT            (30u)
+#define INTC_ICDABR5_INTIICTI0_SHIFT            (31u)
+
+#define INTC_ICDABR6_INTIICSPI0_SHIFT           (0u)
+#define INTC_ICDABR6_INTIICSTI0_SHIFT           (1u)
+#define INTC_ICDABR6_INTIICNAKI0_SHIFT          (2u)
+#define INTC_ICDABR6_INTIICALI0_SHIFT           (3u)
+#define INTC_ICDABR6_INTIICTMOI0_SHIFT          (4u)
+#define INTC_ICDABR6_INTIICTEI1_SHIFT           (5u)
+#define INTC_ICDABR6_INTIICRI1_SHIFT            (6u)
+#define INTC_ICDABR6_INTIICTI1_SHIFT            (7u)
+#define INTC_ICDABR6_INTIICSPI1_SHIFT           (8u)
+#define INTC_ICDABR6_INTIICSTI1_SHIFT           (9u)
+#define INTC_ICDABR6_INTIICNAKI1_SHIFT          (10u)
+#define INTC_ICDABR6_INTIICALI1_SHIFT           (11u)
+#define INTC_ICDABR6_INTIICTMOI1_SHIFT          (12u)
+#define INTC_ICDABR6_INTIICTEI2_SHIFT           (13u)
+#define INTC_ICDABR6_INTIICRI2_SHIFT            (14u)
+#define INTC_ICDABR6_INTIICTI2_SHIFT            (15u)
+#define INTC_ICDABR6_INTIICSPI2_SHIFT           (16u)
+#define INTC_ICDABR6_INTIICSTI2_SHIFT           (17u)
+#define INTC_ICDABR6_INTIICNAKI2_SHIFT          (18u)
+#define INTC_ICDABR6_INTIICALI2_SHIFT           (19u)
+#define INTC_ICDABR6_INTIICTMOI2_SHIFT          (20u)
+#define INTC_ICDABR6_INTIICTEI3_SHIFT           (21u)
+#define INTC_ICDABR6_INTIICRI3_SHIFT            (22u)
+#define INTC_ICDABR6_INTIICTI3_SHIFT            (23u)
+#define INTC_ICDABR6_INTIICSPI3_SHIFT           (24u)
+#define INTC_ICDABR6_INTIICSTI3_SHIFT           (25u)
+#define INTC_ICDABR6_INTIICNAKI3_SHIFT          (26u)
+#define INTC_ICDABR6_INTIICALI3_SHIFT           (27u)
+#define INTC_ICDABR6_INTIICTMOI3_SHIFT          (28u)
+#define INTC_ICDABR6_BRI0_SHIFT                 (29u)
+#define INTC_ICDABR6_ERI0_SHIFT                 (30u)
+#define INTC_ICDABR6_RXI0_SHIFT                 (31u)
+
+#define INTC_ICDABR7_TXI0_SHIFT                 (0u)
+#define INTC_ICDABR7_BRI1_SHIFT                 (1u)
+#define INTC_ICDABR7_ERI1_SHIFT                 (2u)
+#define INTC_ICDABR7_RXI1_SHIFT                 (3u)
+#define INTC_ICDABR7_TXI1_SHIFT                 (4u)
+#define INTC_ICDABR7_BRI2_SHIFT                 (5u)
+#define INTC_ICDABR7_ERI2_SHIFT                 (6u)
+#define INTC_ICDABR7_RXI2_SHIFT                 (7u)
+#define INTC_ICDABR7_TXI2_SHIFT                 (8u)
+#define INTC_ICDABR7_BRI3_SHIFT                 (9u)
+#define INTC_ICDABR7_ERI3_SHIFT                 (10u)
+#define INTC_ICDABR7_RXI3_SHIFT                 (11u)
+#define INTC_ICDABR7_TXI3_SHIFT                 (12u)
+#define INTC_ICDABR7_BRI4_SHIFT                 (13u)
+#define INTC_ICDABR7_ERI4_SHIFT                 (14u)
+#define INTC_ICDABR7_RXI4_SHIFT                 (15u)
+#define INTC_ICDABR7_TXI4_SHIFT                 (16u)
+#define INTC_ICDABR7_BRI5_SHIFT                 (17u)
+#define INTC_ICDABR7_ERI5_SHIFT                 (18u)
+#define INTC_ICDABR7_RXI5_SHIFT                 (19u)
+#define INTC_ICDABR7_TXI5_SHIFT                 (20u)
+#define INTC_ICDABR7_BRI6_SHIFT                 (21u)
+#define INTC_ICDABR7_ERI6_SHIFT                 (22u)
+#define INTC_ICDABR7_RXI6_SHIFT                 (23u)
+#define INTC_ICDABR7_TXI6_SHIFT                 (24u)
+#define INTC_ICDABR7_BRI7_SHIFT                 (25u)
+#define INTC_ICDABR7_ERI7_SHIFT                 (26u)
+#define INTC_ICDABR7_RXI7_SHIFT                 (27u)
+#define INTC_ICDABR7_TXI7_SHIFT                 (28u)
+#define INTC_ICDABR7_INTRCANGERR_SHIFT          (29u)
+#define INTC_ICDABR7_INTRCANGRECC_SHIFT         (30u)
+#define INTC_ICDABR7_INTRCAN0REC_SHIFT          (31u)
+
+#define INTC_ICDABR8_INTRCAN0ERR_SHIFT          (0u)
+#define INTC_ICDABR8_INTRCAN0TRX_SHIFT          (1u)
+#define INTC_ICDABR8_INTRCAN1REC_SHIFT          (2u)
+#define INTC_ICDABR8_INTRCAN1ERR_SHIFT          (3u)
+#define INTC_ICDABR8_INTRCAN1TRX_SHIFT          (4u)
+#define INTC_ICDABR8_INTRCAN2REC_SHIFT          (5u)
+#define INTC_ICDABR8_INTRCAN2ERR_SHIFT          (6u)
+#define INTC_ICDABR8_INTRCAN2TRX_SHIFT          (7u)
+#define INTC_ICDABR8_INTRCAN3REC_SHIFT          (8u)
+#define INTC_ICDABR8_INTRCAN3ERR_SHIFT          (9u)
+#define INTC_ICDABR8_INTRCAN3TRX_SHIFT          (10u)
+#define INTC_ICDABR8_INTRCAN4REC_SHIFT          (11u)
+#define INTC_ICDABR8_INTRCAN4ERR_SHIFT          (12u)
+#define INTC_ICDABR8_INTRCAN4TRX_SHIFT          (13u)
+#define INTC_ICDABR8_SPEI0_SHIFT                (14u)
+#define INTC_ICDABR8_SPRI0_SHIFT                (15u)
+#define INTC_ICDABR8_SPTI0_SHIFT                (16u)
+#define INTC_ICDABR8_SPEI1_SHIFT                (17u)
+#define INTC_ICDABR8_SPRI1_SHIFT                (18u)
+#define INTC_ICDABR8_SPTI1_SHIFT                (19u)
+#define INTC_ICDABR8_SPEI2_SHIFT                (20u)
+#define INTC_ICDABR8_SPRI2_SHIFT                (21u)
+#define INTC_ICDABR8_SPTI2_SHIFT                (22u)
+#define INTC_ICDABR8_SPEI3_SHIFT                (23u)
+#define INTC_ICDABR8_SPRI3_SHIFT                (24u)
+#define INTC_ICDABR8_SPTI3_SHIFT                (25u)
+#define INTC_ICDABR8_SPEI4_SHIFT                (26u)
+#define INTC_ICDABR8_SPRI4_SHIFT                (27u)
+#define INTC_ICDABR8_SPTI4_SHIFT                (28u)
+#define INTC_ICDABR8_IEBBTD_SHIFT               (29u)
+#define INTC_ICDABR8_IEBBTERR_SHIFT             (30u)
+#define INTC_ICDABR8_IEBBTSTA_SHIFT             (31u)
+
+#define INTC_ICDABR9_IEBBTV_SHIFT               (0u)
+#define INTC_ICDABR9_ISY_SHIFT                  (1u)
+#define INTC_ICDABR9_IERR_SHIFT                 (2u)
+#define INTC_ICDABR9_ITARG_SHIFT                (3u)
+#define INTC_ICDABR9_ISEC_SHIFT                 (4u)
+#define INTC_ICDABR9_IBUF_SHIFT                 (5u)
+#define INTC_ICDABR9_IREADY_SHIFT               (6u)
+#define INTC_ICDABR9_FLSTE_SHIFT                (7u)
+#define INTC_ICDABR9_FLTENDI_SHIFT              (8u)
+#define INTC_ICDABR9_FLTREQ0I_SHIFT             (9u)
+#define INTC_ICDABR9_FLTREQ1I_SHIFT             (10u)
+#define INTC_ICDABR9_MMC0_SHIFT                 (11u)
+#define INTC_ICDABR9_MMC1_SHIFT                 (12u)
+#define INTC_ICDABR9_MMC2_SHIFT                 (13u)
+#define INTC_ICDABR9_SDHI0_3_SHIFT              (14u)
+#define INTC_ICDABR9_SDHI0_0_SHIFT              (15u)
+#define INTC_ICDABR9_SDHI0_1_SHIFT              (16u)
+#define INTC_ICDABR9_SDHI1_3_SHIFT              (17u)
+#define INTC_ICDABR9_SDHI1_0_SHIFT              (18u)
+#define INTC_ICDABR9_SDHI1_1_SHIFT              (19u)
+#define INTC_ICDABR9_ARM_SHIFT                  (20u)
+#define INTC_ICDABR9_PRD_SHIFT                  (21u)
+#define INTC_ICDABR9_CUP_SHIFT                  (22u)
+#define INTC_ICDABR9_SCUAI0_SHIFT               (23u)
+#define INTC_ICDABR9_SCUAI1_SHIFT               (24u)
+#define INTC_ICDABR9_SCUFDI0_SHIFT              (25u)
+#define INTC_ICDABR9_SCUFDI1_SHIFT              (26u)
+#define INTC_ICDABR9_SCUFDI2_SHIFT              (27u)
+#define INTC_ICDABR9_SCUFDI3_SHIFT              (28u)
+#define INTC_ICDABR9_SCUFUI0_SHIFT              (29u)
+#define INTC_ICDABR9_SCUFUI1_SHIFT              (30u)
+#define INTC_ICDABR9_SCUFUI2_SHIFT              (31u)
+
+#define INTC_ICDABR10_SCUFUI3_SHIFT             (0u)
+#define INTC_ICDABR10_SCUDVI0_SHIFT             (1u)
+#define INTC_ICDABR10_SCUDVI1_SHIFT             (2u)
+#define INTC_ICDABR10_SCUDVI2_SHIFT             (3u)
+#define INTC_ICDABR10_SCUDVI3_SHIFT             (4u)
+#define INTC_ICDABR10_MLB_CINT_SHIFT            (5u)
+#define INTC_ICDABR10_MLB_SINT_SHIFT            (6u)
+#define INTC_ICDABR10_DRC0_SHIFT                (7u)
+#define INTC_ICDABR10_DRC1_SHIFT                (8u)
+#define INTC_ICDABR10_LINI0_INT_T_SHIFT         (11u)
+#define INTC_ICDABR10_LINI0_INT_R_SHIFT         (12u)
+#define INTC_ICDABR10_LINI0_INT_S_SHIFT         (13u)
+#define INTC_ICDABR10_LINI0_INT_M_SHIFT         (14u)
+#define INTC_ICDABR10_LINI1_INT_T_SHIFT         (15u)
+#define INTC_ICDABR10_LINI1_INT_R_SHIFT         (16u)
+#define INTC_ICDABR10_LINI1_INT_S_SHIFT         (17u)
+#define INTC_ICDABR10_LINI1_INT_M_SHIFT         (18u)
+#define INTC_ICDABR10_ERI0_SHIFT                (27u)
+#define INTC_ICDABR10_RXI0_SHIFT                (28u)
+#define INTC_ICDABR10_TXI0_SHIFT                (29u)
+#define INTC_ICDABR10_TEI0_SHIFT                (30u)
+#define INTC_ICDABR10_ERI1_SHIFT                (31u)
+
+#define INTC_ICDABR11_RXI1_SHIFT                (0u)
+#define INTC_ICDABR11_TXI1_SHIFT                (1u)
+#define INTC_ICDABR11_TEI1_SHIFT                (2u)
+#define INTC_ICDABR11_AVBI_DATA_SHIFT           (3u)
+#define INTC_ICDABR11_AVBI_ERROR_SHIFT          (4u)
+#define INTC_ICDABR11_AVBI_MANAGE_SHIFT         (5u)
+#define INTC_ICDABR11_AVBI_MAC_SHIFT            (6u)
+#define INTC_ICDABR11_ETHERI_SHIFT              (7u)
+#define INTC_ICDABR11_CEUI_SHIFT                (12u)
+#define INTC_ICDABR11_H2XMLB_ERRINT_SHIFT       (29u)
+#define INTC_ICDABR11_H2XIC1_ERRINT_SHIFT       (30u)
+#define INTC_ICDABR11_X2HPERI1_ERRINT_SHIFT     (31u)
+
+#define INTC_ICDABR12_X2HPERI2_ERRINT_SHIFT     (0u)
+#define INTC_ICDABR12_X2HPERI34_ERRINT_SHIFT    (1u)
+#define INTC_ICDABR12_X2HPERI5_ERRINT_SHIFT     (2u)
+#define INTC_ICDABR12_X2HPERI67_ERRINT_SHIFT    (3u)
+#define INTC_ICDABR12_X2HDBGR_ERRINT_SHIFT      (4u)
+#define INTC_ICDABR12_X2HBSC_ERRINT_SHIFT       (5u)
+#define INTC_ICDABR12_X2HSPI1_ERRINT_SHIFT      (6u)
+#define INTC_ICDABR12_X2HSPI2_ERRINT_SHIFT      (7u)
+#define INTC_ICDABR12_PRRI_SHIFT                (8u)
+#define INTC_ICDABR12_IFEI0_SHIFT               (9u)
+#define INTC_ICDABR12_OFFI0_SHIFT               (10u)
+#define INTC_ICDABR12_PFVEI0_SHIFT              (11u)
+#define INTC_ICDABR12_IFEI1_SHIFT               (12u)
+#define INTC_ICDABR12_OFFI1_SHIFT               (13u)
+#define INTC_ICDABR12_PFVEI1_SHIFT              (14u)
+
+#define INTC_ICDABR13_TINT0_SHIFT               (0u)
+#define INTC_ICDABR13_TINT1_SHIFT               (1u)
+#define INTC_ICDABR13_TINT2_SHIFT               (2u)
+#define INTC_ICDABR13_TINT3_SHIFT               (3u)
+#define INTC_ICDABR13_TINT4_SHIFT               (4u)
+#define INTC_ICDABR13_TINT5_SHIFT               (5u)
+#define INTC_ICDABR13_TINT6_SHIFT               (6u)
+#define INTC_ICDABR13_TINT7_SHIFT               (7u)
+#define INTC_ICDABR13_TINT8_SHIFT               (8u)
+#define INTC_ICDABR13_TINT9_SHIFT               (9u)
+#define INTC_ICDABR13_TINT10_SHIFT              (10u)
+#define INTC_ICDABR13_TINT11_SHIFT              (11u)
+#define INTC_ICDABR13_TINT12_SHIFT              (12u)
+#define INTC_ICDABR13_TINT13_SHIFT              (13u)
+#define INTC_ICDABR13_TINT14_SHIFT              (14u)
+#define INTC_ICDABR13_TINT15_SHIFT              (15u)
+#define INTC_ICDABR13_TINT16_SHIFT              (16u)
+#define INTC_ICDABR13_TINT17_SHIFT              (17u)
+#define INTC_ICDABR13_TINT18_SHIFT              (18u)
+#define INTC_ICDABR13_TINT19_SHIFT              (19u)
+#define INTC_ICDABR13_TINT20_SHIFT              (20u)
+#define INTC_ICDABR13_TINT21_SHIFT              (21u)
+#define INTC_ICDABR13_TINT22_SHIFT              (22u)
+#define INTC_ICDABR13_TINT23_SHIFT              (23u)
+#define INTC_ICDABR13_TINT24_SHIFT              (24u)
+#define INTC_ICDABR13_TINT25_SHIFT              (25u)
+#define INTC_ICDABR13_TINT26_SHIFT              (26u)
+#define INTC_ICDABR13_TINT27_SHIFT              (27u)
+#define INTC_ICDABR13_TINT28_SHIFT              (28u)
+#define INTC_ICDABR13_TINT29_SHIFT              (29u)
+#define INTC_ICDABR13_TINT30_SHIFT              (30u)
+#define INTC_ICDABR13_TINT31_SHIFT              (31u)
+
+#define INTC_ICDABR14_TINT32_SHIFT              (0u)
+#define INTC_ICDABR14_TINT33_SHIFT              (1u)
+#define INTC_ICDABR14_TINT34_SHIFT              (2u)
+#define INTC_ICDABR14_TINT35_SHIFT              (3u)
+#define INTC_ICDABR14_TINT36_SHIFT              (4u)
+#define INTC_ICDABR14_TINT37_SHIFT              (5u)
+#define INTC_ICDABR14_TINT38_SHIFT              (6u)
+#define INTC_ICDABR14_TINT39_SHIFT              (7u)
+#define INTC_ICDABR14_TINT40_SHIFT              (8u)
+#define INTC_ICDABR14_TINT41_SHIFT              (9u)
+#define INTC_ICDABR14_TINT42_SHIFT              (10u)
+#define INTC_ICDABR14_TINT43_SHIFT              (11u)
+#define INTC_ICDABR14_TINT44_SHIFT              (12u)
+#define INTC_ICDABR14_TINT45_SHIFT              (13u)
+#define INTC_ICDABR14_TINT46_SHIFT              (14u)
+#define INTC_ICDABR14_TINT47_SHIFT              (15u)
+#define INTC_ICDABR14_TINT48_SHIFT              (16u)
+#define INTC_ICDABR14_TINT49_SHIFT              (17u)
+#define INTC_ICDABR14_TINT50_SHIFT              (18u)
+#define INTC_ICDABR14_TINT51_SHIFT              (19u)
+#define INTC_ICDABR14_TINT52_SHIFT              (20u)
+#define INTC_ICDABR14_TINT53_SHIFT              (21u)
+#define INTC_ICDABR14_TINT54_SHIFT              (22u)
+#define INTC_ICDABR14_TINT55_SHIFT              (23u)
+#define INTC_ICDABR14_TINT56_SHIFT              (24u)
+#define INTC_ICDABR14_TINT57_SHIFT              (25u)
+#define INTC_ICDABR14_TINT58_SHIFT              (26u)
+#define INTC_ICDABR14_TINT59_SHIFT              (27u)
+#define INTC_ICDABR14_TINT60_SHIFT              (28u)
+#define INTC_ICDABR14_TINT61_SHIFT              (29u)
+#define INTC_ICDABR14_TINT62_SHIFT              (30u)
+#define INTC_ICDABR14_TINT63_SHIFT              (31u)
+
+#define INTC_ICDABR15_TINT64_SHIFT              (0u)
+#define INTC_ICDABR15_TINT65_SHIFT              (1u)
+#define INTC_ICDABR15_TINT66_SHIFT              (2u)
+#define INTC_ICDABR15_TINT67_SHIFT              (3u)
+#define INTC_ICDABR15_TINT68_SHIFT              (4u)
+#define INTC_ICDABR15_TINT69_SHIFT              (5u)
+#define INTC_ICDABR15_TINT70_SHIFT              (6u)
+#define INTC_ICDABR15_TINT71_SHIFT              (7u)
+#define INTC_ICDABR15_TINT72_SHIFT              (8u)
+#define INTC_ICDABR15_TINT73_SHIFT              (9u)
+#define INTC_ICDABR15_TINT74_SHIFT              (10u)
+#define INTC_ICDABR15_TINT75_SHIFT              (11u)
+#define INTC_ICDABR15_TINT76_SHIFT              (12u)
+#define INTC_ICDABR15_TINT77_SHIFT              (13u)
+#define INTC_ICDABR15_TINT78_SHIFT              (14u)
+#define INTC_ICDABR15_TINT79_SHIFT              (15u)
+#define INTC_ICDABR15_TINT80_SHIFT              (16u)
+#define INTC_ICDABR15_TINT81_SHIFT              (17u)
+#define INTC_ICDABR15_TINT82_SHIFT              (18u)
+#define INTC_ICDABR15_TINT83_SHIFT              (19u)
+#define INTC_ICDABR15_TINT84_SHIFT              (20u)
+#define INTC_ICDABR15_TINT85_SHIFT              (21u)
+#define INTC_ICDABR15_TINT86_SHIFT              (22u)
+#define INTC_ICDABR15_TINT87_SHIFT              (23u)
+#define INTC_ICDABR15_TINT88_SHIFT              (24u)
+#define INTC_ICDABR15_TINT89_SHIFT              (25u)
+#define INTC_ICDABR15_TINT90_SHIFT              (26u)
+#define INTC_ICDABR15_TINT91_SHIFT              (27u)
+#define INTC_ICDABR15_TINT92_SHIFT              (28u)
+#define INTC_ICDABR15_TINT93_SHIFT              (29u)
+#define INTC_ICDABR15_TINT94_SHIFT              (30u)
+#define INTC_ICDABR15_TINT95_SHIFT              (31u)
+
+#define INTC_ICDABR16_TINT96_SHIFT              (0u)
+#define INTC_ICDABR16_TINT97_SHIFT              (1u)
+#define INTC_ICDABR16_TINT98_SHIFT              (2u)
+#define INTC_ICDABR16_TINT99_SHIFT              (3u)
+#define INTC_ICDABR16_TINT100_SHIFT             (4u)
+#define INTC_ICDABR16_TINT101_SHIFT             (5u)
+#define INTC_ICDABR16_TINT102_SHIFT             (6u)
+#define INTC_ICDABR16_TINT103_SHIFT             (7u)
+#define INTC_ICDABR16_TINT104_SHIFT             (8u)
+#define INTC_ICDABR16_TINT105_SHIFT             (9u)
+#define INTC_ICDABR16_TINT106_SHIFT             (10u)
+#define INTC_ICDABR16_TINT107_SHIFT             (11u)
+#define INTC_ICDABR16_TINT108_SHIFT             (12u)
+#define INTC_ICDABR16_TINT109_SHIFT             (13u)
+#define INTC_ICDABR16_TINT110_SHIFT             (14u)
+#define INTC_ICDABR16_TINT111_SHIFT             (15u)
+#define INTC_ICDABR16_TINT112_SHIFT             (16u)
+#define INTC_ICDABR16_TINT113_SHIFT             (17u)
+#define INTC_ICDABR16_TINT114_SHIFT             (18u)
+#define INTC_ICDABR16_TINT115_SHIFT             (19u)
+#define INTC_ICDABR16_TINT116_SHIFT             (20u)
+#define INTC_ICDABR16_TINT117_SHIFT             (21u)
+#define INTC_ICDABR16_TINT118_SHIFT             (22u)
+#define INTC_ICDABR16_TINT119_SHIFT             (23u)
+#define INTC_ICDABR16_TINT120_SHIFT             (24u)
+#define INTC_ICDABR16_TINT121_SHIFT             (25u)
+#define INTC_ICDABR16_TINT122_SHIFT             (26u)
+#define INTC_ICDABR16_TINT123_SHIFT             (27u)
+#define INTC_ICDABR16_TINT124_SHIFT             (28u)
+#define INTC_ICDABR16_TINT125_SHIFT             (29u)
+#define INTC_ICDABR16_TINT126_SHIFT             (30u)
+#define INTC_ICDABR16_TINT127_SHIFT             (31u)
+
+#define INTC_ICDABR17_TINT128_SHIFT             (0u)
+#define INTC_ICDABR17_TINT129_SHIFT             (1u)
+#define INTC_ICDABR17_TINT130_SHIFT             (2u)
+#define INTC_ICDABR17_TINT131_SHIFT             (3u)
+#define INTC_ICDABR17_TINT132_SHIFT             (4u)
+#define INTC_ICDABR17_TINT133_SHIFT             (5u)
+#define INTC_ICDABR17_TINT134_SHIFT             (6u)
+#define INTC_ICDABR17_TINT135_SHIFT             (7u)
+#define INTC_ICDABR17_TINT136_SHIFT             (8u)
+#define INTC_ICDABR17_TINT137_SHIFT             (9u)
+#define INTC_ICDABR17_TINT138_SHIFT             (10u)
+#define INTC_ICDABR17_TINT139_SHIFT             (11u)
+#define INTC_ICDABR17_TINT140_SHIFT             (12u)
+#define INTC_ICDABR17_TINT141_SHIFT             (13u)
+#define INTC_ICDABR17_TINT142_SHIFT             (14u)
+#define INTC_ICDABR17_TINT143_SHIFT             (15u)
+#define INTC_ICDABR17_TINT144_SHIFT             (16u)
+#define INTC_ICDABR17_TINT145_SHIFT             (17u)
+#define INTC_ICDABR17_TINT146_SHIFT             (18u)
+#define INTC_ICDABR17_TINT147_SHIFT             (19u)
+#define INTC_ICDABR17_TINT148_SHIFT             (20u)
+#define INTC_ICDABR17_TINT149_SHIFT             (21u)
+#define INTC_ICDABR17_TINT150_SHIFT             (22u)
+#define INTC_ICDABR17_TINT151_SHIFT             (23u)
+#define INTC_ICDABR17_TINT152_SHIFT             (24u)
+#define INTC_ICDABR17_TINT153_SHIFT             (25u)
+#define INTC_ICDABR17_TINT154_SHIFT             (26u)
+#define INTC_ICDABR17_TINT155_SHIFT             (27u)
+#define INTC_ICDABR17_TINT156_SHIFT             (28u)
+#define INTC_ICDABR17_TINT157_SHIFT             (29u)
+#define INTC_ICDABR17_TINT158_SHIFT             (30u)
+#define INTC_ICDABR17_TINT159_SHIFT             (31u)
+
+#define INTC_ICDABR18_TINT160_SHIFT             (0u)
+#define INTC_ICDABR18_TINT161_SHIFT             (1u)
+#define INTC_ICDABR18_TINT162_SHIFT             (2u)
+#define INTC_ICDABR18_TINT163_SHIFT             (3u)
+#define INTC_ICDABR18_TINT164_SHIFT             (4u)
+#define INTC_ICDABR18_TINT165_SHIFT             (5u)
+#define INTC_ICDABR18_TINT166_SHIFT             (6u)
+#define INTC_ICDABR18_TINT167_SHIFT             (7u)
+#define INTC_ICDABR18_TINT168_SHIFT             (8u)
+#define INTC_ICDABR18_TINT169_SHIFT             (9u)
+#define INTC_ICDABR18_TINT170_SHIFT             (10u)
+
+#define INTC_ICDIPR0_SW0_SHIFT                  (0u)
+#define INTC_ICDIPR0_SW1_SHIFT                  (8u)
+#define INTC_ICDIPR0_SW2_SHIFT                  (16u)
+#define INTC_ICDIPR0_SW3_SHIFT                  (24u)
+
+#define INTC_ICDIPR1_SW4_SHIFT                  (0u)
+#define INTC_ICDIPR1_SW5_SHIFT                  (8u)
+#define INTC_ICDIPR1_SW6_SHIFT                  (16u)
+#define INTC_ICDIPR1_SW7_SHIFT                  (24u)
+
+#define INTC_ICDIPR2_SW8_SHIFT                  (0u)
+#define INTC_ICDIPR2_SW9_SHIFT                  (8u)
+#define INTC_ICDIPR2_SW10_SHIFT                 (16u)
+#define INTC_ICDIPR2_SW11_SHIFT                 (24u)
+
+#define INTC_ICDIPR3_SW12_SHIFT                 (0u)
+#define INTC_ICDIPR3_SW13_SHIFT                 (8u)
+#define INTC_ICDIPR3_SW14_SHIFT                 (16u)
+#define INTC_ICDIPR3_SW15_SHIFT                 (24u)
+
+#define INTC_ICDIPR4_PMUIRQ0_SHIFT              (0u)
+#define INTC_ICDIPR4_COMMRX0_SHIFT              (8u)
+#define INTC_ICDIPR4_COMMTX0_SHIFT              (16u)
+#define INTC_ICDIPR4_CTIIRQ0_SHIFT              (24u)
+
+#define INTC_ICDIPR8_IRQ0_SHIFT                 (0u)
+#define INTC_ICDIPR8_IRQ1_SHIFT                 (8u)
+#define INTC_ICDIPR8_IRQ2_SHIFT                 (16u)
+#define INTC_ICDIPR8_IRQ3_SHIFT                 (24u)
+
+#define INTC_ICDIPR9_IRQ4_SHIFT                 (0u)
+#define INTC_ICDIPR9_IRQ5_SHIFT                 (8u)
+#define INTC_ICDIPR9_IRQ6_SHIFT                 (16u)
+#define INTC_ICDIPR9_IRQ7_SHIFT                 (24u)
+
+#define INTC_ICDIPR10_PL310ERR_SHIFT            (0u)
+#define INTC_ICDIPR10_DMAINT0_SHIFT             (8u)
+#define INTC_ICDIPR10_DMAINT1_SHIFT             (16u)
+#define INTC_ICDIPR10_DMAINT2_SHIFT             (24u)
+
+#define INTC_ICDIPR11_DMAINT3_SHIFT             (0u)
+#define INTC_ICDIPR11_DMAINT4_SHIFT             (8u)
+#define INTC_ICDIPR11_DMAINT5_SHIFT             (16u)
+#define INTC_ICDIPR11_DMAINT6_SHIFT             (24u)
+
+#define INTC_ICDIPR12_DMAINT7_SHIFT             (0u)
+#define INTC_ICDIPR12_DMAINT8_SHIFT             (8u)
+#define INTC_ICDIPR12_DMAINT9_SHIFT             (16u)
+#define INTC_ICDIPR12_DMAINT10_SHIFT            (24u)
+
+#define INTC_ICDIPR13_DMAINT11_SHIFT            (0u)
+#define INTC_ICDIPR13_DMAINT12_SHIFT            (8u)
+#define INTC_ICDIPR13_DMAINT13_SHIFT            (16u)
+#define INTC_ICDIPR13_DMAINT14_SHIFT            (24u)
+
+#define INTC_ICDIPR14_DMAINT15_SHIFT            (0u)
+#define INTC_ICDIPR14_DMAERR_SHIFT              (8u)
+
+#define INTC_ICDIPR18_USBI0_SHIFT               (8u)
+#define INTC_ICDIPR18_USBI1_SHIFT               (16u)
+#define INTC_ICDIPR18_S0_VI_VSYNC0_SHIFT        (24u)
+
+#define INTC_ICDIPR19_S0_LO_VSYNC0_SHIFT        (0u)
+#define INTC_ICDIPR19_S0_VSYNCERR0_SHIFT        (8u)
+#define INTC_ICDIPR19_GR3_VLINE0_SHIFT          (16u)
+#define INTC_ICDIPR19_S0_VFIELD0_SHIFT          (24u)
+
+#define INTC_ICDIPR20_IV1_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDIPR20_IV3_VBUFERR0_SHIFT        (8u)
+#define INTC_ICDIPR20_IV5_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDIPR20_IV6_VBUFERR0_SHIFT        (24u)
+
+#define INTC_ICDIPR21_S0_WLINE0_SHIFT           (0u)
+#define INTC_ICDIPR21_S1_VI_VSYNC0_SHIFT        (8u)
+#define INTC_ICDIPR21_S1_LO_VSYNC0_SHIFT        (16u)
+#define INTC_ICDIPR21_S1_VSYNCERR0_SHIFT        (24u)
+
+#define INTC_ICDIPR22_S1_VFIELD0_SHIFT          (0u)
+#define INTC_ICDIPR22_IV2_VBUFERR0_SHIFT        (8u)
+#define INTC_ICDIPR22_IV4_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDIPR22_S1_WLINE0_SHIFT           (24u)
+
+#define INTC_ICDIPR23_OIR_VI_VSYNC0_SHIFT       (0u)
+#define INTC_ICDIPR23_OIR_LO_VSYNC0_SHIFT       (8u)
+#define INTC_ICDIPR23_OIR_VSYNCERR0_SHIFT       (16u)
+#define INTC_ICDIPR23_OIR_VFIELD0_SHIFT         (24u)
+
+#define INTC_ICDIPR24_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDIPR24_IV8_VBUFERR0_SHIFT        (8u)
+#define INTC_ICDIPR24_S0_VI_VSYNC1_SHIFT        (24u)
+
+#define INTC_ICDIPR25_S0_LO_VSYNC1_SHIFT        (0u)
+#define INTC_ICDIPR25_S0_VSYNCERR1_SHIFT        (8u)
+#define INTC_ICDIPR25_GR3_VLINE1_SHIFT          (16u)
+#define INTC_ICDIPR25_S0_VFIELD1_SHIFT          (24u)
+
+#define INTC_ICDIPR26_IV1_VBUFERR1_SHIFT        (0u)
+#define INTC_ICDIPR26_IV3_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDIPR26_IV5_VBUFERR1_SHIFT        (16u)
+#define INTC_ICDIPR26_IV6_VBUFERR1_SHIFT        (24u)
+
+#define INTC_ICDIPR27_S0_WLINE1_SHIFT           (0u)
+#define INTC_ICDIPR27_S1_VI_VSYNC1_SHIFT        (8u)
+#define INTC_ICDIPR27_S1_LO_VSYNC1_SHIFT        (16u)
+#define INTC_ICDIPR27_S1_VSYNCERR1_SHIFT        (24u)
+
+#define INTC_ICDIPR28_S1_VFIELD1_SHIFT          (0u)
+#define INTC_ICDIPR28_IV2_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDIPR28_IV4_VBUFERR1_SHIFT        (16u)
+#define INTC_ICDIPR28_S1_WLINE1_SHIFT           (24u)
+
+#define INTC_ICDIPR29_OIR_VI_VSYNC1_SHIFT       (0u)
+#define INTC_ICDIPR29_OIR_LO_VSYNC1_SHIFT       (8u)
+#define INTC_ICDIPR29_OIR_VLINE1_SHIFT          (16u)
+#define INTC_ICDIPR29_OIR_VFIELD1_SHIFT         (24u)
+
+#define INTC_ICDIPR30_IV7_VBUFERR1_SHIFT        (0u)
+#define INTC_ICDIPR30_IV8_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDIPR30_IMRDI_SHIFT               (24u)
+
+#define INTC_ICDIPR31_IMR2I0_SHIFT              (0u)
+#define INTC_ICDIPR31_IMR2I1_SHIFT              (8u)
+#define INTC_ICDIPR31_JEDI_SHIFT                (16u)
+#define INTC_ICDIPR31_JDTI_SHIFT                (24u)
+
+#define INTC_ICDIPR32_CMP0_SHIFT                (0u)
+#define INTC_ICDIPR32_CMP1_SHIFT                (8u)
+#define INTC_ICDIPR32_INT0_SHIFT                (16u)
+#define INTC_ICDIPR32_INT1_SHIFT                (24u)
+
+#define INTC_ICDIPR33_INT2_SHIFT                (0u)
+#define INTC_ICDIPR33_INT3_SHIFT                (8u)
+#define INTC_ICDIPR33_OSTM0TINT_SHIFT           (16u)
+#define INTC_ICDIPR33_OSTM1TINT_SHIFT           (24u)
+
+#define INTC_ICDIPR34_CMI_SHIFT                 (0u)
+#define INTC_ICDIPR34_WTOUT_SHIFT               (8u)
+#define INTC_ICDIPR34_ITI_SHIFT                 (16u)
+#define INTC_ICDIPR34_TGI0A_SHIFT               (24u)
+
+#define INTC_ICDIPR35_TGI0B_SHIFT               (0u)
+#define INTC_ICDIPR35_TGI0C_SHIFT               (8u)
+#define INTC_ICDIPR35_TGI0D_SHIFT               (16u)
+#define INTC_ICDIPR35_TGI0V_SHIFT               (24u)
+
+#define INTC_ICDIPR36_TGI0E_SHIFT               (0u)
+#define INTC_ICDIPR36_TGI0F_SHIFT               (8u)
+#define INTC_ICDIPR36_TGI1A_SHIFT               (16u)
+#define INTC_ICDIPR36_TGI1B_SHIFT               (24u)
+
+#define INTC_ICDIPR37_TGI1V_SHIFT               (0u)
+#define INTC_ICDIPR37_TGI1U_SHIFT               (8u)
+#define INTC_ICDIPR37_TGI2A_SHIFT               (16u)
+#define INTC_ICDIPR37_TGI2B_SHIFT               (24u)
+
+#define INTC_ICDIPR38_TGI2V_SHIFT               (0u)
+#define INTC_ICDIPR38_TGI2U_SHIFT               (8u)
+#define INTC_ICDIPR38_TGI3A_SHIFT               (16u)
+#define INTC_ICDIPR38_TGI3B_SHIFT               (24u)
+
+#define INTC_ICDIPR39_TGI3C_SHIFT               (0u)
+#define INTC_ICDIPR39_TGI3D_SHIFT               (8u)
+#define INTC_ICDIPR39_TGI3V_SHIFT               (16u)
+#define INTC_ICDIPR39_TGI4A_SHIFT               (24u)
+
+#define INTC_ICDIPR40_TGI4B_SHIFT               (0u)
+#define INTC_ICDIPR40_TGI4C_SHIFT               (8u)
+#define INTC_ICDIPR40_TGI4D_SHIFT               (16u)
+#define INTC_ICDIPR40_TGI4V_SHIFT               (24u)
+
+#define INTC_ICDIPR41_CMI1_SHIFT                (0u)
+#define INTC_ICDIPR41_CMI2_SHIFT                (8u)
+#define INTC_ICDIPR41_SGDEI0_SHIFT              (16u)
+#define INTC_ICDIPR41_SGDEI1_SHIFT              (24u)
+
+#define INTC_ICDIPR42_SGDEI2_SHIFT              (0u)
+#define INTC_ICDIPR42_SGDEI3_SHIFT              (8u)
+#define INTC_ICDIPR42_ADI_SHIFT                 (16u)
+#define INTC_ICDIPR42_LMTI_SHIFT                (24u)
+
+#define INTC_ICDIPR43_SSII0_SHIFT               (0u)
+#define INTC_ICDIPR43_SSIRXI0_SHIFT             (8u)
+#define INTC_ICDIPR43_SSITXI0_SHIFT             (16u)
+#define INTC_ICDIPR43_SSII1_SHIFT               (24u)
+
+#define INTC_ICDIPR44_SSIRXI1_SHIFT             (0u)
+#define INTC_ICDIPR44_SSITXI1_SHIFT             (8u)
+#define INTC_ICDIPR44_SSII2_SHIFT               (16u)
+#define INTC_ICDIPR44_SSIRTI2_SHIFT             (24u)
+
+#define INTC_ICDIPR45_SSII3_SHIFT               (0u)
+#define INTC_ICDIPR45_SSIRXI3_SHIFT             (8u)
+#define INTC_ICDIPR45_SSITXI3_SHIFT             (16u)
+#define INTC_ICDIPR45_SSII4_SHIFT               (24u)
+
+#define INTC_ICDIPR46_SSIRTI4_SHIFT             (0u)
+#define INTC_ICDIPR46_SSII5_SHIFT               (8u)
+#define INTC_ICDIPR46_SSIRXI5_SHIFT             (16u)
+#define INTC_ICDIPR46_SSITXI5_SHIFT             (24u)
+
+#define INTC_ICDIPR47_SPDIFI_SHIFT              (0u)
+#define INTC_ICDIPR47_INTIICTEI0_SHIFT          (8u)
+#define INTC_ICDIPR47_INTIICRI0_SHIFT           (16u)
+#define INTC_ICDIPR47_INTIICTI0_SHIFT           (24u)
+
+#define INTC_ICDIPR48_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDIPR48_INTIICSTI0_SHIFT          (8u)
+#define INTC_ICDIPR48_INTIICNAKI0_SHIFT         (16u)
+#define INTC_ICDIPR48_INTIICALI0_SHIFT          (24u)
+
+#define INTC_ICDIPR49_INTIICTMOI0_SHIFT         (0u)
+#define INTC_ICDIPR49_INTIICTEI1_SHIFT          (8u)
+#define INTC_ICDIPR49_INTIICRI1_SHIFT           (16u)
+#define INTC_ICDIPR49_INTIICTI1_SHIFT           (24u)
+
+#define INTC_ICDIPR50_INTIICSPI1_SHIFT          (0u)
+#define INTC_ICDIPR50_INTIICSTI1_SHIFT          (8u)
+#define INTC_ICDIPR50_INTIICNAKI1_SHIFT         (16u)
+#define INTC_ICDIPR50_INTIICALI1_SHIFT          (24u)
+
+#define INTC_ICDIPR51_INTIICTMOI1_SHIFT         (0u)
+#define INTC_ICDIPR51_INTIICTEI2_SHIFT          (8u)
+#define INTC_ICDIPR51_INTIICRI2_SHIFT           (16u)
+#define INTC_ICDIPR51_INTIICTI2_SHIFT           (24u)
+
+#define INTC_ICDIPR52_INTIICSPI2_SHIFT          (0u)
+#define INTC_ICDIPR52_INTIICSTI2_SHIFT          (8u)
+#define INTC_ICDIPR52_INTIICNAKI2_SHIFT         (16u)
+#define INTC_ICDIPR52_INTIICALI2_SHIFT          (24u)
+
+#define INTC_ICDIPR53_INTIICTMOI2_SHIFT         (0u)
+#define INTC_ICDIPR53_INTIICTEI3_SHIFT          (8u)
+#define INTC_ICDIPR53_INTIICRI3_SHIFT           (16u)
+#define INTC_ICDIPR53_INTIICTI3_SHIFT           (24u)
+
+#define INTC_ICDIPR54_INTIICSPI3_SHIFT          (0u)
+#define INTC_ICDIPR54_INTIICSTI3_SHIFT          (8u)
+#define INTC_ICDIPR54_INTIICNAKI3_SHIFT         (16u)
+#define INTC_ICDIPR54_INTIICALI3_SHIFT          (24u)
+
+#define INTC_ICDIPR55_INTIICTMOI3_SHIFT         (0u)
+#define INTC_ICDIPR55_BRI0_SHIFT                (8u)
+#define INTC_ICDIPR55_ERI0_SHIFT                (16u)
+#define INTC_ICDIPR55_RXI0_SHIFT                (24u)
+
+#define INTC_ICDIPR56_TXI0_SHIFT                (0u)
+#define INTC_ICDIPR56_BRI1_SHIFT                (8u)
+#define INTC_ICDIPR56_ERI1_SHIFT                (16u)
+#define INTC_ICDIPR56_RXI1_SHIFT                (24u)
+
+#define INTC_ICDIPR57_TXI1_SHIFT                (0u)
+#define INTC_ICDIPR57_BRI2_SHIFT                (8u)
+#define INTC_ICDIPR57_ERI2_SHIFT                (16u)
+#define INTC_ICDIPR57_RXI2_SHIFT                (24u)
+
+#define INTC_ICDIPR58_TXI2_SHIFT                (0u)
+#define INTC_ICDIPR58_BRI3_SHIFT                (8u)
+#define INTC_ICDIPR58_ERI3_SHIFT                (16u)
+#define INTC_ICDIPR58_RXI3_SHIFT                (24u)
+
+#define INTC_ICDIPR59_TXI3_SHIFT                (0u)
+#define INTC_ICDIPR59_BRI4_SHIFT                (8u)
+#define INTC_ICDIPR59_ERI4_SHIFT                (16u)
+#define INTC_ICDIPR59_RXI4_SHIFT                (24u)
+
+#define INTC_ICDIPR60_TXI4_SHIFT                (0u)
+#define INTC_ICDIPR60_BRI5_SHIFT                (8u)
+#define INTC_ICDIPR60_ERI5_SHIFT                (16u)
+#define INTC_ICDIPR60_RXI5_SHIFT                (24u)
+
+#define INTC_ICDIPR61_TXI5_SHIFT                (0u)
+#define INTC_ICDIPR61_BRI6_SHIFT                (8u)
+#define INTC_ICDIPR61_ERI6_SHIFT                (16u)
+#define INTC_ICDIPR61_RXI6_SHIFT                (24u)
+
+#define INTC_ICDIPR62_TXI6_SHIFT                (0u)
+#define INTC_ICDIPR62_BRI7_SHIFT                (8u)
+#define INTC_ICDIPR62_ERI7_SHIFT                (16u)
+#define INTC_ICDIPR62_RXI7_SHIFT                (24u)
+
+#define INTC_ICDIPR63_TXI7_SHIFT                (0u)
+#define INTC_ICDIPR63_INTRCANGERR_SHIFT         (8u)
+#define INTC_ICDIPR63_INTRCANGRECC_SHIFT        (16u)
+#define INTC_ICDIPR63_INTRCAN0REC_SHIFT         (24u)
+
+#define INTC_ICDIPR64_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDIPR64_INTRCAN0TRX_SHIFT         (8u)
+#define INTC_ICDIPR64_INTRCAN1REC_SHIFT         (16u)
+#define INTC_ICDIPR64_INTRCAN1ERR_SHIFT         (24u)
+
+#define INTC_ICDIPR65_INTRCAN1TRX_SHIFT         (0u)
+#define INTC_ICDIPR65_INTRCAN2REC_SHIFT         (8u)
+#define INTC_ICDIPR65_INTRCAN2ERR_SHIFT         (16u)
+#define INTC_ICDIPR65_INTRCAN2TRX_SHIFT         (24u)
+
+#define INTC_ICDIPR66_INTRCAN3REC_SHIFT         (0u)
+#define INTC_ICDIPR66_INTRCAN3ERR_SHIFT         (8u)
+#define INTC_ICDIPR66_INTRCAN3TRX_SHIFT         (16u)
+#define INTC_ICDIPR66_INTRCAN4REC_SHIFT         (24u)
+
+#define INTC_ICDIPR67_INTRCAN4ERR_SHIFT         (0u)
+#define INTC_ICDIPR67_INTRCAN4TRX_SHIFT         (8u)
+#define INTC_ICDIPR67_SPEI0_SHIFT               (16u)
+#define INTC_ICDIPR67_SPRI0_SHIFT               (24u)
+
+#define INTC_ICDIPR68_SPTI0_SHIFT               (0u)
+#define INTC_ICDIPR68_SPEI1_SHIFT               (8u)
+#define INTC_ICDIPR68_SPRI1_SHIFT               (16u)
+#define INTC_ICDIPR68_SPTI1_SHIFT               (24u)
+
+#define INTC_ICDIPR69_SPEI2_SHIFT               (0u)
+#define INTC_ICDIPR69_SPRI2_SHIFT               (8u)
+#define INTC_ICDIPR69_SPTI2_SHIFT               (16u)
+#define INTC_ICDIPR69_SPEI3_SHIFT               (24u)
+
+#define INTC_ICDIPR70_SPRI3_SHIFT               (0u)
+#define INTC_ICDIPR70_SPTI3_SHIFT               (8u)
+#define INTC_ICDIPR70_SPEI4_SHIFT               (16u)
+#define INTC_ICDIPR70_SPRI4_SHIFT               (24u)
+
+#define INTC_ICDIPR71_SPTI4_SHIFT               (0u)
+#define INTC_ICDIPR71_IEBBTD_SHIFT              (8u)
+#define INTC_ICDIPR71_IEBBTERR_SHIFT            (16u)
+#define INTC_ICDIPR71_IEBBTSTA_SHIFT            (24u)
+
+#define INTC_ICDIPR72_IEBBTV_SHIFT              (0u)
+#define INTC_ICDIPR72_ISY_SHIFT                 (8u)
+#define INTC_ICDIPR72_IERR_SHIFT                (16u)
+#define INTC_ICDIPR72_ITARG_SHIFT               (24u)
+
+#define INTC_ICDIPR73_ISEC_SHIFT                (0u)
+#define INTC_ICDIPR73_IBUF_SHIFT                (8u)
+#define INTC_ICDIPR73_IREADY_SHIFT              (16u)
+#define INTC_ICDIPR73_FLSTE_SHIFT               (24u)
+
+#define INTC_ICDIPR74_FLTENDI_SHIFT             (0u)
+#define INTC_ICDIPR74_FLTREQ0I_SHIFT            (8u)
+#define INTC_ICDIPR74_FLTREQ1I_SHIFT            (16u)
+#define INTC_ICDIPR74_MMC0_SHIFT                (24u)
+
+#define INTC_ICDIPR75_MMC1_SHIFT                (0u)
+#define INTC_ICDIPR75_MMC2_SHIFT                (8u)
+#define INTC_ICDIPR75_SDHI0_3_SHIFT             (16u)
+#define INTC_ICDIPR75_SDHI0_0_SHIFT             (24u)
+
+#define INTC_ICDIPR76_SDHI0_1_SHIFT             (0u)
+#define INTC_ICDIPR76_SDHI1_3_SHIFT             (8u)
+#define INTC_ICDIPR76_SDHI1_0_SHIFT             (16u)
+#define INTC_ICDIPR76_SDHI1_1_SHIFT             (24u)
+
+#define INTC_ICDIPR77_ARM_SHIFT                 (0u)
+#define INTC_ICDIPR77_PRD_SHIFT                 (8u)
+#define INTC_ICDIPR77_CUP_SHIFT                 (16u)
+#define INTC_ICDIPR77_SCUAI0_SHIFT              (24u)
+
+#define INTC_ICDIPR78_SCUAI1_SHIFT              (0u)
+#define INTC_ICDIPR78_SCUFDI0_SHIFT             (8u)
+#define INTC_ICDIPR78_SCUFDI1_SHIFT             (16u)
+#define INTC_ICDIPR78_SCUFDI2_SHIFT             (24u)
+
+#define INTC_ICDIPR79_SCUFDI3_SHIFT             (0u)
+#define INTC_ICDIPR79_SCUFUI0_SHIFT             (8u)
+#define INTC_ICDIPR79_SCUFUI1_SHIFT             (16u)
+#define INTC_ICDIPR79_SCUFUI2_SHIFT             (24u)
+
+#define INTC_ICDIPR80_SCUFUI3_SHIFT             (0u)
+#define INTC_ICDIPR80_SCUDVI0_SHIFT             (8u)
+#define INTC_ICDIPR80_SCUDVI1_SHIFT             (16u)
+#define INTC_ICDIPR80_SCUDVI2_SHIFT             (24u)
+
+#define INTC_ICDIPR81_SCUDVI3_SHIFT             (0u)
+#define INTC_ICDIPR81_MLB_CINT_SHIFT            (8u)
+#define INTC_ICDIPR81_MLB_SINT_SHIFT            (16u)
+#define INTC_ICDIPR81_DRC0_SHIFT                (24u)
+
+#define INTC_ICDIPR82_DRC1_SHIFT                (0u)
+#define INTC_ICDIPR82_LINI0_INT_T_SHIFT         (24u)
+
+#define INTC_ICDIPR83_LINI0_INT_R_SHIFT         (0u)
+#define INTC_ICDIPR83_LINI0_INT_S_SHIFT         (8u)
+#define INTC_ICDIPR83_LINI0_INT_M_SHIFT         (16u)
+#define INTC_ICDIPR83_LINI1_INT_T_SHIFT         (24u)
+
+#define INTC_ICDIPR84_LINI1_INT_R_SHIFT         (0u)
+#define INTC_ICDIPR84_LINI1_INT_S_SHIFT         (8u)
+#define INTC_ICDIPR84_LINI1_INT_M_SHIFT         (16u)
+
+#define INTC_ICDIPR86_ERI0_SHIFT                (24u)
+
+#define INTC_ICDIPR87_RXI0_SHIFT                (0u)
+#define INTC_ICDIPR87_TXI0_SHIFT                (8u)
+#define INTC_ICDIPR87_TEI0_SHIFT                (16u)
+#define INTC_ICDIPR87_ERI1_SHIFT                (24u)
+
+#define INTC_ICDIPR88_RXI1_SHIFT                (0u)
+#define INTC_ICDIPR88_TXI1_SHIFT                (8u)
+#define INTC_ICDIPR88_TEI1_SHIFT                (16u)
+#define INTC_ICDIPR88_AVBI_DATA_SHIFT           (24u)
+
+#define INTC_ICDIPR89_AVBI_ERROR_SHIFT          (0u)
+#define INTC_ICDIPR89_AVBI_MANAGE_SHIFT         (8u)
+#define INTC_ICDIPR89_AVBI_MAC_SHIFT            (16u)
+#define INTC_ICDIPR89_ETHERI_SHIFT              (24u)
+
+#define INTC_ICDIPR91_CEUI_SHIFT                (0u)
+
+#define INTC_ICDIPR95_H2XMLB_ERRINT_SHIFT       (8u)
+#define INTC_ICDIPR95_H2XIC1_ERRINT_SHIFT       (16u)
+#define INTC_ICDIPR95_X2HPERI1_ERRINT_SHIFT     (24u)
+
+#define INTC_ICDIPR96_X2HPERI2_ERRINT_SHIFT     (0u)
+#define INTC_ICDIPR96_X2HPERI34_ERRINT_SHIFT    (8u)
+#define INTC_ICDIPR96_X2HPERI5_ERRINT_SHIFT     (16u)
+#define INTC_ICDIPR96_X2HPERI67_ERRINT_SHIFT    (24u)
+
+#define INTC_ICDIPR97_X2HDBGR_ERRINT_SHIFT      (0u)
+#define INTC_ICDIPR97_X2HBSC_ERRINT_SHIFT       (8u)
+#define INTC_ICDIPR97_X2HSPI1_ERRINT_SHIFT      (16u)
+#define INTC_ICDIPR97_X2HSPI2_ERRINT_SHIFT      (24u)
+
+#define INTC_ICDIPR98_PRRI_SHIFT                (0u)
+#define INTC_ICDIPR98_IFEI0_SHIFT               (8u)
+#define INTC_ICDIPR98_OFFI0_SHIFT               (16u)
+#define INTC_ICDIPR98_PFVEI0_SHIFT              (24u)
+
+#define INTC_ICDIPR99_IFEI1_SHIFT               (0u)
+#define INTC_ICDIPR99_OFFI1_SHIFT               (8u)
+#define INTC_ICDIPR99_PFVEI1_SHIFT              (16u)
+
+#define INTC_ICDIPR104_TINT0_SHIFT              (0u)
+#define INTC_ICDIPR104_TINT1_SHIFT              (8u)
+#define INTC_ICDIPR104_TINT2_SHIFT              (16u)
+#define INTC_ICDIPR104_TINT3_SHIFT              (24u)
+
+#define INTC_ICDIPR105_TINT4_SHIFT              (0u)
+#define INTC_ICDIPR105_TINT5_SHIFT              (8u)
+#define INTC_ICDIPR105_TINT6_SHIFT              (16u)
+#define INTC_ICDIPR105_TINT7_SHIFT              (24u)
+
+#define INTC_ICDIPR106_TINT8_SHIFT              (0u)
+#define INTC_ICDIPR106_TINT9_SHIFT              (8u)
+#define INTC_ICDIPR106_TINT10_SHIFT             (16u)
+#define INTC_ICDIPR106_TINT11_SHIFT             (24u)
+
+#define INTC_ICDIPR107_TINT12_SHIFT             (0u)
+#define INTC_ICDIPR107_TINT13_SHIFT             (8u)
+#define INTC_ICDIPR107_TINT14_SHIFT             (16u)
+#define INTC_ICDIPR107_TINT15_SHIFT             (24u)
+
+#define INTC_ICDIPR108_TINT16_SHIFT             (0u)
+#define INTC_ICDIPR108_TINT17_SHIFT             (8u)
+#define INTC_ICDIPR108_TINT18_SHIFT             (16u)
+#define INTC_ICDIPR108_TINT19_SHIFT             (24u)
+
+#define INTC_ICDIPR109_TINT20_SHIFT             (0u)
+#define INTC_ICDIPR109_TINT21_SHIFT             (8u)
+#define INTC_ICDIPR109_TINT22_SHIFT             (16u)
+#define INTC_ICDIPR109_TINT23_SHIFT             (24u)
+
+#define INTC_ICDIPR110_TINT24_SHIFT             (0u)
+#define INTC_ICDIPR110_TINT25_SHIFT             (8u)
+#define INTC_ICDIPR110_TINT26_SHIFT             (16u)
+#define INTC_ICDIPR110_TINT27_SHIFT             (24u)
+
+#define INTC_ICDIPR111_TINT28_SHIFT             (0u)
+#define INTC_ICDIPR111_TINT29_SHIFT             (8u)
+#define INTC_ICDIPR111_TINT30_SHIFT             (16u)
+#define INTC_ICDIPR111_TINT31_SHIFT             (24u)
+
+#define INTC_ICDIPR112_TINT32_SHIFT             (0u)
+#define INTC_ICDIPR112_TINT33_SHIFT             (8u)
+#define INTC_ICDIPR112_TINT34_SHIFT             (16u)
+#define INTC_ICDIPR112_TINT35_SHIFT             (24u)
+
+#define INTC_ICDIPR113_TINT36_SHIFT             (0u)
+#define INTC_ICDIPR113_TINT37_SHIFT             (8u)
+#define INTC_ICDIPR113_TINT38_SHIFT             (16u)
+#define INTC_ICDIPR113_TINT39_SHIFT             (24u)
+
+#define INTC_ICDIPR114_TINT40_SHIFT             (0u)
+#define INTC_ICDIPR114_TINT41_SHIFT             (8u)
+#define INTC_ICDIPR114_TINT42_SHIFT             (16u)
+#define INTC_ICDIPR114_TINT43_SHIFT             (24u)
+
+#define INTC_ICDIPR115_TINT44_SHIFT             (0u)
+#define INTC_ICDIPR115_TINT45_SHIFT             (8u)
+#define INTC_ICDIPR115_TINT46_SHIFT             (16u)
+#define INTC_ICDIPR115_TINT47_SHIFT             (24u)
+
+#define INTC_ICDIPR116_TINT48_SHIFT             (0u)
+#define INTC_ICDIPR116_TINT49_SHIFT             (8u)
+#define INTC_ICDIPR116_TINT50_SHIFT             (16u)
+#define INTC_ICDIPR116_TINT51_SHIFT             (24u)
+
+#define INTC_ICDIPR117_TINT52_SHIFT             (0u)
+#define INTC_ICDIPR117_TINT53_SHIFT             (8u)
+#define INTC_ICDIPR117_TINT54_SHIFT             (16u)
+#define INTC_ICDIPR117_TINT55_SHIFT             (24u)
+
+#define INTC_ICDIPR118_TINT56_SHIFT             (0u)
+#define INTC_ICDIPR118_TINT57_SHIFT             (8u)
+#define INTC_ICDIPR118_TINT58_SHIFT             (16u)
+#define INTC_ICDIPR118_TINT59_SHIFT             (24u)
+
+#define INTC_ICDIPR119_TINT60_SHIFT             (0u)
+#define INTC_ICDIPR119_TINT61_SHIFT             (8u)
+#define INTC_ICDIPR119_TINT62_SHIFT             (16u)
+#define INTC_ICDIPR119_TINT63_SHIFT             (24u)
+
+#define INTC_ICDIPR120_TINT64_SHIFT             (0u)
+#define INTC_ICDIPR120_TINT65_SHIFT             (8u)
+#define INTC_ICDIPR120_TINT66_SHIFT             (16u)
+#define INTC_ICDIPR120_TINT67_SHIFT             (24u)
+
+#define INTC_ICDIPR121_TINT68_SHIFT             (0u)
+#define INTC_ICDIPR121_TINT69_SHIFT             (8u)
+#define INTC_ICDIPR121_TINT70_SHIFT             (16u)
+#define INTC_ICDIPR121_TINT71_SHIFT             (24u)
+
+#define INTC_ICDIPR122_TINT72_SHIFT             (0u)
+#define INTC_ICDIPR122_TINT73_SHIFT             (8u)
+#define INTC_ICDIPR122_TINT74_SHIFT             (16u)
+#define INTC_ICDIPR122_TINT75_SHIFT             (24u)
+
+#define INTC_ICDIPR123_TINT76_SHIFT             (0u)
+#define INTC_ICDIPR123_TINT77_SHIFT             (8u)
+#define INTC_ICDIPR123_TINT78_SHIFT             (16u)
+#define INTC_ICDIPR123_TINT79_SHIFT             (24u)
+
+#define INTC_ICDIPR124_TINT80_SHIFT             (0u)
+#define INTC_ICDIPR124_TINT81_SHIFT             (8u)
+#define INTC_ICDIPR124_TINT82_SHIFT             (16u)
+#define INTC_ICDIPR124_TINT83_SHIFT             (24u)
+
+#define INTC_ICDIPR125_TINT84_SHIFT             (0u)
+#define INTC_ICDIPR125_TINT85_SHIFT             (8u)
+#define INTC_ICDIPR125_TINT86_SHIFT             (16u)
+#define INTC_ICDIPR125_TINT87_SHIFT             (24u)
+
+#define INTC_ICDIPR126_TINT88_SHIFT             (0u)
+#define INTC_ICDIPR126_TINT89_SHIFT             (8u)
+#define INTC_ICDIPR126_TINT90_SHIFT             (16u)
+#define INTC_ICDIPR126_TINT91_SHIFT             (24u)
+
+#define INTC_ICDIPR127_TINT92_SHIFT             (0u)
+#define INTC_ICDIPR127_TINT93_SHIFT             (8u)
+#define INTC_ICDIPR127_TINT94_SHIFT             (16u)
+#define INTC_ICDIPR127_TINT95_SHIFT             (24u)
+
+#define INTC_ICDIPR128_TINT96_SHIFT             (0u)
+#define INTC_ICDIPR128_TINT97_SHIFT             (8u)
+#define INTC_ICDIPR128_TINT98_SHIFT             (16u)
+#define INTC_ICDIPR128_TINT99_SHIFT             (24u)
+
+#define INTC_ICDIPR129_TINT100_SHIFT            (0u)
+#define INTC_ICDIPR129_TINT101_SHIFT            (8u)
+#define INTC_ICDIPR129_TINT102_SHIFT            (16u)
+#define INTC_ICDIPR129_TINT103_SHIFT            (24u)
+
+#define INTC_ICDIPR130_TINT104_SHIFT            (0u)
+#define INTC_ICDIPR130_TINT105_SHIFT            (8u)
+#define INTC_ICDIPR130_TINT106_SHIFT            (16u)
+#define INTC_ICDIPR130_TINT107_SHIFT            (24u)
+
+#define INTC_ICDIPR131_TINT108_SHIFT            (0u)
+#define INTC_ICDIPR131_TINT109_SHIFT            (8u)
+#define INTC_ICDIPR131_TINT110_SHIFT            (16u)
+#define INTC_ICDIPR131_TINT111_SHIFT            (24u)
+
+#define INTC_ICDIPR132_TINT112_SHIFT            (0u)
+#define INTC_ICDIPR132_TINT113_SHIFT            (8u)
+#define INTC_ICDIPR132_TINT114_SHIFT            (16u)
+#define INTC_ICDIPR132_TINT115_SHIFT            (24u)
+
+#define INTC_ICDIPR133_TINT116_SHIFT            (0u)
+#define INTC_ICDIPR133_TINT117_SHIFT            (8u)
+#define INTC_ICDIPR133_TINT118_SHIFT            (16u)
+#define INTC_ICDIPR133_TINT119_SHIFT            (24u)
+
+#define INTC_ICDIPR134_TINT120_SHIFT            (0u)
+#define INTC_ICDIPR134_TINT121_SHIFT            (8u)
+#define INTC_ICDIPR134_TINT122_SHIFT            (16u)
+#define INTC_ICDIPR134_TINT123_SHIFT            (24u)
+
+#define INTC_ICDIPR135_TINT124_SHIFT            (0u)
+#define INTC_ICDIPR135_TINT125_SHIFT            (8u)
+#define INTC_ICDIPR135_TINT126_SHIFT            (16u)
+#define INTC_ICDIPR135_TINT127_SHIFT            (24u)
+
+#define INTC_ICDIPR136_TINT128_SHIFT            (0u)
+#define INTC_ICDIPR136_TINT129_SHIFT            (8u)
+#define INTC_ICDIPR136_TINT130_SHIFT            (16u)
+#define INTC_ICDIPR136_TINT131_SHIFT            (24u)
+
+#define INTC_ICDIPR137_TINT132_SHIFT            (0u)
+#define INTC_ICDIPR137_TINT133_SHIFT            (8u)
+#define INTC_ICDIPR137_TINT134_SHIFT            (16u)
+#define INTC_ICDIPR137_TINT135_SHIFT            (24u)
+
+#define INTC_ICDIPR138_TINT136_SHIFT            (0u)
+#define INTC_ICDIPR138_TINT137_SHIFT            (8u)
+#define INTC_ICDIPR138_TINT138_SHIFT            (16u)
+#define INTC_ICDIPR138_TINT139_SHIFT            (24u)
+
+#define INTC_ICDIPR139_TINT140_SHIFT            (0u)
+#define INTC_ICDIPR139_TINT141_SHIFT            (8u)
+#define INTC_ICDIPR139_TINT142_SHIFT            (16u)
+#define INTC_ICDIPR139_TINT143_SHIFT            (24u)
+
+#define INTC_ICDIPR140_TINT144_SHIFT            (0u)
+#define INTC_ICDIPR140_TINT145_SHIFT            (8u)
+#define INTC_ICDIPR140_TINT146_SHIFT            (16u)
+#define INTC_ICDIPR140_TINT147_SHIFT            (24u)
+
+#define INTC_ICDIPR141_TINT148_SHIFT            (0u)
+#define INTC_ICDIPR141_TINT149_SHIFT            (8u)
+#define INTC_ICDIPR141_TINT150_SHIFT            (16u)
+#define INTC_ICDIPR141_TINT151_SHIFT            (24u)
+
+#define INTC_ICDIPR142_TINT152_SHIFT            (0u)
+#define INTC_ICDIPR142_TINT153_SHIFT            (8u)
+#define INTC_ICDIPR142_TINT154_SHIFT            (16u)
+#define INTC_ICDIPR142_TINT155_SHIFT            (24u)
+
+#define INTC_ICDIPR143_TINT156_SHIFT            (0u)
+#define INTC_ICDIPR143_TINT157_SHIFT            (8u)
+#define INTC_ICDIPR143_TINT158_SHIFT            (16u)
+#define INTC_ICDIPR143_TINT159_SHIFT            (24u)
+
+#define INTC_ICDIPR144_TINT160_SHIFT            (0u)
+#define INTC_ICDIPR144_TINT161_SHIFT            (8u)
+#define INTC_ICDIPR144_TINT162_SHIFT            (16u)
+#define INTC_ICDIPR144_TINT163_SHIFT            (24u)
+
+#define INTC_ICDIPR145_TINT164_SHIFT            (0u)
+#define INTC_ICDIPR145_TINT165_SHIFT            (8u)
+#define INTC_ICDIPR145_TINT166_SHIFT            (16u)
+#define INTC_ICDIPR145_TINT167_SHIFT            (24u)
+
+#define INTC_ICDIPR146_TINT168_SHIFT            (0u)
+#define INTC_ICDIPR146_TINT169_SHIFT            (8u)
+#define INTC_ICDIPR146_TINT170_SHIFT            (16u)
+
+#define INTC_ICDIPTR0_SW0_SHIFT                 (0u)
+#define INTC_ICDIPTR0_SW1_SHIFT                 (8u)
+#define INTC_ICDIPTR0_SW2_SHIFT                 (16u)
+#define INTC_ICDIPTR0_SW3_SHIFT                 (24u)
+
+#define INTC_ICDIPTR1_SW4_SHIFT                 (0u)
+#define INTC_ICDIPTR1_SW5_SHIFT                 (8u)
+#define INTC_ICDIPTR1_SW6_SHIFT                 (16u)
+#define INTC_ICDIPTR1_SW7_SHIFT                 (24u)
+
+#define INTC_ICDIPTR2_SW8_SHIFT                 (0u)
+#define INTC_ICDIPTR2_SW9_SHIFT                 (8u)
+#define INTC_ICDIPTR2_SW10_SHIFT                (16u)
+#define INTC_ICDIPTR2_SW11_SHIFT                (24u)
+
+#define INTC_ICDIPTR3_SW12_SHIFT                (0u)
+#define INTC_ICDIPTR3_SW13_SHIFT                (8u)
+#define INTC_ICDIPTR3_SW14_SHIFT                (16u)
+#define INTC_ICDIPTR3_SW15_SHIFT                (24u)
+
+#define INTC_ICDIPTR4_PMUIRQ0_SHIFT             (0u)
+#define INTC_ICDIPTR4_COMMRX0_SHIFT             (8u)
+#define INTC_ICDIPTR4_COMMTX0_SHIFT             (16u)
+#define INTC_ICDIPTR4_CTIIRQ0_SHIFT             (24u)
+
+#define INTC_ICDIPTR8_IRQ0_SHIFT                (0u)
+#define INTC_ICDIPTR8_IRQ1_SHIFT                (8u)
+#define INTC_ICDIPTR8_IRQ2_SHIFT                (16u)
+#define INTC_ICDIPTR8_IRQ3_SHIFT                (24u)
+
+#define INTC_ICDIPTR9_IRQ4_SHIFT                (0u)
+#define INTC_ICDIPTR9_IRQ5_SHIFT                (8u)
+#define INTC_ICDIPTR9_IRQ6_SHIFT                (16u)
+#define INTC_ICDIPTR9_IRQ7_SHIFT                (24u)
+
+#define INTC_ICDIPTR10_PL310ERR_SHIFT           (0u)
+#define INTC_ICDIPTR10_DMAINT0_SHIFT            (8u)
+#define INTC_ICDIPTR10_DMAINT1_SHIFT            (16u)
+#define INTC_ICDIPTR10_DMAINT2_SHIFT            (24u)
+
+#define INTC_ICDIPTR11_DMAINT3_SHIFT            (0u)
+#define INTC_ICDIPTR11_DMAINT4_SHIFT            (8u)
+#define INTC_ICDIPTR11_DMAINT5_SHIFT            (16u)
+#define INTC_ICDIPTR11_DMAINT6_SHIFT            (24u)
+
+#define INTC_ICDIPTR12_DMAINT7_SHIFT            (0u)
+#define INTC_ICDIPTR12_DMAINT8_SHIFT            (8u)
+#define INTC_ICDIPTR12_DMAINT9_SHIFT            (16u)
+#define INTC_ICDIPTR12_DMAINT10_SHIFT           (24u)
+
+#define INTC_ICDIPTR13_DMAINT11_SHIFT           (0u)
+#define INTC_ICDIPTR13_DMAINT12_SHIFT           (8u)
+#define INTC_ICDIPTR13_DMAINT13_SHIFT           (16u)
+#define INTC_ICDIPTR13_DMAINT14_SHIFT           (24u)
+
+#define INTC_ICDIPTR14_DMAINT15_SHIFT           (0u)
+#define INTC_ICDIPTR14_DMAERR_SHIFT             (8u)
+
+#define INTC_ICDIPTR18_USBI0_SHIFT              (8u)
+#define INTC_ICDIPTR18_USBI1_SHIFT              (16u)
+#define INTC_ICDIPTR18_S0_VI_VSYNC0_SHIFT       (24u)
+
+#define INTC_ICDIPTR19_S0_LO_VSYNC0_SHIFT       (0u)
+#define INTC_ICDIPTR19_S0_VSYNCERR0_SHIFT       (8u)
+#define INTC_ICDIPTR19_GR3_VLINE0_SHIFT         (16u)
+#define INTC_ICDIPTR19_S0_VFIELD0_SHIFT         (24u)
+
+#define INTC_ICDIPTR20_IV1_VBUFERR0_SHIFT       (0u)
+#define INTC_ICDIPTR20_IV3_VBUFERR0_SHIFT       (8u)
+#define INTC_ICDIPTR20_IV5_VBUFERR0_SHIFT       (16u)
+#define INTC_ICDIPTR20_IV6_VBUFERR0_SHIFT       (24u)
+
+#define INTC_ICDIPTR21_S0_WLINE0_SHIFT          (0u)
+#define INTC_ICDIPTR21_S1_VI_VSYNC0_SHIFT       (8u)
+#define INTC_ICDIPTR21_S1_LO_VSYNC0_SHIFT       (16u)
+#define INTC_ICDIPTR21_S1_VSYNCERR0_SHIFT       (24u)
+
+#define INTC_ICDIPTR22_S1_VFIELD0_SHIFT         (0u)
+#define INTC_ICDIPTR22_IV2_VBUFERR0_SHIFT       (8u)
+#define INTC_ICDIPTR22_IV4_VBUFERR0_SHIFT       (16u)
+#define INTC_ICDIPTR22_S1_WLINE0_SHIFT          (24u)
+
+#define INTC_ICDIPTR23_OIR_VI_VSYNC0_SHIFT      (0u)
+#define INTC_ICDIPTR23_OIR_LO_VSYNC0_SHIFT      (8u)
+#define INTC_ICDIPTR23_OIR_VSYNCERR0_SHIFT      (16u)
+#define INTC_ICDIPTR23_OIR_VFIELD0_SHIFT        (24u)
+
+#define INTC_ICDIPTR24_IV7_VBUFERR0_SHIFT       (0u)
+#define INTC_ICDIPTR24_IV8_VBUFERR0_SHIFT       (8u)
+#define INTC_ICDIPTR24_S0_VI_VSYNC1_SHIFT       (24u)
+
+#define INTC_ICDIPTR25_S0_LO_VSYNC1_SHIFT       (0u)
+#define INTC_ICDIPTR25_S0_VSYNCERR1_SHIFT       (8u)
+#define INTC_ICDIPTR25_GR3_VLINE1_SHIFT         (16u)
+#define INTC_ICDIPTR25_S0_VFIELD1_SHIFT         (24u)
+
+#define INTC_ICDIPTR26_IV1_VBUFERR1_SHIFT       (0u)
+#define INTC_ICDIPTR26_IV3_VBUFERR1_SHIFT       (8u)
+#define INTC_ICDIPTR26_IV5_VBUFERR1_SHIFT       (16u)
+#define INTC_ICDIPTR26_IV6_VBUFERR1_SHIFT       (24u)
+
+#define INTC_ICDIPTR27_S0_WLINE1_SHIFT          (0u)
+#define INTC_ICDIPTR27_S1_VI_VSYNC1_SHIFT       (8u)
+#define INTC_ICDIPTR27_S1_LO_VSYNC1_SHIFT       (16u)
+#define INTC_ICDIPTR27_S1_VSYNCERR1_SHIFT       (24u)
+
+#define INTC_ICDIPTR28_S1_VFIELD1_SHIFT         (0u)
+#define INTC_ICDIPTR28_IV2_VBUFERR1_SHIFT       (8u)
+#define INTC_ICDIPTR28_IV4_VBUFERR1_SHIFT       (16u)
+#define INTC_ICDIPTR28_S1_WLINE1_SHIFT          (24u)
+
+#define INTC_ICDIPTR29_OIR_VI_VSYNC1_SHIFT      (0u)
+#define INTC_ICDIPTR29_OIR_LO_VSYNC1_SHIFT      (8u)
+#define INTC_ICDIPTR29_OIR_VLINE1_SHIFT         (16u)
+#define INTC_ICDIPTR29_OIR_VFIELD1_SHIFT        (24u)
+
+#define INTC_ICDIPTR30_IV7_VBUFERR1_SHIFT       (0u)
+#define INTC_ICDIPTR30_IV8_VBUFERR1_SHIFT       (8u)
+#define INTC_ICDIPTR30_IMRDI_SHIFT              (24u)
+
+#define INTC_ICDIPTR31_IMR2I0_SHIFT             (0u)
+#define INTC_ICDIPTR31_IMR2I1_SHIFT             (8u)
+#define INTC_ICDIPTR31_JEDI_SHIFT               (16u)
+#define INTC_ICDIPTR31_JDTI_SHIFT               (24u)
+
+#define INTC_ICDIPTR32_CMP0_SHIFT               (0u)
+#define INTC_ICDIPTR32_CMP1_SHIFT               (8u)
+#define INTC_ICDIPTR32_INT0_SHIFT               (16u)
+#define INTC_ICDIPTR32_INT1_SHIFT               (24u)
+
+#define INTC_ICDIPTR33_INT2_SHIFT               (0u)
+#define INTC_ICDIPTR33_INT3_SHIFT               (8u)
+#define INTC_ICDIPTR33_OSTM0TINT_SHIFT          (16u)
+#define INTC_ICDIPTR33_OSTM1TINT_SHIFT          (24u)
+
+#define INTC_ICDIPTR34_CMI_SHIFT                (0u)
+#define INTC_ICDIPTR34_WTOUT_SHIFT              (8u)
+#define INTC_ICDIPTR34_ITI_SHIFT                (16u)
+#define INTC_ICDIPTR34_TGI0A_SHIFT              (24u)
+
+#define INTC_ICDIPTR35_TGI0B_SHIFT              (0u)
+#define INTC_ICDIPTR35_TGI0C_SHIFT              (8u)
+#define INTC_ICDIPTR35_TGI0D_SHIFT              (16u)
+#define INTC_ICDIPTR35_TGI0V_SHIFT              (24u)
+
+#define INTC_ICDIPTR36_TGI0E_SHIFT              (0u)
+#define INTC_ICDIPTR36_TGI0F_SHIFT              (8u)
+#define INTC_ICDIPTR36_TGI1A_SHIFT              (16u)
+#define INTC_ICDIPTR36_TGI1B_SHIFT              (24u)
+
+#define INTC_ICDIPTR37_TGI1V_SHIFT              (0u)
+#define INTC_ICDIPTR37_TGI1U_SHIFT              (8u)
+#define INTC_ICDIPTR37_TGI2A_SHIFT              (16u)
+#define INTC_ICDIPTR37_TGI2B_SHIFT              (24u)
+
+#define INTC_ICDIPTR38_TGI2V_SHIFT              (0u)
+#define INTC_ICDIPTR38_TGI2U_SHIFT              (8u)
+#define INTC_ICDIPTR38_TGI3A_SHIFT              (16u)
+#define INTC_ICDIPTR38_TGI3B_SHIFT              (24u)
+
+#define INTC_ICDIPTR39_TGI3C_SHIFT              (0u)
+#define INTC_ICDIPTR39_TGI3D_SHIFT              (8u)
+#define INTC_ICDIPTR39_TGI3V_SHIFT              (16u)
+#define INTC_ICDIPTR39_TGI4A_SHIFT              (24u)
+
+#define INTC_ICDIPTR40_TGI4B_SHIFT              (0u)
+#define INTC_ICDIPTR40_TGI4C_SHIFT              (8u)
+#define INTC_ICDIPTR40_TGI4D_SHIFT              (16u)
+#define INTC_ICDIPTR40_TGI4V_SHIFT              (24u)
+
+#define INTC_ICDIPTR41_CMI1_SHIFT               (0u)
+#define INTC_ICDIPTR41_CMI2_SHIFT               (8u)
+#define INTC_ICDIPTR41_SGDEI0_SHIFT             (16u)
+#define INTC_ICDIPTR41_SGDEI1_SHIFT             (24u)
+
+#define INTC_ICDIPTR42_SGDEI2_SHIFT             (0u)
+#define INTC_ICDIPTR42_SGDEI3_SHIFT             (8u)
+#define INTC_ICDIPTR42_ADI_SHIFT                (16u)
+#define INTC_ICDIPTR42_LMTI_SHIFT               (24u)
+
+#define INTC_ICDIPTR43_SSII0_SHIFT              (0u)
+#define INTC_ICDIPTR43_SSIRXI0_SHIFT            (8u)
+#define INTC_ICDIPTR43_SSITXI0_SHIFT            (16u)
+#define INTC_ICDIPTR43_SSII1_SHIFT              (24u)
+
+#define INTC_ICDIPTR44_SSIRXI1_SHIFT            (0u)
+#define INTC_ICDIPTR44_SSITXI1_SHIFT            (8u)
+#define INTC_ICDIPTR44_SSII2_SHIFT              (16u)
+#define INTC_ICDIPTR44_SSIRTI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR45_SSII3_SHIFT              (0u)
+#define INTC_ICDIPTR45_SSIRXI3_SHIFT            (8u)
+#define INTC_ICDIPTR45_SSITXI3_SHIFT            (16u)
+#define INTC_ICDIPTR45_SSII4_SHIFT              (24u)
+
+#define INTC_ICDIPTR46_SSIRTI4_SHIFT            (0u)
+#define INTC_ICDIPTR46_SSII5_SHIFT              (8u)
+#define INTC_ICDIPTR46_SSIRXI5_SHIFT            (16u)
+#define INTC_ICDIPTR46_SSITXI5_SHIFT            (24u)
+
+#define INTC_ICDIPTR47_SPDIFI_SHIFT             (0u)
+#define INTC_ICDIPTR47_INTIICTEI0_SHIFT         (8u)
+#define INTC_ICDIPTR47_INTIICRI0_SHIFT          (16u)
+#define INTC_ICDIPTR47_INTIICTI0_SHIFT          (24u)
+
+#define INTC_ICDIPTR48_INTIICSPI0_SHIFT         (0u)
+#define INTC_ICDIPTR48_INTIICSTI0_SHIFT         (8u)
+#define INTC_ICDIPTR48_INTIICNAKI0_SHIFT        (16u)
+#define INTC_ICDIPTR48_INTIICALI0_SHIFT         (24u)
+
+#define INTC_ICDIPTR49_INTIICTMOI0_SHIFT        (0u)
+#define INTC_ICDIPTR49_INTIICTEI1_SHIFT         (8u)
+#define INTC_ICDIPTR49_INTIICRI1_SHIFT          (16u)
+#define INTC_ICDIPTR49_INTIICTI1_SHIFT          (24u)
+
+#define INTC_ICDIPTR50_INTIICSPI1_SHIFT         (0u)
+#define INTC_ICDIPTR50_INTIICSTI1_SHIFT         (8u)
+#define INTC_ICDIPTR50_INTIICNAKI1_SHIFT        (16u)
+#define INTC_ICDIPTR50_INTIICALI1_SHIFT         (24u)
+
+#define INTC_ICDIPTR51_INTIICTMOI1_SHIFT        (0u)
+#define INTC_ICDIPTR51_INTIICTEI2_SHIFT         (8u)
+#define INTC_ICDIPTR51_INTIICRI2_SHIFT          (16u)
+#define INTC_ICDIPTR51_INTIICTI2_SHIFT          (24u)
+
+#define INTC_ICDIPTR52_INTIICSPI2_SHIFT         (0u)
+#define INTC_ICDIPTR52_INTIICSTI2_SHIFT         (8u)
+#define INTC_ICDIPTR52_INTIICNAKI2_SHIFT        (16u)
+#define INTC_ICDIPTR52_INTIICALI2_SHIFT         (24u)
+
+#define INTC_ICDIPTR53_INTIICTMOI2_SHIFT        (0u)
+#define INTC_ICDIPTR53_INTIICTEI3_SHIFT         (8u)
+#define INTC_ICDIPTR53_INTIICRI3_SHIFT          (16u)
+#define INTC_ICDIPTR53_INTIICTI3_SHIFT          (24u)
+
+#define INTC_ICDIPTR54_INTIICSPI3_SHIFT         (0u)
+#define INTC_ICDIPTR54_INTIICSTI3_SHIFT         (8u)
+#define INTC_ICDIPTR54_INTIICNAKI3_SHIFT        (16u)
+#define INTC_ICDIPTR54_INTIICALI3_SHIFT         (24u)
+
+#define INTC_ICDIPTR55_INTIICTMOI3_SHIFT        (0u)
+#define INTC_ICDIPTR55_BRI0_SHIFT               (8u)
+#define INTC_ICDIPTR55_ERI0_SHIFT               (16u)
+#define INTC_ICDIPTR55_RXI0_SHIFT               (24u)
+
+#define INTC_ICDIPTR56_TXI0_SHIFT               (0u)
+#define INTC_ICDIPTR56_BRI1_SHIFT               (8u)
+#define INTC_ICDIPTR56_ERI1_SHIFT               (16u)
+#define INTC_ICDIPTR56_RXI1_SHIFT               (24u)
+
+#define INTC_ICDIPTR57_TXI1_SHIFT               (0u)
+#define INTC_ICDIPTR57_BRI2_SHIFT               (8u)
+#define INTC_ICDIPTR57_ERI2_SHIFT               (16u)
+#define INTC_ICDIPTR57_RXI2_SHIFT               (24u)
+
+#define INTC_ICDIPTR58_TXI2_SHIFT               (0u)
+#define INTC_ICDIPTR58_BRI3_SHIFT               (8u)
+#define INTC_ICDIPTR58_ERI3_SHIFT               (16u)
+#define INTC_ICDIPTR58_RXI3_SHIFT               (24u)
+
+#define INTC_ICDIPTR59_TXI3_SHIFT               (0u)
+#define INTC_ICDIPTR59_BRI4_SHIFT               (8u)
+#define INTC_ICDIPTR59_ERI4_SHIFT               (16u)
+#define INTC_ICDIPTR59_RXI4_SHIFT               (24u)
+
+#define INTC_ICDIPTR60_TXI4_SHIFT               (0u)
+#define INTC_ICDIPTR60_BRI5_SHIFT               (8u)
+#define INTC_ICDIPTR60_ERI5_SHIFT               (16u)
+#define INTC_ICDIPTR60_RXI5_SHIFT               (24u)
+
+#define INTC_ICDIPTR61_TXI5_SHIFT               (0u)
+#define INTC_ICDIPTR61_BRI6_SHIFT               (8u)
+#define INTC_ICDIPTR61_ERI6_SHIFT               (16u)
+#define INTC_ICDIPTR61_RXI6_SHIFT               (24u)
+
+#define INTC_ICDIPTR62_TXI6_SHIFT               (0u)
+#define INTC_ICDIPTR62_BRI7_SHIFT               (8u)
+#define INTC_ICDIPTR62_ERI7_SHIFT               (16u)
+#define INTC_ICDIPTR62_RXI7_SHIFT               (24u)
+
+#define INTC_ICDIPTR63_TXI7_SHIFT               (0u)
+#define INTC_ICDIPTR63_INTRCANGERR_SHIFT        (8u)
+#define INTC_ICDIPTR63_INTRCANGRECC_SHIFT       (16u)
+#define INTC_ICDIPTR63_INTRCAN0REC_SHIFT        (24u)
+
+#define INTC_ICDIPTR64_INTRCAN0ERR_SHIFT        (0u)
+#define INTC_ICDIPTR64_INTRCAN0TRX_SHIFT        (8u)
+#define INTC_ICDIPTR64_INTRCAN1REC_SHIFT        (16u)
+#define INTC_ICDIPTR64_INTRCAN1ERR_SHIFT        (24u)
+
+#define INTC_ICDIPTR65_INTRCAN1TRX_SHIFT        (0u)
+#define INTC_ICDIPTR65_INTRCAN2REC_SHIFT        (8u)
+#define INTC_ICDIPTR65_INTRCAN2ERR_SHIFT        (16u)
+#define INTC_ICDIPTR65_INTRCAN2TRX_SHIFT        (24u)
+
+#define INTC_ICDIPTR66_INTRCAN3REC_SHIFT        (0u)
+#define INTC_ICDIPTR66_INTRCAN3ERR_SHIFT        (8u)
+#define INTC_ICDIPTR66_INTRCAN3TRX_SHIFT        (16u)
+#define INTC_ICDIPTR66_INTRCAN4REC_SHIFT        (24u)
+
+#define INTC_ICDIPTR67_INTRCAN4ERR_SHIFT        (0u)
+#define INTC_ICDIPTR67_INTRCAN4TRX_SHIFT        (8u)
+#define INTC_ICDIPTR67_SPEI0_SHIFT              (16u)
+#define INTC_ICDIPTR67_SPRI0_SHIFT              (24u)
+
+#define INTC_ICDIPTR68_SPTI0_SHIFT              (0u)
+#define INTC_ICDIPTR68_SPEI1_SHIFT              (8u)
+#define INTC_ICDIPTR68_SPRI1_SHIFT              (16u)
+#define INTC_ICDIPTR68_SPTI1_SHIFT              (24u)
+
+#define INTC_ICDIPTR69_SPEI2_SHIFT              (0u)
+#define INTC_ICDIPTR69_SPRI2_SHIFT              (8u)
+#define INTC_ICDIPTR69_SPTI2_SHIFT              (16u)
+#define INTC_ICDIPTR69_SPEI3_SHIFT              (24u)
+
+#define INTC_ICDIPTR70_SPRI3_SHIFT              (0u)
+#define INTC_ICDIPTR70_SPTI3_SHIFT              (8u)
+#define INTC_ICDIPTR70_SPEI4_SHIFT              (16u)
+#define INTC_ICDIPTR70_SPRI4_SHIFT              (24u)
+
+#define INTC_ICDIPTR71_SPTI4_SHIFT              (0u)
+#define INTC_ICDIPTR71_IEBBTD_SHIFT             (8u)
+#define INTC_ICDIPTR71_IEBBTERR_SHIFT           (16u)
+#define INTC_ICDIPTR71_IEBBTSTA_SHIFT           (24u)
+
+#define INTC_ICDIPTR72_IEBBTV_SHIFT             (0u)
+#define INTC_ICDIPTR72_ISY_SHIFT                (8u)
+#define INTC_ICDIPTR72_IERR_SHIFT               (16u)
+#define INTC_ICDIPTR72_ITARG_SHIFT              (24u)
+
+#define INTC_ICDIPTR73_ISEC_SHIFT               (0u)
+#define INTC_ICDIPTR73_IBUF_SHIFT               (8u)
+#define INTC_ICDIPTR73_IREADY_SHIFT             (16u)
+#define INTC_ICDIPTR73_FLSTE_SHIFT              (24u)
+
+#define INTC_ICDIPTR74_FLTENDI_SHIFT            (0u)
+#define INTC_ICDIPTR74_FLTREQ0I_SHIFT           (8u)
+#define INTC_ICDIPTR74_FLTREQ1I_SHIFT           (16u)
+#define INTC_ICDIPTR74_MMC0_SHIFT               (24u)
+
+#define INTC_ICDIPTR75_MMC1_SHIFT               (0u)
+#define INTC_ICDIPTR75_MMC2_SHIFT               (8u)
+#define INTC_ICDIPTR75_SDHI0_3_SHIFT            (16u)
+#define INTC_ICDIPTR75_SDHI0_0_SHIFT            (24u)
+
+#define INTC_ICDIPTR76_SDHI0_1_SHIFT            (0u)
+#define INTC_ICDIPTR76_SDHI1_3_SHIFT            (8u)
+#define INTC_ICDIPTR76_SDHI1_0_SHIFT            (16u)
+#define INTC_ICDIPTR76_SDHI1_1_SHIFT            (24u)
+
+#define INTC_ICDIPTR77_ARM_SHIFT                (0u)
+#define INTC_ICDIPTR77_PRD_SHIFT                (8u)
+#define INTC_ICDIPTR77_CUP_SHIFT                (16u)
+#define INTC_ICDIPTR77_SCUAI0_SHIFT             (24u)
+
+#define INTC_ICDIPTR78_SCUAI1_SHIFT             (0u)
+#define INTC_ICDIPTR78_SCUFDI0_SHIFT            (8u)
+#define INTC_ICDIPTR78_SCUFDI1_SHIFT            (16u)
+#define INTC_ICDIPTR78_SCUFDI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR79_SCUFDI3_SHIFT            (0u)
+#define INTC_ICDIPTR79_SCUFUI0_SHIFT            (8u)
+#define INTC_ICDIPTR79_SCUFUI1_SHIFT            (16u)
+#define INTC_ICDIPTR79_SCUFUI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR80_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDIPTR80_SCUDVI0_SHIFT            (8u)
+#define INTC_ICDIPTR80_SCUDVI1_SHIFT            (16u)
+#define INTC_ICDIPTR80_SCUDVI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR81_SCUDVI3_SHIFT            (0u)
+#define INTC_ICDIPTR81_MLB_CINT_SHIFT           (8u)
+#define INTC_ICDIPTR81_MLB_SINT_SHIFT           (16u)
+#define INTC_ICDIPTR81_DRC0_SHIFT               (24u)
+
+#define INTC_ICDIPTR82_DRC1_SHIFT               (0u)
+#define INTC_ICDIPTR82_LINI0_INT_T_SHIFT        (24u)
+
+#define INTC_ICDIPTR83_LINI0_INT_R_SHIFT        (0u)
+#define INTC_ICDIPTR83_LINI0_INT_S_SHIFT        (8u)
+#define INTC_ICDIPTR83_LINI0_INT_M_SHIFT        (16u)
+#define INTC_ICDIPTR83_LINI1_INT_T_SHIFT        (24u)
+
+#define INTC_ICDIPTR84_LINI1_INT_R_SHIFT        (0u)
+#define INTC_ICDIPTR84_LINI1_INT_S_SHIFT        (8u)
+#define INTC_ICDIPTR84_LINI1_INT_M_SHIFT        (16u)
+
+#define INTC_ICDIPTR86_ERI0_SHIFT               (24u)
+
+#define INTC_ICDIPTR87_RXI0_SHIFT               (0u)
+#define INTC_ICDIPTR87_TXI0_SHIFT               (8u)
+#define INTC_ICDIPTR87_TEI0_SHIFT               (16u)
+#define INTC_ICDIPTR87_ERI1_SHIFT               (24u)
+
+#define INTC_ICDIPTR88_RXI1_SHIFT               (0u)
+#define INTC_ICDIPTR88_TXI1_SHIFT               (8u)
+#define INTC_ICDIPTR88_TEI1_SHIFT               (16u)
+#define INTC_ICDIPTR88_AVBI_DATA_SHIFT          (24u)
+
+#define INTC_ICDIPTR89_AVBI_ERROR_SHIFT         (0u)
+#define INTC_ICDIPTR89_AVBI_MANAGE_SHIFT        (8u)
+#define INTC_ICDIPTR89_AVBI_MAC_SHIFT           (16u)
+#define INTC_ICDIPTR89_ETHERI_SHIFT             (24u)
+
+#define INTC_ICDIPTR91_CEUI_SHIFT               (0u)
+
+#define INTC_ICDIPTR95_H2XMLB_ERRINT_SHIFT      (8u)
+#define INTC_ICDIPTR95_H2XIC1_ERRINT_SHIFT      (16u)
+#define INTC_ICDIPTR95_X2HPERI1_ERRINT_SHIFT    (24u)
+
+#define INTC_ICDIPTR96_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDIPTR96_X2HPERI34_ERRINT_SHIFT   (8u)
+#define INTC_ICDIPTR96_X2HPERI5_ERRINT_SHIFT    (16u)
+#define INTC_ICDIPTR96_X2HPERI67_ERRINT_SHIFT   (24u)
+
+#define INTC_ICDIPTR97_X2HDBGR_ERRINT_SHIFT     (0u)
+#define INTC_ICDIPTR97_X2HBSC_ERRINT_SHIFT      (8u)
+#define INTC_ICDIPTR97_X2HSPI1_ERRINT_SHIFT     (16u)
+#define INTC_ICDIPTR97_X2HSPI2_ERRINT_SHIFT     (24u)
+
+#define INTC_ICDIPTR98_PRRI_SHIFT               (0u)
+#define INTC_ICDIPTR98_IFEI0_SHIFT              (8u)
+#define INTC_ICDIPTR98_OFFI0_SHIFT              (16u)
+#define INTC_ICDIPTR98_PFVEI0_SHIFT             (24u)
+
+#define INTC_ICDIPTR99_IFEI1_SHIFT              (0u)
+#define INTC_ICDIPTR99_OFFI1_SHIFT              (8u)
+#define INTC_ICDIPTR99_PFVEI1_SHIFT             (16u)
+
+#define INTC_ICDIPTR104_TINT0_SHIFT             (0u)
+#define INTC_ICDIPTR104_TINT1_SHIFT             (8u)
+#define INTC_ICDIPTR104_TINT2_SHIFT             (16u)
+#define INTC_ICDIPTR104_TINT3_SHIFT             (24u)
+
+#define INTC_ICDIPTR105_TINT4_SHIFT             (0u)
+#define INTC_ICDIPTR105_TINT5_SHIFT             (8u)
+#define INTC_ICDIPTR105_TINT6_SHIFT             (16u)
+#define INTC_ICDIPTR105_TINT7_SHIFT             (24u)
+
+#define INTC_ICDIPTR106_TINT8_SHIFT             (0u)
+#define INTC_ICDIPTR106_TINT9_SHIFT             (8u)
+#define INTC_ICDIPTR106_TINT10_SHIFT            (16u)
+#define INTC_ICDIPTR106_TINT11_SHIFT            (24u)
+
+#define INTC_ICDIPTR107_TINT12_SHIFT            (0u)
+#define INTC_ICDIPTR107_TINT13_SHIFT            (8u)
+#define INTC_ICDIPTR107_TINT14_SHIFT            (16u)
+#define INTC_ICDIPTR107_TINT15_SHIFT            (24u)
+
+#define INTC_ICDIPTR108_TINT16_SHIFT            (0u)
+#define INTC_ICDIPTR108_TINT17_SHIFT            (8u)
+#define INTC_ICDIPTR108_TINT18_SHIFT            (16u)
+#define INTC_ICDIPTR108_TINT19_SHIFT            (24u)
+
+#define INTC_ICDIPTR109_TINT20_SHIFT            (0u)
+#define INTC_ICDIPTR109_TINT21_SHIFT            (8u)
+#define INTC_ICDIPTR109_TINT22_SHIFT            (16u)
+#define INTC_ICDIPTR109_TINT23_SHIFT            (24u)
+
+#define INTC_ICDIPTR110_TINT24_SHIFT            (0u)
+#define INTC_ICDIPTR110_TINT25_SHIFT            (8u)
+#define INTC_ICDIPTR110_TINT26_SHIFT            (16u)
+#define INTC_ICDIPTR110_TINT27_SHIFT            (24u)
+
+#define INTC_ICDIPTR111_TINT28_SHIFT            (0u)
+#define INTC_ICDIPTR111_TINT29_SHIFT            (8u)
+#define INTC_ICDIPTR111_TINT30_SHIFT            (16u)
+#define INTC_ICDIPTR111_TINT31_SHIFT            (24u)
+
+#define INTC_ICDIPTR112_TINT32_SHIFT            (0u)
+#define INTC_ICDIPTR112_TINT33_SHIFT            (8u)
+#define INTC_ICDIPTR112_TINT34_SHIFT            (16u)
+#define INTC_ICDIPTR112_TINT35_SHIFT            (24u)
+
+#define INTC_ICDIPTR113_TINT36_SHIFT            (0u)
+#define INTC_ICDIPTR113_TINT37_SHIFT            (8u)
+#define INTC_ICDIPTR113_TINT38_SHIFT            (16u)
+#define INTC_ICDIPTR113_TINT39_SHIFT            (24u)
+
+#define INTC_ICDIPTR114_TINT40_SHIFT            (0u)
+#define INTC_ICDIPTR114_TINT41_SHIFT            (8u)
+#define INTC_ICDIPTR114_TINT42_SHIFT            (16u)
+#define INTC_ICDIPTR114_TINT43_SHIFT            (24u)
+
+#define INTC_ICDIPTR115_TINT44_SHIFT            (0u)
+#define INTC_ICDIPTR115_TINT45_SHIFT            (8u)
+#define INTC_ICDIPTR115_TINT46_SHIFT            (16u)
+#define INTC_ICDIPTR115_TINT47_SHIFT            (24u)
+
+#define INTC_ICDIPTR116_TINT48_SHIFT            (0u)
+#define INTC_ICDIPTR116_TINT49_SHIFT            (8u)
+#define INTC_ICDIPTR116_TINT50_SHIFT            (16u)
+#define INTC_ICDIPTR116_TINT51_SHIFT            (24u)
+
+#define INTC_ICDIPTR117_TINT52_SHIFT            (0u)
+#define INTC_ICDIPTR117_TINT53_SHIFT            (8u)
+#define INTC_ICDIPTR117_TINT54_SHIFT            (16u)
+#define INTC_ICDIPTR117_TINT55_SHIFT            (24u)
+
+#define INTC_ICDIPTR118_TINT56_SHIFT            (0u)
+#define INTC_ICDIPTR118_TINT57_SHIFT            (8u)
+#define INTC_ICDIPTR118_TINT58_SHIFT            (16u)
+#define INTC_ICDIPTR118_TINT59_SHIFT            (24u)
+
+#define INTC_ICDIPTR119_TINT60_SHIFT            (0u)
+#define INTC_ICDIPTR119_TINT61_SHIFT            (8u)
+#define INTC_ICDIPTR119_TINT62_SHIFT            (16u)
+#define INTC_ICDIPTR119_TINT63_SHIFT            (24u)
+
+#define INTC_ICDIPTR120_TINT64_SHIFT            (0u)
+#define INTC_ICDIPTR120_TINT65_SHIFT            (8u)
+#define INTC_ICDIPTR120_TINT66_SHIFT            (16u)
+#define INTC_ICDIPTR120_TINT67_SHIFT            (24u)
+
+#define INTC_ICDIPTR121_TINT68_SHIFT            (0u)
+#define INTC_ICDIPTR121_TINT69_SHIFT            (8u)
+#define INTC_ICDIPTR121_TINT70_SHIFT            (16u)
+#define INTC_ICDIPTR121_TINT71_SHIFT            (24u)
+
+#define INTC_ICDIPTR122_TINT72_SHIFT            (0u)
+#define INTC_ICDIPTR122_TINT73_SHIFT            (8u)
+#define INTC_ICDIPTR122_TINT74_SHIFT            (16u)
+#define INTC_ICDIPTR122_TINT75_SHIFT            (24u)
+
+#define INTC_ICDIPTR123_TINT76_SHIFT            (0u)
+#define INTC_ICDIPTR123_TINT77_SHIFT            (8u)
+#define INTC_ICDIPTR123_TINT78_SHIFT            (16u)
+#define INTC_ICDIPTR123_TINT79_SHIFT            (24u)
+
+#define INTC_ICDIPTR124_TINT80_SHIFT            (0u)
+#define INTC_ICDIPTR124_TINT81_SHIFT            (8u)
+#define INTC_ICDIPTR124_TINT82_SHIFT            (16u)
+#define INTC_ICDIPTR124_TINT83_SHIFT            (24u)
+
+#define INTC_ICDIPTR125_TINT84_SHIFT            (0u)
+#define INTC_ICDIPTR125_TINT85_SHIFT            (8u)
+#define INTC_ICDIPTR125_TINT86_SHIFT            (16u)
+#define INTC_ICDIPTR125_TINT87_SHIFT            (24u)
+
+#define INTC_ICDIPTR126_TINT88_SHIFT            (0u)
+#define INTC_ICDIPTR126_TINT89_SHIFT            (8u)
+#define INTC_ICDIPTR126_TINT90_SHIFT            (16u)
+#define INTC_ICDIPTR126_TINT91_SHIFT            (24u)
+
+#define INTC_ICDIPTR127_TINT92_SHIFT            (0u)
+#define INTC_ICDIPTR127_TINT93_SHIFT            (8u)
+#define INTC_ICDIPTR127_TINT94_SHIFT            (16u)
+#define INTC_ICDIPTR127_TINT95_SHIFT            (24u)
+
+#define INTC_ICDIPTR128_TINT96_SHIFT            (0u)
+#define INTC_ICDIPTR128_TINT97_SHIFT            (8u)
+#define INTC_ICDIPTR128_TINT98_SHIFT            (16u)
+#define INTC_ICDIPTR128_TINT99_SHIFT            (24u)
+
+#define INTC_ICDIPTR129_TINT100_SHIFT           (0u)
+#define INTC_ICDIPTR129_TINT101_SHIFT           (8u)
+#define INTC_ICDIPTR129_TINT102_SHIFT           (16u)
+#define INTC_ICDIPTR129_TINT103_SHIFT           (24u)
+
+#define INTC_ICDIPTR130_TINT104_SHIFT           (0u)
+#define INTC_ICDIPTR130_TINT105_SHIFT           (8u)
+#define INTC_ICDIPTR130_TINT106_SHIFT           (16u)
+#define INTC_ICDIPTR130_TINT107_SHIFT           (24u)
+
+#define INTC_ICDIPTR131_TINT108_SHIFT           (0u)
+#define INTC_ICDIPTR131_TINT109_SHIFT           (8u)
+#define INTC_ICDIPTR131_TINT110_SHIFT           (16u)
+#define INTC_ICDIPTR131_TINT111_SHIFT           (24u)
+
+#define INTC_ICDIPTR132_TINT112_SHIFT           (0u)
+#define INTC_ICDIPTR132_TINT113_SHIFT           (8u)
+#define INTC_ICDIPTR132_TINT114_SHIFT           (16u)
+#define INTC_ICDIPTR132_TINT115_SHIFT           (24u)
+
+#define INTC_ICDIPTR133_TINT116_SHIFT           (0u)
+#define INTC_ICDIPTR133_TINT117_SHIFT           (8u)
+#define INTC_ICDIPTR133_TINT118_SHIFT           (16u)
+#define INTC_ICDIPTR133_TINT119_SHIFT           (24u)
+
+#define INTC_ICDIPTR134_TINT120_SHIFT           (0u)
+#define INTC_ICDIPTR134_TINT121_SHIFT           (8u)
+#define INTC_ICDIPTR134_TINT122_SHIFT           (16u)
+#define INTC_ICDIPTR134_TINT123_SHIFT           (24u)
+
+#define INTC_ICDIPTR135_TINT124_SHIFT           (0u)
+#define INTC_ICDIPTR135_TINT125_SHIFT           (8u)
+#define INTC_ICDIPTR135_TINT126_SHIFT           (16u)
+#define INTC_ICDIPTR135_TINT127_SHIFT           (24u)
+
+#define INTC_ICDIPTR136_TINT128_SHIFT           (0u)
+#define INTC_ICDIPTR136_TINT129_SHIFT           (8u)
+#define INTC_ICDIPTR136_TINT130_SHIFT           (16u)
+#define INTC_ICDIPTR136_TINT131_SHIFT           (24u)
+
+#define INTC_ICDIPTR137_TINT132_SHIFT           (0u)
+#define INTC_ICDIPTR137_TINT133_SHIFT           (8u)
+#define INTC_ICDIPTR137_TINT134_SHIFT           (16u)
+#define INTC_ICDIPTR137_TINT135_SHIFT           (24u)
+
+#define INTC_ICDIPTR138_TINT136_SHIFT           (0u)
+#define INTC_ICDIPTR138_TINT137_SHIFT           (8u)
+#define INTC_ICDIPTR138_TINT138_SHIFT           (16u)
+#define INTC_ICDIPTR138_TINT139_SHIFT           (24u)
+
+#define INTC_ICDIPTR139_TINT140_SHIFT           (0u)
+#define INTC_ICDIPTR139_TINT141_SHIFT           (8u)
+#define INTC_ICDIPTR139_TINT142_SHIFT           (16u)
+#define INTC_ICDIPTR139_TINT143_SHIFT           (24u)
+
+#define INTC_ICDIPTR140_TINT144_SHIFT           (0u)
+#define INTC_ICDIPTR140_TINT145_SHIFT           (8u)
+#define INTC_ICDIPTR140_TINT146_SHIFT           (16u)
+#define INTC_ICDIPTR140_TINT147_SHIFT           (24u)
+
+#define INTC_ICDIPTR141_TINT148_SHIFT           (0u)
+#define INTC_ICDIPTR141_TINT149_SHIFT           (8u)
+#define INTC_ICDIPTR141_TINT150_SHIFT           (16u)
+#define INTC_ICDIPTR141_TINT151_SHIFT           (24u)
+
+#define INTC_ICDIPTR142_TINT152_SHIFT           (0u)
+#define INTC_ICDIPTR142_TINT153_SHIFT           (8u)
+#define INTC_ICDIPTR142_TINT154_SHIFT           (16u)
+#define INTC_ICDIPTR142_TINT155_SHIFT           (24u)
+
+#define INTC_ICDIPTR143_TINT156_SHIFT           (0u)
+#define INTC_ICDIPTR143_TINT157_SHIFT           (8u)
+#define INTC_ICDIPTR143_TINT158_SHIFT           (16u)
+#define INTC_ICDIPTR143_TINT159_SHIFT           (24u)
+
+#define INTC_ICDIPTR144_TINT160_SHIFT           (0u)
+#define INTC_ICDIPTR144_TINT161_SHIFT           (8u)
+#define INTC_ICDIPTR144_TINT162_SHIFT           (16u)
+#define INTC_ICDIPTR144_TINT163_SHIFT           (24u)
+
+#define INTC_ICDIPTR145_TINT164_SHIFT           (0u)
+#define INTC_ICDIPTR145_TINT165_SHIFT           (8u)
+#define INTC_ICDIPTR145_TINT166_SHIFT           (16u)
+#define INTC_ICDIPTR145_TINT167_SHIFT           (24u)
+
+#define INTC_ICDIPTR146_TINT168_SHIFT           (0u)
+#define INTC_ICDIPTR146_TINT169_SHIFT           (8u)
+#define INTC_ICDIPTR146_TINT170_SHIFT           (16u)
+
+#define INTC_ICDICFR0_SW0_0_SHIFT               (0u)
+#define INTC_ICDICFR0_SW0_1_SHIFT               (1u)
+#define INTC_ICDICFR0_SW1_0_SHIFT               (2u)
+#define INTC_ICDICFR0_SW1_1_SHIFT               (3u)
+#define INTC_ICDICFR0_SW2_0_SHIFT               (4u)
+#define INTC_ICDICFR0_SW2_1_SHIFT               (5u)
+#define INTC_ICDICFR0_SW3_0_SHIFT               (6u)
+#define INTC_ICDICFR0_SW3_1_SHIFT               (7u)
+#define INTC_ICDICFR0_SW4_0_SHIFT               (8u)
+#define INTC_ICDICFR0_SW4_1_SHIFT               (9u)
+#define INTC_ICDICFR0_SW5_0_SHIFT               (10u)
+#define INTC_ICDICFR0_SW5_1_SHIFT               (11u)
+#define INTC_ICDICFR0_SW6_0_SHIFT               (12u)
+#define INTC_ICDICFR0_SW6_1_SHIFT               (13u)
+#define INTC_ICDICFR0_SW7_0_SHIFT               (14u)
+#define INTC_ICDICFR0_SW7_1_SHIFT               (15u)
+#define INTC_ICDICFR0_SW8_0_SHIFT               (16u)
+#define INTC_ICDICFR0_SW8_1_SHIFT               (17u)
+#define INTC_ICDICFR0_SW9_0_SHIFT               (18u)
+#define INTC_ICDICFR0_SW9_1_SHIFT               (19u)
+#define INTC_ICDICFR0_SW10_0_SHIFT              (20u)
+#define INTC_ICDICFR0_SW10_1_SHIFT              (21u)
+#define INTC_ICDICFR0_SW11_0_SHIFT              (22u)
+#define INTC_ICDICFR0_SW11_1_SHIFT              (23u)
+#define INTC_ICDICFR0_SW12_0_SHIFT              (24u)
+#define INTC_ICDICFR0_SW12_1_SHIFT              (25u)
+#define INTC_ICDICFR0_SW13_0_SHIFT              (26u)
+#define INTC_ICDICFR0_SW13_1_SHIFT              (27u)
+#define INTC_ICDICFR0_SW14_0_SHIFT              (28u)
+#define INTC_ICDICFR0_SW14_1_SHIFT              (29u)
+#define INTC_ICDICFR0_SW15_0_SHIFT              (30u)
+#define INTC_ICDICFR0_SW15_1_SHIFT              (31u)
+
+#define INTC_ICDICFR1_PMUIRQ0_0_SHIFT           (0u)
+#define INTC_ICDICFR1_PMUIRQ0_1_SHIFT           (1u)
+#define INTC_ICDICFR1_COMMRX0_0_SHIFT           (2u)
+#define INTC_ICDICFR1_COMMRX0_1_SHIFT           (3u)
+#define INTC_ICDICFR1_COMMTX0_0_SHIFT           (4u)
+#define INTC_ICDICFR1_COMMTX0_1_SHIFT           (5u)
+#define INTC_ICDICFR1_CTIIRQ0_0_SHIFT           (6u)
+#define INTC_ICDICFR1_CTIIRQ0_1_SHIFT           (7u)
+
+#define INTC_ICDICFR2_IRQ0_0_SHIFT              (0u)
+#define INTC_ICDICFR2_IRQ0_1_SHIFT              (1u)
+#define INTC_ICDICFR2_IRQ1_0_SHIFT              (2u)
+#define INTC_ICDICFR2_IRQ1_1_SHIFT              (3u)
+#define INTC_ICDICFR2_IRQ2_0_SHIFT              (4u)
+#define INTC_ICDICFR2_IRQ2_1_SHIFT              (5u)
+#define INTC_ICDICFR2_IRQ3_0_SHIFT              (6u)
+#define INTC_ICDICFR2_IRQ3_1_SHIFT              (7u)
+#define INTC_ICDICFR2_IRQ4_0_SHIFT              (8u)
+#define INTC_ICDICFR2_IRQ4_1_SHIFT              (9u)
+#define INTC_ICDICFR2_IRQ5_0_SHIFT              (10u)
+#define INTC_ICDICFR2_IRQ5_1_SHIFT              (11u)
+#define INTC_ICDICFR2_IRQ6_0_SHIFT              (12u)
+#define INTC_ICDICFR2_IRQ6_1_SHIFT              (13u)
+#define INTC_ICDICFR2_IRQ7_0_SHIFT              (14u)
+#define INTC_ICDICFR2_IRQ7_1_SHIFT              (15u)
+#define INTC_ICDICFR2_PL310ERR_0_SHIFT          (16u)
+#define INTC_ICDICFR2_PL310ERR_1_SHIFT          (17u)
+#define INTC_ICDICFR2_DMAINT0_0_SHIFT           (18u)
+#define INTC_ICDICFR2_DMAINT0_1_SHIFT           (19u)
+#define INTC_ICDICFR2_DMAINT1_0_SHIFT           (20u)
+#define INTC_ICDICFR2_DMAINT1_1_SHIFT           (21u)
+#define INTC_ICDICFR2_DMAINT2_0_SHIFT           (22u)
+#define INTC_ICDICFR2_DMAINT2_1_SHIFT           (23u)
+#define INTC_ICDICFR2_DMAINT3_0_SHIFT           (24u)
+#define INTC_ICDICFR2_DMAINT3_1_SHIFT           (25u)
+#define INTC_ICDICFR2_DMAINT4_0_SHIFT           (26u)
+#define INTC_ICDICFR2_DMAINT4_1_SHIFT           (27u)
+#define INTC_ICDICFR2_DMAINT5_0_SHIFT           (28u)
+#define INTC_ICDICFR2_DMAINT5_1_SHIFT           (29u)
+#define INTC_ICDICFR2_DMAINT6_0_SHIFT           (30u)
+#define INTC_ICDICFR2_DMAINT6_1_SHIFT           (31u)
+
+#define INTC_ICDICFR3_DMAINT7_0_SHIFT           (0u)
+#define INTC_ICDICFR3_DMAINT7_1_SHIFT           (1u)
+#define INTC_ICDICFR3_DMAINT8_0_SHIFT           (2u)
+#define INTC_ICDICFR3_DMAINT8_1_SHIFT           (3u)
+#define INTC_ICDICFR3_DMAINT9_0_SHIFT           (4u)
+#define INTC_ICDICFR3_DMAINT9_1_SHIFT           (5u)
+#define INTC_ICDICFR3_DMAINT10_0_SHIFT          (6u)
+#define INTC_ICDICFR3_DMAINT10_1_SHIFT          (7u)
+#define INTC_ICDICFR3_DMAINT11_0_SHIFT          (8u)
+#define INTC_ICDICFR3_DMAINT11_1_SHIFT          (9u)
+#define INTC_ICDICFR3_DMAINT12_0_SHIFT          (10u)
+#define INTC_ICDICFR3_DMAINT12_1_SHIFT          (11u)
+#define INTC_ICDICFR3_DMAINT13_0_SHIFT          (12u)
+#define INTC_ICDICFR3_DMAINT13_1_SHIFT          (13u)
+#define INTC_ICDICFR3_DMAINT14_0_SHIFT          (14u)
+#define INTC_ICDICFR3_DMAINT14_1_SHIFT          (15u)
+#define INTC_ICDICFR3_DMAINT15_0_SHIFT          (16u)
+#define INTC_ICDICFR3_DMAINT15_1_SHIFT          (17u)
+#define INTC_ICDICFR3_DMAERR_0_SHIFT            (18u)
+#define INTC_ICDICFR3_DMAERR_1_SHIFT            (19u)
+
+#define INTC_ICDICFR4_USBI0_0_SHIFT             (18u)
+#define INTC_ICDICFR4_USBI0_1_SHIFT             (19u)
+#define INTC_ICDICFR4_USBI1_0_SHIFT             (20u)
+#define INTC_ICDICFR4_USBI1_1_SHIFT             (21u)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_0_SHIFT      (22u)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_1_SHIFT      (23u)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_0_SHIFT      (24u)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_1_SHIFT      (25u)
+#define INTC_ICDICFR4_S0_VSYNCERR0_0_SHIFT      (26u)
+#define INTC_ICDICFR4_S0_VSYNCERR0_1_SHIFT      (27u)
+#define INTC_ICDICFR4_GR3_VLINE0_0_SHIFT        (28u)
+#define INTC_ICDICFR4_GR3_VLINE0_1_SHIFT        (29u)
+#define INTC_ICDICFR4_S0_VFIELD0_0_SHIFT        (30u)
+#define INTC_ICDICFR4_S0_VFIELD0_1_SHIFT        (31u)
+
+#define INTC_ICDICFR5_IV1_VBUFERR0_0_SHIFT      (0u)
+#define INTC_ICDICFR5_IV1_VBUFERR0_1_SHIFT      (1u)
+#define INTC_ICDICFR5_IV3_VBUFERR0_0_SHIFT      (2u)
+#define INTC_ICDICFR5_IV3_VBUFERR0_1_SHIFT      (3u)
+#define INTC_ICDICFR5_IV5_VBUFERR0_0_SHIFT      (4u)
+#define INTC_ICDICFR5_IV5_VBUFERR0_1_SHIFT      (5u)
+#define INTC_ICDICFR5_IV6_VBUFERR0_0_SHIFT      (6u)
+#define INTC_ICDICFR5_IV6_VBUFERR0_1_SHIFT      (7u)
+#define INTC_ICDICFR5_S0_WLINE0_0_SHIFT         (8u)
+#define INTC_ICDICFR5_S0_WLINE0_1_SHIFT         (9u)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_0_SHIFT      (10u)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_1_SHIFT      (11u)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_0_SHIFT      (12u)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_1_SHIFT      (13u)
+#define INTC_ICDICFR5_S1_VSYNCERR0_0_SHIFT      (14u)
+#define INTC_ICDICFR5_S1_VSYNCERR0_1_SHIFT      (15u)
+#define INTC_ICDICFR5_S1_VFIELD0_0_SHIFT        (16u)
+#define INTC_ICDICFR5_S1_VFIELD0_1_SHIFT        (17u)
+#define INTC_ICDICFR5_IV2_VBUFERR0_0_SHIFT      (18u)
+#define INTC_ICDICFR5_IV2_VBUFERR0_1_SHIFT      (19u)
+#define INTC_ICDICFR5_IV4_VBUFERR0_0_SHIFT      (20u)
+#define INTC_ICDICFR5_IV4_VBUFERR0_1_SHIFT      (21u)
+#define INTC_ICDICFR5_S1_WLINE0_0_SHIFT         (22u)
+#define INTC_ICDICFR5_S1_WLINE0_1_SHIFT         (23u)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_0_SHIFT     (24u)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_1_SHIFT     (25u)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_0_SHIFT     (26u)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_1_SHIFT     (27u)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_0_SHIFT     (28u)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_1_SHIFT     (29u)
+#define INTC_ICDICFR5_OIR_VFIELD0_0_SHIFT       (30u)
+#define INTC_ICDICFR5_OIR_VFIELD0_1_SHIFT       (31u)
+
+#define INTC_ICDICFR6_IV7_VBUFERR0_0_SHIFT      (0u)
+#define INTC_ICDICFR6_IV7_VBUFERR0_1_SHIFT      (1u)
+#define INTC_ICDICFR6_IV8_VBUFERR0_0_SHIFT      (2u)
+#define INTC_ICDICFR6_IV8_VBUFERR0_1_SHIFT      (3u)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_0_SHIFT      (6u)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_1_SHIFT      (7u)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_0_SHIFT      (8u)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_1_SHIFT      (9u)
+#define INTC_ICDICFR6_S0_VSYNCERR1_0_SHIFT      (10u)
+#define INTC_ICDICFR6_S0_VSYNCERR1_1_SHIFT      (11u)
+#define INTC_ICDICFR6_GR3_VLINE1_0_SHIFT        (12u)
+#define INTC_ICDICFR6_GR3_VLINE1_1_SHIFT        (13u)
+#define INTC_ICDICFR6_S0_VFIELD1_0_SHIFT        (14u)
+#define INTC_ICDICFR6_S0_VFIELD1_1_SHIFT        (15u)
+#define INTC_ICDICFR6_IV1_VBUFERR1_0_SHIFT      (16u)
+#define INTC_ICDICFR6_IV1_VBUFERR1_1_SHIFT      (17u)
+#define INTC_ICDICFR6_IV3_VBUFERR1_0_SHIFT      (18u)
+#define INTC_ICDICFR6_IV3_VBUFERR1_1_SHIFT      (19u)
+#define INTC_ICDICFR6_IV5_VBUFERR1_0_SHIFT      (20u)
+#define INTC_ICDICFR6_IV5_VBUFERR1_1_SHIFT      (21u)
+#define INTC_ICDICFR6_IV6_VBUFERR1_0_SHIFT      (22u)
+#define INTC_ICDICFR6_IV6_VBUFERR1_1_SHIFT      (23u)
+#define INTC_ICDICFR6_S0_WLINE1_0_SHIFT         (24u)
+#define INTC_ICDICFR6_S0_WLINE1_1_SHIFT         (25u)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_0_SHIFT      (26u)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_1_SHIFT      (27u)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_0_SHIFT      (28u)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_1_SHIFT      (29u)
+#define INTC_ICDICFR6_S1_VSYNCERR1_0_SHIFT      (30u)
+#define INTC_ICDICFR6_S1_VSYNCERR1_1_SHIFT      (31u)
+
+#define INTC_ICDICFR7_S1_VFIELD1_0_SHIFT        (0u)
+#define INTC_ICDICFR7_S1_VFIELD1_1_SHIFT        (1u)
+#define INTC_ICDICFR7_IV2_VBUFERR1_0_SHIFT      (2u)
+#define INTC_ICDICFR7_IV2_VBUFERR1_1_SHIFT      (3u)
+#define INTC_ICDICFR7_IV4_VBUFERR1_0_SHIFT      (4u)
+#define INTC_ICDICFR7_IV4_VBUFERR1_1_SHIFT      (5u)
+#define INTC_ICDICFR7_S1_WLINE1_0_SHIFT         (6u)
+#define INTC_ICDICFR7_S1_WLINE1_1_SHIFT         (7u)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_0_SHIFT     (8u)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_1_SHIFT     (9u)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_0_SHIFT     (10u)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_1_SHIFT     (11u)
+#define INTC_ICDICFR7_OIR_VLINE1_0_SHIFT        (12u)
+#define INTC_ICDICFR7_OIR_VLINE1_1_SHIFT        (13u)
+#define INTC_ICDICFR7_OIR_VFIELD1_0_SHIFT       (14u)
+#define INTC_ICDICFR7_OIR_VFIELD1_1_SHIFT       (15u)
+#define INTC_ICDICFR7_IV7_VBUFERR1_0_SHIFT      (16u)
+#define INTC_ICDICFR7_IV7_VBUFERR1_1_SHIFT      (17u)
+#define INTC_ICDICFR7_IV8_VBUFERR1_0_SHIFT      (18u)
+#define INTC_ICDICFR7_IV8_VBUFERR1_1_SHIFT      (19u)
+#define INTC_ICDICFR7_IMRDI_0_SHIFT             (22u)
+#define INTC_ICDICFR7_IMRDI_1_SHIFT             (23u)
+#define INTC_ICDICFR7_IMR2I0_0_SHIFT            (24u)
+#define INTC_ICDICFR7_IMR2I0_1_SHIFT            (25u)
+#define INTC_ICDICFR7_IMR2I1_0_SHIFT            (26u)
+#define INTC_ICDICFR7_IMR2I1_1_SHIFT            (27u)
+#define INTC_ICDICFR7_JEDI_0_SHIFT              (28u)
+#define INTC_ICDICFR7_JEDI_1_SHIFT              (29u)
+#define INTC_ICDICFR7_JDTI_0_SHIFT              (30u)
+#define INTC_ICDICFR7_JDTI_1_SHIFT              (31u)
+
+#define INTC_ICDICFR8_CMP0_0_SHIFT              (0u)
+#define INTC_ICDICFR8_CMP0_1_SHIFT              (1u)
+#define INTC_ICDICFR8_CMP1_0_SHIFT              (2u)
+#define INTC_ICDICFR8_CMP1_1_SHIFT              (3u)
+#define INTC_ICDICFR8_INT0_0_SHIFT              (4u)
+#define INTC_ICDICFR8_INT0_1_SHIFT              (5u)
+#define INTC_ICDICFR8_INT1_0_SHIFT              (6u)
+#define INTC_ICDICFR8_INT1_1_SHIFT              (7u)
+#define INTC_ICDICFR8_INT2_0_SHIFT              (8u)
+#define INTC_ICDICFR8_INT2_1_SHIFT              (9u)
+#define INTC_ICDICFR8_INT3_0_SHIFT              (10u)
+#define INTC_ICDICFR8_INT3_1_SHIFT              (11u)
+#define INTC_ICDICFR8_OSTM0TINT_0_SHIFT         (12u)
+#define INTC_ICDICFR8_OSTM0TINT_1_SHIFT         (13u)
+#define INTC_ICDICFR8_OSTM1TINT_0_SHIFT         (14u)
+#define INTC_ICDICFR8_OSTM1TINT_1_SHIFT         (15u)
+#define INTC_ICDICFR8_CMI_0_SHIFT               (16u)
+#define INTC_ICDICFR8_CMI_1_SHIFT               (17u)
+#define INTC_ICDICFR8_WTOUT_0_SHIFT             (18u)
+#define INTC_ICDICFR8_WTOUT_1_SHIFT             (19u)
+#define INTC_ICDICFR8_ITI_0_SHIFT               (20u)
+#define INTC_ICDICFR8_ITI_1_SHIFT               (21u)
+#define INTC_ICDICFR8_TGI0A_0_SHIFT             (22u)
+#define INTC_ICDICFR8_TGI0A_1_SHIFT             (23u)
+#define INTC_ICDICFR8_TGI0B_0_SHIFT             (24u)
+#define INTC_ICDICFR8_TGI0B_1_SHIFT             (25u)
+#define INTC_ICDICFR8_TGI0C_0_SHIFT             (26u)
+#define INTC_ICDICFR8_TGI0C_1_SHIFT             (27u)
+#define INTC_ICDICFR8_TGI0D_0_SHIFT             (28u)
+#define INTC_ICDICFR8_TGI0D_1_SHIFT             (29u)
+#define INTC_ICDICFR8_TGI0V_0_SHIFT             (30u)
+#define INTC_ICDICFR8_TGI0V_1_SHIFT             (31u)
+
+#define INTC_ICDICFR9_TGI0E_0_SHIFT             (0u)
+#define INTC_ICDICFR9_TGI0E_1_SHIFT             (1u)
+#define INTC_ICDICFR9_TGI0F_0_SHIFT             (2u)
+#define INTC_ICDICFR9_TGI0F_1_SHIFT             (3u)
+#define INTC_ICDICFR9_TGI1A_0_SHIFT             (4u)
+#define INTC_ICDICFR9_TGI1A_1_SHIFT             (5u)
+#define INTC_ICDICFR9_TGI1B_0_SHIFT             (6u)
+#define INTC_ICDICFR9_TGI1B_1_SHIFT             (7u)
+#define INTC_ICDICFR9_TGI1V_0_SHIFT             (8u)
+#define INTC_ICDICFR9_TGI1V_1_SHIFT             (9u)
+#define INTC_ICDICFR9_TGI1U_0_SHIFT             (10u)
+#define INTC_ICDICFR9_TGI1U_1_SHIFT             (11u)
+#define INTC_ICDICFR9_TGI2A_0_SHIFT             (12u)
+#define INTC_ICDICFR9_TGI2A_1_SHIFT             (13u)
+#define INTC_ICDICFR9_TGI2B_0_SHIFT             (14u)
+#define INTC_ICDICFR9_TGI2B_1_SHIFT             (15u)
+#define INTC_ICDICFR9_TGI2V_0_SHIFT             (16u)
+#define INTC_ICDICFR9_TGI2V_1_SHIFT             (17u)
+#define INTC_ICDICFR9_TGI2U_0_SHIFT             (18u)
+#define INTC_ICDICFR9_TGI2U_1_SHIFT             (19u)
+#define INTC_ICDICFR9_TGI3A_0_SHIFT             (20u)
+#define INTC_ICDICFR9_TGI3A_1_SHIFT             (21u)
+#define INTC_ICDICFR9_TGI3B_0_SHIFT             (22u)
+#define INTC_ICDICFR9_TGI3B_1_SHIFT             (23u)
+#define INTC_ICDICFR9_TGI3C_0_SHIFT             (24u)
+#define INTC_ICDICFR9_TGI3C_1_SHIFT             (25u)
+#define INTC_ICDICFR9_TGI3D_0_SHIFT             (26u)
+#define INTC_ICDICFR9_TGI3D_1_SHIFT             (27u)
+#define INTC_ICDICFR9_TGI3V_0_SHIFT             (28u)
+#define INTC_ICDICFR9_TGI3V_1_SHIFT             (29u)
+#define INTC_ICDICFR9_TGI4A_0_SHIFT             (30u)
+#define INTC_ICDICFR9_TGI4A_1_SHIFT             (31u)
+
+#define INTC_ICDICFR10_TGI4B_0_SHIFT            (0u)
+#define INTC_ICDICFR10_TGI4B_1_SHIFT            (1u)
+#define INTC_ICDICFR10_TGI4C_0_SHIFT            (2u)
+#define INTC_ICDICFR10_TGI4C_1_SHIFT            (3u)
+#define INTC_ICDICFR10_TGI4D_0_SHIFT            (4u)
+#define INTC_ICDICFR10_TGI4D_1_SHIFT            (5u)
+#define INTC_ICDICFR10_TGI4V_0_SHIFT            (6u)
+#define INTC_ICDICFR10_TGI4V_1_SHIFT            (7u)
+#define INTC_ICDICFR10_CMI1_0_SHIFT             (8u)
+#define INTC_ICDICFR10_CMI1_1_SHIFT             (9u)
+#define INTC_ICDICFR10_CMI2_0_SHIFT             (10u)
+#define INTC_ICDICFR10_CMI2_1_SHIFT             (11u)
+#define INTC_ICDICFR10_SGDEI0_0_SHIFT           (12u)
+#define INTC_ICDICFR10_SGDEI0_1_SHIFT           (13u)
+#define INTC_ICDICFR10_SGDEI1_0_SHIFT           (14u)
+#define INTC_ICDICFR10_SGDEI1_1_SHIFT           (15u)
+#define INTC_ICDICFR10_SGDEI2_0_SHIFT           (16u)
+#define INTC_ICDICFR10_SGDEI2_1_SHIFT           (17u)
+#define INTC_ICDICFR10_SGDEI3_0_SHIFT           (18u)
+#define INTC_ICDICFR10_SGDEI3_1_SHIFT           (19u)
+#define INTC_ICDICFR10_ADI_0_SHIFT              (20u)
+#define INTC_ICDICFR10_ADI_1_SHIFT              (21u)
+#define INTC_ICDICFR10_LMTI_0_SHIFT             (22u)
+#define INTC_ICDICFR10_LMTI_1_SHIFT             (23u)
+#define INTC_ICDICFR10_SSII0_0_SHIFT            (24u)
+#define INTC_ICDICFR10_SSII0_1_SHIFT            (25u)
+#define INTC_ICDICFR10_SSIRXI0_0_SHIFT          (26u)
+#define INTC_ICDICFR10_SSIRXI0_1_SHIFT          (27u)
+#define INTC_ICDICFR10_SSITXI0_0_SHIFT          (28u)
+#define INTC_ICDICFR10_SSITXI0_1_SHIFT          (29u)
+#define INTC_ICDICFR10_SSII1_0_SHIFT            (30u)
+#define INTC_ICDICFR10_SSII1_1_SHIFT            (31u)
+
+#define INTC_ICDICFR11_SSIRXI1_0_SHIFT          (0u)
+#define INTC_ICDICFR11_SSIRXI1_1_SHIFT          (1u)
+#define INTC_ICDICFR11_SSITXI1_0_SHIFT          (2u)
+#define INTC_ICDICFR11_SSITXI1_1_SHIFT          (3u)
+#define INTC_ICDICFR11_SSII2_0_SHIFT            (4u)
+#define INTC_ICDICFR11_SSII2_1_SHIFT            (5u)
+#define INTC_ICDICFR11_SSIRTI2_0_SHIFT          (6u)
+#define INTC_ICDICFR11_SSIRTI2_1_SHIFT          (7u)
+#define INTC_ICDICFR11_SSII3_0_SHIFT            (8u)
+#define INTC_ICDICFR11_SSII3_1_SHIFT            (9u)
+#define INTC_ICDICFR11_SSIRXI3_0_SHIFT          (10u)
+#define INTC_ICDICFR11_SSIRXI3_1_SHIFT          (11u)
+#define INTC_ICDICFR11_SSITXI3_0_SHIFT          (12u)
+#define INTC_ICDICFR11_SSITXI3_1_SHIFT          (13u)
+#define INTC_ICDICFR11_SSII4_0_SHIFT            (14u)
+#define INTC_ICDICFR11_SSII4_1_SHIFT            (15u)
+#define INTC_ICDICFR11_SSIRTI4_0_SHIFT          (16u)
+#define INTC_ICDICFR11_SSIRTI4_1_SHIFT          (17u)
+#define INTC_ICDICFR11_SSII5_0_SHIFT            (18u)
+#define INTC_ICDICFR11_SSII5_1_SHIFT            (19u)
+#define INTC_ICDICFR11_SSIRXI5_0_SHIFT          (20u)
+#define INTC_ICDICFR11_SSIRXI5_1_SHIFT          (21u)
+#define INTC_ICDICFR11_SSITXI5_0_SHIFT          (22u)
+#define INTC_ICDICFR11_SSITXI5_1_SHIFT          (23u)
+#define INTC_ICDICFR11_SPDIFI_0_SHIFT           (24u)
+#define INTC_ICDICFR11_SPDIFI_1_SHIFT           (25u)
+#define INTC_ICDICFR11_INTIICTEI0_0_SHIFT       (26u)
+#define INTC_ICDICFR11_INTIICTEI0_1_SHIFT       (27u)
+#define INTC_ICDICFR11_INTIICRI0_0_SHIFT        (28u)
+#define INTC_ICDICFR11_INTIICRI0_1_SHIFT        (29u)
+#define INTC_ICDICFR11_INTIICTI0_0_SHIFT        (30u)
+#define INTC_ICDICFR11_INTIICTI0_1_SHIFT        (31u)
+
+#define INTC_ICDICFR12_INTIICSPI0_0_SHIFT       (0u)
+#define INTC_ICDICFR12_INTIICSPI0_1_SHIFT       (1u)
+#define INTC_ICDICFR12_INTIICSTI0_0_SHIFT       (2u)
+#define INTC_ICDICFR12_INTIICSTI0_1_SHIFT       (3u)
+#define INTC_ICDICFR12_INTIICNAKI0_0_SHIFT      (4u)
+#define INTC_ICDICFR12_INTIICNAKI0_1_SHIFT      (5u)
+#define INTC_ICDICFR12_INTIICALI0_0_SHIFT       (6u)
+#define INTC_ICDICFR12_INTIICALI0_1_SHIFT       (7u)
+#define INTC_ICDICFR12_INTIICTMOI0_0_SHIFT      (8u)
+#define INTC_ICDICFR12_INTIICTMOI0_1_SHIFT      (9u)
+#define INTC_ICDICFR12_INTIICTEI1_0_SHIFT       (10u)
+#define INTC_ICDICFR12_INTIICTEI1_1_SHIFT       (11u)
+#define INTC_ICDICFR12_INTIICRI1_0_SHIFT        (12u)
+#define INTC_ICDICFR12_INTIICRI1_1_SHIFT        (13u)
+#define INTC_ICDICFR12_INTIICTI1_0_SHIFT        (14u)
+#define INTC_ICDICFR12_INTIICTI1_1_SHIFT        (15u)
+#define INTC_ICDICFR12_INTIICSPI1_0_SHIFT       (16u)
+#define INTC_ICDICFR12_INTIICSPI1_1_SHIFT       (17u)
+#define INTC_ICDICFR12_INTIICSTI1_0_SHIFT       (18u)
+#define INTC_ICDICFR12_INTIICSTI1_1_SHIFT       (19u)
+#define INTC_ICDICFR12_INTIICNAKI1_0_SHIFT      (20u)
+#define INTC_ICDICFR12_INTIICNAKI1_1_SHIFT      (21u)
+#define INTC_ICDICFR12_INTIICALI1_0_SHIFT       (22u)
+#define INTC_ICDICFR12_INTIICALI1_1_SHIFT       (23u)
+#define INTC_ICDICFR12_INTIICTMOI1_0_SHIFT      (24u)
+#define INTC_ICDICFR12_INTIICTMOI1_1_SHIFT      (25u)
+#define INTC_ICDICFR12_INTIICTEI2_0_SHIFT       (26u)
+#define INTC_ICDICFR12_INTIICTEI2_1_SHIFT       (27u)
+#define INTC_ICDICFR12_INTIICRI2_0_SHIFT        (28u)
+#define INTC_ICDICFR12_INTIICRI2_1_SHIFT        (29u)
+#define INTC_ICDICFR12_INTIICTI2_0_SHIFT        (30u)
+#define INTC_ICDICFR12_INTIICTI2_1_SHIFT        (31u)
+
+#define INTC_ICDICFR13_INTIICSPI2_0_SHIFT       (0u)
+#define INTC_ICDICFR13_INTIICSPI2_1_SHIFT       (1u)
+#define INTC_ICDICFR13_INTIICSTI2_0_SHIFT       (2u)
+#define INTC_ICDICFR13_INTIICSTI2_1_SHIFT       (3u)
+#define INTC_ICDICFR13_INTIICNAKI2_0_SHIFT      (4u)
+#define INTC_ICDICFR13_INTIICNAKI2_1_SHIFT      (5u)
+#define INTC_ICDICFR13_INTIICALI2_0_SHIFT       (6u)
+#define INTC_ICDICFR13_INTIICALI2_1_SHIFT       (7u)
+#define INTC_ICDICFR13_INTIICTMOI2_0_SHIFT      (8u)
+#define INTC_ICDICFR13_INTIICTMOI2_1_SHIFT      (9u)
+#define INTC_ICDICFR13_INTIICTEI3_0_SHIFT       (10u)
+#define INTC_ICDICFR13_INTIICTEI3_1_SHIFT       (11u)
+#define INTC_ICDICFR13_INTIICRI3_0_SHIFT        (12u)
+#define INTC_ICDICFR13_INTIICRI3_1_SHIFT        (13u)
+#define INTC_ICDICFR13_INTIICTI3_0_SHIFT        (14u)
+#define INTC_ICDICFR13_INTIICTI3_1_SHIFT        (15u)
+#define INTC_ICDICFR13_INTIICSPI3_0_SHIFT       (16u)
+#define INTC_ICDICFR13_INTIICSPI3_1_SHIFT       (17u)
+#define INTC_ICDICFR13_INTIICSTI3_0_SHIFT       (18u)
+#define INTC_ICDICFR13_INTIICSTI3_1_SHIFT       (19u)
+#define INTC_ICDICFR13_INTIICNAKI3_0_SHIFT      (20u)
+#define INTC_ICDICFR13_INTIICNAKI3_1_SHIFT      (21u)
+#define INTC_ICDICFR13_INTIICALI3_0_SHIFT       (22u)
+#define INTC_ICDICFR13_INTIICALI3_1_SHIFT       (23u)
+#define INTC_ICDICFR13_INTIICTMOI3_0_SHIFT      (24u)
+#define INTC_ICDICFR13_INTIICTMOI3_1_SHIFT      (25u)
+#define INTC_ICDICFR13_BRI0_0_SHIFT             (26u)
+#define INTC_ICDICFR13_BRI0_1_SHIFT             (27u)
+#define INTC_ICDICFR13_ERI0_0_SHIFT             (28u)
+#define INTC_ICDICFR13_ERI0_1_SHIFT             (29u)
+#define INTC_ICDICFR13_RXI0_0_SHIFT             (30u)
+#define INTC_ICDICFR13_RXI0_1_SHIFT             (31u)
+
+#define INTC_ICDICFR14_TXI0_0_SHIFT             (0u)
+#define INTC_ICDICFR14_TXI0_1_SHIFT             (1u)
+#define INTC_ICDICFR14_BRI1_0_SHIFT             (2u)
+#define INTC_ICDICFR14_BRI1_1_SHIFT             (3u)
+#define INTC_ICDICFR14_ERI1_0_SHIFT             (4u)
+#define INTC_ICDICFR14_ERI1_1_SHIFT             (5u)
+#define INTC_ICDICFR14_RXI1_0_SHIFT             (6u)
+#define INTC_ICDICFR14_RXI1_1_SHIFT             (7u)
+#define INTC_ICDICFR14_TXI1_0_SHIFT             (8u)
+#define INTC_ICDICFR14_TXI1_1_SHIFT             (9u)
+#define INTC_ICDICFR14_BRI2_0_SHIFT             (10u)
+#define INTC_ICDICFR14_BRI2_1_SHIFT             (11u)
+#define INTC_ICDICFR14_ERI2_0_SHIFT             (12u)
+#define INTC_ICDICFR14_ERI2_1_SHIFT             (13u)
+#define INTC_ICDICFR14_RXI2_0_SHIFT             (14u)
+#define INTC_ICDICFR14_RXI2_1_SHIFT             (15u)
+#define INTC_ICDICFR14_TXI2_0_SHIFT             (16u)
+#define INTC_ICDICFR14_TXI2_1_SHIFT             (17u)
+#define INTC_ICDICFR14_BRI3_0_SHIFT             (18u)
+#define INTC_ICDICFR14_BRI3_1_SHIFT             (19u)
+#define INTC_ICDICFR14_ERI3_0_SHIFT             (20u)
+#define INTC_ICDICFR14_ERI3_1_SHIFT             (21u)
+#define INTC_ICDICFR14_RXI3_0_SHIFT             (22u)
+#define INTC_ICDICFR14_RXI3_1_SHIFT             (23u)
+#define INTC_ICDICFR14_TXI3_0_SHIFT             (24u)
+#define INTC_ICDICFR14_TXI3_1_SHIFT             (25u)
+#define INTC_ICDICFR14_BRI4_0_SHIFT             (26u)
+#define INTC_ICDICFR14_BRI4_1_SHIFT             (27u)
+#define INTC_ICDICFR14_ERI4_0_SHIFT             (28u)
+#define INTC_ICDICFR14_ERI4_1_SHIFT             (29u)
+#define INTC_ICDICFR14_RXI4_0_SHIFT             (30u)
+#define INTC_ICDICFR14_RXI4_1_SHIFT             (31u)
+
+#define INTC_ICDICFR15_TXI4_0_SHIFT             (0u)
+#define INTC_ICDICFR15_TXI4_1_SHIFT             (1u)
+#define INTC_ICDICFR15_BRI5_0_SHIFT             (2u)
+#define INTC_ICDICFR15_BRI5_1_SHIFT             (3u)
+#define INTC_ICDICFR15_ERI5_0_SHIFT             (4u)
+#define INTC_ICDICFR15_ERI5_1_SHIFT             (5u)
+#define INTC_ICDICFR15_RXI5_0_SHIFT             (6u)
+#define INTC_ICDICFR15_RXI5_1_SHIFT             (7u)
+#define INTC_ICDICFR15_TXI5_0_SHIFT             (8u)
+#define INTC_ICDICFR15_TXI5_1_SHIFT             (9u)
+#define INTC_ICDICFR15_BRI6_0_SHIFT             (10u)
+#define INTC_ICDICFR15_BRI6_1_SHIFT             (11u)
+#define INTC_ICDICFR15_ERI6_0_SHIFT             (12u)
+#define INTC_ICDICFR15_ERI6_1_SHIFT             (13u)
+#define INTC_ICDICFR15_RXI6_0_SHIFT             (14u)
+#define INTC_ICDICFR15_RXI6_1_SHIFT             (15u)
+#define INTC_ICDICFR15_TXI6_0_SHIFT             (16u)
+#define INTC_ICDICFR15_TXI6_1_SHIFT             (17u)
+#define INTC_ICDICFR15_BRI7_0_SHIFT             (18u)
+#define INTC_ICDICFR15_BRI7_1_SHIFT             (19u)
+#define INTC_ICDICFR15_ERI7_0_SHIFT             (20u)
+#define INTC_ICDICFR15_ERI7_1_SHIFT             (21u)
+#define INTC_ICDICFR15_RXI7_0_SHIFT             (22u)
+#define INTC_ICDICFR15_RXI7_1_SHIFT             (23u)
+#define INTC_ICDICFR15_TXI7_0_SHIFT             (24u)
+#define INTC_ICDICFR15_TXI7_1_SHIFT             (25u)
+#define INTC_ICDICFR15_INTRCANGERR_0_SHIFT      (26u)
+#define INTC_ICDICFR15_INTRCANGERR_1_SHIFT      (27u)
+#define INTC_ICDICFR15_INTRCANGRECC_0_SHIFT     (28u)
+#define INTC_ICDICFR15_INTRCANGRECC_1_SHIFT     (29u)
+#define INTC_ICDICFR15_INTRCAN0REC_0_SHIFT      (30u)
+#define INTC_ICDICFR15_INTRCAN0REC_1_SHIFT      (31u)
+
+#define INTC_ICDICFR16_INTRCAN0ERR_0_SHIFT      (0u)
+#define INTC_ICDICFR16_INTRCAN0ERR_1_SHIFT      (1u)
+#define INTC_ICDICFR16_INTRCAN0TRX_0_SHIFT      (2u)
+#define INTC_ICDICFR16_INTRCAN0TRX_1_SHIFT      (3u)
+#define INTC_ICDICFR16_INTRCAN1REC_0_SHIFT      (4u)
+#define INTC_ICDICFR16_INTRCAN1REC_1_SHIFT      (5u)
+#define INTC_ICDICFR16_INTRCAN1ERR_0_SHIFT      (6u)
+#define INTC_ICDICFR16_INTRCAN1ERR_1_SHIFT      (7u)
+#define INTC_ICDICFR16_INTRCAN1TRX_0_SHIFT      (8u)
+#define INTC_ICDICFR16_INTRCAN1TRX_1_SHIFT      (9u)
+#define INTC_ICDICFR16_INTRCAN2REC_0_SHIFT      (10u)
+#define INTC_ICDICFR16_INTRCAN2REC_1_SHIFT      (11u)
+#define INTC_ICDICFR16_INTRCAN2ERR_0_SHIFT      (12u)
+#define INTC_ICDICFR16_INTRCAN2ERR_1_SHIFT      (13u)
+#define INTC_ICDICFR16_INTRCAN2TRX_0_SHIFT      (14u)
+#define INTC_ICDICFR16_INTRCAN2TRX_1_SHIFT      (15u)
+#define INTC_ICDICFR16_INTRCAN3REC_0_SHIFT      (16u)
+#define INTC_ICDICFR16_INTRCAN3REC_1_SHIFT      (17u)
+#define INTC_ICDICFR16_INTRCAN3ERR_0_SHIFT      (18u)
+#define INTC_ICDICFR16_INTRCAN3ERR_1_SHIFT      (19u)
+#define INTC_ICDICFR16_INTRCAN3TRX_0_SHIFT      (20u)
+#define INTC_ICDICFR16_INTRCAN3TRX_1_SHIFT      (21u)
+#define INTC_ICDICFR16_INTRCAN4REC_0_SHIFT      (22u)
+#define INTC_ICDICFR16_INTRCAN4REC_1_SHIFT      (23u)
+#define INTC_ICDICFR16_INTRCAN4ERR_0_SHIFT      (24u)
+#define INTC_ICDICFR16_INTRCAN4ERR_1_SHIFT      (25u)
+#define INTC_ICDICFR16_INTRCAN4TRX_0_SHIFT      (26u)
+#define INTC_ICDICFR16_INTRCAN4TRX_1_SHIFT      (27u)
+#define INTC_ICDICFR16_SPEI0_0_SHIFT            (28u)
+#define INTC_ICDICFR16_SPEI0_1_SHIFT            (29u)
+#define INTC_ICDICFR16_SPRI0_0_SHIFT            (30u)
+#define INTC_ICDICFR16_SPRI0_1_SHIFT            (31u)
+
+#define INTC_ICDICFR17_SPTI0_0_SHIFT            (0u)
+#define INTC_ICDICFR17_SPTI0_1_SHIFT            (1u)
+#define INTC_ICDICFR17_SPEI1_0_SHIFT            (2u)
+#define INTC_ICDICFR17_SPEI1_1_SHIFT            (3u)
+#define INTC_ICDICFR17_SPRI1_0_SHIFT            (4u)
+#define INTC_ICDICFR17_SPRI1_1_SHIFT            (5u)
+#define INTC_ICDICFR17_SPTI1_0_SHIFT            (6u)
+#define INTC_ICDICFR17_SPTI1_1_SHIFT            (7u)
+#define INTC_ICDICFR17_SPEI2_0_SHIFT            (8u)
+#define INTC_ICDICFR17_SPEI2_1_SHIFT            (9u)
+#define INTC_ICDICFR17_SPRI2_0_SHIFT            (10u)
+#define INTC_ICDICFR17_SPRI2_1_SHIFT            (11u)
+#define INTC_ICDICFR17_SPTI2_0_SHIFT            (12u)
+#define INTC_ICDICFR17_SPTI2_1_SHIFT            (13u)
+#define INTC_ICDICFR17_SPEI3_0_SHIFT            (14u)
+#define INTC_ICDICFR17_SPEI3_1_SHIFT            (15u)
+#define INTC_ICDICFR17_SPRI3_0_SHIFT            (16u)
+#define INTC_ICDICFR17_SPRI3_1_SHIFT            (17u)
+#define INTC_ICDICFR17_SPTI3_0_SHIFT            (18u)
+#define INTC_ICDICFR17_SPTI3_1_SHIFT            (19u)
+#define INTC_ICDICFR17_SPEI4_0_SHIFT            (20u)
+#define INTC_ICDICFR17_SPEI4_1_SHIFT            (21u)
+#define INTC_ICDICFR17_SPRI4_0_SHIFT            (22u)
+#define INTC_ICDICFR17_SPRI4_1_SHIFT            (23u)
+#define INTC_ICDICFR17_SPTI4_0_SHIFT            (24u)
+#define INTC_ICDICFR17_SPTI4_1_SHIFT            (25u)
+#define INTC_ICDICFR17_IEBBTD_0_SHIFT           (26u)
+#define INTC_ICDICFR17_IEBBTD_1_SHIFT           (27u)
+#define INTC_ICDICFR17_IEBBTERR_0_SHIFT         (28u)
+#define INTC_ICDICFR17_IEBBTERR_1_SHIFT         (29u)
+#define INTC_ICDICFR17_IEBBTSTA_0_SHIFT         (30u)
+#define INTC_ICDICFR17_IEBBTSTA_1_SHIFT         (31u)
+
+#define INTC_ICDICFR18_IEBBTV_0_SHIFT           (0u)
+#define INTC_ICDICFR18_IEBBTV_1_SHIFT           (1u)
+#define INTC_ICDICFR18_ISY_0_SHIFT              (2u)
+#define INTC_ICDICFR18_ISY_1_SHIFT              (3u)
+#define INTC_ICDICFR18_IERR_0_SHIFT             (4u)
+#define INTC_ICDICFR18_IERR_1_SHIFT             (5u)
+#define INTC_ICDICFR18_ITARG_0_SHIFT            (6u)
+#define INTC_ICDICFR18_ITARG_1_SHIFT            (7u)
+#define INTC_ICDICFR18_ISEC_0_SHIFT             (8u)
+#define INTC_ICDICFR18_ISEC_1_SHIFT             (9u)
+#define INTC_ICDICFR18_IBUF_0_SHIFT             (10u)
+#define INTC_ICDICFR18_IBUF_1_SHIFT             (11u)
+#define INTC_ICDICFR18_IREADY_0_SHIFT           (12u)
+#define INTC_ICDICFR18_IREADY_1_SHIFT           (13u)
+#define INTC_ICDICFR18_FLSTE_0_SHIFT            (14u)
+#define INTC_ICDICFR18_FLSTE_1_SHIFT            (15u)
+#define INTC_ICDICFR18_FLTENDI_0_SHIFT          (16u)
+#define INTC_ICDICFR18_FLTENDI_1_SHIFT          (17u)
+#define INTC_ICDICFR18_FLTREQ0I_0_SHIFT         (18u)
+#define INTC_ICDICFR18_FLTREQ0I_1_SHIFT         (19u)
+#define INTC_ICDICFR18_FLTREQ1I_0_SHIFT         (20u)
+#define INTC_ICDICFR18_FLTREQ1I_1_SHIFT         (21u)
+#define INTC_ICDICFR18_MMC0_0_SHIFT             (22u)
+#define INTC_ICDICFR18_MMC0_1_SHIFT             (23u)
+#define INTC_ICDICFR18_MMC1_0_SHIFT             (24u)
+#define INTC_ICDICFR18_MMC1_1_SHIFT             (25u)
+#define INTC_ICDICFR18_MMC2_0_SHIFT             (26u)
+#define INTC_ICDICFR18_MMC2_1_SHIFT             (27u)
+#define INTC_ICDICFR18_SDHI0_3_0_SHIFT          (28u)
+#define INTC_ICDICFR18_SDHI0_3_1_SHIFT          (29u)
+#define INTC_ICDICFR18_SDHI0_0_0_SHIFT          (30u)
+#define INTC_ICDICFR18_SDHI0_0_1_SHIFT          (31u)
+
+#define INTC_ICDICFR19_SDHI0_1_0_SHIFT          (0u)
+#define INTC_ICDICFR19_SDHI0_1_1_SHIFT          (1u)
+#define INTC_ICDICFR19_SDHI1_3_0_SHIFT          (2u)
+#define INTC_ICDICFR19_SDHI1_3_1_SHIFT          (3u)
+#define INTC_ICDICFR19_SDHI1_0_0_SHIFT          (4u)
+#define INTC_ICDICFR19_SDHI1_0_1_SHIFT          (5u)
+#define INTC_ICDICFR19_SDHI1_1_0_SHIFT          (6u)
+#define INTC_ICDICFR19_SDHI1_1_1_SHIFT          (7u)
+#define INTC_ICDICFR19_ARM_0_SHIFT              (8u)
+#define INTC_ICDICFR19_ARM_1_SHIFT              (9u)
+#define INTC_ICDICFR19_PRD_0_SHIFT              (10u)
+#define INTC_ICDICFR19_PRD_1_SHIFT              (11u)
+#define INTC_ICDICFR19_CUP_0_SHIFT              (12u)
+#define INTC_ICDICFR19_CUP_1_SHIFT              (13u)
+#define INTC_ICDICFR19_SCUAI0_0_SHIFT           (14u)
+#define INTC_ICDICFR19_SCUAI0_1_SHIFT           (15u)
+#define INTC_ICDICFR19_SCUAI1_0_SHIFT           (16u)
+#define INTC_ICDICFR19_SCUAI1_1_SHIFT           (17u)
+#define INTC_ICDICFR19_SCUFDI0_0_SHIFT          (18u)
+#define INTC_ICDICFR19_SCUFDI0_1_SHIFT          (19u)
+#define INTC_ICDICFR19_SCUFDI1_0_SHIFT          (20u)
+#define INTC_ICDICFR19_SCUFDI1_1_SHIFT          (21u)
+#define INTC_ICDICFR19_SCUFDI2_0_SHIFT          (22u)
+#define INTC_ICDICFR19_SCUFDI2_1_SHIFT          (23u)
+#define INTC_ICDICFR19_SCUFDI3_0_SHIFT          (24u)
+#define INTC_ICDICFR19_SCUFDI3_1_SHIFT          (25u)
+#define INTC_ICDICFR19_SCUFUI0_0_SHIFT          (26u)
+#define INTC_ICDICFR19_SCUFUI0_1_SHIFT          (27u)
+#define INTC_ICDICFR19_SCUFUI1_0_SHIFT          (28u)
+#define INTC_ICDICFR19_SCUFUI1_1_SHIFT          (29u)
+#define INTC_ICDICFR19_SCUFUI2_0_SHIFT          (30u)
+#define INTC_ICDICFR19_SCUFUI2_1_SHIFT          (31u)
+
+#define INTC_ICDICFR20_SCUFUI3_0_SHIFT          (0u)
+#define INTC_ICDICFR20_SCUFUI3_1_SHIFT          (1u)
+#define INTC_ICDICFR20_SCUDVI0_0_SHIFT          (2u)
+#define INTC_ICDICFR20_SCUDVI0_1_SHIFT          (3u)
+#define INTC_ICDICFR20_SCUDVI1_0_SHIFT          (4u)
+#define INTC_ICDICFR20_SCUDVI1_1_SHIFT          (5u)
+#define INTC_ICDICFR20_SCUDVI2_0_SHIFT          (6u)
+#define INTC_ICDICFR20_SCUDVI2_1_SHIFT          (7u)
+#define INTC_ICDICFR20_SCUDVI3_0_SHIFT          (8u)
+#define INTC_ICDICFR20_SCUDVI3_1_SHIFT          (9u)
+#define INTC_ICDICFR20_MLB_CINT_0_SHIFT         (10u)
+#define INTC_ICDICFR20_MLB_CINT_1_SHIFT         (11u)
+#define INTC_ICDICFR20_MLB_SINT_0_SHIFT         (12u)
+#define INTC_ICDICFR20_MLB_SINT_1_SHIFT         (13u)
+#define INTC_ICDICFR20_DRC0_0_SHIFT             (14u)
+#define INTC_ICDICFR20_DRC0_1_SHIFT             (15u)
+#define INTC_ICDICFR20_DRC1_0_SHIFT             (16u)
+#define INTC_ICDICFR20_DRC1_1_SHIFT             (17u)
+#define INTC_ICDICFR20_LINI0_INT_T_0_SHIFT      (22u)
+#define INTC_ICDICFR20_LINI0_INT_T_1_SHIFT      (23u)
+#define INTC_ICDICFR20_LINI0_INT_R_0_SHIFT      (24u)
+#define INTC_ICDICFR20_LINI0_INT_R_1_SHIFT      (25u)
+#define INTC_ICDICFR20_LINI0_INT_S_0_SHIFT      (26u)
+#define INTC_ICDICFR20_LINI0_INT_S_1_SHIFT      (27u)
+#define INTC_ICDICFR20_LINI0_INT_M_0_SHIFT      (28u)
+#define INTC_ICDICFR20_LINI0_INT_M_1_SHIFT      (29u)
+#define INTC_ICDICFR20_LINI1_INT_T_0_SHIFT      (30u)
+#define INTC_ICDICFR20_LINI1_INT_T_1_SHIFT      (31u)
+
+#define INTC_ICDICFR21_LINI1_INT_R_0_SHIFT      (0u)
+#define INTC_ICDICFR21_LINI1_INT_R_1_SHIFT      (1u)
+#define INTC_ICDICFR21_LINI1_INT_S_0_SHIFT      (2u)
+#define INTC_ICDICFR21_LINI1_INT_S_1_SHIFT      (3u)
+#define INTC_ICDICFR21_LINI1_INT_M_0_SHIFT      (4u)
+#define INTC_ICDICFR21_LINI1_INT_M_1_SHIFT      (5u)
+#define INTC_ICDICFR21_ERI0_0_SHIFT             (22u)
+#define INTC_ICDICFR21_ERI0_1_SHIFT             (23u)
+#define INTC_ICDICFR21_RXI0_0_SHIFT             (24u)
+#define INTC_ICDICFR21_RXI0_1_SHIFT             (25u)
+#define INTC_ICDICFR21_TXI0_0_SHIFT             (26u)
+#define INTC_ICDICFR21_TXI0_1_SHIFT             (27u)
+#define INTC_ICDICFR21_TEI0_0_SHIFT             (28u)
+#define INTC_ICDICFR21_TEI0_1_SHIFT             (29u)
+#define INTC_ICDICFR21_ERI1_0_SHIFT             (30u)
+#define INTC_ICDICFR21_ERI1_1_SHIFT             (31u)
+
+#define INTC_ICDICFR22_RXI1_0_SHIFT             (0u)
+#define INTC_ICDICFR22_RXI1_1_SHIFT             (1u)
+#define INTC_ICDICFR22_TXI1_0_SHIFT             (2u)
+#define INTC_ICDICFR22_TXI1_1_SHIFT             (3u)
+#define INTC_ICDICFR22_TEI1_0_SHIFT             (4u)
+#define INTC_ICDICFR22_TEI1_1_SHIFT             (5u)
+#define INTC_ICDICFR22_AVBI_DATA_0_SHIFT        (6u)
+#define INTC_ICDICFR22_AVBI_DATA_1_SHIFT        (7u)
+#define INTC_ICDICFR22_AVBI_ERROR_0_SHIFT       (8u)
+#define INTC_ICDICFR22_AVBI_ERROR_1_SHIFT       (9u)
+#define INTC_ICDICFR22_AVBI_MANAGE_0_SHIFT      (10u)
+#define INTC_ICDICFR22_AVBI_MANAGE_1_SHIFT      (11u)
+#define INTC_ICDICFR22_AVBI_MAC_0_SHIFT         (12u)
+#define INTC_ICDICFR22_AVBI_MAC_1_SHIFT         (13u)
+#define INTC_ICDICFR22_ETHERI_0_SHIFT           (14u)
+#define INTC_ICDICFR22_ETHERI_1_SHIFT           (15u)
+#define INTC_ICDICFR22_CEUI_0_SHIFT             (24u)
+#define INTC_ICDICFR22_CEUI_1_SHIFT             (25u)
+
+#define INTC_ICDICFR23_H2XMLB_ERRINT_0_SHIFT    (26u)
+#define INTC_ICDICFR23_H2XMLB_ERRINT_1_SHIFT    (27u)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_0_SHIFT    (28u)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_1_SHIFT    (29u)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_0_SHIFT  (30u)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_1_SHIFT  (31u)
+
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_0_SHIFT  (0u)
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_1_SHIFT  (1u)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_0_SHIFT (2u)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_1_SHIFT (3u)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_0_SHIFT  (4u)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_1_SHIFT  (5u)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_0_SHIFT (6u)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_1_SHIFT (7u)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_0_SHIFT   (8u)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_1_SHIFT   (9u)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_0_SHIFT    (10u)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_1_SHIFT    (11u)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_0_SHIFT   (12u)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_1_SHIFT   (13u)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_0_SHIFT   (14u)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_1_SHIFT   (15u)
+#define INTC_ICDICFR24_PRRI_0_SHIFT             (16u)
+#define INTC_ICDICFR24_PRRI_1_SHIFT             (17u)
+#define INTC_ICDICFR24_IFEI0_0_SHIFT            (18u)
+#define INTC_ICDICFR24_IFEI0_1_SHIFT            (19u)
+#define INTC_ICDICFR24_OFFI0_0_SHIFT            (20u)
+#define INTC_ICDICFR24_OFFI0_1_SHIFT            (21u)
+#define INTC_ICDICFR24_PFVEI0_0_SHIFT           (22u)
+#define INTC_ICDICFR24_PFVEI0_1_SHIFT           (23u)
+#define INTC_ICDICFR24_IFEI1_0_SHIFT            (24u)
+#define INTC_ICDICFR24_IFEI1_1_SHIFT            (25u)
+#define INTC_ICDICFR24_OFFI1_0_SHIFT            (26u)
+#define INTC_ICDICFR24_OFFI1_1_SHIFT            (27u)
+#define INTC_ICDICFR24_PFVEI1_0_SHIFT           (28u)
+#define INTC_ICDICFR24_PFVEI1_1_SHIFT           (29u)
+
+#define INTC_ICDICFR26_TINT0_0_SHIFT            (0u)
+#define INTC_ICDICFR26_TINT0_1_SHIFT            (1u)
+#define INTC_ICDICFR26_TINT1_0_SHIFT            (2u)
+#define INTC_ICDICFR26_TINT1_1_SHIFT            (3u)
+#define INTC_ICDICFR26_TINT2_0_SHIFT            (4u)
+#define INTC_ICDICFR26_TINT2_1_SHIFT            (5u)
+#define INTC_ICDICFR26_TINT3_0_SHIFT            (6u)
+#define INTC_ICDICFR26_TINT3_1_SHIFT            (7u)
+#define INTC_ICDICFR26_TINT4_0_SHIFT            (8u)
+#define INTC_ICDICFR26_TINT4_1_SHIFT            (9u)
+#define INTC_ICDICFR26_TINT5_0_SHIFT            (10u)
+#define INTC_ICDICFR26_TINT5_1_SHIFT            (11u)
+#define INTC_ICDICFR26_TINT6_0_SHIFT            (12u)
+#define INTC_ICDICFR26_TINT6_1_SHIFT            (13u)
+#define INTC_ICDICFR26_TINT7_0_SHIFT            (14u)
+#define INTC_ICDICFR26_TINT7_1_SHIFT            (15u)
+#define INTC_ICDICFR26_TINT8_0_SHIFT            (16u)
+#define INTC_ICDICFR26_TINT8_1_SHIFT            (17u)
+#define INTC_ICDICFR26_TINT9_0_SHIFT            (18u)
+#define INTC_ICDICFR26_TINT9_1_SHIFT            (19u)
+#define INTC_ICDICFR26_TINT10_0_SHIFT           (20u)
+#define INTC_ICDICFR26_TINT10_1_SHIFT           (21u)
+#define INTC_ICDICFR26_TINT11_0_SHIFT           (22u)
+#define INTC_ICDICFR26_TINT11_1_SHIFT           (23u)
+#define INTC_ICDICFR26_TINT12_0_SHIFT           (24u)
+#define INTC_ICDICFR26_TINT12_1_SHIFT           (25u)
+#define INTC_ICDICFR26_TINT13_0_SHIFT           (26u)
+#define INTC_ICDICFR26_TINT13_1_SHIFT           (27u)
+#define INTC_ICDICFR26_TINT14_0_SHIFT           (28u)
+#define INTC_ICDICFR26_TINT14_1_SHIFT           (29u)
+#define INTC_ICDICFR26_TINT15_0_SHIFT           (30u)
+#define INTC_ICDICFR26_TINT15_1_SHIFT           (31u)
+
+#define INTC_ICDICFR27_TINT16_0_SHIFT           (0u)
+#define INTC_ICDICFR27_TINT16_1_SHIFT           (1u)
+#define INTC_ICDICFR27_TINT17_0_SHIFT           (2u)
+#define INTC_ICDICFR27_TINT17_1_SHIFT           (3u)
+#define INTC_ICDICFR27_TINT18_0_SHIFT           (4u)
+#define INTC_ICDICFR27_TINT18_1_SHIFT           (5u)
+#define INTC_ICDICFR27_TINT19_0_SHIFT           (6u)
+#define INTC_ICDICFR27_TINT19_1_SHIFT           (7u)
+#define INTC_ICDICFR27_TINT20_0_SHIFT           (8u)
+#define INTC_ICDICFR27_TINT20_1_SHIFT           (9u)
+#define INTC_ICDICFR27_TINT21_0_SHIFT           (10u)
+#define INTC_ICDICFR27_TINT21_1_SHIFT           (11u)
+#define INTC_ICDICFR27_TINT22_0_SHIFT           (12u)
+#define INTC_ICDICFR27_TINT22_1_SHIFT           (13u)
+#define INTC_ICDICFR27_TINT23_0_SHIFT           (14u)
+#define INTC_ICDICFR27_TINT23_1_SHIFT           (15u)
+#define INTC_ICDICFR27_TINT24_0_SHIFT           (16u)
+#define INTC_ICDICFR27_TINT24_1_SHIFT           (17u)
+#define INTC_ICDICFR27_TINT25_0_SHIFT           (18u)
+#define INTC_ICDICFR27_TINT25_1_SHIFT           (19u)
+#define INTC_ICDICFR27_TINT26_0_SHIFT           (20u)
+#define INTC_ICDICFR27_TINT26_1_SHIFT           (21u)
+#define INTC_ICDICFR27_TINT27_0_SHIFT           (22u)
+#define INTC_ICDICFR27_TINT27_1_SHIFT           (23u)
+#define INTC_ICDICFR27_TINT28_0_SHIFT           (24u)
+#define INTC_ICDICFR27_TINT28_1_SHIFT           (25u)
+#define INTC_ICDICFR27_TINT29_0_SHIFT           (26u)
+#define INTC_ICDICFR27_TINT29_1_SHIFT           (27u)
+#define INTC_ICDICFR27_TINT30_0_SHIFT           (28u)
+#define INTC_ICDICFR27_TINT30_1_SHIFT           (29u)
+#define INTC_ICDICFR27_TINT31_0_SHIFT           (30u)
+#define INTC_ICDICFR27_TINT31_1_SHIFT           (31u)
+
+#define INTC_ICDICFR28_TINT32_0_SHIFT           (0u)
+#define INTC_ICDICFR28_TINT32_1_SHIFT           (1u)
+#define INTC_ICDICFR28_TINT33_0_SHIFT           (2u)
+#define INTC_ICDICFR28_TINT33_1_SHIFT           (3u)
+#define INTC_ICDICFR28_TINT34_0_SHIFT           (4u)
+#define INTC_ICDICFR28_TINT34_1_SHIFT           (5u)
+#define INTC_ICDICFR28_TINT35_0_SHIFT           (6u)
+#define INTC_ICDICFR28_TINT35_1_SHIFT           (7u)
+#define INTC_ICDICFR28_TINT36_0_SHIFT           (8u)
+#define INTC_ICDICFR28_TINT36_1_SHIFT           (9u)
+#define INTC_ICDICFR28_TINT37_0_SHIFT           (10u)
+#define INTC_ICDICFR28_TINT37_1_SHIFT           (11u)
+#define INTC_ICDICFR28_TINT38_0_SHIFT           (12u)
+#define INTC_ICDICFR28_TINT38_1_SHIFT           (13u)
+#define INTC_ICDICFR28_TINT39_0_SHIFT           (14u)
+#define INTC_ICDICFR28_TINT39_1_SHIFT           (15u)
+#define INTC_ICDICFR28_TINT40_0_SHIFT           (16u)
+#define INTC_ICDICFR28_TINT40_1_SHIFT           (17u)
+#define INTC_ICDICFR28_TINT41_0_SHIFT           (18u)
+#define INTC_ICDICFR28_TINT41_1_SHIFT           (19u)
+#define INTC_ICDICFR28_TINT42_0_SHIFT           (20u)
+#define INTC_ICDICFR28_TINT42_1_SHIFT           (21u)
+#define INTC_ICDICFR28_TINT43_0_SHIFT           (22u)
+#define INTC_ICDICFR28_TINT43_1_SHIFT           (23u)
+#define INTC_ICDICFR28_TINT44_0_SHIFT           (24u)
+#define INTC_ICDICFR28_TINT44_1_SHIFT           (25u)
+#define INTC_ICDICFR28_TINT45_0_SHIFT           (26u)
+#define INTC_ICDICFR28_TINT45_1_SHIFT           (27u)
+#define INTC_ICDICFR28_TINT46_0_SHIFT           (28u)
+#define INTC_ICDICFR28_TINT46_1_SHIFT           (29u)
+#define INTC_ICDICFR28_TINT47_0_SHIFT           (30u)
+#define INTC_ICDICFR28_TINT47_1_SHIFT           (31u)
+
+#define INTC_ICDICFR29_TINT48_0_SHIFT           (0u)
+#define INTC_ICDICFR29_TINT48_1_SHIFT           (1u)
+#define INTC_ICDICFR29_TINT49_0_SHIFT           (2u)
+#define INTC_ICDICFR29_TINT49_1_SHIFT           (3u)
+#define INTC_ICDICFR29_TINT50_0_SHIFT           (4u)
+#define INTC_ICDICFR29_TINT50_1_SHIFT           (5u)
+#define INTC_ICDICFR29_TINT51_0_SHIFT           (6u)
+#define INTC_ICDICFR29_TINT51_1_SHIFT           (7u)
+#define INTC_ICDICFR29_TINT52_0_SHIFT           (8u)
+#define INTC_ICDICFR29_TINT52_1_SHIFT           (9u)
+#define INTC_ICDICFR29_TINT53_0_SHIFT           (10u)
+#define INTC_ICDICFR29_TINT53_1_SHIFT           (11u)
+#define INTC_ICDICFR29_TINT54_0_SHIFT           (12u)
+#define INTC_ICDICFR29_TINT54_1_SHIFT           (13u)
+#define INTC_ICDICFR29_TINT55_0_SHIFT           (14u)
+#define INTC_ICDICFR29_TINT55_1_SHIFT           (15u)
+#define INTC_ICDICFR29_TINT56_0_SHIFT           (16u)
+#define INTC_ICDICFR29_TINT56_1_SHIFT           (17u)
+#define INTC_ICDICFR29_TINT57_0_SHIFT           (18u)
+#define INTC_ICDICFR29_TINT57_1_SHIFT           (19u)
+#define INTC_ICDICFR29_TINT58_0_SHIFT           (20u)
+#define INTC_ICDICFR29_TINT58_1_SHIFT           (21u)
+#define INTC_ICDICFR29_TINT59_0_SHIFT           (22u)
+#define INTC_ICDICFR29_TINT59_1_SHIFT           (23u)
+#define INTC_ICDICFR29_TINT60_0_SHIFT           (24u)
+#define INTC_ICDICFR29_TINT60_1_SHIFT           (25u)
+#define INTC_ICDICFR29_TINT61_0_SHIFT           (26u)
+#define INTC_ICDICFR29_TINT61_1_SHIFT           (27u)
+#define INTC_ICDICFR29_TINT62_0_SHIFT           (28u)
+#define INTC_ICDICFR29_TINT62_1_SHIFT           (29u)
+#define INTC_ICDICFR29_TINT63_0_SHIFT           (30u)
+#define INTC_ICDICFR29_TINT63_1_SHIFT           (31u)
+
+#define INTC_ICDICFR30_TINT64_0_SHIFT           (0u)
+#define INTC_ICDICFR30_TINT64_1_SHIFT           (1u)
+#define INTC_ICDICFR30_TINT65_0_SHIFT           (2u)
+#define INTC_ICDICFR30_TINT65_1_SHIFT           (3u)
+#define INTC_ICDICFR30_TINT66_0_SHIFT           (4u)
+#define INTC_ICDICFR30_TINT66_1_SHIFT           (5u)
+#define INTC_ICDICFR30_TINT67_0_SHIFT           (6u)
+#define INTC_ICDICFR30_TINT67_1_SHIFT           (7u)
+#define INTC_ICDICFR30_TINT68_0_SHIFT           (8u)
+#define INTC_ICDICFR30_TINT68_1_SHIFT           (9u)
+#define INTC_ICDICFR30_TINT69_0_SHIFT           (10u)
+#define INTC_ICDICFR30_TINT69_1_SHIFT           (11u)
+#define INTC_ICDICFR30_TINT70_0_SHIFT           (12u)
+#define INTC_ICDICFR30_TINT70_1_SHIFT           (13u)
+#define INTC_ICDICFR30_TINT71_0_SHIFT           (14u)
+#define INTC_ICDICFR30_TINT71_1_SHIFT           (15u)
+#define INTC_ICDICFR30_TINT72_0_SHIFT           (16u)
+#define INTC_ICDICFR30_TINT72_1_SHIFT           (17u)
+#define INTC_ICDICFR30_TINT73_0_SHIFT           (18u)
+#define INTC_ICDICFR30_TINT73_1_SHIFT           (19u)
+#define INTC_ICDICFR30_TINT74_0_SHIFT           (20u)
+#define INTC_ICDICFR30_TINT74_1_SHIFT           (21u)
+#define INTC_ICDICFR30_TINT75_0_SHIFT           (22u)
+#define INTC_ICDICFR30_TINT75_1_SHIFT           (23u)
+#define INTC_ICDICFR30_TINT76_0_SHIFT           (24u)
+#define INTC_ICDICFR30_TINT76_1_SHIFT           (25u)
+#define INTC_ICDICFR30_TINT77_0_SHIFT           (26u)
+#define INTC_ICDICFR30_TINT77_1_SHIFT           (27u)
+#define INTC_ICDICFR30_TINT78_0_SHIFT           (28u)
+#define INTC_ICDICFR30_TINT78_1_SHIFT           (29u)
+#define INTC_ICDICFR30_TINT79_0_SHIFT           (30u)
+#define INTC_ICDICFR30_TINT79_1_SHIFT           (31u)
+
+#define INTC_ICDICFR31_TINT80_0_SHIFT           (0u)
+#define INTC_ICDICFR31_TINT80_1_SHIFT           (1u)
+#define INTC_ICDICFR31_TINT81_0_SHIFT           (2u)
+#define INTC_ICDICFR31_TINT81_1_SHIFT           (3u)
+#define INTC_ICDICFR31_TINT82_0_SHIFT           (4u)
+#define INTC_ICDICFR31_TINT82_1_SHIFT           (5u)
+#define INTC_ICDICFR31_TINT83_0_SHIFT           (6u)
+#define INTC_ICDICFR31_TINT83_1_SHIFT           (7u)
+#define INTC_ICDICFR31_TINT84_0_SHIFT           (8u)
+#define INTC_ICDICFR31_TINT84_1_SHIFT           (9u)
+#define INTC_ICDICFR31_TINT85_0_SHIFT           (10u)
+#define INTC_ICDICFR31_TINT85_1_SHIFT           (11u)
+#define INTC_ICDICFR31_TINT86_0_SHIFT           (12u)
+#define INTC_ICDICFR31_TINT86_1_SHIFT           (13u)
+#define INTC_ICDICFR31_TINT87_0_SHIFT           (14u)
+#define INTC_ICDICFR31_TINT87_1_SHIFT           (15u)
+#define INTC_ICDICFR31_TINT88_0_SHIFT           (16u)
+#define INTC_ICDICFR31_TINT88_1_SHIFT           (17u)
+#define INTC_ICDICFR31_TINT89_0_SHIFT           (18u)
+#define INTC_ICDICFR31_TINT89_1_SHIFT           (19u)
+#define INTC_ICDICFR31_TINT90_0_SHIFT           (20u)
+#define INTC_ICDICFR31_TINT90_1_SHIFT           (21u)
+#define INTC_ICDICFR31_TINT91_0_SHIFT           (22u)
+#define INTC_ICDICFR31_TINT91_1_SHIFT           (23u)
+#define INTC_ICDICFR31_TINT92_0_SHIFT           (24u)
+#define INTC_ICDICFR31_TINT92_1_SHIFT           (25u)
+#define INTC_ICDICFR31_TINT93_0_SHIFT           (26u)
+#define INTC_ICDICFR31_TINT93_1_SHIFT           (27u)
+#define INTC_ICDICFR31_TINT94_0_SHIFT           (28u)
+#define INTC_ICDICFR31_TINT94_1_SHIFT           (29u)
+#define INTC_ICDICFR31_TINT95_0_SHIFT           (30u)
+#define INTC_ICDICFR31_TINT95_1_SHIFT           (31u)
+
+#define INTC_ICDICFR32_TINT96_0_SHIFT           (0u)
+#define INTC_ICDICFR32_TINT96_1_SHIFT           (1u)
+#define INTC_ICDICFR32_TINT97_0_SHIFT           (2u)
+#define INTC_ICDICFR32_TINT97_1_SHIFT           (3u)
+#define INTC_ICDICFR32_TINT98_0_SHIFT           (4u)
+#define INTC_ICDICFR32_TINT98_1_SHIFT           (5u)
+#define INTC_ICDICFR32_TINT99_0_SHIFT           (6u)
+#define INTC_ICDICFR32_TINT99_1_SHIFT           (7u)
+#define INTC_ICDICFR32_TINT100_0_SHIFT          (8u)
+#define INTC_ICDICFR32_TINT100_1_SHIFT          (9u)
+#define INTC_ICDICFR32_TINT101_0_SHIFT          (10u)
+#define INTC_ICDICFR32_TINT101_1_SHIFT          (11u)
+#define INTC_ICDICFR32_TINT102_0_SHIFT          (12u)
+#define INTC_ICDICFR32_TINT102_1_SHIFT          (13u)
+#define INTC_ICDICFR32_TINT103_0_SHIFT          (14u)
+#define INTC_ICDICFR32_TINT103_1_SHIFT          (15u)
+#define INTC_ICDICFR32_TINT104_0_SHIFT          (16u)
+#define INTC_ICDICFR32_TINT104_1_SHIFT          (17u)
+#define INTC_ICDICFR32_TINT105_0_SHIFT          (18u)
+#define INTC_ICDICFR32_TINT105_1_SHIFT          (19u)
+#define INTC_ICDICFR32_TINT106_0_SHIFT          (20u)
+#define INTC_ICDICFR32_TINT106_1_SHIFT          (21u)
+#define INTC_ICDICFR32_TINT107_0_SHIFT          (22u)
+#define INTC_ICDICFR32_TINT107_1_SHIFT          (23u)
+#define INTC_ICDICFR32_TINT108_0_SHIFT          (24u)
+#define INTC_ICDICFR32_TINT108_1_SHIFT          (25u)
+#define INTC_ICDICFR32_TINT109_0_SHIFT          (26u)
+#define INTC_ICDICFR32_TINT109_1_SHIFT          (27u)
+#define INTC_ICDICFR32_TINT110_0_SHIFT          (28u)
+#define INTC_ICDICFR32_TINT110_1_SHIFT          (29u)
+#define INTC_ICDICFR32_TINT111_0_SHIFT          (30u)
+#define INTC_ICDICFR32_TINT111_1_SHIFT          (31u)
+
+#define INTC_ICDICFR33_TINT112_0_SHIFT          (0u)
+#define INTC_ICDICFR33_TINT112_1_SHIFT          (1u)
+#define INTC_ICDICFR33_TINT113_0_SHIFT          (2u)
+#define INTC_ICDICFR33_TINT113_1_SHIFT          (3u)
+#define INTC_ICDICFR33_TINT114_0_SHIFT          (4u)
+#define INTC_ICDICFR33_TINT114_1_SHIFT          (5u)
+#define INTC_ICDICFR33_TINT115_0_SHIFT          (6u)
+#define INTC_ICDICFR33_TINT115_1_SHIFT          (7u)
+#define INTC_ICDICFR33_TINT116_0_SHIFT          (8u)
+#define INTC_ICDICFR33_TINT116_1_SHIFT          (9u)
+#define INTC_ICDICFR33_TINT117_0_SHIFT          (10u)
+#define INTC_ICDICFR33_TINT117_1_SHIFT          (11u)
+#define INTC_ICDICFR33_TINT118_0_SHIFT          (12u)
+#define INTC_ICDICFR33_TINT118_1_SHIFT          (13u)
+#define INTC_ICDICFR33_TINT119_0_SHIFT          (14u)
+#define INTC_ICDICFR33_TINT119_1_SHIFT          (15u)
+#define INTC_ICDICFR33_TINT120_0_SHIFT          (16u)
+#define INTC_ICDICFR33_TINT120_1_SHIFT          (17u)
+#define INTC_ICDICFR33_TINT121_0_SHIFT          (18u)
+#define INTC_ICDICFR33_TINT121_1_SHIFT          (19u)
+#define INTC_ICDICFR33_TINT122_0_SHIFT          (20u)
+#define INTC_ICDICFR33_TINT122_1_SHIFT          (21u)
+#define INTC_ICDICFR33_TINT123_0_SHIFT          (22u)
+#define INTC_ICDICFR33_TINT123_1_SHIFT          (23u)
+#define INTC_ICDICFR33_TINT124_0_SHIFT          (24u)
+#define INTC_ICDICFR33_TINT124_1_SHIFT          (25u)
+#define INTC_ICDICFR33_TINT125_0_SHIFT          (26u)
+#define INTC_ICDICFR33_TINT125_1_SHIFT          (27u)
+#define INTC_ICDICFR33_TINT126_0_SHIFT          (28u)
+#define INTC_ICDICFR33_TINT126_1_SHIFT          (29u)
+#define INTC_ICDICFR33_TINT127_0_SHIFT          (30u)
+#define INTC_ICDICFR33_TINT127_1_SHIFT          (31u)
+
+#define INTC_ICDICFR34_TINT128_0_SHIFT          (0u)
+#define INTC_ICDICFR34_TINT128_1_SHIFT          (1u)
+#define INTC_ICDICFR34_TINT129_0_SHIFT          (2u)
+#define INTC_ICDICFR34_TINT129_1_SHIFT          (3u)
+#define INTC_ICDICFR34_TINT130_0_SHIFT          (4u)
+#define INTC_ICDICFR34_TINT130_1_SHIFT          (5u)
+#define INTC_ICDICFR34_TINT131_0_SHIFT          (6u)
+#define INTC_ICDICFR34_TINT131_1_SHIFT          (7u)
+#define INTC_ICDICFR34_TINT132_0_SHIFT          (8u)
+#define INTC_ICDICFR34_TINT132_1_SHIFT          (9u)
+#define INTC_ICDICFR34_TINT133_0_SHIFT          (10u)
+#define INTC_ICDICFR34_TINT133_1_SHIFT          (11u)
+#define INTC_ICDICFR34_TINT134_0_SHIFT          (12u)
+#define INTC_ICDICFR34_TINT134_1_SHIFT          (13u)
+#define INTC_ICDICFR34_TINT135_0_SHIFT          (14u)
+#define INTC_ICDICFR34_TINT135_1_SHIFT          (15u)
+#define INTC_ICDICFR34_TINT136_0_SHIFT          (16u)
+#define INTC_ICDICFR34_TINT136_1_SHIFT          (17u)
+#define INTC_ICDICFR34_TINT137_0_SHIFT          (18u)
+#define INTC_ICDICFR34_TINT137_1_SHIFT          (19u)
+#define INTC_ICDICFR34_TINT138_0_SHIFT          (20u)
+#define INTC_ICDICFR34_TINT138_1_SHIFT          (21u)
+#define INTC_ICDICFR34_TINT139_0_SHIFT          (22u)
+#define INTC_ICDICFR34_TINT139_1_SHIFT          (23u)
+#define INTC_ICDICFR34_TINT140_0_SHIFT          (24u)
+#define INTC_ICDICFR34_TINT140_1_SHIFT          (25u)
+#define INTC_ICDICFR34_TINT141_0_SHIFT          (26u)
+#define INTC_ICDICFR34_TINT141_1_SHIFT          (27u)
+#define INTC_ICDICFR34_TINT142_0_SHIFT          (28u)
+#define INTC_ICDICFR34_TINT142_1_SHIFT          (29u)
+#define INTC_ICDICFR34_TINT143_0_SHIFT          (30u)
+#define INTC_ICDICFR34_TINT143_1_SHIFT          (31u)
+
+#define INTC_ICDICFR35_TINT144_0_SHIFT          (0u)
+#define INTC_ICDICFR35_TINT144_1_SHIFT          (1u)
+#define INTC_ICDICFR35_TINT145_0_SHIFT          (2u)
+#define INTC_ICDICFR35_TINT145_1_SHIFT          (3u)
+#define INTC_ICDICFR35_TINT146_0_SHIFT          (4u)
+#define INTC_ICDICFR35_TINT146_1_SHIFT          (5u)
+#define INTC_ICDICFR35_TINT147_0_SHIFT          (6u)
+#define INTC_ICDICFR35_TINT147_1_SHIFT          (7u)
+#define INTC_ICDICFR35_TINT148_0_SHIFT          (8u)
+#define INTC_ICDICFR35_TINT148_1_SHIFT          (9u)
+#define INTC_ICDICFR35_TINT149_0_SHIFT          (10u)
+#define INTC_ICDICFR35_TINT149_1_SHIFT          (11u)
+#define INTC_ICDICFR35_TINT150_0_SHIFT          (12u)
+#define INTC_ICDICFR35_TINT150_1_SHIFT          (13u)
+#define INTC_ICDICFR35_TINT151_0_SHIFT          (14u)
+#define INTC_ICDICFR35_TINT151_1_SHIFT          (15u)
+#define INTC_ICDICFR35_TINT152_0_SHIFT          (16u)
+#define INTC_ICDICFR35_TINT152_1_SHIFT          (17u)
+#define INTC_ICDICFR35_TINT153_0_SHIFT          (18u)
+#define INTC_ICDICFR35_TINT153_1_SHIFT          (19u)
+#define INTC_ICDICFR35_TINT154_0_SHIFT          (20u)
+#define INTC_ICDICFR35_TINT154_1_SHIFT          (21u)
+#define INTC_ICDICFR35_TINT155_0_SHIFT          (22u)
+#define INTC_ICDICFR35_TINT155_1_SHIFT          (23u)
+#define INTC_ICDICFR35_TINT156_0_SHIFT          (24u)
+#define INTC_ICDICFR35_TINT156_1_SHIFT          (25u)
+#define INTC_ICDICFR35_TINT157_0_SHIFT          (26u)
+#define INTC_ICDICFR35_TINT157_1_SHIFT          (27u)
+#define INTC_ICDICFR35_TINT158_0_SHIFT          (28u)
+#define INTC_ICDICFR35_TINT158_1_SHIFT          (29u)
+#define INTC_ICDICFR35_TINT159_0_SHIFT          (30u)
+#define INTC_ICDICFR35_TINT159_1_SHIFT          (31u)
+
+#define INTC_ICDICFR36_TINT160_0_SHIFT          (0u)
+#define INTC_ICDICFR36_TINT160_1_SHIFT          (1u)
+#define INTC_ICDICFR36_TINT161_0_SHIFT          (2u)
+#define INTC_ICDICFR36_TINT161_1_SHIFT          (3u)
+#define INTC_ICDICFR36_TINT162_0_SHIFT          (4u)
+#define INTC_ICDICFR36_TINT162_1_SHIFT          (5u)
+#define INTC_ICDICFR36_TINT163_0_SHIFT          (6u)
+#define INTC_ICDICFR36_TINT163_1_SHIFT          (7u)
+#define INTC_ICDICFR36_TINT164_0_SHIFT          (8u)
+#define INTC_ICDICFR36_TINT164_1_SHIFT          (9u)
+#define INTC_ICDICFR36_TINT165_0_SHIFT          (10u)
+#define INTC_ICDICFR36_TINT165_1_SHIFT          (11u)
+#define INTC_ICDICFR36_TINT166_0_SHIFT          (12u)
+#define INTC_ICDICFR36_TINT166_1_SHIFT          (13u)
+#define INTC_ICDICFR36_TINT167_0_SHIFT          (14u)
+#define INTC_ICDICFR36_TINT167_1_SHIFT          (15u)
+#define INTC_ICDICFR36_TINT168_0_SHIFT          (16u)
+#define INTC_ICDICFR36_TINT168_1_SHIFT          (17u)
+#define INTC_ICDICFR36_TINT169_0_SHIFT          (18u)
+#define INTC_ICDICFR36_TINT169_1_SHIFT          (19u)
+#define INTC_ICDICFR36_TINT170_0_SHIFT          (20u)
+#define INTC_ICDICFR36_TINT170_1_SHIFT          (21u)
+
+#define INTC_ICDSGIR_SGIINTID_SHIFT             (0u)
+#define INTC_ICDSGIR_SATT_SHIFT                 (15u)
+#define INTC_ICDSGIR_CPUTargetList_SHIFT        (16u)
+#define INTC_ICDSGIR_TargetListFilter_SHIFT     (24u)
+
+#define INTC_ICCICR_EnableS_SHIFT               (0u)
+#define INTC_ICCICR_EnableNS_SHIFT              (1u)
+#define INTC_ICCICR_AckCtl_SHIFT                (2u)
+#define INTC_ICCICR_FIQEn_SHIFT                 (3u)
+#define INTC_ICCICR_SBPR_SHIFT                  (4u)
+
+#define INTC_ICCPMR_Priority_SHIFT              (0u)
+
+#define INTC_ICCBPR_Binarypoint_SHIFT           (0u)
+
+#define INTC_ICCIAR_ACKINTID_SHIFT              (0u)
+#define INTC_ICCIAR_CPUID_SHIFT                 (10u)
+
+#define INTC_ICCEOIR_EOIINTID_SHIFT             (0u)
+#define INTC_ICCEOIR_CPUID_SHIFT                (10u)
+
+#define INTC_ICCRPR_Priority_SHIFT              (0u)
+
+#define INTC_ICCHPIR_PENDINTID_SHIFT            (0u)
+#define INTC_ICCHPIR_CPUID_SHIFT                (10u)
+
+#define INTC_ICCABPR_Binarypoint_SHIFT          (0u)
+
+#define INTC_ICCIIDR_Implementer_SHIFT          (0u)
+#define INTC_ICCIIDR_Revision_SHIFT             (12u)
+#define INTC_ICCIIDR_Architecture_version_SHIFT (16u)
+#define INTC_ICCIIDR_ProductID_SHIFT            (20u)
+
+#define INTC_ICR0_NMIF_SHIFT                    (1u)
+#define INTC_ICR0_NMIE_SHIFT                    (8u)
+#define INTC_ICR0_NMIL_SHIFT                    (15u)
+
+#define INTC_ICR1_IRQ00S_SHIFT                  (0u)
+#define INTC_ICR1_IRQ01S_SHIFT                  (1u)
+#define INTC_ICR1_IRQ10S_SHIFT                  (2u)
+#define INTC_ICR1_IRQ11S_SHIFT                  (3u)
+#define INTC_ICR1_IRQ20S_SHIFT                  (4u)
+#define INTC_ICR1_IRQ21S_SHIFT                  (5u)
+#define INTC_ICR1_IRQ30S_SHIFT                  (6u)
+#define INTC_ICR1_IRQ31S_SHIFT                  (7u)
+#define INTC_ICR1_IRQ40S_SHIFT                  (8u)
+#define INTC_ICR1_IRQ41S_SHIFT                  (9u)
+#define INTC_ICR1_IRQ50S_SHIFT                  (10u)
+#define INTC_ICR1_IRQ51S_SHIFT                  (11u)
+#define INTC_ICR1_IRQ60S_SHIFT                  (12u)
+#define INTC_ICR1_IRQ61S_SHIFT                  (13u)
+#define INTC_ICR1_IRQ70S_SHIFT                  (14u)
+#define INTC_ICR1_IRQ71S_SHIFT                  (15u)
+
+#define INTC_IRQRR_IRQ0F_SHIFT                  (0u)
+#define INTC_IRQRR_IRQ1F_SHIFT                  (1u)
+#define INTC_IRQRR_IRQ2F_SHIFT                  (2u)
+#define INTC_IRQRR_IRQ3F_SHIFT                  (3u)
+#define INTC_IRQRR_IRQ4F_SHIFT                  (4u)
+#define INTC_IRQRR_IRQ5F_SHIFT                  (5u)
+#define INTC_IRQRR_IRQ6F_SHIFT                  (6u)
+#define INTC_IRQRR_IRQ7F_SHIFT                  (7u)
+
+
+#endif /* INTC_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h	(revision 374)
@@ -0,0 +1,462 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : mtu2_iobitmask.h
+* $Rev: 1138 $
+* $Date:: 2014-08-08 11:03:56 +0900#$
+* Description : MTU2 register define header
+*******************************************************************************/
+#ifndef MTU2_IOBITMASK_H
+#define MTU2_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define MTU2_TCR_n_TPSC                         (0x07u)
+#define MTU2_TCR_n_CKEG                         (0x18u)
+#define MTU2_TCR_n_CCLR                         (0xE0u)
+
+#define MTU2_TMDR_n_MD                          (0x0Fu)
+
+#define MTU2_TIOR_2_IOA                         (0x0Fu)
+#define MTU2_TIOR_2_IOB                         (0xF0u)
+
+#define MTU2_TIER_n_TGIEA                       (0x01u)
+#define MTU2_TIER_n_TGIEB                       (0x02u)
+#define MTU2_TIER_n_TCIEV                       (0x10u)
+#define MTU2_TIER_2_TCIEU                       (0x20u)
+#define MTU2_TIER_n_TTGE                        (0x80u)
+
+#define MTU2_TSR_n_TGFA                         (0x01u)
+#define MTU2_TSR_n_TGFB                         (0x02u)
+#define MTU2_TSR_n_TCFV                         (0x10u)
+#define MTU2_TSR_2_TCFU                         (0x20u)
+#define MTU2_TSR_2_TCFD                         (0x80u)
+
+#define MTU2_TCNT_n_D                           (0xFFFFu)
+
+#define MTU2_TGRA_n_D                           (0xFFFFu)
+
+#define MTU2_TGRB_n_D                           (0xFFFFu)
+
+#define MTU2_TMDR_3_BFA                         (0x10u)
+#define MTU2_TMDR_3_BFB                         (0x20u)
+
+#define MTU2_TMDR_4_BFA                         (0x10u)
+#define MTU2_TMDR_4_BFB                         (0x20u)
+
+#define MTU2_TIORH_3_IOA                        (0x0Fu)
+#define MTU2_TIORH_3_IOB                        (0xF0u)
+
+#define MTU2_TIORL_3_IOC                        (0x0Fu)
+#define MTU2_TIORL_3_IOD                        (0xF0u)
+
+#define MTU2_TIORH_4_IOA                        (0x0Fu)
+#define MTU2_TIORH_4_IOB                        (0xF0u)
+
+#define MTU2_TIORL_4_IOC                        (0x0Fu)
+#define MTU2_TIORL_4_IOD                        (0xF0u)
+
+#define MTU2_TIER_3_TGIEC                       (0x04u)
+#define MTU2_TIER_3_TGIED                       (0x08u)
+
+#define MTU2_TIER_4_TGIEC                       (0x04u)
+#define MTU2_TIER_4_TGIED                       (0x08u)
+#define MTU2_TIER_4_TTGE2                       (0x40u)
+
+#define MTU2_TOER_OE3B                          (0x01u)
+#define MTU2_TOER_OE4A                          (0x02u)
+#define MTU2_TOER_OE4B                          (0x04u)
+#define MTU2_TOER_OE3D                          (0x08u)
+#define MTU2_TOER_OE4C                          (0x10u)
+#define MTU2_TOER_OE4D                          (0x20u)
+
+#define MTU2_TGCR_UF                            (0x01u)
+#define MTU2_TGCR_VF                            (0x02u)
+#define MTU2_TGCR_WF                            (0x04u)
+#define MTU2_TGCR_FB                            (0x08u)
+#define MTU2_TGCR_P                             (0x10u)
+#define MTU2_TGCR_N                             (0x20u)
+#define MTU2_TGCR_BDC                           (0x40u)
+
+#define MTU2_TOCR1_OLSP                         (0x01u)
+#define MTU2_TOCR1_OLSN                         (0x02u)
+#define MTU2_TOCR1_TOCS                         (0x04u)
+#define MTU2_TOCR1_TOCL                         (0x08u)
+#define MTU2_TOCR1_PSYE                         (0x40u)
+
+#define MTU2_TOCR2_OLS1P                        (0x01u)
+#define MTU2_TOCR2_OLS1N                        (0x02u)
+#define MTU2_TOCR2_OLS2P                        (0x04u)
+#define MTU2_TOCR2_OLS2N                        (0x08u)
+#define MTU2_TOCR2_OLS3P                        (0x10u)
+#define MTU2_TOCR2_OLS3N                        (0x20u)
+#define MTU2_TOCR2_BF                           (0xC0u)
+
+#define MTU2_TCDR_D                             (0xFFFFu)
+
+#define MTU2_TDDR_D                             (0xFFFFu)
+
+#define MTU2_TCNTS_D                            (0xFFFFu)
+
+#define MTU2_TCBR_D                             (0xFFFFu)
+
+#define MTU2_TGRC_3_D                           (0xFFFFu)
+
+#define MTU2_TGRD_3_D                           (0xFFFFu)
+
+#define MTU2_TGRC_4_D                           (0xFFFFu)
+
+#define MTU2_TGRD_4_D                           (0xFFFFu)
+
+#define MTU2_TSR_3_TGFC                         (0x04u)
+#define MTU2_TSR_3_TGFD                         (0x08u)
+#define MTU2_TSR_3_TCFD                         (0x80u)
+
+#define MTU2_TSR_4_TGFC                         (0x04u)
+#define MTU2_TSR_4_TGFD                         (0x08u)
+#define MTU2_TSR_4_TCFD                         (0x80u)
+
+#define MTU2_TITCR_4VCOR                        (0x07u)
+#define MTU2_TITCR_T4VEN                        (0x08u)
+#define MTU2_TITCR_3ACOR                        (0x70u)
+#define MTU2_TITCR_T3AEN                        (0x80u)
+
+#define MTU2_TITCNT_4VCNT                       (0x07u)
+#define MTU2_TITCNT_3ACNT                       (0x70u)
+
+#define MTU2_TBTER_BTE                          (0x03u)
+
+#define MTU2_TDER_TDER                          (0x01u)
+
+#define MTU2_TOLBR_OLS1P                        (0x01u)
+#define MTU2_TOLBR_OLS1N                        (0x02u)
+#define MTU2_TOLBR_OLS2P                        (0x04u)
+#define MTU2_TOLBR_OLS2N                        (0x08u)
+#define MTU2_TOLBR_OLS3P                        (0x10u)
+#define MTU2_TOLBR_OLS3N                        (0x20u)
+
+#define MTU2_TBTM_3_TTSA                        (0x01u)
+#define MTU2_TBTM_3_TTSB                        (0x02u)
+
+#define MTU2_TBTM_4_TTSA                        (0x01u)
+#define MTU2_TBTM_4_TTSB                        (0x02u)
+
+#define MTU2_TADCR_ITB4VE                       (0x0001u)
+#define MTU2_TADCR_ITB3AE                       (0x0002u)
+#define MTU2_TADCR_ITA4VE                       (0x0004u)
+#define MTU2_TADCR_ITA3AE                       (0x0008u)
+#define MTU2_TADCR_DT4BE                        (0x0010u)
+#define MTU2_TADCR_UT4BE                        (0x0020u)
+#define MTU2_TADCR_DT4AE                        (0x0040u)
+#define MTU2_TADCR_UT4AE                        (0x0080u)
+#define MTU2_TADCR_BF                           (0xC000u)
+
+#define MTU2_TADCORA_4_D                        (0xFFFFu)
+
+#define MTU2_TADCORB_4_D                        (0xFFFFu)
+
+#define MTU2_TADCOBRA_4_D                       (0xFFFFu)
+
+#define MTU2_TADCOBRB_4_D                       (0xFFFFu)
+
+#define MTU2_TWCR_WRE                           (0x01u)
+#define MTU2_TWCR_CCE                           (0x80u)
+
+#define MTU2_TSTR_CST0                          (0x01u)
+#define MTU2_TSTR_CST1                          (0x02u)
+#define MTU2_TSTR_CST2                          (0x04u)
+#define MTU2_TSTR_CST3                          (0x40u)
+#define MTU2_TSTR_CST4                          (0x80u)
+
+#define MTU2_TSYR_SYNC0                         (0x01u)
+#define MTU2_TSYR_SYNC1                         (0x02u)
+#define MTU2_TSYR_SYNC2                         (0x04u)
+#define MTU2_TSYR_SYNC3                         (0x40u)
+#define MTU2_TSYR_SYNC4                         (0x80u)
+
+#define MTU2_TRWER_RWE                          (0x01u)
+
+#define MTU2_TMDR_0_BFA                         (0x10u)
+#define MTU2_TMDR_0_BFB                         (0x20u)
+#define MTU2_TMDR_0_BFE                         (0x40u)
+
+#define MTU2_TIORH_0_IOA                        (0x0Fu)
+#define MTU2_TIORH_0_IOB                        (0xF0u)
+
+#define MTU2_TIORL_0_IOC                        (0x0Fu)
+#define MTU2_TIORL_0_IOD                        (0xF0u)
+
+#define MTU2_TIER_0_TGIEC                       (0x04u)
+#define MTU2_TIER_0_TGIED                       (0x08u)
+
+#define MTU2_TSR_0_TGFC                         (0x04u)
+#define MTU2_TSR_0_TGFD                         (0x08u)
+
+#define MTU2_TGRC_0_D                           (0xFFFFu)
+
+#define MTU2_TGRD_0_D                           (0xFFFFu)
+
+#define MTU2_TGRE_0_D                           (0xFFFFu)
+
+#define MTU2_TGRF_0_D                           (0xFFFFu)
+
+#define MTU2_TIER2_0_TGIEE                      (0x01u)
+#define MTU2_TIER2_0_TGIEF                      (0x02u)
+
+#define MTU2_TSR2_0_TGFE                        (0x01u)
+#define MTU2_TSR2_0_TGFF                        (0x02u)
+
+#define MTU2_TBTM_0_TTSA                        (0x01u)
+#define MTU2_TBTM_0_TTSB                        (0x02u)
+#define MTU2_TBTM_0_TTSE                        (0x04u)
+
+#define MTU2_TIOR_1_IOA                         (0x0Fu)
+#define MTU2_TIOR_1_IOB                         (0xF0u)
+
+#define MTU2_TIER_1_TCIEU                       (0x20u)
+
+#define MTU2_TSR_1_TCFU                         (0x20u)
+#define MTU2_TSR_1_TCFD                         (0x80u)
+
+#define MTU2_TICCR_I1AE                         (0x01u)
+#define MTU2_TICCR_I1BE                         (0x02u)
+#define MTU2_TICCR_I2AE                         (0x04u)
+#define MTU2_TICCR_I2BE                         (0x08u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define MTU2_TCR_n_TPSC_SHIFT                   (0u)
+#define MTU2_TCR_n_CKEG_SHIFT                   (3u)
+#define MTU2_TCR_n_CCLR_SHIFT                   (5u)
+
+#define MTU2_TMDR_n_MD_SHIFT                    (0u)
+
+#define MTU2_TIOR_2_IOA_SHIFT                   (0u)
+#define MTU2_TIOR_2_IOB_SHIFT                   (4u)
+
+#define MTU2_TIER_n_TGIEA_SHIFT                 (0u)
+#define MTU2_TIER_n_TGIEB_SHIFT                 (1u)
+#define MTU2_TIER_n_TCIEV_SHIFT                 (4u)
+#define MTU2_TIER_2_TCIEU_SHIFT                 (5u)
+#define MTU2_TIER_n_TTGE_SHIFT                  (7u)
+
+#define MTU2_TSR_n_TGFA_SHIFT                   (0u)
+#define MTU2_TSR_n_TGFB_SHIFT                   (1u)
+#define MTU2_TSR_n_TCFV_SHIFT                   (4u)
+#define MTU2_TSR_2_TCFU_SHIFT                   (5u)
+#define MTU2_TSR_2_TCFD_SHIFT                   (7u)
+
+#define MTU2_TCNT_n_D_SHIFT                     (0u)
+
+#define MTU2_TGRA_n_D_SHIFT                     (0u)
+
+#define MTU2_TGRB_n_D_SHIFT                     (0u)
+
+#define MTU2_TMDR_3_BFA_SHIFT                   (4u)
+#define MTU2_TMDR_3_BFB_SHIFT                   (5u)
+
+#define MTU2_TMDR_4_BFA_SHIFT                   (4u)
+#define MTU2_TMDR_4_BFB_SHIFT                   (5u)
+
+#define MTU2_TIORH_3_IOA_SHIFT                  (0u)
+#define MTU2_TIORH_3_IOB_SHIFT                  (4u)
+
+#define MTU2_TIORL_3_IOC_SHIFT                  (0u)
+#define MTU2_TIORL_3_IOD_SHIFT                  (4u)
+
+#define MTU2_TIORH_4_IOA_SHIFT                  (0u)
+#define MTU2_TIORH_4_IOB_SHIFT                  (4u)
+
+#define MTU2_TIORL_4_IOC_SHIFT                  (0u)
+#define MTU2_TIORL_4_IOD_SHIFT                  (4u)
+
+#define MTU2_TIER_3_TGIEC_SHIFT                 (2u)
+#define MTU2_TIER_3_TGIED_SHIFT                 (3u)
+
+#define MTU2_TIER_4_TGIEC_SHIFT                 (2u)
+#define MTU2_TIER_4_TGIED_SHIFT                 (3u)
+#define MTU2_TIER_4_TTGE2_SHIFT                 (6u)
+
+#define MTU2_TOER_OE3B_SHIFT                    (0u)
+#define MTU2_TOER_OE4A_SHIFT                    (1u)
+#define MTU2_TOER_OE4B_SHIFT                    (2u)
+#define MTU2_TOER_OE3D_SHIFT                    (3u)
+#define MTU2_TOER_OE4C_SHIFT                    (4u)
+#define MTU2_TOER_OE4D_SHIFT                    (5u)
+
+#define MTU2_TGCR_UF_SHIFT                      (0u)
+#define MTU2_TGCR_VF_SHIFT                      (1u)
+#define MTU2_TGCR_WF_SHIFT                      (2u)
+#define MTU2_TGCR_FB_SHIFT                      (3u)
+#define MTU2_TGCR_P_SHIFT                       (4u)
+#define MTU2_TGCR_N_SHIFT                       (5u)
+#define MTU2_TGCR_BDC_SHIFT                     (6u)
+
+#define MTU2_TOCR1_OLSP_SHIFT                   (0u)
+#define MTU2_TOCR1_OLSN_SHIFT                   (1u)
+#define MTU2_TOCR1_TOCS_SHIFT                   (2u)
+#define MTU2_TOCR1_TOCL_SHIFT                   (3u)
+#define MTU2_TOCR1_PSYE_SHIFT                   (6u)
+
+#define MTU2_TOCR2_OLS1P_SHIFT                  (0u)
+#define MTU2_TOCR2_OLS1N_SHIFT                  (1u)
+#define MTU2_TOCR2_OLS2P_SHIFT                  (2u)
+#define MTU2_TOCR2_OLS2N_SHIFT                  (3u)
+#define MTU2_TOCR2_OLS3P_SHIFT                  (4u)
+#define MTU2_TOCR2_OLS3N_SHIFT                  (5u)
+#define MTU2_TOCR2_BF_SHIFT                     (6u)
+
+#define MTU2_TCDR_D_SHIFT                       (0u)
+
+#define MTU2_TDDR_D_SHIFT                       (0u)
+
+#define MTU2_TCNTS_D_SHIFT                      (0u)
+
+#define MTU2_TCBR_D_SHIFT                       (0u)
+
+#define MTU2_TGRC_3_D_SHIFT                     (0u)
+
+#define MTU2_TGRD_3_D_SHIFT                     (0u)
+
+#define MTU2_TGRC_4_D_SHIFT                     (0u)
+
+#define MTU2_TGRD_4_D_SHIFT                     (0u)
+
+#define MTU2_TSR_3_TGFC_SHIFT                   (2u)
+#define MTU2_TSR_3_TGFD_SHIFT                   (3u)
+#define MTU2_TSR_3_TCFD_SHIFT                   (7u)
+
+#define MTU2_TSR_4_TGFC_SHIFT                   (2u)
+#define MTU2_TSR_4_TGFD_SHIFT                   (3u)
+#define MTU2_TSR_4_TCFD_SHIFT                   (7u)
+
+#define MTU2_TITCR_4VCOR_SHIFT                  (0u)
+#define MTU2_TITCR_T4VEN_SHIFT                  (3u)
+#define MTU2_TITCR_3ACOR_SHIFT                  (4u)
+#define MTU2_TITCR_T3AEN_SHIFT                  (7u)
+
+#define MTU2_TITCNT_4VCNT_SHIFT                 (0u)
+#define MTU2_TITCNT_3ACNT_SHIFT                 (4u)
+
+#define MTU2_TBTER_BTE_SHIFT                    (0u)
+
+#define MTU2_TDER_TDER_SHIFT                    (0u)
+
+#define MTU2_TOLBR_OLS1P_SHIFT                  (0u)
+#define MTU2_TOLBR_OLS1N_SHIFT                  (1u)
+#define MTU2_TOLBR_OLS2P_SHIFT                  (2u)
+#define MTU2_TOLBR_OLS2N_SHIFT                  (3u)
+#define MTU2_TOLBR_OLS3P_SHIFT                  (4u)
+#define MTU2_TOLBR_OLS3N_SHIFT                  (5u)
+
+#define MTU2_TBTM_3_TTSA_SHIFT                  (0u)
+#define MTU2_TBTM_3_TTSB_SHIFT                  (1u)
+
+#define MTU2_TBTM_4_TTSA_SHIFT                  (0u)
+#define MTU2_TBTM_4_TTSB_SHIFT                  (1u)
+
+#define MTU2_TADCR_ITB4VE_SHIFT                 (0u)
+#define MTU2_TADCR_ITB3AE_SHIFT                 (1u)
+#define MTU2_TADCR_ITA4VE_SHIFT                 (2u)
+#define MTU2_TADCR_ITA3AE_SHIFT                 (3u)
+#define MTU2_TADCR_DT4BE_SHIFT                  (4u)
+#define MTU2_TADCR_UT4BE_SHIFT                  (5u)
+#define MTU2_TADCR_DT4AE_SHIFT                  (6u)
+#define MTU2_TADCR_UT4AE_SHIFT                  (7u)
+#define MTU2_TADCR_BF_SHIFT                     (14u)
+
+#define MTU2_TADCORA_4_D_SHIFT                  (0u)
+
+#define MTU2_TADCORB_4_D_SHIFT                  (0u)
+
+#define MTU2_TADCOBRA_4_D_SHIFT                 (0u)
+
+#define MTU2_TADCOBRB_4_D_SHIFT                 (0u)
+
+#define MTU2_TWCR_WRE_SHIFT                     (0u)
+#define MTU2_TWCR_CCE_SHIFT                     (7u)
+
+#define MTU2_TSTR_CST0_SHIFT                    (0u)
+#define MTU2_TSTR_CST1_SHIFT                    (1u)
+#define MTU2_TSTR_CST2_SHIFT                    (2u)
+#define MTU2_TSTR_CST3_SHIFT                    (6u)
+#define MTU2_TSTR_CST4_SHIFT                    (7u)
+
+#define MTU2_TSYR_SYNC0_SHIFT                   (0u)
+#define MTU2_TSYR_SYNC1_SHIFT                   (1u)
+#define MTU2_TSYR_SYNC2_SHIFT                   (2u)
+#define MTU2_TSYR_SYNC3_SHIFT                   (6u)
+#define MTU2_TSYR_SYNC4_SHIFT                   (7u)
+
+#define MTU2_TRWER_RWE_SHIFT                    (0u)
+
+#define MTU2_TMDR_0_BFA_SHIFT                   (4u)
+#define MTU2_TMDR_0_BFB_SHIFT                   (5u)
+#define MTU2_TMDR_0_BFE_SHIFT                   (6u)
+
+#define MTU2_TIORH_0_IOA_SHIFT                  (0u)
+#define MTU2_TIORH_0_IOB_SHIFT                  (4u)
+
+#define MTU2_TIORL_0_IOC_SHIFT                  (0u)
+#define MTU2_TIORL_0_IOD_SHIFT                  (4u)
+
+#define MTU2_TIER_0_TGIEC_SHIFT                 (2u)
+#define MTU2_TIER_0_TGIED_SHIFT                 (3u)
+
+#define MTU2_TSR_0_TGFC_SHIFT                   (2u)
+#define MTU2_TSR_0_TGFD_SHIFT                   (3u)
+
+#define MTU2_TGRC_0_D_SHIFT                     (0u)
+
+#define MTU2_TGRD_0_D_SHIFT                     (0u)
+
+#define MTU2_TGRE_0_D_SHIFT                     (0u)
+
+#define MTU2_TGRF_0_D_SHIFT                     (0u)
+
+#define MTU2_TIER2_0_TGIEE_SHIFT                (0u)
+#define MTU2_TIER2_0_TGIEF_SHIFT                (1u)
+
+#define MTU2_TSR2_0_TGFE_SHIFT                  (0u)
+#define MTU2_TSR2_0_TGFF_SHIFT                  (1u)
+
+#define MTU2_TBTM_0_TTSA_SHIFT                  (0u)
+#define MTU2_TBTM_0_TTSB_SHIFT                  (1u)
+#define MTU2_TBTM_0_TTSE_SHIFT                  (2u)
+
+#define MTU2_TIOR_1_IOA_SHIFT                   (0u)
+#define MTU2_TIOR_1_IOB_SHIFT                   (4u)
+
+#define MTU2_TIER_1_TCIEU_SHIFT                 (5u)
+
+#define MTU2_TSR_1_TCFU_SHIFT                   (5u)
+#define MTU2_TSR_1_TCFD_SHIFT                   (7u)
+
+#define MTU2_TICCR_I1AE_SHIFT                   (0u)
+#define MTU2_TICCR_I1BE_SHIFT                   (1u)
+#define MTU2_TICCR_I2AE_SHIFT                   (2u)
+#define MTU2_TICCR_I2BE_SHIFT                   (3u)
+
+
+#endif /* MTU2_IOBITMASK_H */
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h	(revision 374)
@@ -0,0 +1,123 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : ostm_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : OSTM register define header
+*******************************************************************************/
+#ifndef OSTM_IOBITMASK_H
+#define OSTM_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- OSTM0 ---- */
+#define OSTM0_OSTMnCMP_OSTMnCMP                 (0xFFFFFFFFuL)
+
+#define OSTM0_OSTMnCNT_OSTMnCNT                 (0xFFFFFFFFuL)
+
+#define OSTM0_OSTMnTE_OSTMnTE                   (0x01u)
+
+#define OSTM0_OSTMnTS_OSTMnTS                   (0x01u)
+
+#define OSTM0_OSTMnTT_OSTMnTT                   (0x01u)
+
+#define OSTM0_OSTMnCTL_MD0                      (0x00000001uL)
+#define OSTM0_OSTMnCTL_MD1                      (0x00000002uL)
+
+/* ---- OSTM1 ---- */
+#define OSTM1_OSTMnCMP_OSTMnCMP                 (0xFFFFFFFFuL)
+
+#define OSTM1_OSTMnCNT_OSTMnCNT                 (0xFFFFFFFFuL)
+
+#define OSTM1_OSTMnTE_OSTMnTE                   (0x01u)
+
+#define OSTM1_OSTMnTS_OSTMnTS                   (0x01u)
+
+#define OSTM1_OSTMnTT_OSTMnTT                   (0x01u)
+
+#define OSTM1_OSTMnCTL_MD0                      (0x00000001uL)
+#define OSTM1_OSTMnCTL_MD1                      (0x00000002uL)
+
+/* ---- OSTMn ---- */
+#define OSTMn_OSTMnCMP_OSTMnCMP                 (0xFFFFFFFFuL)
+
+#define OSTMn_OSTMnCNT_OSTMnCNT                 (0xFFFFFFFFuL)
+
+#define OSTMn_OSTMnTE_OSTMnTE                   (0x01u)
+
+#define OSTMn_OSTMnTS_OSTMnTS                   (0x01u)
+
+#define OSTMn_OSTMnTT_OSTMnTT                   (0x01u)
+
+#define OSTMn_OSTMnCTL_MD0                      (0x00000001uL)
+#define OSTMn_OSTMnCTL_MD1                      (0x00000002uL)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- OSTM0 ---- */
+#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT           (0u)
+
+#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT           (0u)
+
+#define OSTM0_OSTMnTE_OSTMnTE_SHIFT             (0u)
+
+#define OSTM0_OSTMnTS_OSTMnTS_SHIFT             (0u)
+
+#define OSTM0_OSTMnTT_OSTMnTT_SHIFT             (0u)
+
+#define OSTM0_OSTMnCTL_MD0_SHIFT                (0u)
+#define OSTM0_OSTMnCTL_MD1_SHIFT                (1u)
+
+/* ---- OSTM1 ---- */
+#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT           (0u)
+
+#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT           (0u)
+
+#define OSTM1_OSTMnTE_OSTMnTE_SHIFT             (0u)
+
+#define OSTM1_OSTMnTS_OSTMnTS_SHIFT             (0u)
+
+#define OSTM1_OSTMnTT_OSTMnTT_SHIFT             (0u)
+
+#define OSTM1_OSTMnCTL_MD0_SHIFT                (0u)
+#define OSTM1_OSTMnCTL_MD1_SHIFT                (1u)
+
+/* ---- OSTMn ---- */
+#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT           (0u)
+
+#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT           (0u)
+
+#define OSTMn_OSTMnTE_OSTMnTE_SHIFT             (0u)
+
+#define OSTMn_OSTMnTS_OSTMnTS_SHIFT             (0u)
+
+#define OSTMn_OSTMnTT_OSTMnTT_SHIFT             (0u)
+
+#define OSTMn_OSTMnCTL_MD0_SHIFT                (0u)
+#define OSTMn_OSTMnCTL_MD1_SHIFT                (1u)
+
+
+#endif /* OSTM_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h	(revision 374)
@@ -0,0 +1,231 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : riic_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : RIIC register define header
+*******************************************************************************/
+#ifndef RIIC_IOBITMASK_H
+#define RIIC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define RIICn_RIICnCR1_SDAI                     (0x01u)
+#define RIICn_RIICnCR1_SCLI                     (0x02u)
+#define RIICn_RIICnCR1_SDAO                     (0x04u)
+#define RIICn_RIICnCR1_SCLO                     (0x08u)
+#define RIICn_RIICnCR1_SOWP                     (0x10u)
+#define RIICn_RIICnCR1_CLO                      (0x20u)
+#define RIICn_RIICnCR1_IICRST                   (0x40u)
+#define RIICn_RIICnCR1_ICE                      (0x80u)
+
+#define RIICn_RIICnCR2_ST                       (0x02u)
+#define RIICn_RIICnCR2_RS                       (0x04u)
+#define RIICn_RIICnCR2_SP                       (0x08u)
+#define RIICn_RIICnCR2_TRS                      (0x20u)
+#define RIICn_RIICnCR2_MST                      (0x40u)
+#define RIICn_RIICnCR2_BBSY                     (0x80u)
+
+#define RIICn_RIICnMR1_BC                       (0x07u)
+#define RIICn_RIICnMR1_BCWP                     (0x08u)
+#define RIICn_RIICnMR1_CKS                      (0x70u)
+#define RIICn_RIICnMR1_MTWP                     (0x80u)
+
+#define RIICn_RIICnMR2_TMOS                     (0x01u)
+#define RIICn_RIICnMR2_TMOL                     (0x02u)
+#define RIICn_RIICnMR2_TMOH                     (0x04u)
+#define RIICn_RIICnMR2_SDDL                     (0x70u)
+#define RIICn_RIICnMR2_DLCS                     (0x80u)
+
+#define RIICn_RIICnMR3_NF                       (0x03u)
+#define RIICn_RIICnMR3_ACKBR                    (0x04u)
+#define RIICn_RIICnMR3_ACKBT                    (0x08u)
+#define RIICn_RIICnMR3_ACKWP                    (0x10u)
+#define RIICn_RIICnMR3_RDRFS                    (0x20u)
+#define RIICn_RIICnMR3_WAIT                     (0x40u)
+#define RIICn_RIICnMR3_SMBS                     (0x80u)
+
+#define RIICn_RIICnFER_TMOE                     (0x01u)
+#define RIICn_RIICnFER_MALE                     (0x02u)
+#define RIICn_RIICnFER_NALE                     (0x04u)
+#define RIICn_RIICnFER_SALE                     (0x08u)
+#define RIICn_RIICnFER_NACKE                    (0x10u)
+#define RIICn_RIICnFER_NFE                      (0x20u)
+#define RIICn_RIICnFER_SCLE                     (0x40u)
+#define RIICn_RIICnFER_FMPE                     (0x80u)
+
+#define RIICn_RIICnSER_SAR0E                    (0x01u)
+#define RIICn_RIICnSER_SAR1E                    (0x02u)
+#define RIICn_RIICnSER_SAR2E                    (0x04u)
+#define RIICn_RIICnSER_GCAE                     (0x08u)
+#define RIICn_RIICnSER_DIDE                     (0x20u)
+#define RIICn_RIICnSER_HOAE                     (0x80u)
+
+#define RIICn_RIICnIER_TMOIE                    (0x01u)
+#define RIICn_RIICnIER_ALIE                     (0x02u)
+#define RIICn_RIICnIER_STIE                     (0x04u)
+#define RIICn_RIICnIER_SPIE                     (0x08u)
+#define RIICn_RIICnIER_NAKIE                    (0x10u)
+#define RIICn_RIICnIER_RIE                      (0x20u)
+#define RIICn_RIICnIER_TEIE                     (0x40u)
+#define RIICn_RIICnIER_TIE                      (0x80u)
+
+#define RIICn_RIICnSR1_AAS0                     (0x01u)
+#define RIICn_RIICnSR1_AAS1                     (0x02u)
+#define RIICn_RIICnSR1_AAS2                     (0x04u)
+#define RIICn_RIICnSR1_GCA                      (0x08u)
+#define RIICn_RIICnSR1_DID                      (0x20u)
+#define RIICn_RIICnSR1_HOA                      (0x80u)
+
+#define RIICn_RIICnSR2_TMOF                     (0x01u)
+#define RIICn_RIICnSR2_AL                       (0x02u)
+#define RIICn_RIICnSR2_START                    (0x04u)
+#define RIICn_RIICnSR2_STOP                     (0x08u)
+#define RIICn_RIICnSR2_NACKF                    (0x10u)
+#define RIICn_RIICnSR2_RDRF                     (0x20u)
+#define RIICn_RIICnSR2_TEND                     (0x40u)
+#define RIICn_RIICnSR2_TDRE                     (0x80u)
+
+#define RIICn_RIICnSAR0_SVA0                    (0x0001u)
+#define RIICn_RIICnSAR0_SVA                     (0x03FEu)
+#define RIICn_RIICnSAR0_FSy                     (0x8000u)
+
+#define RIICn_RIICnSAR1_SVA0                    (0x0001u)
+#define RIICn_RIICnSAR1_SVA                     (0x03FEu)
+#define RIICn_RIICnSAR1_FSy                     (0x8000u)
+
+#define RIICn_RIICnSAR2_SVA0                    (0x0001u)
+#define RIICn_RIICnSAR2_SVA                     (0x03FEu)
+#define RIICn_RIICnSAR2_FSy                     (0x8000u)
+
+#define RIICn_RIICnBRL_BRL                      (0x1Fu)
+
+#define RIICn_RIICnBRH_BRH                      (0x1Fu)
+
+#define RIICn_RIICnDRT_DRT                      (0xFFu)
+
+#define RIICn_RIICnDRR_DRR                      (0xFFu)
+
+
+/* ==== Shift values for IO registers ==== */
+#define RIICn_RIICnCR1_SDAI_SHIFT               (0u)
+#define RIICn_RIICnCR1_SCLI_SHIFT               (1u)
+#define RIICn_RIICnCR1_SDAO_SHIFT               (2u)
+#define RIICn_RIICnCR1_SCLO_SHIFT               (3u)
+#define RIICn_RIICnCR1_SOWP_SHIFT               (4u)
+#define RIICn_RIICnCR1_CLO_SHIFT                (5u)
+#define RIICn_RIICnCR1_IICRST_SHIFT             (6u)
+#define RIICn_RIICnCR1_ICE_SHIFT                (7u)
+
+#define RIICn_RIICnCR2_ST_SHIFT                 (1u)
+#define RIICn_RIICnCR2_RS_SHIFT                 (2u)
+#define RIICn_RIICnCR2_SP_SHIFT                 (3u)
+#define RIICn_RIICnCR2_TRS_SHIFT                (5u)
+#define RIICn_RIICnCR2_MST_SHIFT                (6u)
+#define RIICn_RIICnCR2_BBSY_SHIFT               (7u)
+
+#define RIICn_RIICnMR1_BC_SHIFT                 (0u)
+#define RIICn_RIICnMR1_BCWP_SHIFT               (3u)
+#define RIICn_RIICnMR1_CKS_SHIFT                (4u)
+#define RIICn_RIICnMR1_MTWP_SHIFT               (7u)
+
+#define RIICn_RIICnMR2_TMOS_SHIFT               (0u)
+#define RIICn_RIICnMR2_TMOL_SHIFT               (1u)
+#define RIICn_RIICnMR2_TMOH_SHIFT               (2u)
+#define RIICn_RIICnMR2_SDDL_SHIFT               (4u)
+#define RIICn_RIICnMR2_DLCS_SHIFT               (7u)
+
+#define RIICn_RIICnMR3_NF_SHIFT                 (0u)
+#define RIICn_RIICnMR3_ACKBR_SHIFT              (2u)
+#define RIICn_RIICnMR3_ACKBT_SHIFT              (3u)
+#define RIICn_RIICnMR3_ACKWP_SHIFT              (4u)
+#define RIICn_RIICnMR3_RDRFS_SHIFT              (5u)
+#define RIICn_RIICnMR3_WAIT_SHIFT               (6u)
+#define RIICn_RIICnMR3_SMBS_SHIFT               (7u)
+
+#define RIICn_RIICnFER_TMOE_SHIFT               (0u)
+#define RIICn_RIICnFER_MALE_SHIFT               (1u)
+#define RIICn_RIICnFER_NALE_SHIFT               (2u)
+#define RIICn_RIICnFER_SALE_SHIFT               (3u)
+#define RIICn_RIICnFER_NACKE_SHIFT              (4u)
+#define RIICn_RIICnFER_NFE_SHIFT                (5u)
+#define RIICn_RIICnFER_SCLE_SHIFT               (6u)
+#define RIICn_RIICnFER_FMPE_SHIFT               (7u)
+
+#define RIICn_RIICnSER_SAR0E_SHIFT              (0u)
+#define RIICn_RIICnSER_SAR1E_SHIFT              (1u)
+#define RIICn_RIICnSER_SAR2E_SHIFT              (2u)
+#define RIICn_RIICnSER_GCAE_SHIFT               (3u)
+#define RIICn_RIICnSER_DIDE_SHIFT               (5u)
+#define RIICn_RIICnSER_HOAE_SHIFT               (7u)
+
+#define RIICn_RIICnIER_TMOIE_SHIFT              (0u)
+#define RIICn_RIICnIER_ALIE_SHIFT               (1u)
+#define RIICn_RIICnIER_STIE_SHIFT               (2u)
+#define RIICn_RIICnIER_SPIE_SHIFT               (3u)
+#define RIICn_RIICnIER_NAKIE_SHIFT              (4u)
+#define RIICn_RIICnIER_RIE_SHIFT                (5u)
+#define RIICn_RIICnIER_TEIE_SHIFT               (6u)
+#define RIICn_RIICnIER_TIE_SHIFT                (7u)
+
+#define RIICn_RIICnSR1_AAS0_SHIFT               (0u)
+#define RIICn_RIICnSR1_AAS1_SHIFT               (1u)
+#define RIICn_RIICnSR1_AAS2_SHIFT               (2u)
+#define RIICn_RIICnSR1_GCA_SHIFT                (3u)
+#define RIICn_RIICnSR1_DID_SHIFT                (5u)
+#define RIICn_RIICnSR1_HOA_SHIFT                (7u)
+
+#define RIICn_RIICnSR2_TMOF_SHIFT               (0u)
+#define RIICn_RIICnSR2_AL_SHIFT                 (1u)
+#define RIICn_RIICnSR2_START_SHIFT              (2u)
+#define RIICn_RIICnSR2_STOP_SHIFT               (3u)
+#define RIICn_RIICnSR2_NACKF_SHIFT              (4u)
+#define RIICn_RIICnSR2_RDRF_SHIFT               (5u)
+#define RIICn_RIICnSR2_TEND_SHIFT               (6u)
+#define RIICn_RIICnSR2_TDRE_SHIFT               (7u)
+
+#define RIICn_RIICnSAR0_SVA0_SHIFT              (0u)
+#define RIICn_RIICnSAR0_SVA_SHIFT               (1u)
+#define RIICn_RIICnSAR0_FSy_SHIFT               (15u)
+
+#define RIICn_RIICnSAR1_SVA0_SHIFT              (0u)
+#define RIICn_RIICnSAR1_SVA_SHIFT               (1u)
+#define RIICn_RIICnSAR1_FSy_SHIFT               (15u)
+
+#define RIICn_RIICnSAR2_SVA0_SHIFT              (0u)
+#define RIICn_RIICnSAR2_SVA_SHIFT               (1u)
+#define RIICn_RIICnSAR2_FSy_SHIFT               (15u)
+
+#define RIICn_RIICnBRL_BRL_SHIFT                (0u)
+
+#define RIICn_RIICnBRH_BRH_SHIFT                (0u)
+
+#define RIICn_RIICnDRT_DRT_SHIFT                (0u)
+
+#define RIICn_RIICnDRR_DRR_SHIFT                (0u)
+
+
+#endif /* RIIC_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h	(revision 374)
@@ -0,0 +1,215 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : rspi_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : Renesas Serial Peripheral Interface register define header
+*******************************************************************************/
+#ifndef RSPI_IOBITMASK_H
+#define RSPI_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define RSPIn_SPCR_MODFEN                   (0x04u)
+#define RSPIn_SPCR_MSTR                     (0x08u)
+#define RSPIn_SPCR_SPEIE                    (0x10u)
+#define RSPIn_SPCR_SPTIE                    (0x20u)
+#define RSPIn_SPCR_SPE                      (0x40u)
+#define RSPIn_SPCR_SPRIE                    (0x80u)
+
+#define RSPIn_SSLP_SSL0P                    (0x01u)
+
+#define RSPIn_SPPCR_SPLP                    (0x01u)
+#define RSPIn_SPPCR_MOIFV                   (0x10u)
+#define RSPIn_SPPCR_MOIFE                   (0x20u)
+
+#define RSPIn_SPSR_OVRF                     (0x01u)
+#define RSPIn_SPSR_MODF                     (0x04u)
+#define RSPIn_SPSR_SPTEF                    (0x20u)
+#define RSPIn_SPSR_TEND                     (0x40u)
+#define RSPIn_SPSR_SPRF                     (0x80u)
+
+#define RSPIn_SPDR_UINT32                   (0xFFFFFFFFuL)
+
+#define RSPIn_SPDR_UINT16                   (0xFFFFu)
+
+#define RSPIn_SPDR_UINT8                    (0xFFu)
+
+#define RSPIn_SPSCR_SPSLN                   (0x03u)
+
+#define RSPIn_SPSSR_SPCP                    (0x03u)
+
+#define RSPIn_SPBR_SPR                      (0xFFu)
+
+#define RSPIn_SPDCR_SPLW                    (0x60u)
+#define RSPIn_SPDCR_TXDMY                   (0x80u)
+
+#define RSPIn_SPCKD_SCKDL                   (0x07u)
+
+#define RSPIn_SSLND_SLNDL                   (0x07u)
+
+#define RSPIn_SPND_SPNDL                    (0x07u)
+
+#define RSPIn_SPCMD0_CPHA                   (0x0001u)
+#define RSPIn_SPCMD0_CPOL                   (0x0002u)
+#define RSPIn_SPCMD0_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD0_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD0_SPB                    (0x0F00u)
+#define RSPIn_SPCMD0_LSBF                   (0x1000u)
+#define RSPIn_SPCMD0_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD0_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD0_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPCMD1_CPHA                   (0x0001u)
+#define RSPIn_SPCMD1_CPOL                   (0x0002u)
+#define RSPIn_SPCMD1_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD1_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD1_SPB                    (0x0F00u)
+#define RSPIn_SPCMD1_LSBF                   (0x1000u)
+#define RSPIn_SPCMD1_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD1_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD1_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPCMD2_CPHA                   (0x0001u)
+#define RSPIn_SPCMD2_CPOL                   (0x0002u)
+#define RSPIn_SPCMD2_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD2_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD2_SPB                    (0x0F00u)
+#define RSPIn_SPCMD2_LSBF                   (0x1000u)
+#define RSPIn_SPCMD2_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD2_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD2_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPCMD3_CPHA                   (0x0001u)
+#define RSPIn_SPCMD3_CPOL                   (0x0002u)
+#define RSPIn_SPCMD3_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD3_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD3_SPB                    (0x0F00u)
+#define RSPIn_SPCMD3_LSBF                   (0x1000u)
+#define RSPIn_SPCMD3_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD3_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD3_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPBFCR_RXTRG                  (0x07u)
+#define RSPIn_SPBFCR_TXTRG                  (0x30u)
+#define RSPIn_SPBFCR_RXRST                  (0x40u)
+#define RSPIn_SPBFCR_TXRST                  (0x80u)
+
+#define RSPIn_SPBFDR_R                      (0x003Fu)
+#define RSPIn_SPBFDR_T                      (0x0F00u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define RSPIn_SPCR_MODFEN_SHIFT             (2u)
+#define RSPIn_SPCR_MSTR_SHIFT               (3u)
+#define RSPIn_SPCR_SPEIE_SHIFT              (4u)
+#define RSPIn_SPCR_SPTIE_SHIFT              (5u)
+#define RSPIn_SPCR_SPE_SHIFT                (6u)
+#define RSPIn_SPCR_SPRIE_SHIFT              (7u)
+
+#define RSPIn_SSLP_SSL0P_SHIFT              (0u)
+
+#define RSPIn_SPPCR_SPLP_SHIFT              (0u)
+#define RSPIn_SPPCR_MOIFV_SHIFT             (4u)
+#define RSPIn_SPPCR_MOIFE_SHIFT             (5u)
+
+#define RSPIn_SPSR_OVRF_SHIFT               (0u)
+#define RSPIn_SPSR_MODF_SHIFT               (2u)
+#define RSPIn_SPSR_SPTEF_SHIFT              (5u)
+#define RSPIn_SPSR_TEND_SHIFT               (6u)
+#define RSPIn_SPSR_SPRF_SHIFT               (7u)
+
+#define RSPIn_SPDR_UINT32_SHIFT             (0u)
+
+#define RSPIn_SPDR_UINT16_SHIFT             (0u)
+
+#define RSPIn_SPDR_UINT8_SHIFT              (0u)
+
+#define RSPIn_SPSCR_SPSLN_SHIFT             (0u)
+
+#define RSPIn_SPSSR_SPCP_SHIFT              (0u)
+
+#define RSPIn_SPBR_SPR_SHIFT                (0u)
+
+#define RSPIn_SPDCR_SPLW_SHIFT              (5u)
+#define RSPIn_SPDCR_TXDMY_SHIFT             (7u)
+
+#define RSPIn_SPCKD_SCKDL_SHIFT             (0u)
+
+#define RSPIn_SSLND_SLNDL_SHIFT             (0u)
+
+#define RSPIn_SPND_SPNDL_SHIFT              (0u)
+
+#define RSPIn_SPCMD0_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD0_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD0_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD0_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD0_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD0_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD0_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD0_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD0_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPCMD1_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD1_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD1_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD1_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD1_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD1_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD1_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD1_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD1_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPCMD2_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD2_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD2_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD2_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD2_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD2_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD2_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD2_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD2_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPCMD3_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD3_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD3_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD3_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD3_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD3_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD3_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD3_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD3_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPBFCR_RXTRG_SHIFT            (0u)
+#define RSPIn_SPBFCR_TXTRG_SHIFT            (4u)
+#define RSPIn_SPBFCR_RXRST_SHIFT            (6u)
+#define RSPIn_SPBFCR_TXRST_SHIFT            (7u)
+
+#define RSPIn_SPBFDR_R_SHIFT                (0u)
+#define RSPIn_SPBFDR_T_SHIFT                (8u)
+
+
+#endif /* RSPI_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h	(revision 374)
@@ -0,0 +1,1065 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : scif_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : SCIF register define header
+*******************************************************************************/
+#ifndef SCIF_IOBITMASK_H
+#define SCIF_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- SCIF0 ---- */
+#define SCIF0_SCSMR_CKS                         (0x0003u)
+#define SCIF0_SCSMR_STOP                        (0x0008u)
+#define SCIF0_SCSMR_OE                          (0x0010u)
+#define SCIF0_SCSMR_PE                          (0x0020u)
+#define SCIF0_SCSMR_CHR                         (0x0040u)
+#define SCIF0_SCSMR_CA                          (0x0080u)
+
+#define SCIF0_SCBRR_D                           (0xFFu)
+
+#define SCIF0_SCSCR_CKE                         (0x0003u)
+#define SCIF0_SCSCR_REIE                        (0x0008u)
+#define SCIF0_SCSCR_RE                          (0x0010u)
+#define SCIF0_SCSCR_TE                          (0x0020u)
+#define SCIF0_SCSCR_RIE                         (0x0040u)
+#define SCIF0_SCSCR_TIE                         (0x0080u)
+
+#define SCIF0_SCFTDR_D                          (0xFFu)
+
+#define SCIF0_SCFSR_DR                          (0x0001u)
+#define SCIF0_SCFSR_RDF                         (0x0002u)
+#define SCIF0_SCFSR_PER                         (0x0004u)
+#define SCIF0_SCFSR_FER                         (0x0008u)
+#define SCIF0_SCFSR_BRK                         (0x0010u)
+#define SCIF0_SCFSR_TDFE                        (0x0020u)
+#define SCIF0_SCFSR_TEND                        (0x0040u)
+#define SCIF0_SCFSR_ER                          (0x0080u)
+#define SCIF0_SCFSR_FERN                        (0x0F00u)
+#define SCIF0_SCFSR_PERN                        (0xF000u)
+
+#define SCIF0_SCFRDR_D                          (0xFFu)
+
+#define SCIF0_SCFCR_LOOP                        (0x0001u)
+#define SCIF0_SCFCR_RFRST                       (0x0002u)
+#define SCIF0_SCFCR_TFRST                       (0x0004u)
+#define SCIF0_SCFCR_MCE                         (0x0008u)
+#define SCIF0_SCFCR_TTRG                        (0x0030u)
+#define SCIF0_SCFCR_RTRG                        (0x00C0u)
+#define SCIF0_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF0_SCFDR_R                           (0x001Fu)
+#define SCIF0_SCFDR_T                           (0x1F00u)
+
+#define SCIF0_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF0_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF0_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF0_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF0_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF0_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF0_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF0_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF0_SCLSR_ORER                        (0x0001u)
+
+#define SCIF0_SCEMR_ABCS                        (0x0001u)
+#define SCIF0_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF1 ---- */
+#define SCIF1_SCSMR_CKS                         (0x0003u)
+#define SCIF1_SCSMR_STOP                        (0x0008u)
+#define SCIF1_SCSMR_OE                          (0x0010u)
+#define SCIF1_SCSMR_PE                          (0x0020u)
+#define SCIF1_SCSMR_CHR                         (0x0040u)
+#define SCIF1_SCSMR_CA                          (0x0080u)
+
+#define SCIF1_SCBRR_D                           (0xFFu)
+
+#define SCIF1_SCSCR_CKE                         (0x0003u)
+#define SCIF1_SCSCR_REIE                        (0x0008u)
+#define SCIF1_SCSCR_RE                          (0x0010u)
+#define SCIF1_SCSCR_TE                          (0x0020u)
+#define SCIF1_SCSCR_RIE                         (0x0040u)
+#define SCIF1_SCSCR_TIE                         (0x0080u)
+
+#define SCIF1_SCFTDR_D                          (0xFFu)
+
+#define SCIF1_SCFSR_DR                          (0x0001u)
+#define SCIF1_SCFSR_RDF                         (0x0002u)
+#define SCIF1_SCFSR_PER                         (0x0004u)
+#define SCIF1_SCFSR_FER                         (0x0008u)
+#define SCIF1_SCFSR_BRK                         (0x0010u)
+#define SCIF1_SCFSR_TDFE                        (0x0020u)
+#define SCIF1_SCFSR_TEND                        (0x0040u)
+#define SCIF1_SCFSR_ER                          (0x0080u)
+#define SCIF1_SCFSR_FERN                        (0x0F00u)
+#define SCIF1_SCFSR_PERN                        (0xF000u)
+
+#define SCIF1_SCFRDR_D                          (0xFFu)
+
+#define SCIF1_SCFCR_LOOP                        (0x0001u)
+#define SCIF1_SCFCR_RFRST                       (0x0002u)
+#define SCIF1_SCFCR_TFRST                       (0x0004u)
+#define SCIF1_SCFCR_MCE                         (0x0008u)
+#define SCIF1_SCFCR_TTRG                        (0x0030u)
+#define SCIF1_SCFCR_RTRG                        (0x00C0u)
+#define SCIF1_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF1_SCFDR_R                           (0x001Fu)
+#define SCIF1_SCFDR_T                           (0x1F00u)
+
+#define SCIF1_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF1_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF1_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF1_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF1_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF1_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF1_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF1_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF1_SCLSR_ORER                        (0x0001u)
+
+#define SCIF1_SCEMR_ABCS                        (0x0001u)
+#define SCIF1_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF2 ---- */
+#define SCIF2_SCSMR_CKS                         (0x0003u)
+#define SCIF2_SCSMR_STOP                        (0x0008u)
+#define SCIF2_SCSMR_OE                          (0x0010u)
+#define SCIF2_SCSMR_PE                          (0x0020u)
+#define SCIF2_SCSMR_CHR                         (0x0040u)
+#define SCIF2_SCSMR_CA                          (0x0080u)
+
+#define SCIF2_SCBRR_D                           (0xFFu)
+
+#define SCIF2_SCSCR_CKE                         (0x0003u)
+#define SCIF2_SCSCR_REIE                        (0x0008u)
+#define SCIF2_SCSCR_RE                          (0x0010u)
+#define SCIF2_SCSCR_TE                          (0x0020u)
+#define SCIF2_SCSCR_RIE                         (0x0040u)
+#define SCIF2_SCSCR_TIE                         (0x0080u)
+
+#define SCIF2_SCFTDR_D                          (0xFFu)
+
+#define SCIF2_SCFSR_DR                          (0x0001u)
+#define SCIF2_SCFSR_RDF                         (0x0002u)
+#define SCIF2_SCFSR_PER                         (0x0004u)
+#define SCIF2_SCFSR_FER                         (0x0008u)
+#define SCIF2_SCFSR_BRK                         (0x0010u)
+#define SCIF2_SCFSR_TDFE                        (0x0020u)
+#define SCIF2_SCFSR_TEND                        (0x0040u)
+#define SCIF2_SCFSR_ER                          (0x0080u)
+#define SCIF2_SCFSR_FERN                        (0x0F00u)
+#define SCIF2_SCFSR_PERN                        (0xF000u)
+
+#define SCIF2_SCFRDR_D                          (0xFFu)
+
+#define SCIF2_SCFCR_LOOP                        (0x0001u)
+#define SCIF2_SCFCR_RFRST                       (0x0002u)
+#define SCIF2_SCFCR_TFRST                       (0x0004u)
+#define SCIF2_SCFCR_MCE                         (0x0008u)
+#define SCIF2_SCFCR_TTRG                        (0x0030u)
+#define SCIF2_SCFCR_RTRG                        (0x00C0u)
+#define SCIF2_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF2_SCFDR_R                           (0x001Fu)
+#define SCIF2_SCFDR_T                           (0x1F00u)
+
+#define SCIF2_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF2_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF2_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF2_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF2_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF2_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF2_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF2_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF2_SCLSR_ORER                        (0x0001u)
+
+#define SCIF2_SCEMR_ABCS                        (0x0001u)
+#define SCIF2_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF3 ---- */
+#define SCIF3_SCSMR_CKS                         (0x0003u)
+#define SCIF3_SCSMR_STOP                        (0x0008u)
+#define SCIF3_SCSMR_OE                          (0x0010u)
+#define SCIF3_SCSMR_PE                          (0x0020u)
+#define SCIF3_SCSMR_CHR                         (0x0040u)
+#define SCIF3_SCSMR_CA                          (0x0080u)
+
+#define SCIF3_SCBRR_D                           (0xFFu)
+
+#define SCIF3_SCSCR_CKE                         (0x0003u)
+#define SCIF3_SCSCR_REIE                        (0x0008u)
+#define SCIF3_SCSCR_RE                          (0x0010u)
+#define SCIF3_SCSCR_TE                          (0x0020u)
+#define SCIF3_SCSCR_RIE                         (0x0040u)
+#define SCIF3_SCSCR_TIE                         (0x0080u)
+
+#define SCIF3_SCFTDR_D                          (0xFFu)
+
+#define SCIF3_SCFSR_DR                          (0x0001u)
+#define SCIF3_SCFSR_RDF                         (0x0002u)
+#define SCIF3_SCFSR_PER                         (0x0004u)
+#define SCIF3_SCFSR_FER                         (0x0008u)
+#define SCIF3_SCFSR_BRK                         (0x0010u)
+#define SCIF3_SCFSR_TDFE                        (0x0020u)
+#define SCIF3_SCFSR_TEND                        (0x0040u)
+#define SCIF3_SCFSR_ER                          (0x0080u)
+#define SCIF3_SCFSR_FERN                        (0x0F00u)
+#define SCIF3_SCFSR_PERN                        (0xF000u)
+
+#define SCIF3_SCFRDR_D                          (0xFFu)
+
+#define SCIF3_SCFCR_LOOP                        (0x0001u)
+#define SCIF3_SCFCR_RFRST                       (0x0002u)
+#define SCIF3_SCFCR_TFRST                       (0x0004u)
+#define SCIF3_SCFCR_MCE                         (0x0008u)
+#define SCIF3_SCFCR_TTRG                        (0x0030u)
+#define SCIF3_SCFCR_RTRG                        (0x00C0u)
+#define SCIF3_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF3_SCFDR_R                           (0x001Fu)
+#define SCIF3_SCFDR_T                           (0x1F00u)
+
+#define SCIF3_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF3_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF3_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF3_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF3_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF3_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF3_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF3_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF3_SCLSR_ORER                        (0x0001u)
+
+#define SCIF3_SCEMR_ABCS                        (0x0001u)
+#define SCIF3_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF4 ---- */
+#define SCIF4_SCSMR_CKS                         (0x0003u)
+#define SCIF4_SCSMR_STOP                        (0x0008u)
+#define SCIF4_SCSMR_OE                          (0x0010u)
+#define SCIF4_SCSMR_PE                          (0x0020u)
+#define SCIF4_SCSMR_CHR                         (0x0040u)
+#define SCIF4_SCSMR_CA                          (0x0080u)
+
+#define SCIF4_SCBRR_D                           (0xFFu)
+
+#define SCIF4_SCSCR_CKE                         (0x0003u)
+#define SCIF4_SCSCR_REIE                        (0x0008u)
+#define SCIF4_SCSCR_RE                          (0x0010u)
+#define SCIF4_SCSCR_TE                          (0x0020u)
+#define SCIF4_SCSCR_RIE                         (0x0040u)
+#define SCIF4_SCSCR_TIE                         (0x0080u)
+
+#define SCIF4_SCFTDR_D                          (0xFFu)
+
+#define SCIF4_SCFSR_DR                          (0x0001u)
+#define SCIF4_SCFSR_RDF                         (0x0002u)
+#define SCIF4_SCFSR_PER                         (0x0004u)
+#define SCIF4_SCFSR_FER                         (0x0008u)
+#define SCIF4_SCFSR_BRK                         (0x0010u)
+#define SCIF4_SCFSR_TDFE                        (0x0020u)
+#define SCIF4_SCFSR_TEND                        (0x0040u)
+#define SCIF4_SCFSR_ER                          (0x0080u)
+#define SCIF4_SCFSR_FERN                        (0x0F00u)
+#define SCIF4_SCFSR_PERN                        (0xF000u)
+
+#define SCIF4_SCFRDR_D                          (0xFFu)
+
+#define SCIF4_SCFCR_LOOP                        (0x0001u)
+#define SCIF4_SCFCR_RFRST                       (0x0002u)
+#define SCIF4_SCFCR_TFRST                       (0x0004u)
+#define SCIF4_SCFCR_MCE                         (0x0008u)
+#define SCIF4_SCFCR_TTRG                        (0x0030u)
+#define SCIF4_SCFCR_RTRG                        (0x00C0u)
+#define SCIF4_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF4_SCFDR_R                           (0x001Fu)
+#define SCIF4_SCFDR_T                           (0x1F00u)
+
+#define SCIF4_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF4_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF4_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF4_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF4_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF4_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF4_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF4_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF4_SCLSR_ORER                        (0x0001u)
+
+#define SCIF4_SCEMR_ABCS                        (0x0001u)
+#define SCIF4_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF5 ---- */
+#define SCIF5_SCSMR_CKS                         (0x0003u)
+#define SCIF5_SCSMR_STOP                        (0x0008u)
+#define SCIF5_SCSMR_OE                          (0x0010u)
+#define SCIF5_SCSMR_PE                          (0x0020u)
+#define SCIF5_SCSMR_CHR                         (0x0040u)
+#define SCIF5_SCSMR_CA                          (0x0080u)
+
+#define SCIF5_SCBRR_D                           (0xFFu)
+
+#define SCIF5_SCSCR_CKE                         (0x0003u)
+#define SCIF5_SCSCR_REIE                        (0x0008u)
+#define SCIF5_SCSCR_RE                          (0x0010u)
+#define SCIF5_SCSCR_TE                          (0x0020u)
+#define SCIF5_SCSCR_RIE                         (0x0040u)
+#define SCIF5_SCSCR_TIE                         (0x0080u)
+
+#define SCIF5_SCFTDR_D                          (0xFFu)
+
+#define SCIF5_SCFSR_DR                          (0x0001u)
+#define SCIF5_SCFSR_RDF                         (0x0002u)
+#define SCIF5_SCFSR_PER                         (0x0004u)
+#define SCIF5_SCFSR_FER                         (0x0008u)
+#define SCIF5_SCFSR_BRK                         (0x0010u)
+#define SCIF5_SCFSR_TDFE                        (0x0020u)
+#define SCIF5_SCFSR_TEND                        (0x0040u)
+#define SCIF5_SCFSR_ER                          (0x0080u)
+#define SCIF5_SCFSR_FERN                        (0x0F00u)
+#define SCIF5_SCFSR_PERN                        (0xF000u)
+
+#define SCIF5_SCFRDR_D                          (0xFFu)
+
+#define SCIF5_SCFCR_LOOP                        (0x0001u)
+#define SCIF5_SCFCR_RFRST                       (0x0002u)
+#define SCIF5_SCFCR_TFRST                       (0x0004u)
+#define SCIF5_SCFCR_MCE                         (0x0008u)
+#define SCIF5_SCFCR_TTRG                        (0x0030u)
+#define SCIF5_SCFCR_RTRG                        (0x00C0u)
+#define SCIF5_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF5_SCFDR_R                           (0x001Fu)
+#define SCIF5_SCFDR_T                           (0x1F00u)
+
+#define SCIF5_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF5_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF5_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF5_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF5_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF5_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF5_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF5_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF5_SCLSR_ORER                        (0x0001u)
+
+#define SCIF5_SCEMR_ABCS                        (0x0001u)
+#define SCIF5_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF6 ---- */
+#define SCIF6_SCSMR_CKS                         (0x0003u)
+#define SCIF6_SCSMR_STOP                        (0x0008u)
+#define SCIF6_SCSMR_OE                          (0x0010u)
+#define SCIF6_SCSMR_PE                          (0x0020u)
+#define SCIF6_SCSMR_CHR                         (0x0040u)
+#define SCIF6_SCSMR_CA                          (0x0080u)
+
+#define SCIF6_SCBRR_D                           (0xFFu)
+
+#define SCIF6_SCSCR_CKE                         (0x0003u)
+#define SCIF6_SCSCR_REIE                        (0x0008u)
+#define SCIF6_SCSCR_RE                          (0x0010u)
+#define SCIF6_SCSCR_TE                          (0x0020u)
+#define SCIF6_SCSCR_RIE                         (0x0040u)
+#define SCIF6_SCSCR_TIE                         (0x0080u)
+
+#define SCIF6_SCFTDR_D                          (0xFFu)
+
+#define SCIF6_SCFSR_DR                          (0x0001u)
+#define SCIF6_SCFSR_RDF                         (0x0002u)
+#define SCIF6_SCFSR_PER                         (0x0004u)
+#define SCIF6_SCFSR_FER                         (0x0008u)
+#define SCIF6_SCFSR_BRK                         (0x0010u)
+#define SCIF6_SCFSR_TDFE                        (0x0020u)
+#define SCIF6_SCFSR_TEND                        (0x0040u)
+#define SCIF6_SCFSR_ER                          (0x0080u)
+#define SCIF6_SCFSR_FERN                        (0x0F00u)
+#define SCIF6_SCFSR_PERN                        (0xF000u)
+
+#define SCIF6_SCFRDR_D                          (0xFFu)
+
+#define SCIF6_SCFCR_LOOP                        (0x0001u)
+#define SCIF6_SCFCR_RFRST                       (0x0002u)
+#define SCIF6_SCFCR_TFRST                       (0x0004u)
+#define SCIF6_SCFCR_MCE                         (0x0008u)
+#define SCIF6_SCFCR_TTRG                        (0x0030u)
+#define SCIF6_SCFCR_RTRG                        (0x00C0u)
+#define SCIF6_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF6_SCFDR_R                           (0x001Fu)
+#define SCIF6_SCFDR_T                           (0x1F00u)
+
+#define SCIF6_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF6_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF6_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF6_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF6_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF6_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF6_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF6_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF6_SCLSR_ORER                        (0x0001u)
+
+#define SCIF6_SCEMR_ABCS                        (0x0001u)
+#define SCIF6_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF7 ---- */
+#define SCIF7_SCSMR_CKS                         (0x0003u)
+#define SCIF7_SCSMR_STOP                        (0x0008u)
+#define SCIF7_SCSMR_OE                          (0x0010u)
+#define SCIF7_SCSMR_PE                          (0x0020u)
+#define SCIF7_SCSMR_CHR                         (0x0040u)
+#define SCIF7_SCSMR_CA                          (0x0080u)
+
+#define SCIF7_SCBRR_D                           (0xFFu)
+
+#define SCIF7_SCSCR_CKE                         (0x0003u)
+#define SCIF7_SCSCR_REIE                        (0x0008u)
+#define SCIF7_SCSCR_RE                          (0x0010u)
+#define SCIF7_SCSCR_TE                          (0x0020u)
+#define SCIF7_SCSCR_RIE                         (0x0040u)
+#define SCIF7_SCSCR_TIE                         (0x0080u)
+
+#define SCIF7_SCFTDR_D                          (0xFFu)
+
+#define SCIF7_SCFSR_DR                          (0x0001u)
+#define SCIF7_SCFSR_RDF                         (0x0002u)
+#define SCIF7_SCFSR_PER                         (0x0004u)
+#define SCIF7_SCFSR_FER                         (0x0008u)
+#define SCIF7_SCFSR_BRK                         (0x0010u)
+#define SCIF7_SCFSR_TDFE                        (0x0020u)
+#define SCIF7_SCFSR_TEND                        (0x0040u)
+#define SCIF7_SCFSR_ER                          (0x0080u)
+#define SCIF7_SCFSR_FERN                        (0x0F00u)
+#define SCIF7_SCFSR_PERN                        (0xF000u)
+
+#define SCIF7_SCFRDR_D                          (0xFFu)
+
+#define SCIF7_SCFCR_LOOP                        (0x0001u)
+#define SCIF7_SCFCR_RFRST                       (0x0002u)
+#define SCIF7_SCFCR_TFRST                       (0x0004u)
+#define SCIF7_SCFCR_MCE                         (0x0008u)
+#define SCIF7_SCFCR_TTRG                        (0x0030u)
+#define SCIF7_SCFCR_RTRG                        (0x00C0u)
+#define SCIF7_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF7_SCFDR_R                           (0x001Fu)
+#define SCIF7_SCFDR_T                           (0x1F00u)
+
+#define SCIF7_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF7_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF7_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF7_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF7_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF7_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF7_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF7_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF7_SCLSR_ORER                        (0x0001u)
+
+#define SCIF7_SCEMR_ABCS                        (0x0001u)
+#define SCIF7_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIFn ---- */
+#define SCIFn_SCSMR_CKS                         (0x0003u)
+#define SCIFn_SCSMR_STOP                        (0x0008u)
+#define SCIFn_SCSMR_OE                          (0x0010u)
+#define SCIFn_SCSMR_PE                          (0x0020u)
+#define SCIFn_SCSMR_CHR                         (0x0040u)
+#define SCIFn_SCSMR_CA                          (0x0080u)
+
+#define SCIFn_SCBRR_D                           (0xFFu)
+
+#define SCIFn_SCSCR_CKE                         (0x0003u)
+#define SCIFn_SCSCR_REIE                        (0x0008u)
+#define SCIFn_SCSCR_RE                          (0x0010u)
+#define SCIFn_SCSCR_TE                          (0x0020u)
+#define SCIFn_SCSCR_RIE                         (0x0040u)
+#define SCIFn_SCSCR_TIE                         (0x0080u)
+
+#define SCIFn_SCFTDR_D                          (0xFFu)
+
+#define SCIFn_SCFSR_DR                          (0x0001u)
+#define SCIFn_SCFSR_RDF                         (0x0002u)
+#define SCIFn_SCFSR_PER                         (0x0004u)
+#define SCIFn_SCFSR_FER                         (0x0008u)
+#define SCIFn_SCFSR_BRK                         (0x0010u)
+#define SCIFn_SCFSR_TDFE                        (0x0020u)
+#define SCIFn_SCFSR_TEND                        (0x0040u)
+#define SCIFn_SCFSR_ER                          (0x0080u)
+#define SCIFn_SCFSR_FERN                        (0x0F00u)
+#define SCIFn_SCFSR_PERN                        (0xF000u)
+
+#define SCIFn_SCFRDR_D                          (0xFFu)
+
+#define SCIFn_SCFCR_LOOP                        (0x0001u)
+#define SCIFn_SCFCR_RFRST                       (0x0002u)
+#define SCIFn_SCFCR_TFRST                       (0x0004u)
+#define SCIFn_SCFCR_MCE                         (0x0008u)
+#define SCIFn_SCFCR_TTRG                        (0x0030u)
+#define SCIFn_SCFCR_RTRG                        (0x00C0u)
+#define SCIFn_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIFn_SCFDR_R                           (0x001Fu)
+#define SCIFn_SCFDR_T                           (0x1F00u)
+
+#define SCIFn_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIFn_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIFn_SCSPTR_SCKDT                      (0x0004u)
+#define SCIFn_SCSPTR_SCKIO                      (0x0008u)
+#define SCIFn_SCSPTR_CTSDT                      (0x0010u)
+#define SCIFn_SCSPTR_CTSIO                      (0x0020u)
+#define SCIFn_SCSPTR_RTSDT                      (0x0040u)
+#define SCIFn_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIFn_SCLSR_ORER                        (0x0001u)
+
+#define SCIFn_SCEMR_ABCS                        (0x0001u)
+#define SCIFn_SCEMR_BGDM                        (0x0080u)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- SCIF0 ---- */
+#define SCIF0_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF0_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF0_SCSMR_OE_SHIFT                    (4u)
+#define SCIF0_SCSMR_PE_SHIFT                    (5u)
+#define SCIF0_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF0_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF0_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF0_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF0_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF0_SCSCR_RE_SHIFT                    (4u)
+#define SCIF0_SCSCR_TE_SHIFT                    (5u)
+#define SCIF0_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF0_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF0_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF0_SCFSR_DR_SHIFT                    (0u)
+#define SCIF0_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF0_SCFSR_PER_SHIFT                   (2u)
+#define SCIF0_SCFSR_FER_SHIFT                   (3u)
+#define SCIF0_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF0_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF0_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF0_SCFSR_ER_SHIFT                    (7u)
+#define SCIF0_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF0_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF0_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF0_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF0_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF0_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF0_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF0_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF0_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF0_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF0_SCFDR_R_SHIFT                     (0u)
+#define SCIF0_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF0_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF0_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF0_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF0_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF0_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF0_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF0_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF0_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF0_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF0_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF0_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF1 ---- */
+#define SCIF1_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF1_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF1_SCSMR_OE_SHIFT                    (4u)
+#define SCIF1_SCSMR_PE_SHIFT                    (5u)
+#define SCIF1_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF1_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF1_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF1_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF1_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF1_SCSCR_RE_SHIFT                    (4u)
+#define SCIF1_SCSCR_TE_SHIFT                    (5u)
+#define SCIF1_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF1_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF1_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF1_SCFSR_DR_SHIFT                    (0u)
+#define SCIF1_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF1_SCFSR_PER_SHIFT                   (2u)
+#define SCIF1_SCFSR_FER_SHIFT                   (3u)
+#define SCIF1_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF1_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF1_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF1_SCFSR_ER_SHIFT                    (7u)
+#define SCIF1_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF1_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF1_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF1_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF1_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF1_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF1_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF1_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF1_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF1_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF1_SCFDR_R_SHIFT                     (0u)
+#define SCIF1_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF1_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF1_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF1_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF1_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF1_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF1_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF1_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF1_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF1_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF1_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF1_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF2 ---- */
+#define SCIF2_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF2_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF2_SCSMR_OE_SHIFT                    (4u)
+#define SCIF2_SCSMR_PE_SHIFT                    (5u)
+#define SCIF2_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF2_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF2_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF2_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF2_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF2_SCSCR_RE_SHIFT                    (4u)
+#define SCIF2_SCSCR_TE_SHIFT                    (5u)
+#define SCIF2_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF2_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF2_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF2_SCFSR_DR_SHIFT                    (0u)
+#define SCIF2_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF2_SCFSR_PER_SHIFT                   (2u)
+#define SCIF2_SCFSR_FER_SHIFT                   (3u)
+#define SCIF2_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF2_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF2_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF2_SCFSR_ER_SHIFT                    (7u)
+#define SCIF2_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF2_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF2_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF2_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF2_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF2_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF2_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF2_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF2_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF2_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF2_SCFDR_R_SHIFT                     (0u)
+#define SCIF2_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF2_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF2_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF2_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF2_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF2_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF2_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF2_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF2_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF2_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF2_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF2_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF3 ---- */
+#define SCIF3_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF3_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF3_SCSMR_OE_SHIFT                    (4u)
+#define SCIF3_SCSMR_PE_SHIFT                    (5u)
+#define SCIF3_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF3_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF3_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF3_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF3_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF3_SCSCR_RE_SHIFT                    (4u)
+#define SCIF3_SCSCR_TE_SHIFT                    (5u)
+#define SCIF3_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF3_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF3_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF3_SCFSR_DR_SHIFT                    (0u)
+#define SCIF3_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF3_SCFSR_PER_SHIFT                   (2u)
+#define SCIF3_SCFSR_FER_SHIFT                   (3u)
+#define SCIF3_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF3_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF3_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF3_SCFSR_ER_SHIFT                    (7u)
+#define SCIF3_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF3_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF3_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF3_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF3_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF3_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF3_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF3_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF3_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF3_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF3_SCFDR_R_SHIFT                     (0u)
+#define SCIF3_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF3_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF3_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF3_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF3_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF3_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF3_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF3_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF3_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF3_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF3_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF3_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF4 ---- */
+#define SCIF4_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF4_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF4_SCSMR_OE_SHIFT                    (4u)
+#define SCIF4_SCSMR_PE_SHIFT                    (5u)
+#define SCIF4_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF4_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF4_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF4_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF4_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF4_SCSCR_RE_SHIFT                    (4u)
+#define SCIF4_SCSCR_TE_SHIFT                    (5u)
+#define SCIF4_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF4_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF4_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF4_SCFSR_DR_SHIFT                    (0u)
+#define SCIF4_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF4_SCFSR_PER_SHIFT                   (2u)
+#define SCIF4_SCFSR_FER_SHIFT                   (3u)
+#define SCIF4_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF4_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF4_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF4_SCFSR_ER_SHIFT                    (7u)
+#define SCIF4_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF4_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF4_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF4_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF4_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF4_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF4_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF4_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF4_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF4_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF4_SCFDR_R_SHIFT                     (0u)
+#define SCIF4_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF4_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF4_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF4_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF4_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF4_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF4_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF4_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF4_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF4_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF4_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF4_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF5 ---- */
+#define SCIF5_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF5_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF5_SCSMR_OE_SHIFT                    (4u)
+#define SCIF5_SCSMR_PE_SHIFT                    (5u)
+#define SCIF5_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF5_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF5_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF5_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF5_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF5_SCSCR_RE_SHIFT                    (4u)
+#define SCIF5_SCSCR_TE_SHIFT                    (5u)
+#define SCIF5_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF5_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF5_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF5_SCFSR_DR_SHIFT                    (0u)
+#define SCIF5_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF5_SCFSR_PER_SHIFT                   (2u)
+#define SCIF5_SCFSR_FER_SHIFT                   (3u)
+#define SCIF5_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF5_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF5_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF5_SCFSR_ER_SHIFT                    (7u)
+#define SCIF5_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF5_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF5_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF5_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF5_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF5_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF5_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF5_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF5_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF5_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF5_SCFDR_R_SHIFT                     (0u)
+#define SCIF5_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF5_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF5_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF5_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF5_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF5_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF5_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF5_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF5_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF5_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF5_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF5_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF6 ---- */
+#define SCIF6_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF6_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF6_SCSMR_OE_SHIFT                    (4u)
+#define SCIF6_SCSMR_PE_SHIFT                    (5u)
+#define SCIF6_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF6_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF6_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF6_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF6_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF6_SCSCR_RE_SHIFT                    (4u)
+#define SCIF6_SCSCR_TE_SHIFT                    (5u)
+#define SCIF6_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF6_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF6_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF6_SCFSR_DR_SHIFT                    (0u)
+#define SCIF6_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF6_SCFSR_PER_SHIFT                   (2u)
+#define SCIF6_SCFSR_FER_SHIFT                   (3u)
+#define SCIF6_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF6_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF6_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF6_SCFSR_ER_SHIFT                    (7u)
+#define SCIF6_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF6_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF6_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF6_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF6_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF6_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF6_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF6_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF6_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF6_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF6_SCFDR_R_SHIFT                     (0u)
+#define SCIF6_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF6_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF6_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF6_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF6_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF6_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF6_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF6_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF6_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF6_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF6_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF6_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF7 ---- */
+#define SCIF7_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF7_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF7_SCSMR_OE_SHIFT                    (4u)
+#define SCIF7_SCSMR_PE_SHIFT                    (5u)
+#define SCIF7_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF7_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF7_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF7_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF7_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF7_SCSCR_RE_SHIFT                    (4u)
+#define SCIF7_SCSCR_TE_SHIFT                    (5u)
+#define SCIF7_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF7_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF7_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF7_SCFSR_DR_SHIFT                    (0u)
+#define SCIF7_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF7_SCFSR_PER_SHIFT                   (2u)
+#define SCIF7_SCFSR_FER_SHIFT                   (3u)
+#define SCIF7_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF7_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF7_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF7_SCFSR_ER_SHIFT                    (7u)
+#define SCIF7_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF7_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF7_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF7_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF7_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF7_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF7_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF7_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF7_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF7_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF7_SCFDR_R_SHIFT                     (0u)
+#define SCIF7_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF7_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF7_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF7_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF7_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF7_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF7_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF7_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF7_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF7_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF7_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF7_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIFn ---- */
+#define SCIFn_SCSMR_CKS_SHIFT                   (0u)
+#define SCIFn_SCSMR_STOP_SHIFT                  (3u)
+#define SCIFn_SCSMR_OE_SHIFT                    (4u)
+#define SCIFn_SCSMR_PE_SHIFT                    (5u)
+#define SCIFn_SCSMR_CHR_SHIFT                   (6u)
+#define SCIFn_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIFn_SCBRR_D_SHIFT                     (0u)
+
+#define SCIFn_SCSCR_CKE_SHIFT                   (0u)
+#define SCIFn_SCSCR_REIE_SHIFT                  (3u)
+#define SCIFn_SCSCR_RE_SHIFT                    (4u)
+#define SCIFn_SCSCR_TE_SHIFT                    (5u)
+#define SCIFn_SCSCR_RIE_SHIFT                   (6u)
+#define SCIFn_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIFn_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIFn_SCFSR_DR_SHIFT                    (0u)
+#define SCIFn_SCFSR_RDF_SHIFT                   (1u)
+#define SCIFn_SCFSR_PER_SHIFT                   (2u)
+#define SCIFn_SCFSR_FER_SHIFT                   (3u)
+#define SCIFn_SCFSR_BRK_SHIFT                   (4u)
+#define SCIFn_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIFn_SCFSR_TEND_SHIFT                  (6u)
+#define SCIFn_SCFSR_ER_SHIFT                    (7u)
+#define SCIFn_SCFSR_FERN_SHIFT                  (8u)
+#define SCIFn_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIFn_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIFn_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIFn_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIFn_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIFn_SCFCR_MCE_SHIFT                   (3u)
+#define SCIFn_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIFn_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIFn_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIFn_SCFDR_R_SHIFT                     (0u)
+#define SCIFn_SCFDR_T_SHIFT                     (8u)
+
+#define SCIFn_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIFn_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIFn_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIFn_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIFn_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIFn_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIFn_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIFn_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIFn_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIFn_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIFn_SCEMR_BGDM_SHIFT                  (7u)
+
+
+#endif /* SCIF_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/spibsc_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/spibsc_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/spibsc_iobitmask.h	(revision 374)
@@ -0,0 +1,292 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name     : spibsc_iobitmask.h
+* $Rev: $
+* $Date::                           $
+* Description : SPI multi I/O bus controller register define header
+*******************************************************************************/
+#ifndef SPIBSC_IOBITMASK_H
+#define SPIBSC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define SPIBSC_CMNCR_BSZ               (0x00000003uL)
+
+#define SPIBSC_CMNCR_CPOL              (0x00000008uL)
+#define SPIBSC_CMNCR_SSLP              (0x00000010uL)
+#define SPIBSC_CMNCR_CPHAR             (0x00000020uL)
+#define SPIBSC_CMNCR_CPHAT             (0x00000040uL)
+
+#define SPIBSC_CMNCR_IO0FV             (0x00000300uL)
+
+#define SPIBSC_CMNCR_IO2FV             (0x00003000uL)
+#define SPIBSC_CMNCR_IO3FV             (0x0000C000uL)
+#define SPIBSC_CMNCR_MOIIO0            (0x00030000uL)
+#define SPIBSC_CMNCR_MOIIO1            (0x000C0000uL)
+#define SPIBSC_CMNCR_MOIIO2            (0x00300000uL)
+#define SPIBSC_CMNCR_MOIIO3            (0x00C00000uL)
+#define SPIBSC_CMNCR_SFDE              (0x01000000uL)
+
+#define SPIBSC_CMNCR_MD                (0x80000000uL)
+
+#define SPIBSC_SSLDR_SCKDL             (0x00000007uL)
+
+#define SPIBSC_SSLDR_SLNDL             (0x00000700uL)
+
+#define SPIBSC_SSLDR_SPNDL             (0x00070000uL)
+
+#define SPIBSC_SPBCR_BRDV              (0x00000003uL)
+
+#define SPIBSC_SPBCR_SPBR              (0x0000FF00uL)
+
+#define SPIBSC_DRCR_SSLE               (0x00000001uL)
+
+#define SPIBSC_DRCR_RBE                (0x00000100uL)
+#define SPIBSC_DRCR_RCF                (0x00000200uL)
+
+#define SPIBSC_DRCR_RBURST             (0x000F0000uL)
+
+#define SPIBSC_DRCR_SSLN               (0x01000000uL)
+
+#define SPIBSC_DRCMR_OCMD              (0x000000FFuL)
+
+#define SPIBSC_DRCMR_CMD               (0x00FF0000uL)
+
+#define SPIBSC_DREAR_EAC               (0x00000007uL)
+
+#define SPIBSC_DREAR_EAV               (0x00FF0000uL)
+
+#define SPIBSC_DROPR_OPD0              (0x000000FFuL)
+#define SPIBSC_DROPR_OPD1              (0x0000FF00uL)
+#define SPIBSC_DROPR_OPD2              (0x00FF0000uL)
+#define SPIBSC_DROPR_OPD3              (0xFF000000uL)
+
+#define SPIBSC_DRENR_OPDE              (0x000000F0uL)
+#define SPIBSC_DRENR_ADE               (0x00000F00uL)
+#define SPIBSC_DRENR_OCDE              (0x00001000uL)
+
+#define SPIBSC_DRENR_CDE               (0x00004000uL)
+#define SPIBSC_DRENR_DME               (0x00008000uL)
+#define SPIBSC_DRENR_DRDB              (0x00030000uL)
+
+#define SPIBSC_DRENR_OPDB              (0x00300000uL)
+
+#define SPIBSC_DRENR_ADB               (0x03000000uL)
+
+#define SPIBSC_DRENR_OCDB              (0x30000000uL)
+#define SPIBSC_DRENR_CDB               (0xC0000000uL)
+
+#define SPIBSC_SMCR_SPIE               (0x00000001uL)
+#define SPIBSC_SMCR_SPIWE              (0x00000002uL)
+#define SPIBSC_SMCR_SPIRE              (0x00000004uL)
+
+#define SPIBSC_SMCR_SSLKP              (0x00000100uL)
+
+#define SPIBSC_SMCMR_OCMD              (0x000000FFuL)
+
+#define SPIBSC_SMCMR_CMD               (0x00FF0000uL)
+
+#define SPIBSC_SMADR_ADR               (0xFFFFFFFFuL)
+
+#define SPIBSC_SMOPR_OPD0              (0x000000FFuL)
+#define SPIBSC_SMOPR_OPD1              (0x0000FF00uL)
+#define SPIBSC_SMOPR_OPD2              (0x00FF0000uL)
+#define SPIBSC_SMOPR_OPD3              (0xFF000000uL)
+
+#define SPIBSC_SMENR_SPIDE             (0x0000000FuL)
+#define SPIBSC_SMENR_OPDE              (0x000000F0uL)
+#define SPIBSC_SMENR_ADE               (0x00000F00uL)
+#define SPIBSC_SMENR_OCDE              (0x00001000uL)
+
+#define SPIBSC_SMENR_CDE               (0x00004000uL)
+#define SPIBSC_SMENR_DME               (0x00008000uL)
+#define SPIBSC_SMENR_SPIDB             (0x00030000uL)
+
+#define SPIBSC_SMENR_OPDB              (0x00300000uL)
+
+#define SPIBSC_SMENR_ADB               (0x03000000uL)
+
+#define SPIBSC_SMENR_OCDB              (0x30000000uL)
+#define SPIBSC_SMENR_CDB               (0xC0000000uL)
+
+#define SPIBSC_SMRDR0_RDATA0           (0xFFFFFFFFuL)
+#define SPIBSC_SMRDR1_RDATA1           (0xFFFFFFFFuL)
+#define SPIBSC_SMWDR0_WDATA0           (0xFFFFFFFFuL)
+#define SPIBSC_SMWDR1_WDATA1           (0xFFFFFFFFuL)
+
+#define SPIBSC_CMNSR_TEND              (0x00000001uL)
+#define SPIBSC_CMNSR_SSLF              (0x00000002uL)
+
+#define SPIBSC_DRDMCR_DMCYC            (0x00000007uL)
+
+#define SPIBSC_DRDMCR_DMDB             (0x00030000uL)
+
+#define SPIBSC_DRDRENR_DRDRE           (0x00000001uL)
+
+#define SPIBSC_DRDRENR_OPDRE           (0x00000010uL)
+
+#define SPIBSC_DRDRENR_ADDRE           (0x00000100uL)
+
+#define SPIBSC_SMDMCR_DMCYC            (0x00000007uL)
+
+#define SPIBSC_SMDMCR_DMDB             (0x00030000uL)
+
+#define SPIBSC_SMDRENR_SPIDRE          (0x00000001uL)
+
+#define SPIBSC_SMDRENR_OPDRE           (0x00000010uL)
+
+#define SPIBSC_SMDRENR_ADDRE           (0x00000100uL)
+
+/* Shift parameter */
+#define SPIBSC_CMNCR_BSZ_SHIFT         (0u)
+
+#define SPIBSC_CMNCR_CPOL_SHIFT        (3u)
+#define SPIBSC_CMNCR_SSLP_SHIFT        (4u)
+#define SPIBSC_CMNCR_CPHAR_SHIFT       (5u)
+#define SPIBSC_CMNCR_CPHAT_SHIFT       (6u)
+
+#define SPIBSC_CMNCR_IO0FV_SHIFT       (8u)
+
+#define SPIBSC_CMNCR_IO2FV_SHIFT       (12u)
+#define SPIBSC_CMNCR_IO3FV_SHIFT       (14u)
+#define SPIBSC_CMNCR_MOIIO0_SHIFT      (16u)
+#define SPIBSC_CMNCR_MOIIO1_SHIFT      (18u)
+#define SPIBSC_CMNCR_MOIIO2_SHIFT      (20u)
+#define SPIBSC_CMNCR_MOIIO3_SHIFT      (22u)
+#define SPIBSC_CMNCR_SFDE_SHIFT        (24u)
+
+#define SPIBSC_CMNCR_MD_SHIFT          (31u)
+
+#define SPIBSC_SSLDR_SCKDL_SHIFT       (0u)
+
+#define SPIBSC_SSLDR_SLNDL_SHIFT       (8u)
+
+#define SPIBSC_SSLDR_SPNDL_SHIFT       (16u)
+
+#define SPIBSC_SPBCR_BRDV_SHIFT        (0u)
+
+#define SPIBSC_SPBCR_SPBR_SHIFT        (8u)
+
+#define SPIBSC_DRCR_SSLE_SHIFT         (0u)
+
+#define SPIBSC_DRCR_RBE_SHIFT          (8u)
+#define SPIBSC_DRCR_RCF_SHIFT          (9u)
+
+#define SPIBSC_DRCR_RBURST_SHIFT       (16u)
+
+#define SPIBSC_DRCR_SSLN_SHIFT         (24u)
+
+#define SPIBSC_DRCMR_OCMD_SHIFT        (0u)
+
+#define SPIBSC_DRCMR_CMD_SHIFT         (16u)
+
+#define SPIBSC_DREAR_EAC_SHIFT         (0u)
+
+#define SPIBSC_DREAR_EAV_SHIFT         (16u)
+
+#define SPIBSC_DROPR_OPD0_SHIFT        (0u)
+#define SPIBSC_DROPR_OPD1_SHIFT        (8u)
+#define SPIBSC_DROPR_OPD2_SHIFT        (16u)
+#define SPIBSC_DROPR_OPD3_SHIFT        (24u)
+
+#define SPIBSC_DRENR_OPDE_SHIFT        (4u)
+#define SPIBSC_DRENR_ADE_SHIFT         (8u)
+#define SPIBSC_DRENR_OCDE_SHIFT        (12u)
+
+#define SPIBSC_DRENR_CDE_SHIFT         (14u)
+#define SPIBSC_DRENR_DME_SHIFT         (15u)
+#define SPIBSC_DRENR_DRDB_SHIFT        (16u)
+
+#define SPIBSC_DRENR_OPDB_SHIFT        (20u)
+
+#define SPIBSC_DRENR_ADB_SHIFT         (24u)
+
+#define SPIBSC_DRENR_OCDB_SHIFT        (28u)
+#define SPIBSC_DRENR_CDB_SHIFT         (30u)
+
+#define SPIBSC_SMCR_SPIE_SHIFT         (0u)
+#define SPIBSC_SMCR_SPIWE_SHIFT        (1u)
+#define SPIBSC_SMCR_SPIRE_SHIFT        (2u)
+
+#define SPIBSC_SMCR_SSLKP_SHIFT        (8u)
+
+#define SPIBSC_SMCMR_OCMD_SHIFT        (0u)
+
+#define SPIBSC_SMCMR_CMD_SHIFT         (16u)
+
+#define SPIBSC_SMADR_ADR_SHIFT         (0u)
+
+#define SPIBSC_SMOPR_OPD0_SHIFT        (0u)
+#define SPIBSC_SMOPR_OPD1_SHIFT        (8u)
+#define SPIBSC_SMOPR_OPD2_SHIFT        (16u)
+#define SPIBSC_SMOPR_OPD3_SHIFT        (24u)
+
+#define SPIBSC_SMENR_SPIDE_SHIFT       (0u)
+#define SPIBSC_SMENR_OPDE_SHIFT        (4u)
+#define SPIBSC_SMENR_ADE_SHIFT         (8u)
+#define SPIBSC_SMENR_OCDE_SHIFT        (12u)
+
+#define SPIBSC_SMENR_CDE_SHIFT         (14u)
+#define SPIBSC_SMENR_DME_SHIFT         (15u)
+#define SPIBSC_SMENR_SPIDB_SHIFT       (16u)
+
+#define SPIBSC_SMENR_OPDB_SHIFT        (20u)
+
+#define SPIBSC_SMENR_ADB_SHIFT         (24u)
+
+#define SPIBSC_SMENR_OCDB_SHIFT        (28u)
+#define SPIBSC_SMENR_CDB_SHIFT         (30u)
+
+#define SPIBSC_SMRDR0_RDATA0_SHIFT     (0u)
+#define SPIBSC_SMRDR1_RDATA1_SHIFT     (0u)
+#define SPIBSC_SMWDR0_WDATA0_SHIFT     (0u)
+#define SPIBSC_SMWDR1_WDATA1_SHIFT     (0u)
+
+#define SPIBSC_CMNSR_TEND_SHIFT        (0u)
+#define SPIBSC_CMNSR_SSLF_SHIFT        (1u)
+
+#define SPIBSC_DRDMCR_DMCYC_SHIFT      (0u)
+
+#define SPIBSC_DRDMCR_DMDB_SHIFT       (16u)
+
+#define SPIBSC_DRDRENR_DRDRE_SHIFT     (0u)
+
+#define SPIBSC_DRDRENR_OPDRE_SHIFT     (4u)
+
+#define SPIBSC_DRDRENR_ADDRE_SHIFT     (8u)
+
+#define SPIBSC_SMDMCR_DMCYC_SHIFT      (0u)
+
+#define SPIBSC_SMDMCR_DMDB_SHIFT       (16u)
+
+#define SPIBSC_SMDRENR_SPIDRE_SHIFT    (0u)
+
+#define SPIBSC_SMDRENR_OPDRE_SHIFT     (4u)
+
+#define SPIBSC_SMDRENR_ADDRE_SHIFT     (8u)
+
+#endif /* SPIBSC_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h	(revision 374)
@@ -0,0 +1,731 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : usb_iobitmask.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : USB register define header
+*******************************************************************************/
+#ifndef USB_IOBITMASK_H
+#define USB_IOBITMASK_H
+
+/*==============================================*/
+/* SYSCFG                                       */
+/*==============================================*/
+#define     USB_SYSCFG_USBE                 (0x0001u)
+#define     USB_SYSCFG_UPLLE                (0x0002u)
+#define     USB_SYSCFG_UCKSEL               (0x0004u)
+/* #define  USB_SYSCFG_RESERVED1            (0x0008u) */
+#define     USB_SYSCFG_DPRPU                (0x0010u)
+#define     USB_SYSCFG_DRPD                 (0x0020u)
+#define     USB_SYSCFG_DCFM                 (0x0040u)
+#define     USB_SYSCFG_HSE                  (0x0080u)
+/* #define  USB_SYSCFG_RESERVED2            (0xFF00u) */
+
+#define     USB_SYSCFG_USBE_SHIFT           (0)
+#define     USB_SYSCFG_UPLLE_SHIFT          (1)
+#define     USB_SYSCFG_UCKSEL_SHIFT         (2)
+/* #define  USB_SYSCFG_RESERVED1_SHIFT      (3) */
+#define     USB_SYSCFG_DPRPU_SHIFT          (4)
+#define     USB_SYSCFG_DRPD_SHIFT           (5)
+#define     USB_SYSCFG_DCFM_SHIFT           (6)
+#define     USB_SYSCFG_HSE_SHIFT            (7)
+/* #define  USB_SYSCFG_RESERVED2_SHIFT      (8) */
+
+/*==============================================*/
+/* BUSWAIT                                      */
+/*==============================================*/
+#define     USB_BUSWAIT_BWAIT               (0x003Fu)
+
+#define     USB_BUSWAIT_BWAIT_SHIFT         (0)
+
+/*==============================================*/
+/* SYSSTS0                                      */
+/*==============================================*/
+#define     USB_SYSSTS0_LNST                (0x0003u)
+#define     USB_SYSSTS0_SOFEA               (0x0020u)
+#define     USB_SYSSTS0_HTACT               (0x0040u)
+
+#define     USB_SYSSTS0_LNST_SHIFT          (0)
+#define     USB_SYSSTS0_SOFEA_SHIFT         (5)
+#define     USB_SYSSTS0_HTACT_SHIFT         (6)
+
+/*==============================================*/
+/* DVSTCTR0                                     */
+/*==============================================*/
+#define     USB_DVSTCTR0_RHST               (0x0007u)
+/* #define  USB_DVSTCTR0_RESERVED           (0x0008u) */
+#define     USB_DVSTCTR0_UACT               (0x0010u)
+#define     USB_DVSTCTR0_RESUME             (0x0020u)
+#define     USB_DVSTCTR0_USBRST             (0x0040u)
+#define     USB_DVSTCTR0_RWUPE              (0x0080u)
+#define     USB_DVSTCTR0_WKUP               (0x0100u)
+
+#define     USB_DVSTCTR0_RHST_SHIFT         (0)
+/* #define  USB_DVSTCTR0_RESERVED_SHIFT     (3) */
+#define     USB_DVSTCTR0_UACT_SHIFT         (4)
+#define     USB_DVSTCTR0_RESUME_SHIFT       (5)
+#define     USB_DVSTCTR0_USBRST_SHIFT       (6)
+#define     USB_DVSTCTR0_RWUPE_SHIFT        (7)
+#define     USB_DVSTCTR0_WKUP_SHIFT         (8)
+
+/*==============================================*/
+/* TESTMODE                                     */
+/*==============================================*/
+#define     USB_TESTMODE_UTST               (0x000Fu)
+/* #define  USB_TESTMODE_RESERVED           (0xFFF0u) */
+
+#define     USB_TESTMODE_UTST_SHIFT         (0)
+/* #define  USB_TESTMODE_RESERVED_SHIFT     (4) */
+
+/*==============================================*/
+/* DnFBCFG                                      */
+/*==============================================*/
+/* #define      USB_DnFBCFG_RESERVED1       (0x000Fu) */
+#define     USB_DnFBCFG_TENDE               (0x0010u)
+/* #define      USB_DnFBCFG_RESERVED2       (0x0FE0u) */
+#define     USB_DnFBCFG_DFACC               (0x3000u)
+/* #define      USB_DnFBCFG_RESERVED3       (0xC000u) */
+
+/* #define  USB_DnFBCFG_RESERVED1_SHIFT     (0) */
+#define     USB_DnFBCFG_TENDE_SHIFT         (4)
+/* #define  USB_DnFBCFG_RESERVED2_SHIFT     (5) */
+#define     USB_DnFBCFG_DFACC_SHIFT         (12)
+/* #define  USB_DnFBCFG_RESERVED3_SHIFT     (14) */
+
+/*==============================================*/
+/* CFIFO                                        */
+/*==============================================*/
+#define     USB_CFIFO_FIFOPORT              (0xFFFFFFFFuL)
+
+#define     USB_CFIFO_FIFOPORT_SHIFT        (0)
+
+/*==============================================*/
+/* DnFIFO                                       */
+/*==============================================*/
+#define     USB_DnFIFO_FIFOPORT             (0xFFFFFFFFuL)
+
+#define     USB_DnFIFO_FIFOPORT_SHIFT       (0)
+
+/*==============================================*/
+/* CFIFOSEL                                     */
+/*==============================================*/
+#define     USB_CFIFOSEL_CURPIPE            (0x000Fu)
+/* #define  USB_CFIFOSEL_RESERVED1          (0x0010u) */
+#define     USB_CFIFOSEL_ISEL_              (0x0020u)
+/* #define  USB_CFIFOSEL_RESERVED2          (0x00C0u) */
+#define     USB_CFIFOSEL_BIGEND             (0x0100u)
+/* #define  USB_CFIFOSEL_RESERVED3          (0x0200u) */
+#define     USB_CFIFOSEL_MBW                (0x0C00u)
+/* #define  USB_CFIFOSEL_RESERVED4          (0x3000u) */
+#define     USB_CFIFOSEL_REW                (0x4000u)
+#define     USB_CFIFOSEL_RCNT               (0x8000u)
+
+#define     USB_CFIFOSEL_CURPIPE_SHIFT      (0)
+/* #define  USB_CFIFOSEL_RESERVED1_SHIFT    (4) */
+#define     USB_CFIFOSEL_ISEL_SHIFT_        (5)
+/* #define  USB_CFIFOSEL_RESERVED2_SHIFT    (6) */
+#define     USB_CFIFOSEL_BIGEND_SHIFT       (8)
+/* #define  USB_CFIFOSEL_RESERVED3_SHIFT    (9) */
+#define     USB_CFIFOSEL_MBW_SHIFT          (10)
+/* #define  USB_CFIFOSEL_RESERVED4_SHIFT    (12) */
+#define     USB_CFIFOSEL_REW_SHIFT          (14)
+#define     USB_CFIFOSEL_RCNT_SHIFT         (15)
+
+/*==============================================*/
+/* DnFIFOSEL                                    */
+/*==============================================*/
+#define     USB_DnFIFOSEL_CURPIPE           (0x000Fu)
+/* #define  USB_DnFIFOSEL_RESERVED1         (0x00F0u) */
+#define     USB_DnFIFOSEL_BIGEND            (0x0100u)
+/* #define  USB_DnFIFOSEL_RESERVED2         (0x0200u) */
+#define     USB_DnFIFOSEL_MBW               (0x0C00u)
+#define     USB_DnFIFOSEL_DREQE             (0x1000u)
+#define     USB_DnFIFOSEL_DCLRM             (0x2000u)
+#define     USB_DnFIFOSEL_REW               (0x4000u)
+#define     USB_DnFIFOSEL_RCNT              (0x8000u)
+
+#define     USB_DnFIFOSEL_CURPIPE_SHIFT     (0)
+/* #define  USB_DnFIFOSEL_RESERVED1_SHIFT   (4) */
+#define     USB_DnFIFOSEL_BIGEND_SHIFT      (8)
+/* #define  USB_DnFIFOSEL_RESERVED2_SHIFT   (9) */
+#define     USB_DnFIFOSEL_MBW_SHIFT         (10)
+#define     USB_DnFIFOSEL_DREQE_SHIFT       (12)
+#define     USB_DnFIFOSEL_DCLRM_SHIFT       (13)
+#define     USB_DnFIFOSEL_REW_SHIFT         (14)
+#define     USB_DnFIFOSEL_RCNT_SHIFT        (15)
+
+/*==============================================*/
+/* CFIFOCTR                                     */
+/*==============================================*/
+#define     USB_CFIFOCTR_DTLN               (0x0FFFu)
+/* #define  USB_CFIFOCTR_RESERVED           (0x1000u) */
+#define     USB_CFIFOCTR_FRDY               (0x2000u)
+#define     USB_CFIFOCTR_BCLR               (0x4000u)
+#define     USB_CFIFOCTR_BVAL               (0x8000u)
+
+#define     USB_CFIFOCTR_DTLN_SHIFT         (0)
+/* #define  USB_CFIFOCTR_RESERVED_SHIFT     (12) */
+#define     USB_CFIFOCTR_FRDY_SHIFT         (13)
+#define     USB_CFIFOCTR_BCLR_SHIFT         (14)
+#define     USB_CFIFOCTR_BVAL_SHIFT         (15)
+
+/*==============================================*/
+/* DnFIFOCTR                                    */
+/*==============================================*/
+#define     USB_DnFIFOCTR_DTLN              (0x0FFFu)
+/* #define  USB_DnFIFOCTR_RESERVED          (0x1000u) */
+#define     USB_DnFIFOCTR_FRDY              (0x2000u)
+#define     USB_DnFIFOCTR_BCLR              (0x4000u)
+#define     USB_DnFIFOCTR_BVAL              (0x8000u)
+
+#define     USB_DnFIFOCTR_DTLN_SHIFT        (0)
+/* #define  USB_DnFIFOCTR_RESERVED_SHIFT    (12) */
+#define     USB_DnFIFOCTR_FRDY_SHIFT        (13)
+#define     USB_DnFIFOCTR_BCLR_SHIFT        (14)
+#define     USB_DnFIFOCTR_BVAL_SHIFT        (15)
+
+/*==============================================*/
+/* INTENB0                                      */
+/*==============================================*/
+/* #define  USB_INTENB0_RESERVED            (0x00FFu) */
+#define     USB_INTENB0_BRDYE               (0x0100u)
+#define     USB_INTENB0_NRDYE               (0x0200u)
+#define     USB_INTENB0_BEMPE               (0x0400u)
+#define     USB_INTENB0_CTRE                (0x0800u)
+#define     USB_INTENB0_DVSE                (0x1000u)
+#define     USB_INTENB0_SOFE                (0x2000u)
+#define     USB_INTENB0_RSME                (0x4000u)
+#define     USB_INTENB0_VBSE                (0x8000u)
+
+/* #define  USB_INTENB0_RESERVED_SHIFT      (0) */
+#define     USB_INTENB0_BRDYE_SHIFT         (8)
+#define     USB_INTENB0_NRDYE_SHIFT         (9)
+#define     USB_INTENB0_BEMPE_SHIFT         (10)
+#define     USB_INTENB0_CTRE_SHIFT          (11)
+#define     USB_INTENB0_DVSE_SHIFT          (12)
+#define     USB_INTENB0_SOFE_SHIFT          (13)
+#define     USB_INTENB0_RSME_SHIFT          (14)
+#define     USB_INTENB0_VBSE_SHIFT          (15)
+
+/*==============================================*/
+/* INTENB1                                      */
+/*==============================================*/
+/* #define  USB_INTENB1_RESERVED1           (0x000Fu) */
+#define     USB_INTENB1_SACKE               (0x0010u)
+#define     USB_INTENB1_SIGNE               (0x0020u)
+#define     USB_INTENB1_EOFERRE             (0x0040u)
+/* #define  USB_INTENB1_RESERVED2           (0x0780u) */
+#define     USB_INTENB1_ATTCHE              (0x0800u)
+#define     USB_INTENB1_DTCHE               (0x1000u)
+/* #define  USB_INTENB1_RESERVED3           (0x2000u) */
+#define     USB_INTENB1_BCHGE               (0x4000u)
+/* #define  USB_INTENB1_RESERVED4           (0x8000u) */
+
+/* #define  USB_INTENB1_RESERVED1_SHIFT     (0) */
+#define     USB_INTENB1_SACKE_SHIFT         (4)
+#define     USB_INTENB1_SIGNE_SHIFT         (5)
+#define     USB_INTENB1_EOFERRE_SHIFT       (6)
+/* #define  USB_INTENB1_RESERVED2_SHIFT     (7) */
+#define     USB_INTENB1_ATTCHE_SHIFT        (11)
+#define     USB_INTENB1_DTCHE_SHIFT         (12)
+/* #define  USB_INTENB1_RESERVED3_SHIFT     (13) */
+#define     USB_INTENB1_BCHGE_SHIFT         (14)
+/* #define  USB_INTENB1_RESERVED4_SHIFT     (15) */
+
+/*==============================================*/
+/* BRDYENB                                      */
+/*==============================================*/
+#define     USB_BRDYENB                     (0xFFFFu)
+
+#define     USB_BRDYENB_SHIFT               (0)
+
+/*==============================================*/
+/* NRDYENB                                      */
+/*==============================================*/
+#define     USB_NRDYENB                     (0xFFFFu)
+
+#define     USB_NRDYENB_SHIFT               (0)
+
+/*==============================================*/
+/* BEMPENB                                      */
+/*==============================================*/
+#define     USB_BEMPENB                     (0xFFFFu)
+
+#define     USB_BEMPENB_SHIFT               (0)
+
+/*==============================================*/
+/* SOFCFG                                       */
+/*==============================================*/
+/* #define  USB_SOFCFG_RESERVED1            (0x003Fu) */
+#define     USB_SOFCFG_BRDYM                (0x0040u)
+/* #define  USB_SOFCFG_RESERVED2            (0x0080u) */
+#define     USB_SOFCFG_TRNENSEL             (0x0100u)
+/* #define  USB_SOFCFG_RESERVED3            (0xFE00u) */
+
+/* #define  USB_SOFCFG_RESERVED1_SHIFT      (0) */
+#define     USB_SOFCFG_BRDYM_SHIFT          (6)
+/* #define  USB_SOFCFG_RESERVED2_SHIFT      (7) */
+#define     USB_SOFCFG_TRNENSEL_SHIFT       (8)
+/* #define  USB_SOFCFG_RESERVED3_SHIFT      (9) */
+
+/*==============================================*/
+/* INTSTS0                                      */
+/*==============================================*/
+#define     USB_INTSTS0_CTSQ                (0x0007u)
+#define     USB_INTSTS0_VALID               (0x0008u)
+#define     USB_INTSTS0_DVSQ                (0x0070u)
+#define     USB_INTSTS0_VBSTS               (0x0080u)
+#define     USB_INTSTS0_BRDY                (0x0100u)
+#define     USB_INTSTS0_NRDY                (0x0200u)
+#define     USB_INTSTS0_BEMP                (0x0400u)
+#define     USB_INTSTS0_CTRT                (0x0800u)
+#define     USB_INTSTS0_DVST                (0x1000u)
+#define     USB_INTSTS0_SOFR                (0x2000u)
+#define     USB_INTSTS0_RESM                (0x4000u)
+#define     USB_INTSTS0_VBINT               (0x8000u)
+
+#define     USB_INTSTS0_CTSQ_SHIFT          (0)
+#define     USB_INTSTS0_VALID_SHIFT         (3)
+#define     USB_INTSTS0_DVSQ_SHIFT          (4)
+#define     USB_INTSTS0_VBSTS_SHIFT         (7)
+#define     USB_INTSTS0_BRDY_SHIFT          (8)
+#define     USB_INTSTS0_NRDY_SHIFT          (9)
+#define     USB_INTSTS0_BEMP_SHIFT          (10)
+#define     USB_INTSTS0_CTRT_SHIFT          (11)
+#define     USB_INTSTS0_DVST_SHIFT          (12)
+#define     USB_INTSTS0_SOFR_SHIFT          (13)
+#define     USB_INTSTS0_RESM_SHIFT          (14)
+#define     USB_INTSTS0_VBINT_SHIFT         (15)
+
+/*==============================================*/
+/* INTSTS1                                      */
+/*==============================================*/
+/* #define  USB_INTSTS1_RESERVED1           (0x000Fu) */
+#define     USB_INTSTS1_SACK                (0x0010u)
+#define     USB_INTSTS1_SIGN                (0x0020u)
+#define     USB_INTSTS1_EOFERR              (0x0040u)
+/* #define  USB_INTSTS1_RESERVED2           (0x0780u) */
+#define     USB_INTSTS1_ATTCH               (0x0800u)
+#define     USB_INTSTS1_DTCH                (0x1000u)
+/* #define  USB_INTSTS1_RESERVED3           (0x2000u) */
+#define     USB_INTSTS1_BCHG                (0x4000u)
+/* #define  USB_INTSTS1_RESERVED4           (0x8000u) */
+
+/* #define  USB_INTSTS1_RESERVED1_SHIFT     (0) */
+#define     USB_INTSTS1_SACK_SHIFT          (4)
+#define     USB_INTSTS1_SIGN_SHIFT          (5)
+#define     USB_INTSTS1_EOFERR_SHIFT        (6)
+/* #define  USB_INTSTS1_RESERVED2_SHIFT     (7) */
+#define     USB_INTSTS1_ATTCH_SHIFT         (11)
+#define     USB_INTSTS1_DTCH_SHIFT          (12)
+/* #define  USB_INTSTS1_RESERVED3_SHIFT     (13) */
+#define     USB_INTSTS1_BCHG_SHIFT          (14)
+/* #define  USB_INTSTS1_RESERVED4_SHIFT     (15) */
+
+/*==============================================*/
+/* BRDYSTS                                      */
+/*==============================================*/
+#define     USB_BRDYSTS                     (0xFFFFu)
+
+#define     USB_BRDYSTS_SHIFT               (0)
+
+/*==============================================*/
+/* NRDYSTS                                      */
+/*==============================================*/
+#define     USB_NRDYSTS                     (0xFFFFu)
+
+#define     USB_NRDYSTS_SHIFT               (0)
+
+/*==============================================*/
+/* BEMPSTS                                      */
+/*==============================================*/
+#define     USB_BEMPSTS                     (0xFFFFu)
+
+#define     USB_BEMPSTS_SHIFT               (0)
+
+/*==============================================*/
+/* FRMNUM                                       */
+/*==============================================*/
+#define     USB_FRMNUM_FRNM                 (0x07FFu)
+/* #define  USB_FRMNUM_RESERVED             (0x3800u) */
+#define     USB_FRMNUM_CRCE                 (0x4000u)
+#define     USB_FRMNUM_OVRN                 (0x8000u)
+
+#define     USB_FRMNUM_FRNM_SHIFT           (0)
+/* #define  USB_FRMNUM_RESERVED_SHIFT       (11) */
+#define     USB_FRMNUM_CRCE_SHIFT           (14)
+#define     USB_FRMNUM_OVRN_SHIFT           (15)
+
+/*==============================================*/
+/* UFRMNUM                                      */
+/*==============================================*/
+#define     USB_UFRMNUM_UFRNM               (0x0007u)
+/* #define  USB_UFRMNUM_RESERVED            (0xFFF8u) */
+
+#define     USB_UFRMNUM_UFRNM_SHIFT         (0)
+/* #define  USB_UFRMNUM_RESERVED_SHIFT      (3) */
+
+/*==============================================*/
+/* USBADDR                                      */
+/*==============================================*/
+#define     USB_USBADDR_USBADDR             (0x007Fu)
+/* #define  USB_USBADDR_RESERVED            (0xFF80u) */
+
+#define     USB_USBADDR_USBADDR_SHIFT       (0)
+/* #define  USB_USBADDR_RESERVED_SHIFT      (7) */
+
+/*==============================================*/
+/* USBREQ                                       */
+/*==============================================*/
+#define     USB_USBREQ_BMREQUESTTYPE        (0x00FFu)
+#define     USB_USBREQ_BREQUEST             (0xFF00u)
+
+#define     USB_USBREQ_BMREQUESTTYPE_SHIFT  (0)
+#define     USB_USBREQ_BREQUEST_SHIFT       (8)
+
+/*==============================================*/
+/* USBVAL                                       */
+/*==============================================*/
+#define     USB_USBVAL                      (0xFFFFu)
+
+#define     USB_USBVAL_SHIFT                (0)
+
+/*==============================================*/
+/* USBINDX                                      */
+/*==============================================*/
+#define     USB_USBINDX                     (0xFFFFu)
+
+#define     USB_USBINDX_SHIFT               (0)
+
+/*==============================================*/
+/* USBLENG                                      */
+/*==============================================*/
+#define     USB_USBLENG                     (0xFFFFu)
+
+#define     USB_USBLENG_SHIFT               (0)
+
+/*==============================================*/
+/* DCPCFG                                       */
+/*==============================================*/
+/* #define  USB_DCPCFG_RESERVED1            (0x000Fu) */
+#define     USB_DCPCFG_DIR                  (0x0010u)
+/* #define  USB_DCPCFG_RESERVED2            (0x0060u) */
+#define     USB_DCPCFG_SHTNAK               (0x0080u)
+#define     USB_DCPCFG_CNTMD                (0x0100u)
+/* #define  USB_DCPCFG_RESERVED3            (0xFE00u) */
+
+/* #define  USB_DCPCFG_RESERVED1_SHIFT      (0) */
+#define     USB_DCPCFG_DIR_SHIFT            (4)
+/* #define  USB_DCPCFG_RESERVED2_SHIFT      (5) */
+#define     USB_DCPCFG_SHTNK_SHIFT          (7)
+#define     USB_DCPCFG_CNTMD_SHIFT          (8)
+/* #define  USB_DCPCFG_RESERVED3            (9) */
+
+/*==============================================*/
+/* DCPMAXP                                      */
+/*==============================================*/
+#define     USB_DCPMAXP_MXPS                (0x007Fu)
+/* #define  USB_DCPMAXP_RESERVED            (0x0F80u) */
+#define     USB_DCPMAXP_DEVSEL              (0xF000u)
+
+#define     USB_DCPMAXP_MXPS_SHIFT          (0)
+/* #define  USB_DCPMAXP_RESERVED_SHIFT      (7) */
+#define     USB_DCPMAXP_DEVSEL_SHIFT        (12)
+
+/*==============================================*/
+/* DCPCTR                                       */
+/*==============================================*/
+#define     USB_DCPCTR_PID                  (0x0003u)
+#define     USB_DCPCTR_CCPL                 (0x0004u)
+/* #define  USB_DCPCTR_RESERVED1            (0x0008u) */
+#define     USB_DCPCTR_PINGE                (0x0010u)
+#define     USB_DCPCTR_PBUSY                (0x0020u)
+#define     USB_DCPCTR_SQMON                (0x0040u)
+#define     USB_DCPCTR_SQSET                (0x0080u)
+#define     USB_DCPCTR_SQCLR                (0x0100u)
+/* #define  USB_DCPCTR_RESERVED2            (0x0600u) */
+#define     USB_DCPCTR_SUREQCLR             (0x0800u)
+#define     USB_DCPCTR_CSSTS                (0x1000u)
+#define     USB_DCPCTR_CSCLR                (0x2000u)
+#define     USB_DCPCTR_SUREQ                (0x4000u)
+#define     USB_DCPCTR_BSTS                 (0x8000u)
+
+#define     USB_DCPCTR_PID_SHIFT            (0)
+#define     USB_DCPCTR_CCPL_SHIFT           (2)
+/* #define  USB_DCPCTR_RESERVED1_SHIFT      (3) */
+#define     USB_DCPCTR_PINGE_SHIFT          (4)
+#define     USB_DCPCTR_PBUSY_SHIFT          (5)
+#define     USB_DCPCTR_SQMON_SHIFT          (6)
+#define     USB_DCPCTR_SQSET_SHIFT          (7)
+#define     USB_DCPCTR_SQCLR_SHIFT          (8)
+/* #define  USB_DCPCTR_RESERVED2_SHIFT      (9) */
+#define     USB_DCPCTR_SUREQCLR_SHIFT       (11)
+#define     USB_DCPCTR_CSSTS_SHIFT          (12)
+#define     USB_DCPCTR_CSCLR_SHIFT          (13)
+#define     USB_DCPCTR_SUREQ_SHIFT          (14)
+#define     USB_DCPCTR_BSTS_SHIFT           (15)
+
+/*==============================================*/
+/* PIPESEL                                      */
+/*==============================================*/
+#define     USB_PIPESEL_PIPESEL             (0x000Fu)
+/* #define  USB_PIPESEL_RESERVED            (0xFFF0u) */
+
+#define     USB_PIPESEL_PIPESEL_SHIFT       (0)
+/* #define  USB_PIPESEL_RESERVED_SHIFT      (4) */
+
+/*==============================================*/
+/* PIPECFG                                      */
+/*==============================================*/
+#define     USB_PIPECFG_EPNUM               (0x000Fu)
+#define     USB_PIPECFG_DIR                 (0x0010u)
+/* #define  USB_PIPECFG_RESERVED1           (0x0060u) */
+#define     USB_PIPECFG_SHTNAK              (0x0080u)
+#define     USB_PIPECFG_CNTMD               (0x0100u)
+#define     USB_PIPECFG_DBLB                (0x0200u)
+#define     USB_PIPECFG_BFRE                (0x0400u)
+/* #define  USB_PIPECFG_RESERVED2           (0x3800u) */
+#define     USB_PIPECFG_TYPE                (0xC000u)
+
+#define     USB_PIPECFG_EPNUM_SHIFT         (0)
+#define     USB_PIPECFG_DIR_SHIFT           (4)
+/* #define  USB_PIPECFG_RESERVED1_SHIFT     (5) */
+#define     USB_PIPECFG_SHTNAK_SHIFT        (7)
+#define     USB_PIPECFG_CNTMD_SHIFT         (8)
+#define     USB_PIPECFG_DBLB_SHIFT          (9)
+#define     USB_PIPECFG_BFRE_SHIFT          (10)
+/* #define  USB_PIPECFG_RESERVED2_SHIFT     (11) */
+#define     USB_PIPECFG_TYPE_SHIFT          (14)
+
+/*==============================================*/
+/* PIPEBUF                                      */
+/*==============================================*/
+#define     USB_PIPEBUF_BUFNMB              (0x00FFu)
+/* #define  USB_PIPEBUF_RESERVED1           (0x0300u) */
+#define     USB_PIPEBUF_BUFSIZE             (0x7C00u)
+/* #define  USB_PIPEBUF_RESERVED2           (0x8000u) */
+
+#define     USB_PIPEBUF_BUFNMB_SHIFT        (0)
+/* #define  USB_PIPEBUF_RESERVED1_SHIFT     (8) */
+#define     USB_PIPEBUF_BUFSIZE_SHIFT       (10)
+/* #define  USB_PIPEBUF_RESERVED2_SHIFT     (15) */
+
+/*==============================================*/
+/* PIPEMAXP                                     */
+/*==============================================*/
+#define     USB_PIPEMAXP_MXPS               (0x07FFu)
+/* #define  USB_PIPEMAXP_RESERVED           (0x0800u) */
+#define     USB_PIPEMAXP_DEVSEL             (0xF000u)
+
+#define     USB_PIPEMAXP_MXPS_SHIFT         (0)
+/* #define  USB_PIPEMAXP_RESERVED_SHIFT     (11) */
+#define     USB_PIPEMAXP_DEVSEL_SHIFT       (12)
+
+/*==============================================*/
+/* PIPEPERI                                     */
+/*==============================================*/
+#define     USB_PIPEPERI_IITV               (0x0007u)
+/* #define  USB_PIPEPERI_RESERVED1          (0x0FF8u) */
+#define     USB_PIPEPERI_IFIS               (0x1000u)
+/* #define  USB_PIPEPERI_RESERVED2          (0xE000u) */
+
+#define     USB_PIPEPERI_IITV_SHIFT         (0)
+/* #define  USB_PIPEPERI_RESERVED1_SHIFT    (3) */
+#define     USB_PIPEPERI_IFIS_SHIFT         (12)
+/* #define  USB_PIPEPERI_RESERVED2_SHIFT    (13) */
+
+/*==============================================*/
+/* PIPEnCTR_1_5                                 */
+/*==============================================*/
+#define     USB_PIPEnCTR_1_5_PID                (0x0003u)
+/* #define  USB_PIPEnCTR_1_5_RESERVED1          (0x001Cu) */
+#define     USB_PIPEnCTR_1_5_PBUSY              (0x0020u)
+#define     USB_PIPEnCTR_1_5_SQMON              (0x0040u)
+#define     USB_PIPEnCTR_1_5_SQSET              (0x0080u)
+#define     USB_PIPEnCTR_1_5_SQCLR              (0x0100u)
+#define     USB_PIPEnCTR_1_5_ACLRM              (0x0200u)
+#define     USB_PIPEnCTR_1_5_ATREPM             (0x0400u)
+/* #define  USB_PIPEnCTR_1_5_RESERVED2          (0x0800u) */
+#define     USB_PIPEnCTR_1_5_CSSTS              (0x1000u)
+#define     USB_PIPEnCTR_1_5_CSCLR              (0x2000u)
+#define     USB_PIPEnCTR_1_5_INBUFM             (0x4000u)
+#define     USB_PIPEnCTR_1_5_BSTS               (0x8000u)
+
+#define     USB_PIPEnCTR_1_5_PID_SHIFT          (0)
+/* #define  USB_PIPEnCTR_1_5_RESERVED1_SHIFT    (2) */
+#define     USB_PIPEnCTR_1_5_PBUSY_SHIFT        (5)
+#define     USB_PIPEnCTR_1_5_SQMON_SHIFT        (6)
+#define     USB_PIPEnCTR_1_5_SQSET_SHIFT        (7)
+#define     USB_PIPEnCTR_1_5_SQCLR_SHIFT        (8)
+#define     USB_PIPEnCTR_1_5_ACLRM_SHIFT        (9)
+#define     USB_PIPEnCTR_1_5_ATREPM_SHIFT       (10)
+/* #define  USB_PIPEnCTR_1_5_RESERVED2_SHIFT    (11) */
+#define     USB_PIPEnCTR_1_5_CSSTS_SHIFT        (12)
+#define     USB_PIPEnCTR_1_5_CSCLR_SHIFT        (13)
+#define     USB_PIPEnCTR_1_5_INBUFM_SHIFT       (14)
+#define     USB_PIPEnCTR_1_5_BSTS_SHIFT         (15)
+
+/*==============================================*/
+/* PIPEnCTR_6_8                                 */
+/*==============================================*/
+#define     USB_PIPEnCTR_6_8_PID                (0x0003u)
+/* #define  USB_PIPEnCTR_6_8_RESERVED1          (0x001Cu) */
+#define     USB_PIPEnCTR_6_8_PBUSY              (0x0020u)
+#define     USB_PIPEnCTR_6_8_SQMON              (0x0040u)
+#define     USB_PIPEnCTR_6_8_SQSET              (0x0080u)
+#define     USB_PIPEnCTR_6_8_SQCLR              (0x0100u)
+#define     USB_PIPEnCTR_6_8_ACLRM              (0x0200u)
+/* #define  USB_PIPEnCTR_6_8_RESERVED2          (0x0C00u) */
+#define     USB_PIPEnCTR_6_8_CSSTS              (0x1000u)
+#define     USB_PIPEnCTR_6_8_CSCLR              (0x2000u)
+/* #define  USB_PIPEnCTR_6_8_RESERVED3          (0x4000u) */
+#define     USB_PIPEnCTR_6_8_BSTS               (0x8000u)
+
+#define     USB_PIPEnCTR_6_8_PID_SHIFT          (0)
+/* #define  USB_PIPEnCTR_6_8_RESERVED1_SHIFT    (2) */
+#define     USB_PIPEnCTR_6_8_PBUSY_SHIFT        (5)
+#define     USB_PIPEnCTR_6_8_SQMON_SHIFT        (6)
+#define     USB_PIPEnCTR_6_8_SQSET_SHIFT        (7)
+#define     USB_PIPEnCTR_6_8_SQCLR_SHIFT        (8)
+#define     USB_PIPEnCTR_6_8_ACLRM_SHIFT        (9)
+/* #define  USB_PIPEnCTR_6_8_RESERVED2_SHIFT    (10) */
+#define     USB_PIPEnCTR_6_8_CSSTS_SHIFT        (12)
+#define     USB_PIPEnCTR_6_8_CSCLR_SHIFT        (13)
+/* #define  USB_PIPEnCTR_6_8_RESERVED3_SHIFT    (14) */
+#define     USB_PIPEnCTR_6_8_BSTS_SHIFT         (15)
+
+/*==============================================*/
+/* PIPEnCTR_9                                   */
+/*==============================================*/
+#define     USB_PIPEnCTR_9_PID                  (0x0003u)
+/* #define  USB_PIPEnCTR_9_RESERVED1            (0x001Cu) */
+#define     USB_PIPEnCTR_9_PBUSY                (0x0020u)
+#define     USB_PIPEnCTR_9_SQMON                (0x0040u)
+#define     USB_PIPEnCTR_9_SQSET                (0x0080u)
+#define     USB_PIPEnCTR_9_SQCLR                (0x0100u)
+#define     USB_PIPEnCTR_9_ACLRM                (0x0200u)
+#define     USB_PIPEnCTR_9_ATREPM               (0x0400u)
+/* #define  USB_PIPEnCTR_9_RESERVED2            (0x0800u) */
+#define     USB_PIPEnCTR_9_CSSTS                (0x1000u)
+#define     USB_PIPEnCTR_9_CSCLR                (0x2000u)
+#define     USB_PIPEnCTR_9_INBUFM               (0x4000u)
+#define     USB_PIPEnCTR_9_BSTS                 (0x8000u)
+
+#define     USB_PIPEnCTR_9_PID_SHIFT            (0)
+/* #define  USB_PIPEnCTR_9_RESERVED1_SHIFT      (2) */
+#define     USB_PIPEnCTR_9_PBUSY_SHIFT          (5)
+#define     USB_PIPEnCTR_9_SQMON_SHIFT          (6)
+#define     USB_PIPEnCTR_9_SQSET_SHIFT          (7)
+#define     USB_PIPEnCTR_9_SQCLR_SHIFT          (8)
+#define     USB_PIPEnCTR_9_ACLRM_SHIFT          (9)
+#define     USB_PIPEnCTR_9_ATREPM_SHIFT         (10)
+/* #define  USB_PIPEnCTR_9_RESERVED2_SHIFT      (11) */
+#define     USB_PIPEnCTR_9_CSSTS_SHIFT          (12)
+#define     USB_PIPEnCTR_9_CSCLR_SHIFT          (13)
+#define     USB_PIPEnCTR_9_INBUFM_SHIFT         (14)
+#define     USB_PIPEnCTR_9_BSTS_SHIFT           (15)
+
+/*==============================================*/
+/* PIPEnCTR_A_F                                 */
+/*==============================================*/
+#define     USB_PIPEnCTR_A_F_PID                (0x0003u)
+/* #define  USB_PIPEnCTR_A_F_RESERVED1          (0x001Cu) */
+#define     USB_PIPEnCTR_A_F_PBUSY              (0x0020u)
+#define     USB_PIPEnCTR_A_F_SQMON              (0x0040u)
+#define     USB_PIPEnCTR_A_F_SQSET              (0x0080u)
+#define     USB_PIPEnCTR_A_F_SQCLR              (0x0100u)
+#define     USB_PIPEnCTR_A_F_ACLRM              (0x0200u)
+#define     USB_PIPEnCTR_A_F_ATREPM             (0x0400u)
+/* #define  USB_PIPEnCTR_A_F_RESERVED2          (0x3800u) */
+#define     USB_PIPEnCTR_A_F_INBUFM             (0x4000u)
+#define     USB_PIPEnCTR_A_F_BSTS               (0x8000u)
+
+#define     USB_PIPEnCTR_A_F_PID_SHIFT          (0)
+/* #define  USB_PIPEnCTR_A_F_RESERVED1_SHIFT    (2) */
+#define     USB_PIPEnCTR_A_F_PBUSY_SHIFT        (5)
+#define     USB_PIPEnCTR_A_F_SQMON_SHIFT        (6)
+#define     USB_PIPEnCTR_A_F_SQSET_SHIFT        (7)
+#define     USB_PIPEnCTR_A_F_SQCLR_SHIFT        (8)
+#define     USB_PIPEnCTR_A_F_ACLRM_SHIFT        (9)
+#define     USB_PIPEnCTR_A_F_ATREPM_SHIFT       (10)
+/* #define  USB_PIPEnCTR_A_F_RESERVED2_SHIFT    (11) */
+#define     USB_PIPEnCTR_A_F_INBUFM_SHIFT       (14)
+#define     USB_PIPEnCTR_A_F_BSTS_SHIFT         (15)
+
+/*==============================================*/
+/* PIPEnTRE                                     */
+/*==============================================*/
+/* #define  USB_PIPEnTRE_RESERVED1              (0x00FFu) */
+#define     USB_PIPEnTRE_TRCLR                  (0x0100u)
+#define     USB_PIPEnTRE_TRENB                  (0x0200u)
+/* #define  USB_PIPEnTRE_RESERVED2              (0xFC00u) */
+
+/* #define  USB_PIPEnTRE_RESERVED1_SHIFT        (0) */
+#define     USB_PIPEnTRE_TRCLR_SHIFT            (8)
+#define     USB_PIPEnTRE_TRENB_SHIFT            (9)
+/* #define  USB_PIPEnTRE_RESERVED2_SHIFT        (10) */
+
+/*==============================================*/
+/* PIPEnTRN                                     */
+/*==============================================*/
+#define     USB_PIPEnTRN                        (0xFFFFu)
+
+#define     USB_PIPEnTRN_SHIFT                  (0)
+
+/*==============================================*/
+/* DEVADDn                                      */
+/*==============================================*/
+/* #define  USB_DEVADDn_RESERVED1               (0x003Fu) */
+#define     USB_DEVADDn_USBSPD                  (0x00C0u)
+#define     USB_DEVADDn_HUBPORT                 (0x0700u)
+#define     USB_DEVADDn_UPPHUB                  (0x7800u)
+/* #define  USB_DEVADDn_RESERVED2               (0x8000u) */
+
+/* #define  USB_DEVADDn_RESERVED1_SHIFT         (0) */
+#define     USB_DEVADDn_USBSPD_SHIFT            (6)
+#define     USB_DEVADDn_HUBPORT_SHIFT           (8)
+#define     USB_DEVADDn_UPPHUB_SHIFT            (11)
+/* #define  USB_DEVADDn_RESERVED2_SHIFT         (15) */
+
+/*==============================================*/
+/* SUSPMODE                                     */
+/*==============================================*/
+/* #define  USB_SUSPMODE_RESERVED1              (0x3FFFu) */
+#define     USB_SUSPMODE_SUSPM                  (0x4000u)
+/* #define  USB_SUSPMODE_RESERVED2              (0x8000u) */
+
+/* #define  USB_SUSPMODE_RESERVED1_SHIFT        (0) */
+#define     USB_SUSPMODE_SUSPM_SHIFT            (14)
+/* #define  USB_SUSPMODE_RESERVED2_SHIFT        (15) */
+
+/*==============================================*/
+/* DnFIFOBm                                     */
+/*==============================================*/
+#define     USB_DnFIFOBm                        (0xFFFFu)
+
+#define     USB_DnFIFOBm_SHIFT                  (0)
+
+#endif /* USB_IOBITMASK_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefine.h	(revision 374)
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef R7S721000_IODEFINE_H
+#define R7S721000_IODEFINE_H
+
+#define H H_BYTE
+
+#include "iodefines/iodefine_typedef.h"                         /* (V2.00h) */
+
+#include "iodefines/adc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/bsc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/ceu_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/cpg_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/disc_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/dmac_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/dvdec_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/ether_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/flctl_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/gpio_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/ieb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/inb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/intc_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/irda_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/jcu_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/l2c_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/lin_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/lvds_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/mlb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/mmc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/mtu2_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/ostm_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/pfv_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/pwm_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/riic_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/romdec_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/rscan0_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/rspi_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/rtc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/scif_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/scim_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/scux_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/sdg_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/spdif_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/spibsc_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/ssif_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/usb20_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/vdc5_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/wdt_iodefine.h"                             /* (V2.00h) */
+
+#undef H
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h	(revision 374)
@@ -0,0 +1,107 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : adc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef ADC_IODEFINE_H
+#define ADC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
+
+
+#define ADCADDRA (ADC.ADDRA)
+#define ADCADDRB (ADC.ADDRB)
+#define ADCADDRC (ADC.ADDRC)
+#define ADCADDRD (ADC.ADDRD)
+#define ADCADDRE (ADC.ADDRE)
+#define ADCADDRF (ADC.ADDRF)
+#define ADCADDRG (ADC.ADDRG)
+#define ADCADDRH (ADC.ADDRH)
+#define ADCADCMPHA (ADC.ADCMPHA)
+#define ADCADCMPLA (ADC.ADCMPLA)
+#define ADCADCMPHB (ADC.ADCMPHB)
+#define ADCADCMPLB (ADC.ADCMPLB)
+#define ADCADCMPHC (ADC.ADCMPHC)
+#define ADCADCMPLC (ADC.ADCMPLC)
+#define ADCADCMPHD (ADC.ADCMPHD)
+#define ADCADCMPLD (ADC.ADCMPLD)
+#define ADCADCMPHE (ADC.ADCMPHE)
+#define ADCADCMPLE (ADC.ADCMPLE)
+#define ADCADCMPHF (ADC.ADCMPHF)
+#define ADCADCMPLF (ADC.ADCMPLF)
+#define ADCADCMPHG (ADC.ADCMPHG)
+#define ADCADCMPLG (ADC.ADCMPLG)
+#define ADCADCMPHH (ADC.ADCMPHH)
+#define ADCADCMPLH (ADC.ADCMPLH)
+#define ADCADCSR (ADC.ADCSR)
+#define ADCADCMPER (ADC.ADCMPER)
+#define ADCADCMPSR (ADC.ADCMPSR)
+
+
+typedef struct st_adc
+{
+                                                           /* ADC              */
+    volatile uint16_t ADDRA;                                  /*  ADDRA           */
+    volatile uint16_t ADDRB;                                  /*  ADDRB           */
+    volatile uint16_t ADDRC;                                  /*  ADDRC           */
+    volatile uint16_t ADDRD;                                  /*  ADDRD           */
+    volatile uint16_t ADDRE;                                  /*  ADDRE           */
+    volatile uint16_t ADDRF;                                  /*  ADDRF           */
+    volatile uint16_t ADDRG;                                  /*  ADDRG           */
+    volatile uint16_t ADDRH;                                  /*  ADDRH           */
+    volatile uint8_t   dummy32[16];                            /*                  */
+    volatile uint16_t ADCMPHA;                                /*  ADCMPHA         */
+    volatile uint16_t ADCMPLA;                                /*  ADCMPLA         */
+    volatile uint16_t ADCMPHB;                                /*  ADCMPHB         */
+    volatile uint16_t ADCMPLB;                                /*  ADCMPLB         */
+    volatile uint16_t ADCMPHC;                                /*  ADCMPHC         */
+    volatile uint16_t ADCMPLC;                                /*  ADCMPLC         */
+    volatile uint16_t ADCMPHD;                                /*  ADCMPHD         */
+    volatile uint16_t ADCMPLD;                                /*  ADCMPLD         */
+    volatile uint16_t ADCMPHE;                                /*  ADCMPHE         */
+    volatile uint16_t ADCMPLE;                                /*  ADCMPLE         */
+    volatile uint16_t ADCMPHF;                                /*  ADCMPHF         */
+    volatile uint16_t ADCMPLF;                                /*  ADCMPLF         */
+    volatile uint16_t ADCMPHG;                                /*  ADCMPHG         */
+    volatile uint16_t ADCMPLG;                                /*  ADCMPLG         */
+    volatile uint16_t ADCMPHH;                                /*  ADCMPHH         */
+    volatile uint16_t ADCMPLH;                                /*  ADCMPLH         */
+    volatile uint8_t   dummy33[32];                            /*                  */
+    volatile uint16_t ADCSR;                                  /*  ADCSR           */
+    volatile uint16_t ADCMPER;                                /*  ADCMPER         */
+    volatile uint16_t ADCMPSR;                                /*  ADCMPSR         */
+} r_io_adc_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h	(revision 374)
@@ -0,0 +1,115 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef BSC_IODEFINE_H
+#define BSC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
+
+
+#define BSCCMNCR (BSC.CMNCR)
+#define BSCCS0BCR (BSC.CS0BCR)
+#define BSCCS1BCR (BSC.CS1BCR)
+#define BSCCS2BCR (BSC.CS2BCR)
+#define BSCCS3BCR (BSC.CS3BCR)
+#define BSCCS4BCR (BSC.CS4BCR)
+#define BSCCS5BCR (BSC.CS5BCR)
+#define BSCCS0WCR (BSC.CS0WCR)
+#define BSCCS1WCR (BSC.CS1WCR)
+#define BSCCS2WCR (BSC.CS2WCR)
+#define BSCCS3WCR (BSC.CS3WCR)
+#define BSCCS4WCR (BSC.CS4WCR)
+#define BSCCS5WCR (BSC.CS5WCR)
+#define BSCSDCR (BSC.SDCR)
+#define BSCRTCSR (BSC.RTCSR)
+#define BSCRTCNT (BSC.RTCNT)
+#define BSCRTCOR (BSC.RTCOR)
+#define BSCTOSCOR0 (BSC.TOSCOR0)
+#define BSCTOSCOR1 (BSC.TOSCOR1)
+#define BSCTOSCOR2 (BSC.TOSCOR2)
+#define BSCTOSCOR3 (BSC.TOSCOR3)
+#define BSCTOSCOR4 (BSC.TOSCOR4)
+#define BSCTOSCOR5 (BSC.TOSCOR5)
+#define BSCTOSTR (BSC.TOSTR)
+#define BSCTOENR (BSC.TOENR)
+
+#define BSC_CSnBCR_COUNT (6)
+#define BSC_CSnWCR_COUNT (6)
+#define BSC_TOSCORn_COUNT (6)
+
+
+typedef struct st_bsc
+{
+                                                           /* BSC              */
+    volatile uint32_t  CMNCR;                                  /*  CMNCR           */
+
+/* #define BSC_CSnBCR_COUNT (6) */
+    volatile uint32_t  CS0BCR;                                 /*  CS0BCR          */
+    volatile uint32_t  CS1BCR;                                 /*  CS1BCR          */
+    volatile uint32_t  CS2BCR;                                 /*  CS2BCR          */
+    volatile uint32_t  CS3BCR;                                 /*  CS3BCR          */
+    volatile uint32_t  CS4BCR;                                 /*  CS4BCR          */
+    volatile uint32_t  CS5BCR;                                 /*  CS5BCR          */
+    volatile uint8_t   dummy4[12];                             /*                  */
+
+/* #define BSC_CSnWCR_COUNT (6) */
+    volatile uint32_t  CS0WCR;                                 /*  CS0WCR          */
+    volatile uint32_t  CS1WCR;                                 /*  CS1WCR          */
+    volatile uint32_t  CS2WCR;                                 /*  CS2WCR          */
+    volatile uint32_t  CS3WCR;                                 /*  CS3WCR          */
+    volatile uint32_t  CS4WCR;                                 /*  CS4WCR          */
+    volatile uint32_t  CS5WCR;                                 /*  CS5WCR          */
+    volatile uint8_t   dummy5[12];                             /*                  */
+    volatile uint32_t  SDCR;                                   /*  SDCR            */
+    volatile uint32_t  RTCSR;                                  /*  RTCSR           */
+    volatile uint32_t  RTCNT;                                  /*  RTCNT           */
+    volatile uint32_t  RTCOR;                                  /*  RTCOR           */
+    volatile uint8_t   dummy6[4];                              /*                  */
+
+/* #define BSC_TOSCORn_COUNT (6) */
+    volatile uint32_t  TOSCOR0;                                /*  TOSCOR0         */
+    volatile uint32_t  TOSCOR1;                                /*  TOSCOR1         */
+    volatile uint32_t  TOSCOR2;                                /*  TOSCOR2         */
+    volatile uint32_t  TOSCOR3;                                /*  TOSCOR3         */
+    volatile uint32_t  TOSCOR4;                                /*  TOSCOR4         */
+    volatile uint32_t  TOSCOR5;                                /*  TOSCOR5         */
+    volatile uint8_t   dummy7[8];                              /*                  */
+    volatile uint32_t  TOSTR;                                  /*  TOSTR           */
+    volatile uint32_t  TOENR;                                  /*  TOENR           */
+} r_io_bsc_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h	(revision 374)
@@ -0,0 +1,295 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ceu_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef CEU_IODEFINE_H
+#define CEU_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
+
+
+/* Start of channel array defines of CEU */
+
+/* Channel array defines of CEUn */
+/*(Sample) value = CEUn[ channel ]->CAMOR; */
+#define CEUn_COUNT  (3)
+#define CEUn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    (volatile struct st_ceu_n*)&CEU_A, \
+    (volatile struct st_ceu_n*)&CEU_B, \
+    (volatile struct st_ceu_n*)&CEU_M \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
+#define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
+#define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
+
+/* End of channel array defines of CEU */
+
+
+#define CEUCAPSR (CEU.CAPSR)
+#define CEUCAPCR (CEU.CAPCR)
+#define CEUCAMCR (CEU.CAMCR)
+#define CEUCMCYR (CEU.CMCYR)
+#define CEUCAMOR_A (CEU.CAMOR_A)
+#define CEUCAPWR_A (CEU.CAPWR_A)
+#define CEUCAIFR (CEU.CAIFR)
+#define CEUCRCNTR (CEU.CRCNTR)
+#define CEUCRCMPR (CEU.CRCMPR)
+#define CEUCFLCR_A (CEU.CFLCR_A)
+#define CEUCFSZR_A (CEU.CFSZR_A)
+#define CEUCDWDR_A (CEU.CDWDR_A)
+#define CEUCDAYR_A (CEU.CDAYR_A)
+#define CEUCDACR_A (CEU.CDACR_A)
+#define CEUCDBYR_A (CEU.CDBYR_A)
+#define CEUCDBCR_A (CEU.CDBCR_A)
+#define CEUCBDSR_A (CEU.CBDSR_A)
+#define CEUCFWCR (CEU.CFWCR)
+#define CEUCLFCR_A (CEU.CLFCR_A)
+#define CEUCDOCR_A (CEU.CDOCR_A)
+#define CEUCEIER (CEU.CEIER)
+#define CEUCETCR (CEU.CETCR)
+#define CEUCSTSR (CEU.CSTSR)
+#define CEUCDSSR (CEU.CDSSR)
+#define CEUCDAYR2_A (CEU.CDAYR2_A)
+#define CEUCDACR2_A (CEU.CDACR2_A)
+#define CEUCDBYR2_A (CEU.CDBYR2_A)
+#define CEUCDBCR2_A (CEU.CDBCR2_A)
+#define CEUCAMOR_B (CEU.CAMOR_B)
+#define CEUCAPWR_B (CEU.CAPWR_B)
+#define CEUCFLCR_B (CEU.CFLCR_B)
+#define CEUCFSZR_B (CEU.CFSZR_B)
+#define CEUCDWDR_B (CEU.CDWDR_B)
+#define CEUCDAYR_B (CEU.CDAYR_B)
+#define CEUCDACR_B (CEU.CDACR_B)
+#define CEUCDBYR_B (CEU.CDBYR_B)
+#define CEUCDBCR_B (CEU.CDBCR_B)
+#define CEUCBDSR_B (CEU.CBDSR_B)
+#define CEUCLFCR_B (CEU.CLFCR_B)
+#define CEUCDOCR_B (CEU.CDOCR_B)
+#define CEUCDAYR2_B (CEU.CDAYR2_B)
+#define CEUCDACR2_B (CEU.CDACR2_B)
+#define CEUCDBYR2_B (CEU.CDBYR2_B)
+#define CEUCDBCR2_B (CEU.CDBCR2_B)
+#define CEUCAMOR_M (CEU.CAMOR_M)
+#define CEUCAPWR_M (CEU.CAPWR_M)
+#define CEUCFLCR_M (CEU.CFLCR_M)
+#define CEUCFSZR_M (CEU.CFSZR_M)
+#define CEUCDWDR_M (CEU.CDWDR_M)
+#define CEUCDAYR_M (CEU.CDAYR_M)
+#define CEUCDACR_M (CEU.CDACR_M)
+#define CEUCDBYR_M (CEU.CDBYR_M)
+#define CEUCDBCR_M (CEU.CDBCR_M)
+#define CEUCBDSR_M (CEU.CBDSR_M)
+#define CEUCLFCR_M (CEU.CLFCR_M)
+#define CEUCDOCR_M (CEU.CDOCR_M)
+#define CEUCDAYR2_M (CEU.CDAYR2_M)
+#define CEUCDACR2_M (CEU.CDACR2_M)
+#define CEUCDBYR2_M (CEU.CDBYR2_M)
+#define CEUCDBCR2_M (CEU.CDBCR2_M)
+
+
+typedef struct st_ceu
+{
+                                                           /* CEU              */
+
+/* start of struct st_ceu_n */
+    volatile uint32_t  CAPSR;                                  /*  CAPSR           */
+    volatile uint32_t  CAPCR;                                  /*  CAPCR           */
+    volatile uint32_t  CAMCR;                                  /*  CAMCR           */
+    volatile uint32_t  CMCYR;                                  /*  CMCYR           */
+    volatile uint32_t  CAMOR_A;                                /*  CAMOR_A         */
+    volatile uint32_t  CAPWR_A;                                /*  CAPWR_A         */
+    volatile uint32_t  CAIFR;                                  /*  CAIFR           */
+    volatile uint8_t   dummy305[12];                           /*                  */
+    volatile uint32_t  CRCNTR;                                 /*  CRCNTR          */
+    volatile uint32_t  CRCMPR;                                 /*  CRCMPR          */
+    volatile uint32_t  CFLCR_A;                                /*  CFLCR_A         */
+    volatile uint32_t  CFSZR_A;                                /*  CFSZR_A         */
+    volatile uint32_t  CDWDR_A;                                /*  CDWDR_A         */
+    volatile uint32_t  CDAYR_A;                                /*  CDAYR_A         */
+    volatile uint32_t  CDACR_A;                                /*  CDACR_A         */
+    volatile uint32_t  CDBYR_A;                                /*  CDBYR_A         */
+    volatile uint32_t  CDBCR_A;                                /*  CDBCR_A         */
+    volatile uint32_t  CBDSR_A;                                /*  CBDSR_A         */
+    volatile uint8_t   dummy306[12];                           /*                  */
+    volatile uint32_t  CFWCR;                                  /*  CFWCR           */
+    volatile uint32_t  CLFCR_A;                                /*  CLFCR_A         */
+    volatile uint32_t  CDOCR_A;                                /*  CDOCR_A         */
+    volatile uint8_t   dummy307[8];                            /*                  */
+    volatile uint32_t  CEIER;                                  /*  CEIER           */
+    volatile uint32_t  CETCR;                                  /*  CETCR           */
+    volatile uint8_t   dummy308[4];                            /*                  */
+    volatile uint32_t  CSTSR;                                  /*  CSTSR           */
+    volatile uint8_t   dummy309[4];                            /*                  */
+    volatile uint32_t  CDSSR;                                  /*  CDSSR           */
+    volatile uint8_t   dummy310[8];                            /*                  */
+    volatile uint32_t  CDAYR2_A;                               /*  CDAYR2_A        */
+    volatile uint32_t  CDACR2_A;                               /*  CDACR2_A        */
+    volatile uint32_t  CDBYR2_A;                               /*  CDBYR2_A        */
+    volatile uint32_t  CDBCR2_A;                               /*  CDBCR2_A        */
+
+/* end of struct st_ceu_n */
+    volatile uint8_t   dummy3110[3936];                        /*                  */
+
+/* start of struct st_ceu_n */
+    volatile uint8_t   dummy3111[4];                           /*                  */
+    volatile uint8_t   dummy3112[4];                           /*                  */
+    volatile uint8_t   dummy3113[4];                           /*                  */
+    volatile uint8_t   dummy3114[4];                           /*                  */
+    volatile uint32_t  CAMOR_B;                                /*  CAMOR_B         */
+    volatile uint32_t  CAPWR_B;                                /*  CAPWR_B         */
+    volatile uint8_t   dummy3120[4];                           /*                  */
+    volatile uint8_t   dummy3121[12];                          /*                  */
+    volatile uint8_t   dummy3122[4];                           /*                  */
+    volatile uint8_t   dummy3123[4];                           /*                  */
+    volatile uint32_t  CFLCR_B;                                /*  CFLCR_B         */
+    volatile uint32_t  CFSZR_B;                                /*  CFSZR_B         */
+    volatile uint32_t  CDWDR_B;                                /*  CDWDR_B         */
+    volatile uint32_t  CDAYR_B;                                /*  CDAYR_B         */
+    volatile uint32_t  CDACR_B;                                /*  CDACR_B         */
+    volatile uint32_t  CDBYR_B;                                /*  CDBYR_B         */
+    volatile uint32_t  CDBCR_B;                                /*  CDBCR_B         */
+    volatile uint32_t  CBDSR_B;                                /*  CBDSR_B         */
+    volatile uint8_t   dummy3130[12];                          /*                  */
+    volatile uint8_t   dummy3131[4];                           /*                  */
+    volatile uint32_t  CLFCR_B;                                /*  CLFCR_B         */
+    volatile uint32_t  CDOCR_B;                                /*  CDOCR_B         */
+    volatile uint8_t   dummy3140[8];                           /*                  */
+    volatile uint8_t   dummy3141[4];                           /*                  */
+    volatile uint8_t   dummy3142[4];                           /*                  */
+    volatile uint8_t   dummy3143[4];                           /*                  */
+    volatile uint8_t   dummy3144[4];                           /*                  */
+    volatile uint8_t   dummy3145[4];                           /*                  */
+    volatile uint8_t   dummy3146[4];                           /*                  */
+    volatile uint8_t   dummy3147[8];                           /*                  */
+    volatile uint32_t  CDAYR2_B;                               /*  CDAYR2_B        */
+    volatile uint32_t  CDACR2_B;                               /*  CDACR2_B        */
+    volatile uint32_t  CDBYR2_B;                               /*  CDBYR2_B        */
+    volatile uint32_t  CDBCR2_B;                               /*  CDBCR2_B        */
+
+/* end of struct st_ceu_n */
+    volatile uint8_t   dummy3150[3936];                        /*                  */
+
+/* start of struct st_ceu_n */
+    volatile uint8_t   dummy3151[4];                           /*                  */
+    volatile uint8_t   dummy3152[4];                           /*                  */
+    volatile uint8_t   dummy3153[4];                           /*                  */
+    volatile uint8_t   dummy3154[4];                           /*                  */
+    volatile uint32_t  CAMOR_M;                                /*  CAMOR_M         */
+    volatile uint32_t  CAPWR_M;                                /*  CAPWR_M         */
+    volatile uint8_t   dummy3160[4];                           /*                  */
+    volatile uint8_t   dummy3161[12];                          /*                  */
+    volatile uint8_t   dummy3162[4];                           /*                  */
+    volatile uint8_t   dummy3163[4];                           /*                  */
+    volatile uint32_t  CFLCR_M;                                /*  CFLCR_M         */
+    volatile uint32_t  CFSZR_M;                                /*  CFSZR_M         */
+    volatile uint32_t  CDWDR_M;                                /*  CDWDR_M         */
+    volatile uint32_t  CDAYR_M;                                /*  CDAYR_M         */
+    volatile uint32_t  CDACR_M;                                /*  CDACR_M         */
+    volatile uint32_t  CDBYR_M;                                /*  CDBYR_M         */
+    volatile uint32_t  CDBCR_M;                                /*  CDBCR_M         */
+    volatile uint32_t  CBDSR_M;                                /*  CBDSR_M         */
+    volatile uint8_t   dummy3170[12];                          /*                  */
+    volatile uint8_t   dummy3171[4];                           /*                  */
+    volatile uint32_t  CLFCR_M;                                /*  CLFCR_M         */
+    volatile uint32_t  CDOCR_M;                                /*  CDOCR_M         */
+    volatile uint8_t   dummy3180[8];                           /*                  */
+    volatile uint8_t   dummy3181[4];                           /*                  */
+    volatile uint8_t   dummy3182[4];                           /*                  */
+    volatile uint8_t   dummy3183[4];                           /*                  */
+    volatile uint8_t   dummy3184[4];                           /*                  */
+    volatile uint8_t   dummy3185[4];                           /*                  */
+    volatile uint8_t   dummy3186[4];                           /*                  */
+    volatile uint8_t   dummy3187[8];                           /*                  */
+    volatile uint32_t  CDAYR2_M;                               /*  CDAYR2_M        */
+    volatile uint32_t  CDACR2_M;                               /*  CDACR2_M        */
+    volatile uint32_t  CDBYR2_M;                               /*  CDBYR2_M        */
+    volatile uint32_t  CDBCR2_M;                               /*  CDBCR2_M        */
+
+/* end of struct st_ceu_n */
+} r_io_ceu_t;
+
+
+typedef struct st_ceu_n
+{
+ 
+    volatile uint32_t  not_common1;                            /*                  */
+    volatile uint32_t  not_common2;                            /*                  */
+    volatile uint32_t  not_common3;                            /*                  */
+    volatile uint32_t  not_common4;                            /*                  */
+    volatile uint32_t  CAMOR;                                  /*  CAMOR           */
+    volatile uint32_t  CAPWR;                                  /*  CAPWR           */
+    volatile uint32_t  not_common5;                            /*                  */
+    volatile uint8_t   dummy322[12];                           /*                  */
+    volatile uint32_t  not_common6;                            /*                  */
+    volatile uint32_t  not_common7;                            /*                  */
+    volatile uint32_t  CFLCR;                                  /*  CFLCR           */
+    volatile uint32_t  CFSZR;                                  /*  CFSZR           */
+    volatile uint32_t  CDWDR;                                  /*  CDWDR           */
+    volatile uint32_t  CDAYR;                                  /*  CDAYR           */
+    volatile uint32_t  CDACR;                                  /*  CDACR           */
+    volatile uint32_t  CDBYR;                                  /*  CDBYR           */
+    volatile uint32_t  CDBCR;                                  /*  CDBCR           */
+    volatile uint32_t  CBDSR;                                  /*  CBDSR           */
+    volatile uint8_t   dummy323[12];                           /*                  */
+    volatile uint32_t  not_common8;                            /*                  */
+    volatile uint32_t  CLFCR;                                  /*  CLFCR           */
+    volatile uint32_t  CDOCR;                                  /*  CDOCR           */
+    volatile uint8_t   dummy324[8];                            /*                  */
+    volatile uint32_t  not_common9;                            /*                  */
+    volatile uint32_t  not_common10;                           /*                  */
+    volatile uint8_t   dummy325[4];                            /*                  */
+    volatile uint32_t  not_common11;                           /*                  */
+    volatile uint8_t   dummy326[4];                            /*                  */
+    volatile uint32_t  not_common12;                           /*                  */
+    volatile uint8_t   dummy327[8];                            /*                  */
+    volatile uint32_t  CDAYR2;                                 /*  CDAYR2          */
+    volatile uint32_t  CDACR2;                                 /*  CDACR2          */
+    volatile uint32_t  CDBYR2;                                 /*  CDBYR2          */
+    volatile uint32_t  CDBCR2;                                 /*  CDBCR2          */
+} r_io_ceu_n_t;
+
+
+/* Channel array defines of CEUn (2)*/
+#ifdef  DECLARE_CEUn_CHANNELS
+volatile struct st_ceu_n*  CEUn[ CEUn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CEUn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CEUn_CHANNELS */
+/* End of channel array defines of CEUn (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h	(revision 374)
@@ -0,0 +1,307 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : cpg_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef CPG_IODEFINE_H
+#define CPG_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
+
+
+/* Start of channel array defines of CPG */
+
+/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
+#define CPG_FROM_SWRSTCR1_ARRAY_COUNT  (3)
+#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
+#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
+#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+
+
+/* Channel array defines of CPG_FROM_STBCR3_ARRAY */
+/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
+#define CPG_FROM_STBCR3_ARRAY_COUNT  (10)
+#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
+    &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
+#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
+#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
+#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
+#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
+#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
+#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
+#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
+#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
+#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+
+
+/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
+#define CPG_FROM_SYSCR1_ARRAY_COUNT  (3)
+#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
+#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
+#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
+
+/* End of channel array defines of CPG */
+
+
+#define CPGFRQCR (CPG.FRQCR)
+#define CPGFRQCR2 (CPG.FRQCR2)
+#define CPGCPUSTS (CPG.CPUSTS)
+#define CPGSTBCR1 (CPG.STBCR1)
+#define CPGSTBCR2 (CPG.STBCR2)
+#define CPGSTBREQ1 (CPG.STBREQ1)
+#define CPGSTBREQ2 (CPG.STBREQ2)
+#define CPGSTBACK1 (CPG.STBACK1)
+#define CPGSTBACK2 (CPG.STBACK2)
+#define CPGSYSCR1 (CPG.SYSCR1)
+#define CPGSYSCR2 (CPG.SYSCR2)
+#define CPGSYSCR3 (CPG.SYSCR3)
+#define CPGSTBCR3 (CPG.STBCR3)
+#define CPGSTBCR4 (CPG.STBCR4)
+#define CPGSTBCR5 (CPG.STBCR5)
+#define CPGSTBCR6 (CPG.STBCR6)
+#define CPGSTBCR7 (CPG.STBCR7)
+#define CPGSTBCR8 (CPG.STBCR8)
+#define CPGSTBCR9 (CPG.STBCR9)
+#define CPGSTBCR10 (CPG.STBCR10)
+#define CPGSTBCR11 (CPG.STBCR11)
+#define CPGSTBCR12 (CPG.STBCR12)
+#define CPGSWRSTCR1 (CPG.SWRSTCR1)
+#define CPGSWRSTCR2 (CPG.SWRSTCR2)
+#define CPGSWRSTCR3 (CPG.SWRSTCR3)
+#define CPGSTBCR13 (CPG.STBCR13)
+#define CPGRRAMKP (CPG.RRAMKP)
+#define CPGDSCTR (CPG.DSCTR)
+#define CPGDSSSR (CPG.DSSSR)
+#define CPGDSESR (CPG.DSESR)
+#define CPGDSFR (CPG.DSFR)
+#define CPGXTALCTR (CPG.XTALCTR)
+
+
+typedef struct st_cpg
+{
+                                                           /* CPG              */
+    volatile uint16_t FRQCR;                                  /*  FRQCR           */
+    volatile uint8_t   dummy319[2];                            /*                  */
+    volatile uint16_t FRQCR2;                                 /*  FRQCR2          */
+    volatile uint8_t   dummy320[2];                            /*                  */
+    volatile uint8_t   CPUSTS;                                 /*  CPUSTS          */
+    volatile uint8_t   dummy321[7];                            /*                  */
+    volatile uint8_t   STBCR1;                                 /*  STBCR1          */
+    volatile uint8_t   dummy322[3];                            /*                  */
+    volatile uint8_t   STBCR2;                                 /*  STBCR2          */
+    volatile uint8_t   dummy323[11];                           /*                  */
+    volatile uint8_t   STBREQ1;                                /*  STBREQ1         */
+    volatile uint8_t   dummy324[3];                            /*                  */
+    volatile uint8_t   STBREQ2;                                /*  STBREQ2         */
+    volatile uint8_t   dummy325[11];                           /*                  */
+    volatile uint8_t   STBACK1;                                /*  STBACK1         */
+    volatile uint8_t   dummy326[3];                            /*                  */
+    volatile uint8_t   STBACK2;                                /*  STBACK2         */
+    volatile uint8_t   dummy327[955];                          /*                  */
+
+/* start of struct st_cpg_from_syscr1 */
+    volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
+    volatile uint8_t   dummy328[3];                            /*                  */
+
+/* end of struct st_cpg_from_syscr1 */
+
+/* start of struct st_cpg_from_syscr1 */
+    volatile uint8_t   SYSCR2;                                 /*  SYSCR2          */
+    volatile uint8_t   dummy329[3];                            /*                  */
+
+/* end of struct st_cpg_from_syscr1 */
+
+/* start of struct st_cpg_from_syscr1 */
+    volatile uint8_t   SYSCR3;                                 /*  SYSCR3          */
+    volatile uint8_t   dummy3300[3];                           /*                  */
+
+/* end of struct st_cpg_from_syscr1 */
+    volatile uint8_t   dummy3301[20];                          /*                  */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
+    volatile uint8_t   dummy331[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR4;                                 /*  STBCR4          */
+    volatile uint8_t   dummy332[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR5;                                 /*  STBCR5          */
+    volatile uint8_t   dummy333[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR6;                                 /*  STBCR6          */
+    volatile uint8_t   dummy334[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR7;                                 /*  STBCR7          */
+    volatile uint8_t   dummy335[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR8;                                 /*  STBCR8          */
+    volatile uint8_t   dummy336[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR9;                                 /*  STBCR9          */
+    volatile uint8_t   dummy337[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR10;                                /*  STBCR10         */
+    volatile uint8_t   dummy338[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR11;                                /*  STBCR11         */
+    volatile uint8_t   dummy339[3];                            /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR12;                                /*  STBCR12         */
+    volatile uint8_t   dummy3400[3];                           /*                  */
+
+/* end of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   dummy3401[24];                          /*                  */
+
+/* start of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+    volatile uint8_t   dummy341[3];                            /*                  */
+
+/* end of struct st_cpg_from_swrstcr1 */
+
+/* start of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   SWRSTCR2;                               /*  SWRSTCR2        */
+    volatile uint8_t   dummy342[3];                            /*                  */
+
+/* end of struct st_cpg_from_swrstcr1 */
+
+/* start of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   SWRSTCR3;                               /*  SWRSTCR3        */
+    volatile uint8_t   dummy3430[3];                           /*                  */
+
+/* end of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   dummy3431[4];                           /*                  */
+    volatile uint8_t   STBCR13;                                /*  STBCR13         */
+    volatile uint8_t   dummy344[70543];                        /*                  */
+    volatile uint8_t   RRAMKP;                                 /*  RRAMKP          */
+    volatile uint8_t   dummy345[1];                            /*                  */
+    volatile uint8_t   DSCTR;                                  /*  DSCTR           */
+    volatile uint8_t   dummy346[1];                            /*                  */
+    volatile uint16_t DSSSR;                                  /*  DSSSR           */
+    volatile uint16_t DSESR;                                  /*  DSESR           */
+    volatile uint16_t DSFR;                                   /*  DSFR            */
+    volatile uint8_t   dummy347[6];                            /*                  */
+    volatile uint8_t   XTALCTR;                                /*  XTALCTR         */
+} r_io_cpg_t;
+
+
+typedef struct st_cpg_from_syscr1
+{
+ 
+    volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_cpg_from_syscr1_t;
+
+
+typedef struct st_cpg_from_stbcr3
+{
+ 
+    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_cpg_from_stbcr3_t;
+
+
+typedef struct st_cpg_from_swrstcr1
+{
+ 
+    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_cpg_from_swrstcr1_t;
+
+
+/* Channel array defines of CPG (2)*/
+#ifdef  DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS
+volatile struct st_cpg_from_swrstcr1*  CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS
+volatile struct st_cpg_from_stbcr3*  CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS
+volatile struct st_cpg_from_syscr1*  CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */
+/* End of channel array defines of CPG (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h	(revision 374)
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : disc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef DISC_IODEFINE_H
+#define DISC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
+#define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
+
+
+/* Start of channel array defines of DISC */
+
+/* Channel array defines of DISC */
+/*(Sample) value = DISC[ channel ]->DOCMCR; */
+#define DISC_COUNT  (2)
+#define DISC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DISC0, &DISC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of DISC */
+
+
+#define DISC0DOCMCR (DISC0.DOCMCR)
+#define DISC0DOCMSTR (DISC0.DOCMSTR)
+#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR)
+#define DISC0DOCMIENR (DISC0.DOCMIENR)
+#define DISC0DOCMPMR (DISC0.DOCMPMR)
+#define DISC0DOCMECRCR (DISC0.DOCMECRCR)
+#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR)
+#define DISC0DOCMSPXR (DISC0.DOCMSPXR)
+#define DISC0DOCMSPYR (DISC0.DOCMSPYR)
+#define DISC0DOCMSZXR (DISC0.DOCMSZXR)
+#define DISC0DOCMSZYR (DISC0.DOCMSZYR)
+#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR)
+#define DISC1DOCMCR (DISC1.DOCMCR)
+#define DISC1DOCMSTR (DISC1.DOCMSTR)
+#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR)
+#define DISC1DOCMIENR (DISC1.DOCMIENR)
+#define DISC1DOCMPMR (DISC1.DOCMPMR)
+#define DISC1DOCMECRCR (DISC1.DOCMECRCR)
+#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR)
+#define DISC1DOCMSPXR (DISC1.DOCMSPXR)
+#define DISC1DOCMSPYR (DISC1.DOCMSPYR)
+#define DISC1DOCMSZXR (DISC1.DOCMSZXR)
+#define DISC1DOCMSZYR (DISC1.DOCMSZYR)
+#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR)
+
+
+typedef struct st_disc
+{
+                                                           /* DISC             */
+    volatile uint32_t  DOCMCR;                                 /*  DOCMCR          */
+    volatile uint32_t  DOCMSTR;                                /*  DOCMSTR         */
+    volatile uint32_t  DOCMCLSTR;                              /*  DOCMCLSTR       */
+    volatile uint32_t  DOCMIENR;                               /*  DOCMIENR        */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  DOCMPMR;                                /*  DOCMPMR         */
+    volatile uint32_t  DOCMECRCR;                              /*  DOCMECRCR       */
+    volatile uint32_t  DOCMCCRCR;                              /*  DOCMCCRCR       */
+    volatile uint32_t  DOCMSPXR;                               /*  DOCMSPXR        */
+    volatile uint32_t  DOCMSPYR;                               /*  DOCMSPYR        */
+    volatile uint32_t  DOCMSZXR;                               /*  DOCMSZXR        */
+    volatile uint32_t  DOCMSZYR;                               /*  DOCMSZYR        */
+    volatile uint32_t  DOCMCRCIR;                              /*  DOCMCRCIR       */
+} r_io_disc_t;
+
+
+/* Channel array defines of DISC (2)*/
+#ifdef  DECLARE_DISC_CHANNELS
+volatile struct st_disc*  DISC[ DISC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DISC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DISC_CHANNELS */
+/* End of channel array defines of DISC (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h	(revision 374)
@@ -0,0 +1,807 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dmac_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef DMAC_IODEFINE_H
+#define DMAC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+
+
+/* Channel array defines of DMACmm */
+#define DMACmm_COUNT  (8)
+#define DMACmm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
+#define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
+#define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
+#define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
+#define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
+#define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
+#define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
+#define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
+
+
+/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
+#define DMAC    (*(struct st_dmac    *)0xE8200000uL) /* DMAC */
+
+
+/* Start of channel array defines of DMAC */
+
+/* Channel array defines of DMACn */
+/*(Sample) value = DMACn[ channel ]->N0SA_n; */
+#define DMACn_COUNT  (16)
+#define DMACn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
+    &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC0   (*(struct st_dmac_n *)&DMAC.N0SA_0)              /* DMAC0 */
+#define DMAC1   (*(struct st_dmac_n *)&DMAC.N0SA_1)              /* DMAC1 */
+#define DMAC2   (*(struct st_dmac_n *)&DMAC.N0SA_2)              /* DMAC2 */
+#define DMAC3   (*(struct st_dmac_n *)&DMAC.N0SA_3)              /* DMAC3 */
+#define DMAC4   (*(struct st_dmac_n *)&DMAC.N0SA_4)              /* DMAC4 */
+#define DMAC5   (*(struct st_dmac_n *)&DMAC.N0SA_5)              /* DMAC5 */
+#define DMAC6   (*(struct st_dmac_n *)&DMAC.N0SA_6)              /* DMAC6 */
+#define DMAC7   (*(struct st_dmac_n *)&DMAC.N0SA_7)              /* DMAC7 */
+#define DMAC8   (*(struct st_dmac_n *)&DMAC.N0SA_8)              /* DMAC8 */
+#define DMAC9   (*(struct st_dmac_n *)&DMAC.N0SA_9)              /* DMAC9 */
+#define DMAC10  (*(struct st_dmac_n *)&DMAC.N0SA_10)             /* DMAC10 */
+#define DMAC11  (*(struct st_dmac_n *)&DMAC.N0SA_11)             /* DMAC11 */
+#define DMAC12  (*(struct st_dmac_n *)&DMAC.N0SA_12)             /* DMAC12 */
+#define DMAC13  (*(struct st_dmac_n *)&DMAC.N0SA_13)             /* DMAC13 */
+#define DMAC14  (*(struct st_dmac_n *)&DMAC.N0SA_14)             /* DMAC14 */
+#define DMAC15  (*(struct st_dmac_n *)&DMAC.N0SA_15)             /* DMAC15 */
+
+
+/* Channel array defines of DMACnn */
+/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
+#define DMACnn_COUNT  (2)
+#define DMACnn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC07, &DMAC815 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC07  (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7)     /* DMAC07 */
+#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15)    /* DMAC815 */
+
+/* End of channel array defines of DMAC */
+
+
+#define DMACN0SA_0 (DMAC.N0SA_0)
+#define DMACN0DA_0 (DMAC.N0DA_0)
+#define DMACN0TB_0 (DMAC.N0TB_0)
+#define DMACN1SA_0 (DMAC.N1SA_0)
+#define DMACN1DA_0 (DMAC.N1DA_0)
+#define DMACN1TB_0 (DMAC.N1TB_0)
+#define DMACCRSA_0 (DMAC.CRSA_0)
+#define DMACCRDA_0 (DMAC.CRDA_0)
+#define DMACCRTB_0 (DMAC.CRTB_0)
+#define DMACCHSTAT_0 (DMAC.CHSTAT_0)
+#define DMACCHCTRL_0 (DMAC.CHCTRL_0)
+#define DMACCHCFG_0 (DMAC.CHCFG_0)
+#define DMACCHITVL_0 (DMAC.CHITVL_0)
+#define DMACCHEXT_0 (DMAC.CHEXT_0)
+#define DMACNXLA_0 (DMAC.NXLA_0)
+#define DMACCRLA_0 (DMAC.CRLA_0)
+#define DMACN0SA_1 (DMAC.N0SA_1)
+#define DMACN0DA_1 (DMAC.N0DA_1)
+#define DMACN0TB_1 (DMAC.N0TB_1)
+#define DMACN1SA_1 (DMAC.N1SA_1)
+#define DMACN1DA_1 (DMAC.N1DA_1)
+#define DMACN1TB_1 (DMAC.N1TB_1)
+#define DMACCRSA_1 (DMAC.CRSA_1)
+#define DMACCRDA_1 (DMAC.CRDA_1)
+#define DMACCRTB_1 (DMAC.CRTB_1)
+#define DMACCHSTAT_1 (DMAC.CHSTAT_1)
+#define DMACCHCTRL_1 (DMAC.CHCTRL_1)
+#define DMACCHCFG_1 (DMAC.CHCFG_1)
+#define DMACCHITVL_1 (DMAC.CHITVL_1)
+#define DMACCHEXT_1 (DMAC.CHEXT_1)
+#define DMACNXLA_1 (DMAC.NXLA_1)
+#define DMACCRLA_1 (DMAC.CRLA_1)
+#define DMACN0SA_2 (DMAC.N0SA_2)
+#define DMACN0DA_2 (DMAC.N0DA_2)
+#define DMACN0TB_2 (DMAC.N0TB_2)
+#define DMACN1SA_2 (DMAC.N1SA_2)
+#define DMACN1DA_2 (DMAC.N1DA_2)
+#define DMACN1TB_2 (DMAC.N1TB_2)
+#define DMACCRSA_2 (DMAC.CRSA_2)
+#define DMACCRDA_2 (DMAC.CRDA_2)
+#define DMACCRTB_2 (DMAC.CRTB_2)
+#define DMACCHSTAT_2 (DMAC.CHSTAT_2)
+#define DMACCHCTRL_2 (DMAC.CHCTRL_2)
+#define DMACCHCFG_2 (DMAC.CHCFG_2)
+#define DMACCHITVL_2 (DMAC.CHITVL_2)
+#define DMACCHEXT_2 (DMAC.CHEXT_2)
+#define DMACNXLA_2 (DMAC.NXLA_2)
+#define DMACCRLA_2 (DMAC.CRLA_2)
+#define DMACN0SA_3 (DMAC.N0SA_3)
+#define DMACN0DA_3 (DMAC.N0DA_3)
+#define DMACN0TB_3 (DMAC.N0TB_3)
+#define DMACN1SA_3 (DMAC.N1SA_3)
+#define DMACN1DA_3 (DMAC.N1DA_3)
+#define DMACN1TB_3 (DMAC.N1TB_3)
+#define DMACCRSA_3 (DMAC.CRSA_3)
+#define DMACCRDA_3 (DMAC.CRDA_3)
+#define DMACCRTB_3 (DMAC.CRTB_3)
+#define DMACCHSTAT_3 (DMAC.CHSTAT_3)
+#define DMACCHCTRL_3 (DMAC.CHCTRL_3)
+#define DMACCHCFG_3 (DMAC.CHCFG_3)
+#define DMACCHITVL_3 (DMAC.CHITVL_3)
+#define DMACCHEXT_3 (DMAC.CHEXT_3)
+#define DMACNXLA_3 (DMAC.NXLA_3)
+#define DMACCRLA_3 (DMAC.CRLA_3)
+#define DMACN0SA_4 (DMAC.N0SA_4)
+#define DMACN0DA_4 (DMAC.N0DA_4)
+#define DMACN0TB_4 (DMAC.N0TB_4)
+#define DMACN1SA_4 (DMAC.N1SA_4)
+#define DMACN1DA_4 (DMAC.N1DA_4)
+#define DMACN1TB_4 (DMAC.N1TB_4)
+#define DMACCRSA_4 (DMAC.CRSA_4)
+#define DMACCRDA_4 (DMAC.CRDA_4)
+#define DMACCRTB_4 (DMAC.CRTB_4)
+#define DMACCHSTAT_4 (DMAC.CHSTAT_4)
+#define DMACCHCTRL_4 (DMAC.CHCTRL_4)
+#define DMACCHCFG_4 (DMAC.CHCFG_4)
+#define DMACCHITVL_4 (DMAC.CHITVL_4)
+#define DMACCHEXT_4 (DMAC.CHEXT_4)
+#define DMACNXLA_4 (DMAC.NXLA_4)
+#define DMACCRLA_4 (DMAC.CRLA_4)
+#define DMACN0SA_5 (DMAC.N0SA_5)
+#define DMACN0DA_5 (DMAC.N0DA_5)
+#define DMACN0TB_5 (DMAC.N0TB_5)
+#define DMACN1SA_5 (DMAC.N1SA_5)
+#define DMACN1DA_5 (DMAC.N1DA_5)
+#define DMACN1TB_5 (DMAC.N1TB_5)
+#define DMACCRSA_5 (DMAC.CRSA_5)
+#define DMACCRDA_5 (DMAC.CRDA_5)
+#define DMACCRTB_5 (DMAC.CRTB_5)
+#define DMACCHSTAT_5 (DMAC.CHSTAT_5)
+#define DMACCHCTRL_5 (DMAC.CHCTRL_5)
+#define DMACCHCFG_5 (DMAC.CHCFG_5)
+#define DMACCHITVL_5 (DMAC.CHITVL_5)
+#define DMACCHEXT_5 (DMAC.CHEXT_5)
+#define DMACNXLA_5 (DMAC.NXLA_5)
+#define DMACCRLA_5 (DMAC.CRLA_5)
+#define DMACN0SA_6 (DMAC.N0SA_6)
+#define DMACN0DA_6 (DMAC.N0DA_6)
+#define DMACN0TB_6 (DMAC.N0TB_6)
+#define DMACN1SA_6 (DMAC.N1SA_6)
+#define DMACN1DA_6 (DMAC.N1DA_6)
+#define DMACN1TB_6 (DMAC.N1TB_6)
+#define DMACCRSA_6 (DMAC.CRSA_6)
+#define DMACCRDA_6 (DMAC.CRDA_6)
+#define DMACCRTB_6 (DMAC.CRTB_6)
+#define DMACCHSTAT_6 (DMAC.CHSTAT_6)
+#define DMACCHCTRL_6 (DMAC.CHCTRL_6)
+#define DMACCHCFG_6 (DMAC.CHCFG_6)
+#define DMACCHITVL_6 (DMAC.CHITVL_6)
+#define DMACCHEXT_6 (DMAC.CHEXT_6)
+#define DMACNXLA_6 (DMAC.NXLA_6)
+#define DMACCRLA_6 (DMAC.CRLA_6)
+#define DMACN0SA_7 (DMAC.N0SA_7)
+#define DMACN0DA_7 (DMAC.N0DA_7)
+#define DMACN0TB_7 (DMAC.N0TB_7)
+#define DMACN1SA_7 (DMAC.N1SA_7)
+#define DMACN1DA_7 (DMAC.N1DA_7)
+#define DMACN1TB_7 (DMAC.N1TB_7)
+#define DMACCRSA_7 (DMAC.CRSA_7)
+#define DMACCRDA_7 (DMAC.CRDA_7)
+#define DMACCRTB_7 (DMAC.CRTB_7)
+#define DMACCHSTAT_7 (DMAC.CHSTAT_7)
+#define DMACCHCTRL_7 (DMAC.CHCTRL_7)
+#define DMACCHCFG_7 (DMAC.CHCFG_7)
+#define DMACCHITVL_7 (DMAC.CHITVL_7)
+#define DMACCHEXT_7 (DMAC.CHEXT_7)
+#define DMACNXLA_7 (DMAC.NXLA_7)
+#define DMACCRLA_7 (DMAC.CRLA_7)
+#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7)
+#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7)
+#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7)
+#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7)
+#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7)
+#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7)
+#define DMACN0SA_8 (DMAC.N0SA_8)
+#define DMACN0DA_8 (DMAC.N0DA_8)
+#define DMACN0TB_8 (DMAC.N0TB_8)
+#define DMACN1SA_8 (DMAC.N1SA_8)
+#define DMACN1DA_8 (DMAC.N1DA_8)
+#define DMACN1TB_8 (DMAC.N1TB_8)
+#define DMACCRSA_8 (DMAC.CRSA_8)
+#define DMACCRDA_8 (DMAC.CRDA_8)
+#define DMACCRTB_8 (DMAC.CRTB_8)
+#define DMACCHSTAT_8 (DMAC.CHSTAT_8)
+#define DMACCHCTRL_8 (DMAC.CHCTRL_8)
+#define DMACCHCFG_8 (DMAC.CHCFG_8)
+#define DMACCHITVL_8 (DMAC.CHITVL_8)
+#define DMACCHEXT_8 (DMAC.CHEXT_8)
+#define DMACNXLA_8 (DMAC.NXLA_8)
+#define DMACCRLA_8 (DMAC.CRLA_8)
+#define DMACN0SA_9 (DMAC.N0SA_9)
+#define DMACN0DA_9 (DMAC.N0DA_9)
+#define DMACN0TB_9 (DMAC.N0TB_9)
+#define DMACN1SA_9 (DMAC.N1SA_9)
+#define DMACN1DA_9 (DMAC.N1DA_9)
+#define DMACN1TB_9 (DMAC.N1TB_9)
+#define DMACCRSA_9 (DMAC.CRSA_9)
+#define DMACCRDA_9 (DMAC.CRDA_9)
+#define DMACCRTB_9 (DMAC.CRTB_9)
+#define DMACCHSTAT_9 (DMAC.CHSTAT_9)
+#define DMACCHCTRL_9 (DMAC.CHCTRL_9)
+#define DMACCHCFG_9 (DMAC.CHCFG_9)
+#define DMACCHITVL_9 (DMAC.CHITVL_9)
+#define DMACCHEXT_9 (DMAC.CHEXT_9)
+#define DMACNXLA_9 (DMAC.NXLA_9)
+#define DMACCRLA_9 (DMAC.CRLA_9)
+#define DMACN0SA_10 (DMAC.N0SA_10)
+#define DMACN0DA_10 (DMAC.N0DA_10)
+#define DMACN0TB_10 (DMAC.N0TB_10)
+#define DMACN1SA_10 (DMAC.N1SA_10)
+#define DMACN1DA_10 (DMAC.N1DA_10)
+#define DMACN1TB_10 (DMAC.N1TB_10)
+#define DMACCRSA_10 (DMAC.CRSA_10)
+#define DMACCRDA_10 (DMAC.CRDA_10)
+#define DMACCRTB_10 (DMAC.CRTB_10)
+#define DMACCHSTAT_10 (DMAC.CHSTAT_10)
+#define DMACCHCTRL_10 (DMAC.CHCTRL_10)
+#define DMACCHCFG_10 (DMAC.CHCFG_10)
+#define DMACCHITVL_10 (DMAC.CHITVL_10)
+#define DMACCHEXT_10 (DMAC.CHEXT_10)
+#define DMACNXLA_10 (DMAC.NXLA_10)
+#define DMACCRLA_10 (DMAC.CRLA_10)
+#define DMACN0SA_11 (DMAC.N0SA_11)
+#define DMACN0DA_11 (DMAC.N0DA_11)
+#define DMACN0TB_11 (DMAC.N0TB_11)
+#define DMACN1SA_11 (DMAC.N1SA_11)
+#define DMACN1DA_11 (DMAC.N1DA_11)
+#define DMACN1TB_11 (DMAC.N1TB_11)
+#define DMACCRSA_11 (DMAC.CRSA_11)
+#define DMACCRDA_11 (DMAC.CRDA_11)
+#define DMACCRTB_11 (DMAC.CRTB_11)
+#define DMACCHSTAT_11 (DMAC.CHSTAT_11)
+#define DMACCHCTRL_11 (DMAC.CHCTRL_11)
+#define DMACCHCFG_11 (DMAC.CHCFG_11)
+#define DMACCHITVL_11 (DMAC.CHITVL_11)
+#define DMACCHEXT_11 (DMAC.CHEXT_11)
+#define DMACNXLA_11 (DMAC.NXLA_11)
+#define DMACCRLA_11 (DMAC.CRLA_11)
+#define DMACN0SA_12 (DMAC.N0SA_12)
+#define DMACN0DA_12 (DMAC.N0DA_12)
+#define DMACN0TB_12 (DMAC.N0TB_12)
+#define DMACN1SA_12 (DMAC.N1SA_12)
+#define DMACN1DA_12 (DMAC.N1DA_12)
+#define DMACN1TB_12 (DMAC.N1TB_12)
+#define DMACCRSA_12 (DMAC.CRSA_12)
+#define DMACCRDA_12 (DMAC.CRDA_12)
+#define DMACCRTB_12 (DMAC.CRTB_12)
+#define DMACCHSTAT_12 (DMAC.CHSTAT_12)
+#define DMACCHCTRL_12 (DMAC.CHCTRL_12)
+#define DMACCHCFG_12 (DMAC.CHCFG_12)
+#define DMACCHITVL_12 (DMAC.CHITVL_12)
+#define DMACCHEXT_12 (DMAC.CHEXT_12)
+#define DMACNXLA_12 (DMAC.NXLA_12)
+#define DMACCRLA_12 (DMAC.CRLA_12)
+#define DMACN0SA_13 (DMAC.N0SA_13)
+#define DMACN0DA_13 (DMAC.N0DA_13)
+#define DMACN0TB_13 (DMAC.N0TB_13)
+#define DMACN1SA_13 (DMAC.N1SA_13)
+#define DMACN1DA_13 (DMAC.N1DA_13)
+#define DMACN1TB_13 (DMAC.N1TB_13)
+#define DMACCRSA_13 (DMAC.CRSA_13)
+#define DMACCRDA_13 (DMAC.CRDA_13)
+#define DMACCRTB_13 (DMAC.CRTB_13)
+#define DMACCHSTAT_13 (DMAC.CHSTAT_13)
+#define DMACCHCTRL_13 (DMAC.CHCTRL_13)
+#define DMACCHCFG_13 (DMAC.CHCFG_13)
+#define DMACCHITVL_13 (DMAC.CHITVL_13)
+#define DMACCHEXT_13 (DMAC.CHEXT_13)
+#define DMACNXLA_13 (DMAC.NXLA_13)
+#define DMACCRLA_13 (DMAC.CRLA_13)
+#define DMACN0SA_14 (DMAC.N0SA_14)
+#define DMACN0DA_14 (DMAC.N0DA_14)
+#define DMACN0TB_14 (DMAC.N0TB_14)
+#define DMACN1SA_14 (DMAC.N1SA_14)
+#define DMACN1DA_14 (DMAC.N1DA_14)
+#define DMACN1TB_14 (DMAC.N1TB_14)
+#define DMACCRSA_14 (DMAC.CRSA_14)
+#define DMACCRDA_14 (DMAC.CRDA_14)
+#define DMACCRTB_14 (DMAC.CRTB_14)
+#define DMACCHSTAT_14 (DMAC.CHSTAT_14)
+#define DMACCHCTRL_14 (DMAC.CHCTRL_14)
+#define DMACCHCFG_14 (DMAC.CHCFG_14)
+#define DMACCHITVL_14 (DMAC.CHITVL_14)
+#define DMACCHEXT_14 (DMAC.CHEXT_14)
+#define DMACNXLA_14 (DMAC.NXLA_14)
+#define DMACCRLA_14 (DMAC.CRLA_14)
+#define DMACN0SA_15 (DMAC.N0SA_15)
+#define DMACN0DA_15 (DMAC.N0DA_15)
+#define DMACN0TB_15 (DMAC.N0TB_15)
+#define DMACN1SA_15 (DMAC.N1SA_15)
+#define DMACN1DA_15 (DMAC.N1DA_15)
+#define DMACN1TB_15 (DMAC.N1TB_15)
+#define DMACCRSA_15 (DMAC.CRSA_15)
+#define DMACCRDA_15 (DMAC.CRDA_15)
+#define DMACCRTB_15 (DMAC.CRTB_15)
+#define DMACCHSTAT_15 (DMAC.CHSTAT_15)
+#define DMACCHCTRL_15 (DMAC.CHCTRL_15)
+#define DMACCHCFG_15 (DMAC.CHCFG_15)
+#define DMACCHITVL_15 (DMAC.CHITVL_15)
+#define DMACCHEXT_15 (DMAC.CHEXT_15)
+#define DMACNXLA_15 (DMAC.NXLA_15)
+#define DMACCRLA_15 (DMAC.CRLA_15)
+#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15)
+#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15)
+#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15)
+#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15)
+#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15)
+#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15)
+#define DMACDMARS0 (DMAC.DMARS0)
+#define DMACDMARS1 (DMAC.DMARS1)
+#define DMACDMARS2 (DMAC.DMARS2)
+#define DMACDMARS3 (DMAC.DMARS3)
+#define DMACDMARS4 (DMAC.DMARS4)
+#define DMACDMARS5 (DMAC.DMARS5)
+#define DMACDMARS6 (DMAC.DMARS6)
+#define DMACDMARS7 (DMAC.DMARS7)
+
+
+typedef struct st_dmars_mm
+{
+ 
+    volatile uint32_t  DMARS;                                    /*  DMARS     */
+} r_io_dmars_mm_t;
+
+
+typedef struct st_dmac
+{
+                                                           /* DMAC             */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
+    volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
+    volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
+    volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
+    volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
+    volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
+    volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
+    volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
+    volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
+    volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
+    volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
+    volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
+    volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
+    volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
+    volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
+    volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
+    volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
+    volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
+    volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
+    volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
+    volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
+    volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
+    volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
+    volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
+    volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
+    volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
+    volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
+    volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
+    volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
+    volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
+    volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
+    volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
+    volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
+    volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
+    volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
+    volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
+    volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
+    volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
+    volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
+    volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
+    volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
+    volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
+    volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
+    volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
+    volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
+    volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
+    volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
+    volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
+    volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
+    volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
+    volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
+    volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
+    volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
+    volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
+    volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
+    volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
+    volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
+    volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
+    volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
+    volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
+    volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
+    volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
+    volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
+    volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
+    volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
+    volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
+    volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
+    volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
+    volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
+    volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
+    volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
+    volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
+    volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
+    volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
+    volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
+    volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
+    volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
+    volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
+    volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
+    volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
+    volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
+    volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
+    volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
+    volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
+    volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
+    volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
+    volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
+    volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
+    volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
+    volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
+    volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
+    volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
+    volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
+    volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
+    volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
+    volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
+    volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
+    volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
+    volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
+    volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
+    volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
+    volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
+    volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
+    volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
+    volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
+    volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
+    volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
+    volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
+    volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
+    volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
+    volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
+    volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
+    volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
+    volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
+    volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
+    volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
+    volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
+    volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
+    volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
+    volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
+    volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
+
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy187[256];                          /*                  */
+
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy188[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy189[220];                          /*                  */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
+    volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
+    volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
+    volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
+    volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
+    volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
+    volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
+    volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
+    volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
+    volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
+    volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
+    volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
+    volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
+    volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
+    volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
+    volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
+    volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
+    volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
+    volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
+    volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
+    volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
+    volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
+    volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
+    volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
+    volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
+    volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
+    volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
+    volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
+    volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
+    volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
+    volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
+    volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
+    volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
+    volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
+    volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
+    volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
+    volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
+    volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
+    volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
+    volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
+    volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
+    volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
+    volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
+    volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
+    volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
+    volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
+    volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
+    volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
+    volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
+    volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
+    volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
+    volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
+    volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
+    volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
+    volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
+    volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
+    volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
+    volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
+    volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
+    volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
+    volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
+    volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
+    volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
+    volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
+    volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
+    volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
+    volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
+    volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
+    volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
+    volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
+    volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
+    volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
+    volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
+    volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
+    volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
+    volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
+    volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
+    volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
+    volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
+    volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
+    volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
+    volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
+    volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
+    volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
+    volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
+    volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
+    volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
+    volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
+    volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
+    volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
+    volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
+    volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
+    volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
+    volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
+    volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
+    volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
+    volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
+    volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
+    volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
+    volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
+    volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
+    volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
+    volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
+    volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
+    volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
+    volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
+    volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
+    volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
+    volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
+    volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
+    volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
+    volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
+    volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
+    volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
+    volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
+    volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
+    volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
+    volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
+    volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
+    volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
+    volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
+
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy190[256];                          /*                  */
+
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
+    volatile uint8_t   dummy191[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
+    volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
+    volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
+    volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
+    volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
+
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy192[350095580];                    /*                  */
+    volatile uint32_t  DMARS0;                                 /*  DMARS0          */
+    volatile uint32_t  DMARS1;                                 /*  DMARS1          */
+    volatile uint32_t  DMARS2;                                 /*  DMARS2          */
+    volatile uint32_t  DMARS3;                                 /*  DMARS3          */
+    volatile uint32_t  DMARS4;                                 /*  DMARS4          */
+    volatile uint32_t  DMARS5;                                 /*  DMARS5          */
+    volatile uint32_t  DMARS6;                                 /*  DMARS6          */
+    volatile uint32_t  DMARS7;                                 /*  DMARS7          */
+} r_io_dmac_t;
+
+
+typedef struct st_dmaccommon_n
+{
+ 
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy1[12];                             /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+} r_io_dmaccommon_n_t;
+
+
+typedef struct st_dmac_n
+{
+ 
+    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
+    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
+    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
+    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
+    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
+    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
+    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
+    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
+    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
+    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
+    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
+    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
+    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
+    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
+    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
+    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
+} r_io_dmac_n_t;
+
+
+/* Channel array defines of DMAC (2)*/
+#ifdef  DECLARE_DMACmm_CHANNELS
+volatile struct st_dmars_mm*  DMACmm[ DMACmm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACmm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACmm_CHANNELS */
+
+#ifdef  DECLARE_DMACn_CHANNELS
+volatile struct st_dmac_n*  DMACn[ DMACn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACn_CHANNELS */
+
+#ifdef  DECLARE_DMACnn_CHANNELS
+volatile struct st_dmaccommon_n*  DMACnn[ DMACnn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACnn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACnn_CHANNELS */
+/* End of channel array defines of DMAC (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h	(revision 374)
@@ -0,0 +1,441 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dvdec_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef DVDEC_IODEFINE_H
+#define DVDEC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
+#define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
+
+
+/* Start of channel array defines of DVDEC */
+
+/* Channel array defines of DVDEC */
+/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
+#define DVDEC_COUNT  (2)
+#define DVDEC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DVDEC0, &DVDEC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of DVDEC */
+
+
+#define ADCCR1_1 (DVDEC1.ADCCR1)
+#define TGCR1_1 (DVDEC1.TGCR1)
+#define TGCR2_1 (DVDEC1.TGCR2)
+#define TGCR3_1 (DVDEC1.TGCR3)
+#define SYNSCR1_1 (DVDEC1.SYNSCR1)
+#define SYNSCR2_1 (DVDEC1.SYNSCR2)
+#define SYNSCR3_1 (DVDEC1.SYNSCR3)
+#define SYNSCR4_1 (DVDEC1.SYNSCR4)
+#define SYNSCR5_1 (DVDEC1.SYNSCR5)
+#define HAFCCR1_1 (DVDEC1.HAFCCR1)
+#define HAFCCR2_1 (DVDEC1.HAFCCR2)
+#define HAFCCR3_1 (DVDEC1.HAFCCR3)
+#define VCDWCR1_1 (DVDEC1.VCDWCR1)
+#define DCPCR1_1 (DVDEC1.DCPCR1)
+#define DCPCR2_1 (DVDEC1.DCPCR2)
+#define DCPCR3_1 (DVDEC1.DCPCR3)
+#define DCPCR4_1 (DVDEC1.DCPCR4)
+#define DCPCR5_1 (DVDEC1.DCPCR5)
+#define DCPCR6_1 (DVDEC1.DCPCR6)
+#define DCPCR7_1 (DVDEC1.DCPCR7)
+#define DCPCR8_1 (DVDEC1.DCPCR8)
+#define NSDCR_1 (DVDEC1.NSDCR)
+#define BTLCR_1 (DVDEC1.BTLCR)
+#define BTGPCR_1 (DVDEC1.BTGPCR)
+#define ACCCR1_1 (DVDEC1.ACCCR1)
+#define ACCCR2_1 (DVDEC1.ACCCR2)
+#define ACCCR3_1 (DVDEC1.ACCCR3)
+#define TINTCR_1 (DVDEC1.TINTCR)
+#define YCDCR_1 (DVDEC1.YCDCR)
+#define AGCCR1_1 (DVDEC1.AGCCR1)
+#define AGCCR2_1 (DVDEC1.AGCCR2)
+#define PKLIMITCR_1 (DVDEC1.PKLIMITCR)
+#define RGORCR1_1 (DVDEC1.RGORCR1)
+#define RGORCR2_1 (DVDEC1.RGORCR2)
+#define RGORCR3_1 (DVDEC1.RGORCR3)
+#define RGORCR4_1 (DVDEC1.RGORCR4)
+#define RGORCR5_1 (DVDEC1.RGORCR5)
+#define RGORCR6_1 (DVDEC1.RGORCR6)
+#define RGORCR7_1 (DVDEC1.RGORCR7)
+#define AFCPFCR_1 (DVDEC1.AFCPFCR)
+#define RUPDCR_1 (DVDEC1.RUPDCR)
+#define VSYNCSR_1 (DVDEC1.VSYNCSR)
+#define HSYNCSR_1 (DVDEC1.HSYNCSR)
+#define DCPSR1_1 (DVDEC1.DCPSR1)
+#define DCPSR2_1 (DVDEC1.DCPSR2)
+#define NSDSR_1 (DVDEC1.NSDSR)
+#define CROMASR1_1 (DVDEC1.CROMASR1)
+#define CROMASR2_1 (DVDEC1.CROMASR2)
+#define SYNCSSR_1 (DVDEC1.SYNCSSR)
+#define AGCCSR1_1 (DVDEC1.AGCCSR1)
+#define AGCCSR2_1 (DVDEC1.AGCCSR2)
+#define YCSCR3_1 (DVDEC1.YCSCR3)
+#define YCSCR4_1 (DVDEC1.YCSCR4)
+#define YCSCR5_1 (DVDEC1.YCSCR5)
+#define YCSCR6_1 (DVDEC1.YCSCR6)
+#define YCSCR7_1 (DVDEC1.YCSCR7)
+#define YCSCR8_1 (DVDEC1.YCSCR8)
+#define YCSCR9_1 (DVDEC1.YCSCR9)
+#define YCSCR11_1 (DVDEC1.YCSCR11)
+#define YCSCR12_1 (DVDEC1.YCSCR12)
+#define DCPCR9_1 (DVDEC1.DCPCR9)
+#define YCTWA_F0_1 (DVDEC1.YCTWA_F0)
+#define YCTWA_F1_1 (DVDEC1.YCTWA_F1)
+#define YCTWA_F2_1 (DVDEC1.YCTWA_F2)
+#define YCTWA_F3_1 (DVDEC1.YCTWA_F3)
+#define YCTWA_F4_1 (DVDEC1.YCTWA_F4)
+#define YCTWA_F5_1 (DVDEC1.YCTWA_F5)
+#define YCTWA_F6_1 (DVDEC1.YCTWA_F6)
+#define YCTWA_F7_1 (DVDEC1.YCTWA_F7)
+#define YCTWA_F8_1 (DVDEC1.YCTWA_F8)
+#define YCTWB_F0_1 (DVDEC1.YCTWB_F0)
+#define YCTWB_F1_1 (DVDEC1.YCTWB_F1)
+#define YCTWB_F2_1 (DVDEC1.YCTWB_F2)
+#define YCTWB_F3_1 (DVDEC1.YCTWB_F3)
+#define YCTWB_F4_1 (DVDEC1.YCTWB_F4)
+#define YCTWB_F5_1 (DVDEC1.YCTWB_F5)
+#define YCTWB_F6_1 (DVDEC1.YCTWB_F6)
+#define YCTWB_F7_1 (DVDEC1.YCTWB_F7)
+#define YCTWB_F8_1 (DVDEC1.YCTWB_F8)
+#define YCTNA_F0_1 (DVDEC1.YCTNA_F0)
+#define YCTNA_F1_1 (DVDEC1.YCTNA_F1)
+#define YCTNA_F2_1 (DVDEC1.YCTNA_F2)
+#define YCTNA_F3_1 (DVDEC1.YCTNA_F3)
+#define YCTNA_F4_1 (DVDEC1.YCTNA_F4)
+#define YCTNA_F5_1 (DVDEC1.YCTNA_F5)
+#define YCTNA_F6_1 (DVDEC1.YCTNA_F6)
+#define YCTNA_F7_1 (DVDEC1.YCTNA_F7)
+#define YCTNA_F8_1 (DVDEC1.YCTNA_F8)
+#define YCTNB_F0_1 (DVDEC1.YCTNB_F0)
+#define YCTNB_F1_1 (DVDEC1.YCTNB_F1)
+#define YCTNB_F2_1 (DVDEC1.YCTNB_F2)
+#define YCTNB_F3_1 (DVDEC1.YCTNB_F3)
+#define YCTNB_F4_1 (DVDEC1.YCTNB_F4)
+#define YCTNB_F5_1 (DVDEC1.YCTNB_F5)
+#define YCTNB_F6_1 (DVDEC1.YCTNB_F6)
+#define YCTNB_F7_1 (DVDEC1.YCTNB_F7)
+#define YCTNB_F8_1 (DVDEC1.YCTNB_F8)
+#define YGAINCR_1 (DVDEC1.YGAINCR)
+#define CBGAINCR_1 (DVDEC1.CBGAINCR)
+#define CRGAINCR_1 (DVDEC1.CRGAINCR)
+#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE)
+#define PGACR_1 (DVDEC1.PGACR)
+#define ADCCR2_1 (DVDEC1.ADCCR2)
+#define ADCCR1_0 (DVDEC0.ADCCR1)
+#define TGCR1_0 (DVDEC0.TGCR1)
+#define TGCR2_0 (DVDEC0.TGCR2)
+#define TGCR3_0 (DVDEC0.TGCR3)
+#define SYNSCR1_0 (DVDEC0.SYNSCR1)
+#define SYNSCR2_0 (DVDEC0.SYNSCR2)
+#define SYNSCR3_0 (DVDEC0.SYNSCR3)
+#define SYNSCR4_0 (DVDEC0.SYNSCR4)
+#define SYNSCR5_0 (DVDEC0.SYNSCR5)
+#define HAFCCR1_0 (DVDEC0.HAFCCR1)
+#define HAFCCR2_0 (DVDEC0.HAFCCR2)
+#define HAFCCR3_0 (DVDEC0.HAFCCR3)
+#define VCDWCR1_0 (DVDEC0.VCDWCR1)
+#define DCPCR1_0 (DVDEC0.DCPCR1)
+#define DCPCR2_0 (DVDEC0.DCPCR2)
+#define DCPCR3_0 (DVDEC0.DCPCR3)
+#define DCPCR4_0 (DVDEC0.DCPCR4)
+#define DCPCR5_0 (DVDEC0.DCPCR5)
+#define DCPCR6_0 (DVDEC0.DCPCR6)
+#define DCPCR7_0 (DVDEC0.DCPCR7)
+#define DCPCR8_0 (DVDEC0.DCPCR8)
+#define NSDCR_0 (DVDEC0.NSDCR)
+#define BTLCR_0 (DVDEC0.BTLCR)
+#define BTGPCR_0 (DVDEC0.BTGPCR)
+#define ACCCR1_0 (DVDEC0.ACCCR1)
+#define ACCCR2_0 (DVDEC0.ACCCR2)
+#define ACCCR3_0 (DVDEC0.ACCCR3)
+#define TINTCR_0 (DVDEC0.TINTCR)
+#define YCDCR_0 (DVDEC0.YCDCR)
+#define AGCCR1_0 (DVDEC0.AGCCR1)
+#define AGCCR2_0 (DVDEC0.AGCCR2)
+#define PKLIMITCR_0 (DVDEC0.PKLIMITCR)
+#define RGORCR1_0 (DVDEC0.RGORCR1)
+#define RGORCR2_0 (DVDEC0.RGORCR2)
+#define RGORCR3_0 (DVDEC0.RGORCR3)
+#define RGORCR4_0 (DVDEC0.RGORCR4)
+#define RGORCR5_0 (DVDEC0.RGORCR5)
+#define RGORCR6_0 (DVDEC0.RGORCR6)
+#define RGORCR7_0 (DVDEC0.RGORCR7)
+#define AFCPFCR_0 (DVDEC0.AFCPFCR)
+#define RUPDCR_0 (DVDEC0.RUPDCR)
+#define VSYNCSR_0 (DVDEC0.VSYNCSR)
+#define HSYNCSR_0 (DVDEC0.HSYNCSR)
+#define DCPSR1_0 (DVDEC0.DCPSR1)
+#define DCPSR2_0 (DVDEC0.DCPSR2)
+#define NSDSR_0 (DVDEC0.NSDSR)
+#define CROMASR1_0 (DVDEC0.CROMASR1)
+#define CROMASR2_0 (DVDEC0.CROMASR2)
+#define SYNCSSR_0 (DVDEC0.SYNCSSR)
+#define AGCCSR1_0 (DVDEC0.AGCCSR1)
+#define AGCCSR2_0 (DVDEC0.AGCCSR2)
+#define YCSCR3_0 (DVDEC0.YCSCR3)
+#define YCSCR4_0 (DVDEC0.YCSCR4)
+#define YCSCR5_0 (DVDEC0.YCSCR5)
+#define YCSCR6_0 (DVDEC0.YCSCR6)
+#define YCSCR7_0 (DVDEC0.YCSCR7)
+#define YCSCR8_0 (DVDEC0.YCSCR8)
+#define YCSCR9_0 (DVDEC0.YCSCR9)
+#define YCSCR11_0 (DVDEC0.YCSCR11)
+#define YCSCR12_0 (DVDEC0.YCSCR12)
+#define DCPCR9_0 (DVDEC0.DCPCR9)
+#define YCTWA_F0_0 (DVDEC0.YCTWA_F0)
+#define YCTWA_F1_0 (DVDEC0.YCTWA_F1)
+#define YCTWA_F2_0 (DVDEC0.YCTWA_F2)
+#define YCTWA_F3_0 (DVDEC0.YCTWA_F3)
+#define YCTWA_F4_0 (DVDEC0.YCTWA_F4)
+#define YCTWA_F5_0 (DVDEC0.YCTWA_F5)
+#define YCTWA_F6_0 (DVDEC0.YCTWA_F6)
+#define YCTWA_F7_0 (DVDEC0.YCTWA_F7)
+#define YCTWA_F8_0 (DVDEC0.YCTWA_F8)
+#define YCTWB_F0_0 (DVDEC0.YCTWB_F0)
+#define YCTWB_F1_0 (DVDEC0.YCTWB_F1)
+#define YCTWB_F2_0 (DVDEC0.YCTWB_F2)
+#define YCTWB_F3_0 (DVDEC0.YCTWB_F3)
+#define YCTWB_F4_0 (DVDEC0.YCTWB_F4)
+#define YCTWB_F5_0 (DVDEC0.YCTWB_F5)
+#define YCTWB_F6_0 (DVDEC0.YCTWB_F6)
+#define YCTWB_F7_0 (DVDEC0.YCTWB_F7)
+#define YCTWB_F8_0 (DVDEC0.YCTWB_F8)
+#define YCTNA_F0_0 (DVDEC0.YCTNA_F0)
+#define YCTNA_F1_0 (DVDEC0.YCTNA_F1)
+#define YCTNA_F2_0 (DVDEC0.YCTNA_F2)
+#define YCTNA_F3_0 (DVDEC0.YCTNA_F3)
+#define YCTNA_F4_0 (DVDEC0.YCTNA_F4)
+#define YCTNA_F5_0 (DVDEC0.YCTNA_F5)
+#define YCTNA_F6_0 (DVDEC0.YCTNA_F6)
+#define YCTNA_F7_0 (DVDEC0.YCTNA_F7)
+#define YCTNA_F8_0 (DVDEC0.YCTNA_F8)
+#define YCTNB_F0_0 (DVDEC0.YCTNB_F0)
+#define YCTNB_F1_0 (DVDEC0.YCTNB_F1)
+#define YCTNB_F2_0 (DVDEC0.YCTNB_F2)
+#define YCTNB_F3_0 (DVDEC0.YCTNB_F3)
+#define YCTNB_F4_0 (DVDEC0.YCTNB_F4)
+#define YCTNB_F5_0 (DVDEC0.YCTNB_F5)
+#define YCTNB_F6_0 (DVDEC0.YCTNB_F6)
+#define YCTNB_F7_0 (DVDEC0.YCTNB_F7)
+#define YCTNB_F8_0 (DVDEC0.YCTNB_F8)
+#define YGAINCR_0 (DVDEC0.YGAINCR)
+#define CBGAINCR_0 (DVDEC0.CBGAINCR)
+#define CRGAINCR_0 (DVDEC0.CRGAINCR)
+#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE)
+#define PGACR_0 (DVDEC0.PGACR)
+#define ADCCR2_0 (DVDEC0.ADCCR2)
+
+#define DVDEC_TGCRn_COUNT (3)
+#define DVDEC_SYNSCRn_COUNT (5)
+#define DVDEC_HAFCCRn_COUNT (3)
+#define DVDEC_DCPCRn_COUNT (8)
+#define DVDEC_ACCCRn_COUNT (3)
+#define DVDEC_AGCCRn_COUNT (2)
+#define DVDEC_RGORCRn_COUNT (7)
+#define DVDEC_DCPSRn_COUNT (2)
+#define DVDEC_CROMASRn_COUNT (2)
+#define DVDEC_AGCCSRn_COUNT (2)
+#define DVDEC_YCSCRn_COUNT (7)
+#define DVDEC_YCTWA_Fn_COUNT (9)
+#define DVDEC_YCTWB_Fn_COUNT (9)
+#define DVDEC_YCTNA_Fn_COUNT (9)
+#define DVDEC_YCTNB_Fn_COUNT (9)
+
+
+typedef struct st_dvdec
+{
+                                                           /* DVDEC            */
+    volatile uint16_t ADCCR1;                                 /*  ADCCR1          */
+    volatile uint8_t   dummy1[4];                              /*                  */
+
+/* #define DVDEC_TGCRn_COUNT (3) */
+    volatile uint16_t TGCR1;                                  /*  TGCR1           */
+    volatile uint16_t TGCR2;                                  /*  TGCR2           */
+    volatile uint16_t TGCR3;                                  /*  TGCR3           */
+    volatile uint8_t   dummy2[6];                              /*                  */
+
+/* #define DVDEC_SYNSCRn_COUNT (5) */
+    volatile uint16_t SYNSCR1;                                /*  SYNSCR1         */
+    volatile uint16_t SYNSCR2;                                /*  SYNSCR2         */
+    volatile uint16_t SYNSCR3;                                /*  SYNSCR3         */
+    volatile uint16_t SYNSCR4;                                /*  SYNSCR4         */
+    volatile uint16_t SYNSCR5;                                /*  SYNSCR5         */
+
+/* #define DVDEC_HAFCCRn_COUNT (3) */
+    volatile uint16_t HAFCCR1;                                /*  HAFCCR1         */
+    volatile uint16_t HAFCCR2;                                /*  HAFCCR2         */
+    volatile uint16_t HAFCCR3;                                /*  HAFCCR3         */
+    volatile uint16_t VCDWCR1;                                /*  VCDWCR1         */
+    volatile uint8_t   dummy3[4];                              /*                  */
+
+/* #define DVDEC_DCPCRn_COUNT (8) */
+    volatile uint16_t DCPCR1;                                 /*  DCPCR1          */
+    volatile uint16_t DCPCR2;                                 /*  DCPCR2          */
+    volatile uint16_t DCPCR3;                                 /*  DCPCR3          */
+    volatile uint16_t DCPCR4;                                 /*  DCPCR4          */
+    volatile uint16_t DCPCR5;                                 /*  DCPCR5          */
+    volatile uint16_t DCPCR6;                                 /*  DCPCR6          */
+    volatile uint16_t DCPCR7;                                 /*  DCPCR7          */
+    volatile uint16_t DCPCR8;                                 /*  DCPCR8          */
+    volatile uint16_t NSDCR;                                  /*  NSDCR           */
+    volatile uint16_t BTLCR;                                  /*  BTLCR           */
+    volatile uint16_t BTGPCR;                                 /*  BTGPCR          */
+
+/* #define DVDEC_ACCCRn_COUNT (3) */
+    volatile uint16_t ACCCR1;                                 /*  ACCCR1          */
+    volatile uint16_t ACCCR2;                                 /*  ACCCR2          */
+    volatile uint16_t ACCCR3;                                 /*  ACCCR3          */
+    volatile uint16_t TINTCR;                                 /*  TINTCR          */
+    volatile uint16_t YCDCR;                                  /*  YCDCR           */
+
+/* #define DVDEC_AGCCRn_COUNT (2) */
+    volatile uint16_t AGCCR1;                                 /*  AGCCR1          */
+    volatile uint16_t AGCCR2;                                 /*  AGCCR2          */
+    volatile uint16_t PKLIMITCR;                              /*  PKLIMITCR       */
+
+/* #define DVDEC_RGORCRn_COUNT (7) */
+    volatile uint16_t RGORCR1;                                /*  RGORCR1         */
+    volatile uint16_t RGORCR2;                                /*  RGORCR2         */
+    volatile uint16_t RGORCR3;                                /*  RGORCR3         */
+    volatile uint16_t RGORCR4;                                /*  RGORCR4         */
+    volatile uint16_t RGORCR5;                                /*  RGORCR5         */
+    volatile uint16_t RGORCR6;                                /*  RGORCR6         */
+    volatile uint16_t RGORCR7;                                /*  RGORCR7         */
+    volatile uint8_t   dummy4[24];                             /*                  */
+    volatile uint16_t AFCPFCR;                                /*  AFCPFCR         */
+    volatile uint16_t RUPDCR;                                 /*  RUPDCR          */
+    volatile uint16_t VSYNCSR;                                /*  VSYNCSR         */
+    volatile uint16_t HSYNCSR;                                /*  HSYNCSR         */
+
+/* #define DVDEC_DCPSRn_COUNT (2) */
+    volatile uint16_t DCPSR1;                                 /*  DCPSR1          */
+    volatile uint16_t DCPSR2;                                 /*  DCPSR2          */
+    volatile uint8_t   dummy5[4];                              /*                  */
+    volatile uint16_t NSDSR;                                  /*  NSDSR           */
+
+/* #define DVDEC_CROMASRn_COUNT (2) */
+    volatile uint16_t CROMASR1;                               /*  CROMASR1        */
+    volatile uint16_t CROMASR2;                               /*  CROMASR2        */
+    volatile uint16_t SYNCSSR;                                /*  SYNCSSR         */
+
+/* #define DVDEC_AGCCSRn_COUNT (2) */
+    volatile uint16_t AGCCSR1;                                /*  AGCCSR1         */
+    volatile uint16_t AGCCSR2;                                /*  AGCCSR2         */
+    volatile uint8_t   dummy6[108];                            /*                  */
+
+/* #define DVDEC_YCSCRn_COUNT (7) */
+    volatile uint16_t YCSCR3;                                 /*  YCSCR3          */
+    volatile uint16_t YCSCR4;                                 /*  YCSCR4          */
+    volatile uint16_t YCSCR5;                                 /*  YCSCR5          */
+    volatile uint16_t YCSCR6;                                 /*  YCSCR6          */
+    volatile uint16_t YCSCR7;                                 /*  YCSCR7          */
+    volatile uint16_t YCSCR8;                                 /*  YCSCR8          */
+    volatile uint16_t YCSCR9;                                 /*  YCSCR9          */
+    volatile uint8_t   dummy7[2];                              /*                  */
+    volatile uint16_t YCSCR11;                                /*  YCSCR11         */
+    volatile uint16_t YCSCR12;                                /*  YCSCR12         */
+    volatile uint8_t   dummy8[104];                            /*                  */
+    volatile uint16_t DCPCR9;                                 /*  DCPCR9          */
+    volatile uint8_t   dummy9[16];                             /*                  */
+
+/* #define DVDEC_YCTWA_Fn_COUNT (9) */
+    volatile uint16_t YCTWA_F0;                               /*  YCTWA_F0        */
+    volatile uint16_t YCTWA_F1;                               /*  YCTWA_F1        */
+    volatile uint16_t YCTWA_F2;                               /*  YCTWA_F2        */
+    volatile uint16_t YCTWA_F3;                               /*  YCTWA_F3        */
+    volatile uint16_t YCTWA_F4;                               /*  YCTWA_F4        */
+    volatile uint16_t YCTWA_F5;                               /*  YCTWA_F5        */
+    volatile uint16_t YCTWA_F6;                               /*  YCTWA_F6        */
+    volatile uint16_t YCTWA_F7;                               /*  YCTWA_F7        */
+    volatile uint16_t YCTWA_F8;                               /*  YCTWA_F8        */
+
+/* #define DVDEC_YCTWB_Fn_COUNT (9) */
+    volatile uint16_t YCTWB_F0;                               /*  YCTWB_F0        */
+    volatile uint16_t YCTWB_F1;                               /*  YCTWB_F1        */
+    volatile uint16_t YCTWB_F2;                               /*  YCTWB_F2        */
+    volatile uint16_t YCTWB_F3;                               /*  YCTWB_F3        */
+    volatile uint16_t YCTWB_F4;                               /*  YCTWB_F4        */
+    volatile uint16_t YCTWB_F5;                               /*  YCTWB_F5        */
+    volatile uint16_t YCTWB_F6;                               /*  YCTWB_F6        */
+    volatile uint16_t YCTWB_F7;                               /*  YCTWB_F7        */
+    volatile uint16_t YCTWB_F8;                               /*  YCTWB_F8        */
+
+/* #define DVDEC_YCTNA_Fn_COUNT (9) */
+    volatile uint16_t YCTNA_F0;                               /*  YCTNA_F0        */
+    volatile uint16_t YCTNA_F1;                               /*  YCTNA_F1        */
+    volatile uint16_t YCTNA_F2;                               /*  YCTNA_F2        */
+    volatile uint16_t YCTNA_F3;                               /*  YCTNA_F3        */
+    volatile uint16_t YCTNA_F4;                               /*  YCTNA_F4        */
+    volatile uint16_t YCTNA_F5;                               /*  YCTNA_F5        */
+    volatile uint16_t YCTNA_F6;                               /*  YCTNA_F6        */
+    volatile uint16_t YCTNA_F7;                               /*  YCTNA_F7        */
+    volatile uint16_t YCTNA_F8;                               /*  YCTNA_F8        */
+
+/* #define DVDEC_YCTNB_Fn_COUNT (9) */
+    volatile uint16_t YCTNB_F0;                               /*  YCTNB_F0        */
+    volatile uint16_t YCTNB_F1;                               /*  YCTNB_F1        */
+    volatile uint16_t YCTNB_F2;                               /*  YCTNB_F2        */
+    volatile uint16_t YCTNB_F3;                               /*  YCTNB_F3        */
+    volatile uint16_t YCTNB_F4;                               /*  YCTNB_F4        */
+    volatile uint16_t YCTNB_F5;                               /*  YCTNB_F5        */
+    volatile uint16_t YCTNB_F6;                               /*  YCTNB_F6        */
+    volatile uint16_t YCTNB_F7;                               /*  YCTNB_F7        */
+    volatile uint16_t YCTNB_F8;                               /*  YCTNB_F8        */
+    volatile uint8_t   dummy10[38];                            /*                  */
+    volatile uint16_t YGAINCR;                                /*  YGAINCR         */
+    volatile uint16_t CBGAINCR;                               /*  CBGAINCR        */
+    volatile uint16_t CRGAINCR;                               /*  CRGAINCR        */
+    volatile uint8_t   dummy11[122];                           /*                  */
+    volatile uint16_t PGA_UPDATE;                             /*  PGA_UPDATE      */
+    volatile uint16_t PGACR;                                  /*  PGACR           */
+    volatile uint16_t ADCCR2;                                 /*  ADCCR2          */
+} r_io_dvdec_t;
+
+
+/* Channel array defines of DVDEC (2)*/
+#ifdef  DECLARE_DVDEC_CHANNELS
+volatile struct st_dvdec*  DVDEC[ DVDEC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DVDEC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DVDEC_CHANNELS */
+/* End of channel array defines of DVDEC (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h	(revision 374)
@@ -0,0 +1,509 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ether_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef ETHER_IODEFINE_H
+#define ETHER_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
+
+
+/* Start of channel array defines of ETHER */
+
+/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
+/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
+#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  (32)
+#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
+    &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
+    &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
+    &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
+#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
+#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
+#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
+#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
+#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
+#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
+#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
+#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
+#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
+#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
+#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
+#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
+#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
+#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
+#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
+#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
+#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
+#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
+#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
+#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
+#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
+#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
+#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
+#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
+#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
+#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
+#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
+#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
+#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
+#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
+#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
+
+/* End of channel array defines of ETHER */
+
+
+#define ETHEREDSR0 (ETHER.EDSR0)
+#define ETHERTDLAR0 (ETHER.TDLAR0)
+#define ETHERTDFAR0 (ETHER.TDFAR0)
+#define ETHERTDFXR0 (ETHER.TDFXR0)
+#define ETHERTDFFR0 (ETHER.TDFFR0)
+#define ETHERRDLAR0 (ETHER.RDLAR0)
+#define ETHERRDFAR0 (ETHER.RDFAR0)
+#define ETHERRDFXR0 (ETHER.RDFXR0)
+#define ETHERRDFFR0 (ETHER.RDFFR0)
+#define ETHEREDMR0 (ETHER.EDMR0)
+#define ETHEREDTRR0 (ETHER.EDTRR0)
+#define ETHEREDRRR0 (ETHER.EDRRR0)
+#define ETHEREESR0 (ETHER.EESR0)
+#define ETHEREESIPR0 (ETHER.EESIPR0)
+#define ETHERTRSCER0 (ETHER.TRSCER0)
+#define ETHERRMFCR0 (ETHER.RMFCR0)
+#define ETHERTFTR0 (ETHER.TFTR0)
+#define ETHERFDR0 (ETHER.FDR0)
+#define ETHERRMCR0 (ETHER.RMCR0)
+#define ETHERRPADIR0 (ETHER.RPADIR0)
+#define ETHERFCFTR0 (ETHER.FCFTR0)
+#define ETHERCSMR (ETHER.CSMR)
+#define ETHERCSSBM (ETHER.CSSBM)
+#define ETHERCSSMR (ETHER.CSSMR)
+#define ETHERECMR0 (ETHER.ECMR0)
+#define ETHERRFLR0 (ETHER.RFLR0)
+#define ETHERECSR0 (ETHER.ECSR0)
+#define ETHERECSIPR0 (ETHER.ECSIPR0)
+#define ETHERPIR0 (ETHER.PIR0)
+#define ETHERAPR0 (ETHER.APR0)
+#define ETHERMPR0 (ETHER.MPR0)
+#define ETHERPFTCR0 (ETHER.PFTCR0)
+#define ETHERPFRCR0 (ETHER.PFRCR0)
+#define ETHERTPAUSER0 (ETHER.TPAUSER0)
+#define ETHERMAHR0 (ETHER.MAHR0)
+#define ETHERMALR0 (ETHER.MALR0)
+#define ETHERCEFCR0 (ETHER.CEFCR0)
+#define ETHERFRECR0 (ETHER.FRECR0)
+#define ETHERTSFRCR0 (ETHER.TSFRCR0)
+#define ETHERTLFRCR0 (ETHER.TLFRCR0)
+#define ETHERRFCR0 (ETHER.RFCR0)
+#define ETHERMAFCR0 (ETHER.MAFCR0)
+#define ETHERARSTR (ETHER.ARSTR)
+#define ETHERTSU_CTRST (ETHER.TSU_CTRST)
+#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0)
+#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY)
+#define ETHERTSU_TEN (ETHER.TSU_TEN)
+#define ETHERTXNLCR0 (ETHER.TXNLCR0)
+#define ETHERTXALCR0 (ETHER.TXALCR0)
+#define ETHERRXNLCR0 (ETHER.RXNLCR0)
+#define ETHERRXALCR0 (ETHER.RXALCR0)
+#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0)
+#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0)
+#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1)
+#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1)
+#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2)
+#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2)
+#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3)
+#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3)
+#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4)
+#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4)
+#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5)
+#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5)
+#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6)
+#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6)
+#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7)
+#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7)
+#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8)
+#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8)
+#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9)
+#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9)
+#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10)
+#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10)
+#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11)
+#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11)
+#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12)
+#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12)
+#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13)
+#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13)
+#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14)
+#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14)
+#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15)
+#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15)
+#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16)
+#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16)
+#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17)
+#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17)
+#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18)
+#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18)
+#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19)
+#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19)
+#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20)
+#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20)
+#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21)
+#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21)
+#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22)
+#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22)
+#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23)
+#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23)
+#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24)
+#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24)
+#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25)
+#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25)
+#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26)
+#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26)
+#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27)
+#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27)
+#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28)
+#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28)
+#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29)
+#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29)
+#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30)
+#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30)
+#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31)
+#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31)
+
+
+typedef struct st_ether
+{
+                                                           /* ETHER            */
+    volatile uint32_t  EDSR0;                                  /*  EDSR0           */
+    volatile uint8_t   dummy207[12];                           /*                  */
+    volatile uint32_t  TDLAR0;                                 /*  TDLAR0          */
+    volatile uint32_t  TDFAR0;                                 /*  TDFAR0          */
+    volatile uint32_t  TDFXR0;                                 /*  TDFXR0          */
+    volatile uint32_t  TDFFR0;                                 /*  TDFFR0          */
+    volatile uint8_t   dummy208[16];                           /*                  */
+    volatile uint32_t  RDLAR0;                                 /*  RDLAR0          */
+    volatile uint32_t  RDFAR0;                                 /*  RDFAR0          */
+    volatile uint32_t  RDFXR0;                                 /*  RDFXR0          */
+    volatile uint32_t  RDFFR0;                                 /*  RDFFR0          */
+    volatile uint8_t   dummy209[960];                          /*                  */
+    volatile uint32_t  EDMR0;                                  /*  EDMR0           */
+    volatile uint8_t   dummy210[4];                            /*                  */
+    volatile uint32_t  EDTRR0;                                 /*  EDTRR0          */
+    volatile uint8_t   dummy211[4];                            /*                  */
+    volatile uint32_t  EDRRR0;                                 /*  EDRRR0          */
+    volatile uint8_t   dummy212[20];                           /*                  */
+    volatile uint32_t  EESR0;                                  /*  EESR0           */
+    volatile uint8_t   dummy213[4];                            /*                  */
+    volatile uint32_t  EESIPR0;                                /*  EESIPR0         */
+    volatile uint8_t   dummy214[4];                            /*                  */
+    volatile uint32_t  TRSCER0;                                /*  TRSCER0         */
+    volatile uint8_t   dummy215[4];                            /*                  */
+    volatile uint32_t  RMFCR0;                                 /*  RMFCR0          */
+    volatile uint8_t   dummy216[4];                            /*                  */
+    volatile uint32_t  TFTR0;                                  /*  TFTR0           */
+    volatile uint8_t   dummy217[4];                            /*                  */
+    volatile uint32_t  FDR0;                                   /*  FDR0            */
+    volatile uint8_t   dummy218[4];                            /*                  */
+    volatile uint32_t  RMCR0;                                  /*  RMCR0           */
+    volatile uint8_t   dummy219[4];                            /*                  */
+    volatile uint32_t  RPADIR0;                                /*  RPADIR0         */
+    volatile uint8_t   dummy220[4];                            /*                  */
+    volatile uint32_t  FCFTR0;                                 /*  FCFTR0          */
+    volatile uint8_t   dummy221[120];                          /*                  */
+    volatile uint32_t  CSMR;                                   /*  CSMR            */
+    volatile uint32_t  CSSBM;                                  /*  CSSBM           */
+    volatile uint32_t  CSSMR;                                  /*  CSSMR           */
+    volatile uint8_t   dummy222[16];                           /*                  */
+    volatile uint32_t  ECMR0;                                  /*  ECMR0           */
+    volatile uint8_t   dummy223[4];                            /*                  */
+    volatile uint32_t  RFLR0;                                  /*  RFLR0           */
+    volatile uint8_t   dummy224[4];                            /*                  */
+    volatile uint32_t  ECSR0;                                  /*  ECSR0           */
+    volatile uint8_t   dummy225[4];                            /*                  */
+    volatile uint32_t  ECSIPR0;                                /*  ECSIPR0         */
+    volatile uint8_t   dummy226[4];                            /*                  */
+    volatile uint32_t  PIR0;                                   /*  PIR0            */
+    volatile uint8_t   dummy227[48];                           /*                  */
+    volatile uint32_t  APR0;                                   /*  APR0            */
+    volatile uint32_t  MPR0;                                   /*  MPR0            */
+    volatile uint32_t  PFTCR0;                                 /*  PFTCR0          */
+    volatile uint32_t  PFRCR0;                                 /*  PFRCR0          */
+    volatile uint32_t  TPAUSER0;                               /*  TPAUSER0        */
+    volatile uint8_t   dummy228[88];                           /*                  */
+    volatile uint32_t  MAHR0;                                  /*  MAHR0           */
+    volatile uint8_t   dummy229[4];                            /*                  */
+    volatile uint32_t  MALR0;                                  /*  MALR0           */
+    volatile uint8_t   dummy230[372];                          /*                  */
+    volatile uint32_t  CEFCR0;                                 /*  CEFCR0          */
+    volatile uint8_t   dummy231[4];                            /*                  */
+    volatile uint32_t  FRECR0;                                 /*  FRECR0          */
+    volatile uint8_t   dummy232[4];                            /*                  */
+    volatile uint32_t  TSFRCR0;                                /*  TSFRCR0         */
+    volatile uint8_t   dummy233[4];                            /*                  */
+    volatile uint32_t  TLFRCR0;                                /*  TLFRCR0         */
+    volatile uint8_t   dummy234[4];                            /*                  */
+    volatile uint32_t  RFCR0;                                  /*  RFCR0           */
+    volatile uint8_t   dummy235[20];                           /*                  */
+    volatile uint32_t  MAFCR0;                                 /*  MAFCR0          */
+    volatile uint8_t   dummy236[4228];                         /*                  */
+    volatile uint32_t  ARSTR;                                  /*  ARSTR           */
+    volatile uint32_t  TSU_CTRST;                              /*  TSU_CTRST       */
+    volatile uint8_t   dummy237[80];                           /*                  */
+    volatile uint32_t  TSU_VTAG0;                              /*  TSU_VTAG0       */
+    volatile uint8_t   dummy238[4];                            /*                  */
+    volatile uint32_t  TSU_ADSBSY;                             /*  TSU_ADSBSY      */
+    volatile uint32_t  TSU_TEN;                                /*  TSU_TEN         */
+    volatile uint8_t   dummy239[24];                           /*                  */
+    volatile uint32_t  TXNLCR0;                                /*  TXNLCR0         */
+    volatile uint32_t  TXALCR0;                                /*  TXALCR0         */
+    volatile uint32_t  RXNLCR0;                                /*  RXNLCR0         */
+    volatile uint32_t  RXALCR0;                                /*  RXALCR0         */
+    volatile uint8_t   dummy240[112];                          /*                  */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
+    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH1;                              /*  TSU_ADRH1       */
+    volatile uint32_t  TSU_ADRL1;                              /*  TSU_ADRL1       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH2;                              /*  TSU_ADRH2       */
+    volatile uint32_t  TSU_ADRL2;                              /*  TSU_ADRL2       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH3;                              /*  TSU_ADRH3       */
+    volatile uint32_t  TSU_ADRL3;                              /*  TSU_ADRL3       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH4;                              /*  TSU_ADRH4       */
+    volatile uint32_t  TSU_ADRL4;                              /*  TSU_ADRL4       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH5;                              /*  TSU_ADRH5       */
+    volatile uint32_t  TSU_ADRL5;                              /*  TSU_ADRL5       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH6;                              /*  TSU_ADRH6       */
+    volatile uint32_t  TSU_ADRL6;                              /*  TSU_ADRL6       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH7;                              /*  TSU_ADRH7       */
+    volatile uint32_t  TSU_ADRL7;                              /*  TSU_ADRL7       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH8;                              /*  TSU_ADRH8       */
+    volatile uint32_t  TSU_ADRL8;                              /*  TSU_ADRL8       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH9;                              /*  TSU_ADRH9       */
+    volatile uint32_t  TSU_ADRL9;                              /*  TSU_ADRL9       */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH10;                             /*  TSU_ADRH10      */
+    volatile uint32_t  TSU_ADRL10;                             /*  TSU_ADRL10      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH11;                             /*  TSU_ADRH11      */
+    volatile uint32_t  TSU_ADRL11;                             /*  TSU_ADRL11      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH12;                             /*  TSU_ADRH12      */
+    volatile uint32_t  TSU_ADRL12;                             /*  TSU_ADRL12      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH13;                             /*  TSU_ADRH13      */
+    volatile uint32_t  TSU_ADRL13;                             /*  TSU_ADRL13      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH14;                             /*  TSU_ADRH14      */
+    volatile uint32_t  TSU_ADRL14;                             /*  TSU_ADRL14      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH15;                             /*  TSU_ADRH15      */
+    volatile uint32_t  TSU_ADRL15;                             /*  TSU_ADRL15      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH16;                             /*  TSU_ADRH16      */
+    volatile uint32_t  TSU_ADRL16;                             /*  TSU_ADRL16      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH17;                             /*  TSU_ADRH17      */
+    volatile uint32_t  TSU_ADRL17;                             /*  TSU_ADRL17      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH18;                             /*  TSU_ADRH18      */
+    volatile uint32_t  TSU_ADRL18;                             /*  TSU_ADRL18      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH19;                             /*  TSU_ADRH19      */
+    volatile uint32_t  TSU_ADRL19;                             /*  TSU_ADRL19      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH20;                             /*  TSU_ADRH20      */
+    volatile uint32_t  TSU_ADRL20;                             /*  TSU_ADRL20      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH21;                             /*  TSU_ADRH21      */
+    volatile uint32_t  TSU_ADRL21;                             /*  TSU_ADRL21      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH22;                             /*  TSU_ADRH22      */
+    volatile uint32_t  TSU_ADRL22;                             /*  TSU_ADRL22      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH23;                             /*  TSU_ADRH23      */
+    volatile uint32_t  TSU_ADRL23;                             /*  TSU_ADRL23      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH24;                             /*  TSU_ADRH24      */
+    volatile uint32_t  TSU_ADRL24;                             /*  TSU_ADRL24      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH25;                             /*  TSU_ADRH25      */
+    volatile uint32_t  TSU_ADRL25;                             /*  TSU_ADRL25      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH26;                             /*  TSU_ADRH26      */
+    volatile uint32_t  TSU_ADRL26;                             /*  TSU_ADRL26      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH27;                             /*  TSU_ADRH27      */
+    volatile uint32_t  TSU_ADRL27;                             /*  TSU_ADRL27      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH28;                             /*  TSU_ADRH28      */
+    volatile uint32_t  TSU_ADRL28;                             /*  TSU_ADRL28      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH29;                             /*  TSU_ADRH29      */
+    volatile uint32_t  TSU_ADRL29;                             /*  TSU_ADRL29      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH30;                             /*  TSU_ADRH30      */
+    volatile uint32_t  TSU_ADRL30;                             /*  TSU_ADRL30      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH31;                             /*  TSU_ADRH31      */
+    volatile uint32_t  TSU_ADRL31;                             /*  TSU_ADRL31      */
+
+/* end of struct st_ether_from_tsu_adrh0 */
+} r_io_ether_t;
+
+
+typedef struct st_ether_from_tsu_adrh0
+{
+ 
+    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
+    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+} r_io_ether_from_tsu_adrh0_t;
+
+
+/* Channel array defines of ETHER (2)*/
+#ifdef  DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS
+volatile struct st_ether_from_tsu_adrh0*  ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */
+/* End of channel array defines of ETHER (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h	(revision 374)
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : flctl_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef FLCTL_IODEFINE_H
+#define FLCTL_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
+
+
+#define FLCTLFLCMNCR (FLCTL.FLCMNCR)
+#define FLCTLFLCMDCR (FLCTL.FLCMDCR)
+#define FLCTLFLCMCDR (FLCTL.FLCMCDR)
+#define FLCTLFLADR (FLCTL.FLADR)
+#define FLCTLFLDATAR (FLCTL.FLDATAR)
+#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR)
+#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR)
+#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR)
+#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT)
+#define FLCTLFLTRCR (FLCTL.FLTRCR)
+#define FLCTLFLADR2 (FLCTL.FLADR2)
+#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO)
+
+
+typedef struct st_flctl
+{
+                                                           /* FLCTL            */
+    volatile uint32_t  FLCMNCR;                                /*  FLCMNCR         */
+    volatile uint32_t  FLCMDCR;                                /*  FLCMDCR         */
+    volatile uint32_t  FLCMCDR;                                /*  FLCMCDR         */
+    volatile uint32_t  FLADR;                                  /*  FLADR           */
+    volatile uint32_t  FLDATAR;                                /*  FLDATAR         */
+    volatile uint32_t  FLDTCNTR;                               /*  FLDTCNTR        */
+    volatile uint32_t  FLINTDMACR;                             /*  FLINTDMACR      */
+    volatile uint32_t  FLBSYTMR;                               /*  FLBSYTMR        */
+    volatile uint32_t  FLBSYCNT;                               /*  FLBSYCNT        */
+    volatile uint8_t   dummy555[8];                            /*                  */
+    volatile uint8_t   FLTRCR;                                 /*  FLTRCR          */
+    volatile uint8_t   dummy556[15];                           /*                  */
+    volatile uint32_t  FLADR2;                                 /*  FLADR2          */
+    volatile uint8_t   dummy557[16];                           /*                  */
+    volatile uint32_t  FLDTFIFO;                               /*  FLDTFIFO        */
+} r_io_flctl_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h	(revision 374)
@@ -0,0 +1,1431 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : gpio_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef GPIO_IODEFINE_H
+#define GPIO_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define GPIO    (*(struct st_gpio    *)0xFCFE3004uL) /* GPIO */
+
+
+/* Start of channel array defines of GPIO */
+
+/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
+#define GPIO_FROM_PIPC1_ARRAY_COUNT  (11)
+#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \
+    &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */
+#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */
+#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */
+#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */
+#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */
+#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */
+#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */
+#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */
+#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */
+#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */
+#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */
+
+
+/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
+#define GPIO_FROM_PBDC1_ARRAY_COUNT  (11)
+#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \
+    &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */
+#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */
+#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */
+#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */
+#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */
+#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */
+#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */
+#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */
+#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */
+#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */
+#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */
+
+
+/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
+#define GPIO_FROM_PIBC1_ARRAY_COUNT  (12)
+#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \
+    &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */
+#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
+#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
+#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */
+#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */
+#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */
+#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */
+#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */
+#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */
+#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */
+#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */
+#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */
+
+
+/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
+#define GPIO_FROM_PFCAE1_ARRAY_COUNT  (11)
+#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \
+    &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */
+#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */
+#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */
+#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */
+#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */
+#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */
+#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */
+#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */
+#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */
+#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */
+#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */
+
+
+/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */
+/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
+#define GPIO_FROM_PNOT1_ARRAY_COUNT  (11)
+#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \
+    &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */
+#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */
+#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */
+#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */
+#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */
+#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */
+#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */
+#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */
+#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */
+#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */
+#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */
+
+
+/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
+#define GPIO_FROM_PFCE1_ARRAY_COUNT  (11)
+#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \
+    &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */
+#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */
+#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */
+#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */
+#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */
+#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */
+#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */
+#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */
+#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */
+#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */
+#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */
+
+
+/* Channel array defines of GPIO_FROM_PFC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
+#define GPIO_FROM_PFC1_ARRAY_COUNT  (11)
+#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \
+    &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */
+#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */
+#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */
+#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */
+#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */
+#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */
+#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */
+#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */
+#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */
+#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */
+#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */
+
+
+/* Channel array defines of GPIO_FROM_PMC0_ARRAY */
+/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
+#define GPIO_FROM_PMC0_ARRAY_COUNT  (12)
+#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \
+    &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */
+#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */
+#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */
+#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */
+#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */
+#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */
+#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */
+#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */
+#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */
+#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */
+#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */
+#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */
+
+
+/* Channel array defines of GPIO_FROM_PM1_ARRAY */
+/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
+#define GPIO_FROM_PM1_ARRAY_COUNT  (11)
+#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \
+    &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1)    /* GPIO_FROM_PM1 */
+#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2)    /* GPIO_FROM_PM2 */
+#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3)    /* GPIO_FROM_PM3 */
+#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4)    /* GPIO_FROM_PM4 */
+#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5)    /* GPIO_FROM_PM5 */
+#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6)    /* GPIO_FROM_PM6 */
+#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7)    /* GPIO_FROM_PM7 */
+#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8)    /* GPIO_FROM_PM8 */
+#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9)    /* GPIO_FROM_PM9 */
+#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10)  /* GPIO_FROM_PM10 */
+#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11)  /* GPIO_FROM_PM11 */
+
+
+/* Channel array defines of GPIO_FROM_PPR0_ARRAY */
+/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
+#define GPIO_FROM_PPR0_ARRAY_COUNT  (12)
+#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \
+    &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */
+#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */
+#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */
+#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */
+#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */
+#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */
+#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */
+#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */
+#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */
+#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */
+#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */
+#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */
+
+
+/* Channel array defines of GPIO_FROM_P1_ARRAY */
+/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
+#define GPIO_FROM_P1_ARRAY_COUNT  (11)
+#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \
+    &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1)       /* GPIO_FROM_P1 */
+#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2)       /* GPIO_FROM_P2 */
+#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3)       /* GPIO_FROM_P3 */
+#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4)       /* GPIO_FROM_P4 */
+#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5)       /* GPIO_FROM_P5 */
+#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6)       /* GPIO_FROM_P6 */
+#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7)       /* GPIO_FROM_P7 */
+#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8)       /* GPIO_FROM_P8 */
+#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9)       /* GPIO_FROM_P9 */
+#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10)     /* GPIO_FROM_P10 */
+#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11)     /* GPIO_FROM_P11 */
+
+/* End of channel array defines of GPIO */
+
+
+#define GPIOP1 (GPIO.P1)
+#define GPIOP2 (GPIO.P2)
+#define GPIOP3 (GPIO.P3)
+#define GPIOP4 (GPIO.P4)
+#define GPIOP5 (GPIO.P5)
+#define GPIOP6 (GPIO.P6)
+#define GPIOP7 (GPIO.P7)
+#define GPIOP8 (GPIO.P8)
+#define GPIOP9 (GPIO.P9)
+#define GPIOP10 (GPIO.P10)
+#define GPIOP11 (GPIO.P11)
+#define GPIOPSR1 (GPIO.PSR1)
+#define GPIOPSR2 (GPIO.PSR2)
+#define GPIOPSR3 (GPIO.PSR3)
+#define GPIOPSR4 (GPIO.PSR4)
+#define GPIOPSR5 (GPIO.PSR5)
+#define GPIOPSR6 (GPIO.PSR6)
+#define GPIOPSR7 (GPIO.PSR7)
+#define GPIOPSR8 (GPIO.PSR8)
+#define GPIOPSR9 (GPIO.PSR9)
+#define GPIOPSR10 (GPIO.PSR10)
+#define GPIOPSR11 (GPIO.PSR11)
+#define GPIOPPR0 (GPIO.PPR0)
+#define GPIOPPR1 (GPIO.PPR1)
+#define GPIOPPR2 (GPIO.PPR2)
+#define GPIOPPR3 (GPIO.PPR3)
+#define GPIOPPR4 (GPIO.PPR4)
+#define GPIOPPR5 (GPIO.PPR5)
+#define GPIOPPR6 (GPIO.PPR6)
+#define GPIOPPR7 (GPIO.PPR7)
+#define GPIOPPR8 (GPIO.PPR8)
+#define GPIOPPR9 (GPIO.PPR9)
+#define GPIOPPR10 (GPIO.PPR10)
+#define GPIOPPR11 (GPIO.PPR11)
+#define GPIOPM1 (GPIO.PM1)
+#define GPIOPM2 (GPIO.PM2)
+#define GPIOPM3 (GPIO.PM3)
+#define GPIOPM4 (GPIO.PM4)
+#define GPIOPM5 (GPIO.PM5)
+#define GPIOPM6 (GPIO.PM6)
+#define GPIOPM7 (GPIO.PM7)
+#define GPIOPM8 (GPIO.PM8)
+#define GPIOPM9 (GPIO.PM9)
+#define GPIOPM10 (GPIO.PM10)
+#define GPIOPM11 (GPIO.PM11)
+#define GPIOPMC0 (GPIO.PMC0)
+#define GPIOPMC1 (GPIO.PMC1)
+#define GPIOPMC2 (GPIO.PMC2)
+#define GPIOPMC3 (GPIO.PMC3)
+#define GPIOPMC4 (GPIO.PMC4)
+#define GPIOPMC5 (GPIO.PMC5)
+#define GPIOPMC6 (GPIO.PMC6)
+#define GPIOPMC7 (GPIO.PMC7)
+#define GPIOPMC8 (GPIO.PMC8)
+#define GPIOPMC9 (GPIO.PMC9)
+#define GPIOPMC10 (GPIO.PMC10)
+#define GPIOPMC11 (GPIO.PMC11)
+#define GPIOPFC1 (GPIO.PFC1)
+#define GPIOPFC2 (GPIO.PFC2)
+#define GPIOPFC3 (GPIO.PFC3)
+#define GPIOPFC4 (GPIO.PFC4)
+#define GPIOPFC5 (GPIO.PFC5)
+#define GPIOPFC6 (GPIO.PFC6)
+#define GPIOPFC7 (GPIO.PFC7)
+#define GPIOPFC8 (GPIO.PFC8)
+#define GPIOPFC9 (GPIO.PFC9)
+#define GPIOPFC10 (GPIO.PFC10)
+#define GPIOPFC11 (GPIO.PFC11)
+#define GPIOPFCE1 (GPIO.PFCE1)
+#define GPIOPFCE2 (GPIO.PFCE2)
+#define GPIOPFCE3 (GPIO.PFCE3)
+#define GPIOPFCE4 (GPIO.PFCE4)
+#define GPIOPFCE5 (GPIO.PFCE5)
+#define GPIOPFCE6 (GPIO.PFCE6)
+#define GPIOPFCE7 (GPIO.PFCE7)
+#define GPIOPFCE8 (GPIO.PFCE8)
+#define GPIOPFCE9 (GPIO.PFCE9)
+#define GPIOPFCE10 (GPIO.PFCE10)
+#define GPIOPFCE11 (GPIO.PFCE11)
+#define GPIOPNOT1 (GPIO.PNOT1)
+#define GPIOPNOT2 (GPIO.PNOT2)
+#define GPIOPNOT3 (GPIO.PNOT3)
+#define GPIOPNOT4 (GPIO.PNOT4)
+#define GPIOPNOT5 (GPIO.PNOT5)
+#define GPIOPNOT6 (GPIO.PNOT6)
+#define GPIOPNOT7 (GPIO.PNOT7)
+#define GPIOPNOT8 (GPIO.PNOT8)
+#define GPIOPNOT9 (GPIO.PNOT9)
+#define GPIOPNOT10 (GPIO.PNOT10)
+#define GPIOPNOT11 (GPIO.PNOT11)
+#define GPIOPMSR1 (GPIO.PMSR1)
+#define GPIOPMSR2 (GPIO.PMSR2)
+#define GPIOPMSR3 (GPIO.PMSR3)
+#define GPIOPMSR4 (GPIO.PMSR4)
+#define GPIOPMSR5 (GPIO.PMSR5)
+#define GPIOPMSR6 (GPIO.PMSR6)
+#define GPIOPMSR7 (GPIO.PMSR7)
+#define GPIOPMSR8 (GPIO.PMSR8)
+#define GPIOPMSR9 (GPIO.PMSR9)
+#define GPIOPMSR10 (GPIO.PMSR10)
+#define GPIOPMSR11 (GPIO.PMSR11)
+#define GPIOPMCSR0 (GPIO.PMCSR0)
+#define GPIOPMCSR1 (GPIO.PMCSR1)
+#define GPIOPMCSR2 (GPIO.PMCSR2)
+#define GPIOPMCSR3 (GPIO.PMCSR3)
+#define GPIOPMCSR4 (GPIO.PMCSR4)
+#define GPIOPMCSR5 (GPIO.PMCSR5)
+#define GPIOPMCSR6 (GPIO.PMCSR6)
+#define GPIOPMCSR7 (GPIO.PMCSR7)
+#define GPIOPMCSR8 (GPIO.PMCSR8)
+#define GPIOPMCSR9 (GPIO.PMCSR9)
+#define GPIOPMCSR10 (GPIO.PMCSR10)
+#define GPIOPMCSR11 (GPIO.PMCSR11)
+#define GPIOPFCAE1 (GPIO.PFCAE1)
+#define GPIOPFCAE2 (GPIO.PFCAE2)
+#define GPIOPFCAE3 (GPIO.PFCAE3)
+#define GPIOPFCAE4 (GPIO.PFCAE4)
+#define GPIOPFCAE5 (GPIO.PFCAE5)
+#define GPIOPFCAE6 (GPIO.PFCAE6)
+#define GPIOPFCAE7 (GPIO.PFCAE7)
+#define GPIOPFCAE8 (GPIO.PFCAE8)
+#define GPIOPFCAE9 (GPIO.PFCAE9)
+#define GPIOPFCAE10 (GPIO.PFCAE10)
+#define GPIOPFCAE11 (GPIO.PFCAE11)
+#define GPIOSNCR (GPIO.SNCR)
+#define GPIOPIBC0 (GPIO.PIBC0)
+#define GPIOPIBC1 (GPIO.PIBC1)
+#define GPIOPIBC2 (GPIO.PIBC2)
+#define GPIOPIBC3 (GPIO.PIBC3)
+#define GPIOPIBC4 (GPIO.PIBC4)
+#define GPIOPIBC5 (GPIO.PIBC5)
+#define GPIOPIBC6 (GPIO.PIBC6)
+#define GPIOPIBC7 (GPIO.PIBC7)
+#define GPIOPIBC8 (GPIO.PIBC8)
+#define GPIOPIBC9 (GPIO.PIBC9)
+#define GPIOPIBC10 (GPIO.PIBC10)
+#define GPIOPIBC11 (GPIO.PIBC11)
+#define GPIOPBDC1 (GPIO.PBDC1)
+#define GPIOPBDC2 (GPIO.PBDC2)
+#define GPIOPBDC3 (GPIO.PBDC3)
+#define GPIOPBDC4 (GPIO.PBDC4)
+#define GPIOPBDC5 (GPIO.PBDC5)
+#define GPIOPBDC6 (GPIO.PBDC6)
+#define GPIOPBDC7 (GPIO.PBDC7)
+#define GPIOPBDC8 (GPIO.PBDC8)
+#define GPIOPBDC9 (GPIO.PBDC9)
+#define GPIOPBDC10 (GPIO.PBDC10)
+#define GPIOPBDC11 (GPIO.PBDC11)
+#define GPIOPIPC1 (GPIO.PIPC1)
+#define GPIOPIPC2 (GPIO.PIPC2)
+#define GPIOPIPC3 (GPIO.PIPC3)
+#define GPIOPIPC4 (GPIO.PIPC4)
+#define GPIOPIPC5 (GPIO.PIPC5)
+#define GPIOPIPC6 (GPIO.PIPC6)
+#define GPIOPIPC7 (GPIO.PIPC7)
+#define GPIOPIPC8 (GPIO.PIPC8)
+#define GPIOPIPC9 (GPIO.PIPC9)
+#define GPIOPIPC10 (GPIO.PIPC10)
+#define GPIOPIPC11 (GPIO.PIPC11)
+#define GPIOJPPR0 (GPIO.JPPR0)
+#define GPIOJPMC0 (GPIO.JPMC0)
+#define GPIOJPMCSR0 (GPIO.JPMCSR0)
+#define GPIOJPIBC0 (GPIO.JPIBC0)
+
+#define GPIO_PSRn_COUNT (11)
+#define GPIO_PMSRn_COUNT (11)
+#define GPIO_PMCSRn_COUNT (12)
+
+
+typedef struct st_gpio
+{
+                                                           /* GPIO             */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy348[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P2;                                     /*  P2              */
+    volatile uint8_t   dummy349[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P3;                                     /*  P3              */
+    volatile uint8_t   dummy350[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P4;                                     /*  P4              */
+    volatile uint8_t   dummy351[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P5;                                     /*  P5              */
+    volatile uint8_t   dummy352[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P6;                                     /*  P6              */
+    volatile uint8_t   dummy353[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P7;                                     /*  P7              */
+    volatile uint8_t   dummy354[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P8;                                     /*  P8              */
+    volatile uint8_t   dummy355[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P9;                                     /*  P9              */
+    volatile uint8_t   dummy356[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P10;                                    /*  P10             */
+    volatile uint8_t   dummy357[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P11;                                    /*  P11             */
+    volatile uint8_t   dummy3580[2];                           /*                  */
+
+/* end of struct st_gpio_from_p1 */
+    volatile uint8_t   dummy3581[212];                         /*                  */
+
+/* #define GPIO_PSRn_COUNT (11) */
+    volatile uint32_t  PSR1;                                   /*  PSR1            */
+    volatile uint32_t  PSR2;                                   /*  PSR2            */
+    volatile uint32_t  PSR3;                                   /*  PSR3            */
+    volatile uint32_t  PSR4;                                   /*  PSR4            */
+    volatile uint32_t  PSR5;                                   /*  PSR5            */
+    volatile uint32_t  PSR6;                                   /*  PSR6            */
+    volatile uint32_t  PSR7;                                   /*  PSR7            */
+    volatile uint32_t  PSR8;                                   /*  PSR8            */
+    volatile uint32_t  PSR9;                                   /*  PSR9            */
+    volatile uint32_t  PSR10;                                  /*  PSR10           */
+    volatile uint32_t  PSR11;                                  /*  PSR11           */
+    volatile uint8_t   dummy359[208];                          /*                  */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy360[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR1;                                   /*  PPR1            */
+    volatile uint8_t   dummy361[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR2;                                   /*  PPR2            */
+    volatile uint8_t   dummy362[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR3;                                   /*  PPR3            */
+    volatile uint8_t   dummy363[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR4;                                   /*  PPR4            */
+    volatile uint8_t   dummy364[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR5;                                   /*  PPR5            */
+    volatile uint8_t   dummy365[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR6;                                   /*  PPR6            */
+    volatile uint8_t   dummy366[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR7;                                   /*  PPR7            */
+    volatile uint8_t   dummy367[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR8;                                   /*  PPR8            */
+    volatile uint8_t   dummy368[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR9;                                   /*  PPR9            */
+    volatile uint8_t   dummy369[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR10;                                  /*  PPR10           */
+    volatile uint8_t   dummy370[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR11;                                  /*  PPR11           */
+    volatile uint8_t   dummy3710[2];                           /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+    volatile uint8_t   dummy3711[212];                         /*                  */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy372[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM2;                                    /*  PM2             */
+    volatile uint8_t   dummy373[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM3;                                    /*  PM3             */
+    volatile uint8_t   dummy374[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM4;                                    /*  PM4             */
+    volatile uint8_t   dummy375[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM5;                                    /*  PM5             */
+    volatile uint8_t   dummy376[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM6;                                    /*  PM6             */
+    volatile uint8_t   dummy377[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM7;                                    /*  PM7             */
+    volatile uint8_t   dummy378[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM8;                                    /*  PM8             */
+    volatile uint8_t   dummy379[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM9;                                    /*  PM9             */
+    volatile uint8_t   dummy380[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM10;                                   /*  PM10            */
+    volatile uint8_t   dummy381[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM11;                                   /*  PM11            */
+    volatile uint8_t   dummy3820[2];                           /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+    volatile uint8_t   dummy3821[208];                         /*                  */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy383[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC1;                                   /*  PMC1            */
+    volatile uint8_t   dummy384[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC2;                                   /*  PMC2            */
+    volatile uint8_t   dummy385[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC3;                                   /*  PMC3            */
+    volatile uint8_t   dummy386[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC4;                                   /*  PMC4            */
+    volatile uint8_t   dummy387[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC5;                                   /*  PMC5            */
+    volatile uint8_t   dummy388[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC6;                                   /*  PMC6            */
+    volatile uint8_t   dummy389[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC7;                                   /*  PMC7            */
+    volatile uint8_t   dummy390[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC8;                                   /*  PMC8            */
+    volatile uint8_t   dummy391[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC9;                                   /*  PMC9            */
+    volatile uint8_t   dummy392[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC10;                                  /*  PMC10           */
+    volatile uint8_t   dummy393[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC11;                                  /*  PMC11           */
+    volatile uint8_t   dummy3940[2];                           /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+    volatile uint8_t   dummy3941[212];                         /*                  */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy395[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC2;                                   /*  PFC2            */
+    volatile uint8_t   dummy396[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC3;                                   /*  PFC3            */
+    volatile uint8_t   dummy397[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC4;                                   /*  PFC4            */
+    volatile uint8_t   dummy398[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC5;                                   /*  PFC5            */
+    volatile uint8_t   dummy399[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC6;                                   /*  PFC6            */
+    volatile uint8_t   dummy400[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC7;                                   /*  PFC7            */
+    volatile uint8_t   dummy401[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC8;                                   /*  PFC8            */
+    volatile uint8_t   dummy402[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC9;                                   /*  PFC9            */
+    volatile uint8_t   dummy403[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC10;                                  /*  PFC10           */
+    volatile uint8_t   dummy404[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC11;                                  /*  PFC11           */
+    volatile uint8_t   dummy4050[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+    volatile uint8_t   dummy4051[212];                         /*                  */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy406[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE2;                                  /*  PFCE2           */
+    volatile uint8_t   dummy407[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE3;                                  /*  PFCE3           */
+    volatile uint8_t   dummy408[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE4;                                  /*  PFCE4           */
+    volatile uint8_t   dummy409[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE5;                                  /*  PFCE5           */
+    volatile uint8_t   dummy410[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE6;                                  /*  PFCE6           */
+    volatile uint8_t   dummy411[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE7;                                  /*  PFCE7           */
+    volatile uint8_t   dummy412[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE8;                                  /*  PFCE8           */
+    volatile uint8_t   dummy413[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE9;                                  /*  PFCE9           */
+    volatile uint8_t   dummy414[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE10;                                 /*  PFCE10          */
+    volatile uint8_t   dummy415[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE11;                                 /*  PFCE11          */
+    volatile uint8_t   dummy4160[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+    volatile uint8_t   dummy4161[212];                         /*                  */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy417[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT2;                                  /*  PNOT2           */
+    volatile uint8_t   dummy418[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT3;                                  /*  PNOT3           */
+    volatile uint8_t   dummy419[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT4;                                  /*  PNOT4           */
+    volatile uint8_t   dummy420[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT5;                                  /*  PNOT5           */
+    volatile uint8_t   dummy421[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT6;                                  /*  PNOT6           */
+    volatile uint8_t   dummy422[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT7;                                  /*  PNOT7           */
+    volatile uint8_t   dummy423[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT8;                                  /*  PNOT8           */
+    volatile uint8_t   dummy424[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT9;                                  /*  PNOT9           */
+    volatile uint8_t   dummy425[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT10;                                 /*  PNOT10          */
+    volatile uint8_t   dummy426[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT11;                                 /*  PNOT11          */
+    volatile uint8_t   dummy4270[2];                           /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+    volatile uint8_t   dummy4271[212];                         /*                  */
+
+/* #define GPIO_PMSRn_COUNT (11) */
+    volatile uint32_t  PMSR1;                                  /*  PMSR1           */
+    volatile uint32_t  PMSR2;                                  /*  PMSR2           */
+    volatile uint32_t  PMSR3;                                  /*  PMSR3           */
+    volatile uint32_t  PMSR4;                                  /*  PMSR4           */
+    volatile uint32_t  PMSR5;                                  /*  PMSR5           */
+    volatile uint32_t  PMSR6;                                  /*  PMSR6           */
+    volatile uint32_t  PMSR7;                                  /*  PMSR7           */
+    volatile uint32_t  PMSR8;                                  /*  PMSR8           */
+    volatile uint32_t  PMSR9;                                  /*  PMSR9           */
+    volatile uint32_t  PMSR10;                                 /*  PMSR10          */
+    volatile uint32_t  PMSR11;                                 /*  PMSR11          */
+    volatile uint8_t   dummy428[208];                          /*                  */
+
+/* #define GPIO_PMCSRn_COUNT (12) */
+    volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
+    volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
+    volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
+    volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
+    volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
+    volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
+    volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
+    volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
+    volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
+    volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
+    volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
+    volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
+    volatile uint8_t   dummy429[212];                          /*                  */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy430[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
+    volatile uint8_t   dummy431[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
+    volatile uint8_t   dummy432[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
+    volatile uint8_t   dummy433[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
+    volatile uint8_t   dummy434[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
+    volatile uint8_t   dummy435[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
+    volatile uint8_t   dummy436[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
+    volatile uint8_t   dummy437[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
+    volatile uint8_t   dummy438[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE10;                                /*  PFCAE10         */
+    volatile uint8_t   dummy439[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE11;                                /*  PFCAE11         */
+    volatile uint8_t   dummy4400[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+    volatile uint8_t   dummy4401[464];                         /*                  */
+    volatile uint32_t  SNCR;                                   /*  SNCR            */
+    volatile uint8_t   dummy441[13308];                        /*                  */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC0;                                  /*  PIBC0           */
+    volatile uint8_t   dummy442[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy443[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC2;                                  /*  PIBC2           */
+    volatile uint8_t   dummy444[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC3;                                  /*  PIBC3           */
+    volatile uint8_t   dummy445[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC4;                                  /*  PIBC4           */
+    volatile uint8_t   dummy446[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC5;                                  /*  PIBC5           */
+    volatile uint8_t   dummy447[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC6;                                  /*  PIBC6           */
+    volatile uint8_t   dummy448[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC7;                                  /*  PIBC7           */
+    volatile uint8_t   dummy449[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC8;                                  /*  PIBC8           */
+    volatile uint8_t   dummy450[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC9;                                  /*  PIBC9           */
+    volatile uint8_t   dummy451[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC10;                                 /*  PIBC10          */
+    volatile uint8_t   dummy452[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC11;                                 /*  PIBC11          */
+    volatile uint8_t   dummy4530[2];                           /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+    volatile uint8_t   dummy4531[212];                         /*                  */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy454[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC2;                                  /*  PBDC2           */
+    volatile uint8_t   dummy455[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC3;                                  /*  PBDC3           */
+    volatile uint8_t   dummy456[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC4;                                  /*  PBDC4           */
+    volatile uint8_t   dummy457[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC5;                                  /*  PBDC5           */
+    volatile uint8_t   dummy458[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC6;                                  /*  PBDC6           */
+    volatile uint8_t   dummy459[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC7;                                  /*  PBDC7           */
+    volatile uint8_t   dummy460[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC8;                                  /*  PBDC8           */
+    volatile uint8_t   dummy461[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC9;                                  /*  PBDC9           */
+    volatile uint8_t   dummy462[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC10;                                 /*  PBDC10          */
+    volatile uint8_t   dummy463[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC11;                                 /*  PBDC11          */
+    volatile uint8_t   dummy4640[2];                           /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+    volatile uint8_t   dummy4641[212];                         /*                  */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy465[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC2;                                  /*  PIPC2           */
+    volatile uint8_t   dummy466[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC3;                                  /*  PIPC3           */
+    volatile uint8_t   dummy467[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC4;                                  /*  PIPC4           */
+    volatile uint8_t   dummy468[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC5;                                  /*  PIPC5           */
+    volatile uint8_t   dummy469[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC6;                                  /*  PIPC6           */
+    volatile uint8_t   dummy470[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC7;                                  /*  PIPC7           */
+    volatile uint8_t   dummy471[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC8;                                  /*  PIPC8           */
+    volatile uint8_t   dummy472[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC9;                                  /*  PIPC9           */
+    volatile uint8_t   dummy473[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC10;                                 /*  PIPC10          */
+    volatile uint8_t   dummy474[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC11;                                 /*  PIPC11          */
+    volatile uint8_t   dummy4750[2];                           /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+    volatile uint8_t   dummy4751[2288];                        /*                  */
+    volatile uint16_t JPPR0;                                  /*  JPPR0           */
+    volatile uint8_t   dummy476[30];                           /*                  */
+    volatile uint16_t JPMC0;                                  /*  JPMC0           */
+    volatile uint8_t   dummy477[78];                           /*                  */
+    volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
+    volatile uint8_t   dummy478[876];                          /*                  */
+    volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
+} r_io_gpio_t;
+
+
+typedef struct st_gpio_from_p1
+{
+ 
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_gpio_from_p1_t;
+
+
+typedef struct st_gpio_from_ppr0
+{
+ 
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_ppr0_t;
+
+
+typedef struct st_gpio_from_pm1
+{
+ 
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pm1_t;
+
+
+typedef struct st_gpio_from_pmc0
+{
+ 
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pmc0_t;
+
+
+typedef struct st_gpio_from_pfc1
+{
+ 
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfc1_t;
+
+
+typedef struct st_gpio_from_pfce1
+{
+ 
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfce1_t;
+
+
+typedef struct st_gpio_from_pnot1
+{
+ 
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pnot1_t;
+
+
+typedef struct st_gpio_from_pfcae1
+{
+ 
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfcae1_t;
+
+
+typedef struct st_gpio_from_pibc1
+{
+ 
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pibc1_t;
+
+
+typedef struct st_gpio_from_pbdc1
+{
+ 
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pbdc1_t;
+
+
+typedef struct st_gpio_from_pipc1
+{
+ 
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pipc1_t;
+
+
+/* Channel array defines of GPIO (2)*/
+#ifdef  DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pipc1*  GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pbdc1*  GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pibc1*  GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfcae1*  GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pnot1*  GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfce1*  GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfc1*  GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS
+volatile struct st_gpio_from_pmc0*  GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pm1*  GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PM1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS
+volatile struct st_gpio_from_ppr0*  GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS
+volatile struct st_gpio_from_p1*  GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_P1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */
+/* End of channel array defines of GPIO (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h	(revision 374)
@@ -0,0 +1,128 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ieb_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef IEB_IODEFINE_H
+#define IEB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
+
+
+#define IEBB0BCR (IEB.B0BCR)
+#define IEBB0PSR (IEB.B0PSR)
+#define IEBB0UAR (IEB.B0UAR)
+#define IEBB0SAR (IEB.B0SAR)
+#define IEBB0PAR (IEB.B0PAR)
+#define IEBB0RSA (IEB.B0RSA)
+#define IEBB0CDR (IEB.B0CDR)
+#define IEBB0TCD (IEB.B0TCD)
+#define IEBB0RCD (IEB.B0RCD)
+#define IEBB0DLR (IEB.B0DLR)
+#define IEBB0TDL (IEB.B0TDL)
+#define IEBB0RDL (IEB.B0RDL)
+#define IEBB0CKS (IEB.B0CKS)
+#define IEBB0TMS (IEB.B0TMS)
+#define IEBB0PCR (IEB.B0PCR)
+#define IEBB0BSR (IEB.B0BSR)
+#define IEBB0SSR (IEB.B0SSR)
+#define IEBB0USR (IEB.B0USR)
+#define IEBB0ISR (IEB.B0ISR)
+#define IEBB0ESR (IEB.B0ESR)
+#define IEBB0FSR (IEB.B0FSR)
+#define IEBB0SCR (IEB.B0SCR)
+#define IEBB0CCR (IEB.B0CCR)
+#define IEBB0STC0 (IEB.B0STC0)
+#define IEBB0STC1 (IEB.B0STC1)
+#define IEBB0DR (IEB.B0DR)
+
+
+typedef struct st_ieb
+{
+                                                           /* IEB              */
+    volatile uint8_t   B0BCR;                                  /*  B0BCR           */
+    volatile uint8_t   dummy495[3];                            /*                  */
+    volatile uint8_t   B0PSR;                                  /*  B0PSR           */
+    volatile uint8_t   dummy496[3];                            /*                  */
+    volatile uint16_t B0UAR;                                  /*  B0UAR           */
+    volatile uint8_t   dummy497[2];                            /*                  */
+    volatile uint16_t B0SAR;                                  /*  B0SAR           */
+    volatile uint8_t   dummy498[2];                            /*                  */
+    volatile uint16_t B0PAR;                                  /*  B0PAR           */
+    volatile uint8_t   dummy499[2];                            /*                  */
+    volatile uint16_t B0RSA;                                  /*  B0RSA           */
+    volatile uint8_t   dummy500[2];                            /*                  */
+    volatile uint8_t   B0CDR;                                  /*  B0CDR           */
+    volatile uint8_t   dummy501[3];                            /*                  */
+    volatile uint8_t   B0TCD;                                  /*  B0TCD           */
+    volatile uint8_t   dummy502[3];                            /*                  */
+    volatile uint8_t   B0RCD;                                  /*  B0RCD           */
+    volatile uint8_t   dummy503[3];                            /*                  */
+    volatile uint8_t   B0DLR;                                  /*  B0DLR           */
+    volatile uint8_t   dummy504[3];                            /*                  */
+    volatile uint8_t   B0TDL;                                  /*  B0TDL           */
+    volatile uint8_t   dummy505[3];                            /*                  */
+    volatile uint8_t   B0RDL;                                  /*  B0RDL           */
+    volatile uint8_t   dummy506[3];                            /*                  */
+    volatile uint8_t   B0CKS;                                  /*  B0CKS           */
+    volatile uint8_t   dummy507[3];                            /*                  */
+    volatile uint8_t   B0TMS;                                  /*  B0TMS           */
+    volatile uint8_t   dummy508[3];                            /*                  */
+    volatile uint8_t   B0PCR;                                  /*  B0PCR           */
+    volatile uint8_t   dummy509[3];                            /*                  */
+    volatile uint16_t B0BSR;                                  /*  B0BSR           */
+    volatile uint8_t   dummy510[2];                            /*                  */
+    volatile uint8_t   B0SSR;                                  /*  B0SSR           */
+    volatile uint8_t   dummy511[3];                            /*                  */
+    volatile uint8_t   B0USR;                                  /*  B0USR           */
+    volatile uint8_t   dummy512[3];                            /*                  */
+    volatile uint8_t   B0ISR;                                  /*  B0ISR           */
+    volatile uint8_t   dummy513[3];                            /*                  */
+    volatile uint8_t   B0ESR;                                  /*  B0ESR           */
+    volatile uint8_t   dummy514[3];                            /*                  */
+    volatile uint8_t   B0FSR;                                  /*  B0FSR           */
+    volatile uint8_t   dummy515[3];                            /*                  */
+    volatile uint8_t   B0SCR;                                  /*  B0SCR           */
+    volatile uint8_t   dummy516[3];                            /*                  */
+    volatile uint8_t   B0CCR;                                  /*  B0CCR           */
+    volatile uint8_t   dummy517[3];                            /*                  */
+    volatile uint8_t   B0STC0;                                 /*  B0STC0          */
+    volatile uint8_t   dummy518[3];                            /*                  */
+    volatile uint8_t   B0STC1;                                 /*  B0STC1          */
+    volatile uint8_t   dummy519[3];                            /*                  */
+    volatile uint8_t   B0DR;                                   /*  B0DR            */
+} r_io_ieb_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h	(revision 374)
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : inb_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef INB_IODEFINE_H
+#define INB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
+
+
+#define INBRMPR (INB.RMPR)
+#define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
+#define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
+#define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
+#define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
+#define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
+#define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
+#define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
+#define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
+#define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
+#define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
+#define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
+#define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
+#define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
+#define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
+#define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
+#define INBAXIRERRST0 (INB.AXIRERRST0)
+#define INBAXIRERRST1 (INB.AXIRERRST1)
+#define INBAXIRERRST2 (INB.AXIRERRST2)
+#define INBAXIRERRST3 (INB.AXIRERRST3)
+#define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
+#define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
+#define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
+#define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
+
+#define INB_AXIBUSCTLn_COUNT (11)
+#define INB_AXIRERRCTLn_COUNT (4)
+#define INB_AXIRERRSTn_COUNT (4)
+#define INB_AXIRERRCLRn_COUNT (4)
+
+
+typedef struct st_inb
+{
+                                                           /* INB              */
+    volatile uint32_t  RMPR;                                   /*  RMPR            */
+
+/* #define INB_AXIBUSCTLn_COUNT (11) */
+    volatile uint32_t  AXIBUSCTL0;                             /*  AXIBUSCTL0      */
+    volatile uint32_t  AXIBUSCTL1;                             /*  AXIBUSCTL1      */
+    volatile uint32_t  AXIBUSCTL2;                             /*  AXIBUSCTL2      */
+    volatile uint32_t  AXIBUSCTL3;                             /*  AXIBUSCTL3      */
+    volatile uint32_t  AXIBUSCTL4;                             /*  AXIBUSCTL4      */
+    volatile uint32_t  AXIBUSCTL5;                             /*  AXIBUSCTL5      */
+    volatile uint32_t  AXIBUSCTL6;                             /*  AXIBUSCTL6      */
+    volatile uint32_t  AXIBUSCTL7;                             /*  AXIBUSCTL7      */
+    volatile uint32_t  AXIBUSCTL8;                             /*  AXIBUSCTL8      */
+    volatile uint32_t  AXIBUSCTL9;                             /*  AXIBUSCTL9      */
+    volatile uint32_t  AXIBUSCTL10;                            /*  AXIBUSCTL10     */
+
+/* #define INB_AXIRERRCTLn_COUNT (4) */
+    volatile uint32_t  AXIRERRCTL0;                            /*  AXIRERRCTL0     */
+    volatile uint32_t  AXIRERRCTL1;                            /*  AXIRERRCTL1     */
+    volatile uint32_t  AXIRERRCTL2;                            /*  AXIRERRCTL2     */
+    volatile uint32_t  AXIRERRCTL3;                            /*  AXIRERRCTL3     */
+
+/* #define INB_AXIRERRSTn_COUNT (4) */
+    volatile uint32_t  AXIRERRST0;                             /*  AXIRERRST0      */
+    volatile uint32_t  AXIRERRST1;                             /*  AXIRERRST1      */
+    volatile uint32_t  AXIRERRST2;                             /*  AXIRERRST2      */
+    volatile uint32_t  AXIRERRST3;                             /*  AXIRERRST3      */
+
+/* #define INB_AXIRERRCLRn_COUNT (4) */
+    volatile uint32_t  AXIRERRCLR0;                            /*  AXIRERRCLR0     */
+    volatile uint32_t  AXIRERRCLR1;                            /*  AXIRERRCLR1     */
+    volatile uint32_t  AXIRERRCLR2;                            /*  AXIRERRCLR2     */
+    volatile uint32_t  AXIRERRCLR3;                            /*  AXIRERRCLR3     */
+} r_io_inb_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h	(revision 374)
@@ -0,0 +1,1054 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef INTC_IODEFINE_H
+#define INTC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
+
+
+#define INTCICDDCR (INTC.ICDDCR)
+#define INTCICDICTR (INTC.ICDICTR)
+#define INTCICDIIDR (INTC.ICDIIDR)
+#define INTCICDISR0 (INTC.ICDISR0)
+#define INTCICDISR1 (INTC.ICDISR1)
+#define INTCICDISR2 (INTC.ICDISR2)
+#define INTCICDISR3 (INTC.ICDISR3)
+#define INTCICDISR4 (INTC.ICDISR4)
+#define INTCICDISR5 (INTC.ICDISR5)
+#define INTCICDISR6 (INTC.ICDISR6)
+#define INTCICDISR7 (INTC.ICDISR7)
+#define INTCICDISR8 (INTC.ICDISR8)
+#define INTCICDISR9 (INTC.ICDISR9)
+#define INTCICDISR10 (INTC.ICDISR10)
+#define INTCICDISR11 (INTC.ICDISR11)
+#define INTCICDISR12 (INTC.ICDISR12)
+#define INTCICDISR13 (INTC.ICDISR13)
+#define INTCICDISR14 (INTC.ICDISR14)
+#define INTCICDISR15 (INTC.ICDISR15)
+#define INTCICDISR16 (INTC.ICDISR16)
+#define INTCICDISR17 (INTC.ICDISR17)
+#define INTCICDISR18 (INTC.ICDISR18)
+#define INTCICDISER0 (INTC.ICDISER0)
+#define INTCICDISER1 (INTC.ICDISER1)
+#define INTCICDISER2 (INTC.ICDISER2)
+#define INTCICDISER3 (INTC.ICDISER3)
+#define INTCICDISER4 (INTC.ICDISER4)
+#define INTCICDISER5 (INTC.ICDISER5)
+#define INTCICDISER6 (INTC.ICDISER6)
+#define INTCICDISER7 (INTC.ICDISER7)
+#define INTCICDISER8 (INTC.ICDISER8)
+#define INTCICDISER9 (INTC.ICDISER9)
+#define INTCICDISER10 (INTC.ICDISER10)
+#define INTCICDISER11 (INTC.ICDISER11)
+#define INTCICDISER12 (INTC.ICDISER12)
+#define INTCICDISER13 (INTC.ICDISER13)
+#define INTCICDISER14 (INTC.ICDISER14)
+#define INTCICDISER15 (INTC.ICDISER15)
+#define INTCICDISER16 (INTC.ICDISER16)
+#define INTCICDISER17 (INTC.ICDISER17)
+#define INTCICDISER18 (INTC.ICDISER18)
+#define INTCICDICER0 (INTC.ICDICER0)
+#define INTCICDICER1 (INTC.ICDICER1)
+#define INTCICDICER2 (INTC.ICDICER2)
+#define INTCICDICER3 (INTC.ICDICER3)
+#define INTCICDICER4 (INTC.ICDICER4)
+#define INTCICDICER5 (INTC.ICDICER5)
+#define INTCICDICER6 (INTC.ICDICER6)
+#define INTCICDICER7 (INTC.ICDICER7)
+#define INTCICDICER8 (INTC.ICDICER8)
+#define INTCICDICER9 (INTC.ICDICER9)
+#define INTCICDICER10 (INTC.ICDICER10)
+#define INTCICDICER11 (INTC.ICDICER11)
+#define INTCICDICER12 (INTC.ICDICER12)
+#define INTCICDICER13 (INTC.ICDICER13)
+#define INTCICDICER14 (INTC.ICDICER14)
+#define INTCICDICER15 (INTC.ICDICER15)
+#define INTCICDICER16 (INTC.ICDICER16)
+#define INTCICDICER17 (INTC.ICDICER17)
+#define INTCICDICER18 (INTC.ICDICER18)
+#define INTCICDISPR0 (INTC.ICDISPR0)
+#define INTCICDISPR1 (INTC.ICDISPR1)
+#define INTCICDISPR2 (INTC.ICDISPR2)
+#define INTCICDISPR3 (INTC.ICDISPR3)
+#define INTCICDISPR4 (INTC.ICDISPR4)
+#define INTCICDISPR5 (INTC.ICDISPR5)
+#define INTCICDISPR6 (INTC.ICDISPR6)
+#define INTCICDISPR7 (INTC.ICDISPR7)
+#define INTCICDISPR8 (INTC.ICDISPR8)
+#define INTCICDISPR9 (INTC.ICDISPR9)
+#define INTCICDISPR10 (INTC.ICDISPR10)
+#define INTCICDISPR11 (INTC.ICDISPR11)
+#define INTCICDISPR12 (INTC.ICDISPR12)
+#define INTCICDISPR13 (INTC.ICDISPR13)
+#define INTCICDISPR14 (INTC.ICDISPR14)
+#define INTCICDISPR15 (INTC.ICDISPR15)
+#define INTCICDISPR16 (INTC.ICDISPR16)
+#define INTCICDISPR17 (INTC.ICDISPR17)
+#define INTCICDISPR18 (INTC.ICDISPR18)
+#define INTCICDICPR0 (INTC.ICDICPR0)
+#define INTCICDICPR1 (INTC.ICDICPR1)
+#define INTCICDICPR2 (INTC.ICDICPR2)
+#define INTCICDICPR3 (INTC.ICDICPR3)
+#define INTCICDICPR4 (INTC.ICDICPR4)
+#define INTCICDICPR5 (INTC.ICDICPR5)
+#define INTCICDICPR6 (INTC.ICDICPR6)
+#define INTCICDICPR7 (INTC.ICDICPR7)
+#define INTCICDICPR8 (INTC.ICDICPR8)
+#define INTCICDICPR9 (INTC.ICDICPR9)
+#define INTCICDICPR10 (INTC.ICDICPR10)
+#define INTCICDICPR11 (INTC.ICDICPR11)
+#define INTCICDICPR12 (INTC.ICDICPR12)
+#define INTCICDICPR13 (INTC.ICDICPR13)
+#define INTCICDICPR14 (INTC.ICDICPR14)
+#define INTCICDICPR15 (INTC.ICDICPR15)
+#define INTCICDICPR16 (INTC.ICDICPR16)
+#define INTCICDICPR17 (INTC.ICDICPR17)
+#define INTCICDICPR18 (INTC.ICDICPR18)
+#define INTCICDABR0 (INTC.ICDABR0)
+#define INTCICDABR1 (INTC.ICDABR1)
+#define INTCICDABR2 (INTC.ICDABR2)
+#define INTCICDABR3 (INTC.ICDABR3)
+#define INTCICDABR4 (INTC.ICDABR4)
+#define INTCICDABR5 (INTC.ICDABR5)
+#define INTCICDABR6 (INTC.ICDABR6)
+#define INTCICDABR7 (INTC.ICDABR7)
+#define INTCICDABR8 (INTC.ICDABR8)
+#define INTCICDABR9 (INTC.ICDABR9)
+#define INTCICDABR10 (INTC.ICDABR10)
+#define INTCICDABR11 (INTC.ICDABR11)
+#define INTCICDABR12 (INTC.ICDABR12)
+#define INTCICDABR13 (INTC.ICDABR13)
+#define INTCICDABR14 (INTC.ICDABR14)
+#define INTCICDABR15 (INTC.ICDABR15)
+#define INTCICDABR16 (INTC.ICDABR16)
+#define INTCICDABR17 (INTC.ICDABR17)
+#define INTCICDABR18 (INTC.ICDABR18)
+#define INTCICDIPR0 (INTC.ICDIPR0)
+#define INTCICDIPR1 (INTC.ICDIPR1)
+#define INTCICDIPR2 (INTC.ICDIPR2)
+#define INTCICDIPR3 (INTC.ICDIPR3)
+#define INTCICDIPR4 (INTC.ICDIPR4)
+#define INTCICDIPR5 (INTC.ICDIPR5)
+#define INTCICDIPR6 (INTC.ICDIPR6)
+#define INTCICDIPR7 (INTC.ICDIPR7)
+#define INTCICDIPR8 (INTC.ICDIPR8)
+#define INTCICDIPR9 (INTC.ICDIPR9)
+#define INTCICDIPR10 (INTC.ICDIPR10)
+#define INTCICDIPR11 (INTC.ICDIPR11)
+#define INTCICDIPR12 (INTC.ICDIPR12)
+#define INTCICDIPR13 (INTC.ICDIPR13)
+#define INTCICDIPR14 (INTC.ICDIPR14)
+#define INTCICDIPR15 (INTC.ICDIPR15)
+#define INTCICDIPR16 (INTC.ICDIPR16)
+#define INTCICDIPR17 (INTC.ICDIPR17)
+#define INTCICDIPR18 (INTC.ICDIPR18)
+#define INTCICDIPR19 (INTC.ICDIPR19)
+#define INTCICDIPR20 (INTC.ICDIPR20)
+#define INTCICDIPR21 (INTC.ICDIPR21)
+#define INTCICDIPR22 (INTC.ICDIPR22)
+#define INTCICDIPR23 (INTC.ICDIPR23)
+#define INTCICDIPR24 (INTC.ICDIPR24)
+#define INTCICDIPR25 (INTC.ICDIPR25)
+#define INTCICDIPR26 (INTC.ICDIPR26)
+#define INTCICDIPR27 (INTC.ICDIPR27)
+#define INTCICDIPR28 (INTC.ICDIPR28)
+#define INTCICDIPR29 (INTC.ICDIPR29)
+#define INTCICDIPR30 (INTC.ICDIPR30)
+#define INTCICDIPR31 (INTC.ICDIPR31)
+#define INTCICDIPR32 (INTC.ICDIPR32)
+#define INTCICDIPR33 (INTC.ICDIPR33)
+#define INTCICDIPR34 (INTC.ICDIPR34)
+#define INTCICDIPR35 (INTC.ICDIPR35)
+#define INTCICDIPR36 (INTC.ICDIPR36)
+#define INTCICDIPR37 (INTC.ICDIPR37)
+#define INTCICDIPR38 (INTC.ICDIPR38)
+#define INTCICDIPR39 (INTC.ICDIPR39)
+#define INTCICDIPR40 (INTC.ICDIPR40)
+#define INTCICDIPR41 (INTC.ICDIPR41)
+#define INTCICDIPR42 (INTC.ICDIPR42)
+#define INTCICDIPR43 (INTC.ICDIPR43)
+#define INTCICDIPR44 (INTC.ICDIPR44)
+#define INTCICDIPR45 (INTC.ICDIPR45)
+#define INTCICDIPR46 (INTC.ICDIPR46)
+#define INTCICDIPR47 (INTC.ICDIPR47)
+#define INTCICDIPR48 (INTC.ICDIPR48)
+#define INTCICDIPR49 (INTC.ICDIPR49)
+#define INTCICDIPR50 (INTC.ICDIPR50)
+#define INTCICDIPR51 (INTC.ICDIPR51)
+#define INTCICDIPR52 (INTC.ICDIPR52)
+#define INTCICDIPR53 (INTC.ICDIPR53)
+#define INTCICDIPR54 (INTC.ICDIPR54)
+#define INTCICDIPR55 (INTC.ICDIPR55)
+#define INTCICDIPR56 (INTC.ICDIPR56)
+#define INTCICDIPR57 (INTC.ICDIPR57)
+#define INTCICDIPR58 (INTC.ICDIPR58)
+#define INTCICDIPR59 (INTC.ICDIPR59)
+#define INTCICDIPR60 (INTC.ICDIPR60)
+#define INTCICDIPR61 (INTC.ICDIPR61)
+#define INTCICDIPR62 (INTC.ICDIPR62)
+#define INTCICDIPR63 (INTC.ICDIPR63)
+#define INTCICDIPR64 (INTC.ICDIPR64)
+#define INTCICDIPR65 (INTC.ICDIPR65)
+#define INTCICDIPR66 (INTC.ICDIPR66)
+#define INTCICDIPR67 (INTC.ICDIPR67)
+#define INTCICDIPR68 (INTC.ICDIPR68)
+#define INTCICDIPR69 (INTC.ICDIPR69)
+#define INTCICDIPR70 (INTC.ICDIPR70)
+#define INTCICDIPR71 (INTC.ICDIPR71)
+#define INTCICDIPR72 (INTC.ICDIPR72)
+#define INTCICDIPR73 (INTC.ICDIPR73)
+#define INTCICDIPR74 (INTC.ICDIPR74)
+#define INTCICDIPR75 (INTC.ICDIPR75)
+#define INTCICDIPR76 (INTC.ICDIPR76)
+#define INTCICDIPR77 (INTC.ICDIPR77)
+#define INTCICDIPR78 (INTC.ICDIPR78)
+#define INTCICDIPR79 (INTC.ICDIPR79)
+#define INTCICDIPR80 (INTC.ICDIPR80)
+#define INTCICDIPR81 (INTC.ICDIPR81)
+#define INTCICDIPR82 (INTC.ICDIPR82)
+#define INTCICDIPR83 (INTC.ICDIPR83)
+#define INTCICDIPR84 (INTC.ICDIPR84)
+#define INTCICDIPR85 (INTC.ICDIPR85)
+#define INTCICDIPR86 (INTC.ICDIPR86)
+#define INTCICDIPR87 (INTC.ICDIPR87)
+#define INTCICDIPR88 (INTC.ICDIPR88)
+#define INTCICDIPR89 (INTC.ICDIPR89)
+#define INTCICDIPR90 (INTC.ICDIPR90)
+#define INTCICDIPR91 (INTC.ICDIPR91)
+#define INTCICDIPR92 (INTC.ICDIPR92)
+#define INTCICDIPR93 (INTC.ICDIPR93)
+#define INTCICDIPR94 (INTC.ICDIPR94)
+#define INTCICDIPR95 (INTC.ICDIPR95)
+#define INTCICDIPR96 (INTC.ICDIPR96)
+#define INTCICDIPR97 (INTC.ICDIPR97)
+#define INTCICDIPR98 (INTC.ICDIPR98)
+#define INTCICDIPR99 (INTC.ICDIPR99)
+#define INTCICDIPR100 (INTC.ICDIPR100)
+#define INTCICDIPR101 (INTC.ICDIPR101)
+#define INTCICDIPR102 (INTC.ICDIPR102)
+#define INTCICDIPR103 (INTC.ICDIPR103)
+#define INTCICDIPR104 (INTC.ICDIPR104)
+#define INTCICDIPR105 (INTC.ICDIPR105)
+#define INTCICDIPR106 (INTC.ICDIPR106)
+#define INTCICDIPR107 (INTC.ICDIPR107)
+#define INTCICDIPR108 (INTC.ICDIPR108)
+#define INTCICDIPR109 (INTC.ICDIPR109)
+#define INTCICDIPR110 (INTC.ICDIPR110)
+#define INTCICDIPR111 (INTC.ICDIPR111)
+#define INTCICDIPR112 (INTC.ICDIPR112)
+#define INTCICDIPR113 (INTC.ICDIPR113)
+#define INTCICDIPR114 (INTC.ICDIPR114)
+#define INTCICDIPR115 (INTC.ICDIPR115)
+#define INTCICDIPR116 (INTC.ICDIPR116)
+#define INTCICDIPR117 (INTC.ICDIPR117)
+#define INTCICDIPR118 (INTC.ICDIPR118)
+#define INTCICDIPR119 (INTC.ICDIPR119)
+#define INTCICDIPR120 (INTC.ICDIPR120)
+#define INTCICDIPR121 (INTC.ICDIPR121)
+#define INTCICDIPR122 (INTC.ICDIPR122)
+#define INTCICDIPR123 (INTC.ICDIPR123)
+#define INTCICDIPR124 (INTC.ICDIPR124)
+#define INTCICDIPR125 (INTC.ICDIPR125)
+#define INTCICDIPR126 (INTC.ICDIPR126)
+#define INTCICDIPR127 (INTC.ICDIPR127)
+#define INTCICDIPR128 (INTC.ICDIPR128)
+#define INTCICDIPR129 (INTC.ICDIPR129)
+#define INTCICDIPR130 (INTC.ICDIPR130)
+#define INTCICDIPR131 (INTC.ICDIPR131)
+#define INTCICDIPR132 (INTC.ICDIPR132)
+#define INTCICDIPR133 (INTC.ICDIPR133)
+#define INTCICDIPR134 (INTC.ICDIPR134)
+#define INTCICDIPR135 (INTC.ICDIPR135)
+#define INTCICDIPR136 (INTC.ICDIPR136)
+#define INTCICDIPR137 (INTC.ICDIPR137)
+#define INTCICDIPR138 (INTC.ICDIPR138)
+#define INTCICDIPR139 (INTC.ICDIPR139)
+#define INTCICDIPR140 (INTC.ICDIPR140)
+#define INTCICDIPR141 (INTC.ICDIPR141)
+#define INTCICDIPR142 (INTC.ICDIPR142)
+#define INTCICDIPR143 (INTC.ICDIPR143)
+#define INTCICDIPR144 (INTC.ICDIPR144)
+#define INTCICDIPR145 (INTC.ICDIPR145)
+#define INTCICDIPR146 (INTC.ICDIPR146)
+#define INTCICDIPTR0 (INTC.ICDIPTR0)
+#define INTCICDIPTR1 (INTC.ICDIPTR1)
+#define INTCICDIPTR2 (INTC.ICDIPTR2)
+#define INTCICDIPTR3 (INTC.ICDIPTR3)
+#define INTCICDIPTR4 (INTC.ICDIPTR4)
+#define INTCICDIPTR5 (INTC.ICDIPTR5)
+#define INTCICDIPTR6 (INTC.ICDIPTR6)
+#define INTCICDIPTR7 (INTC.ICDIPTR7)
+#define INTCICDIPTR8 (INTC.ICDIPTR8)
+#define INTCICDIPTR9 (INTC.ICDIPTR9)
+#define INTCICDIPTR10 (INTC.ICDIPTR10)
+#define INTCICDIPTR11 (INTC.ICDIPTR11)
+#define INTCICDIPTR12 (INTC.ICDIPTR12)
+#define INTCICDIPTR13 (INTC.ICDIPTR13)
+#define INTCICDIPTR14 (INTC.ICDIPTR14)
+#define INTCICDIPTR15 (INTC.ICDIPTR15)
+#define INTCICDIPTR16 (INTC.ICDIPTR16)
+#define INTCICDIPTR17 (INTC.ICDIPTR17)
+#define INTCICDIPTR18 (INTC.ICDIPTR18)
+#define INTCICDIPTR19 (INTC.ICDIPTR19)
+#define INTCICDIPTR20 (INTC.ICDIPTR20)
+#define INTCICDIPTR21 (INTC.ICDIPTR21)
+#define INTCICDIPTR22 (INTC.ICDIPTR22)
+#define INTCICDIPTR23 (INTC.ICDIPTR23)
+#define INTCICDIPTR24 (INTC.ICDIPTR24)
+#define INTCICDIPTR25 (INTC.ICDIPTR25)
+#define INTCICDIPTR26 (INTC.ICDIPTR26)
+#define INTCICDIPTR27 (INTC.ICDIPTR27)
+#define INTCICDIPTR28 (INTC.ICDIPTR28)
+#define INTCICDIPTR29 (INTC.ICDIPTR29)
+#define INTCICDIPTR30 (INTC.ICDIPTR30)
+#define INTCICDIPTR31 (INTC.ICDIPTR31)
+#define INTCICDIPTR32 (INTC.ICDIPTR32)
+#define INTCICDIPTR33 (INTC.ICDIPTR33)
+#define INTCICDIPTR34 (INTC.ICDIPTR34)
+#define INTCICDIPTR35 (INTC.ICDIPTR35)
+#define INTCICDIPTR36 (INTC.ICDIPTR36)
+#define INTCICDIPTR37 (INTC.ICDIPTR37)
+#define INTCICDIPTR38 (INTC.ICDIPTR38)
+#define INTCICDIPTR39 (INTC.ICDIPTR39)
+#define INTCICDIPTR40 (INTC.ICDIPTR40)
+#define INTCICDIPTR41 (INTC.ICDIPTR41)
+#define INTCICDIPTR42 (INTC.ICDIPTR42)
+#define INTCICDIPTR43 (INTC.ICDIPTR43)
+#define INTCICDIPTR44 (INTC.ICDIPTR44)
+#define INTCICDIPTR45 (INTC.ICDIPTR45)
+#define INTCICDIPTR46 (INTC.ICDIPTR46)
+#define INTCICDIPTR47 (INTC.ICDIPTR47)
+#define INTCICDIPTR48 (INTC.ICDIPTR48)
+#define INTCICDIPTR49 (INTC.ICDIPTR49)
+#define INTCICDIPTR50 (INTC.ICDIPTR50)
+#define INTCICDIPTR51 (INTC.ICDIPTR51)
+#define INTCICDIPTR52 (INTC.ICDIPTR52)
+#define INTCICDIPTR53 (INTC.ICDIPTR53)
+#define INTCICDIPTR54 (INTC.ICDIPTR54)
+#define INTCICDIPTR55 (INTC.ICDIPTR55)
+#define INTCICDIPTR56 (INTC.ICDIPTR56)
+#define INTCICDIPTR57 (INTC.ICDIPTR57)
+#define INTCICDIPTR58 (INTC.ICDIPTR58)
+#define INTCICDIPTR59 (INTC.ICDIPTR59)
+#define INTCICDIPTR60 (INTC.ICDIPTR60)
+#define INTCICDIPTR61 (INTC.ICDIPTR61)
+#define INTCICDIPTR62 (INTC.ICDIPTR62)
+#define INTCICDIPTR63 (INTC.ICDIPTR63)
+#define INTCICDIPTR64 (INTC.ICDIPTR64)
+#define INTCICDIPTR65 (INTC.ICDIPTR65)
+#define INTCICDIPTR66 (INTC.ICDIPTR66)
+#define INTCICDIPTR67 (INTC.ICDIPTR67)
+#define INTCICDIPTR68 (INTC.ICDIPTR68)
+#define INTCICDIPTR69 (INTC.ICDIPTR69)
+#define INTCICDIPTR70 (INTC.ICDIPTR70)
+#define INTCICDIPTR71 (INTC.ICDIPTR71)
+#define INTCICDIPTR72 (INTC.ICDIPTR72)
+#define INTCICDIPTR73 (INTC.ICDIPTR73)
+#define INTCICDIPTR74 (INTC.ICDIPTR74)
+#define INTCICDIPTR75 (INTC.ICDIPTR75)
+#define INTCICDIPTR76 (INTC.ICDIPTR76)
+#define INTCICDIPTR77 (INTC.ICDIPTR77)
+#define INTCICDIPTR78 (INTC.ICDIPTR78)
+#define INTCICDIPTR79 (INTC.ICDIPTR79)
+#define INTCICDIPTR80 (INTC.ICDIPTR80)
+#define INTCICDIPTR81 (INTC.ICDIPTR81)
+#define INTCICDIPTR82 (INTC.ICDIPTR82)
+#define INTCICDIPTR83 (INTC.ICDIPTR83)
+#define INTCICDIPTR84 (INTC.ICDIPTR84)
+#define INTCICDIPTR85 (INTC.ICDIPTR85)
+#define INTCICDIPTR86 (INTC.ICDIPTR86)
+#define INTCICDIPTR87 (INTC.ICDIPTR87)
+#define INTCICDIPTR88 (INTC.ICDIPTR88)
+#define INTCICDIPTR89 (INTC.ICDIPTR89)
+#define INTCICDIPTR90 (INTC.ICDIPTR90)
+#define INTCICDIPTR91 (INTC.ICDIPTR91)
+#define INTCICDIPTR92 (INTC.ICDIPTR92)
+#define INTCICDIPTR93 (INTC.ICDIPTR93)
+#define INTCICDIPTR94 (INTC.ICDIPTR94)
+#define INTCICDIPTR95 (INTC.ICDIPTR95)
+#define INTCICDIPTR96 (INTC.ICDIPTR96)
+#define INTCICDIPTR97 (INTC.ICDIPTR97)
+#define INTCICDIPTR98 (INTC.ICDIPTR98)
+#define INTCICDIPTR99 (INTC.ICDIPTR99)
+#define INTCICDIPTR100 (INTC.ICDIPTR100)
+#define INTCICDIPTR101 (INTC.ICDIPTR101)
+#define INTCICDIPTR102 (INTC.ICDIPTR102)
+#define INTCICDIPTR103 (INTC.ICDIPTR103)
+#define INTCICDIPTR104 (INTC.ICDIPTR104)
+#define INTCICDIPTR105 (INTC.ICDIPTR105)
+#define INTCICDIPTR106 (INTC.ICDIPTR106)
+#define INTCICDIPTR107 (INTC.ICDIPTR107)
+#define INTCICDIPTR108 (INTC.ICDIPTR108)
+#define INTCICDIPTR109 (INTC.ICDIPTR109)
+#define INTCICDIPTR110 (INTC.ICDIPTR110)
+#define INTCICDIPTR111 (INTC.ICDIPTR111)
+#define INTCICDIPTR112 (INTC.ICDIPTR112)
+#define INTCICDIPTR113 (INTC.ICDIPTR113)
+#define INTCICDIPTR114 (INTC.ICDIPTR114)
+#define INTCICDIPTR115 (INTC.ICDIPTR115)
+#define INTCICDIPTR116 (INTC.ICDIPTR116)
+#define INTCICDIPTR117 (INTC.ICDIPTR117)
+#define INTCICDIPTR118 (INTC.ICDIPTR118)
+#define INTCICDIPTR119 (INTC.ICDIPTR119)
+#define INTCICDIPTR120 (INTC.ICDIPTR120)
+#define INTCICDIPTR121 (INTC.ICDIPTR121)
+#define INTCICDIPTR122 (INTC.ICDIPTR122)
+#define INTCICDIPTR123 (INTC.ICDIPTR123)
+#define INTCICDIPTR124 (INTC.ICDIPTR124)
+#define INTCICDIPTR125 (INTC.ICDIPTR125)
+#define INTCICDIPTR126 (INTC.ICDIPTR126)
+#define INTCICDIPTR127 (INTC.ICDIPTR127)
+#define INTCICDIPTR128 (INTC.ICDIPTR128)
+#define INTCICDIPTR129 (INTC.ICDIPTR129)
+#define INTCICDIPTR130 (INTC.ICDIPTR130)
+#define INTCICDIPTR131 (INTC.ICDIPTR131)
+#define INTCICDIPTR132 (INTC.ICDIPTR132)
+#define INTCICDIPTR133 (INTC.ICDIPTR133)
+#define INTCICDIPTR134 (INTC.ICDIPTR134)
+#define INTCICDIPTR135 (INTC.ICDIPTR135)
+#define INTCICDIPTR136 (INTC.ICDIPTR136)
+#define INTCICDIPTR137 (INTC.ICDIPTR137)
+#define INTCICDIPTR138 (INTC.ICDIPTR138)
+#define INTCICDIPTR139 (INTC.ICDIPTR139)
+#define INTCICDIPTR140 (INTC.ICDIPTR140)
+#define INTCICDIPTR141 (INTC.ICDIPTR141)
+#define INTCICDIPTR142 (INTC.ICDIPTR142)
+#define INTCICDIPTR143 (INTC.ICDIPTR143)
+#define INTCICDIPTR144 (INTC.ICDIPTR144)
+#define INTCICDIPTR145 (INTC.ICDIPTR145)
+#define INTCICDIPTR146 (INTC.ICDIPTR146)
+#define INTCICDICFR0 (INTC.ICDICFR0)
+#define INTCICDICFR1 (INTC.ICDICFR1)
+#define INTCICDICFR2 (INTC.ICDICFR2)
+#define INTCICDICFR3 (INTC.ICDICFR3)
+#define INTCICDICFR4 (INTC.ICDICFR4)
+#define INTCICDICFR5 (INTC.ICDICFR5)
+#define INTCICDICFR6 (INTC.ICDICFR6)
+#define INTCICDICFR7 (INTC.ICDICFR7)
+#define INTCICDICFR8 (INTC.ICDICFR8)
+#define INTCICDICFR9 (INTC.ICDICFR9)
+#define INTCICDICFR10 (INTC.ICDICFR10)
+#define INTCICDICFR11 (INTC.ICDICFR11)
+#define INTCICDICFR12 (INTC.ICDICFR12)
+#define INTCICDICFR13 (INTC.ICDICFR13)
+#define INTCICDICFR14 (INTC.ICDICFR14)
+#define INTCICDICFR15 (INTC.ICDICFR15)
+#define INTCICDICFR16 (INTC.ICDICFR16)
+#define INTCICDICFR17 (INTC.ICDICFR17)
+#define INTCICDICFR18 (INTC.ICDICFR18)
+#define INTCICDICFR19 (INTC.ICDICFR19)
+#define INTCICDICFR20 (INTC.ICDICFR20)
+#define INTCICDICFR21 (INTC.ICDICFR21)
+#define INTCICDICFR22 (INTC.ICDICFR22)
+#define INTCICDICFR23 (INTC.ICDICFR23)
+#define INTCICDICFR24 (INTC.ICDICFR24)
+#define INTCICDICFR25 (INTC.ICDICFR25)
+#define INTCICDICFR26 (INTC.ICDICFR26)
+#define INTCICDICFR27 (INTC.ICDICFR27)
+#define INTCICDICFR28 (INTC.ICDICFR28)
+#define INTCICDICFR29 (INTC.ICDICFR29)
+#define INTCICDICFR30 (INTC.ICDICFR30)
+#define INTCICDICFR31 (INTC.ICDICFR31)
+#define INTCICDICFR32 (INTC.ICDICFR32)
+#define INTCICDICFR33 (INTC.ICDICFR33)
+#define INTCICDICFR34 (INTC.ICDICFR34)
+#define INTCICDICFR35 (INTC.ICDICFR35)
+#define INTCICDICFR36 (INTC.ICDICFR36)
+#define INTCPPI_STATUS (INTC.PPI_STATUS)
+#define INTCSPI_STATUS0 (INTC.SPI_STATUS0)
+#define INTCSPI_STATUS1 (INTC.SPI_STATUS1)
+#define INTCSPI_STATUS2 (INTC.SPI_STATUS2)
+#define INTCSPI_STATUS3 (INTC.SPI_STATUS3)
+#define INTCSPI_STATUS4 (INTC.SPI_STATUS4)
+#define INTCSPI_STATUS5 (INTC.SPI_STATUS5)
+#define INTCSPI_STATUS6 (INTC.SPI_STATUS6)
+#define INTCSPI_STATUS7 (INTC.SPI_STATUS7)
+#define INTCSPI_STATUS8 (INTC.SPI_STATUS8)
+#define INTCSPI_STATUS9 (INTC.SPI_STATUS9)
+#define INTCSPI_STATUS10 (INTC.SPI_STATUS10)
+#define INTCSPI_STATUS11 (INTC.SPI_STATUS11)
+#define INTCSPI_STATUS12 (INTC.SPI_STATUS12)
+#define INTCSPI_STATUS13 (INTC.SPI_STATUS13)
+#define INTCSPI_STATUS14 (INTC.SPI_STATUS14)
+#define INTCSPI_STATUS15 (INTC.SPI_STATUS15)
+#define INTCSPI_STATUS16 (INTC.SPI_STATUS16)
+#define INTCICDSGIR (INTC.ICDSGIR)
+#define INTCICCICR (INTC.ICCICR)
+#define INTCICCPMR (INTC.ICCPMR)
+#define INTCICCBPR (INTC.ICCBPR)
+#define INTCICCIAR (INTC.ICCIAR)
+#define INTCICCEOIR (INTC.ICCEOIR)
+#define INTCICCRPR (INTC.ICCRPR)
+#define INTCICCHPIR (INTC.ICCHPIR)
+#define INTCICCABPR (INTC.ICCABPR)
+#define INTCICCIIDR (INTC.ICCIIDR)
+#define INTCICR0 (INTC.ICR0)
+#define INTCICR1 (INTC.ICR1)
+#define INTCIRQRR (INTC.IRQRR)
+
+#define INTC_ICDISR0_COUNT (19)
+#define INTC_ICDISER0_COUNT (19)
+#define INTC_ICDICER0_COUNT (19)
+#define INTC_ICDISPR0_COUNT (19)
+#define INTC_ICDICPR0_COUNT (19)
+#define INTC_ICDABR0_COUNT (19)
+#define INTC_ICDIPR0_COUNT (147)
+#define INTC_ICDIPTR0_COUNT (147)
+#define INTC_ICDICFR0_COUNT (37)
+#define INTC_SPI_STATUS0_COUNT (17)
+
+
+typedef struct st_intc
+{
+                                                           /* INTC             */
+    volatile uint32_t  ICDDCR;                                 /*  ICDDCR          */
+    volatile uint32_t  ICDICTR;                                /*  ICDICTR         */
+    volatile uint32_t  ICDIIDR;                                /*  ICDIIDR         */
+    volatile uint8_t   dummy193[116];                          /*                  */
+
+/* #define INTC_ICDISR0_COUNT (19) */
+    volatile uint32_t  ICDISR0;                                /*  ICDISR0         */
+    volatile uint32_t  ICDISR1;                                /*  ICDISR1         */
+    volatile uint32_t  ICDISR2;                                /*  ICDISR2         */
+    volatile uint32_t  ICDISR3;                                /*  ICDISR3         */
+    volatile uint32_t  ICDISR4;                                /*  ICDISR4         */
+    volatile uint32_t  ICDISR5;                                /*  ICDISR5         */
+    volatile uint32_t  ICDISR6;                                /*  ICDISR6         */
+    volatile uint32_t  ICDISR7;                                /*  ICDISR7         */
+    volatile uint32_t  ICDISR8;                                /*  ICDISR8         */
+    volatile uint32_t  ICDISR9;                                /*  ICDISR9         */
+    volatile uint32_t  ICDISR10;                               /*  ICDISR10        */
+    volatile uint32_t  ICDISR11;                               /*  ICDISR11        */
+    volatile uint32_t  ICDISR12;                               /*  ICDISR12        */
+    volatile uint32_t  ICDISR13;                               /*  ICDISR13        */
+    volatile uint32_t  ICDISR14;                               /*  ICDISR14        */
+    volatile uint32_t  ICDISR15;                               /*  ICDISR15        */
+    volatile uint32_t  ICDISR16;                               /*  ICDISR16        */
+    volatile uint32_t  ICDISR17;                               /*  ICDISR17        */
+    volatile uint32_t  ICDISR18;                               /*  ICDISR18        */
+    volatile uint8_t   dummy194[52];                           /*                  */
+
+/* #define INTC_ICDISER0_COUNT (19) */
+    volatile uint32_t  ICDISER0;                               /*  ICDISER0        */
+    volatile uint32_t  ICDISER1;                               /*  ICDISER1        */
+    volatile uint32_t  ICDISER2;                               /*  ICDISER2        */
+    volatile uint32_t  ICDISER3;                               /*  ICDISER3        */
+    volatile uint32_t  ICDISER4;                               /*  ICDISER4        */
+    volatile uint32_t  ICDISER5;                               /*  ICDISER5        */
+    volatile uint32_t  ICDISER6;                               /*  ICDISER6        */
+    volatile uint32_t  ICDISER7;                               /*  ICDISER7        */
+    volatile uint32_t  ICDISER8;                               /*  ICDISER8        */
+    volatile uint32_t  ICDISER9;                               /*  ICDISER9        */
+    volatile uint32_t  ICDISER10;                              /*  ICDISER10       */
+    volatile uint32_t  ICDISER11;                              /*  ICDISER11       */
+    volatile uint32_t  ICDISER12;                              /*  ICDISER12       */
+    volatile uint32_t  ICDISER13;                              /*  ICDISER13       */
+    volatile uint32_t  ICDISER14;                              /*  ICDISER14       */
+    volatile uint32_t  ICDISER15;                              /*  ICDISER15       */
+    volatile uint32_t  ICDISER16;                              /*  ICDISER16       */
+    volatile uint32_t  ICDISER17;                              /*  ICDISER17       */
+    volatile uint32_t  ICDISER18;                              /*  ICDISER18       */
+    volatile uint8_t   dummy195[52];                           /*                  */
+
+/* #define INTC_ICDICER0_COUNT (19) */
+    volatile uint32_t  ICDICER0;                               /*  ICDICER0        */
+    volatile uint32_t  ICDICER1;                               /*  ICDICER1        */
+    volatile uint32_t  ICDICER2;                               /*  ICDICER2        */
+    volatile uint32_t  ICDICER3;                               /*  ICDICER3        */
+    volatile uint32_t  ICDICER4;                               /*  ICDICER4        */
+    volatile uint32_t  ICDICER5;                               /*  ICDICER5        */
+    volatile uint32_t  ICDICER6;                               /*  ICDICER6        */
+    volatile uint32_t  ICDICER7;                               /*  ICDICER7        */
+    volatile uint32_t  ICDICER8;                               /*  ICDICER8        */
+    volatile uint32_t  ICDICER9;                               /*  ICDICER9        */
+    volatile uint32_t  ICDICER10;                              /*  ICDICER10       */
+    volatile uint32_t  ICDICER11;                              /*  ICDICER11       */
+    volatile uint32_t  ICDICER12;                              /*  ICDICER12       */
+    volatile uint32_t  ICDICER13;                              /*  ICDICER13       */
+    volatile uint32_t  ICDICER14;                              /*  ICDICER14       */
+    volatile uint32_t  ICDICER15;                              /*  ICDICER15       */
+    volatile uint32_t  ICDICER16;                              /*  ICDICER16       */
+    volatile uint32_t  ICDICER17;                              /*  ICDICER17       */
+    volatile uint32_t  ICDICER18;                              /*  ICDICER18       */
+    volatile uint8_t   dummy196[52];                           /*                  */
+
+/* #define INTC_ICDISPR0_COUNT (19) */
+    volatile uint32_t  ICDISPR0;                               /*  ICDISPR0        */
+    volatile uint32_t  ICDISPR1;                               /*  ICDISPR1        */
+    volatile uint32_t  ICDISPR2;                               /*  ICDISPR2        */
+    volatile uint32_t  ICDISPR3;                               /*  ICDISPR3        */
+    volatile uint32_t  ICDISPR4;                               /*  ICDISPR4        */
+    volatile uint32_t  ICDISPR5;                               /*  ICDISPR5        */
+    volatile uint32_t  ICDISPR6;                               /*  ICDISPR6        */
+    volatile uint32_t  ICDISPR7;                               /*  ICDISPR7        */
+    volatile uint32_t  ICDISPR8;                               /*  ICDISPR8        */
+    volatile uint32_t  ICDISPR9;                               /*  ICDISPR9        */
+    volatile uint32_t  ICDISPR10;                              /*  ICDISPR10       */
+    volatile uint32_t  ICDISPR11;                              /*  ICDISPR11       */
+    volatile uint32_t  ICDISPR12;                              /*  ICDISPR12       */
+    volatile uint32_t  ICDISPR13;                              /*  ICDISPR13       */
+    volatile uint32_t  ICDISPR14;                              /*  ICDISPR14       */
+    volatile uint32_t  ICDISPR15;                              /*  ICDISPR15       */
+    volatile uint32_t  ICDISPR16;                              /*  ICDISPR16       */
+    volatile uint32_t  ICDISPR17;                              /*  ICDISPR17       */
+    volatile uint32_t  ICDISPR18;                              /*  ICDISPR18       */
+    volatile uint8_t   dummy197[52];                           /*                  */
+
+/* #define INTC_ICDICPR0_COUNT (19) */
+    volatile uint32_t  ICDICPR0;                               /*  ICDICPR0        */
+    volatile uint32_t  ICDICPR1;                               /*  ICDICPR1        */
+    volatile uint32_t  ICDICPR2;                               /*  ICDICPR2        */
+    volatile uint32_t  ICDICPR3;                               /*  ICDICPR3        */
+    volatile uint32_t  ICDICPR4;                               /*  ICDICPR4        */
+    volatile uint32_t  ICDICPR5;                               /*  ICDICPR5        */
+    volatile uint32_t  ICDICPR6;                               /*  ICDICPR6        */
+    volatile uint32_t  ICDICPR7;                               /*  ICDICPR7        */
+    volatile uint32_t  ICDICPR8;                               /*  ICDICPR8        */
+    volatile uint32_t  ICDICPR9;                               /*  ICDICPR9        */
+    volatile uint32_t  ICDICPR10;                              /*  ICDICPR10       */
+    volatile uint32_t  ICDICPR11;                              /*  ICDICPR11       */
+    volatile uint32_t  ICDICPR12;                              /*  ICDICPR12       */
+    volatile uint32_t  ICDICPR13;                              /*  ICDICPR13       */
+    volatile uint32_t  ICDICPR14;                              /*  ICDICPR14       */
+    volatile uint32_t  ICDICPR15;                              /*  ICDICPR15       */
+    volatile uint32_t  ICDICPR16;                              /*  ICDICPR16       */
+    volatile uint32_t  ICDICPR17;                              /*  ICDICPR17       */
+    volatile uint32_t  ICDICPR18;                              /*  ICDICPR18       */
+    volatile uint8_t   dummy198[52];                           /*                  */
+
+/* #define INTC_ICDABR0_COUNT (19) */
+    volatile uint32_t  ICDABR0;                                /*  ICDABR0         */
+    volatile uint32_t  ICDABR1;                                /*  ICDABR1         */
+    volatile uint32_t  ICDABR2;                                /*  ICDABR2         */
+    volatile uint32_t  ICDABR3;                                /*  ICDABR3         */
+    volatile uint32_t  ICDABR4;                                /*  ICDABR4         */
+    volatile uint32_t  ICDABR5;                                /*  ICDABR5         */
+    volatile uint32_t  ICDABR6;                                /*  ICDABR6         */
+    volatile uint32_t  ICDABR7;                                /*  ICDABR7         */
+    volatile uint32_t  ICDABR8;                                /*  ICDABR8         */
+    volatile uint32_t  ICDABR9;                                /*  ICDABR9         */
+    volatile uint32_t  ICDABR10;                               /*  ICDABR10        */
+    volatile uint32_t  ICDABR11;                               /*  ICDABR11        */
+    volatile uint32_t  ICDABR12;                               /*  ICDABR12        */
+    volatile uint32_t  ICDABR13;                               /*  ICDABR13        */
+    volatile uint32_t  ICDABR14;                               /*  ICDABR14        */
+    volatile uint32_t  ICDABR15;                               /*  ICDABR15        */
+    volatile uint32_t  ICDABR16;                               /*  ICDABR16        */
+    volatile uint32_t  ICDABR17;                               /*  ICDABR17        */
+    volatile uint32_t  ICDABR18;                               /*  ICDABR18        */
+    volatile uint8_t   dummy199[180];                          /*                  */
+
+/* #define INTC_ICDIPR0_COUNT (147) */
+    volatile uint32_t  ICDIPR0;                                /*  ICDIPR0         */
+    volatile uint32_t  ICDIPR1;                                /*  ICDIPR1         */
+    volatile uint32_t  ICDIPR2;                                /*  ICDIPR2         */
+    volatile uint32_t  ICDIPR3;                                /*  ICDIPR3         */
+    volatile uint32_t  ICDIPR4;                                /*  ICDIPR4         */
+    volatile uint32_t  ICDIPR5;                                /*  ICDIPR5         */
+    volatile uint32_t  ICDIPR6;                                /*  ICDIPR6         */
+    volatile uint32_t  ICDIPR7;                                /*  ICDIPR7         */
+    volatile uint32_t  ICDIPR8;                                /*  ICDIPR8         */
+    volatile uint32_t  ICDIPR9;                                /*  ICDIPR9         */
+    volatile uint32_t  ICDIPR10;                               /*  ICDIPR10        */
+    volatile uint32_t  ICDIPR11;                               /*  ICDIPR11        */
+    volatile uint32_t  ICDIPR12;                               /*  ICDIPR12        */
+    volatile uint32_t  ICDIPR13;                               /*  ICDIPR13        */
+    volatile uint32_t  ICDIPR14;                               /*  ICDIPR14        */
+    volatile uint32_t  ICDIPR15;                               /*  ICDIPR15        */
+    volatile uint32_t  ICDIPR16;                               /*  ICDIPR16        */
+    volatile uint32_t  ICDIPR17;                               /*  ICDIPR17        */
+    volatile uint32_t  ICDIPR18;                               /*  ICDIPR18        */
+    volatile uint32_t  ICDIPR19;                               /*  ICDIPR19        */
+    volatile uint32_t  ICDIPR20;                               /*  ICDIPR20        */
+    volatile uint32_t  ICDIPR21;                               /*  ICDIPR21        */
+    volatile uint32_t  ICDIPR22;                               /*  ICDIPR22        */
+    volatile uint32_t  ICDIPR23;                               /*  ICDIPR23        */
+    volatile uint32_t  ICDIPR24;                               /*  ICDIPR24        */
+    volatile uint32_t  ICDIPR25;                               /*  ICDIPR25        */
+    volatile uint32_t  ICDIPR26;                               /*  ICDIPR26        */
+    volatile uint32_t  ICDIPR27;                               /*  ICDIPR27        */
+    volatile uint32_t  ICDIPR28;                               /*  ICDIPR28        */
+    volatile uint32_t  ICDIPR29;                               /*  ICDIPR29        */
+    volatile uint32_t  ICDIPR30;                               /*  ICDIPR30        */
+    volatile uint32_t  ICDIPR31;                               /*  ICDIPR31        */
+    volatile uint32_t  ICDIPR32;                               /*  ICDIPR32        */
+    volatile uint32_t  ICDIPR33;                               /*  ICDIPR33        */
+    volatile uint32_t  ICDIPR34;                               /*  ICDIPR34        */
+    volatile uint32_t  ICDIPR35;                               /*  ICDIPR35        */
+    volatile uint32_t  ICDIPR36;                               /*  ICDIPR36        */
+    volatile uint32_t  ICDIPR37;                               /*  ICDIPR37        */
+    volatile uint32_t  ICDIPR38;                               /*  ICDIPR38        */
+    volatile uint32_t  ICDIPR39;                               /*  ICDIPR39        */
+    volatile uint32_t  ICDIPR40;                               /*  ICDIPR40        */
+    volatile uint32_t  ICDIPR41;                               /*  ICDIPR41        */
+    volatile uint32_t  ICDIPR42;                               /*  ICDIPR42        */
+    volatile uint32_t  ICDIPR43;                               /*  ICDIPR43        */
+    volatile uint32_t  ICDIPR44;                               /*  ICDIPR44        */
+    volatile uint32_t  ICDIPR45;                               /*  ICDIPR45        */
+    volatile uint32_t  ICDIPR46;                               /*  ICDIPR46        */
+    volatile uint32_t  ICDIPR47;                               /*  ICDIPR47        */
+    volatile uint32_t  ICDIPR48;                               /*  ICDIPR48        */
+    volatile uint32_t  ICDIPR49;                               /*  ICDIPR49        */
+    volatile uint32_t  ICDIPR50;                               /*  ICDIPR50        */
+    volatile uint32_t  ICDIPR51;                               /*  ICDIPR51        */
+    volatile uint32_t  ICDIPR52;                               /*  ICDIPR52        */
+    volatile uint32_t  ICDIPR53;                               /*  ICDIPR53        */
+    volatile uint32_t  ICDIPR54;                               /*  ICDIPR54        */
+    volatile uint32_t  ICDIPR55;                               /*  ICDIPR55        */
+    volatile uint32_t  ICDIPR56;                               /*  ICDIPR56        */
+    volatile uint32_t  ICDIPR57;                               /*  ICDIPR57        */
+    volatile uint32_t  ICDIPR58;                               /*  ICDIPR58        */
+    volatile uint32_t  ICDIPR59;                               /*  ICDIPR59        */
+    volatile uint32_t  ICDIPR60;                               /*  ICDIPR60        */
+    volatile uint32_t  ICDIPR61;                               /*  ICDIPR61        */
+    volatile uint32_t  ICDIPR62;                               /*  ICDIPR62        */
+    volatile uint32_t  ICDIPR63;                               /*  ICDIPR63        */
+    volatile uint32_t  ICDIPR64;                               /*  ICDIPR64        */
+    volatile uint32_t  ICDIPR65;                               /*  ICDIPR65        */
+    volatile uint32_t  ICDIPR66;                               /*  ICDIPR66        */
+    volatile uint32_t  ICDIPR67;                               /*  ICDIPR67        */
+    volatile uint32_t  ICDIPR68;                               /*  ICDIPR68        */
+    volatile uint32_t  ICDIPR69;                               /*  ICDIPR69        */
+    volatile uint32_t  ICDIPR70;                               /*  ICDIPR70        */
+    volatile uint32_t  ICDIPR71;                               /*  ICDIPR71        */
+    volatile uint32_t  ICDIPR72;                               /*  ICDIPR72        */
+    volatile uint32_t  ICDIPR73;                               /*  ICDIPR73        */
+    volatile uint32_t  ICDIPR74;                               /*  ICDIPR74        */
+    volatile uint32_t  ICDIPR75;                               /*  ICDIPR75        */
+    volatile uint32_t  ICDIPR76;                               /*  ICDIPR76        */
+    volatile uint32_t  ICDIPR77;                               /*  ICDIPR77        */
+    volatile uint32_t  ICDIPR78;                               /*  ICDIPR78        */
+    volatile uint32_t  ICDIPR79;                               /*  ICDIPR79        */
+    volatile uint32_t  ICDIPR80;                               /*  ICDIPR80        */
+    volatile uint32_t  ICDIPR81;                               /*  ICDIPR81        */
+    volatile uint32_t  ICDIPR82;                               /*  ICDIPR82        */
+    volatile uint32_t  ICDIPR83;                               /*  ICDIPR83        */
+    volatile uint32_t  ICDIPR84;                               /*  ICDIPR84        */
+    volatile uint32_t  ICDIPR85;                               /*  ICDIPR85        */
+    volatile uint32_t  ICDIPR86;                               /*  ICDIPR86        */
+    volatile uint32_t  ICDIPR87;                               /*  ICDIPR87        */
+    volatile uint32_t  ICDIPR88;                               /*  ICDIPR88        */
+    volatile uint32_t  ICDIPR89;                               /*  ICDIPR89        */
+    volatile uint32_t  ICDIPR90;                               /*  ICDIPR90        */
+    volatile uint32_t  ICDIPR91;                               /*  ICDIPR91        */
+    volatile uint32_t  ICDIPR92;                               /*  ICDIPR92        */
+    volatile uint32_t  ICDIPR93;                               /*  ICDIPR93        */
+    volatile uint32_t  ICDIPR94;                               /*  ICDIPR94        */
+    volatile uint32_t  ICDIPR95;                               /*  ICDIPR95        */
+    volatile uint32_t  ICDIPR96;                               /*  ICDIPR96        */
+    volatile uint32_t  ICDIPR97;                               /*  ICDIPR97        */
+    volatile uint32_t  ICDIPR98;                               /*  ICDIPR98        */
+    volatile uint32_t  ICDIPR99;                               /*  ICDIPR99        */
+    volatile uint32_t  ICDIPR100;                              /*  ICDIPR100       */
+    volatile uint32_t  ICDIPR101;                              /*  ICDIPR101       */
+    volatile uint32_t  ICDIPR102;                              /*  ICDIPR102       */
+    volatile uint32_t  ICDIPR103;                              /*  ICDIPR103       */
+    volatile uint32_t  ICDIPR104;                              /*  ICDIPR104       */
+    volatile uint32_t  ICDIPR105;                              /*  ICDIPR105       */
+    volatile uint32_t  ICDIPR106;                              /*  ICDIPR106       */
+    volatile uint32_t  ICDIPR107;                              /*  ICDIPR107       */
+    volatile uint32_t  ICDIPR108;                              /*  ICDIPR108       */
+    volatile uint32_t  ICDIPR109;                              /*  ICDIPR109       */
+    volatile uint32_t  ICDIPR110;                              /*  ICDIPR110       */
+    volatile uint32_t  ICDIPR111;                              /*  ICDIPR111       */
+    volatile uint32_t  ICDIPR112;                              /*  ICDIPR112       */
+    volatile uint32_t  ICDIPR113;                              /*  ICDIPR113       */
+    volatile uint32_t  ICDIPR114;                              /*  ICDIPR114       */
+    volatile uint32_t  ICDIPR115;                              /*  ICDIPR115       */
+    volatile uint32_t  ICDIPR116;                              /*  ICDIPR116       */
+    volatile uint32_t  ICDIPR117;                              /*  ICDIPR117       */
+    volatile uint32_t  ICDIPR118;                              /*  ICDIPR118       */
+    volatile uint32_t  ICDIPR119;                              /*  ICDIPR119       */
+    volatile uint32_t  ICDIPR120;                              /*  ICDIPR120       */
+    volatile uint32_t  ICDIPR121;                              /*  ICDIPR121       */
+    volatile uint32_t  ICDIPR122;                              /*  ICDIPR122       */
+    volatile uint32_t  ICDIPR123;                              /*  ICDIPR123       */
+    volatile uint32_t  ICDIPR124;                              /*  ICDIPR124       */
+    volatile uint32_t  ICDIPR125;                              /*  ICDIPR125       */
+    volatile uint32_t  ICDIPR126;                              /*  ICDIPR126       */
+    volatile uint32_t  ICDIPR127;                              /*  ICDIPR127       */
+    volatile uint32_t  ICDIPR128;                              /*  ICDIPR128       */
+    volatile uint32_t  ICDIPR129;                              /*  ICDIPR129       */
+    volatile uint32_t  ICDIPR130;                              /*  ICDIPR130       */
+    volatile uint32_t  ICDIPR131;                              /*  ICDIPR131       */
+    volatile uint32_t  ICDIPR132;                              /*  ICDIPR132       */
+    volatile uint32_t  ICDIPR133;                              /*  ICDIPR133       */
+    volatile uint32_t  ICDIPR134;                              /*  ICDIPR134       */
+    volatile uint32_t  ICDIPR135;                              /*  ICDIPR135       */
+    volatile uint32_t  ICDIPR136;                              /*  ICDIPR136       */
+    volatile uint32_t  ICDIPR137;                              /*  ICDIPR137       */
+    volatile uint32_t  ICDIPR138;                              /*  ICDIPR138       */
+    volatile uint32_t  ICDIPR139;                              /*  ICDIPR139       */
+    volatile uint32_t  ICDIPR140;                              /*  ICDIPR140       */
+    volatile uint32_t  ICDIPR141;                              /*  ICDIPR141       */
+    volatile uint32_t  ICDIPR142;                              /*  ICDIPR142       */
+    volatile uint32_t  ICDIPR143;                              /*  ICDIPR143       */
+    volatile uint32_t  ICDIPR144;                              /*  ICDIPR144       */
+    volatile uint32_t  ICDIPR145;                              /*  ICDIPR145       */
+    volatile uint32_t  ICDIPR146;                              /*  ICDIPR146       */
+    volatile uint8_t   dummy200[436];                          /*                  */
+
+/* #define INTC_ICDIPTR0_COUNT (147) */
+    volatile uint32_t  ICDIPTR0;                               /*  ICDIPTR0        */
+    volatile uint32_t  ICDIPTR1;                               /*  ICDIPTR1        */
+    volatile uint32_t  ICDIPTR2;                               /*  ICDIPTR2        */
+    volatile uint32_t  ICDIPTR3;                               /*  ICDIPTR3        */
+    volatile uint32_t  ICDIPTR4;                               /*  ICDIPTR4        */
+    volatile uint32_t  ICDIPTR5;                               /*  ICDIPTR5        */
+    volatile uint32_t  ICDIPTR6;                               /*  ICDIPTR6        */
+    volatile uint32_t  ICDIPTR7;                               /*  ICDIPTR7        */
+    volatile uint32_t  ICDIPTR8;                               /*  ICDIPTR8        */
+    volatile uint32_t  ICDIPTR9;                               /*  ICDIPTR9        */
+    volatile uint32_t  ICDIPTR10;                              /*  ICDIPTR10       */
+    volatile uint32_t  ICDIPTR11;                              /*  ICDIPTR11       */
+    volatile uint32_t  ICDIPTR12;                              /*  ICDIPTR12       */
+    volatile uint32_t  ICDIPTR13;                              /*  ICDIPTR13       */
+    volatile uint32_t  ICDIPTR14;                              /*  ICDIPTR14       */
+    volatile uint32_t  ICDIPTR15;                              /*  ICDIPTR15       */
+    volatile uint32_t  ICDIPTR16;                              /*  ICDIPTR16       */
+    volatile uint32_t  ICDIPTR17;                              /*  ICDIPTR17       */
+    volatile uint32_t  ICDIPTR18;                              /*  ICDIPTR18       */
+    volatile uint32_t  ICDIPTR19;                              /*  ICDIPTR19       */
+    volatile uint32_t  ICDIPTR20;                              /*  ICDIPTR20       */
+    volatile uint32_t  ICDIPTR21;                              /*  ICDIPTR21       */
+    volatile uint32_t  ICDIPTR22;                              /*  ICDIPTR22       */
+    volatile uint32_t  ICDIPTR23;                              /*  ICDIPTR23       */
+    volatile uint32_t  ICDIPTR24;                              /*  ICDIPTR24       */
+    volatile uint32_t  ICDIPTR25;                              /*  ICDIPTR25       */
+    volatile uint32_t  ICDIPTR26;                              /*  ICDIPTR26       */
+    volatile uint32_t  ICDIPTR27;                              /*  ICDIPTR27       */
+    volatile uint32_t  ICDIPTR28;                              /*  ICDIPTR28       */
+    volatile uint32_t  ICDIPTR29;                              /*  ICDIPTR29       */
+    volatile uint32_t  ICDIPTR30;                              /*  ICDIPTR30       */
+    volatile uint32_t  ICDIPTR31;                              /*  ICDIPTR31       */
+    volatile uint32_t  ICDIPTR32;                              /*  ICDIPTR32       */
+    volatile uint32_t  ICDIPTR33;                              /*  ICDIPTR33       */
+    volatile uint32_t  ICDIPTR34;                              /*  ICDIPTR34       */
+    volatile uint32_t  ICDIPTR35;                              /*  ICDIPTR35       */
+    volatile uint32_t  ICDIPTR36;                              /*  ICDIPTR36       */
+    volatile uint32_t  ICDIPTR37;                              /*  ICDIPTR37       */
+    volatile uint32_t  ICDIPTR38;                              /*  ICDIPTR38       */
+    volatile uint32_t  ICDIPTR39;                              /*  ICDIPTR39       */
+    volatile uint32_t  ICDIPTR40;                              /*  ICDIPTR40       */
+    volatile uint32_t  ICDIPTR41;                              /*  ICDIPTR41       */
+    volatile uint32_t  ICDIPTR42;                              /*  ICDIPTR42       */
+    volatile uint32_t  ICDIPTR43;                              /*  ICDIPTR43       */
+    volatile uint32_t  ICDIPTR44;                              /*  ICDIPTR44       */
+    volatile uint32_t  ICDIPTR45;                              /*  ICDIPTR45       */
+    volatile uint32_t  ICDIPTR46;                              /*  ICDIPTR46       */
+    volatile uint32_t  ICDIPTR47;                              /*  ICDIPTR47       */
+    volatile uint32_t  ICDIPTR48;                              /*  ICDIPTR48       */
+    volatile uint32_t  ICDIPTR49;                              /*  ICDIPTR49       */
+    volatile uint32_t  ICDIPTR50;                              /*  ICDIPTR50       */
+    volatile uint32_t  ICDIPTR51;                              /*  ICDIPTR51       */
+    volatile uint32_t  ICDIPTR52;                              /*  ICDIPTR52       */
+    volatile uint32_t  ICDIPTR53;                              /*  ICDIPTR53       */
+    volatile uint32_t  ICDIPTR54;                              /*  ICDIPTR54       */
+    volatile uint32_t  ICDIPTR55;                              /*  ICDIPTR55       */
+    volatile uint32_t  ICDIPTR56;                              /*  ICDIPTR56       */
+    volatile uint32_t  ICDIPTR57;                              /*  ICDIPTR57       */
+    volatile uint32_t  ICDIPTR58;                              /*  ICDIPTR58       */
+    volatile uint32_t  ICDIPTR59;                              /*  ICDIPTR59       */
+    volatile uint32_t  ICDIPTR60;                              /*  ICDIPTR60       */
+    volatile uint32_t  ICDIPTR61;                              /*  ICDIPTR61       */
+    volatile uint32_t  ICDIPTR62;                              /*  ICDIPTR62       */
+    volatile uint32_t  ICDIPTR63;                              /*  ICDIPTR63       */
+    volatile uint32_t  ICDIPTR64;                              /*  ICDIPTR64       */
+    volatile uint32_t  ICDIPTR65;                              /*  ICDIPTR65       */
+    volatile uint32_t  ICDIPTR66;                              /*  ICDIPTR66       */
+    volatile uint32_t  ICDIPTR67;                              /*  ICDIPTR67       */
+    volatile uint32_t  ICDIPTR68;                              /*  ICDIPTR68       */
+    volatile uint32_t  ICDIPTR69;                              /*  ICDIPTR69       */
+    volatile uint32_t  ICDIPTR70;                              /*  ICDIPTR70       */
+    volatile uint32_t  ICDIPTR71;                              /*  ICDIPTR71       */
+    volatile uint32_t  ICDIPTR72;                              /*  ICDIPTR72       */
+    volatile uint32_t  ICDIPTR73;                              /*  ICDIPTR73       */
+    volatile uint32_t  ICDIPTR74;                              /*  ICDIPTR74       */
+    volatile uint32_t  ICDIPTR75;                              /*  ICDIPTR75       */
+    volatile uint32_t  ICDIPTR76;                              /*  ICDIPTR76       */
+    volatile uint32_t  ICDIPTR77;                              /*  ICDIPTR77       */
+    volatile uint32_t  ICDIPTR78;                              /*  ICDIPTR78       */
+    volatile uint32_t  ICDIPTR79;                              /*  ICDIPTR79       */
+    volatile uint32_t  ICDIPTR80;                              /*  ICDIPTR80       */
+    volatile uint32_t  ICDIPTR81;                              /*  ICDIPTR81       */
+    volatile uint32_t  ICDIPTR82;                              /*  ICDIPTR82       */
+    volatile uint32_t  ICDIPTR83;                              /*  ICDIPTR83       */
+    volatile uint32_t  ICDIPTR84;                              /*  ICDIPTR84       */
+    volatile uint32_t  ICDIPTR85;                              /*  ICDIPTR85       */
+    volatile uint32_t  ICDIPTR86;                              /*  ICDIPTR86       */
+    volatile uint32_t  ICDIPTR87;                              /*  ICDIPTR87       */
+    volatile uint32_t  ICDIPTR88;                              /*  ICDIPTR88       */
+    volatile uint32_t  ICDIPTR89;                              /*  ICDIPTR89       */
+    volatile uint32_t  ICDIPTR90;                              /*  ICDIPTR90       */
+    volatile uint32_t  ICDIPTR91;                              /*  ICDIPTR91       */
+    volatile uint32_t  ICDIPTR92;                              /*  ICDIPTR92       */
+    volatile uint32_t  ICDIPTR93;                              /*  ICDIPTR93       */
+    volatile uint32_t  ICDIPTR94;                              /*  ICDIPTR94       */
+    volatile uint32_t  ICDIPTR95;                              /*  ICDIPTR95       */
+    volatile uint32_t  ICDIPTR96;                              /*  ICDIPTR96       */
+    volatile uint32_t  ICDIPTR97;                              /*  ICDIPTR97       */
+    volatile uint32_t  ICDIPTR98;                              /*  ICDIPTR98       */
+    volatile uint32_t  ICDIPTR99;                              /*  ICDIPTR99       */
+    volatile uint32_t  ICDIPTR100;                             /*  ICDIPTR100      */
+    volatile uint32_t  ICDIPTR101;                             /*  ICDIPTR101      */
+    volatile uint32_t  ICDIPTR102;                             /*  ICDIPTR102      */
+    volatile uint32_t  ICDIPTR103;                             /*  ICDIPTR103      */
+    volatile uint32_t  ICDIPTR104;                             /*  ICDIPTR104      */
+    volatile uint32_t  ICDIPTR105;                             /*  ICDIPTR105      */
+    volatile uint32_t  ICDIPTR106;                             /*  ICDIPTR106      */
+    volatile uint32_t  ICDIPTR107;                             /*  ICDIPTR107      */
+    volatile uint32_t  ICDIPTR108;                             /*  ICDIPTR108      */
+    volatile uint32_t  ICDIPTR109;                             /*  ICDIPTR109      */
+    volatile uint32_t  ICDIPTR110;                             /*  ICDIPTR110      */
+    volatile uint32_t  ICDIPTR111;                             /*  ICDIPTR111      */
+    volatile uint32_t  ICDIPTR112;                             /*  ICDIPTR112      */
+    volatile uint32_t  ICDIPTR113;                             /*  ICDIPTR113      */
+    volatile uint32_t  ICDIPTR114;                             /*  ICDIPTR114      */
+    volatile uint32_t  ICDIPTR115;                             /*  ICDIPTR115      */
+    volatile uint32_t  ICDIPTR116;                             /*  ICDIPTR116      */
+    volatile uint32_t  ICDIPTR117;                             /*  ICDIPTR117      */
+    volatile uint32_t  ICDIPTR118;                             /*  ICDIPTR118      */
+    volatile uint32_t  ICDIPTR119;                             /*  ICDIPTR119      */
+    volatile uint32_t  ICDIPTR120;                             /*  ICDIPTR120      */
+    volatile uint32_t  ICDIPTR121;                             /*  ICDIPTR121      */
+    volatile uint32_t  ICDIPTR122;                             /*  ICDIPTR122      */
+    volatile uint32_t  ICDIPTR123;                             /*  ICDIPTR123      */
+    volatile uint32_t  ICDIPTR124;                             /*  ICDIPTR124      */
+    volatile uint32_t  ICDIPTR125;                             /*  ICDIPTR125      */
+    volatile uint32_t  ICDIPTR126;                             /*  ICDIPTR126      */
+    volatile uint32_t  ICDIPTR127;                             /*  ICDIPTR127      */
+    volatile uint32_t  ICDIPTR128;                             /*  ICDIPTR128      */
+    volatile uint32_t  ICDIPTR129;                             /*  ICDIPTR129      */
+    volatile uint32_t  ICDIPTR130;                             /*  ICDIPTR130      */
+    volatile uint32_t  ICDIPTR131;                             /*  ICDIPTR131      */
+    volatile uint32_t  ICDIPTR132;                             /*  ICDIPTR132      */
+    volatile uint32_t  ICDIPTR133;                             /*  ICDIPTR133      */
+    volatile uint32_t  ICDIPTR134;                             /*  ICDIPTR134      */
+    volatile uint32_t  ICDIPTR135;                             /*  ICDIPTR135      */
+    volatile uint32_t  ICDIPTR136;                             /*  ICDIPTR136      */
+    volatile uint32_t  ICDIPTR137;                             /*  ICDIPTR137      */
+    volatile uint32_t  ICDIPTR138;                             /*  ICDIPTR138      */
+    volatile uint32_t  ICDIPTR139;                             /*  ICDIPTR139      */
+    volatile uint32_t  ICDIPTR140;                             /*  ICDIPTR140      */
+    volatile uint32_t  ICDIPTR141;                             /*  ICDIPTR141      */
+    volatile uint32_t  ICDIPTR142;                             /*  ICDIPTR142      */
+    volatile uint32_t  ICDIPTR143;                             /*  ICDIPTR143      */
+    volatile uint32_t  ICDIPTR144;                             /*  ICDIPTR144      */
+    volatile uint32_t  ICDIPTR145;                             /*  ICDIPTR145      */
+    volatile uint32_t  ICDIPTR146;                             /*  ICDIPTR146      */
+    volatile uint8_t   dummy201[436];                          /*                  */
+
+/* #define INTC_ICDICFR0_COUNT (37) */
+    volatile uint32_t  ICDICFR0;                               /*  ICDICFR0        */
+    volatile uint32_t  ICDICFR1;                               /*  ICDICFR1        */
+    volatile uint32_t  ICDICFR2;                               /*  ICDICFR2        */
+    volatile uint32_t  ICDICFR3;                               /*  ICDICFR3        */
+    volatile uint32_t  ICDICFR4;                               /*  ICDICFR4        */
+    volatile uint32_t  ICDICFR5;                               /*  ICDICFR5        */
+    volatile uint32_t  ICDICFR6;                               /*  ICDICFR6        */
+    volatile uint32_t  ICDICFR7;                               /*  ICDICFR7        */
+    volatile uint32_t  ICDICFR8;                               /*  ICDICFR8        */
+    volatile uint32_t  ICDICFR9;                               /*  ICDICFR9        */
+    volatile uint32_t  ICDICFR10;                              /*  ICDICFR10       */
+    volatile uint32_t  ICDICFR11;                              /*  ICDICFR11       */
+    volatile uint32_t  ICDICFR12;                              /*  ICDICFR12       */
+    volatile uint32_t  ICDICFR13;                              /*  ICDICFR13       */
+    volatile uint32_t  ICDICFR14;                              /*  ICDICFR14       */
+    volatile uint32_t  ICDICFR15;                              /*  ICDICFR15       */
+    volatile uint32_t  ICDICFR16;                              /*  ICDICFR16       */
+    volatile uint32_t  ICDICFR17;                              /*  ICDICFR17       */
+    volatile uint32_t  ICDICFR18;                              /*  ICDICFR18       */
+    volatile uint32_t  ICDICFR19;                              /*  ICDICFR19       */
+    volatile uint32_t  ICDICFR20;                              /*  ICDICFR20       */
+    volatile uint32_t  ICDICFR21;                              /*  ICDICFR21       */
+    volatile uint32_t  ICDICFR22;                              /*  ICDICFR22       */
+    volatile uint32_t  ICDICFR23;                              /*  ICDICFR23       */
+    volatile uint32_t  ICDICFR24;                              /*  ICDICFR24       */
+    volatile uint32_t  ICDICFR25;                              /*  ICDICFR25       */
+    volatile uint32_t  ICDICFR26;                              /*  ICDICFR26       */
+    volatile uint32_t  ICDICFR27;                              /*  ICDICFR27       */
+    volatile uint32_t  ICDICFR28;                              /*  ICDICFR28       */
+    volatile uint32_t  ICDICFR29;                              /*  ICDICFR29       */
+    volatile uint32_t  ICDICFR30;                              /*  ICDICFR30       */
+    volatile uint32_t  ICDICFR31;                              /*  ICDICFR31       */
+    volatile uint32_t  ICDICFR32;                              /*  ICDICFR32       */
+    volatile uint32_t  ICDICFR33;                              /*  ICDICFR33       */
+    volatile uint32_t  ICDICFR34;                              /*  ICDICFR34       */
+    volatile uint32_t  ICDICFR35;                              /*  ICDICFR35       */
+    volatile uint32_t  ICDICFR36;                              /*  ICDICFR36       */
+    volatile uint8_t   dummy202[108];                          /*                  */
+    volatile uint32_t  PPI_STATUS;                             /*  PPI_STATUS      */
+
+/* #define INTC_SPI_STATUS0_COUNT (17) */
+    volatile uint32_t  SPI_STATUS0;                            /*  SPI_STATUS0     */
+    volatile uint32_t  SPI_STATUS1;                            /*  SPI_STATUS1     */
+    volatile uint32_t  SPI_STATUS2;                            /*  SPI_STATUS2     */
+    volatile uint32_t  SPI_STATUS3;                            /*  SPI_STATUS3     */
+    volatile uint32_t  SPI_STATUS4;                            /*  SPI_STATUS4     */
+    volatile uint32_t  SPI_STATUS5;                            /*  SPI_STATUS5     */
+    volatile uint32_t  SPI_STATUS6;                            /*  SPI_STATUS6     */
+    volatile uint32_t  SPI_STATUS7;                            /*  SPI_STATUS7     */
+    volatile uint32_t  SPI_STATUS8;                            /*  SPI_STATUS8     */
+    volatile uint32_t  SPI_STATUS9;                            /*  SPI_STATUS9     */
+    volatile uint32_t  SPI_STATUS10;                           /*  SPI_STATUS10    */
+    volatile uint32_t  SPI_STATUS11;                           /*  SPI_STATUS11    */
+    volatile uint32_t  SPI_STATUS12;                           /*  SPI_STATUS12    */
+    volatile uint32_t  SPI_STATUS13;                           /*  SPI_STATUS13    */
+    volatile uint32_t  SPI_STATUS14;                           /*  SPI_STATUS14    */
+    volatile uint32_t  SPI_STATUS15;                           /*  SPI_STATUS15    */
+    volatile uint32_t  SPI_STATUS16;                           /*  SPI_STATUS16    */
+    volatile uint8_t   dummy203[440];                          /*                  */
+    volatile uint32_t  ICDSGIR;                                /*  ICDSGIR         */
+    volatile uint8_t   dummy204[252];                          /*                  */
+    volatile uint32_t  ICCICR;                                 /*  ICCICR          */
+    volatile uint32_t  ICCPMR;                                 /*  ICCPMR          */
+    volatile uint32_t  ICCBPR;                                 /*  ICCBPR          */
+    volatile uint32_t  ICCIAR;                                 /*  ICCIAR          */
+    volatile uint32_t  ICCEOIR;                                /*  ICCEOIR         */
+    volatile uint32_t  ICCRPR;                                 /*  ICCRPR          */
+    volatile uint32_t  ICCHPIR;                                /*  ICCHPIR         */
+    volatile uint32_t  ICCABPR;                                /*  ICCABPR         */
+    volatile uint8_t   dummy205[220];                          /*                  */
+    volatile uint32_t  ICCIIDR;                                /*  ICCIIDR         */
+    volatile uint8_t   dummy206[350148352];                    /*                  */
+    volatile uint16_t ICR0;                                   /*  ICR0            */
+    volatile uint16_t ICR1;                                   /*  ICR1            */
+    volatile uint16_t IRQRR;                                  /*  IRQRR           */
+} r_io_intc_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h	(revision 374)
@@ -0,0 +1,118 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : iodefine_typedef.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef IODEFINE_TYPEDEF_H
+#define IODEFINE_TYPEDEF_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+/* Shared types and macros for iodefine.h */
+
+/***********************************************************************
+* Macro: IODEFINE_H_VERSION
+************************************************************************/
+#define IODEFINE_H_VERSION  (200)
+
+
+/***********************************************************************
+* Enum: iodefine_byte_select_t
+*
+*   R_IO_L - Low 16bit or Low 8 bit
+*   R_IO_H - High 16bit or Low 8 bit
+*   R_IO_LL - Low 8 bit
+*   R_IO_LH - Middle Low 8 bit
+*   R_IO_HL - Middle High 8 bit
+*   R_IO_HH - High 8 bit
+************************************************************************/
+typedef enum iodefine_byte_select_t
+{
+    R_IO_L = 0, R_IO_H = 1,
+    R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3,
+    L = 0, H = 1,
+    LL= 0, LH = 1, HL = 2, HH = 3
+} iodefine_byte_select_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg32_t
+*   32/16/8 bit access register
+*
+* - Padding : sizeof(iodefine_reg32_t) == 4
+* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+*                       &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg32_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+    volatile uint8_t   UINT8[4];                                /*  8-bit Access    */
+} iodefine_reg32_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg32_16_t
+*   32/16 bit access register
+* 
+* - Padding : sizeof(iodefine_reg32_16_t) == 4
+* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg32_16_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+} iodefine_reg32_16_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg16_8_t
+*   16/8 bit access register
+* 
+* - Padding : sizeof(iodefine_reg16_8_t) == 2
+* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg16_8_t
+{
+    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
+    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
+} iodefine_reg16_8_t;
+
+
+/* End of shared types and macros for iodefine.h */
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h	(revision 374)
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : irda_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef IRDA_IODEFINE_H
+#define IRDA_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define IRDA    (*(struct st_irda    *)0xE8014000uL) /* IRDA */
+
+
+#define IRDAIRCR (IRDA.IRCR)
+
+
+typedef struct st_irda
+{
+                                                           /* IRDA             */
+    volatile uint8_t   IRCR;                                   /*  IRCR            */
+} r_io_irda_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h	(revision 374)
@@ -0,0 +1,197 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : jcu_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef JCU_IODEFINE_H
+#define JCU_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
+
+
+/* Start of channel array defines of JCU */
+
+/* Channel array defines of JCU_JCQTBL0 */
+/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
+#define JCU_JCQTBL0_COUNT  (4)
+#define JCU_JCQTBL0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
+#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
+#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
+#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
+
+/* End of channel array defines of JCU */
+
+
+#define JCUJCMOD (JCU.JCMOD)
+#define JCUJCCMD (JCU.JCCMD)
+#define JCUJCQTN (JCU.JCQTN)
+#define JCUJCHTN (JCU.JCHTN)
+#define JCUJCDRIU (JCU.JCDRIU)
+#define JCUJCDRID (JCU.JCDRID)
+#define JCUJCVSZU (JCU.JCVSZU)
+#define JCUJCVSZD (JCU.JCVSZD)
+#define JCUJCHSZU (JCU.JCHSZU)
+#define JCUJCHSZD (JCU.JCHSZD)
+#define JCUJCDTCU (JCU.JCDTCU)
+#define JCUJCDTCM (JCU.JCDTCM)
+#define JCUJCDTCD (JCU.JCDTCD)
+#define JCUJINTE0 (JCU.JINTE0)
+#define JCUJINTS0 (JCU.JINTS0)
+#define JCUJCDERR (JCU.JCDERR)
+#define JCUJCRST (JCU.JCRST)
+#define JCUJIFECNT (JCU.JIFECNT)
+#define JCUJIFESA (JCU.JIFESA)
+#define JCUJIFESOFST (JCU.JIFESOFST)
+#define JCUJIFEDA (JCU.JIFEDA)
+#define JCUJIFESLC (JCU.JIFESLC)
+#define JCUJIFEDDC (JCU.JIFEDDC)
+#define JCUJIFDCNT (JCU.JIFDCNT)
+#define JCUJIFDSA (JCU.JIFDSA)
+#define JCUJIFDDOFST (JCU.JIFDDOFST)
+#define JCUJIFDDA (JCU.JIFDDA)
+#define JCUJIFDSDC (JCU.JIFDSDC)
+#define JCUJIFDDLC (JCU.JIFDDLC)
+#define JCUJIFDADT (JCU.JIFDADT)
+#define JCUJINTE1 (JCU.JINTE1)
+#define JCUJINTS1 (JCU.JINTS1)
+#define JCUJIFESVSZ (JCU.JIFESVSZ)
+#define JCUJIFESHSZ (JCU.JIFESHSZ)
+#define JCUJCQTBL0 (JCU.JCQTBL0)
+#define JCUJCQTBL1 (JCU.JCQTBL1)
+#define JCUJCQTBL2 (JCU.JCQTBL2)
+#define JCUJCQTBL3 (JCU.JCQTBL3)
+#define JCUJCHTBD0 (JCU.JCHTBD0)
+#define JCUJCHTBA0 (JCU.JCHTBA0)
+#define JCUJCHTBD1 (JCU.JCHTBD1)
+#define JCUJCHTBA1 (JCU.JCHTBA1)
+
+
+typedef struct st_jcu
+{
+                                                           /* JCU              */
+    volatile uint8_t   JCMOD;                                  /*  JCMOD           */
+    volatile uint8_t   JCCMD;                                  /*  JCCMD           */
+    volatile uint8_t   dummy145[1];                            /*                  */
+    volatile uint8_t   JCQTN;                                  /*  JCQTN           */
+    volatile uint8_t   JCHTN;                                  /*  JCHTN           */
+    volatile uint8_t   JCDRIU;                                 /*  JCDRIU          */
+    volatile uint8_t   JCDRID;                                 /*  JCDRID          */
+    volatile uint8_t   JCVSZU;                                 /*  JCVSZU          */
+    volatile uint8_t   JCVSZD;                                 /*  JCVSZD          */
+    volatile uint8_t   JCHSZU;                                 /*  JCHSZU          */
+    volatile uint8_t   JCHSZD;                                 /*  JCHSZD          */
+    volatile uint8_t   JCDTCU;                                 /*  JCDTCU          */
+    volatile uint8_t   JCDTCM;                                 /*  JCDTCM          */
+    volatile uint8_t   JCDTCD;                                 /*  JCDTCD          */
+    volatile uint8_t   JINTE0;                                 /*  JINTE0          */
+    volatile uint8_t   JINTS0;                                 /*  JINTS0          */
+    volatile uint8_t   JCDERR;                                 /*  JCDERR          */
+    volatile uint8_t   JCRST;                                  /*  JCRST           */
+    volatile uint8_t   dummy146[46];                           /*                  */
+    volatile uint32_t  JIFECNT;                                /*  JIFECNT         */
+    volatile uint32_t  JIFESA;                                 /*  JIFESA          */
+    volatile uint32_t  JIFESOFST;                              /*  JIFESOFST       */
+    volatile uint32_t  JIFEDA;                                 /*  JIFEDA          */
+    volatile uint32_t  JIFESLC;                                /*  JIFESLC         */
+    volatile uint32_t  JIFEDDC;                                /*  JIFEDDC         */
+    volatile uint32_t  JIFDCNT;                                /*  JIFDCNT         */
+    volatile uint32_t  JIFDSA;                                 /*  JIFDSA          */
+    volatile uint32_t  JIFDDOFST;                              /*  JIFDDOFST       */
+    volatile uint32_t  JIFDDA;                                 /*  JIFDDA          */
+    volatile uint32_t  JIFDSDC;                                /*  JIFDSDC         */
+    volatile uint32_t  JIFDDLC;                                /*  JIFDDLC         */
+    volatile uint32_t  JIFDADT;                                /*  JIFDADT         */
+    volatile uint8_t   dummy147[24];                           /*                  */
+    volatile uint32_t  JINTE1;                                 /*  JINTE1          */
+    volatile uint32_t  JINTS1;                                 /*  JINTS1          */
+    volatile uint32_t  JIFESVSZ;                               /*  JIFESVSZ        */
+    volatile uint32_t  JIFESHSZ;                               /*  JIFESHSZ        */
+    volatile uint8_t   dummy148[100];                          /*                  */
+
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
+    volatile uint8_t   dummy149[63];                           /*                  */
+
+/* end of struct st_jcu_from_jcqtbl0 */
+
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL1;                                /*  JCQTBL1         */
+    volatile uint8_t   dummy150[63];                           /*                  */
+
+/* end of struct st_jcu_from_jcqtbl0 */
+
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL2;                                /*  JCQTBL2         */
+    volatile uint8_t   dummy151[63];                           /*                  */
+
+/* end of struct st_jcu_from_jcqtbl0 */
+
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL3;                                /*  JCQTBL3         */
+    volatile uint8_t   dummy152[63];                           /*                  */
+
+/* end of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCHTBD0;                                /*  JCHTBD0         */
+    volatile uint8_t   dummy153[31];                           /*                  */
+    volatile uint8_t   JCHTBA0;                                /*  JCHTBA0         */
+    volatile uint8_t   dummy154[223];                          /*                  */
+    volatile uint8_t   JCHTBD1;                                /*  JCHTBD1         */
+    volatile uint8_t   dummy155[31];                           /*                  */
+    volatile uint8_t   JCHTBA1;                                /*  JCHTBA1         */
+} r_io_jcu_t;
+
+
+typedef struct st_jcu_from_jcqtbl0
+{
+ 
+    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
+    volatile uint8_t   dummy1[63];                             /*                  */
+} r_io_jcu_from_jcqtbl0_t;
+
+
+/* Channel array defines of JCU (2)*/
+#ifdef  DECLARE_JCU_JCQTBL0_CHANNELS
+volatile struct st_jcu_from_jcqtbl0*  JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    JCU_JCQTBL0_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_JCU_JCQTBL0_CHANNELS */
+/* End of channel array defines of JCU (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h	(revision 374)
@@ -0,0 +1,231 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : l2c_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef L2C_IODEFINE_H
+#define L2C_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
+
+
+/* Start of channel array defines of L2C */
+
+/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
+/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  (8)
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
+#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
+#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
+#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
+#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
+#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
+#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
+#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
+
+/* End of channel array defines of L2C */
+
+
+#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
+#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
+#define L2CREG1_CONTROL (L2C.REG1_CONTROL)
+#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
+#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
+#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
+#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
+#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
+#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
+#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
+#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
+#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
+#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
+#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
+#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
+#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
+#define L2CREG7_INV_PA (L2C.REG7_INV_PA)
+#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
+#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
+#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
+#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
+#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
+#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
+#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
+#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
+#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
+#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
+#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
+#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
+#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
+#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
+#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
+#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
+#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
+#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
+#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
+#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
+#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
+#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
+#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
+#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
+#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
+#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
+#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
+#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
+#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
+#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
+
+
+typedef struct st_l2c
+{
+                                                           /* L2C              */
+    volatile uint32_t  REG0_CACHE_ID;                          /*  REG0_CACHE_ID   */
+    volatile uint32_t  REG0_CACHE_TYPE;                        /*  REG0_CACHE_TYPE */
+    volatile uint8_t   dummy8[248];                            /*                  */
+    volatile uint32_t  REG1_CONTROL;                           /*  REG1_CONTROL    */
+    volatile uint32_t  REG1_AUX_CONTROL;                       /*  REG1_AUX_CONTROL */
+    volatile uint32_t  REG1_TAG_RAM_CONTROL;                   /*  REG1_TAG_RAM_CONTROL */
+    volatile uint32_t  REG1_DATA_RAM_CONTROL;                  /*  REG1_DATA_RAM_CONTROL */
+    volatile uint8_t   dummy9[240];                            /*                  */
+    volatile uint32_t  REG2_EV_COUNTER_CTRL;                   /*  REG2_EV_COUNTER_CTRL */
+    volatile uint32_t  REG2_EV_COUNTER1_CFG;                   /*  REG2_EV_COUNTER1_CFG */
+    volatile uint32_t  REG2_EV_COUNTER0_CFG;                   /*  REG2_EV_COUNTER0_CFG */
+    volatile uint32_t  REG2_EV_COUNTER1;                       /*  REG2_EV_COUNTER1 */
+    volatile uint32_t  REG2_EV_COUNTER0;                       /*  REG2_EV_COUNTER0 */
+    volatile uint32_t  REG2_INT_MASK;                          /*  REG2_INT_MASK   */
+    volatile uint32_t  REG2_INT_MASK_STATUS;                   /*  REG2_INT_MASK_STATUS */
+    volatile uint32_t  REG2_INT_RAW_STATUS;                    /*  REG2_INT_RAW_STATUS */
+    volatile uint32_t  REG2_INT_CLEAR;                         /*  REG2_INT_CLEAR  */
+    volatile uint8_t   dummy10[1292];                          /*                  */
+    volatile uint32_t  REG7_CACHE_SYNC;                        /*  REG7_CACHE_SYNC */
+    volatile uint8_t   dummy11[60];                            /*                  */
+    volatile uint32_t  REG7_INV_PA;                            /*  REG7_INV_PA     */
+    volatile uint8_t   dummy12[8];                             /*                  */
+    volatile uint32_t  REG7_INV_WAY;                           /*  REG7_INV_WAY    */
+    volatile uint8_t   dummy13[48];                            /*                  */
+    volatile uint32_t  REG7_CLEAN_PA;                          /*  REG7_CLEAN_PA   */
+    volatile uint8_t   dummy14[4];                             /*                  */
+    volatile uint32_t  REG7_CLEAN_INDEX;                       /*  REG7_CLEAN_INDEX */
+    volatile uint32_t  REG7_CLEAN_WAY;                         /*  REG7_CLEAN_WAY  */
+    volatile uint8_t   dummy15[48];                            /*                  */
+    volatile uint32_t  REG7_CLEAN_INV_PA;                      /*  REG7_CLEAN_INV_PA */
+    volatile uint8_t   dummy16[4];                             /*                  */
+    volatile uint32_t  REG7_CLEAN_INV_INDEX;                   /*  REG7_CLEAN_INV_INDEX */
+    volatile uint32_t  REG7_CLEAN_INV_WAY;                     /*  REG7_CLEAN_INV_WAY */
+    volatile uint8_t   dummy17[256];                           /*                  */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
+    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN1;                       /*  REG9_D_LOCKDOWN1 */
+    volatile uint32_t  REG9_I_LOCKDOWN1;                       /*  REG9_I_LOCKDOWN1 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN2;                       /*  REG9_D_LOCKDOWN2 */
+    volatile uint32_t  REG9_I_LOCKDOWN2;                       /*  REG9_I_LOCKDOWN2 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN3;                       /*  REG9_D_LOCKDOWN3 */
+    volatile uint32_t  REG9_I_LOCKDOWN3;                       /*  REG9_I_LOCKDOWN3 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN4;                       /*  REG9_D_LOCKDOWN4 */
+    volatile uint32_t  REG9_I_LOCKDOWN4;                       /*  REG9_I_LOCKDOWN4 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN5;                       /*  REG9_D_LOCKDOWN5 */
+    volatile uint32_t  REG9_I_LOCKDOWN5;                       /*  REG9_I_LOCKDOWN5 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN6;                       /*  REG9_D_LOCKDOWN6 */
+    volatile uint32_t  REG9_I_LOCKDOWN6;                       /*  REG9_I_LOCKDOWN6 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN7;                       /*  REG9_D_LOCKDOWN7 */
+    volatile uint32_t  REG9_I_LOCKDOWN7;                       /*  REG9_I_LOCKDOWN7 */
+
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint8_t   dummy18[16];                            /*                  */
+    volatile uint32_t  REG9_LOCK_LINE_EN;                      /*  REG9_LOCK_LINE_EN */
+    volatile uint32_t  REG9_UNLOCK_WAY;                        /*  REG9_UNLOCK_WAY */
+    volatile uint8_t   dummy19[680];                           /*                  */
+    volatile uint32_t  REG12_ADDR_FILTERING_START;             /*  REG12_ADDR_FILTERING_START */
+    volatile uint32_t  REG12_ADDR_FILTERING_END;               /*  REG12_ADDR_FILTERING_END */
+    volatile uint8_t   dummy20[824];                           /*                  */
+    volatile uint32_t  REG15_DEBUG_CTRL;                       /*  REG15_DEBUG_CTRL */
+    volatile uint8_t   dummy21[28];                            /*                  */
+    volatile uint32_t  REG15_PREFETCH_CTRL;                    /*  REG15_PREFETCH_CTRL */
+    volatile uint8_t   dummy22[28];                            /*                  */
+    volatile uint32_t  REG15_POWER_CTRL;                       /*  REG15_POWER_CTRL */
+} r_io_l2c_t;
+
+
+typedef struct st_l2c_from_reg9_d_lockdown0
+{
+ 
+    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
+    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
+
+
+/* Channel array defines of L2C (2)*/
+#ifdef  DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
+volatile struct st_l2c_from_reg9_d_lockdown0*  L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
+/* End of channel array defines of L2C (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h	(revision 374)
@@ -0,0 +1,161 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lin_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef LIN_IODEFINE_H
+#define LIN_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
+#define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
+
+
+/* Start of channel array defines of LIN */
+
+/* Channel array defines of LIN */
+/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
+#define LIN_COUNT  (2)
+#define LIN_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &LIN0, &LIN1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of LIN */
+
+
+#define LIN0RLN30LWBR (LIN0.RLN3nLWBR)
+#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0)
+#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1)
+#define LIN0RLN30LSTC (LIN0.RLN3nLSTC)
+#define LIN0RLN30LMD (LIN0.RLN3nLMD)
+#define LIN0RLN30LBFC (LIN0.RLN3nLBFC)
+#define LIN0RLN30LSC (LIN0.RLN3nLSC)
+#define LIN0RLN30LWUP (LIN0.RLN3nLWUP)
+#define LIN0RLN30LIE (LIN0.RLN3nLIE)
+#define LIN0RLN30LEDE (LIN0.RLN3nLEDE)
+#define LIN0RLN30LCUC (LIN0.RLN3nLCUC)
+#define LIN0RLN30LTRC (LIN0.RLN3nLTRC)
+#define LIN0RLN30LMST (LIN0.RLN3nLMST)
+#define LIN0RLN30LST (LIN0.RLN3nLST)
+#define LIN0RLN30LEST (LIN0.RLN3nLEST)
+#define LIN0RLN30LDFC (LIN0.RLN3nLDFC)
+#define LIN0RLN30LIDB (LIN0.RLN3nLIDB)
+#define LIN0RLN30LCBR (LIN0.RLN3nLCBR)
+#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1)
+#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2)
+#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3)
+#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4)
+#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5)
+#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6)
+#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7)
+#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8)
+#define LIN1RLN31LWBR (LIN1.RLN3nLWBR)
+#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0)
+#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1)
+#define LIN1RLN31LSTC (LIN1.RLN3nLSTC)
+#define LIN1RLN31LMD (LIN1.RLN3nLMD)
+#define LIN1RLN31LBFC (LIN1.RLN3nLBFC)
+#define LIN1RLN31LSC (LIN1.RLN3nLSC)
+#define LIN1RLN31LWUP (LIN1.RLN3nLWUP)
+#define LIN1RLN31LIE (LIN1.RLN3nLIE)
+#define LIN1RLN31LEDE (LIN1.RLN3nLEDE)
+#define LIN1RLN31LCUC (LIN1.RLN3nLCUC)
+#define LIN1RLN31LTRC (LIN1.RLN3nLTRC)
+#define LIN1RLN31LMST (LIN1.RLN3nLMST)
+#define LIN1RLN31LST (LIN1.RLN3nLST)
+#define LIN1RLN31LEST (LIN1.RLN3nLEST)
+#define LIN1RLN31LDFC (LIN1.RLN3nLDFC)
+#define LIN1RLN31LIDB (LIN1.RLN3nLIDB)
+#define LIN1RLN31LCBR (LIN1.RLN3nLCBR)
+#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1)
+#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2)
+#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3)
+#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4)
+#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5)
+#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6)
+#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7)
+#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8)
+
+#define LIN_LDBn_COUNT (8)
+
+
+typedef struct st_lin
+{
+                                                           /* LIN              */
+    volatile uint8_t   dummy1[1];                              /*                  */
+    volatile uint8_t   RLN3nLWBR;                              /*  RLN3nLWBR       */
+    volatile uint8_t   RLN3nLBRP0;                             /*  RLN3nLBRP0      */
+    volatile uint8_t   RLN3nLBRP1;                             /*  RLN3nLBRP1      */
+    volatile uint8_t   RLN3nLSTC;                              /*  RLN3nLSTC       */
+    volatile uint8_t   dummy2[3];                              /*                  */
+    volatile uint8_t   RLN3nLMD;                               /*  RLN3nLMD        */
+    volatile uint8_t   RLN3nLBFC;                              /*  RLN3nLBFC       */
+    volatile uint8_t   RLN3nLSC;                               /*  RLN3nLSC        */
+    volatile uint8_t   RLN3nLWUP;                              /*  RLN3nLWUP       */
+    volatile uint8_t   RLN3nLIE;                               /*  RLN3nLIE        */
+    volatile uint8_t   RLN3nLEDE;                              /*  RLN3nLEDE       */
+    volatile uint8_t   RLN3nLCUC;                              /*  RLN3nLCUC       */
+    volatile uint8_t   dummy3[1];                              /*                  */
+    volatile uint8_t   RLN3nLTRC;                              /*  RLN3nLTRC       */
+    volatile uint8_t   RLN3nLMST;                              /*  RLN3nLMST       */
+    volatile uint8_t   RLN3nLST;                               /*  RLN3nLST        */
+    volatile uint8_t   RLN3nLEST;                              /*  RLN3nLEST       */
+    volatile uint8_t   RLN3nLDFC;                              /*  RLN3nLDFC       */
+    volatile uint8_t   RLN3nLIDB;                              /*  RLN3nLIDB       */
+    volatile uint8_t   RLN3nLCBR;                              /*  RLN3nLCBR       */
+    volatile uint8_t   dummy4[1];                              /*                  */
+
+/* #define LIN_LDBn_COUNT (8) */
+    volatile uint8_t   RLN3nLDBR1;                             /*  RLN3nLDBR1      */
+    volatile uint8_t   RLN3nLDBR2;                             /*  RLN3nLDBR2      */
+    volatile uint8_t   RLN3nLDBR3;                             /*  RLN3nLDBR3      */
+    volatile uint8_t   RLN3nLDBR4;                             /*  RLN3nLDBR4      */
+    volatile uint8_t   RLN3nLDBR5;                             /*  RLN3nLDBR5      */
+    volatile uint8_t   RLN3nLDBR6;                             /*  RLN3nLDBR6      */
+    volatile uint8_t   RLN3nLDBR7;                             /*  RLN3nLDBR7      */
+    volatile uint8_t   RLN3nLDBR8;                             /*  RLN3nLDBR8      */
+} r_io_lin_t;
+
+
+/* Channel array defines of LIN (2)*/
+#ifdef  DECLARE_LIN_CHANNELS
+volatile struct st_lin*  LIN[ LIN_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    LIN_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_LIN_CHANNELS */
+/* End of channel array defines of LIN (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h	(revision 374)
@@ -0,0 +1,63 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lvds_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef LVDS_IODEFINE_H
+#define LVDS_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
+
+
+#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE)
+#define LVDSLVDSFCL (LVDS.LVDSFCL)
+#define LVDSLCLKSELR (LVDS.LCLKSELR)
+#define LVDSLPLLSETR (LVDS.LPLLSETR)
+#define LVDSLPHYACC (LVDS.LPHYACC)
+
+
+typedef struct st_lvds
+{
+                                                           /* LVDS             */
+    volatile uint32_t  LVDS_UPDATE;                            /*  LVDS_UPDATE     */
+    volatile uint32_t  LVDSFCL;                                /*  LVDSFCL         */
+    volatile uint8_t   dummy608[24];                           /*                  */
+    volatile uint32_t  LCLKSELR;                               /*  LCLKSELR        */
+    volatile uint32_t  LPLLSETR;                               /*  LPLLSETR        */
+    volatile uint8_t   dummy609[4];                            /*                  */
+    volatile uint32_t  LPHYACC;                                /*  LPHYACC         */
+} r_io_lvds_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h	(revision 374)
@@ -0,0 +1,579 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mlb_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef MLB_IODEFINE_H
+#define MLB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define MLB     (*(struct st_mlb     *)0xE8034000uL) /* MLB */
+
+
+/* Start of channel array defines of MLB */
+
+/* Channel array defines of MLB_FROM_CECR0_ARRAY */
+/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
+#define MLB_FROM_CECR0_ARRAY_COUNT  (31)
+#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
+    &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \
+    &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \
+    &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */
+#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */
+#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */
+#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */
+#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */
+#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */
+#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */
+#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */
+#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */
+#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */
+#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */
+#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */
+#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */
+#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */
+#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */
+#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */
+#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */
+#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */
+#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */
+#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */
+#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */
+#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */
+#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */
+#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */
+#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */
+#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */
+#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */
+#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */
+#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */
+#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
+#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
+
+/* End of channel array defines of MLB */
+
+
+#define MLBDCCR (MLB.DCCR)
+#define MLBSSCR (MLB.SSCR)
+#define MLBSDCR (MLB.SDCR)
+#define MLBSMCR (MLB.SMCR)
+#define MLBVCCR (MLB.VCCR)
+#define MLBSBCR (MLB.SBCR)
+#define MLBABCR (MLB.ABCR)
+#define MLBCBCR (MLB.CBCR)
+#define MLBIBCR (MLB.IBCR)
+#define MLBCICR (MLB.CICR)
+#define MLBCECR0 (MLB.CECR0)
+#define MLBCSCR0 (MLB.CSCR0)
+#define MLBCCBCR0 (MLB.CCBCR0)
+#define MLBCNBCR0 (MLB.CNBCR0)
+#define MLBCECR1 (MLB.CECR1)
+#define MLBCSCR1 (MLB.CSCR1)
+#define MLBCCBCR1 (MLB.CCBCR1)
+#define MLBCNBCR1 (MLB.CNBCR1)
+#define MLBCECR2 (MLB.CECR2)
+#define MLBCSCR2 (MLB.CSCR2)
+#define MLBCCBCR2 (MLB.CCBCR2)
+#define MLBCNBCR2 (MLB.CNBCR2)
+#define MLBCECR3 (MLB.CECR3)
+#define MLBCSCR3 (MLB.CSCR3)
+#define MLBCCBCR3 (MLB.CCBCR3)
+#define MLBCNBCR3 (MLB.CNBCR3)
+#define MLBCECR4 (MLB.CECR4)
+#define MLBCSCR4 (MLB.CSCR4)
+#define MLBCCBCR4 (MLB.CCBCR4)
+#define MLBCNBCR4 (MLB.CNBCR4)
+#define MLBCECR5 (MLB.CECR5)
+#define MLBCSCR5 (MLB.CSCR5)
+#define MLBCCBCR5 (MLB.CCBCR5)
+#define MLBCNBCR5 (MLB.CNBCR5)
+#define MLBCECR6 (MLB.CECR6)
+#define MLBCSCR6 (MLB.CSCR6)
+#define MLBCCBCR6 (MLB.CCBCR6)
+#define MLBCNBCR6 (MLB.CNBCR6)
+#define MLBCECR7 (MLB.CECR7)
+#define MLBCSCR7 (MLB.CSCR7)
+#define MLBCCBCR7 (MLB.CCBCR7)
+#define MLBCNBCR7 (MLB.CNBCR7)
+#define MLBCECR8 (MLB.CECR8)
+#define MLBCSCR8 (MLB.CSCR8)
+#define MLBCCBCR8 (MLB.CCBCR8)
+#define MLBCNBCR8 (MLB.CNBCR8)
+#define MLBCECR9 (MLB.CECR9)
+#define MLBCSCR9 (MLB.CSCR9)
+#define MLBCCBCR9 (MLB.CCBCR9)
+#define MLBCNBCR9 (MLB.CNBCR9)
+#define MLBCECR10 (MLB.CECR10)
+#define MLBCSCR10 (MLB.CSCR10)
+#define MLBCCBCR10 (MLB.CCBCR10)
+#define MLBCNBCR10 (MLB.CNBCR10)
+#define MLBCECR11 (MLB.CECR11)
+#define MLBCSCR11 (MLB.CSCR11)
+#define MLBCCBCR11 (MLB.CCBCR11)
+#define MLBCNBCR11 (MLB.CNBCR11)
+#define MLBCECR12 (MLB.CECR12)
+#define MLBCSCR12 (MLB.CSCR12)
+#define MLBCCBCR12 (MLB.CCBCR12)
+#define MLBCNBCR12 (MLB.CNBCR12)
+#define MLBCECR13 (MLB.CECR13)
+#define MLBCSCR13 (MLB.CSCR13)
+#define MLBCCBCR13 (MLB.CCBCR13)
+#define MLBCNBCR13 (MLB.CNBCR13)
+#define MLBCECR14 (MLB.CECR14)
+#define MLBCSCR14 (MLB.CSCR14)
+#define MLBCCBCR14 (MLB.CCBCR14)
+#define MLBCNBCR14 (MLB.CNBCR14)
+#define MLBCECR15 (MLB.CECR15)
+#define MLBCSCR15 (MLB.CSCR15)
+#define MLBCCBCR15 (MLB.CCBCR15)
+#define MLBCNBCR15 (MLB.CNBCR15)
+#define MLBCECR16 (MLB.CECR16)
+#define MLBCSCR16 (MLB.CSCR16)
+#define MLBCCBCR16 (MLB.CCBCR16)
+#define MLBCNBCR16 (MLB.CNBCR16)
+#define MLBCECR17 (MLB.CECR17)
+#define MLBCSCR17 (MLB.CSCR17)
+#define MLBCCBCR17 (MLB.CCBCR17)
+#define MLBCNBCR17 (MLB.CNBCR17)
+#define MLBCECR18 (MLB.CECR18)
+#define MLBCSCR18 (MLB.CSCR18)
+#define MLBCCBCR18 (MLB.CCBCR18)
+#define MLBCNBCR18 (MLB.CNBCR18)
+#define MLBCECR19 (MLB.CECR19)
+#define MLBCSCR19 (MLB.CSCR19)
+#define MLBCCBCR19 (MLB.CCBCR19)
+#define MLBCNBCR19 (MLB.CNBCR19)
+#define MLBCECR20 (MLB.CECR20)
+#define MLBCSCR20 (MLB.CSCR20)
+#define MLBCCBCR20 (MLB.CCBCR20)
+#define MLBCNBCR20 (MLB.CNBCR20)
+#define MLBCECR21 (MLB.CECR21)
+#define MLBCSCR21 (MLB.CSCR21)
+#define MLBCCBCR21 (MLB.CCBCR21)
+#define MLBCNBCR21 (MLB.CNBCR21)
+#define MLBCECR22 (MLB.CECR22)
+#define MLBCSCR22 (MLB.CSCR22)
+#define MLBCCBCR22 (MLB.CCBCR22)
+#define MLBCNBCR22 (MLB.CNBCR22)
+#define MLBCECR23 (MLB.CECR23)
+#define MLBCSCR23 (MLB.CSCR23)
+#define MLBCCBCR23 (MLB.CCBCR23)
+#define MLBCNBCR23 (MLB.CNBCR23)
+#define MLBCECR24 (MLB.CECR24)
+#define MLBCSCR24 (MLB.CSCR24)
+#define MLBCCBCR24 (MLB.CCBCR24)
+#define MLBCNBCR24 (MLB.CNBCR24)
+#define MLBCECR25 (MLB.CECR25)
+#define MLBCSCR25 (MLB.CSCR25)
+#define MLBCCBCR25 (MLB.CCBCR25)
+#define MLBCNBCR25 (MLB.CNBCR25)
+#define MLBCECR26 (MLB.CECR26)
+#define MLBCSCR26 (MLB.CSCR26)
+#define MLBCCBCR26 (MLB.CCBCR26)
+#define MLBCNBCR26 (MLB.CNBCR26)
+#define MLBCECR27 (MLB.CECR27)
+#define MLBCSCR27 (MLB.CSCR27)
+#define MLBCCBCR27 (MLB.CCBCR27)
+#define MLBCNBCR27 (MLB.CNBCR27)
+#define MLBCECR28 (MLB.CECR28)
+#define MLBCSCR28 (MLB.CSCR28)
+#define MLBCCBCR28 (MLB.CCBCR28)
+#define MLBCNBCR28 (MLB.CNBCR28)
+#define MLBCECR29 (MLB.CECR29)
+#define MLBCSCR29 (MLB.CSCR29)
+#define MLBCCBCR29 (MLB.CCBCR29)
+#define MLBCNBCR29 (MLB.CNBCR29)
+#define MLBCECR30 (MLB.CECR30)
+#define MLBCSCR30 (MLB.CSCR30)
+#define MLBCCBCR30 (MLB.CCBCR30)
+#define MLBCNBCR30 (MLB.CNBCR30)
+#define MLBLCBCR0 (MLB.LCBCR0)
+#define MLBLCBCR1 (MLB.LCBCR1)
+#define MLBLCBCR2 (MLB.LCBCR2)
+#define MLBLCBCR3 (MLB.LCBCR3)
+#define MLBLCBCR4 (MLB.LCBCR4)
+#define MLBLCBCR5 (MLB.LCBCR5)
+#define MLBLCBCR6 (MLB.LCBCR6)
+#define MLBLCBCR7 (MLB.LCBCR7)
+#define MLBLCBCR8 (MLB.LCBCR8)
+#define MLBLCBCR9 (MLB.LCBCR9)
+#define MLBLCBCR10 (MLB.LCBCR10)
+#define MLBLCBCR11 (MLB.LCBCR11)
+#define MLBLCBCR12 (MLB.LCBCR12)
+#define MLBLCBCR13 (MLB.LCBCR13)
+#define MLBLCBCR14 (MLB.LCBCR14)
+#define MLBLCBCR15 (MLB.LCBCR15)
+#define MLBLCBCR16 (MLB.LCBCR16)
+#define MLBLCBCR17 (MLB.LCBCR17)
+#define MLBLCBCR18 (MLB.LCBCR18)
+#define MLBLCBCR19 (MLB.LCBCR19)
+#define MLBLCBCR20 (MLB.LCBCR20)
+#define MLBLCBCR21 (MLB.LCBCR21)
+#define MLBLCBCR22 (MLB.LCBCR22)
+#define MLBLCBCR23 (MLB.LCBCR23)
+#define MLBLCBCR24 (MLB.LCBCR24)
+#define MLBLCBCR25 (MLB.LCBCR25)
+#define MLBLCBCR26 (MLB.LCBCR26)
+#define MLBLCBCR27 (MLB.LCBCR27)
+#define MLBLCBCR28 (MLB.LCBCR28)
+#define MLBLCBCR29 (MLB.LCBCR29)
+#define MLBLCBCR30 (MLB.LCBCR30)
+
+#define MLB_LCBCR0_COUNT (31)
+
+
+typedef struct st_mlb
+{
+                                                           /* MLB              */
+    volatile uint32_t  DCCR;                                   /*  DCCR            */
+    volatile uint32_t  SSCR;                                   /*  SSCR            */
+    volatile uint32_t  SDCR;                                   /*  SDCR            */
+    volatile uint32_t  SMCR;                                   /*  SMCR            */
+    volatile uint8_t   dummy156[12];                           /*                  */
+    volatile uint32_t  VCCR;                                   /*  VCCR            */
+    volatile uint32_t  SBCR;                                   /*  SBCR            */
+    volatile uint32_t  ABCR;                                   /*  ABCR            */
+    volatile uint32_t  CBCR;                                   /*  CBCR            */
+    volatile uint32_t  IBCR;                                   /*  IBCR            */
+    volatile uint32_t  CICR;                                   /*  CICR            */
+    volatile uint8_t   dummy157[12];                           /*                  */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR1;                                  /*  CECR1           */
+    volatile uint32_t  CSCR1;                                  /*  CSCR1           */
+    volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
+    volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR2;                                  /*  CECR2           */
+    volatile uint32_t  CSCR2;                                  /*  CSCR2           */
+    volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
+    volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR3;                                  /*  CECR3           */
+    volatile uint32_t  CSCR3;                                  /*  CSCR3           */
+    volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
+    volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR4;                                  /*  CECR4           */
+    volatile uint32_t  CSCR4;                                  /*  CSCR4           */
+    volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
+    volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR5;                                  /*  CECR5           */
+    volatile uint32_t  CSCR5;                                  /*  CSCR5           */
+    volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
+    volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR6;                                  /*  CECR6           */
+    volatile uint32_t  CSCR6;                                  /*  CSCR6           */
+    volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
+    volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR7;                                  /*  CECR7           */
+    volatile uint32_t  CSCR7;                                  /*  CSCR7           */
+    volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
+    volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR8;                                  /*  CECR8           */
+    volatile uint32_t  CSCR8;                                  /*  CSCR8           */
+    volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
+    volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR9;                                  /*  CECR9           */
+    volatile uint32_t  CSCR9;                                  /*  CSCR9           */
+    volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
+    volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR10;                                 /*  CECR10          */
+    volatile uint32_t  CSCR10;                                 /*  CSCR10          */
+    volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
+    volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR11;                                 /*  CECR11          */
+    volatile uint32_t  CSCR11;                                 /*  CSCR11          */
+    volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
+    volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR12;                                 /*  CECR12          */
+    volatile uint32_t  CSCR12;                                 /*  CSCR12          */
+    volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
+    volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR13;                                 /*  CECR13          */
+    volatile uint32_t  CSCR13;                                 /*  CSCR13          */
+    volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
+    volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR14;                                 /*  CECR14          */
+    volatile uint32_t  CSCR14;                                 /*  CSCR14          */
+    volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
+    volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR15;                                 /*  CECR15          */
+    volatile uint32_t  CSCR15;                                 /*  CSCR15          */
+    volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
+    volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR16;                                 /*  CECR16          */
+    volatile uint32_t  CSCR16;                                 /*  CSCR16          */
+    volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
+    volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR17;                                 /*  CECR17          */
+    volatile uint32_t  CSCR17;                                 /*  CSCR17          */
+    volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
+    volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR18;                                 /*  CECR18          */
+    volatile uint32_t  CSCR18;                                 /*  CSCR18          */
+    volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
+    volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR19;                                 /*  CECR19          */
+    volatile uint32_t  CSCR19;                                 /*  CSCR19          */
+    volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
+    volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR20;                                 /*  CECR20          */
+    volatile uint32_t  CSCR20;                                 /*  CSCR20          */
+    volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
+    volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR21;                                 /*  CECR21          */
+    volatile uint32_t  CSCR21;                                 /*  CSCR21          */
+    volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
+    volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR22;                                 /*  CECR22          */
+    volatile uint32_t  CSCR22;                                 /*  CSCR22          */
+    volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
+    volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR23;                                 /*  CECR23          */
+    volatile uint32_t  CSCR23;                                 /*  CSCR23          */
+    volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
+    volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR24;                                 /*  CECR24          */
+    volatile uint32_t  CSCR24;                                 /*  CSCR24          */
+    volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
+    volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR25;                                 /*  CECR25          */
+    volatile uint32_t  CSCR25;                                 /*  CSCR25          */
+    volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
+    volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR26;                                 /*  CECR26          */
+    volatile uint32_t  CSCR26;                                 /*  CSCR26          */
+    volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
+    volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR27;                                 /*  CECR27          */
+    volatile uint32_t  CSCR27;                                 /*  CSCR27          */
+    volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
+    volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR28;                                 /*  CECR28          */
+    volatile uint32_t  CSCR28;                                 /*  CSCR28          */
+    volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
+    volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR29;                                 /*  CECR29          */
+    volatile uint32_t  CSCR29;                                 /*  CSCR29          */
+    volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
+    volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR30;                                 /*  CECR30          */
+    volatile uint32_t  CSCR30;                                 /*  CSCR30          */
+    volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
+    volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
+
+/* end of struct st_mlb_from_cecr0 */
+    volatile uint8_t   dummy158[80];                           /*                  */
+
+/* #define MLB_LCBCR0_COUNT (31) */
+    volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
+    volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
+    volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
+    volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
+    volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
+    volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
+    volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
+    volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
+    volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
+    volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
+    volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
+    volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
+    volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
+    volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
+    volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
+    volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
+    volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
+    volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
+    volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
+    volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
+    volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
+    volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
+    volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
+    volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
+    volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
+    volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
+    volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
+    volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
+    volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
+    volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
+    volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
+} r_io_mlb_t;
+
+
+typedef struct st_mlb_from_cecr0
+{
+ 
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+} r_io_mlb_from_cecr0_t;
+
+
+/* Channel array defines of MLB (2)*/
+#ifdef  DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS
+volatile struct st_mlb_from_cecr0*  MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    MLB_FROM_CECR0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */
+/* End of channel array defines of MLB (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h	(revision 374)
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mmc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef MMC_IODEFINE_H
+#define MMC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
+
+
+#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
+#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
+#define MMCCE_ARG (MMC.CE_ARG)
+#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
+#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
+#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
+#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
+#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
+#define MMCCE_RESP3 (MMC.CE_RESP3)
+#define MMCCE_RESP2 (MMC.CE_RESP2)
+#define MMCCE_RESP1 (MMC.CE_RESP1)
+#define MMCCE_RESP0 (MMC.CE_RESP0)
+#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
+#define MMCCE_DATA (MMC.CE_DATA)
+#define MMCCE_INT (MMC.CE_INT)
+#define MMCCE_INT_EN (MMC.CE_INT_EN)
+#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
+#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
+#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
+#define MMCCE_DETECT (MMC.CE_DETECT)
+#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
+#define MMCCE_VERSION (MMC.CE_VERSION)
+
+#define MMC_CE_RESPn_COUNT (4)
+
+
+typedef struct st_mmc
+{
+                                                           /* MMC              */
+    volatile uint16_t CE_CMD_SETH;                      /*  CE_CMD_SETH */
+    volatile uint16_t CE_CMD_SETL;                      /*  CE_CMD_SETL */
+    volatile uint8_t   dummy182[4];                            /*                  */
+    volatile uint32_t  CE_ARG;                                 /*  CE_ARG          */
+    volatile uint32_t  CE_ARG_CMD12;                           /*  CE_ARG_CMD12    */
+    volatile uint32_t  CE_CMD_CTRL;                            /*  CE_CMD_CTRL     */
+    volatile uint32_t  CE_BLOCK_SET;                           /*  CE_BLOCK_SET    */
+    volatile uint32_t  CE_CLK_CTRL;                            /*  CE_CLK_CTRL     */
+    volatile uint32_t  CE_BUF_ACC;                             /*  CE_BUF_ACC      */
+
+/* #define MMC_CE_RESPn_COUNT (4) */
+    volatile uint32_t  CE_RESP3;                               /*  CE_RESP3        */
+    volatile uint32_t  CE_RESP2;                               /*  CE_RESP2        */
+    volatile uint32_t  CE_RESP1;                               /*  CE_RESP1        */
+    volatile uint32_t  CE_RESP0;                               /*  CE_RESP0        */
+    volatile uint32_t  CE_RESP_CMD12;                          /*  CE_RESP_CMD12   */
+    volatile uint32_t  CE_DATA;                                /*  CE_DATA         */
+    volatile uint8_t   dummy183[8];                            /*                  */
+    volatile uint32_t  CE_INT;                                 /*  CE_INT          */
+    volatile uint32_t  CE_INT_EN;                              /*  CE_INT_EN       */
+    volatile uint32_t  CE_HOST_STS1;                           /*  CE_HOST_STS1    */
+    volatile uint32_t  CE_HOST_STS2;                           /*  CE_HOST_STS2    */
+    volatile uint8_t   dummy184[12];                           /*                  */
+    volatile uint32_t  CE_DMA_MODE;                            /*  CE_DMA_MODE     */
+    volatile uint8_t   dummy185[16];                           /*                  */
+    volatile uint32_t  CE_DETECT;                              /*  CE_DETECT       */
+    volatile uint32_t  CE_ADD_MODE;                            /*  CE_ADD_MODE     */
+    volatile uint8_t   dummy186[4];                            /*                  */
+    volatile uint32_t  CE_VERSION;                             /*  CE_VERSION      */
+} r_io_mmc_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h	(revision 374)
@@ -0,0 +1,226 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mtu2_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef MTU2_IODEFINE_H
+#define MTU2_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
+
+
+#define MTU2TCR_2 (MTU2.TCR_2)
+#define MTU2TMDR_2 (MTU2.TMDR_2)
+#define MTU2TIOR_2 (MTU2.TIOR_2)
+#define MTU2TIER_2 (MTU2.TIER_2)
+#define MTU2TSR_2 (MTU2.TSR_2)
+#define MTU2TCNT_2 (MTU2.TCNT_2)
+#define MTU2TGRA_2 (MTU2.TGRA_2)
+#define MTU2TGRB_2 (MTU2.TGRB_2)
+#define MTU2TCR_3 (MTU2.TCR_3)
+#define MTU2TCR_4 (MTU2.TCR_4)
+#define MTU2TMDR_3 (MTU2.TMDR_3)
+#define MTU2TMDR_4 (MTU2.TMDR_4)
+#define MTU2TIORH_3 (MTU2.TIORH_3)
+#define MTU2TIORL_3 (MTU2.TIORL_3)
+#define MTU2TIORH_4 (MTU2.TIORH_4)
+#define MTU2TIORL_4 (MTU2.TIORL_4)
+#define MTU2TIER_3 (MTU2.TIER_3)
+#define MTU2TIER_4 (MTU2.TIER_4)
+#define MTU2TOER (MTU2.TOER)
+#define MTU2TGCR (MTU2.TGCR)
+#define MTU2TOCR1 (MTU2.TOCR1)
+#define MTU2TOCR2 (MTU2.TOCR2)
+#define MTU2TCNT_3 (MTU2.TCNT_3)
+#define MTU2TCNT_4 (MTU2.TCNT_4)
+#define MTU2TCDR (MTU2.TCDR)
+#define MTU2TDDR (MTU2.TDDR)
+#define MTU2TGRA_3 (MTU2.TGRA_3)
+#define MTU2TGRB_3 (MTU2.TGRB_3)
+#define MTU2TGRA_4 (MTU2.TGRA_4)
+#define MTU2TGRB_4 (MTU2.TGRB_4)
+#define MTU2TCNTS (MTU2.TCNTS)
+#define MTU2TCBR (MTU2.TCBR)
+#define MTU2TGRC_3 (MTU2.TGRC_3)
+#define MTU2TGRD_3 (MTU2.TGRD_3)
+#define MTU2TGRC_4 (MTU2.TGRC_4)
+#define MTU2TGRD_4 (MTU2.TGRD_4)
+#define MTU2TSR_3 (MTU2.TSR_3)
+#define MTU2TSR_4 (MTU2.TSR_4)
+#define MTU2TITCR (MTU2.TITCR)
+#define MTU2TITCNT (MTU2.TITCNT)
+#define MTU2TBTER (MTU2.TBTER)
+#define MTU2TDER (MTU2.TDER)
+#define MTU2TOLBR (MTU2.TOLBR)
+#define MTU2TBTM_3 (MTU2.TBTM_3)
+#define MTU2TBTM_4 (MTU2.TBTM_4)
+#define MTU2TADCR (MTU2.TADCR)
+#define MTU2TADCORA_4 (MTU2.TADCORA_4)
+#define MTU2TADCORB_4 (MTU2.TADCORB_4)
+#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4)
+#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4)
+#define MTU2TWCR (MTU2.TWCR)
+#define MTU2TSTR (MTU2.TSTR)
+#define MTU2TSYR (MTU2.TSYR)
+#define MTU2TRWER (MTU2.TRWER)
+#define MTU2TCR_0 (MTU2.TCR_0)
+#define MTU2TMDR_0 (MTU2.TMDR_0)
+#define MTU2TIORH_0 (MTU2.TIORH_0)
+#define MTU2TIORL_0 (MTU2.TIORL_0)
+#define MTU2TIER_0 (MTU2.TIER_0)
+#define MTU2TSR_0 (MTU2.TSR_0)
+#define MTU2TCNT_0 (MTU2.TCNT_0)
+#define MTU2TGRA_0 (MTU2.TGRA_0)
+#define MTU2TGRB_0 (MTU2.TGRB_0)
+#define MTU2TGRC_0 (MTU2.TGRC_0)
+#define MTU2TGRD_0 (MTU2.TGRD_0)
+#define MTU2TGRE_0 (MTU2.TGRE_0)
+#define MTU2TGRF_0 (MTU2.TGRF_0)
+#define MTU2TIER2_0 (MTU2.TIER2_0)
+#define MTU2TSR2_0 (MTU2.TSR2_0)
+#define MTU2TBTM_0 (MTU2.TBTM_0)
+#define MTU2TCR_1 (MTU2.TCR_1)
+#define MTU2TMDR_1 (MTU2.TMDR_1)
+#define MTU2TIOR_1 (MTU2.TIOR_1)
+#define MTU2TIER_1 (MTU2.TIER_1)
+#define MTU2TSR_1 (MTU2.TSR_1)
+#define MTU2TCNT_1 (MTU2.TCNT_1)
+#define MTU2TGRA_1 (MTU2.TGRA_1)
+#define MTU2TGRB_1 (MTU2.TGRB_1)
+#define MTU2TICCR (MTU2.TICCR)
+
+
+typedef struct st_mtu2
+{
+                                                           /* MTU2             */
+    volatile uint8_t   TCR_2;                                  /*  TCR_2           */
+    volatile uint8_t   TMDR_2;                                 /*  TMDR_2          */
+    volatile uint8_t   TIOR_2;                                 /*  TIOR_2          */
+    volatile uint8_t   dummy520[1];                            /*                  */
+    volatile uint8_t   TIER_2;                                 /*  TIER_2          */
+    volatile uint8_t   TSR_2;                                  /*  TSR_2           */
+    volatile uint16_t TCNT_2;                                 /*  TCNT_2          */
+    volatile uint16_t TGRA_2;                                 /*  TGRA_2          */
+    volatile uint16_t TGRB_2;                                 /*  TGRB_2          */
+    volatile uint8_t   dummy521[500];                          /*                  */
+    volatile uint8_t   TCR_3;                                  /*  TCR_3           */
+    volatile uint8_t   TCR_4;                                  /*  TCR_4           */
+    volatile uint8_t   TMDR_3;                                 /*  TMDR_3          */
+    volatile uint8_t   TMDR_4;                                 /*  TMDR_4          */
+    volatile uint8_t   TIORH_3;                                /*  TIORH_3         */
+    volatile uint8_t   TIORL_3;                                /*  TIORL_3         */
+    volatile uint8_t   TIORH_4;                                /*  TIORH_4         */
+    volatile uint8_t   TIORL_4;                                /*  TIORL_4         */
+    volatile uint8_t   TIER_3;                                 /*  TIER_3          */
+    volatile uint8_t   TIER_4;                                 /*  TIER_4          */
+    volatile uint8_t   TOER;                                   /*  TOER            */
+    volatile uint8_t   dummy522[2];                            /*                  */
+    volatile uint8_t   TGCR;                                   /*  TGCR            */
+    volatile uint8_t   TOCR1;                                  /*  TOCR1           */
+    volatile uint8_t   TOCR2;                                  /*  TOCR2           */
+    volatile uint16_t TCNT_3;                                 /*  TCNT_3          */
+    volatile uint16_t TCNT_4;                                 /*  TCNT_4          */
+    volatile uint16_t TCDR;                                   /*  TCDR            */
+    volatile uint16_t TDDR;                                   /*  TDDR            */
+    volatile uint16_t TGRA_3;                                 /*  TGRA_3          */
+    volatile uint16_t TGRB_3;                                 /*  TGRB_3          */
+    volatile uint16_t TGRA_4;                                 /*  TGRA_4          */
+    volatile uint16_t TGRB_4;                                 /*  TGRB_4          */
+    volatile uint16_t TCNTS;                                  /*  TCNTS           */
+    volatile uint16_t TCBR;                                   /*  TCBR            */
+    volatile uint16_t TGRC_3;                                 /*  TGRC_3          */
+    volatile uint16_t TGRD_3;                                 /*  TGRD_3          */
+    volatile uint16_t TGRC_4;                                 /*  TGRC_4          */
+    volatile uint16_t TGRD_4;                                 /*  TGRD_4          */
+    volatile uint8_t   TSR_3;                                  /*  TSR_3           */
+    volatile uint8_t   TSR_4;                                  /*  TSR_4           */
+    volatile uint8_t   dummy523[2];                            /*                  */
+    volatile uint8_t   TITCR;                                  /*  TITCR           */
+    volatile uint8_t   TITCNT;                                 /*  TITCNT          */
+    volatile uint8_t   TBTER;                                  /*  TBTER           */
+    volatile uint8_t   dummy524[1];                            /*                  */
+    volatile uint8_t   TDER;                                   /*  TDER            */
+    volatile uint8_t   dummy525[1];                            /*                  */
+    volatile uint8_t   TOLBR;                                  /*  TOLBR           */
+    volatile uint8_t   dummy526[1];                            /*                  */
+    volatile uint8_t   TBTM_3;                                 /*  TBTM_3          */
+    volatile uint8_t   TBTM_4;                                 /*  TBTM_4          */
+    volatile uint8_t   dummy527[6];                            /*                  */
+    volatile uint16_t TADCR;                                  /*  TADCR           */
+    volatile uint8_t   dummy528[2];                            /*                  */
+    volatile uint16_t TADCORA_4;                              /*  TADCORA_4       */
+    volatile uint16_t TADCORB_4;                              /*  TADCORB_4       */
+    volatile uint16_t TADCOBRA_4;                             /*  TADCOBRA_4      */
+    volatile uint16_t TADCOBRB_4;                             /*  TADCOBRB_4      */
+    volatile uint8_t   dummy529[20];                           /*                  */
+    volatile uint8_t   TWCR;                                   /*  TWCR            */
+    volatile uint8_t   dummy530[31];                           /*                  */
+    volatile uint8_t   TSTR;                                   /*  TSTR            */
+    volatile uint8_t   TSYR;                                   /*  TSYR            */
+    volatile uint8_t   dummy531[2];                            /*                  */
+    volatile uint8_t   TRWER;                                  /*  TRWER           */
+    volatile uint8_t   dummy532[123];                          /*                  */
+    volatile uint8_t   TCR_0;                                  /*  TCR_0           */
+    volatile uint8_t   TMDR_0;                                 /*  TMDR_0          */
+    volatile uint8_t   TIORH_0;                                /*  TIORH_0         */
+    volatile uint8_t   TIORL_0;                                /*  TIORL_0         */
+    volatile uint8_t   TIER_0;                                 /*  TIER_0          */
+    volatile uint8_t   TSR_0;                                  /*  TSR_0           */
+    volatile uint16_t TCNT_0;                                 /*  TCNT_0          */
+    volatile uint16_t TGRA_0;                                 /*  TGRA_0          */
+    volatile uint16_t TGRB_0;                                 /*  TGRB_0          */
+    volatile uint16_t TGRC_0;                                 /*  TGRC_0          */
+    volatile uint16_t TGRD_0;                                 /*  TGRD_0          */
+    volatile uint8_t   dummy533[16];                           /*                  */
+    volatile uint16_t TGRE_0;                                 /*  TGRE_0          */
+    volatile uint16_t TGRF_0;                                 /*  TGRF_0          */
+    volatile uint8_t   TIER2_0;                                /*  TIER2_0         */
+    volatile uint8_t   TSR2_0;                                 /*  TSR2_0          */
+    volatile uint8_t   TBTM_0;                                 /*  TBTM_0          */
+    volatile uint8_t   dummy534[89];                           /*                  */
+    volatile uint8_t   TCR_1;                                  /*  TCR_1           */
+    volatile uint8_t   TMDR_1;                                 /*  TMDR_1          */
+    volatile uint8_t   TIOR_1;                                 /*  TIOR_1          */
+    volatile uint8_t   dummy535[1];                            /*                  */
+    volatile uint8_t   TIER_1;                                 /*  TIER_1          */
+    volatile uint8_t   TSR_1;                                  /*  TSR_1           */
+    volatile uint16_t TCNT_1;                                 /*  TCNT_1          */
+    volatile uint16_t TGRA_1;                                 /*  TGRA_1          */
+    volatile uint16_t TGRB_1;                                 /*  TGRB_1          */
+    volatile uint8_t   dummy536[4];                            /*                  */
+    volatile uint8_t   TICCR;                                  /*  TICCR           */
+} r_io_mtu2_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h	(revision 374)
@@ -0,0 +1,97 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef OSTM_IODEFINE_H
+#define OSTM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
+#define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
+
+
+/* Start of channel array defines of OSTM */
+
+/* Channel array defines of OSTM */
+/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
+#define OSTM_COUNT  (2)
+#define OSTM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &OSTM0, &OSTM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of OSTM */
+
+
+#define OSTM0CMP (OSTM0.OSTMnCMP)
+#define OSTM0CNT (OSTM0.OSTMnCNT)
+#define OSTM0TE (OSTM0.OSTMnTE)
+#define OSTM0TS (OSTM0.OSTMnTS)
+#define OSTM0TT (OSTM0.OSTMnTT)
+#define OSTM0CTL (OSTM0.OSTMnCTL)
+#define OSTM1CMP (OSTM1.OSTMnCMP)
+#define OSTM1CNT (OSTM1.OSTMnCNT)
+#define OSTM1TE (OSTM1.OSTMnTE)
+#define OSTM1TS (OSTM1.OSTMnTS)
+#define OSTM1TT (OSTM1.OSTMnTT)
+#define OSTM1CTL (OSTM1.OSTMnCTL)
+
+
+typedef struct st_ostm
+{
+                                                           /* OSTM             */
+    volatile uint32_t  OSTMnCMP;                               /*  OSTMnCMP        */
+    volatile uint32_t  OSTMnCNT;                               /*  OSTMnCNT        */
+    volatile uint8_t   dummy1[8];                              /*                  */
+    volatile uint8_t   OSTMnTE;                                /*  OSTMnTE         */
+    volatile uint8_t   dummy2[3];                              /*                  */
+    volatile uint8_t   OSTMnTS;                                /*  OSTMnTS         */
+    volatile uint8_t   dummy3[3];                              /*                  */
+    volatile uint8_t   OSTMnTT;                                /*  OSTMnTT         */
+    volatile uint8_t   dummy4[7];                              /*                  */
+    volatile uint8_t   OSTMnCTL;                               /*  OSTMnCTL        */
+} r_io_ostm_t;
+
+
+/* Channel array defines of OSTM (2)*/
+#ifdef  DECLARE_OSTM_CHANNELS
+volatile struct st_ostm*  OSTM[ OSTM_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    OSTM_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_OSTM_CHANNELS */
+/* End of channel array defines of OSTM (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h	(revision 374)
@@ -0,0 +1,174 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pfv_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef PFV_IODEFINE_H
+#define PFV_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
+#define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
+
+
+/* Start of channel array defines of PFV */
+
+/* Channel array defines of PFV */
+/*(Sample) value = PFV[ channel ]->PFVCR; */
+#define PFV_COUNT  (2)
+#define PFV_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &PFV0, &PFV1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of PFV */
+
+
+#define PFV0PFVCR (PFV0.PFVCR)
+#define PFV0PFVICR (PFV0.PFVICR)
+#define PFV0PFVISR (PFV0.PFVISR)
+#define PFV0PFVID0 (PFV0.PFVID0)
+#define PFV0PFVID1 (PFV0.PFVID1)
+#define PFV0PFVID2 (PFV0.PFVID2)
+#define PFV0PFVID3 (PFV0.PFVID3)
+#define PFV0PFVID4 (PFV0.PFVID4)
+#define PFV0PFVID5 (PFV0.PFVID5)
+#define PFV0PFVID6 (PFV0.PFVID6)
+#define PFV0PFVID7 (PFV0.PFVID7)
+#define PFV0PFVOD0 (PFV0.PFVOD0)
+#define PFV0PFVOD1 (PFV0.PFVOD1)
+#define PFV0PFVOD2 (PFV0.PFVOD2)
+#define PFV0PFVOD3 (PFV0.PFVOD3)
+#define PFV0PFVOD4 (PFV0.PFVOD4)
+#define PFV0PFVOD5 (PFV0.PFVOD5)
+#define PFV0PFVOD6 (PFV0.PFVOD6)
+#define PFV0PFVOD7 (PFV0.PFVOD7)
+#define PFV0PFVIFSR (PFV0.PFVIFSR)
+#define PFV0PFVOFSR (PFV0.PFVOFSR)
+#define PFV0PFVACR (PFV0.PFVACR)
+#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
+#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
+#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
+#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
+#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
+#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
+#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
+#define PFV0PFVSZR (PFV0.PFVSZR)
+#define PFV1PFVCR (PFV1.PFVCR)
+#define PFV1PFVICR (PFV1.PFVICR)
+#define PFV1PFVISR (PFV1.PFVISR)
+#define PFV1PFVID0 (PFV1.PFVID0)
+#define PFV1PFVID1 (PFV1.PFVID1)
+#define PFV1PFVID2 (PFV1.PFVID2)
+#define PFV1PFVID3 (PFV1.PFVID3)
+#define PFV1PFVID4 (PFV1.PFVID4)
+#define PFV1PFVID5 (PFV1.PFVID5)
+#define PFV1PFVID6 (PFV1.PFVID6)
+#define PFV1PFVID7 (PFV1.PFVID7)
+#define PFV1PFVOD0 (PFV1.PFVOD0)
+#define PFV1PFVOD1 (PFV1.PFVOD1)
+#define PFV1PFVOD2 (PFV1.PFVOD2)
+#define PFV1PFVOD3 (PFV1.PFVOD3)
+#define PFV1PFVOD4 (PFV1.PFVOD4)
+#define PFV1PFVOD5 (PFV1.PFVOD5)
+#define PFV1PFVOD6 (PFV1.PFVOD6)
+#define PFV1PFVOD7 (PFV1.PFVOD7)
+#define PFV1PFVIFSR (PFV1.PFVIFSR)
+#define PFV1PFVOFSR (PFV1.PFVOFSR)
+#define PFV1PFVACR (PFV1.PFVACR)
+#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
+#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
+#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
+#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
+#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
+#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
+#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
+#define PFV1PFVSZR (PFV1.PFVSZR)
+
+#define PFVID_COUNT (8)
+#define PFVOD_COUNT (8)
+
+
+typedef struct st_pfv
+{
+                                                           /* PFV              */
+    volatile uint32_t  PFVCR;                                  /*  PFVCR           */
+    volatile uint32_t  PFVICR;                                 /*  PFVICR          */
+    volatile uint32_t  PFVISR;                                 /*  PFVISR          */
+    volatile uint8_t   dummy1[20];                             /*                  */
+
+/* #define PFVID_COUNT (8) */
+    volatile uint32_t  PFVID0;                                 /*  PFVID0          */
+    volatile uint32_t  PFVID1;                                 /*  PFVID1          */
+    volatile uint32_t  PFVID2;                                 /*  PFVID2          */
+    volatile uint32_t  PFVID3;                                 /*  PFVID3          */
+    volatile uint32_t  PFVID4;                                 /*  PFVID4          */
+    volatile uint32_t  PFVID5;                                 /*  PFVID5          */
+    volatile uint32_t  PFVID6;                                 /*  PFVID6          */
+    volatile uint32_t  PFVID7;                                 /*  PFVID7          */
+
+/* #define PFVOD_COUNT (8) */
+    volatile uint32_t  PFVOD0;                                 /*  PFVOD0          */
+    volatile uint32_t  PFVOD1;                                 /*  PFVOD1          */
+    volatile uint32_t  PFVOD2;                                 /*  PFVOD2          */
+    volatile uint32_t  PFVOD3;                                 /*  PFVOD3          */
+    volatile uint32_t  PFVOD4;                                 /*  PFVOD4          */
+    volatile uint32_t  PFVOD5;                                 /*  PFVOD5          */
+    volatile uint32_t  PFVOD6;                                 /*  PFVOD6          */
+    volatile uint32_t  PFVOD7;                                 /*  PFVOD7          */
+    volatile uint8_t   dummy2[4];                              /*                  */
+    volatile uint32_t  PFVIFSR;                                /*  PFVIFSR         */
+    volatile uint32_t  PFVOFSR;                                /*  PFVOFSR         */
+    volatile uint32_t  PFVACR;                                 /*  PFVACR          */
+    volatile uint32_t  PFV_MTX_MODE;                           /*  PFV_MTX_MODE    */
+    volatile uint32_t  PFV_MTX_YG_ADJ0;                        /*  PFV_MTX_YG_ADJ0 */
+    volatile uint32_t  PFV_MTX_YG_ADJ1;                        /*  PFV_MTX_YG_ADJ1 */
+    volatile uint32_t  PFV_MTX_CBB_ADJ0;                       /*  PFV_MTX_CBB_ADJ0 */
+    volatile uint32_t  PFV_MTX_CBB_ADJ1;                       /*  PFV_MTX_CBB_ADJ1 */
+    volatile uint32_t  PFV_MTX_CRR_ADJ0;                       /*  PFV_MTX_CRR_ADJ0 */
+    volatile uint32_t  PFV_MTX_CRR_ADJ1;                       /*  PFV_MTX_CRR_ADJ1 */
+    volatile uint32_t  PFVSZR;                                 /*  PFVSZR          */
+} r_io_pfv_t;
+
+
+/* Channel array defines of PFV (2)*/
+#ifdef  DECLARE_PFV_CHANNELS
+volatile struct st_pfv*  PFV[ PFV_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    PFV_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_PFV_CHANNELS */
+/* End of channel array defines of PFV (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h	(revision 374)
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pwm_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef PWM_IODEFINE_H
+#define PWM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define PWM     (*(struct st_pwm     *)0xFCFF5004uL) /* PWM */
+
+
+/* Start of channel array defines of PWM */
+
+/* Channel array defines of PWMn */
+/*(Sample) value = PWMn[ channel ]->PWCR_1; */
+#define PWMn_COUNT  (2)
+#define PWMn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &PWM1, &PWM2 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define PWM1    (*(struct st_pwm_common *)&PWM.PWCR_1)           /* PWM1 */
+#define PWM2    (*(struct st_pwm_common *)&PWM.PWCR_2)           /* PWM2 */
+
+/* End of channel array defines of PWM */
+
+
+#define PWMPWBTCR (PWM.PWBTCR)
+#define PWMPWCR_1 (PWM.PWCR_1)
+#define PWMPWPR_1 (PWM.PWPR_1)
+#define PWMPWCYR_1 (PWM.PWCYR_1)
+#define PWMPWBFR_1A (PWM.PWBFR_1A)
+#define PWMPWBFR_1C (PWM.PWBFR_1C)
+#define PWMPWBFR_1E (PWM.PWBFR_1E)
+#define PWMPWBFR_1G (PWM.PWBFR_1G)
+#define PWMPWCR_2 (PWM.PWCR_2)
+#define PWMPWPR_2 (PWM.PWPR_2)
+#define PWMPWCYR_2 (PWM.PWCYR_2)
+#define PWMPWBFR_2A (PWM.PWBFR_2A)
+#define PWMPWBFR_2C (PWM.PWBFR_2C)
+#define PWMPWBFR_2E (PWM.PWBFR_2E)
+#define PWMPWBFR_2G (PWM.PWBFR_2G)
+
+
+typedef struct st_pwm
+{
+                                                           /* PWM              */
+    volatile uint8_t   dummy559[2];                            /*                  */
+    volatile uint8_t   PWBTCR;                                 /*  PWBTCR          */
+    volatile uint8_t   dummy560[217];                          /*                  */
+
+/* start of struct st_pwm_common */
+    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
+    volatile uint8_t   dummy561[3];                            /*                  */
+    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
+    volatile uint8_t   dummy562[1];                            /*                  */
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+
+/* end of struct st_pwm_common */
+
+/* start of struct st_pwm_common */
+    volatile uint8_t   PWCR_2;                                 /*  PWCR_2          */
+    volatile uint8_t   dummy563[3];                            /*                  */
+    volatile uint8_t   PWPR_2;                                 /*  PWPR_2          */
+    volatile uint8_t   dummy564[1];                            /*                  */
+    volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
+    volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
+    volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
+    volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
+    volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
+
+/* end of struct st_pwm_common */
+} r_io_pwm_t;
+
+
+typedef struct st_pwm_common
+{
+ 
+    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
+    volatile uint8_t   dummy562[3];                            /*                  */
+    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
+    volatile uint8_t   dummy563[1];                            /*                  */
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+} r_io_pwm_common_t;
+
+
+/* Channel array defines of PWMn (2)*/
+#ifdef  DECLARE_PWMn_CHANNELS
+volatile struct st_pwm_common*  PWMn[ PWMn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    PWMn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_PWMn_CHANNELS */
+/* End of channel array defines of PWMn (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h	(revision 374)
@@ -0,0 +1,584 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : riic_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef RIIC_IODEFINE_H
+#define RIIC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define RIIC0   (*(struct st_riic    *)0xFCFEE000uL) /* RIIC0 */
+#define RIIC1   (*(struct st_riic    *)0xFCFEE400uL) /* RIIC1 */
+#define RIIC2   (*(struct st_riic    *)0xFCFEE800uL) /* RIIC2 */
+#define RIIC3   (*(struct st_riic    *)0xFCFEEC00uL) /* RIIC3 */
+
+
+/* Start of channel array defines of RIIC */
+
+/* Channel array defines of RIIC */
+/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
+#define RIIC_COUNT  (4)
+#define RIIC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RIIC0, &RIIC1, &RIIC2, &RIIC3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of RIIC */
+
+
+#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32)
+#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L])
+#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H])
+#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32)
+#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L])
+#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H])
+#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32)
+#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L])
+#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H])
+#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32)
+#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L])
+#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H])
+#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32)
+#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L])
+#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H])
+#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC0FER (RIIC0.RIICnFER.UINT32)
+#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L])
+#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL])
+#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH])
+#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H])
+#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL])
+#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH])
+#define RIIC0SER (RIIC0.RIICnSER.UINT32)
+#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L])
+#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL])
+#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH])
+#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H])
+#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL])
+#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH])
+#define RIIC0IER (RIIC0.RIICnIER.UINT32)
+#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L])
+#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL])
+#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH])
+#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H])
+#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL])
+#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH])
+#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32)
+#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L])
+#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H])
+#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32)
+#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L])
+#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H])
+#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32)
+#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32)
+#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32)
+#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC0BRL (RIIC0.RIICnBRL.UINT32)
+#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L])
+#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H])
+#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC0BRH (RIIC0.RIICnBRH.UINT32)
+#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L])
+#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H])
+#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC0DRT (RIIC0.RIICnDRT.UINT32)
+#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L])
+#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H])
+#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC0DRR (RIIC0.RIICnDRR.UINT32)
+#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L])
+#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H])
+#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32)
+#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L])
+#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H])
+#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32)
+#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L])
+#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H])
+#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32)
+#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L])
+#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H])
+#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32)
+#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L])
+#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H])
+#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32)
+#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L])
+#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H])
+#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC1FER (RIIC1.RIICnFER.UINT32)
+#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L])
+#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL])
+#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH])
+#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H])
+#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL])
+#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH])
+#define RIIC1SER (RIIC1.RIICnSER.UINT32)
+#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L])
+#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL])
+#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH])
+#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H])
+#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL])
+#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH])
+#define RIIC1IER (RIIC1.RIICnIER.UINT32)
+#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L])
+#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL])
+#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH])
+#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H])
+#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL])
+#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH])
+#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32)
+#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L])
+#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H])
+#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32)
+#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L])
+#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H])
+#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32)
+#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32)
+#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32)
+#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC1BRL (RIIC1.RIICnBRL.UINT32)
+#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L])
+#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H])
+#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC1BRH (RIIC1.RIICnBRH.UINT32)
+#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L])
+#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H])
+#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC1DRT (RIIC1.RIICnDRT.UINT32)
+#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L])
+#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H])
+#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC1DRR (RIIC1.RIICnDRR.UINT32)
+#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L])
+#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H])
+#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32)
+#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L])
+#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H])
+#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32)
+#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L])
+#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H])
+#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32)
+#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L])
+#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H])
+#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32)
+#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L])
+#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H])
+#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32)
+#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L])
+#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H])
+#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC2FER (RIIC2.RIICnFER.UINT32)
+#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L])
+#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL])
+#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH])
+#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H])
+#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL])
+#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH])
+#define RIIC2SER (RIIC2.RIICnSER.UINT32)
+#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L])
+#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL])
+#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH])
+#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H])
+#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL])
+#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH])
+#define RIIC2IER (RIIC2.RIICnIER.UINT32)
+#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L])
+#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL])
+#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH])
+#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H])
+#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL])
+#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH])
+#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32)
+#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L])
+#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H])
+#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32)
+#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L])
+#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H])
+#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32)
+#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32)
+#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32)
+#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC2BRL (RIIC2.RIICnBRL.UINT32)
+#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L])
+#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H])
+#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC2BRH (RIIC2.RIICnBRH.UINT32)
+#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L])
+#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H])
+#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC2DRT (RIIC2.RIICnDRT.UINT32)
+#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L])
+#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H])
+#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC2DRR (RIIC2.RIICnDRR.UINT32)
+#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L])
+#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H])
+#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32)
+#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L])
+#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H])
+#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32)
+#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L])
+#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H])
+#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32)
+#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L])
+#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H])
+#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32)
+#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L])
+#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H])
+#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32)
+#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L])
+#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H])
+#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC3FER (RIIC3.RIICnFER.UINT32)
+#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L])
+#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL])
+#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH])
+#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H])
+#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL])
+#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH])
+#define RIIC3SER (RIIC3.RIICnSER.UINT32)
+#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L])
+#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL])
+#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH])
+#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H])
+#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL])
+#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH])
+#define RIIC3IER (RIIC3.RIICnIER.UINT32)
+#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L])
+#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL])
+#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH])
+#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H])
+#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL])
+#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH])
+#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32)
+#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L])
+#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H])
+#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32)
+#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L])
+#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H])
+#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32)
+#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32)
+#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32)
+#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC3BRL (RIIC3.RIICnBRL.UINT32)
+#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L])
+#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H])
+#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC3BRH (RIIC3.RIICnBRH.UINT32)
+#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L])
+#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H])
+#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC3DRT (RIIC3.RIICnDRT.UINT32)
+#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L])
+#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H])
+#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC3DRR (RIIC3.RIICnDRR.UINT32)
+#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L])
+#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H])
+#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH])
+
+#define RIICnCRm_COUNT (2)
+#define RIICnMRm_COUNT (3)
+#define RIICnSRm_COUNT (2)
+#define RIICnSARm_COUNT (3)
+
+
+typedef struct st_riic
+{
+                                                           /* RIIC             */
+
+/* #define RIICnCRm_COUNT (2) */
+    union iodefine_reg32_t  RIICnCR1;                      /*  RIICnCR1        */
+    union iodefine_reg32_t  RIICnCR2;                      /*  RIICnCR2        */
+
+/* #define RIICnMRm_COUNT (3) */
+    union iodefine_reg32_t  RIICnMR1;                      /*  RIICnMR1        */
+    union iodefine_reg32_t  RIICnMR2;                      /*  RIICnMR2        */
+    union iodefine_reg32_t  RIICnMR3;                      /*  RIICnMR3        */
+    union iodefine_reg32_t  RIICnFER;                      /*  RIICnFER        */
+    union iodefine_reg32_t  RIICnSER;                      /*  RIICnSER        */
+    union iodefine_reg32_t  RIICnIER;                      /*  RIICnIER        */
+
+/* #define RIICnSRm_COUNT (2) */
+    union iodefine_reg32_t  RIICnSR1;                      /*  RIICnSR1        */
+    union iodefine_reg32_t  RIICnSR2;                      /*  RIICnSR2        */
+
+/* #define RIICnSARm_COUNT (3) */
+    union iodefine_reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
+    union iodefine_reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
+    union iodefine_reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
+    union iodefine_reg32_t  RIICnBRL;                      /*  RIICnBRL        */
+    union iodefine_reg32_t  RIICnBRH;                      /*  RIICnBRH        */
+    union iodefine_reg32_t  RIICnDRT;                      /*  RIICnDRT        */
+    union iodefine_reg32_t  RIICnDRR;                      /*  RIICnDRR        */
+    
+} r_io_riic_t;
+
+
+/* Channel array defines of RIIC (2)*/
+#ifdef  DECLARE_RIIC_CHANNELS
+volatile struct st_riic*  RIIC[ RIIC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RIIC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RIIC_CHANNELS */
+/* End of channel array defines of RIIC (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h	(revision 374)
@@ -0,0 +1,194 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : romdec_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef ROMDEC_IODEFINE_H
+#define ROMDEC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
+
+
+#define ROMDECCROMEN (ROMDEC.CROMEN)
+#define ROMDECCROMSY0 (ROMDEC.CROMSY0)
+#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0)
+#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1)
+#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3)
+#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4)
+#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5)
+#define ROMDECCROMST0 (ROMDEC.CROMST0)
+#define ROMDECCROMST1 (ROMDEC.CROMST1)
+#define ROMDECCROMST3 (ROMDEC.CROMST3)
+#define ROMDECCROMST4 (ROMDEC.CROMST4)
+#define ROMDECCROMST5 (ROMDEC.CROMST5)
+#define ROMDECCROMST6 (ROMDEC.CROMST6)
+#define ROMDECCBUFST0 (ROMDEC.CBUFST0)
+#define ROMDECCBUFST1 (ROMDEC.CBUFST1)
+#define ROMDECCBUFST2 (ROMDEC.CBUFST2)
+#define ROMDECHEAD00 (ROMDEC.HEAD00)
+#define ROMDECHEAD01 (ROMDEC.HEAD01)
+#define ROMDECHEAD02 (ROMDEC.HEAD02)
+#define ROMDECHEAD03 (ROMDEC.HEAD03)
+#define ROMDECSHEAD00 (ROMDEC.SHEAD00)
+#define ROMDECSHEAD01 (ROMDEC.SHEAD01)
+#define ROMDECSHEAD02 (ROMDEC.SHEAD02)
+#define ROMDECSHEAD03 (ROMDEC.SHEAD03)
+#define ROMDECSHEAD04 (ROMDEC.SHEAD04)
+#define ROMDECSHEAD05 (ROMDEC.SHEAD05)
+#define ROMDECSHEAD06 (ROMDEC.SHEAD06)
+#define ROMDECSHEAD07 (ROMDEC.SHEAD07)
+#define ROMDECHEAD20 (ROMDEC.HEAD20)
+#define ROMDECHEAD21 (ROMDEC.HEAD21)
+#define ROMDECHEAD22 (ROMDEC.HEAD22)
+#define ROMDECHEAD23 (ROMDEC.HEAD23)
+#define ROMDECSHEAD20 (ROMDEC.SHEAD20)
+#define ROMDECSHEAD21 (ROMDEC.SHEAD21)
+#define ROMDECSHEAD22 (ROMDEC.SHEAD22)
+#define ROMDECSHEAD23 (ROMDEC.SHEAD23)
+#define ROMDECSHEAD24 (ROMDEC.SHEAD24)
+#define ROMDECSHEAD25 (ROMDEC.SHEAD25)
+#define ROMDECSHEAD26 (ROMDEC.SHEAD26)
+#define ROMDECSHEAD27 (ROMDEC.SHEAD27)
+#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0)
+#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1)
+#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2)
+#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3)
+#define ROMDECCROMST0M (ROMDEC.CROMST0M)
+#define ROMDECROMDECRST (ROMDEC.ROMDECRST)
+#define ROMDECRSTSTAT (ROMDEC.RSTSTAT)
+#define ROMDECSSI (ROMDEC.SSI)
+#define ROMDECINTHOLD (ROMDEC.INTHOLD)
+#define ROMDECINHINT (ROMDEC.INHINT)
+#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0)
+#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2)
+#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0)
+
+#define ROMDEC_CROMCTL0_COUNT (2)
+#define ROMDEC_CROMST0_COUNT (2)
+#define ROMDEC_CBUFST0_COUNT (3)
+#define ROMDEC_HEAD00_COUNT (4)
+#define ROMDEC_SHEAD00_COUNT (8)
+#define ROMDEC_HEAD20_COUNT (4)
+#define ROMDEC_SHEAD20_COUNT (8)
+#define ROMDEC_CBUFCTL0_COUNT (4)
+#define ROMDEC_STRMDIN0_COUNT (2)
+
+
+typedef struct st_romdec
+{
+                                                           /* ROMDEC           */
+    volatile uint8_t   CROMEN;                                 /*  CROMEN          */
+    volatile uint8_t   CROMSY0;                                /*  CROMSY0         */
+
+/* #define ROMDEC_CROMCTL0_COUNT (2) */
+    volatile uint8_t   CROMCTL0;                               /*  CROMCTL0        */
+    volatile uint8_t   CROMCTL1;                               /*  CROMCTL1        */
+    volatile uint8_t   dummy23[1];                             /*                  */
+    volatile uint8_t   CROMCTL3;                               /*  CROMCTL3        */
+    volatile uint8_t   CROMCTL4;                               /*  CROMCTL4        */
+    volatile uint8_t   CROMCTL5;                               /*  CROMCTL5        */
+
+/* #define ROMDEC_CROMST0_COUNT (2) */
+    volatile uint8_t   CROMST0;                                /*  CROMST0         */
+    volatile uint8_t   CROMST1;                                /*  CROMST1         */
+    volatile uint8_t   dummy24[1];                             /*                  */
+    volatile uint8_t   CROMST3;                                /*  CROMST3         */
+    volatile uint8_t   CROMST4;                                /*  CROMST4         */
+    volatile uint8_t   CROMST5;                                /*  CROMST5         */
+    volatile uint8_t   CROMST6;                                /*  CROMST6         */
+    volatile uint8_t   dummy25[5];                             /*                  */
+
+/* #define ROMDEC_CBUFST0_COUNT (3) */
+    volatile uint8_t   CBUFST0;                                /*  CBUFST0         */
+    volatile uint8_t   CBUFST1;                                /*  CBUFST1         */
+    volatile uint8_t   CBUFST2;                                /*  CBUFST2         */
+    volatile uint8_t   dummy26[1];                             /*                  */
+
+/* #define ROMDEC_HEAD00_COUNT (4) */
+    volatile uint8_t   HEAD00;                                 /*  HEAD00          */
+    volatile uint8_t   HEAD01;                                 /*  HEAD01          */
+    volatile uint8_t   HEAD02;                                 /*  HEAD02          */
+    volatile uint8_t   HEAD03;                                 /*  HEAD03          */
+
+/* #define ROMDEC_SHEAD00_COUNT (8) */
+    volatile uint8_t   SHEAD00;                                /*  SHEAD00         */
+    volatile uint8_t   SHEAD01;                                /*  SHEAD01         */
+    volatile uint8_t   SHEAD02;                                /*  SHEAD02         */
+    volatile uint8_t   SHEAD03;                                /*  SHEAD03         */
+    volatile uint8_t   SHEAD04;                                /*  SHEAD04         */
+    volatile uint8_t   SHEAD05;                                /*  SHEAD05         */
+    volatile uint8_t   SHEAD06;                                /*  SHEAD06         */
+    volatile uint8_t   SHEAD07;                                /*  SHEAD07         */
+
+/* #define ROMDEC_HEAD20_COUNT (4) */
+    volatile uint8_t   HEAD20;                                 /*  HEAD20          */
+    volatile uint8_t   HEAD21;                                 /*  HEAD21          */
+    volatile uint8_t   HEAD22;                                 /*  HEAD22          */
+    volatile uint8_t   HEAD23;                                 /*  HEAD23          */
+
+/* #define ROMDEC_SHEAD20_COUNT (8) */
+    volatile uint8_t   SHEAD20;                                /*  SHEAD20         */
+    volatile uint8_t   SHEAD21;                                /*  SHEAD21         */
+    volatile uint8_t   SHEAD22;                                /*  SHEAD22         */
+    volatile uint8_t   SHEAD23;                                /*  SHEAD23         */
+    volatile uint8_t   SHEAD24;                                /*  SHEAD24         */
+    volatile uint8_t   SHEAD25;                                /*  SHEAD25         */
+    volatile uint8_t   SHEAD26;                                /*  SHEAD26         */
+    volatile uint8_t   SHEAD27;                                /*  SHEAD27         */
+    volatile uint8_t   dummy27[16];                            /*                  */
+
+/* #define ROMDEC_CBUFCTL0_COUNT (4) */
+    volatile uint8_t   CBUFCTL0;                               /*  CBUFCTL0        */
+    volatile uint8_t   CBUFCTL1;                               /*  CBUFCTL1        */
+    volatile uint8_t   CBUFCTL2;                               /*  CBUFCTL2        */
+    volatile uint8_t   CBUFCTL3;                               /*  CBUFCTL3        */
+    volatile uint8_t   dummy28[1];                             /*                  */
+    volatile uint8_t   CROMST0M;                               /*  CROMST0M        */
+    volatile uint8_t   dummy29[186];                           /*                  */
+    volatile uint8_t   ROMDECRST;                              /*  ROMDECRST       */
+    volatile uint8_t   RSTSTAT;                                /*  RSTSTAT         */
+    volatile uint8_t   SSI;                                    /*  SSI             */
+    volatile uint8_t   dummy30[5];                             /*                  */
+    volatile uint8_t   INTHOLD;                                /*  INTHOLD         */
+    volatile uint8_t   INHINT;                                 /*  INHINT          */
+    volatile uint8_t   dummy31[246];                           /*                  */
+
+/* #define ROMDEC_STRMDIN0_COUNT (2) */
+    volatile uint16_t STRMDIN0;                               /*  STRMDIN0        */
+    volatile uint16_t STRMDIN2;                               /*  STRMDIN2        */
+    volatile uint16_t STRMDOUT0;                              /*  STRMDOUT0       */
+} r_io_romdec_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h	(revision 374)
@@ -0,0 +1,9346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rscan0_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef RSCAN0_IODEFINE_H
+#define RSCAN0_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define RSCAN0  (*(struct st_rscan0  *)0xE803A000uL) /* RSCAN0 */
+
+
+/* Start of channel array defines of RSCAN0 */
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0_CFIDm_COUNT  (15)
+#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \
+    &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */
+#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */
+#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */
+#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */
+#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */
+#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */
+#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */
+#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */
+#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */
+#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */
+#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */
+#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */
+#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */
+#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */
+#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */
+
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0_TMIDp_COUNT  (80)
+#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \
+    &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \
+    &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \
+    &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \
+    &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \
+    &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \
+    &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \
+    &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \
+    &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \
+    &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */
+#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */
+#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */
+#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */
+#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */
+#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */
+#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */
+#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */
+#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */
+#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */
+#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */
+#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */
+#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */
+#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */
+#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */
+#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */
+#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */
+#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */
+#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */
+#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */
+#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */
+#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */
+#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */
+#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */
+#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */
+#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */
+#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */
+#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */
+#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */
+#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */
+#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */
+#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */
+#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */
+#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */
+#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */
+#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */
+#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */
+#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */
+#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */
+#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */
+#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */
+#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */
+#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */
+#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */
+#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */
+#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */
+#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */
+#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */
+#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */
+#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */
+#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */
+#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */
+#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */
+#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */
+#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */
+#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */
+#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */
+#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */
+#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */
+#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */
+#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */
+#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */
+#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */
+#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */
+#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */
+#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */
+#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */
+#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */
+#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */
+#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */
+#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */
+#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */
+#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */
+#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */
+#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */
+#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */
+#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */
+#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */
+#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */
+#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */
+
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0_RFIDm_COUNT  (8)
+#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */
+#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */
+#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */
+#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */
+#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */
+#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */
+#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */
+#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */
+
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0_RMIDp_COUNT  (80)
+#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \
+    &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \
+    &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \
+    &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \
+    &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \
+    &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \
+    &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \
+    &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \
+    &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \
+    &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */
+#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */
+#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */
+#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */
+#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */
+#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */
+#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */
+#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */
+#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */
+#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */
+#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */
+#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */
+#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */
+#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */
+#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */
+#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */
+#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */
+#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */
+#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */
+#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */
+#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */
+#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */
+#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */
+#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */
+#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */
+#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */
+#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */
+#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */
+#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */
+#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */
+#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */
+#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */
+#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */
+#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */
+#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */
+#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */
+#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */
+#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */
+#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */
+#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */
+#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */
+#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */
+#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */
+#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */
+#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */
+#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */
+#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */
+#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */
+#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */
+#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */
+#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */
+#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */
+#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */
+#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */
+#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */
+#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */
+#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */
+#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */
+#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */
+#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */
+#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */
+#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */
+#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */
+#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */
+#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */
+#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */
+#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */
+#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */
+#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */
+#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */
+#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */
+#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */
+#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */
+#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */
+#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */
+#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */
+#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */
+#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */
+#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */
+#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */
+
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */
+/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */
+#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT  (16)
+#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \
+    &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */
+#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */
+#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */
+#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */
+#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */
+#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */
+#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */
+#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */
+#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */
+#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */
+#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */
+#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */
+#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */
+#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */
+#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */
+#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */
+
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */
+/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */
+#define RSCAN_FROM_RSCAN0_CnCFG_COUNT  (5)
+#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */
+#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */
+#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */
+#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */
+#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */
+
+/* End of channel array defines of RSCAN0 */
+
+
+#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32)
+#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L])
+#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL])
+#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH])
+#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H])
+#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL])
+#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH])
+#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32)
+#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L])
+#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL])
+#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH])
+#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H])
+#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL])
+#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH])
+#define RSCAN0C0STS (RSCAN0.C0STS.UINT32)
+#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L])
+#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL])
+#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH])
+#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H])
+#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL])
+#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH])
+#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32)
+#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L])
+#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL])
+#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH])
+#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H])
+#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL])
+#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH])
+#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32)
+#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L])
+#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL])
+#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH])
+#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H])
+#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL])
+#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH])
+#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32)
+#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L])
+#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL])
+#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH])
+#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H])
+#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL])
+#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH])
+#define RSCAN0C1STS (RSCAN0.C1STS.UINT32)
+#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L])
+#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL])
+#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH])
+#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H])
+#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL])
+#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH])
+#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32)
+#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L])
+#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL])
+#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH])
+#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H])
+#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL])
+#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH])
+#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32)
+#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L])
+#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL])
+#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH])
+#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H])
+#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL])
+#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH])
+#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32)
+#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L])
+#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL])
+#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH])
+#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H])
+#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL])
+#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH])
+#define RSCAN0C2STS (RSCAN0.C2STS.UINT32)
+#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L])
+#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL])
+#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH])
+#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H])
+#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL])
+#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH])
+#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32)
+#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L])
+#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL])
+#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH])
+#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H])
+#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL])
+#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH])
+#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32)
+#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L])
+#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL])
+#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH])
+#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H])
+#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL])
+#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH])
+#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32)
+#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L])
+#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL])
+#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH])
+#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H])
+#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL])
+#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH])
+#define RSCAN0C3STS (RSCAN0.C3STS.UINT32)
+#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L])
+#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL])
+#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH])
+#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H])
+#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL])
+#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH])
+#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32)
+#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L])
+#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL])
+#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH])
+#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H])
+#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL])
+#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH])
+#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32)
+#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L])
+#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL])
+#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH])
+#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H])
+#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL])
+#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH])
+#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32)
+#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L])
+#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL])
+#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH])
+#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H])
+#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL])
+#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH])
+#define RSCAN0C4STS (RSCAN0.C4STS.UINT32)
+#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L])
+#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL])
+#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH])
+#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H])
+#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL])
+#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH])
+#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32)
+#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L])
+#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL])
+#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH])
+#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H])
+#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL])
+#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH])
+#define RSCAN0GCFG (RSCAN0.GCFG.UINT32)
+#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L])
+#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL])
+#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH])
+#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H])
+#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL])
+#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH])
+#define RSCAN0GCTR (RSCAN0.GCTR.UINT32)
+#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L])
+#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL])
+#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH])
+#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H])
+#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL])
+#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH])
+#define RSCAN0GSTS (RSCAN0.GSTS.UINT32)
+#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L])
+#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL])
+#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH])
+#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H])
+#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL])
+#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH])
+#define RSCAN0GERFL (RSCAN0.GERFL.UINT32)
+#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L])
+#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL])
+#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH])
+#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H])
+#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL])
+#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH])
+#define RSCAN0GTSC (RSCAN0.GTSC.UINT32)
+#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L])
+#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H])
+#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32)
+#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L])
+#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL])
+#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH])
+#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H])
+#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL])
+#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH])
+#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32)
+#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L])
+#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL])
+#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH])
+#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H])
+#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL])
+#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH])
+#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32)
+#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L])
+#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL])
+#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH])
+#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H])
+#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL])
+#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH])
+#define RSCAN0RMNB (RSCAN0.RMNB.UINT32)
+#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L])
+#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL])
+#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH])
+#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H])
+#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL])
+#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH])
+#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32)
+#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L])
+#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL])
+#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH])
+#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H])
+#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL])
+#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH])
+#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32)
+#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L])
+#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL])
+#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH])
+#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H])
+#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL])
+#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH])
+#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32)
+#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L])
+#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL])
+#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH])
+#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H])
+#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL])
+#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH])
+#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32)
+#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L])
+#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL])
+#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH])
+#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H])
+#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL])
+#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH])
+#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32)
+#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L])
+#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL])
+#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH])
+#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H])
+#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL])
+#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH])
+#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32)
+#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L])
+#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL])
+#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH])
+#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H])
+#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL])
+#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH])
+#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32)
+#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L])
+#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL])
+#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH])
+#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H])
+#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL])
+#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH])
+#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32)
+#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L])
+#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL])
+#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH])
+#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H])
+#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL])
+#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH])
+#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32)
+#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L])
+#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL])
+#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH])
+#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H])
+#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL])
+#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH])
+#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32)
+#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L])
+#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL])
+#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH])
+#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H])
+#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL])
+#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH])
+#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32)
+#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L])
+#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL])
+#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH])
+#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H])
+#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL])
+#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH])
+#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32)
+#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L])
+#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL])
+#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH])
+#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H])
+#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL])
+#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH])
+#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32)
+#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L])
+#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL])
+#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH])
+#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H])
+#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL])
+#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH])
+#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32)
+#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L])
+#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL])
+#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH])
+#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H])
+#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL])
+#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH])
+#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32)
+#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L])
+#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL])
+#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH])
+#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H])
+#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL])
+#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH])
+#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32)
+#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L])
+#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL])
+#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH])
+#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H])
+#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL])
+#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH])
+#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32)
+#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L])
+#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL])
+#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH])
+#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H])
+#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL])
+#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH])
+#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32)
+#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L])
+#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL])
+#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH])
+#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H])
+#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL])
+#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH])
+#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32)
+#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L])
+#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL])
+#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH])
+#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H])
+#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL])
+#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32)
+#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L])
+#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H])
+#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32)
+#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L])
+#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H])
+#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32)
+#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L])
+#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H])
+#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32)
+#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L])
+#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H])
+#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32)
+#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L])
+#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H])
+#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32)
+#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L])
+#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H])
+#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32)
+#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L])
+#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H])
+#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32)
+#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L])
+#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H])
+#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH])
+#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32)
+#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L])
+#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL])
+#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH])
+#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H])
+#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL])
+#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH])
+#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32)
+#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L])
+#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL])
+#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH])
+#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H])
+#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL])
+#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH])
+#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32)
+#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L])
+#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL])
+#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH])
+#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H])
+#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL])
+#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH])
+#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32)
+#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L])
+#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL])
+#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH])
+#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H])
+#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL])
+#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH])
+#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32)
+#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L])
+#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL])
+#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH])
+#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H])
+#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL])
+#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH])
+#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32)
+#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L])
+#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL])
+#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH])
+#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H])
+#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL])
+#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH])
+#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32)
+#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L])
+#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL])
+#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH])
+#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H])
+#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL])
+#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH])
+#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32)
+#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L])
+#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL])
+#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH])
+#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H])
+#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL])
+#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH])
+#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32)
+#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L])
+#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL])
+#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH])
+#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H])
+#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL])
+#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH])
+#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32)
+#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L])
+#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL])
+#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH])
+#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H])
+#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL])
+#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH])
+#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32)
+#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L])
+#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL])
+#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH])
+#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H])
+#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL])
+#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH])
+#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32)
+#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L])
+#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL])
+#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH])
+#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H])
+#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL])
+#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH])
+#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32)
+#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L])
+#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL])
+#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH])
+#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H])
+#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL])
+#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH])
+#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32)
+#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L])
+#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL])
+#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH])
+#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H])
+#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL])
+#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH])
+#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32)
+#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L])
+#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL])
+#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH])
+#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H])
+#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL])
+#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH])
+#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32)
+#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L])
+#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL])
+#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH])
+#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H])
+#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL])
+#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH])
+#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32)
+#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L])
+#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL])
+#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH])
+#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H])
+#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL])
+#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH])
+#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32)
+#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L])
+#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL])
+#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH])
+#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H])
+#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL])
+#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH])
+#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32)
+#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L])
+#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL])
+#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH])
+#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H])
+#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL])
+#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH])
+#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32)
+#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L])
+#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL])
+#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH])
+#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H])
+#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL])
+#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH])
+#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32)
+#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L])
+#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL])
+#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH])
+#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H])
+#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL])
+#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH])
+#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32)
+#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L])
+#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL])
+#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH])
+#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H])
+#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL])
+#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH])
+#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32)
+#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L])
+#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL])
+#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH])
+#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H])
+#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL])
+#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH])
+#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32)
+#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L])
+#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL])
+#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH])
+#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H])
+#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL])
+#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH])
+#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32)
+#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L])
+#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL])
+#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH])
+#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H])
+#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL])
+#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH])
+#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32)
+#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L])
+#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL])
+#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH])
+#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H])
+#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL])
+#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH])
+#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32)
+#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L])
+#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL])
+#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH])
+#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H])
+#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL])
+#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH])
+#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32)
+#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L])
+#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL])
+#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH])
+#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H])
+#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL])
+#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH])
+#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32)
+#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L])
+#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL])
+#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH])
+#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H])
+#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL])
+#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH])
+#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32)
+#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L])
+#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL])
+#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH])
+#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H])
+#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL])
+#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32)
+#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L])
+#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H])
+#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32)
+#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L])
+#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H])
+#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32)
+#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L])
+#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H])
+#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32)
+#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L])
+#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H])
+#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32)
+#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L])
+#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H])
+#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32)
+#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L])
+#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H])
+#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32)
+#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L])
+#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H])
+#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32)
+#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L])
+#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H])
+#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32)
+#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L])
+#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H])
+#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32)
+#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L])
+#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H])
+#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32)
+#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L])
+#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H])
+#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32)
+#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L])
+#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H])
+#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32)
+#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L])
+#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H])
+#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32)
+#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L])
+#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H])
+#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32)
+#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L])
+#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H])
+#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH])
+#define RSCAN0FESTS (RSCAN0.FESTS.UINT32)
+#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L])
+#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL])
+#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH])
+#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H])
+#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL])
+#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH])
+#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32)
+#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L])
+#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL])
+#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH])
+#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H])
+#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL])
+#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH])
+#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32)
+#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L])
+#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL])
+#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH])
+#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H])
+#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL])
+#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH])
+#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32)
+#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L])
+#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL])
+#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH])
+#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H])
+#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL])
+#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH])
+#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32)
+#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L])
+#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL])
+#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH])
+#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H])
+#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL])
+#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH])
+#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32)
+#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L])
+#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL])
+#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH])
+#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H])
+#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL])
+#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH])
+#define RSCAN0TMC0 (RSCAN0.TMC0)
+#define RSCAN0TMC1 (RSCAN0.TMC1)
+#define RSCAN0TMC2 (RSCAN0.TMC2)
+#define RSCAN0TMC3 (RSCAN0.TMC3)
+#define RSCAN0TMC4 (RSCAN0.TMC4)
+#define RSCAN0TMC5 (RSCAN0.TMC5)
+#define RSCAN0TMC6 (RSCAN0.TMC6)
+#define RSCAN0TMC7 (RSCAN0.TMC7)
+#define RSCAN0TMC8 (RSCAN0.TMC8)
+#define RSCAN0TMC9 (RSCAN0.TMC9)
+#define RSCAN0TMC10 (RSCAN0.TMC10)
+#define RSCAN0TMC11 (RSCAN0.TMC11)
+#define RSCAN0TMC12 (RSCAN0.TMC12)
+#define RSCAN0TMC13 (RSCAN0.TMC13)
+#define RSCAN0TMC14 (RSCAN0.TMC14)
+#define RSCAN0TMC15 (RSCAN0.TMC15)
+#define RSCAN0TMC16 (RSCAN0.TMC16)
+#define RSCAN0TMC17 (RSCAN0.TMC17)
+#define RSCAN0TMC18 (RSCAN0.TMC18)
+#define RSCAN0TMC19 (RSCAN0.TMC19)
+#define RSCAN0TMC20 (RSCAN0.TMC20)
+#define RSCAN0TMC21 (RSCAN0.TMC21)
+#define RSCAN0TMC22 (RSCAN0.TMC22)
+#define RSCAN0TMC23 (RSCAN0.TMC23)
+#define RSCAN0TMC24 (RSCAN0.TMC24)
+#define RSCAN0TMC25 (RSCAN0.TMC25)
+#define RSCAN0TMC26 (RSCAN0.TMC26)
+#define RSCAN0TMC27 (RSCAN0.TMC27)
+#define RSCAN0TMC28 (RSCAN0.TMC28)
+#define RSCAN0TMC29 (RSCAN0.TMC29)
+#define RSCAN0TMC30 (RSCAN0.TMC30)
+#define RSCAN0TMC31 (RSCAN0.TMC31)
+#define RSCAN0TMC32 (RSCAN0.TMC32)
+#define RSCAN0TMC33 (RSCAN0.TMC33)
+#define RSCAN0TMC34 (RSCAN0.TMC34)
+#define RSCAN0TMC35 (RSCAN0.TMC35)
+#define RSCAN0TMC36 (RSCAN0.TMC36)
+#define RSCAN0TMC37 (RSCAN0.TMC37)
+#define RSCAN0TMC38 (RSCAN0.TMC38)
+#define RSCAN0TMC39 (RSCAN0.TMC39)
+#define RSCAN0TMC40 (RSCAN0.TMC40)
+#define RSCAN0TMC41 (RSCAN0.TMC41)
+#define RSCAN0TMC42 (RSCAN0.TMC42)
+#define RSCAN0TMC43 (RSCAN0.TMC43)
+#define RSCAN0TMC44 (RSCAN0.TMC44)
+#define RSCAN0TMC45 (RSCAN0.TMC45)
+#define RSCAN0TMC46 (RSCAN0.TMC46)
+#define RSCAN0TMC47 (RSCAN0.TMC47)
+#define RSCAN0TMC48 (RSCAN0.TMC48)
+#define RSCAN0TMC49 (RSCAN0.TMC49)
+#define RSCAN0TMC50 (RSCAN0.TMC50)
+#define RSCAN0TMC51 (RSCAN0.TMC51)
+#define RSCAN0TMC52 (RSCAN0.TMC52)
+#define RSCAN0TMC53 (RSCAN0.TMC53)
+#define RSCAN0TMC54 (RSCAN0.TMC54)
+#define RSCAN0TMC55 (RSCAN0.TMC55)
+#define RSCAN0TMC56 (RSCAN0.TMC56)
+#define RSCAN0TMC57 (RSCAN0.TMC57)
+#define RSCAN0TMC58 (RSCAN0.TMC58)
+#define RSCAN0TMC59 (RSCAN0.TMC59)
+#define RSCAN0TMC60 (RSCAN0.TMC60)
+#define RSCAN0TMC61 (RSCAN0.TMC61)
+#define RSCAN0TMC62 (RSCAN0.TMC62)
+#define RSCAN0TMC63 (RSCAN0.TMC63)
+#define RSCAN0TMC64 (RSCAN0.TMC64)
+#define RSCAN0TMC65 (RSCAN0.TMC65)
+#define RSCAN0TMC66 (RSCAN0.TMC66)
+#define RSCAN0TMC67 (RSCAN0.TMC67)
+#define RSCAN0TMC68 (RSCAN0.TMC68)
+#define RSCAN0TMC69 (RSCAN0.TMC69)
+#define RSCAN0TMC70 (RSCAN0.TMC70)
+#define RSCAN0TMC71 (RSCAN0.TMC71)
+#define RSCAN0TMC72 (RSCAN0.TMC72)
+#define RSCAN0TMC73 (RSCAN0.TMC73)
+#define RSCAN0TMC74 (RSCAN0.TMC74)
+#define RSCAN0TMC75 (RSCAN0.TMC75)
+#define RSCAN0TMC76 (RSCAN0.TMC76)
+#define RSCAN0TMC77 (RSCAN0.TMC77)
+#define RSCAN0TMC78 (RSCAN0.TMC78)
+#define RSCAN0TMC79 (RSCAN0.TMC79)
+#define RSCAN0TMSTS0 (RSCAN0.TMSTS0)
+#define RSCAN0TMSTS1 (RSCAN0.TMSTS1)
+#define RSCAN0TMSTS2 (RSCAN0.TMSTS2)
+#define RSCAN0TMSTS3 (RSCAN0.TMSTS3)
+#define RSCAN0TMSTS4 (RSCAN0.TMSTS4)
+#define RSCAN0TMSTS5 (RSCAN0.TMSTS5)
+#define RSCAN0TMSTS6 (RSCAN0.TMSTS6)
+#define RSCAN0TMSTS7 (RSCAN0.TMSTS7)
+#define RSCAN0TMSTS8 (RSCAN0.TMSTS8)
+#define RSCAN0TMSTS9 (RSCAN0.TMSTS9)
+#define RSCAN0TMSTS10 (RSCAN0.TMSTS10)
+#define RSCAN0TMSTS11 (RSCAN0.TMSTS11)
+#define RSCAN0TMSTS12 (RSCAN0.TMSTS12)
+#define RSCAN0TMSTS13 (RSCAN0.TMSTS13)
+#define RSCAN0TMSTS14 (RSCAN0.TMSTS14)
+#define RSCAN0TMSTS15 (RSCAN0.TMSTS15)
+#define RSCAN0TMSTS16 (RSCAN0.TMSTS16)
+#define RSCAN0TMSTS17 (RSCAN0.TMSTS17)
+#define RSCAN0TMSTS18 (RSCAN0.TMSTS18)
+#define RSCAN0TMSTS19 (RSCAN0.TMSTS19)
+#define RSCAN0TMSTS20 (RSCAN0.TMSTS20)
+#define RSCAN0TMSTS21 (RSCAN0.TMSTS21)
+#define RSCAN0TMSTS22 (RSCAN0.TMSTS22)
+#define RSCAN0TMSTS23 (RSCAN0.TMSTS23)
+#define RSCAN0TMSTS24 (RSCAN0.TMSTS24)
+#define RSCAN0TMSTS25 (RSCAN0.TMSTS25)
+#define RSCAN0TMSTS26 (RSCAN0.TMSTS26)
+#define RSCAN0TMSTS27 (RSCAN0.TMSTS27)
+#define RSCAN0TMSTS28 (RSCAN0.TMSTS28)
+#define RSCAN0TMSTS29 (RSCAN0.TMSTS29)
+#define RSCAN0TMSTS30 (RSCAN0.TMSTS30)
+#define RSCAN0TMSTS31 (RSCAN0.TMSTS31)
+#define RSCAN0TMSTS32 (RSCAN0.TMSTS32)
+#define RSCAN0TMSTS33 (RSCAN0.TMSTS33)
+#define RSCAN0TMSTS34 (RSCAN0.TMSTS34)
+#define RSCAN0TMSTS35 (RSCAN0.TMSTS35)
+#define RSCAN0TMSTS36 (RSCAN0.TMSTS36)
+#define RSCAN0TMSTS37 (RSCAN0.TMSTS37)
+#define RSCAN0TMSTS38 (RSCAN0.TMSTS38)
+#define RSCAN0TMSTS39 (RSCAN0.TMSTS39)
+#define RSCAN0TMSTS40 (RSCAN0.TMSTS40)
+#define RSCAN0TMSTS41 (RSCAN0.TMSTS41)
+#define RSCAN0TMSTS42 (RSCAN0.TMSTS42)
+#define RSCAN0TMSTS43 (RSCAN0.TMSTS43)
+#define RSCAN0TMSTS44 (RSCAN0.TMSTS44)
+#define RSCAN0TMSTS45 (RSCAN0.TMSTS45)
+#define RSCAN0TMSTS46 (RSCAN0.TMSTS46)
+#define RSCAN0TMSTS47 (RSCAN0.TMSTS47)
+#define RSCAN0TMSTS48 (RSCAN0.TMSTS48)
+#define RSCAN0TMSTS49 (RSCAN0.TMSTS49)
+#define RSCAN0TMSTS50 (RSCAN0.TMSTS50)
+#define RSCAN0TMSTS51 (RSCAN0.TMSTS51)
+#define RSCAN0TMSTS52 (RSCAN0.TMSTS52)
+#define RSCAN0TMSTS53 (RSCAN0.TMSTS53)
+#define RSCAN0TMSTS54 (RSCAN0.TMSTS54)
+#define RSCAN0TMSTS55 (RSCAN0.TMSTS55)
+#define RSCAN0TMSTS56 (RSCAN0.TMSTS56)
+#define RSCAN0TMSTS57 (RSCAN0.TMSTS57)
+#define RSCAN0TMSTS58 (RSCAN0.TMSTS58)
+#define RSCAN0TMSTS59 (RSCAN0.TMSTS59)
+#define RSCAN0TMSTS60 (RSCAN0.TMSTS60)
+#define RSCAN0TMSTS61 (RSCAN0.TMSTS61)
+#define RSCAN0TMSTS62 (RSCAN0.TMSTS62)
+#define RSCAN0TMSTS63 (RSCAN0.TMSTS63)
+#define RSCAN0TMSTS64 (RSCAN0.TMSTS64)
+#define RSCAN0TMSTS65 (RSCAN0.TMSTS65)
+#define RSCAN0TMSTS66 (RSCAN0.TMSTS66)
+#define RSCAN0TMSTS67 (RSCAN0.TMSTS67)
+#define RSCAN0TMSTS68 (RSCAN0.TMSTS68)
+#define RSCAN0TMSTS69 (RSCAN0.TMSTS69)
+#define RSCAN0TMSTS70 (RSCAN0.TMSTS70)
+#define RSCAN0TMSTS71 (RSCAN0.TMSTS71)
+#define RSCAN0TMSTS72 (RSCAN0.TMSTS72)
+#define RSCAN0TMSTS73 (RSCAN0.TMSTS73)
+#define RSCAN0TMSTS74 (RSCAN0.TMSTS74)
+#define RSCAN0TMSTS75 (RSCAN0.TMSTS75)
+#define RSCAN0TMSTS76 (RSCAN0.TMSTS76)
+#define RSCAN0TMSTS77 (RSCAN0.TMSTS77)
+#define RSCAN0TMSTS78 (RSCAN0.TMSTS78)
+#define RSCAN0TMSTS79 (RSCAN0.TMSTS79)
+#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32)
+#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32)
+#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32)
+#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32)
+#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32)
+#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32)
+#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32)
+#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32)
+#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32)
+#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32)
+#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L])
+#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H])
+#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32)
+#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L])
+#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H])
+#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32)
+#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L])
+#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H])
+#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH])
+#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32)
+#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L])
+#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL])
+#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH])
+#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H])
+#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL])
+#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH])
+#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32)
+#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L])
+#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL])
+#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH])
+#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H])
+#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL])
+#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH])
+#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32)
+#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L])
+#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL])
+#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH])
+#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H])
+#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL])
+#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH])
+#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32)
+#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L])
+#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL])
+#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH])
+#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H])
+#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL])
+#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH])
+#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32)
+#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L])
+#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL])
+#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH])
+#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H])
+#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL])
+#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH])
+#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32)
+#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L])
+#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL])
+#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH])
+#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H])
+#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL])
+#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH])
+#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32)
+#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L])
+#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL])
+#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH])
+#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H])
+#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL])
+#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH])
+#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32)
+#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L])
+#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL])
+#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH])
+#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H])
+#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL])
+#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32)
+#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L])
+#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H])
+#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32)
+#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L])
+#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H])
+#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32)
+#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L])
+#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H])
+#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32)
+#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L])
+#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H])
+#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32)
+#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L])
+#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H])
+#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32)
+#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32)
+#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32)
+#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32)
+#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32)
+#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH])
+#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32)
+#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L])
+#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL])
+#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH])
+#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H])
+#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL])
+#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH])
+#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32)
+#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L])
+#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL])
+#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH])
+#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H])
+#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL])
+#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH])
+#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32)
+#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L])
+#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL])
+#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH])
+#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H])
+#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL])
+#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH])
+#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32)
+#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L])
+#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL])
+#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH])
+#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H])
+#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL])
+#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH])
+#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32)
+#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L])
+#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL])
+#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH])
+#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H])
+#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL])
+#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH])
+#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32)
+#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L])
+#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL])
+#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH])
+#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H])
+#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL])
+#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH])
+#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32)
+#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L])
+#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL])
+#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH])
+#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H])
+#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL])
+#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH])
+#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32)
+#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L])
+#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL])
+#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH])
+#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H])
+#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL])
+#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH])
+#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32)
+#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L])
+#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL])
+#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH])
+#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H])
+#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL])
+#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH])
+#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32)
+#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L])
+#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL])
+#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH])
+#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H])
+#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL])
+#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32)
+#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L])
+#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H])
+#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32)
+#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L])
+#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H])
+#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32)
+#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L])
+#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H])
+#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32)
+#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L])
+#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H])
+#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32)
+#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L])
+#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H])
+#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH])
+#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32)
+#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L])
+#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL])
+#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH])
+#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H])
+#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL])
+#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH])
+#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32)
+#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L])
+#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL])
+#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH])
+#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H])
+#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL])
+#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH])
+#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32)
+#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L])
+#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL])
+#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH])
+#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H])
+#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL])
+#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH])
+#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32)
+#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L])
+#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL])
+#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH])
+#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H])
+#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL])
+#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH])
+#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32)
+#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L])
+#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H])
+#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32)
+#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L])
+#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL])
+#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH])
+#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H])
+#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL])
+#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH])
+#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32)
+#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L])
+#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL])
+#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH])
+#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H])
+#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL])
+#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH])
+#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32)
+#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L])
+#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL])
+#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH])
+#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H])
+#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL])
+#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH])
+#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32)
+#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L])
+#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL])
+#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH])
+#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H])
+#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL])
+#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH])
+#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32)
+#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L])
+#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL])
+#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH])
+#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H])
+#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL])
+#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH])
+#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32)
+#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L])
+#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL])
+#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH])
+#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H])
+#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL])
+#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH])
+#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32)
+#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L])
+#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL])
+#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH])
+#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H])
+#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL])
+#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH])
+#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32)
+#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L])
+#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL])
+#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH])
+#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H])
+#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL])
+#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH])
+#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32)
+#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L])
+#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL])
+#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH])
+#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H])
+#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL])
+#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH])
+#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32)
+#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L])
+#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL])
+#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH])
+#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H])
+#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL])
+#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH])
+#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32)
+#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L])
+#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL])
+#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH])
+#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H])
+#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL])
+#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH])
+#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32)
+#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L])
+#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL])
+#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH])
+#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H])
+#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL])
+#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH])
+#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32)
+#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L])
+#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL])
+#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH])
+#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H])
+#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL])
+#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH])
+#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32)
+#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L])
+#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL])
+#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH])
+#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H])
+#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL])
+#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH])
+#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32)
+#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L])
+#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL])
+#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH])
+#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H])
+#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL])
+#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH])
+#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32)
+#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L])
+#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL])
+#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH])
+#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H])
+#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL])
+#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH])
+#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32)
+#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L])
+#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL])
+#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH])
+#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H])
+#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL])
+#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH])
+#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32)
+#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L])
+#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL])
+#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH])
+#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H])
+#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL])
+#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH])
+#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32)
+#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L])
+#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL])
+#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH])
+#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H])
+#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL])
+#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH])
+#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32)
+#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L])
+#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL])
+#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH])
+#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H])
+#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL])
+#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH])
+#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32)
+#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L])
+#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL])
+#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH])
+#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H])
+#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL])
+#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH])
+#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32)
+#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L])
+#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL])
+#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH])
+#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H])
+#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL])
+#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH])
+#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32)
+#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L])
+#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL])
+#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH])
+#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H])
+#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL])
+#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH])
+#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32)
+#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L])
+#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL])
+#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH])
+#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H])
+#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL])
+#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH])
+#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32)
+#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L])
+#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL])
+#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH])
+#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H])
+#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL])
+#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH])
+#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32)
+#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L])
+#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL])
+#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH])
+#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H])
+#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL])
+#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH])
+#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32)
+#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L])
+#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL])
+#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH])
+#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H])
+#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL])
+#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH])
+#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32)
+#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L])
+#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL])
+#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH])
+#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H])
+#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL])
+#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH])
+#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32)
+#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L])
+#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL])
+#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH])
+#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H])
+#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL])
+#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH])
+#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32)
+#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L])
+#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL])
+#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH])
+#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H])
+#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL])
+#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH])
+#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32)
+#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L])
+#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL])
+#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH])
+#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H])
+#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL])
+#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH])
+#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32)
+#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L])
+#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL])
+#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH])
+#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H])
+#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL])
+#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH])
+#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32)
+#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L])
+#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL])
+#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH])
+#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H])
+#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL])
+#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH])
+#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32)
+#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L])
+#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL])
+#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH])
+#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H])
+#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL])
+#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH])
+#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32)
+#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L])
+#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL])
+#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH])
+#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H])
+#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL])
+#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH])
+#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32)
+#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L])
+#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL])
+#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH])
+#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H])
+#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL])
+#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH])
+#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32)
+#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L])
+#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL])
+#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH])
+#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H])
+#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL])
+#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH])
+#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32)
+#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L])
+#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL])
+#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH])
+#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H])
+#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL])
+#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH])
+#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32)
+#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L])
+#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL])
+#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH])
+#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H])
+#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL])
+#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH])
+#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32)
+#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L])
+#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL])
+#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH])
+#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H])
+#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL])
+#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH])
+#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32)
+#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L])
+#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL])
+#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH])
+#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H])
+#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL])
+#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH])
+#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32)
+#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L])
+#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL])
+#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH])
+#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H])
+#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL])
+#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH])
+#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32)
+#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L])
+#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL])
+#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH])
+#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H])
+#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL])
+#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH])
+#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32)
+#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L])
+#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL])
+#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH])
+#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H])
+#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL])
+#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH])
+#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32)
+#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L])
+#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL])
+#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH])
+#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H])
+#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL])
+#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH])
+#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32)
+#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L])
+#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL])
+#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH])
+#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H])
+#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL])
+#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH])
+#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32)
+#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L])
+#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL])
+#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH])
+#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H])
+#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL])
+#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH])
+#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32)
+#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L])
+#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL])
+#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH])
+#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H])
+#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL])
+#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH])
+#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32)
+#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L])
+#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL])
+#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH])
+#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H])
+#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL])
+#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH])
+#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32)
+#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L])
+#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL])
+#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH])
+#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H])
+#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL])
+#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH])
+#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32)
+#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L])
+#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL])
+#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH])
+#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H])
+#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL])
+#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH])
+#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32)
+#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L])
+#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL])
+#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH])
+#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H])
+#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL])
+#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH])
+#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32)
+#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L])
+#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL])
+#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH])
+#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H])
+#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL])
+#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH])
+#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32)
+#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L])
+#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL])
+#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH])
+#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H])
+#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL])
+#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH])
+#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32)
+#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L])
+#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL])
+#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH])
+#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H])
+#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL])
+#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH])
+#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32)
+#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L])
+#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL])
+#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH])
+#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H])
+#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL])
+#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH])
+#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32)
+#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L])
+#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL])
+#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH])
+#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H])
+#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL])
+#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH])
+#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32)
+#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L])
+#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL])
+#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH])
+#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H])
+#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL])
+#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH])
+#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32)
+#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L])
+#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL])
+#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH])
+#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H])
+#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL])
+#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH])
+#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32)
+#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L])
+#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL])
+#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH])
+#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H])
+#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL])
+#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH])
+#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32)
+#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L])
+#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL])
+#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH])
+#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H])
+#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL])
+#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH])
+#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32)
+#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L])
+#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL])
+#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH])
+#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H])
+#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL])
+#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH])
+#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32)
+#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L])
+#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL])
+#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH])
+#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H])
+#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL])
+#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH])
+#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32)
+#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L])
+#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL])
+#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH])
+#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H])
+#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL])
+#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH])
+#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32)
+#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L])
+#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL])
+#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH])
+#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H])
+#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL])
+#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH])
+#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32)
+#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L])
+#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL])
+#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH])
+#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H])
+#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL])
+#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH])
+#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32)
+#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L])
+#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL])
+#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH])
+#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H])
+#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL])
+#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH])
+#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32)
+#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L])
+#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL])
+#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH])
+#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H])
+#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL])
+#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH])
+#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32)
+#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L])
+#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL])
+#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH])
+#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H])
+#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL])
+#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH])
+#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32)
+#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L])
+#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL])
+#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH])
+#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H])
+#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL])
+#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH])
+#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32)
+#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L])
+#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL])
+#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH])
+#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H])
+#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL])
+#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH])
+#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32)
+#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L])
+#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL])
+#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH])
+#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H])
+#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL])
+#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH])
+#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32)
+#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L])
+#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL])
+#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH])
+#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H])
+#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL])
+#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH])
+#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32)
+#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L])
+#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL])
+#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH])
+#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H])
+#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL])
+#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH])
+#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32)
+#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L])
+#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL])
+#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH])
+#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H])
+#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL])
+#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH])
+#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32)
+#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L])
+#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL])
+#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH])
+#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H])
+#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL])
+#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH])
+#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32)
+#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L])
+#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL])
+#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH])
+#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H])
+#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL])
+#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH])
+#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32)
+#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L])
+#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL])
+#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH])
+#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H])
+#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL])
+#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH])
+#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32)
+#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L])
+#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL])
+#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH])
+#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H])
+#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL])
+#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH])
+#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32)
+#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L])
+#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL])
+#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH])
+#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H])
+#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL])
+#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH])
+#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32)
+#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L])
+#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL])
+#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH])
+#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H])
+#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL])
+#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH])
+#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32)
+#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L])
+#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL])
+#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH])
+#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H])
+#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL])
+#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH])
+#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32)
+#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L])
+#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL])
+#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH])
+#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H])
+#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL])
+#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH])
+#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32)
+#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L])
+#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL])
+#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH])
+#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H])
+#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL])
+#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH])
+#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32)
+#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L])
+#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL])
+#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH])
+#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H])
+#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL])
+#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH])
+#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32)
+#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L])
+#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL])
+#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH])
+#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H])
+#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL])
+#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH])
+#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32)
+#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L])
+#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL])
+#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH])
+#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H])
+#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL])
+#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH])
+#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32)
+#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L])
+#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL])
+#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH])
+#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H])
+#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL])
+#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH])
+#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32)
+#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L])
+#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL])
+#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH])
+#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H])
+#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL])
+#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH])
+#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32)
+#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L])
+#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL])
+#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH])
+#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H])
+#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL])
+#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH])
+#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32)
+#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L])
+#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL])
+#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH])
+#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H])
+#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL])
+#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH])
+#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32)
+#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L])
+#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL])
+#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH])
+#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H])
+#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL])
+#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH])
+#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32)
+#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L])
+#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL])
+#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH])
+#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H])
+#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL])
+#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH])
+#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32)
+#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L])
+#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL])
+#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH])
+#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H])
+#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL])
+#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH])
+#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32)
+#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L])
+#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL])
+#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH])
+#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H])
+#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL])
+#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH])
+#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32)
+#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L])
+#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL])
+#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH])
+#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H])
+#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL])
+#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH])
+#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32)
+#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L])
+#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL])
+#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH])
+#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H])
+#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL])
+#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH])
+#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32)
+#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L])
+#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL])
+#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH])
+#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H])
+#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL])
+#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH])
+#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32)
+#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L])
+#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL])
+#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH])
+#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H])
+#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL])
+#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH])
+#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32)
+#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L])
+#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL])
+#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH])
+#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H])
+#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL])
+#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH])
+#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32)
+#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L])
+#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL])
+#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH])
+#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H])
+#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL])
+#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH])
+#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32)
+#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L])
+#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL])
+#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH])
+#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H])
+#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL])
+#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH])
+#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32)
+#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L])
+#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL])
+#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH])
+#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H])
+#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL])
+#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH])
+#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32)
+#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L])
+#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL])
+#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH])
+#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H])
+#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL])
+#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH])
+#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32)
+#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L])
+#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL])
+#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH])
+#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H])
+#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL])
+#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH])
+#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32)
+#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L])
+#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL])
+#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH])
+#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H])
+#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL])
+#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH])
+#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32)
+#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L])
+#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL])
+#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH])
+#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H])
+#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL])
+#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH])
+#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32)
+#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L])
+#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL])
+#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH])
+#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H])
+#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL])
+#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH])
+#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32)
+#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L])
+#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL])
+#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH])
+#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H])
+#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL])
+#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH])
+#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32)
+#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L])
+#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL])
+#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH])
+#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H])
+#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL])
+#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH])
+#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32)
+#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L])
+#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL])
+#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH])
+#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H])
+#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL])
+#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH])
+#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32)
+#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L])
+#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL])
+#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH])
+#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H])
+#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL])
+#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH])
+#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32)
+#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L])
+#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL])
+#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH])
+#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H])
+#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL])
+#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH])
+#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32)
+#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L])
+#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL])
+#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH])
+#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H])
+#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL])
+#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH])
+#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32)
+#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L])
+#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL])
+#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH])
+#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H])
+#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL])
+#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH])
+#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32)
+#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L])
+#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL])
+#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH])
+#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H])
+#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL])
+#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH])
+#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32)
+#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L])
+#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL])
+#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH])
+#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H])
+#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL])
+#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH])
+#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32)
+#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L])
+#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL])
+#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH])
+#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H])
+#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL])
+#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH])
+#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32)
+#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L])
+#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL])
+#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH])
+#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H])
+#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL])
+#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH])
+#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32)
+#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L])
+#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL])
+#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH])
+#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H])
+#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL])
+#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH])
+#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32)
+#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L])
+#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL])
+#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH])
+#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H])
+#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL])
+#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH])
+#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32)
+#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L])
+#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL])
+#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH])
+#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H])
+#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL])
+#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH])
+#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32)
+#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L])
+#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL])
+#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH])
+#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H])
+#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL])
+#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH])
+#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32)
+#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L])
+#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL])
+#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH])
+#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H])
+#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL])
+#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH])
+#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32)
+#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L])
+#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL])
+#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH])
+#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H])
+#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL])
+#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH])
+#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32)
+#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L])
+#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL])
+#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH])
+#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H])
+#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL])
+#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH])
+#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32)
+#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L])
+#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL])
+#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH])
+#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H])
+#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL])
+#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH])
+#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32)
+#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L])
+#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL])
+#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH])
+#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H])
+#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL])
+#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH])
+#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32)
+#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L])
+#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL])
+#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH])
+#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H])
+#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL])
+#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH])
+#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32)
+#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L])
+#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL])
+#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH])
+#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H])
+#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL])
+#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH])
+#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32)
+#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L])
+#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL])
+#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH])
+#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H])
+#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL])
+#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH])
+#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32)
+#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L])
+#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL])
+#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH])
+#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H])
+#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL])
+#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH])
+#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32)
+#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L])
+#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL])
+#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH])
+#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H])
+#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL])
+#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH])
+#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32)
+#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L])
+#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL])
+#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH])
+#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H])
+#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL])
+#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH])
+#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32)
+#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L])
+#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL])
+#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH])
+#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H])
+#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL])
+#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH])
+#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32)
+#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L])
+#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL])
+#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH])
+#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H])
+#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL])
+#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH])
+#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32)
+#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L])
+#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL])
+#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH])
+#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H])
+#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL])
+#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH])
+#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32)
+#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L])
+#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL])
+#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH])
+#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H])
+#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL])
+#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH])
+#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32)
+#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L])
+#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL])
+#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH])
+#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H])
+#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL])
+#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH])
+#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32)
+#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L])
+#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL])
+#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH])
+#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H])
+#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL])
+#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH])
+#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32)
+#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L])
+#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL])
+#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH])
+#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H])
+#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL])
+#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH])
+#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32)
+#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L])
+#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL])
+#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH])
+#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H])
+#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL])
+#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH])
+#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32)
+#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L])
+#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL])
+#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH])
+#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H])
+#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL])
+#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH])
+#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32)
+#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L])
+#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL])
+#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH])
+#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H])
+#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL])
+#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH])
+#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32)
+#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L])
+#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL])
+#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH])
+#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H])
+#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL])
+#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH])
+#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32)
+#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L])
+#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL])
+#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH])
+#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H])
+#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL])
+#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH])
+#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32)
+#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L])
+#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL])
+#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH])
+#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H])
+#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL])
+#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH])
+#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32)
+#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L])
+#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL])
+#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH])
+#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H])
+#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL])
+#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH])
+#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32)
+#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L])
+#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL])
+#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH])
+#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H])
+#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL])
+#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH])
+#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32)
+#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L])
+#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL])
+#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH])
+#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H])
+#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL])
+#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH])
+#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32)
+#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L])
+#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL])
+#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH])
+#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H])
+#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL])
+#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH])
+#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32)
+#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L])
+#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL])
+#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH])
+#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H])
+#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL])
+#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH])
+#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32)
+#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L])
+#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL])
+#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH])
+#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H])
+#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL])
+#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH])
+#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32)
+#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L])
+#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL])
+#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH])
+#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H])
+#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL])
+#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH])
+#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32)
+#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L])
+#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL])
+#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH])
+#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H])
+#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL])
+#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH])
+#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32)
+#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L])
+#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL])
+#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH])
+#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H])
+#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL])
+#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH])
+#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32)
+#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L])
+#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL])
+#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH])
+#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H])
+#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL])
+#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH])
+#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32)
+#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L])
+#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL])
+#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH])
+#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H])
+#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL])
+#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH])
+#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32)
+#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L])
+#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL])
+#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH])
+#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H])
+#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL])
+#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH])
+#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32)
+#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L])
+#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL])
+#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH])
+#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H])
+#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL])
+#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH])
+#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32)
+#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L])
+#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL])
+#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH])
+#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H])
+#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL])
+#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH])
+#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32)
+#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L])
+#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL])
+#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH])
+#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H])
+#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL])
+#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH])
+#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32)
+#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L])
+#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL])
+#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH])
+#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H])
+#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL])
+#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH])
+#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32)
+#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L])
+#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL])
+#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH])
+#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H])
+#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL])
+#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH])
+#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32)
+#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L])
+#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL])
+#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH])
+#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H])
+#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL])
+#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH])
+#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32)
+#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L])
+#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL])
+#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH])
+#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H])
+#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL])
+#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH])
+#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32)
+#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L])
+#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL])
+#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH])
+#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H])
+#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL])
+#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH])
+#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32)
+#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L])
+#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL])
+#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH])
+#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H])
+#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL])
+#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH])
+#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32)
+#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L])
+#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL])
+#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH])
+#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H])
+#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL])
+#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH])
+#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32)
+#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L])
+#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL])
+#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH])
+#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H])
+#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL])
+#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH])
+#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32)
+#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L])
+#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL])
+#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH])
+#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H])
+#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL])
+#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH])
+#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32)
+#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L])
+#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL])
+#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH])
+#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H])
+#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL])
+#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH])
+#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32)
+#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L])
+#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL])
+#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH])
+#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H])
+#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL])
+#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH])
+#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32)
+#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L])
+#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL])
+#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH])
+#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H])
+#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL])
+#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH])
+#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32)
+#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L])
+#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL])
+#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH])
+#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H])
+#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL])
+#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH])
+#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32)
+#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L])
+#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL])
+#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH])
+#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H])
+#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL])
+#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH])
+#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32)
+#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L])
+#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL])
+#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH])
+#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H])
+#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL])
+#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH])
+#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32)
+#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L])
+#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL])
+#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH])
+#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H])
+#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL])
+#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH])
+#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32)
+#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L])
+#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL])
+#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH])
+#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H])
+#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL])
+#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH])
+#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32)
+#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L])
+#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL])
+#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH])
+#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H])
+#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL])
+#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH])
+#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32)
+#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L])
+#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL])
+#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH])
+#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H])
+#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL])
+#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH])
+#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32)
+#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L])
+#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL])
+#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH])
+#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H])
+#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL])
+#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH])
+#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32)
+#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L])
+#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL])
+#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH])
+#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H])
+#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL])
+#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH])
+#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32)
+#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L])
+#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL])
+#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH])
+#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H])
+#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL])
+#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH])
+#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32)
+#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L])
+#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL])
+#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH])
+#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H])
+#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL])
+#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH])
+#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32)
+#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L])
+#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL])
+#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH])
+#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H])
+#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL])
+#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH])
+#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32)
+#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L])
+#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL])
+#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH])
+#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H])
+#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL])
+#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH])
+#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32)
+#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L])
+#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL])
+#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH])
+#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H])
+#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL])
+#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH])
+#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32)
+#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L])
+#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL])
+#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH])
+#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H])
+#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL])
+#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH])
+#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32)
+#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L])
+#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL])
+#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH])
+#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H])
+#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL])
+#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH])
+#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32)
+#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L])
+#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL])
+#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH])
+#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H])
+#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL])
+#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH])
+#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32)
+#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L])
+#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL])
+#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH])
+#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H])
+#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL])
+#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH])
+#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32)
+#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L])
+#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL])
+#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH])
+#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H])
+#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL])
+#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH])
+#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32)
+#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L])
+#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL])
+#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH])
+#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H])
+#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL])
+#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH])
+#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32)
+#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L])
+#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL])
+#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH])
+#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H])
+#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL])
+#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH])
+#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32)
+#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L])
+#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL])
+#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH])
+#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H])
+#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL])
+#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH])
+#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32)
+#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L])
+#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL])
+#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH])
+#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H])
+#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL])
+#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH])
+#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32)
+#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L])
+#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL])
+#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH])
+#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H])
+#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL])
+#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH])
+#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32)
+#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L])
+#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL])
+#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH])
+#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H])
+#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL])
+#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH])
+#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32)
+#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L])
+#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL])
+#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH])
+#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H])
+#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL])
+#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH])
+#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32)
+#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L])
+#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL])
+#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH])
+#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H])
+#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL])
+#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH])
+#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32)
+#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L])
+#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL])
+#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH])
+#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H])
+#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL])
+#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH])
+#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32)
+#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L])
+#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL])
+#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH])
+#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H])
+#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL])
+#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH])
+#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32)
+#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L])
+#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL])
+#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH])
+#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H])
+#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL])
+#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH])
+#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32)
+#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L])
+#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL])
+#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH])
+#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H])
+#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL])
+#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH])
+#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32)
+#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L])
+#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL])
+#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH])
+#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H])
+#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL])
+#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH])
+#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32)
+#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L])
+#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL])
+#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH])
+#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H])
+#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL])
+#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH])
+#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32)
+#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L])
+#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL])
+#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH])
+#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H])
+#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL])
+#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH])
+#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32)
+#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L])
+#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL])
+#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH])
+#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H])
+#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL])
+#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH])
+#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32)
+#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L])
+#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL])
+#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH])
+#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H])
+#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL])
+#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH])
+#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32)
+#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L])
+#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL])
+#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH])
+#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H])
+#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL])
+#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH])
+#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32)
+#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L])
+#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL])
+#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH])
+#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H])
+#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL])
+#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH])
+#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32)
+#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L])
+#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL])
+#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH])
+#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H])
+#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL])
+#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH])
+#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32)
+#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L])
+#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL])
+#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH])
+#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H])
+#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL])
+#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH])
+#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32)
+#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L])
+#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL])
+#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH])
+#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H])
+#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL])
+#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH])
+#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32)
+#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L])
+#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL])
+#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH])
+#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H])
+#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL])
+#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH])
+#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32)
+#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L])
+#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL])
+#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH])
+#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H])
+#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL])
+#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH])
+#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32)
+#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L])
+#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL])
+#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH])
+#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H])
+#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL])
+#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH])
+#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32)
+#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L])
+#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL])
+#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH])
+#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H])
+#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL])
+#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH])
+#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32)
+#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L])
+#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL])
+#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH])
+#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H])
+#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL])
+#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH])
+#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32)
+#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L])
+#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL])
+#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH])
+#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H])
+#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL])
+#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH])
+#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32)
+#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L])
+#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL])
+#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH])
+#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H])
+#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL])
+#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH])
+#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32)
+#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L])
+#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL])
+#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH])
+#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H])
+#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL])
+#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH])
+#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32)
+#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L])
+#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL])
+#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH])
+#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H])
+#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL])
+#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH])
+#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32)
+#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L])
+#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL])
+#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH])
+#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H])
+#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL])
+#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH])
+#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32)
+#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L])
+#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL])
+#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH])
+#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H])
+#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL])
+#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH])
+#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32)
+#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L])
+#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL])
+#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH])
+#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H])
+#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL])
+#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH])
+#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32)
+#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L])
+#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL])
+#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH])
+#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H])
+#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL])
+#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH])
+#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32)
+#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L])
+#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL])
+#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH])
+#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H])
+#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL])
+#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH])
+#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32)
+#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L])
+#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL])
+#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH])
+#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H])
+#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL])
+#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH])
+#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32)
+#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L])
+#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL])
+#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH])
+#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H])
+#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL])
+#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH])
+#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32)
+#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L])
+#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL])
+#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH])
+#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H])
+#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL])
+#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH])
+#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32)
+#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L])
+#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL])
+#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH])
+#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H])
+#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL])
+#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH])
+#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32)
+#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L])
+#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL])
+#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH])
+#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H])
+#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL])
+#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH])
+#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32)
+#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L])
+#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL])
+#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH])
+#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H])
+#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL])
+#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH])
+#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32)
+#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L])
+#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL])
+#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH])
+#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H])
+#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL])
+#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH])
+#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32)
+#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L])
+#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL])
+#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH])
+#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H])
+#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL])
+#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH])
+#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32)
+#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L])
+#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL])
+#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH])
+#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H])
+#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL])
+#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH])
+#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32)
+#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L])
+#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL])
+#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH])
+#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H])
+#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL])
+#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH])
+#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32)
+#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L])
+#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL])
+#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH])
+#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H])
+#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL])
+#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH])
+#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32)
+#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L])
+#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL])
+#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH])
+#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H])
+#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL])
+#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH])
+#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32)
+#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L])
+#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL])
+#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH])
+#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H])
+#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL])
+#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH])
+#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32)
+#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L])
+#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL])
+#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH])
+#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H])
+#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL])
+#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH])
+#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32)
+#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L])
+#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL])
+#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH])
+#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H])
+#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL])
+#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH])
+#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32)
+#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L])
+#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL])
+#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH])
+#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H])
+#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL])
+#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH])
+#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32)
+#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L])
+#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL])
+#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH])
+#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H])
+#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL])
+#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH])
+#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32)
+#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L])
+#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL])
+#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH])
+#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H])
+#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL])
+#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH])
+#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32)
+#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L])
+#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL])
+#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH])
+#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H])
+#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL])
+#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH])
+#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32)
+#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L])
+#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL])
+#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH])
+#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H])
+#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL])
+#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH])
+#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32)
+#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L])
+#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL])
+#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH])
+#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H])
+#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL])
+#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH])
+#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32)
+#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L])
+#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL])
+#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH])
+#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H])
+#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL])
+#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH])
+#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32)
+#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L])
+#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL])
+#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH])
+#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H])
+#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL])
+#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH])
+#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32)
+#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L])
+#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL])
+#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH])
+#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H])
+#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL])
+#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH])
+#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32)
+#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L])
+#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL])
+#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH])
+#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H])
+#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL])
+#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH])
+#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32)
+#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L])
+#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL])
+#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH])
+#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H])
+#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL])
+#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH])
+#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32)
+#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L])
+#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL])
+#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH])
+#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H])
+#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL])
+#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH])
+#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32)
+#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L])
+#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL])
+#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH])
+#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H])
+#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL])
+#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH])
+#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32)
+#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L])
+#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL])
+#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH])
+#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H])
+#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL])
+#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH])
+#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32)
+#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L])
+#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL])
+#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH])
+#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H])
+#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL])
+#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH])
+#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32)
+#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L])
+#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL])
+#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH])
+#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H])
+#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL])
+#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH])
+#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32)
+#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L])
+#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL])
+#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH])
+#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H])
+#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL])
+#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH])
+#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32)
+#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L])
+#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL])
+#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH])
+#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H])
+#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL])
+#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH])
+#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32)
+#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L])
+#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL])
+#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH])
+#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H])
+#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL])
+#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH])
+#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32)
+#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L])
+#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL])
+#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH])
+#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H])
+#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL])
+#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH])
+#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32)
+#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L])
+#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL])
+#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH])
+#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H])
+#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL])
+#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH])
+#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32)
+#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L])
+#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL])
+#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH])
+#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H])
+#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL])
+#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH])
+#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32)
+#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L])
+#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL])
+#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH])
+#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H])
+#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL])
+#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH])
+#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32)
+#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L])
+#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL])
+#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH])
+#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H])
+#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL])
+#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH])
+#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32)
+#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L])
+#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL])
+#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH])
+#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H])
+#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL])
+#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH])
+#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32)
+#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L])
+#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL])
+#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH])
+#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H])
+#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL])
+#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH])
+#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32)
+#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L])
+#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL])
+#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH])
+#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H])
+#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL])
+#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH])
+#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32)
+#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L])
+#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL])
+#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH])
+#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H])
+#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL])
+#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH])
+#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32)
+#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L])
+#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL])
+#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH])
+#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H])
+#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL])
+#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH])
+#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32)
+#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L])
+#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL])
+#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH])
+#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H])
+#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL])
+#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH])
+#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32)
+#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L])
+#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL])
+#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH])
+#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H])
+#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL])
+#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH])
+#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32)
+#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L])
+#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL])
+#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH])
+#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H])
+#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL])
+#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH])
+#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32)
+#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L])
+#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL])
+#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH])
+#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H])
+#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL])
+#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH])
+#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32)
+#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L])
+#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL])
+#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH])
+#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H])
+#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL])
+#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH])
+#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32)
+#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L])
+#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL])
+#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH])
+#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H])
+#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL])
+#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH])
+#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32)
+#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L])
+#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL])
+#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH])
+#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H])
+#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL])
+#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH])
+#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32)
+#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L])
+#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL])
+#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH])
+#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H])
+#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL])
+#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH])
+#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32)
+#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L])
+#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL])
+#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH])
+#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H])
+#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL])
+#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH])
+#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32)
+#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L])
+#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL])
+#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH])
+#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H])
+#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL])
+#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH])
+#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32)
+#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L])
+#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL])
+#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH])
+#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H])
+#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL])
+#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH])
+#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32)
+#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L])
+#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL])
+#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH])
+#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H])
+#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL])
+#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH])
+#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32)
+#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L])
+#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL])
+#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH])
+#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H])
+#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL])
+#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH])
+#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32)
+#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L])
+#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL])
+#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH])
+#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H])
+#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL])
+#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH])
+#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32)
+#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L])
+#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL])
+#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH])
+#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H])
+#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL])
+#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH])
+#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32)
+#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L])
+#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL])
+#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH])
+#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H])
+#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL])
+#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH])
+#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32)
+#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L])
+#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL])
+#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH])
+#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H])
+#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL])
+#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH])
+#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32)
+#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L])
+#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL])
+#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH])
+#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H])
+#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL])
+#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH])
+#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32)
+#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L])
+#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL])
+#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH])
+#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H])
+#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL])
+#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH])
+#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32)
+#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L])
+#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL])
+#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH])
+#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H])
+#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL])
+#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH])
+#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32)
+#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L])
+#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL])
+#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH])
+#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H])
+#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL])
+#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH])
+#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32)
+#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L])
+#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL])
+#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH])
+#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H])
+#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL])
+#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH])
+#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32)
+#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L])
+#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL])
+#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH])
+#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H])
+#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL])
+#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH])
+#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32)
+#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L])
+#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL])
+#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH])
+#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H])
+#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL])
+#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH])
+#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32)
+#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L])
+#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL])
+#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH])
+#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H])
+#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL])
+#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH])
+#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32)
+#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L])
+#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL])
+#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH])
+#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H])
+#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL])
+#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH])
+#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32)
+#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L])
+#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL])
+#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH])
+#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H])
+#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL])
+#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH])
+#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32)
+#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L])
+#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL])
+#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH])
+#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H])
+#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL])
+#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH])
+#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32)
+#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L])
+#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL])
+#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH])
+#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H])
+#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL])
+#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH])
+#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32)
+#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L])
+#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL])
+#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH])
+#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H])
+#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL])
+#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH])
+#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32)
+#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L])
+#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL])
+#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH])
+#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H])
+#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL])
+#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH])
+#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32)
+#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L])
+#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL])
+#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH])
+#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H])
+#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL])
+#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH])
+#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32)
+#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L])
+#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL])
+#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH])
+#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H])
+#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL])
+#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH])
+#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32)
+#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L])
+#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL])
+#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH])
+#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H])
+#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL])
+#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH])
+#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32)
+#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L])
+#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL])
+#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH])
+#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H])
+#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL])
+#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH])
+#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32)
+#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L])
+#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL])
+#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH])
+#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H])
+#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL])
+#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH])
+#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32)
+#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L])
+#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL])
+#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH])
+#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H])
+#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL])
+#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH])
+#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32)
+#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L])
+#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL])
+#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH])
+#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H])
+#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL])
+#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH])
+#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32)
+#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L])
+#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL])
+#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH])
+#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H])
+#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL])
+#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH])
+#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32)
+#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L])
+#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL])
+#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH])
+#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H])
+#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL])
+#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH])
+#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32)
+#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L])
+#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL])
+#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH])
+#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H])
+#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL])
+#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH])
+#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32)
+#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L])
+#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL])
+#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH])
+#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H])
+#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL])
+#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH])
+#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32)
+#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L])
+#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL])
+#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH])
+#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H])
+#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL])
+#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH])
+#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32)
+#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L])
+#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL])
+#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH])
+#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H])
+#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL])
+#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH])
+#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32)
+#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L])
+#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL])
+#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH])
+#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H])
+#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL])
+#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH])
+#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32)
+#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L])
+#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL])
+#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH])
+#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H])
+#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL])
+#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH])
+#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32)
+#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L])
+#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL])
+#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH])
+#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H])
+#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL])
+#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH])
+#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32)
+#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L])
+#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL])
+#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH])
+#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H])
+#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL])
+#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH])
+#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32)
+#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L])
+#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL])
+#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH])
+#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H])
+#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL])
+#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH])
+#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32)
+#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L])
+#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL])
+#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH])
+#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H])
+#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL])
+#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH])
+#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32)
+#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L])
+#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL])
+#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH])
+#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H])
+#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL])
+#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH])
+#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32)
+#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L])
+#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL])
+#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH])
+#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H])
+#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL])
+#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH])
+#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32)
+#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L])
+#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL])
+#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH])
+#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H])
+#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL])
+#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH])
+#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32)
+#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L])
+#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL])
+#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH])
+#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H])
+#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL])
+#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH])
+#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32)
+#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L])
+#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL])
+#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH])
+#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H])
+#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL])
+#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH])
+#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32)
+#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L])
+#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL])
+#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH])
+#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H])
+#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL])
+#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH])
+#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32)
+#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L])
+#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL])
+#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH])
+#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H])
+#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL])
+#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH])
+#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32)
+#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L])
+#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL])
+#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH])
+#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H])
+#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL])
+#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH])
+#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32)
+#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L])
+#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL])
+#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH])
+#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H])
+#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL])
+#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH])
+#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32)
+#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L])
+#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL])
+#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH])
+#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H])
+#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL])
+#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH])
+#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32)
+#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L])
+#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL])
+#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH])
+#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H])
+#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL])
+#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH])
+#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32)
+#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L])
+#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL])
+#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH])
+#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H])
+#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL])
+#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH])
+#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32)
+#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L])
+#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL])
+#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH])
+#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H])
+#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL])
+#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH])
+#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32)
+#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L])
+#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL])
+#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH])
+#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H])
+#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL])
+#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH])
+#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32)
+#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L])
+#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL])
+#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH])
+#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H])
+#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL])
+#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH])
+#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32)
+#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L])
+#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL])
+#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH])
+#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H])
+#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL])
+#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH])
+#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32)
+#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L])
+#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL])
+#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH])
+#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H])
+#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL])
+#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH])
+#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32)
+#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L])
+#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL])
+#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH])
+#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H])
+#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL])
+#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH])
+#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32)
+#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L])
+#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL])
+#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH])
+#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H])
+#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL])
+#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH])
+#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32)
+#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L])
+#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL])
+#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH])
+#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H])
+#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL])
+#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH])
+#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32)
+#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L])
+#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL])
+#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH])
+#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H])
+#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL])
+#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH])
+#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32)
+#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L])
+#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL])
+#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH])
+#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H])
+#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL])
+#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH])
+#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32)
+#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L])
+#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL])
+#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH])
+#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H])
+#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL])
+#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH])
+#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32)
+#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L])
+#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL])
+#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH])
+#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H])
+#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL])
+#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH])
+#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32)
+#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L])
+#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL])
+#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH])
+#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H])
+#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL])
+#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH])
+#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32)
+#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L])
+#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL])
+#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH])
+#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H])
+#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL])
+#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH])
+#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32)
+#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L])
+#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL])
+#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH])
+#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H])
+#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL])
+#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH])
+#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32)
+#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L])
+#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL])
+#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH])
+#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H])
+#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL])
+#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH])
+#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32)
+#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L])
+#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL])
+#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH])
+#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H])
+#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL])
+#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH])
+#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32)
+#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L])
+#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL])
+#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH])
+#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H])
+#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL])
+#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH])
+#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32)
+#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L])
+#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL])
+#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH])
+#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H])
+#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL])
+#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH])
+#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32)
+#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L])
+#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL])
+#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH])
+#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H])
+#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL])
+#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH])
+#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32)
+#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L])
+#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL])
+#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH])
+#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H])
+#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL])
+#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH])
+#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32)
+#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L])
+#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL])
+#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH])
+#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H])
+#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL])
+#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH])
+#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32)
+#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L])
+#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL])
+#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH])
+#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H])
+#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL])
+#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH])
+#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32)
+#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L])
+#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL])
+#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH])
+#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H])
+#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL])
+#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH])
+#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32)
+#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L])
+#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL])
+#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH])
+#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H])
+#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL])
+#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH])
+#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32)
+#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L])
+#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL])
+#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH])
+#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H])
+#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL])
+#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH])
+#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32)
+#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L])
+#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL])
+#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH])
+#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H])
+#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL])
+#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH])
+#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32)
+#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L])
+#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL])
+#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH])
+#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H])
+#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL])
+#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH])
+#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32)
+#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L])
+#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL])
+#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH])
+#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H])
+#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL])
+#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH])
+#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32)
+#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L])
+#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL])
+#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH])
+#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H])
+#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL])
+#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH])
+#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32)
+#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L])
+#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL])
+#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH])
+#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H])
+#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL])
+#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH])
+#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32)
+#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L])
+#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL])
+#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH])
+#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H])
+#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL])
+#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH])
+#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32)
+#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L])
+#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL])
+#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH])
+#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H])
+#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL])
+#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH])
+#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32)
+#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L])
+#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL])
+#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH])
+#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H])
+#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL])
+#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH])
+#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32)
+#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L])
+#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL])
+#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH])
+#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H])
+#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL])
+#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH])
+#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32)
+#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L])
+#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL])
+#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH])
+#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H])
+#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL])
+#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH])
+#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32)
+#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L])
+#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL])
+#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH])
+#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H])
+#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL])
+#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH])
+#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32)
+#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L])
+#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL])
+#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH])
+#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H])
+#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL])
+#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH])
+#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32)
+#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L])
+#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL])
+#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH])
+#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H])
+#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL])
+#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH])
+#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32)
+#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L])
+#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL])
+#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH])
+#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H])
+#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL])
+#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH])
+#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32)
+#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L])
+#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL])
+#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH])
+#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H])
+#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL])
+#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH])
+#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32)
+#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L])
+#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL])
+#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH])
+#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H])
+#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL])
+#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH])
+#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32)
+#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L])
+#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL])
+#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH])
+#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H])
+#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL])
+#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH])
+#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32)
+#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L])
+#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL])
+#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH])
+#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H])
+#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL])
+#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH])
+#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32)
+#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L])
+#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL])
+#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH])
+#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H])
+#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL])
+#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH])
+#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32)
+#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L])
+#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL])
+#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH])
+#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H])
+#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL])
+#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH])
+#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32)
+#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L])
+#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL])
+#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH])
+#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H])
+#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL])
+#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH])
+#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32)
+#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L])
+#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL])
+#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH])
+#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H])
+#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL])
+#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH])
+#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32)
+#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L])
+#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL])
+#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH])
+#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H])
+#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL])
+#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH])
+#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32)
+#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L])
+#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL])
+#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH])
+#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H])
+#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL])
+#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH])
+#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32)
+#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L])
+#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL])
+#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH])
+#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H])
+#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL])
+#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH])
+#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32)
+#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L])
+#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL])
+#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH])
+#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H])
+#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL])
+#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH])
+#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32)
+#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L])
+#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL])
+#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH])
+#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H])
+#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL])
+#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH])
+#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32)
+#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L])
+#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL])
+#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH])
+#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H])
+#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL])
+#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH])
+#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32)
+#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L])
+#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL])
+#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH])
+#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H])
+#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL])
+#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH])
+#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32)
+#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L])
+#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL])
+#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH])
+#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H])
+#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL])
+#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH])
+#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32)
+#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L])
+#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL])
+#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH])
+#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H])
+#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL])
+#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH])
+#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32)
+#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L])
+#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL])
+#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH])
+#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H])
+#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL])
+#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH])
+#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32)
+#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L])
+#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL])
+#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH])
+#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H])
+#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL])
+#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH])
+#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32)
+#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L])
+#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL])
+#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH])
+#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H])
+#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL])
+#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH])
+#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32)
+#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L])
+#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL])
+#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH])
+#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H])
+#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL])
+#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH])
+#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32)
+#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L])
+#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL])
+#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH])
+#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H])
+#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL])
+#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH])
+#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32)
+#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L])
+#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL])
+#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH])
+#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H])
+#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL])
+#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH])
+#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32)
+#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L])
+#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL])
+#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH])
+#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H])
+#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL])
+#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH])
+#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32)
+#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L])
+#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL])
+#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH])
+#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H])
+#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL])
+#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH])
+#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32)
+#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L])
+#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL])
+#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH])
+#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H])
+#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL])
+#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH])
+#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32)
+#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L])
+#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL])
+#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH])
+#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H])
+#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL])
+#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH])
+#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32)
+#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L])
+#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL])
+#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH])
+#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H])
+#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL])
+#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH])
+#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32)
+#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L])
+#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL])
+#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH])
+#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H])
+#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL])
+#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH])
+#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32)
+#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L])
+#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL])
+#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH])
+#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H])
+#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL])
+#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH])
+#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32)
+#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L])
+#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL])
+#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH])
+#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H])
+#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL])
+#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH])
+#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32)
+#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L])
+#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL])
+#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH])
+#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H])
+#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL])
+#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH])
+#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32)
+#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L])
+#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL])
+#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH])
+#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H])
+#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL])
+#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH])
+#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32)
+#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L])
+#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL])
+#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH])
+#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H])
+#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL])
+#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH])
+#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32)
+#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L])
+#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL])
+#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH])
+#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H])
+#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL])
+#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH])
+#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32)
+#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L])
+#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL])
+#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH])
+#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H])
+#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL])
+#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH])
+#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32)
+#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L])
+#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL])
+#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH])
+#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H])
+#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL])
+#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH])
+#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32)
+#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L])
+#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL])
+#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH])
+#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H])
+#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL])
+#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH])
+#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32)
+#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L])
+#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL])
+#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH])
+#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H])
+#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL])
+#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH])
+#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32)
+#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L])
+#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL])
+#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH])
+#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H])
+#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL])
+#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH])
+#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32)
+#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L])
+#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL])
+#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH])
+#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H])
+#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL])
+#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH])
+#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32)
+#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L])
+#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL])
+#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH])
+#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H])
+#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL])
+#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH])
+#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32)
+#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L])
+#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL])
+#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH])
+#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H])
+#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL])
+#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH])
+#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32)
+#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L])
+#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL])
+#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH])
+#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H])
+#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL])
+#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH])
+#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32)
+#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L])
+#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL])
+#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH])
+#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H])
+#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL])
+#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH])
+#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32)
+#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L])
+#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL])
+#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH])
+#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H])
+#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL])
+#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH])
+#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32)
+#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L])
+#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL])
+#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH])
+#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H])
+#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL])
+#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH])
+#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32)
+#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L])
+#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL])
+#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH])
+#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H])
+#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL])
+#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH])
+#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32)
+#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L])
+#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL])
+#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH])
+#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H])
+#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL])
+#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH])
+#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32)
+#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L])
+#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL])
+#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH])
+#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H])
+#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL])
+#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH])
+#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32)
+#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L])
+#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL])
+#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH])
+#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H])
+#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL])
+#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH])
+#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32)
+#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L])
+#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL])
+#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH])
+#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H])
+#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL])
+#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH])
+#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32)
+#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L])
+#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL])
+#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH])
+#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H])
+#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL])
+#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH])
+#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32)
+#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L])
+#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL])
+#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH])
+#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H])
+#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL])
+#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH])
+#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32)
+#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L])
+#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL])
+#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH])
+#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H])
+#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL])
+#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH])
+#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32)
+#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L])
+#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL])
+#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH])
+#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H])
+#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL])
+#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH])
+#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32)
+#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L])
+#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL])
+#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH])
+#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H])
+#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL])
+#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH])
+#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32)
+#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L])
+#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL])
+#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH])
+#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H])
+#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL])
+#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH])
+#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32)
+#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L])
+#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL])
+#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH])
+#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H])
+#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL])
+#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH])
+#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32)
+#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L])
+#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL])
+#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH])
+#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H])
+#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL])
+#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH])
+#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32)
+#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L])
+#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL])
+#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH])
+#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H])
+#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL])
+#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH])
+#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32)
+#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L])
+#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL])
+#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH])
+#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H])
+#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL])
+#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH])
+#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32)
+#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L])
+#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL])
+#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH])
+#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H])
+#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL])
+#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH])
+#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32)
+#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L])
+#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL])
+#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH])
+#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H])
+#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL])
+#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH])
+#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32)
+#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L])
+#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL])
+#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH])
+#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H])
+#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL])
+#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH])
+#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32)
+#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L])
+#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL])
+#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH])
+#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H])
+#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL])
+#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH])
+#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32)
+#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L])
+#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL])
+#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH])
+#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H])
+#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL])
+#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH])
+#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32)
+#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L])
+#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL])
+#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH])
+#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H])
+#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL])
+#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH])
+#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32)
+#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L])
+#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL])
+#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH])
+#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H])
+#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL])
+#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH])
+#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32)
+#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L])
+#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL])
+#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH])
+#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H])
+#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL])
+#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH])
+#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32)
+#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L])
+#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL])
+#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH])
+#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H])
+#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL])
+#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH])
+#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32)
+#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L])
+#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL])
+#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH])
+#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H])
+#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL])
+#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH])
+#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32)
+#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L])
+#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL])
+#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH])
+#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H])
+#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL])
+#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH])
+#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32)
+#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L])
+#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL])
+#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH])
+#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H])
+#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL])
+#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH])
+#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32)
+#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L])
+#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL])
+#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH])
+#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H])
+#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL])
+#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH])
+#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32)
+#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L])
+#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL])
+#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH])
+#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H])
+#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL])
+#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH])
+#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32)
+#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L])
+#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL])
+#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH])
+#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H])
+#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL])
+#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH])
+#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32)
+#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L])
+#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL])
+#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH])
+#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H])
+#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL])
+#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH])
+#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32)
+#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L])
+#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL])
+#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH])
+#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H])
+#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL])
+#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH])
+#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32)
+#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L])
+#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL])
+#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH])
+#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H])
+#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL])
+#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH])
+#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32)
+#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L])
+#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL])
+#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH])
+#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H])
+#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL])
+#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH])
+#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32)
+#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L])
+#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL])
+#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH])
+#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H])
+#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL])
+#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH])
+#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32)
+#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L])
+#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL])
+#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH])
+#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H])
+#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL])
+#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH])
+#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32)
+#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L])
+#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL])
+#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH])
+#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H])
+#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL])
+#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH])
+#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32)
+#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L])
+#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL])
+#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH])
+#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H])
+#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL])
+#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH])
+#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32)
+#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L])
+#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL])
+#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH])
+#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H])
+#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL])
+#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH])
+#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32)
+#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L])
+#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL])
+#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH])
+#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H])
+#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL])
+#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH])
+#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32)
+#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L])
+#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL])
+#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH])
+#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H])
+#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL])
+#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH])
+#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32)
+#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L])
+#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL])
+#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH])
+#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H])
+#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL])
+#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH])
+#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32)
+#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L])
+#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL])
+#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH])
+#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H])
+#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL])
+#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH])
+#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32)
+#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L])
+#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL])
+#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH])
+#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H])
+#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL])
+#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH])
+#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32)
+#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L])
+#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL])
+#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH])
+#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H])
+#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL])
+#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH])
+#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32)
+#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L])
+#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL])
+#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH])
+#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H])
+#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL])
+#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH])
+#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32)
+#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L])
+#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL])
+#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH])
+#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H])
+#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL])
+#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH])
+#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32)
+#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L])
+#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL])
+#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH])
+#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H])
+#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL])
+#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH])
+#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32)
+#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L])
+#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL])
+#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH])
+#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H])
+#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL])
+#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH])
+#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32)
+#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L])
+#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL])
+#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH])
+#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H])
+#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL])
+#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH])
+#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32)
+#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L])
+#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL])
+#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH])
+#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H])
+#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL])
+#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH])
+#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32)
+#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L])
+#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL])
+#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH])
+#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H])
+#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL])
+#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH])
+#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32)
+#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L])
+#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL])
+#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH])
+#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H])
+#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL])
+#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH])
+#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32)
+#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L])
+#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL])
+#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH])
+#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H])
+#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL])
+#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH])
+#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32)
+#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L])
+#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL])
+#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH])
+#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H])
+#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL])
+#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH])
+#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32)
+#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L])
+#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL])
+#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH])
+#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H])
+#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL])
+#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH])
+#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32)
+#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L])
+#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL])
+#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH])
+#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H])
+#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL])
+#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH])
+#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32)
+#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L])
+#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL])
+#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH])
+#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H])
+#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL])
+#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH])
+#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32)
+#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L])
+#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL])
+#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH])
+#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H])
+#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL])
+#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH])
+#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32)
+#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L])
+#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL])
+#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH])
+#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H])
+#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL])
+#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH])
+#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32)
+#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L])
+#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL])
+#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH])
+#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H])
+#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL])
+#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH])
+#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32)
+#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L])
+#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL])
+#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH])
+#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H])
+#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL])
+#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH])
+#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32)
+#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L])
+#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL])
+#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH])
+#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H])
+#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL])
+#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH])
+#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32)
+#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L])
+#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL])
+#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH])
+#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H])
+#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL])
+#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH])
+#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32)
+#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L])
+#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL])
+#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH])
+#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H])
+#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL])
+#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH])
+#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32)
+#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L])
+#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL])
+#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH])
+#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H])
+#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL])
+#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH])
+#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32)
+#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L])
+#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL])
+#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH])
+#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H])
+#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL])
+#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH])
+#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32)
+#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L])
+#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL])
+#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH])
+#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H])
+#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL])
+#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH])
+#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32)
+#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L])
+#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL])
+#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH])
+#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H])
+#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL])
+#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH])
+#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32)
+#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L])
+#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL])
+#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH])
+#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H])
+#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL])
+#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH])
+#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32)
+#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L])
+#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL])
+#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH])
+#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H])
+#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL])
+#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH])
+#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32)
+#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L])
+#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL])
+#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH])
+#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H])
+#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL])
+#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH])
+#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32)
+#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L])
+#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL])
+#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH])
+#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H])
+#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL])
+#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH])
+#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32)
+#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L])
+#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL])
+#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH])
+#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H])
+#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL])
+#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH])
+#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32)
+#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L])
+#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL])
+#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH])
+#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H])
+#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL])
+#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH])
+#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32)
+#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L])
+#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL])
+#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH])
+#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H])
+#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL])
+#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH])
+#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32)
+#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L])
+#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL])
+#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH])
+#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H])
+#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL])
+#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH])
+#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32)
+#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L])
+#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL])
+#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH])
+#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H])
+#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL])
+#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH])
+#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32)
+#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L])
+#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL])
+#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH])
+#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H])
+#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL])
+#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH])
+#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32)
+#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L])
+#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL])
+#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH])
+#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H])
+#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL])
+#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH])
+#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32)
+#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L])
+#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL])
+#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH])
+#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H])
+#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL])
+#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH])
+#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32)
+#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L])
+#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL])
+#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH])
+#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H])
+#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL])
+#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH])
+#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32)
+#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L])
+#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL])
+#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH])
+#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H])
+#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL])
+#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH])
+#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32)
+#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L])
+#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL])
+#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH])
+#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H])
+#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL])
+#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH])
+#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32)
+#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L])
+#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL])
+#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH])
+#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H])
+#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL])
+#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH])
+#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32)
+#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L])
+#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL])
+#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH])
+#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H])
+#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL])
+#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH])
+#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32)
+#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L])
+#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL])
+#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH])
+#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H])
+#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL])
+#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH])
+#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32)
+#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L])
+#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL])
+#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH])
+#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H])
+#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL])
+#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH])
+#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32)
+#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L])
+#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL])
+#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH])
+#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H])
+#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL])
+#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH])
+#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32)
+#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L])
+#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL])
+#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH])
+#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H])
+#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL])
+#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH])
+#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32)
+#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L])
+#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL])
+#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH])
+#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H])
+#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL])
+#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH])
+#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32)
+#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L])
+#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL])
+#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH])
+#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H])
+#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL])
+#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH])
+#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32)
+#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L])
+#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL])
+#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH])
+#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H])
+#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL])
+#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH])
+#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32)
+#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L])
+#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL])
+#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH])
+#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H])
+#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL])
+#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH])
+#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32)
+#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L])
+#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL])
+#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH])
+#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H])
+#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL])
+#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH])
+#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32)
+#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L])
+#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL])
+#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH])
+#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H])
+#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL])
+#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH])
+#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32)
+#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L])
+#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL])
+#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH])
+#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H])
+#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL])
+#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH])
+#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32)
+#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L])
+#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL])
+#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH])
+#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H])
+#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL])
+#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH])
+#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32)
+#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L])
+#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL])
+#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH])
+#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H])
+#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL])
+#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH])
+#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32)
+#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L])
+#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL])
+#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH])
+#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H])
+#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL])
+#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH])
+#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32)
+#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L])
+#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL])
+#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH])
+#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H])
+#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL])
+#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH])
+#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32)
+#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L])
+#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL])
+#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH])
+#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H])
+#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL])
+#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH])
+#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32)
+#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L])
+#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL])
+#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH])
+#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H])
+#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL])
+#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH])
+#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32)
+#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L])
+#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL])
+#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH])
+#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H])
+#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL])
+#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH])
+#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32)
+#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L])
+#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL])
+#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH])
+#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H])
+#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL])
+#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH])
+#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32)
+#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L])
+#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL])
+#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH])
+#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H])
+#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL])
+#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH])
+#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32)
+#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L])
+#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL])
+#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH])
+#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H])
+#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL])
+#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH])
+#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32)
+#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L])
+#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL])
+#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH])
+#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H])
+#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL])
+#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH])
+#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32)
+#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L])
+#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL])
+#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH])
+#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H])
+#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL])
+#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH])
+#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32)
+#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L])
+#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL])
+#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH])
+#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H])
+#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL])
+#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH])
+#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32)
+#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L])
+#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL])
+#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH])
+#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H])
+#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL])
+#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH])
+#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32)
+#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L])
+#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL])
+#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH])
+#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H])
+#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL])
+#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH])
+#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32)
+#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L])
+#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL])
+#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH])
+#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H])
+#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL])
+#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH])
+#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32)
+#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L])
+#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL])
+#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH])
+#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H])
+#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL])
+#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH])
+#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32)
+#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L])
+#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL])
+#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH])
+#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H])
+#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL])
+#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH])
+#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32)
+#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L])
+#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL])
+#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH])
+#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H])
+#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL])
+#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH])
+#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32)
+#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L])
+#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL])
+#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH])
+#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H])
+#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL])
+#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH])
+#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32)
+#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L])
+#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL])
+#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH])
+#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H])
+#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL])
+#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH])
+#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32)
+#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L])
+#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL])
+#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH])
+#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H])
+#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL])
+#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH])
+#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32)
+#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L])
+#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL])
+#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH])
+#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H])
+#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL])
+#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH])
+#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32)
+#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L])
+#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL])
+#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH])
+#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H])
+#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL])
+#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH])
+#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32)
+#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L])
+#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL])
+#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH])
+#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H])
+#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL])
+#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH])
+#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32)
+#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L])
+#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL])
+#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH])
+#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H])
+#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL])
+#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH])
+#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32)
+#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L])
+#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL])
+#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH])
+#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H])
+#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL])
+#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH])
+#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32)
+#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L])
+#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL])
+#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH])
+#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H])
+#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL])
+#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH])
+#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32)
+#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L])
+#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL])
+#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH])
+#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H])
+#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL])
+#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH])
+#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32)
+#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L])
+#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL])
+#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH])
+#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H])
+#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL])
+#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH])
+#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32)
+#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L])
+#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL])
+#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH])
+#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H])
+#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL])
+#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH])
+#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32)
+#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L])
+#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL])
+#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH])
+#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H])
+#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL])
+#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH])
+#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32)
+#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L])
+#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL])
+#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH])
+#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H])
+#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL])
+#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH])
+#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32)
+#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L])
+#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL])
+#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH])
+#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H])
+#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL])
+#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH])
+#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32)
+#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L])
+#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL])
+#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH])
+#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H])
+#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL])
+#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH])
+#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32)
+#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L])
+#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL])
+#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH])
+#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H])
+#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL])
+#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH])
+#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32)
+#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L])
+#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL])
+#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH])
+#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H])
+#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL])
+#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH])
+#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32)
+#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L])
+#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL])
+#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH])
+#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H])
+#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL])
+#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH])
+#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32)
+#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L])
+#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL])
+#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH])
+#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H])
+#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL])
+#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH])
+#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32)
+#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L])
+#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL])
+#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH])
+#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H])
+#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL])
+#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH])
+#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32)
+#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L])
+#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL])
+#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH])
+#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H])
+#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL])
+#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH])
+#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32)
+#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L])
+#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL])
+#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH])
+#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H])
+#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL])
+#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH])
+#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32)
+#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L])
+#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL])
+#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH])
+#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H])
+#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL])
+#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH])
+#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32)
+#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L])
+#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL])
+#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH])
+#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H])
+#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL])
+#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH])
+#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32)
+#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L])
+#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL])
+#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH])
+#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H])
+#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL])
+#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH])
+#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32)
+#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L])
+#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL])
+#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH])
+#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H])
+#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL])
+#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH])
+#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32)
+#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L])
+#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL])
+#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH])
+#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H])
+#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL])
+#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH])
+#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32)
+#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L])
+#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL])
+#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH])
+#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H])
+#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL])
+#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH])
+#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32)
+#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L])
+#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL])
+#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH])
+#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H])
+#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL])
+#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH])
+#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32)
+#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L])
+#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL])
+#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH])
+#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H])
+#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL])
+#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH])
+#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32)
+#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L])
+#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL])
+#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH])
+#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H])
+#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL])
+#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH])
+#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32)
+#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L])
+#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL])
+#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH])
+#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H])
+#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL])
+#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH])
+#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32)
+#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L])
+#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL])
+#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH])
+#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H])
+#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL])
+#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH])
+#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32)
+#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L])
+#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL])
+#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH])
+#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H])
+#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL])
+#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH])
+#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32)
+#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L])
+#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL])
+#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH])
+#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H])
+#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL])
+#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH])
+#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32)
+#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L])
+#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL])
+#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH])
+#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H])
+#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL])
+#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH])
+#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32)
+#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L])
+#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL])
+#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH])
+#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H])
+#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL])
+#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH])
+#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32)
+#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L])
+#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL])
+#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH])
+#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H])
+#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL])
+#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH])
+#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32)
+#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L])
+#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL])
+#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH])
+#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H])
+#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL])
+#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH])
+#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32)
+#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L])
+#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL])
+#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH])
+#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H])
+#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL])
+#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH])
+#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32)
+#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L])
+#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL])
+#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH])
+#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H])
+#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL])
+#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH])
+#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32)
+#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L])
+#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL])
+#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH])
+#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H])
+#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL])
+#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH])
+#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32)
+#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L])
+#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL])
+#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH])
+#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H])
+#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL])
+#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH])
+#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32)
+#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L])
+#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL])
+#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH])
+#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H])
+#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL])
+#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH])
+#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32)
+#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L])
+#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL])
+#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH])
+#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H])
+#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL])
+#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH])
+#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32)
+#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L])
+#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL])
+#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH])
+#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H])
+#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL])
+#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH])
+#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32)
+#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L])
+#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL])
+#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH])
+#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H])
+#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL])
+#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH])
+#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32)
+#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L])
+#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL])
+#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH])
+#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H])
+#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL])
+#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH])
+#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32)
+#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L])
+#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL])
+#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH])
+#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H])
+#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL])
+#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH])
+#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32)
+#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L])
+#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL])
+#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH])
+#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H])
+#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL])
+#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH])
+#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32)
+#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L])
+#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL])
+#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH])
+#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H])
+#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL])
+#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH])
+#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32)
+#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L])
+#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL])
+#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH])
+#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H])
+#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL])
+#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH])
+#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32)
+#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L])
+#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL])
+#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH])
+#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H])
+#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL])
+#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH])
+#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32)
+#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L])
+#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL])
+#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH])
+#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H])
+#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL])
+#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH])
+#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32)
+#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L])
+#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL])
+#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH])
+#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H])
+#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL])
+#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH])
+#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32)
+#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L])
+#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL])
+#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH])
+#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H])
+#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL])
+#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH])
+#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32)
+#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L])
+#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL])
+#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH])
+#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H])
+#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL])
+#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH])
+#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32)
+#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L])
+#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL])
+#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH])
+#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H])
+#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL])
+#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH])
+#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32)
+#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L])
+#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL])
+#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH])
+#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H])
+#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL])
+#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH])
+#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32)
+#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L])
+#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL])
+#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH])
+#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H])
+#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL])
+#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH])
+#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32)
+#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L])
+#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL])
+#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH])
+#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H])
+#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL])
+#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH])
+#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32)
+#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L])
+#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL])
+#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH])
+#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H])
+#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL])
+#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH])
+#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32)
+#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L])
+#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL])
+#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH])
+#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H])
+#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL])
+#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH])
+#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32)
+#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L])
+#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL])
+#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH])
+#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H])
+#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL])
+#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH])
+#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32)
+#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L])
+#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL])
+#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH])
+#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H])
+#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL])
+#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH])
+#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32)
+#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L])
+#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL])
+#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH])
+#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H])
+#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL])
+#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH])
+#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32)
+#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L])
+#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL])
+#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH])
+#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H])
+#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL])
+#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH])
+#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32)
+#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L])
+#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL])
+#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH])
+#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H])
+#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL])
+#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH])
+#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32)
+#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L])
+#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL])
+#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH])
+#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H])
+#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL])
+#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH])
+#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32)
+#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L])
+#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL])
+#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH])
+#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H])
+#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL])
+#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH])
+#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32)
+#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L])
+#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL])
+#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH])
+#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H])
+#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL])
+#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH])
+#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32)
+#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L])
+#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL])
+#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH])
+#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H])
+#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL])
+#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH])
+#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32)
+#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L])
+#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL])
+#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH])
+#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H])
+#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL])
+#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH])
+#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32)
+#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L])
+#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL])
+#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH])
+#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H])
+#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL])
+#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH])
+#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32)
+#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L])
+#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL])
+#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH])
+#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H])
+#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL])
+#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH])
+#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32)
+#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L])
+#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL])
+#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH])
+#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H])
+#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL])
+#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH])
+#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32)
+#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L])
+#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL])
+#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH])
+#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H])
+#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL])
+#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH])
+#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32)
+#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L])
+#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL])
+#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH])
+#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H])
+#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL])
+#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH])
+#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32)
+#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L])
+#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL])
+#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH])
+#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H])
+#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL])
+#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH])
+#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32)
+#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L])
+#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL])
+#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH])
+#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H])
+#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL])
+#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH])
+#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32)
+#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L])
+#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL])
+#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH])
+#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H])
+#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL])
+#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH])
+#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32)
+#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L])
+#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL])
+#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH])
+#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H])
+#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL])
+#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH])
+#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32)
+#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L])
+#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL])
+#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH])
+#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H])
+#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL])
+#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH])
+#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32)
+#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L])
+#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL])
+#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH])
+#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H])
+#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL])
+#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH])
+#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32)
+#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L])
+#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL])
+#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH])
+#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H])
+#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL])
+#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH])
+#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32)
+#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L])
+#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL])
+#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH])
+#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H])
+#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL])
+#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH])
+#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32)
+#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L])
+#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL])
+#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH])
+#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H])
+#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL])
+#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH])
+#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32)
+#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L])
+#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL])
+#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH])
+#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H])
+#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL])
+#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH])
+#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32)
+#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L])
+#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL])
+#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH])
+#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H])
+#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL])
+#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH])
+#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32)
+#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L])
+#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL])
+#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH])
+#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H])
+#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL])
+#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH])
+#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32)
+#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L])
+#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL])
+#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH])
+#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H])
+#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL])
+#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH])
+#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32)
+#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L])
+#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL])
+#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH])
+#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H])
+#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL])
+#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH])
+#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32)
+#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L])
+#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL])
+#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH])
+#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H])
+#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL])
+#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH])
+#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32)
+#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L])
+#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL])
+#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH])
+#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H])
+#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL])
+#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH])
+#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32)
+#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L])
+#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL])
+#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH])
+#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H])
+#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL])
+#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH])
+#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32)
+#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L])
+#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL])
+#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH])
+#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H])
+#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL])
+#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH])
+#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32)
+#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L])
+#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL])
+#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH])
+#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H])
+#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL])
+#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH])
+#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32)
+#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L])
+#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL])
+#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH])
+#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H])
+#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL])
+#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH])
+#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32)
+#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L])
+#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL])
+#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH])
+#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H])
+#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL])
+#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH])
+#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32)
+#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L])
+#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL])
+#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH])
+#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H])
+#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL])
+#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH])
+#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32)
+#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L])
+#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL])
+#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH])
+#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H])
+#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL])
+#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH])
+#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32)
+#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L])
+#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL])
+#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH])
+#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H])
+#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL])
+#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH])
+#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32)
+#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L])
+#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL])
+#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH])
+#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H])
+#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL])
+#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH])
+#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32)
+#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L])
+#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL])
+#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH])
+#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H])
+#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL])
+#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH])
+#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32)
+#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L])
+#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL])
+#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH])
+#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H])
+#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL])
+#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH])
+#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32)
+#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L])
+#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL])
+#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH])
+#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H])
+#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL])
+#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH])
+#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32)
+#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L])
+#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL])
+#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH])
+#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H])
+#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL])
+#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH])
+#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32)
+#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L])
+#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL])
+#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH])
+#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H])
+#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL])
+#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH])
+#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32)
+#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L])
+#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL])
+#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH])
+#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H])
+#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL])
+#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH])
+#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32)
+#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L])
+#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL])
+#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH])
+#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H])
+#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL])
+#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH])
+#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32)
+#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L])
+#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL])
+#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH])
+#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H])
+#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL])
+#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH])
+#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32)
+#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L])
+#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL])
+#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH])
+#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H])
+#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL])
+#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH])
+#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32)
+#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L])
+#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL])
+#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH])
+#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H])
+#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL])
+#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH])
+#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32)
+#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L])
+#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL])
+#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH])
+#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H])
+#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL])
+#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH])
+#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32)
+#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L])
+#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL])
+#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH])
+#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H])
+#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL])
+#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH])
+#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32)
+#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L])
+#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL])
+#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH])
+#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H])
+#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL])
+#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH])
+#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32)
+#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L])
+#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL])
+#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH])
+#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H])
+#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL])
+#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH])
+#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32)
+#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L])
+#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL])
+#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH])
+#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H])
+#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL])
+#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH])
+#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32)
+#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L])
+#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL])
+#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH])
+#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H])
+#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL])
+#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH])
+#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32)
+#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L])
+#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL])
+#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH])
+#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H])
+#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL])
+#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH])
+#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32)
+#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L])
+#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL])
+#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH])
+#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H])
+#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL])
+#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH])
+#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32)
+#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L])
+#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL])
+#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH])
+#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H])
+#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL])
+#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH])
+#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32)
+#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L])
+#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL])
+#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH])
+#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H])
+#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL])
+#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH])
+#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32)
+#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L])
+#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL])
+#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH])
+#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H])
+#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL])
+#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH])
+#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32)
+#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L])
+#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL])
+#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH])
+#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H])
+#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL])
+#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH])
+#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32)
+#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L])
+#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL])
+#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH])
+#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H])
+#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL])
+#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH])
+#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32)
+#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L])
+#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL])
+#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH])
+#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H])
+#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL])
+#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH])
+#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32)
+#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L])
+#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL])
+#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH])
+#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H])
+#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL])
+#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH])
+#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32)
+#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L])
+#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL])
+#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH])
+#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H])
+#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL])
+#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH])
+#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32)
+#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L])
+#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL])
+#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH])
+#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H])
+#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL])
+#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH])
+#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32)
+#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L])
+#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL])
+#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH])
+#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H])
+#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL])
+#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH])
+#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32)
+#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L])
+#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL])
+#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH])
+#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H])
+#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL])
+#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH])
+#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32)
+#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L])
+#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL])
+#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH])
+#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H])
+#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL])
+#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH])
+#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32)
+#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L])
+#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL])
+#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH])
+#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H])
+#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL])
+#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH])
+#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32)
+#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L])
+#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL])
+#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH])
+#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H])
+#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL])
+#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH])
+#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32)
+#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L])
+#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL])
+#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH])
+#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H])
+#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL])
+#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH])
+#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32)
+#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L])
+#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL])
+#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH])
+#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H])
+#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL])
+#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH])
+#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32)
+#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L])
+#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL])
+#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH])
+#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H])
+#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL])
+#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH])
+#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32)
+#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L])
+#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL])
+#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH])
+#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H])
+#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL])
+#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH])
+#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32)
+#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L])
+#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL])
+#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH])
+#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H])
+#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL])
+#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH])
+#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32)
+#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L])
+#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL])
+#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH])
+#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H])
+#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL])
+#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH])
+#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32)
+#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L])
+#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL])
+#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH])
+#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H])
+#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL])
+#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH])
+#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32)
+#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L])
+#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL])
+#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH])
+#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H])
+#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL])
+#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH])
+#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32)
+#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L])
+#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL])
+#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH])
+#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H])
+#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL])
+#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH])
+#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32)
+#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L])
+#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL])
+#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH])
+#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H])
+#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL])
+#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH])
+#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32)
+#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L])
+#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL])
+#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH])
+#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H])
+#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL])
+#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH])
+#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32)
+#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L])
+#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL])
+#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH])
+#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H])
+#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL])
+#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH])
+#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32)
+#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L])
+#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL])
+#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH])
+#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H])
+#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL])
+#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH])
+#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32)
+#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L])
+#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL])
+#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH])
+#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H])
+#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL])
+#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH])
+#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32)
+#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L])
+#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL])
+#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH])
+#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H])
+#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL])
+#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH])
+#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32)
+#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L])
+#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL])
+#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH])
+#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H])
+#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL])
+#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH])
+#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32)
+#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L])
+#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL])
+#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH])
+#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H])
+#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL])
+#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH])
+#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32)
+#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L])
+#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL])
+#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH])
+#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H])
+#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL])
+#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH])
+#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32)
+#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L])
+#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL])
+#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH])
+#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H])
+#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL])
+#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH])
+#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32)
+#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L])
+#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL])
+#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH])
+#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H])
+#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL])
+#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH])
+#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32)
+#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L])
+#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL])
+#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH])
+#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H])
+#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL])
+#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH])
+#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32)
+#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L])
+#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL])
+#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH])
+#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H])
+#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL])
+#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH])
+#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32)
+#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L])
+#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL])
+#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH])
+#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H])
+#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL])
+#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH])
+#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32)
+#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L])
+#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL])
+#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH])
+#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H])
+#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL])
+#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH])
+#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32)
+#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L])
+#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL])
+#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH])
+#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H])
+#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL])
+#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH])
+#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32)
+#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L])
+#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL])
+#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH])
+#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H])
+#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL])
+#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH])
+#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32)
+#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L])
+#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL])
+#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH])
+#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H])
+#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL])
+#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH])
+#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32)
+#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L])
+#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL])
+#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH])
+#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H])
+#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL])
+#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH])
+#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32)
+#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L])
+#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL])
+#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH])
+#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H])
+#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL])
+#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH])
+#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32)
+#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L])
+#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL])
+#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH])
+#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H])
+#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL])
+#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH])
+#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32)
+#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L])
+#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL])
+#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH])
+#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H])
+#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL])
+#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH])
+#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32)
+#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L])
+#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL])
+#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH])
+#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H])
+#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL])
+#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH])
+#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32)
+#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L])
+#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL])
+#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH])
+#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H])
+#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL])
+#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH])
+#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32)
+#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L])
+#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL])
+#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH])
+#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H])
+#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL])
+#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH])
+#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32)
+#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L])
+#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL])
+#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH])
+#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H])
+#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL])
+#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH])
+#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32)
+#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L])
+#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL])
+#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH])
+#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H])
+#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL])
+#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH])
+#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32)
+#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L])
+#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL])
+#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH])
+#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H])
+#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL])
+#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH])
+#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32)
+#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L])
+#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL])
+#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH])
+#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H])
+#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL])
+#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH])
+#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32)
+#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L])
+#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL])
+#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH])
+#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H])
+#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL])
+#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH])
+#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32)
+#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L])
+#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL])
+#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH])
+#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H])
+#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL])
+#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH])
+#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32)
+#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L])
+#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL])
+#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH])
+#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H])
+#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL])
+#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH])
+#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32)
+#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L])
+#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL])
+#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH])
+#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H])
+#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL])
+#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH])
+#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32)
+#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L])
+#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL])
+#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH])
+#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H])
+#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL])
+#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH])
+#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32)
+#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L])
+#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL])
+#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH])
+#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H])
+#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL])
+#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH])
+#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32)
+#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L])
+#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL])
+#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH])
+#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H])
+#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL])
+#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH])
+#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32)
+#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L])
+#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL])
+#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH])
+#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H])
+#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL])
+#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH])
+#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32)
+#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L])
+#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL])
+#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH])
+#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H])
+#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL])
+#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH])
+#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32)
+#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L])
+#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL])
+#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH])
+#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H])
+#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL])
+#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH])
+#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32)
+#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L])
+#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL])
+#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH])
+#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H])
+#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL])
+#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH])
+#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32)
+#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L])
+#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL])
+#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH])
+#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H])
+#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL])
+#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH])
+#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32)
+#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L])
+#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL])
+#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH])
+#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H])
+#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL])
+#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH])
+#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32)
+#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L])
+#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL])
+#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH])
+#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H])
+#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL])
+#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH])
+#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32)
+#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L])
+#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL])
+#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH])
+#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H])
+#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL])
+#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH])
+#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32)
+#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L])
+#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL])
+#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH])
+#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H])
+#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL])
+#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH])
+#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32)
+#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L])
+#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL])
+#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH])
+#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H])
+#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL])
+#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH])
+#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32)
+#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L])
+#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL])
+#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH])
+#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H])
+#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL])
+#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH])
+#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32)
+#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L])
+#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL])
+#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH])
+#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H])
+#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL])
+#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH])
+#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32)
+#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L])
+#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL])
+#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH])
+#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H])
+#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL])
+#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH])
+#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32)
+#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L])
+#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL])
+#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH])
+#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H])
+#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL])
+#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH])
+#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32)
+#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L])
+#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL])
+#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH])
+#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H])
+#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL])
+#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH])
+#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32)
+#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L])
+#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL])
+#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH])
+#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H])
+#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL])
+#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH])
+#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32)
+#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L])
+#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL])
+#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH])
+#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H])
+#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL])
+#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH])
+#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32)
+#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L])
+#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL])
+#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH])
+#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H])
+#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL])
+#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH])
+#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32)
+#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L])
+#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL])
+#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH])
+#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H])
+#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL])
+#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH])
+#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32)
+#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L])
+#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL])
+#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH])
+#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H])
+#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL])
+#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH])
+#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32)
+#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L])
+#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL])
+#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH])
+#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H])
+#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL])
+#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH])
+#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32)
+#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L])
+#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL])
+#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH])
+#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H])
+#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL])
+#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH])
+#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32)
+#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L])
+#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL])
+#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH])
+#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H])
+#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL])
+#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH])
+#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32)
+#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L])
+#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL])
+#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH])
+#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H])
+#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL])
+#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH])
+#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32)
+#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L])
+#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL])
+#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH])
+#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H])
+#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL])
+#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH])
+#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32)
+#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L])
+#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL])
+#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH])
+#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H])
+#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL])
+#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH])
+#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32)
+#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L])
+#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL])
+#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH])
+#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H])
+#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL])
+#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH])
+#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32)
+#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L])
+#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL])
+#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH])
+#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H])
+#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL])
+#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH])
+#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32)
+#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L])
+#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL])
+#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH])
+#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H])
+#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL])
+#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH])
+#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32)
+#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L])
+#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL])
+#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH])
+#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H])
+#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL])
+#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH])
+#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32)
+#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L])
+#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL])
+#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH])
+#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H])
+#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL])
+#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH])
+#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32)
+#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L])
+#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL])
+#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH])
+#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H])
+#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL])
+#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH])
+#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32)
+#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L])
+#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL])
+#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH])
+#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H])
+#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL])
+#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH])
+#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32)
+#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L])
+#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL])
+#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH])
+#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H])
+#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL])
+#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH])
+#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32)
+#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L])
+#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL])
+#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH])
+#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H])
+#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL])
+#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH])
+#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32)
+#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L])
+#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL])
+#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH])
+#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H])
+#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL])
+#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH])
+#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32)
+#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L])
+#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL])
+#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH])
+#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H])
+#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL])
+#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH])
+#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32)
+#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L])
+#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL])
+#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH])
+#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H])
+#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL])
+#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH])
+#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32)
+#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L])
+#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL])
+#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH])
+#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H])
+#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL])
+#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH])
+#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32)
+#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L])
+#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL])
+#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH])
+#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H])
+#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL])
+#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH])
+#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32)
+#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L])
+#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL])
+#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH])
+#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H])
+#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL])
+#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH])
+#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32)
+#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L])
+#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL])
+#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH])
+#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H])
+#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL])
+#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH])
+#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32)
+#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L])
+#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL])
+#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH])
+#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H])
+#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL])
+#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH])
+#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32)
+#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L])
+#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL])
+#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH])
+#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H])
+#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL])
+#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH])
+#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32)
+#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L])
+#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL])
+#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH])
+#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H])
+#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL])
+#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH])
+#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32)
+#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L])
+#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL])
+#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH])
+#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H])
+#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL])
+#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH])
+#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32)
+#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L])
+#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL])
+#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH])
+#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H])
+#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL])
+#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH])
+#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32)
+#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L])
+#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL])
+#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH])
+#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H])
+#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL])
+#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH])
+#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32)
+#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L])
+#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL])
+#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH])
+#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H])
+#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL])
+#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH])
+#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32)
+#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L])
+#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL])
+#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH])
+#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H])
+#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL])
+#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH])
+#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32)
+#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L])
+#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL])
+#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH])
+#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H])
+#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL])
+#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH])
+#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32)
+#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L])
+#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL])
+#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH])
+#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H])
+#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL])
+#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH])
+#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32)
+#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L])
+#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL])
+#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH])
+#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H])
+#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL])
+#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH])
+#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32)
+#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L])
+#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL])
+#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH])
+#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H])
+#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL])
+#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH])
+#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32)
+#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L])
+#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL])
+#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH])
+#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H])
+#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL])
+#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH])
+#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32)
+#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L])
+#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL])
+#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH])
+#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H])
+#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL])
+#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH])
+#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32)
+#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L])
+#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL])
+#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH])
+#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H])
+#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL])
+#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH])
+#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32)
+#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L])
+#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL])
+#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH])
+#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H])
+#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL])
+#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH])
+#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32)
+#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L])
+#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL])
+#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH])
+#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H])
+#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL])
+#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH])
+#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32)
+#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L])
+#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL])
+#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH])
+#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H])
+#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL])
+#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH])
+#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32)
+#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L])
+#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL])
+#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH])
+#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H])
+#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL])
+#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH])
+#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32)
+#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L])
+#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL])
+#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH])
+#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H])
+#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL])
+#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH])
+#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32)
+#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L])
+#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL])
+#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH])
+#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H])
+#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL])
+#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH])
+#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32)
+#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L])
+#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL])
+#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH])
+#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H])
+#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL])
+#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH])
+#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32)
+#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L])
+#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL])
+#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH])
+#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H])
+#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL])
+#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH])
+#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32)
+#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L])
+#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL])
+#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH])
+#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H])
+#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL])
+#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH])
+#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32)
+#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L])
+#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL])
+#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH])
+#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H])
+#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL])
+#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH])
+#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32)
+#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L])
+#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL])
+#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH])
+#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H])
+#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL])
+#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH])
+#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32)
+#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L])
+#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL])
+#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH])
+#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H])
+#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL])
+#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH])
+#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32)
+#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L])
+#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL])
+#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH])
+#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H])
+#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL])
+#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH])
+#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32)
+#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L])
+#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL])
+#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH])
+#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H])
+#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL])
+#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH])
+#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32)
+#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L])
+#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL])
+#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH])
+#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H])
+#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL])
+#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH])
+#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32)
+#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L])
+#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL])
+#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH])
+#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H])
+#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL])
+#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH])
+#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32)
+#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L])
+#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL])
+#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH])
+#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H])
+#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL])
+#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH])
+#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32)
+#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L])
+#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL])
+#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH])
+#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H])
+#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL])
+#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH])
+#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32)
+#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L])
+#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL])
+#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH])
+#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H])
+#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL])
+#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH])
+#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32)
+#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L])
+#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL])
+#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH])
+#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H])
+#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL])
+#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH])
+#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32)
+#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L])
+#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL])
+#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH])
+#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H])
+#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL])
+#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH])
+#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32)
+#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L])
+#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL])
+#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH])
+#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H])
+#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL])
+#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH])
+#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32)
+#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L])
+#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL])
+#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH])
+#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H])
+#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL])
+#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH])
+#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32)
+#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L])
+#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL])
+#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH])
+#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H])
+#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL])
+#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH])
+#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32)
+#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L])
+#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL])
+#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH])
+#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H])
+#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL])
+#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH])
+
+#define RSCAN0_GAFLCFG0_COUNT (2)
+#define RSCAN0_RMND0_COUNT (3)
+#define RSCAN0_RFCC0_COUNT (8)
+#define RSCAN0_RFSTS0_COUNT (8)
+#define RSCAN0_RFPCTR0_COUNT (8)
+#define RSCAN0_CFCC0_COUNT (15)
+#define RSCAN0_CFSTS0_COUNT (15)
+#define RSCAN0_CFPCTR0_COUNT (15)
+#define RSCAN0_TMC0_COUNT (80)
+#define RSCAN0_TMSTS0_COUNT (80)
+#define RSCAN0_TMTRSTS0_COUNT (3)
+#define RSCAN0_TMTARSTS0_COUNT (3)
+#define RSCAN0_TMTCSTS0_COUNT (3)
+#define RSCAN0_TMTASTS0_COUNT (3)
+#define RSCAN0_TMIEC0_COUNT (3)
+#define RSCAN0_TXQCC0_COUNT (5)
+#define RSCAN0_TXQSTS0_COUNT (5)
+#define RSCAN0_TXQPCTR0_COUNT (5)
+#define RSCAN0_THLCC0_COUNT (5)
+#define RSCAN0_THLSTS0_COUNT (5)
+#define RSCAN0_THLPCTR0_COUNT (5)
+#define RSCAN0_GTINTSTS0_COUNT (2)
+#define RSCAN0_THLACC0_COUNT (5)
+
+
+typedef struct st_rscan0
+{
+                                                           /* RSCAN0           */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
+    union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
+    union iodefine_reg32_t  C0STS;                         /*  C0STS           */
+    union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
+    union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
+    union iodefine_reg32_t  C1STS;                         /*  C1STS           */
+    union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
+    union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
+    union iodefine_reg32_t  C2STS;                         /*  C2STS           */
+    union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
+    union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
+    union iodefine_reg32_t  C3STS;                         /*  C3STS           */
+    union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
+    union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
+    union iodefine_reg32_t  C4STS;                         /*  C4STS           */
+    union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+    volatile uint8_t   dummy159[52];                           /*                  */
+    union iodefine_reg32_t  GCFG;                          /*  GCFG            */
+    union iodefine_reg32_t  GCTR;                          /*  GCTR            */
+    union iodefine_reg32_t  GSTS;                          /*  GSTS            */
+    union iodefine_reg32_t  GERFL;                         /*  GERFL           */
+    union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
+    union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
+
+/* #define RSCAN0_GAFLCFG0_COUNT (2) */
+    union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
+    union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
+    union iodefine_reg32_t  RMNB;                          /*  RMNB            */
+
+/* #define RSCAN0_RMND0_COUNT (3) */
+    union iodefine_reg32_t  RMND0;                         /*  RMND0           */
+    union iodefine_reg32_t  RMND1;                         /*  RMND1           */
+    union iodefine_reg32_t  RMND2;                         /*  RMND2           */
+    
+    volatile uint8_t   dummy160[4];                            /*                  */
+
+/* #define RSCAN0_RFCC0_COUNT (8) */
+    union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
+    union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
+    union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
+    union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
+    union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
+    union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
+    union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
+    union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
+
+/* #define RSCAN0_RFSTS0_COUNT (8) */
+    union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
+    union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
+    union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
+    union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
+    union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
+    union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
+    union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
+    union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
+
+/* #define RSCAN0_RFPCTR0_COUNT (8) */
+    union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
+    union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
+    union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
+    union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
+    union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
+    union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
+    union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
+    union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
+
+/* #define RSCAN0_CFCC0_COUNT (15) */
+    union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
+    union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
+    union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
+    union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
+    union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
+    union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
+    union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
+    union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
+    union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
+    union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
+    union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
+    union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
+    union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
+    union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
+    union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
+    
+    volatile uint8_t   dummy161[36];                           /*                  */
+
+/* #define RSCAN0_CFSTS0_COUNT (15) */
+    union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
+    union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
+    union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
+    union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
+    union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
+    union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
+    union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
+    union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
+    union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
+    union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
+    union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
+    union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
+    union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
+    union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
+    union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
+    
+    volatile uint8_t   dummy162[36];                           /*                  */
+
+/* #define RSCAN0_CFPCTR0_COUNT (15) */
+    union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
+    union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
+    union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
+    union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
+    union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
+    union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
+    union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
+    union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
+    union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
+    union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
+    union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
+    union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
+    union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
+    union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
+    union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
+    
+    volatile uint8_t   dummy163[36];                           /*                  */
+    union iodefine_reg32_t  FESTS;                         /*  FESTS           */
+    union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
+    union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
+    union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
+    union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
+    union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
+    
+
+/* #define RSCAN0_TMC0_COUNT (80) */
+    volatile uint8_t   TMC0;                                   /*  TMC0            */
+    volatile uint8_t   TMC1;                                   /*  TMC1            */
+    volatile uint8_t   TMC2;                                   /*  TMC2            */
+    volatile uint8_t   TMC3;                                   /*  TMC3            */
+    volatile uint8_t   TMC4;                                   /*  TMC4            */
+    volatile uint8_t   TMC5;                                   /*  TMC5            */
+    volatile uint8_t   TMC6;                                   /*  TMC6            */
+    volatile uint8_t   TMC7;                                   /*  TMC7            */
+    volatile uint8_t   TMC8;                                   /*  TMC8            */
+    volatile uint8_t   TMC9;                                   /*  TMC9            */
+    volatile uint8_t   TMC10;                                  /*  TMC10           */
+    volatile uint8_t   TMC11;                                  /*  TMC11           */
+    volatile uint8_t   TMC12;                                  /*  TMC12           */
+    volatile uint8_t   TMC13;                                  /*  TMC13           */
+    volatile uint8_t   TMC14;                                  /*  TMC14           */
+    volatile uint8_t   TMC15;                                  /*  TMC15           */
+    volatile uint8_t   TMC16;                                  /*  TMC16           */
+    volatile uint8_t   TMC17;                                  /*  TMC17           */
+    volatile uint8_t   TMC18;                                  /*  TMC18           */
+    volatile uint8_t   TMC19;                                  /*  TMC19           */
+    volatile uint8_t   TMC20;                                  /*  TMC20           */
+    volatile uint8_t   TMC21;                                  /*  TMC21           */
+    volatile uint8_t   TMC22;                                  /*  TMC22           */
+    volatile uint8_t   TMC23;                                  /*  TMC23           */
+    volatile uint8_t   TMC24;                                  /*  TMC24           */
+    volatile uint8_t   TMC25;                                  /*  TMC25           */
+    volatile uint8_t   TMC26;                                  /*  TMC26           */
+    volatile uint8_t   TMC27;                                  /*  TMC27           */
+    volatile uint8_t   TMC28;                                  /*  TMC28           */
+    volatile uint8_t   TMC29;                                  /*  TMC29           */
+    volatile uint8_t   TMC30;                                  /*  TMC30           */
+    volatile uint8_t   TMC31;                                  /*  TMC31           */
+    volatile uint8_t   TMC32;                                  /*  TMC32           */
+    volatile uint8_t   TMC33;                                  /*  TMC33           */
+    volatile uint8_t   TMC34;                                  /*  TMC34           */
+    volatile uint8_t   TMC35;                                  /*  TMC35           */
+    volatile uint8_t   TMC36;                                  /*  TMC36           */
+    volatile uint8_t   TMC37;                                  /*  TMC37           */
+    volatile uint8_t   TMC38;                                  /*  TMC38           */
+    volatile uint8_t   TMC39;                                  /*  TMC39           */
+    volatile uint8_t   TMC40;                                  /*  TMC40           */
+    volatile uint8_t   TMC41;                                  /*  TMC41           */
+    volatile uint8_t   TMC42;                                  /*  TMC42           */
+    volatile uint8_t   TMC43;                                  /*  TMC43           */
+    volatile uint8_t   TMC44;                                  /*  TMC44           */
+    volatile uint8_t   TMC45;                                  /*  TMC45           */
+    volatile uint8_t   TMC46;                                  /*  TMC46           */
+    volatile uint8_t   TMC47;                                  /*  TMC47           */
+    volatile uint8_t   TMC48;                                  /*  TMC48           */
+    volatile uint8_t   TMC49;                                  /*  TMC49           */
+    volatile uint8_t   TMC50;                                  /*  TMC50           */
+    volatile uint8_t   TMC51;                                  /*  TMC51           */
+    volatile uint8_t   TMC52;                                  /*  TMC52           */
+    volatile uint8_t   TMC53;                                  /*  TMC53           */
+    volatile uint8_t   TMC54;                                  /*  TMC54           */
+    volatile uint8_t   TMC55;                                  /*  TMC55           */
+    volatile uint8_t   TMC56;                                  /*  TMC56           */
+    volatile uint8_t   TMC57;                                  /*  TMC57           */
+    volatile uint8_t   TMC58;                                  /*  TMC58           */
+    volatile uint8_t   TMC59;                                  /*  TMC59           */
+    volatile uint8_t   TMC60;                                  /*  TMC60           */
+    volatile uint8_t   TMC61;                                  /*  TMC61           */
+    volatile uint8_t   TMC62;                                  /*  TMC62           */
+    volatile uint8_t   TMC63;                                  /*  TMC63           */
+    volatile uint8_t   TMC64;                                  /*  TMC64           */
+    volatile uint8_t   TMC65;                                  /*  TMC65           */
+    volatile uint8_t   TMC66;                                  /*  TMC66           */
+    volatile uint8_t   TMC67;                                  /*  TMC67           */
+    volatile uint8_t   TMC68;                                  /*  TMC68           */
+    volatile uint8_t   TMC69;                                  /*  TMC69           */
+    volatile uint8_t   TMC70;                                  /*  TMC70           */
+    volatile uint8_t   TMC71;                                  /*  TMC71           */
+    volatile uint8_t   TMC72;                                  /*  TMC72           */
+    volatile uint8_t   TMC73;                                  /*  TMC73           */
+    volatile uint8_t   TMC74;                                  /*  TMC74           */
+    volatile uint8_t   TMC75;                                  /*  TMC75           */
+    volatile uint8_t   TMC76;                                  /*  TMC76           */
+    volatile uint8_t   TMC77;                                  /*  TMC77           */
+    volatile uint8_t   TMC78;                                  /*  TMC78           */
+    volatile uint8_t   TMC79;                                  /*  TMC79           */
+    volatile uint8_t   dummy164[48];                           /*                  */
+
+/* #define RSCAN0_TMSTS0_COUNT (80) */
+    volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
+    volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
+    volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
+    volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
+    volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
+    volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
+    volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
+    volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
+    volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
+    volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
+    volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
+    volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
+    volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
+    volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
+    volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
+    volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
+    volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
+    volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
+    volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
+    volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
+    volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
+    volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
+    volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
+    volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
+    volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
+    volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
+    volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
+    volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
+    volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
+    volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
+    volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
+    volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
+    volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
+    volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
+    volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
+    volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
+    volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
+    volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
+    volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
+    volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
+    volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
+    volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
+    volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
+    volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
+    volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
+    volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
+    volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
+    volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
+    volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
+    volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
+    volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
+    volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
+    volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
+    volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
+    volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
+    volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
+    volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
+    volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
+    volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
+    volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
+    volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
+    volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
+    volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
+    volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
+    volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
+    volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
+    volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
+    volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
+    volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
+    volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
+    volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
+    volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
+    volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
+    volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
+    volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
+    volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
+    volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
+    volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
+    volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
+    volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
+    volatile uint8_t   dummy165[48];                           /*                  */
+
+/* #define RSCAN0_TMTRSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
+    union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
+    union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
+    
+    volatile uint8_t   dummy166[4];                            /*                  */
+
+/* #define RSCAN0_TMTARSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
+    union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
+    union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
+    
+    volatile uint8_t   dummy167[4];                            /*                  */
+
+/* #define RSCAN0_TMTCSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
+    union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
+    union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
+    
+    volatile uint8_t   dummy168[4];                            /*                  */
+
+/* #define RSCAN0_TMTASTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
+    union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
+    union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
+    
+    volatile uint8_t   dummy169[4];                            /*                  */
+
+/* #define RSCAN0_TMIEC0_COUNT (3) */
+    union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
+    union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
+    union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
+    
+    volatile uint8_t   dummy170[4];                            /*                  */
+
+/* #define RSCAN0_TXQCC0_COUNT (5) */
+    union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
+    union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
+    union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
+    union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
+    union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
+    
+    volatile uint8_t   dummy171[12];                           /*                  */
+
+/* #define RSCAN0_TXQSTS0_COUNT (5) */
+    union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
+    union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
+    union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
+    union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
+    union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
+    
+    volatile uint8_t   dummy172[12];                           /*                  */
+
+/* #define RSCAN0_TXQPCTR0_COUNT (5) */
+    union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
+    union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
+    union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
+    union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
+    union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
+    
+    volatile uint8_t   dummy173[12];                           /*                  */
+
+/* #define RSCAN0_THLCC0_COUNT (5) */
+    union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
+    union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
+    union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
+    union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
+    union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
+    
+    volatile uint8_t   dummy174[12];                           /*                  */
+
+/* #define RSCAN0_THLSTS0_COUNT (5) */
+    union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
+    union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
+    union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
+    union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
+    union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
+    
+    volatile uint8_t   dummy175[12];                           /*                  */
+
+/* #define RSCAN0_THLPCTR0_COUNT (5) */
+    union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
+    union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
+    union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
+    union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
+    union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
+    
+    volatile uint8_t   dummy176[12];                           /*                  */
+
+/* #define RSCAN0_GTINTSTS0_COUNT (2) */
+    union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
+    union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
+    union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
+    union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
+    
+    volatile uint8_t   dummy177[12];                           /*                  */
+    union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
+    
+    volatile uint8_t   dummy178[128];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
+    union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
+    union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
+    union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
+    union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
+    union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
+    union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
+    union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
+    union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
+    union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
+    union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
+    union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
+    union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
+    union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
+    union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
+    union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
+    union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
+    union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
+    union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
+    union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
+    union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
+    union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
+    union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
+    union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
+    union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
+    union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
+    union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
+    union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
+    union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
+    union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
+    union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
+    union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
+    union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
+    union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
+    union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
+    union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
+    union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
+    union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
+    union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
+    union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
+    union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
+    union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
+    union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
+    union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
+    union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
+    union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
+    union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
+    union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
+    union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID0;                         /*  RMID0           */
+    union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
+    union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
+    union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID1;                         /*  RMID1           */
+    union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
+    union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
+    union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID2;                         /*  RMID2           */
+    union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
+    union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
+    union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID3;                         /*  RMID3           */
+    union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
+    union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
+    union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID4;                         /*  RMID4           */
+    union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
+    union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
+    union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID5;                         /*  RMID5           */
+    union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
+    union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
+    union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID6;                         /*  RMID6           */
+    union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
+    union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
+    union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID7;                         /*  RMID7           */
+    union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
+    union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
+    union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID8;                         /*  RMID8           */
+    union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
+    union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
+    union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID9;                         /*  RMID9           */
+    union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
+    union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
+    union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID10;                        /*  RMID10          */
+    union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
+    union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
+    union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID11;                        /*  RMID11          */
+    union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
+    union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
+    union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID12;                        /*  RMID12          */
+    union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
+    union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
+    union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID13;                        /*  RMID13          */
+    union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
+    union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
+    union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID14;                        /*  RMID14          */
+    union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
+    union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
+    union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID15;                        /*  RMID15          */
+    union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
+    union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
+    union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID16;                        /*  RMID16          */
+    union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
+    union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
+    union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID17;                        /*  RMID17          */
+    union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
+    union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
+    union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID18;                        /*  RMID18          */
+    union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
+    union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
+    union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID19;                        /*  RMID19          */
+    union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
+    union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
+    union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID20;                        /*  RMID20          */
+    union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
+    union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
+    union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID21;                        /*  RMID21          */
+    union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
+    union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
+    union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID22;                        /*  RMID22          */
+    union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
+    union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
+    union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID23;                        /*  RMID23          */
+    union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
+    union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
+    union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID24;                        /*  RMID24          */
+    union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
+    union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
+    union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID25;                        /*  RMID25          */
+    union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
+    union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
+    union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID26;                        /*  RMID26          */
+    union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
+    union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
+    union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID27;                        /*  RMID27          */
+    union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
+    union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
+    union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID28;                        /*  RMID28          */
+    union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
+    union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
+    union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID29;                        /*  RMID29          */
+    union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
+    union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
+    union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID30;                        /*  RMID30          */
+    union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
+    union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
+    union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID31;                        /*  RMID31          */
+    union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
+    union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
+    union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID32;                        /*  RMID32          */
+    union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
+    union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
+    union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID33;                        /*  RMID33          */
+    union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
+    union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
+    union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID34;                        /*  RMID34          */
+    union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
+    union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
+    union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID35;                        /*  RMID35          */
+    union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
+    union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
+    union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID36;                        /*  RMID36          */
+    union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
+    union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
+    union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID37;                        /*  RMID37          */
+    union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
+    union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
+    union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID38;                        /*  RMID38          */
+    union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
+    union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
+    union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID39;                        /*  RMID39          */
+    union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
+    union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
+    union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID40;                        /*  RMID40          */
+    union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
+    union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
+    union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID41;                        /*  RMID41          */
+    union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
+    union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
+    union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID42;                        /*  RMID42          */
+    union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
+    union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
+    union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID43;                        /*  RMID43          */
+    union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
+    union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
+    union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID44;                        /*  RMID44          */
+    union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
+    union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
+    union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID45;                        /*  RMID45          */
+    union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
+    union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
+    union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID46;                        /*  RMID46          */
+    union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
+    union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
+    union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID47;                        /*  RMID47          */
+    union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
+    union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
+    union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID48;                        /*  RMID48          */
+    union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
+    union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
+    union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID49;                        /*  RMID49          */
+    union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
+    union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
+    union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID50;                        /*  RMID50          */
+    union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
+    union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
+    union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID51;                        /*  RMID51          */
+    union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
+    union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
+    union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID52;                        /*  RMID52          */
+    union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
+    union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
+    union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID53;                        /*  RMID53          */
+    union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
+    union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
+    union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID54;                        /*  RMID54          */
+    union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
+    union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
+    union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID55;                        /*  RMID55          */
+    union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
+    union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
+    union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID56;                        /*  RMID56          */
+    union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
+    union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
+    union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID57;                        /*  RMID57          */
+    union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
+    union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
+    union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID58;                        /*  RMID58          */
+    union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
+    union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
+    union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID59;                        /*  RMID59          */
+    union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
+    union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
+    union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID60;                        /*  RMID60          */
+    union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
+    union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
+    union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID61;                        /*  RMID61          */
+    union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
+    union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
+    union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID62;                        /*  RMID62          */
+    union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
+    union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
+    union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID63;                        /*  RMID63          */
+    union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
+    union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
+    union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID64;                        /*  RMID64          */
+    union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
+    union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
+    union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID65;                        /*  RMID65          */
+    union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
+    union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
+    union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID66;                        /*  RMID66          */
+    union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
+    union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
+    union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID67;                        /*  RMID67          */
+    union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
+    union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
+    union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID68;                        /*  RMID68          */
+    union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
+    union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
+    union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID69;                        /*  RMID69          */
+    union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
+    union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
+    union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID70;                        /*  RMID70          */
+    union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
+    union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
+    union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID71;                        /*  RMID71          */
+    union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
+    union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
+    union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID72;                        /*  RMID72          */
+    union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
+    union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
+    union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID73;                        /*  RMID73          */
+    union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
+    union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
+    union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID74;                        /*  RMID74          */
+    union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
+    union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
+    union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID75;                        /*  RMID75          */
+    union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
+    union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
+    union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID76;                        /*  RMID76          */
+    union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
+    union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
+    union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID77;                        /*  RMID77          */
+    union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
+    union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
+    union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID78;                        /*  RMID78          */
+    union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
+    union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
+    union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID79;                        /*  RMID79          */
+    union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
+    union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
+    union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+    volatile uint8_t   dummy179[768];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID0;                         /*  RFID0           */
+    union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
+    union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
+    union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID1;                         /*  RFID1           */
+    union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
+    union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
+    union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID2;                         /*  RFID2           */
+    union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
+    union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
+    union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID3;                         /*  RFID3           */
+    union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
+    union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
+    union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID4;                         /*  RFID4           */
+    union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
+    union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
+    union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID5;                         /*  RFID5           */
+    union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
+    union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
+    union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID6;                         /*  RFID6           */
+    union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
+    union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
+    union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID7;                         /*  RFID7           */
+    union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
+    union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
+    union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID0;                         /*  CFID0           */
+    union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
+    union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
+    union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID1;                         /*  CFID1           */
+    union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
+    union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
+    union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID2;                         /*  CFID2           */
+    union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
+    union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
+    union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID3;                         /*  CFID3           */
+    union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
+    union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
+    union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID4;                         /*  CFID4           */
+    union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
+    union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
+    union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID5;                         /*  CFID5           */
+    union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
+    union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
+    union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID6;                         /*  CFID6           */
+    union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
+    union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
+    union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID7;                         /*  CFID7           */
+    union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
+    union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
+    union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID8;                         /*  CFID8           */
+    union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
+    union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
+    union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID9;                         /*  CFID9           */
+    union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
+    union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
+    union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID10;                        /*  CFID10          */
+    union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
+    union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
+    union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID11;                        /*  CFID11          */
+    union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
+    union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
+    union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID12;                        /*  CFID12          */
+    union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
+    union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
+    union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID13;                        /*  CFID13          */
+    union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
+    union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
+    union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID14;                        /*  CFID14          */
+    union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
+    union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
+    union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+    volatile uint8_t   dummy180[144];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID0;                         /*  TMID0           */
+    union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
+    union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
+    union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID1;                         /*  TMID1           */
+    union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
+    union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
+    union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID2;                         /*  TMID2           */
+    union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
+    union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
+    union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID3;                         /*  TMID3           */
+    union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
+    union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
+    union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID4;                         /*  TMID4           */
+    union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
+    union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
+    union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID5;                         /*  TMID5           */
+    union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
+    union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
+    union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID6;                         /*  TMID6           */
+    union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
+    union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
+    union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID7;                         /*  TMID7           */
+    union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
+    union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
+    union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID8;                         /*  TMID8           */
+    union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
+    union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
+    union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID9;                         /*  TMID9           */
+    union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
+    union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
+    union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID10;                        /*  TMID10          */
+    union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
+    union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
+    union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID11;                        /*  TMID11          */
+    union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
+    union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
+    union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID12;                        /*  TMID12          */
+    union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
+    union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
+    union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID13;                        /*  TMID13          */
+    union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
+    union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
+    union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID14;                        /*  TMID14          */
+    union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
+    union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
+    union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID15;                        /*  TMID15          */
+    union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
+    union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
+    union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID16;                        /*  TMID16          */
+    union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
+    union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
+    union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID17;                        /*  TMID17          */
+    union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
+    union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
+    union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID18;                        /*  TMID18          */
+    union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
+    union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
+    union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID19;                        /*  TMID19          */
+    union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
+    union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
+    union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID20;                        /*  TMID20          */
+    union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
+    union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
+    union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID21;                        /*  TMID21          */
+    union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
+    union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
+    union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID22;                        /*  TMID22          */
+    union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
+    union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
+    union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID23;                        /*  TMID23          */
+    union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
+    union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
+    union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID24;                        /*  TMID24          */
+    union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
+    union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
+    union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID25;                        /*  TMID25          */
+    union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
+    union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
+    union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID26;                        /*  TMID26          */
+    union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
+    union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
+    union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID27;                        /*  TMID27          */
+    union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
+    union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
+    union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID28;                        /*  TMID28          */
+    union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
+    union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
+    union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID29;                        /*  TMID29          */
+    union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
+    union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
+    union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID30;                        /*  TMID30          */
+    union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
+    union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
+    union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID31;                        /*  TMID31          */
+    union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
+    union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
+    union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID32;                        /*  TMID32          */
+    union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
+    union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
+    union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID33;                        /*  TMID33          */
+    union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
+    union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
+    union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID34;                        /*  TMID34          */
+    union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
+    union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
+    union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID35;                        /*  TMID35          */
+    union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
+    union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
+    union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID36;                        /*  TMID36          */
+    union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
+    union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
+    union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID37;                        /*  TMID37          */
+    union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
+    union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
+    union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID38;                        /*  TMID38          */
+    union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
+    union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
+    union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID39;                        /*  TMID39          */
+    union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
+    union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
+    union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID40;                        /*  TMID40          */
+    union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
+    union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
+    union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID41;                        /*  TMID41          */
+    union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
+    union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
+    union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID42;                        /*  TMID42          */
+    union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
+    union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
+    union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID43;                        /*  TMID43          */
+    union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
+    union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
+    union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID44;                        /*  TMID44          */
+    union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
+    union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
+    union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID45;                        /*  TMID45          */
+    union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
+    union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
+    union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID46;                        /*  TMID46          */
+    union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
+    union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
+    union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID47;                        /*  TMID47          */
+    union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
+    union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
+    union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID48;                        /*  TMID48          */
+    union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
+    union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
+    union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID49;                        /*  TMID49          */
+    union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
+    union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
+    union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID50;                        /*  TMID50          */
+    union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
+    union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
+    union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID51;                        /*  TMID51          */
+    union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
+    union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
+    union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID52;                        /*  TMID52          */
+    union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
+    union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
+    union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID53;                        /*  TMID53          */
+    union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
+    union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
+    union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID54;                        /*  TMID54          */
+    union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
+    union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
+    union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID55;                        /*  TMID55          */
+    union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
+    union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
+    union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID56;                        /*  TMID56          */
+    union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
+    union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
+    union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID57;                        /*  TMID57          */
+    union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
+    union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
+    union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID58;                        /*  TMID58          */
+    union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
+    union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
+    union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID59;                        /*  TMID59          */
+    union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
+    union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
+    union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID60;                        /*  TMID60          */
+    union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
+    union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
+    union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID61;                        /*  TMID61          */
+    union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
+    union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
+    union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID62;                        /*  TMID62          */
+    union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
+    union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
+    union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID63;                        /*  TMID63          */
+    union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
+    union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
+    union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID64;                        /*  TMID64          */
+    union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
+    union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
+    union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID65;                        /*  TMID65          */
+    union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
+    union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
+    union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID66;                        /*  TMID66          */
+    union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
+    union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
+    union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID67;                        /*  TMID67          */
+    union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
+    union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
+    union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID68;                        /*  TMID68          */
+    union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
+    union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
+    union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID69;                        /*  TMID69          */
+    union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
+    union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
+    union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID70;                        /*  TMID70          */
+    union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
+    union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
+    union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID71;                        /*  TMID71          */
+    union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
+    union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
+    union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID72;                        /*  TMID72          */
+    union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
+    union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
+    union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID73;                        /*  TMID73          */
+    union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
+    union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
+    union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID74;                        /*  TMID74          */
+    union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
+    union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
+    union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID75;                        /*  TMID75          */
+    union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
+    union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
+    union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID76;                        /*  TMID76          */
+    union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
+    union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
+    union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID77;                        /*  TMID77          */
+    union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
+    union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
+    union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID78;                        /*  TMID78          */
+    union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
+    union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
+    union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID79;                        /*  TMID79          */
+    union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
+    union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
+    union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+    volatile uint8_t   dummy181[768];                          /*                  */
+
+/* #define RSCAN0_THLACC0_COUNT (5) */
+    union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
+    union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
+    union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
+    union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
+    union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
+    
+} r_io_rscan0_t;
+
+
+typedef struct st_rscan_from_rscan0cncfg
+{
+ 
+    union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
+    union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
+    union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
+    union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
+} r_io_rscan_from_rscan0cncfg_t;
+
+
+typedef struct st_rscan_from_rscan0gaflidj
+{
+ 
+    union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
+    union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
+    union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
+    union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
+} r_io_rscan_from_rscan0gaflidj_t;
+
+
+typedef struct st_rscan_from_rscan0rmidp
+{
+ 
+    union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
+    union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
+    union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
+    union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
+} r_io_rscan_from_rscan0rmidp_t;
+
+
+typedef struct st_rscan_from_rscan0rfidm
+{
+ 
+    union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
+    union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
+    union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
+    union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
+} r_io_rscan_from_rscan0rfidm_t;
+
+
+typedef struct st_rscan_from_rscan0tmidp
+{
+ 
+    union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
+    union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
+    union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
+    union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
+} r_io_rscan_from_rscan0tmidp_t;
+
+
+typedef struct st_rscan_from_rscan0cfidm
+{
+ 
+    union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
+    union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
+    union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
+    union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
+} r_io_rscan_from_rscan0cfidm_t;
+
+
+/* Channel array defines of RSCAN0 (2)*/
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS
+volatile struct st_rscan_from_rscan0cfidm*  RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS
+volatile struct st_rscan_from_rscan0tmidp*  RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS
+volatile struct st_rscan_from_rscan0rfidm*  RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS
+volatile struct st_rscan_from_rscan0rmidp*  RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS
+volatile struct st_rscan_from_rscan0gaflidj*  RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS
+volatile struct st_rscan_from_rscan0cncfg*  RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */
+/* End of channel array defines of RSCAN0 (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h	(revision 374)
@@ -0,0 +1,224 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rspi_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef RSPI_IODEFINE_H
+#define RSPI_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
+#define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
+#define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
+#define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
+#define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
+
+
+/* Start of channel array defines of RSPI */
+
+/* Channel array defines of RSPI */
+/*(Sample) value = RSPI[ channel ]->SPCR; */
+#define RSPI_COUNT  (5)
+#define RSPI_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of RSPI */
+
+
+#define SPCR_0 (RSPI0.SPCR)
+#define SSLP_0 (RSPI0.SSLP)
+#define SPPCR_0 (RSPI0.SPPCR)
+#define SPSR_0 (RSPI0.SPSR)
+#define SPDR_0   (RSPI0.SPDR.UINT32)
+#define SPDR_0L  (RSPI0.SPDR.UINT16[R_IO_L])
+#define SPDR_0H  (RSPI0.SPDR.UINT16[R_IO_H])
+#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
+#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
+#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
+#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
+#define SPSCR_0 (RSPI0.SPSCR)
+#define SPSSR_0 (RSPI0.SPSSR)
+#define SPBR_0 (RSPI0.SPBR)
+#define SPDCR_0 (RSPI0.SPDCR)
+#define SPCKD_0 (RSPI0.SPCKD)
+#define SSLND_0 (RSPI0.SSLND)
+#define SPND_0 (RSPI0.SPND)
+#define SPCMD0_0 (RSPI0.SPCMD0)
+#define SPCMD1_0 (RSPI0.SPCMD1)
+#define SPCMD2_0 (RSPI0.SPCMD2)
+#define SPCMD3_0 (RSPI0.SPCMD3)
+#define SPBFCR_0 (RSPI0.SPBFCR)
+#define SPBFDR_0 (RSPI0.SPBFDR)
+#define SPCR_1 (RSPI1.SPCR)
+#define SSLP_1 (RSPI1.SSLP)
+#define SPPCR_1 (RSPI1.SPPCR)
+#define SPSR_1 (RSPI1.SPSR)
+#define SPDR_1   (RSPI1.SPDR.UINT32)
+#define SPDR_1L  (RSPI1.SPDR.UINT16[R_IO_L])
+#define SPDR_1H  (RSPI1.SPDR.UINT16[R_IO_H])
+#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
+#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
+#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
+#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
+#define SPSCR_1 (RSPI1.SPSCR)
+#define SPSSR_1 (RSPI1.SPSSR)
+#define SPBR_1 (RSPI1.SPBR)
+#define SPDCR_1 (RSPI1.SPDCR)
+#define SPCKD_1 (RSPI1.SPCKD)
+#define SSLND_1 (RSPI1.SSLND)
+#define SPND_1 (RSPI1.SPND)
+#define SPCMD0_1 (RSPI1.SPCMD0)
+#define SPCMD1_1 (RSPI1.SPCMD1)
+#define SPCMD2_1 (RSPI1.SPCMD2)
+#define SPCMD3_1 (RSPI1.SPCMD3)
+#define SPBFCR_1 (RSPI1.SPBFCR)
+#define SPBFDR_1 (RSPI1.SPBFDR)
+#define SPCR_2 (RSPI2.SPCR)
+#define SSLP_2 (RSPI2.SSLP)
+#define SPPCR_2 (RSPI2.SPPCR)
+#define SPSR_2 (RSPI2.SPSR)
+#define SPDR_2   (RSPI2.SPDR.UINT32)
+#define SPDR_2L  (RSPI2.SPDR.UINT16[R_IO_L])
+#define SPDR_2H  (RSPI2.SPDR.UINT16[R_IO_H])
+#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
+#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
+#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
+#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
+#define SPSCR_2 (RSPI2.SPSCR)
+#define SPSSR_2 (RSPI2.SPSSR)
+#define SPBR_2 (RSPI2.SPBR)
+#define SPDCR_2 (RSPI2.SPDCR)
+#define SPCKD_2 (RSPI2.SPCKD)
+#define SSLND_2 (RSPI2.SSLND)
+#define SPND_2 (RSPI2.SPND)
+#define SPCMD0_2 (RSPI2.SPCMD0)
+#define SPCMD1_2 (RSPI2.SPCMD1)
+#define SPCMD2_2 (RSPI2.SPCMD2)
+#define SPCMD3_2 (RSPI2.SPCMD3)
+#define SPBFCR_2 (RSPI2.SPBFCR)
+#define SPBFDR_2 (RSPI2.SPBFDR)
+#define SPCR_3 (RSPI3.SPCR)
+#define SSLP_3 (RSPI3.SSLP)
+#define SPPCR_3 (RSPI3.SPPCR)
+#define SPSR_3 (RSPI3.SPSR)
+#define SPDR_3   (RSPI3.SPDR.UINT32)
+#define SPDR_3L  (RSPI3.SPDR.UINT16[R_IO_L])
+#define SPDR_3H  (RSPI3.SPDR.UINT16[R_IO_H])
+#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
+#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
+#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
+#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
+#define SPSCR_3 (RSPI3.SPSCR)
+#define SPSSR_3 (RSPI3.SPSSR)
+#define SPBR_3 (RSPI3.SPBR)
+#define SPDCR_3 (RSPI3.SPDCR)
+#define SPCKD_3 (RSPI3.SPCKD)
+#define SSLND_3 (RSPI3.SSLND)
+#define SPND_3 (RSPI3.SPND)
+#define SPCMD0_3 (RSPI3.SPCMD0)
+#define SPCMD1_3 (RSPI3.SPCMD1)
+#define SPCMD2_3 (RSPI3.SPCMD2)
+#define SPCMD3_3 (RSPI3.SPCMD3)
+#define SPBFCR_3 (RSPI3.SPBFCR)
+#define SPBFDR_3 (RSPI3.SPBFDR)
+#define SPCR_4 (RSPI4.SPCR)
+#define SSLP_4 (RSPI4.SSLP)
+#define SPPCR_4 (RSPI4.SPPCR)
+#define SPSR_4 (RSPI4.SPSR)
+#define SPDR_4   (RSPI4.SPDR.UINT32)
+#define SPDR_4L  (RSPI4.SPDR.UINT16[R_IO_L])
+#define SPDR_4H  (RSPI4.SPDR.UINT16[R_IO_H])
+#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
+#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
+#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
+#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
+#define SPSCR_4 (RSPI4.SPSCR)
+#define SPSSR_4 (RSPI4.SPSSR)
+#define SPBR_4 (RSPI4.SPBR)
+#define SPDCR_4 (RSPI4.SPDCR)
+#define SPCKD_4 (RSPI4.SPCKD)
+#define SSLND_4 (RSPI4.SSLND)
+#define SPND_4 (RSPI4.SPND)
+#define SPCMD0_4 (RSPI4.SPCMD0)
+#define SPCMD1_4 (RSPI4.SPCMD1)
+#define SPCMD2_4 (RSPI4.SPCMD2)
+#define SPCMD3_4 (RSPI4.SPCMD3)
+#define SPBFCR_4 (RSPI4.SPBFCR)
+#define SPBFDR_4 (RSPI4.SPBFDR)
+
+#define SPCMD_COUNT (4)
+
+
+typedef struct st_rspi
+{
+                                                           /* RSPI             */
+    volatile uint8_t   SPCR;                                   /*  SPCR            */
+    volatile uint8_t   SSLP;                                   /*  SSLP            */
+    volatile uint8_t   SPPCR;                                  /*  SPPCR           */
+    volatile uint8_t   SPSR;                                   /*  SPSR            */
+    union iodefine_reg32_t  SPDR;                          /*  SPDR            */
+    
+    volatile uint8_t   SPSCR;                                  /*  SPSCR           */
+    volatile uint8_t   SPSSR;                                  /*  SPSSR           */
+    volatile uint8_t   SPBR;                                   /*  SPBR            */
+    volatile uint8_t   SPDCR;                                  /*  SPDCR           */
+    volatile uint8_t   SPCKD;                                  /*  SPCKD           */
+    volatile uint8_t   SSLND;                                  /*  SSLND           */
+    volatile uint8_t   SPND;                                   /*  SPND            */
+    volatile uint8_t   dummy1[1];                              /*                  */
+
+/* #define SPCMD_COUNT (4) */
+    volatile uint16_t SPCMD0;                                 /*  SPCMD0          */
+    volatile uint16_t SPCMD1;                                 /*  SPCMD1          */
+    volatile uint16_t SPCMD2;                                 /*  SPCMD2          */
+    volatile uint16_t SPCMD3;                                 /*  SPCMD3          */
+    volatile uint8_t   dummy2[8];                              /*                  */
+    volatile uint8_t   SPBFCR;                                 /*  SPBFCR          */
+    volatile uint8_t   dummy3[1];                              /*                  */
+    volatile uint16_t SPBFDR;                                 /*  SPBFDR          */
+} r_io_rspi_t;
+
+
+/* Channel array defines of RSPI (2)*/
+#ifdef  DECLARE_RSPI_CHANNELS
+volatile struct st_rspi*  RSPI[ RSPI_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSPI_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSPI_CHANNELS */
+/* End of channel array defines of RSPI (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h	(revision 374)
@@ -0,0 +1,111 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rtc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef RTC_IODEFINE_H
+#define RTC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
+
+
+#define RTCR64CNT (RTC.R64CNT)
+#define RTCRSECCNT (RTC.RSECCNT)
+#define RTCRMINCNT (RTC.RMINCNT)
+#define RTCRHRCNT (RTC.RHRCNT)
+#define RTCRWKCNT (RTC.RWKCNT)
+#define RTCRDAYCNT (RTC.RDAYCNT)
+#define RTCRMONCNT (RTC.RMONCNT)
+#define RTCRYRCNT (RTC.RYRCNT)
+#define RTCRSECAR (RTC.RSECAR)
+#define RTCRMINAR (RTC.RMINAR)
+#define RTCRHRAR (RTC.RHRAR)
+#define RTCRWKAR (RTC.RWKAR)
+#define RTCRDAYAR (RTC.RDAYAR)
+#define RTCRMONAR (RTC.RMONAR)
+#define RTCRCR1 (RTC.RCR1)
+#define RTCRCR2 (RTC.RCR2)
+#define RTCRYRAR (RTC.RYRAR)
+#define RTCRCR3 (RTC.RCR3)
+#define RTCRCR5 (RTC.RCR5)
+#define RTCRFRH (RTC.RFRH)
+#define RTCRFRL (RTC.RFRL)
+
+
+typedef struct st_rtc
+{
+                                                           /* RTC              */
+    volatile uint8_t   R64CNT;                                 /*  R64CNT          */
+    volatile uint8_t   dummy537[1];                            /*                  */
+    volatile uint8_t   RSECCNT;                                /*  RSECCNT         */
+    volatile uint8_t   dummy538[1];                            /*                  */
+    volatile uint8_t   RMINCNT;                                /*  RMINCNT         */
+    volatile uint8_t   dummy539[1];                            /*                  */
+    volatile uint8_t   RHRCNT;                                 /*  RHRCNT          */
+    volatile uint8_t   dummy540[1];                            /*                  */
+    volatile uint8_t   RWKCNT;                                 /*  RWKCNT          */
+    volatile uint8_t   dummy541[1];                            /*                  */
+    volatile uint8_t   RDAYCNT;                                /*  RDAYCNT         */
+    volatile uint8_t   dummy542[1];                            /*                  */
+    volatile uint8_t   RMONCNT;                                /*  RMONCNT         */
+    volatile uint8_t   dummy543[1];                            /*                  */
+    volatile uint16_t RYRCNT;                                 /*  RYRCNT          */
+    volatile uint8_t   RSECAR;                                 /*  RSECAR          */
+    volatile uint8_t   dummy544[1];                            /*                  */
+    volatile uint8_t   RMINAR;                                 /*  RMINAR          */
+    volatile uint8_t   dummy545[1];                            /*                  */
+    volatile uint8_t   RHRAR;                                  /*  RHRAR           */
+    volatile uint8_t   dummy546[1];                            /*                  */
+    volatile uint8_t   RWKAR;                                  /*  RWKAR           */
+    volatile uint8_t   dummy547[1];                            /*                  */
+    volatile uint8_t   RDAYAR;                                 /*  RDAYAR          */
+    volatile uint8_t   dummy548[1];                            /*                  */
+    volatile uint8_t   RMONAR;                                 /*  RMONAR          */
+    volatile uint8_t   dummy549[1];                            /*                  */
+    volatile uint8_t   RCR1;                                   /*  RCR1            */
+    volatile uint8_t   dummy550[1];                            /*                  */
+    volatile uint8_t   RCR2;                                   /*  RCR2            */
+    volatile uint8_t   dummy551[1];                            /*                  */
+    volatile uint16_t RYRAR;                                  /*  RYRAR           */
+    volatile uint8_t   dummy552[2];                            /*                  */
+    volatile uint8_t   RCR3;                                   /*  RCR3            */
+    volatile uint8_t   dummy553[1];                            /*                  */
+    volatile uint8_t   RCR5;                                   /*  RCR5            */
+    volatile uint8_t   dummy554[3];                            /*                  */
+    volatile uint16_t RFRH;                                   /*  RFRH            */
+    volatile uint16_t RFRL;                                   /*  RFRL            */
+} r_io_rtc_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h	(revision 374)
@@ -0,0 +1,190 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scif_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef SCIF_IODEFINE_H
+#define SCIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
+#define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
+#define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
+#define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
+#define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
+#define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
+#define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
+#define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
+
+
+/* Start of channel array defines of SCIF */
+
+/* Channel array defines of SCIF */
+/*(Sample) value = SCIF[ channel ]->SCSMR; */
+#define SCIF_COUNT  (8)
+#define SCIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SCIF */
+
+
+#define SCSMR_0 (SCIF0.SCSMR)
+#define SCBRR_0 (SCIF0.SCBRR)
+#define SCSCR_0 (SCIF0.SCSCR)
+#define SCFTDR_0 (SCIF0.SCFTDR)
+#define SCFSR_0 (SCIF0.SCFSR)
+#define SCFRDR_0 (SCIF0.SCFRDR)
+#define SCFCR_0 (SCIF0.SCFCR)
+#define SCFDR_0 (SCIF0.SCFDR)
+#define SCSPTR_0 (SCIF0.SCSPTR)
+#define SCLSR_0 (SCIF0.SCLSR)
+#define SCEMR_0 (SCIF0.SCEMR)
+#define SCSMR_1 (SCIF1.SCSMR)
+#define SCBRR_1 (SCIF1.SCBRR)
+#define SCSCR_1 (SCIF1.SCSCR)
+#define SCFTDR_1 (SCIF1.SCFTDR)
+#define SCFSR_1 (SCIF1.SCFSR)
+#define SCFRDR_1 (SCIF1.SCFRDR)
+#define SCFCR_1 (SCIF1.SCFCR)
+#define SCFDR_1 (SCIF1.SCFDR)
+#define SCSPTR_1 (SCIF1.SCSPTR)
+#define SCLSR_1 (SCIF1.SCLSR)
+#define SCEMR_1 (SCIF1.SCEMR)
+#define SCSMR_2 (SCIF2.SCSMR)
+#define SCBRR_2 (SCIF2.SCBRR)
+#define SCSCR_2 (SCIF2.SCSCR)
+#define SCFTDR_2 (SCIF2.SCFTDR)
+#define SCFSR_2 (SCIF2.SCFSR)
+#define SCFRDR_2 (SCIF2.SCFRDR)
+#define SCFCR_2 (SCIF2.SCFCR)
+#define SCFDR_2 (SCIF2.SCFDR)
+#define SCSPTR_2 (SCIF2.SCSPTR)
+#define SCLSR_2 (SCIF2.SCLSR)
+#define SCEMR_2 (SCIF2.SCEMR)
+#define SCSMR_3 (SCIF3.SCSMR)
+#define SCBRR_3 (SCIF3.SCBRR)
+#define SCSCR_3 (SCIF3.SCSCR)
+#define SCFTDR_3 (SCIF3.SCFTDR)
+#define SCFSR_3 (SCIF3.SCFSR)
+#define SCFRDR_3 (SCIF3.SCFRDR)
+#define SCFCR_3 (SCIF3.SCFCR)
+#define SCFDR_3 (SCIF3.SCFDR)
+#define SCSPTR_3 (SCIF3.SCSPTR)
+#define SCLSR_3 (SCIF3.SCLSR)
+#define SCEMR_3 (SCIF3.SCEMR)
+#define SCSMR_4 (SCIF4.SCSMR)
+#define SCBRR_4 (SCIF4.SCBRR)
+#define SCSCR_4 (SCIF4.SCSCR)
+#define SCFTDR_4 (SCIF4.SCFTDR)
+#define SCFSR_4 (SCIF4.SCFSR)
+#define SCFRDR_4 (SCIF4.SCFRDR)
+#define SCFCR_4 (SCIF4.SCFCR)
+#define SCFDR_4 (SCIF4.SCFDR)
+#define SCSPTR_4 (SCIF4.SCSPTR)
+#define SCLSR_4 (SCIF4.SCLSR)
+#define SCEMR_4 (SCIF4.SCEMR)
+#define SCSMR_5 (SCIF5.SCSMR)
+#define SCBRR_5 (SCIF5.SCBRR)
+#define SCSCR_5 (SCIF5.SCSCR)
+#define SCFTDR_5 (SCIF5.SCFTDR)
+#define SCFSR_5 (SCIF5.SCFSR)
+#define SCFRDR_5 (SCIF5.SCFRDR)
+#define SCFCR_5 (SCIF5.SCFCR)
+#define SCFDR_5 (SCIF5.SCFDR)
+#define SCSPTR_5 (SCIF5.SCSPTR)
+#define SCLSR_5 (SCIF5.SCLSR)
+#define SCEMR_5 (SCIF5.SCEMR)
+#define SCSMR_6 (SCIF6.SCSMR)
+#define SCBRR_6 (SCIF6.SCBRR)
+#define SCSCR_6 (SCIF6.SCSCR)
+#define SCFTDR_6 (SCIF6.SCFTDR)
+#define SCFSR_6 (SCIF6.SCFSR)
+#define SCFRDR_6 (SCIF6.SCFRDR)
+#define SCFCR_6 (SCIF6.SCFCR)
+#define SCFDR_6 (SCIF6.SCFDR)
+#define SCSPTR_6 (SCIF6.SCSPTR)
+#define SCLSR_6 (SCIF6.SCLSR)
+#define SCEMR_6 (SCIF6.SCEMR)
+#define SCSMR_7 (SCIF7.SCSMR)
+#define SCBRR_7 (SCIF7.SCBRR)
+#define SCSCR_7 (SCIF7.SCSCR)
+#define SCFTDR_7 (SCIF7.SCFTDR)
+#define SCFSR_7 (SCIF7.SCFSR)
+#define SCFRDR_7 (SCIF7.SCFRDR)
+#define SCFCR_7 (SCIF7.SCFCR)
+#define SCFDR_7 (SCIF7.SCFDR)
+#define SCSPTR_7 (SCIF7.SCSPTR)
+#define SCLSR_7 (SCIF7.SCLSR)
+#define SCEMR_7 (SCIF7.SCEMR)
+
+
+typedef struct st_scif
+{
+                                                           /* SCIF             */
+    volatile uint16_t SCSMR;                                  /*  SCSMR           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+    volatile uint8_t   SCBRR;                                  /*  SCBRR           */
+    volatile uint8_t   dummy2[3];                              /*                  */
+    volatile uint16_t SCSCR;                                  /*  SCSCR           */
+    volatile uint8_t   dummy3[2];                              /*                  */
+    volatile uint8_t   SCFTDR;                                 /*  SCFTDR          */
+    volatile uint8_t   dummy4[3];                              /*                  */
+    volatile uint16_t SCFSR;                                  /*  SCFSR           */
+    volatile uint8_t   dummy5[2];                              /*                  */
+    volatile uint8_t   SCFRDR;                                 /*  SCFRDR          */
+    volatile uint8_t   dummy6[3];                              /*                  */
+    volatile uint16_t SCFCR;                                  /*  SCFCR           */
+    volatile uint8_t   dummy7[2];                              /*                  */
+    volatile uint16_t SCFDR;                                  /*  SCFDR           */
+    volatile uint8_t   dummy8[2];                              /*                  */
+    volatile uint16_t SCSPTR;                                 /*  SCSPTR          */
+    volatile uint8_t   dummy9[2];                              /*                  */
+    volatile uint16_t SCLSR;                                  /*  SCLSR           */
+    volatile uint8_t   dummy10[2];                             /*                  */
+    volatile uint16_t SCEMR;                                  /*  SCEMR           */
+} r_io_scif_t;
+
+
+/* Channel array defines of SCIF (2)*/
+#ifdef  DECLARE_SCIF_CHANNELS
+volatile struct st_scif*  SCIF[ SCIF_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCIF_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCIF_CHANNELS */
+/* End of channel array defines of SCIF (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h	(revision 374)
@@ -0,0 +1,106 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scim_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef SCIM_IODEFINE_H
+#define SCIM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
+#define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
+
+
+/* Start of channel array defines of SCIM */
+
+/* Channel array defines of SCIM */
+/*(Sample) value = SCIM[ channel ]->SMR; */
+#define SCIM_COUNT  (2)
+#define SCIM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIM0, &SCIM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SCIM */
+
+
+#define SMR0 (SCIM0.SMR)
+#define BRR0 (SCIM0.BRR)
+#define SCR0 (SCIM0.SCR)
+#define TDR0 (SCIM0.TDR)
+#define SSR0 (SCIM0.SSR)
+#define RDR0 (SCIM0.RDR)
+#define SCMR0 (SCIM0.SCMR)
+#define SEMR0 (SCIM0.SEMR)
+#define SNFR0 (SCIM0.SNFR)
+#define SECR0 (SCIM0.SECR)
+#define SMR1 (SCIM1.SMR)
+#define BRR1 (SCIM1.BRR)
+#define SCR1 (SCIM1.SCR)
+#define TDR1 (SCIM1.TDR)
+#define SSR1 (SCIM1.SSR)
+#define RDR1 (SCIM1.RDR)
+#define SCMR1 (SCIM1.SCMR)
+#define SEMR1 (SCIM1.SEMR)
+#define SNFR1 (SCIM1.SNFR)
+#define SECR1 (SCIM1.SECR)
+
+
+typedef struct st_scim
+{
+                                                           /* SCIM             */
+    volatile uint8_t   SMR;                                    /*  SMR             */
+    volatile uint8_t   BRR;                                    /*  BRR             */
+    volatile uint8_t   SCR;                                    /*  SCR             */
+    volatile uint8_t   TDR;                                    /*  TDR             */
+    volatile uint8_t   SSR;                                    /*  SSR             */
+    volatile uint8_t   RDR;                                    /*  RDR             */
+    volatile uint8_t   SCMR;                                   /*  SCMR            */
+    volatile uint8_t   SEMR;                                   /*  SEMR            */
+    volatile uint8_t   SNFR;                                   /*  SNFR            */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint8_t   SECR;                                   /*  SECR            */
+} r_io_scim_t;
+
+
+/* Channel array defines of SCIM (2)*/
+#ifdef  DECLARE_SCIM_CHANNELS
+volatile struct st_scim*  SCIM[ SCIM_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCIM_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCIM_CHANNELS */
+/* End of channel array defines of SCIM (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h	(revision 374)
@@ -0,0 +1,921 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scux_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef SCUX_IODEFINE_H
+#define SCUX_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
+
+
+/* Start of channel array defines of SCUX */
+
+/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
+#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
+#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
+#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  (2)
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
+#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
+
+
+/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
+#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
+#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
+#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
+#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
+#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
+#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
+
+
+/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
+#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
+#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
+#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
+
+
+/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
+#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
+#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
+#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
+
+/* End of channel array defines of SCUX */
+
+
+#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
+#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
+#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
+#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
+#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
+#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
+#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
+#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
+#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
+#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
+#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
+#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
+#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
+#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
+#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
+#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
+#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
+#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
+#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
+#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
+#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
+#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
+#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
+#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
+#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
+#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
+#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
+#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
+#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
+#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
+#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
+#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
+#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
+#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
+#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
+#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
+#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
+#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
+#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
+#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
+#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
+#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
+#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
+#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
+#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
+#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
+#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
+#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
+#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
+#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
+#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
+#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
+#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
+#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
+#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
+#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
+#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
+#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
+#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
+#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
+#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
+#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
+#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
+#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
+#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
+#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
+#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
+#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
+#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
+#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
+#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
+#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
+#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
+#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
+#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
+#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
+#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
+#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
+#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
+#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
+#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
+#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
+#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
+#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
+#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
+#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
+#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
+#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
+#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
+#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
+#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
+#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
+#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
+#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
+#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
+#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
+#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
+#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
+#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
+#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
+#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
+#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
+#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
+#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
+#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
+#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
+#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
+#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
+#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
+#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
+#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
+#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
+#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
+#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
+#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
+#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
+#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
+#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
+#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
+#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
+#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
+#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
+#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
+#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
+#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
+#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
+#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
+#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
+#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
+#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
+#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
+#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
+#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
+#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
+#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
+#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
+#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
+#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
+#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
+#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
+#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
+#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
+#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
+#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
+#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
+#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
+#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
+#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
+#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
+#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
+#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
+#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
+#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
+#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
+#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
+#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
+#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
+#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
+#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
+#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
+#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
+#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
+#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
+#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
+#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
+#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
+#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
+#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
+#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
+#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
+#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
+#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
+#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
+#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
+#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
+#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
+#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
+#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
+#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
+#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
+#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
+#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
+#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
+#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
+#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
+#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
+#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
+#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
+#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
+#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
+#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
+#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
+#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
+#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
+#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
+#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
+#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
+#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
+#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
+#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
+#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
+#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
+#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
+#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
+#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
+#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
+#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
+#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
+#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
+#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
+#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
+#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
+#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
+#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
+#define SCUXDMACR_CIM (SCUX.DMACR_CIM)
+#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
+#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
+#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
+#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
+#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
+#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
+#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
+#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
+#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
+#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
+#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
+#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
+#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
+#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
+#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
+#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
+#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
+#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
+#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
+#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
+#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
+#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
+#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
+#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
+#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
+#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
+#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
+#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
+#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
+#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
+#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
+#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
+#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
+#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
+#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
+#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
+#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
+#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
+#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
+#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
+
+#define SCUX_DMATDnCIM_COUNT (4)
+#define SCUX_DMATUnCIM_COUNT (4)
+#define SCUX_FDTSELnCIM_COUNT (4)
+#define SCUX_FUTSELnCIM_COUNT (4)
+#define SCUX_SRCRSELnCIM_COUNT (4)
+
+
+typedef struct st_scux
+{
+                                                           /* SCUX             */
+
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
+    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
+    volatile uint8_t   dummy259[248];                          /*                  */
+
+/* end of struct st_scux_from_ipcir_ipc0_n */
+
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_1;                           /*  IPCIR_IPC0_1    */
+    volatile uint32_t  IPSLR_IPC0_1;                           /*  IPSLR_IPC0_1    */
+    volatile uint8_t   dummy260[248];                          /*                  */
+
+/* end of struct st_scux_from_ipcir_ipc0_n */
+
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_2;                           /*  IPCIR_IPC0_2    */
+    volatile uint32_t  IPSLR_IPC0_2;                           /*  IPSLR_IPC0_2    */
+    volatile uint8_t   dummy261[248];                          /*                  */
+
+/* end of struct st_scux_from_ipcir_ipc0_n */
+
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_3;                           /*  IPCIR_IPC0_3    */
+    volatile uint32_t  IPSLR_IPC0_3;                           /*  IPSLR_IPC0_3    */
+    volatile uint8_t   dummy262[248];                          /*                  */
+
+/* end of struct st_scux_from_ipcir_ipc0_n */
+
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
+    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
+    volatile uint8_t   dummy263[248];                          /*                  */
+
+/* end of struct st_scux_from_opcir_opc0_n */
+
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_1;                           /*  OPCIR_OPC0_1    */
+    volatile uint32_t  OPSLR_OPC0_1;                           /*  OPSLR_OPC0_1    */
+    volatile uint8_t   dummy264[248];                          /*                  */
+
+/* end of struct st_scux_from_opcir_opc0_n */
+
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_2;                           /*  OPCIR_OPC0_2    */
+    volatile uint32_t  OPSLR_OPC0_2;                           /*  OPSLR_OPC0_2    */
+    volatile uint8_t   dummy265[248];                          /*                  */
+
+/* end of struct st_scux_from_opcir_opc0_n */
+
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_3;                           /*  OPCIR_OPC0_3    */
+    volatile uint32_t  OPSLR_OPC0_3;                           /*  OPSLR_OPC0_3    */
+    volatile uint8_t   dummy266[248];                          /*                  */
+
+/* end of struct st_scux_from_opcir_opc0_n */
+
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
+    volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
+    volatile uint32_t  DRQSR_FFD0_0;                           /*  DRQSR_FFD0_0    */
+    volatile uint32_t  FFDPR_FFD0_0;                           /*  FFDPR_FFD0_0    */
+    volatile uint32_t  FFDBR_FFD0_0;                           /*  FFDBR_FFD0_0    */
+    volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
+    volatile uint8_t   dummy267[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
+
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy268[224];                          /*                  */
+
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_1;                           /*  FFDIR_FFD0_1    */
+    volatile uint32_t  FDAIR_FFD0_1;                           /*  FDAIR_FFD0_1    */
+    volatile uint32_t  DRQSR_FFD0_1;                           /*  DRQSR_FFD0_1    */
+    volatile uint32_t  FFDPR_FFD0_1;                           /*  FFDPR_FFD0_1    */
+    volatile uint32_t  FFDBR_FFD0_1;                           /*  FFDBR_FFD0_1    */
+    volatile uint32_t  DEVMR_FFD0_1;                           /*  DEVMR_FFD0_1    */
+    volatile uint8_t   dummy269[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_1;                           /*  DEVCR_FFD0_1    */
+
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy270[224];                          /*                  */
+
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_2;                           /*  FFDIR_FFD0_2    */
+    volatile uint32_t  FDAIR_FFD0_2;                           /*  FDAIR_FFD0_2    */
+    volatile uint32_t  DRQSR_FFD0_2;                           /*  DRQSR_FFD0_2    */
+    volatile uint32_t  FFDPR_FFD0_2;                           /*  FFDPR_FFD0_2    */
+    volatile uint32_t  FFDBR_FFD0_2;                           /*  FFDBR_FFD0_2    */
+    volatile uint32_t  DEVMR_FFD0_2;                           /*  DEVMR_FFD0_2    */
+    volatile uint8_t   dummy271[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_2;                           /*  DEVCR_FFD0_2    */
+
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy272[224];                          /*                  */
+
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_3;                           /*  FFDIR_FFD0_3    */
+    volatile uint32_t  FDAIR_FFD0_3;                           /*  FDAIR_FFD0_3    */
+    volatile uint32_t  DRQSR_FFD0_3;                           /*  DRQSR_FFD0_3    */
+    volatile uint32_t  FFDPR_FFD0_3;                           /*  FFDPR_FFD0_3    */
+    volatile uint32_t  FFDBR_FFD0_3;                           /*  FFDBR_FFD0_3    */
+    volatile uint32_t  DEVMR_FFD0_3;                           /*  DEVMR_FFD0_3    */
+    volatile uint8_t   dummy273[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_3;                           /*  DEVCR_FFD0_3    */
+
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy274[224];                          /*                  */
+
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
+    volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
+    volatile uint32_t  URQSR_FFU0_0;                           /*  URQSR_FFU0_0    */
+    volatile uint32_t  FFUPR_FFU0_0;                           /*  FFUPR_FFU0_0    */
+    volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
+    volatile uint8_t   dummy275[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
+
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy276[228];                          /*                  */
+
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_1;                           /*  FFUIR_FFU0_1    */
+    volatile uint32_t  FUAIR_FFU0_1;                           /*  FUAIR_FFU0_1    */
+    volatile uint32_t  URQSR_FFU0_1;                           /*  URQSR_FFU0_1    */
+    volatile uint32_t  FFUPR_FFU0_1;                           /*  FFUPR_FFU0_1    */
+    volatile uint32_t  UEVMR_FFU0_1;                           /*  UEVMR_FFU0_1    */
+    volatile uint8_t   dummy277[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_1;                           /*  UEVCR_FFU0_1    */
+
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy278[228];                          /*                  */
+
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_2;                           /*  FFUIR_FFU0_2    */
+    volatile uint32_t  FUAIR_FFU0_2;                           /*  FUAIR_FFU0_2    */
+    volatile uint32_t  URQSR_FFU0_2;                           /*  URQSR_FFU0_2    */
+    volatile uint32_t  FFUPR_FFU0_2;                           /*  FFUPR_FFU0_2    */
+    volatile uint32_t  UEVMR_FFU0_2;                           /*  UEVMR_FFU0_2    */
+    volatile uint8_t   dummy279[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_2;                           /*  UEVCR_FFU0_2    */
+
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy280[228];                          /*                  */
+
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_3;                           /*  FFUIR_FFU0_3    */
+    volatile uint32_t  FUAIR_FFU0_3;                           /*  FUAIR_FFU0_3    */
+    volatile uint32_t  URQSR_FFU0_3;                           /*  URQSR_FFU0_3    */
+    volatile uint32_t  FFUPR_FFU0_3;                           /*  FFUPR_FFU0_3    */
+    volatile uint32_t  UEVMR_FFU0_3;                           /*  UEVMR_FFU0_3    */
+    volatile uint8_t   dummy281[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_3;                           /*  UEVCR_FFU0_3    */
+
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy282[228];                          /*                  */
+
+/* start of struct st_scux_from_srcir0_2src0_n */
+    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
+    volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
+    volatile uint32_t  SRCBR0_2SRC0_0;                         /*  SRCBR0_2SRC0_0  */
+    volatile uint32_t  IFSCR0_2SRC0_0;                         /*  IFSCR0_2SRC0_0  */
+    volatile uint32_t  IFSVR0_2SRC0_0;                         /*  IFSVR0_2SRC0_0  */
+    volatile uint32_t  SRCCR0_2SRC0_0;                         /*  SRCCR0_2SRC0_0  */
+    volatile uint32_t  MNFSR0_2SRC0_0;                         /*  MNFSR0_2SRC0_0  */
+    volatile uint32_t  BFSSR0_2SRC0_0;                         /*  BFSSR0_2SRC0_0  */
+    volatile uint32_t  SC2SR0_2SRC0_0;                         /*  SC2SR0_2SRC0_0  */
+    volatile uint32_t  WATSR0_2SRC0_0;                         /*  WATSR0_2SRC0_0  */
+    volatile uint32_t  SEVMR0_2SRC0_0;                         /*  SEVMR0_2SRC0_0  */
+    volatile uint8_t   dummy283[4];                            /*                  */
+    volatile uint32_t  SEVCR0_2SRC0_0;                         /*  SEVCR0_2SRC0_0  */
+    volatile uint32_t  SRCIR1_2SRC0_0;                         /*  SRCIR1_2SRC0_0  */
+    volatile uint32_t  SADIR1_2SRC0_0;                         /*  SADIR1_2SRC0_0  */
+    volatile uint32_t  SRCBR1_2SRC0_0;                         /*  SRCBR1_2SRC0_0  */
+    volatile uint32_t  IFSCR1_2SRC0_0;                         /*  IFSCR1_2SRC0_0  */
+    volatile uint32_t  IFSVR1_2SRC0_0;                         /*  IFSVR1_2SRC0_0  */
+    volatile uint32_t  SRCCR1_2SRC0_0;                         /*  SRCCR1_2SRC0_0  */
+    volatile uint32_t  MNFSR1_2SRC0_0;                         /*  MNFSR1_2SRC0_0  */
+    volatile uint32_t  BFSSR1_2SRC0_0;                         /*  BFSSR1_2SRC0_0  */
+    volatile uint32_t  SC2SR1_2SRC0_0;                         /*  SC2SR1_2SRC0_0  */
+    volatile uint32_t  WATSR1_2SRC0_0;                         /*  WATSR1_2SRC0_0  */
+    volatile uint32_t  SEVMR1_2SRC0_0;                         /*  SEVMR1_2SRC0_0  */
+    volatile uint8_t   dummy284[4];                            /*                  */
+    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
+    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
+
+/* end of struct st_scux_from_srcir0_2src0_n */
+    volatile uint8_t   dummy285[148];                          /*                  */
+
+/* start of struct st_scux_from_srcir0_2src0_n */
+    volatile uint32_t  SRCIR0_2SRC0_1;                         /*  SRCIR0_2SRC0_1  */
+    volatile uint32_t  SADIR0_2SRC0_1;                         /*  SADIR0_2SRC0_1  */
+    volatile uint32_t  SRCBR0_2SRC0_1;                         /*  SRCBR0_2SRC0_1  */
+    volatile uint32_t  IFSCR0_2SRC0_1;                         /*  IFSCR0_2SRC0_1  */
+    volatile uint32_t  IFSVR0_2SRC0_1;                         /*  IFSVR0_2SRC0_1  */
+    volatile uint32_t  SRCCR0_2SRC0_1;                         /*  SRCCR0_2SRC0_1  */
+    volatile uint32_t  MNFSR0_2SRC0_1;                         /*  MNFSR0_2SRC0_1  */
+    volatile uint32_t  BFSSR0_2SRC0_1;                         /*  BFSSR0_2SRC0_1  */
+    volatile uint32_t  SC2SR0_2SRC0_1;                         /*  SC2SR0_2SRC0_1  */
+    volatile uint32_t  WATSR0_2SRC0_1;                         /*  WATSR0_2SRC0_1  */
+    volatile uint32_t  SEVMR0_2SRC0_1;                         /*  SEVMR0_2SRC0_1  */
+    volatile uint8_t   dummy286[4];                            /*                  */
+    volatile uint32_t  SEVCR0_2SRC0_1;                         /*  SEVCR0_2SRC0_1  */
+    volatile uint32_t  SRCIR1_2SRC0_1;                         /*  SRCIR1_2SRC0_1  */
+    volatile uint32_t  SADIR1_2SRC0_1;                         /*  SADIR1_2SRC0_1  */
+    volatile uint32_t  SRCBR1_2SRC0_1;                         /*  SRCBR1_2SRC0_1  */
+    volatile uint32_t  IFSCR1_2SRC0_1;                         /*  IFSCR1_2SRC0_1  */
+    volatile uint32_t  IFSVR1_2SRC0_1;                         /*  IFSVR1_2SRC0_1  */
+    volatile uint32_t  SRCCR1_2SRC0_1;                         /*  SRCCR1_2SRC0_1  */
+    volatile uint32_t  MNFSR1_2SRC0_1;                         /*  MNFSR1_2SRC0_1  */
+    volatile uint32_t  BFSSR1_2SRC0_1;                         /*  BFSSR1_2SRC0_1  */
+    volatile uint32_t  SC2SR1_2SRC0_1;                         /*  SC2SR1_2SRC0_1  */
+    volatile uint32_t  WATSR1_2SRC0_1;                         /*  WATSR1_2SRC0_1  */
+    volatile uint32_t  SEVMR1_2SRC0_1;                         /*  SEVMR1_2SRC0_1  */
+    volatile uint8_t   dummy287[4];                            /*                  */
+    volatile uint32_t  SEVCR1_2SRC0_1;                         /*  SEVCR1_2SRC0_1  */
+    volatile uint32_t  SRCIRR_2SRC0_1;                         /*  SRCIRR_2SRC0_1  */
+
+/* end of struct st_scux_from_srcir0_2src0_n */
+    volatile uint8_t   dummy288[148];                          /*                  */
+
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
+    volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
+    volatile uint32_t  DVUBR_DVU0_0;                           /*  DVUBR_DVU0_0    */
+    volatile uint32_t  DVUCR_DVU0_0;                           /*  DVUCR_DVU0_0    */
+    volatile uint32_t  ZCMCR_DVU0_0;                           /*  ZCMCR_DVU0_0    */
+    volatile uint32_t  VRCTR_DVU0_0;                           /*  VRCTR_DVU0_0    */
+    volatile uint32_t  VRPDR_DVU0_0;                           /*  VRPDR_DVU0_0    */
+    volatile uint32_t  VRDBR_DVU0_0;                           /*  VRDBR_DVU0_0    */
+    volatile uint32_t  VRWTR_DVU0_0;                           /*  VRWTR_DVU0_0    */
+    volatile uint32_t  VOL0R_DVU0_0;                           /*  VOL0R_DVU0_0    */
+    volatile uint32_t  VOL1R_DVU0_0;                           /*  VOL1R_DVU0_0    */
+    volatile uint32_t  VOL2R_DVU0_0;                           /*  VOL2R_DVU0_0    */
+    volatile uint32_t  VOL3R_DVU0_0;                           /*  VOL3R_DVU0_0    */
+    volatile uint32_t  VOL4R_DVU0_0;                           /*  VOL4R_DVU0_0    */
+    volatile uint32_t  VOL5R_DVU0_0;                           /*  VOL5R_DVU0_0    */
+    volatile uint32_t  VOL6R_DVU0_0;                           /*  VOL6R_DVU0_0    */
+    volatile uint32_t  VOL7R_DVU0_0;                           /*  VOL7R_DVU0_0    */
+    volatile uint32_t  DVUER_DVU0_0;                           /*  DVUER_DVU0_0    */
+    volatile uint32_t  DVUSR_DVU0_0;                           /*  DVUSR_DVU0_0    */
+    volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
+    volatile uint8_t   dummy289[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
+
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy290[168];                          /*                  */
+
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_1;                           /*  DVUIR_DVU0_1    */
+    volatile uint32_t  VADIR_DVU0_1;                           /*  VADIR_DVU0_1    */
+    volatile uint32_t  DVUBR_DVU0_1;                           /*  DVUBR_DVU0_1    */
+    volatile uint32_t  DVUCR_DVU0_1;                           /*  DVUCR_DVU0_1    */
+    volatile uint32_t  ZCMCR_DVU0_1;                           /*  ZCMCR_DVU0_1    */
+    volatile uint32_t  VRCTR_DVU0_1;                           /*  VRCTR_DVU0_1    */
+    volatile uint32_t  VRPDR_DVU0_1;                           /*  VRPDR_DVU0_1    */
+    volatile uint32_t  VRDBR_DVU0_1;                           /*  VRDBR_DVU0_1    */
+    volatile uint32_t  VRWTR_DVU0_1;                           /*  VRWTR_DVU0_1    */
+    volatile uint32_t  VOL0R_DVU0_1;                           /*  VOL0R_DVU0_1    */
+    volatile uint32_t  VOL1R_DVU0_1;                           /*  VOL1R_DVU0_1    */
+    volatile uint32_t  VOL2R_DVU0_1;                           /*  VOL2R_DVU0_1    */
+    volatile uint32_t  VOL3R_DVU0_1;                           /*  VOL3R_DVU0_1    */
+    volatile uint32_t  VOL4R_DVU0_1;                           /*  VOL4R_DVU0_1    */
+    volatile uint32_t  VOL5R_DVU0_1;                           /*  VOL5R_DVU0_1    */
+    volatile uint32_t  VOL6R_DVU0_1;                           /*  VOL6R_DVU0_1    */
+    volatile uint32_t  VOL7R_DVU0_1;                           /*  VOL7R_DVU0_1    */
+    volatile uint32_t  DVUER_DVU0_1;                           /*  DVUER_DVU0_1    */
+    volatile uint32_t  DVUSR_DVU0_1;                           /*  DVUSR_DVU0_1    */
+    volatile uint32_t  VEVMR_DVU0_1;                           /*  VEVMR_DVU0_1    */
+    volatile uint8_t   dummy291[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_1;                           /*  VEVCR_DVU0_1    */
+
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy292[168];                          /*                  */
+
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_2;                           /*  DVUIR_DVU0_2    */
+    volatile uint32_t  VADIR_DVU0_2;                           /*  VADIR_DVU0_2    */
+    volatile uint32_t  DVUBR_DVU0_2;                           /*  DVUBR_DVU0_2    */
+    volatile uint32_t  DVUCR_DVU0_2;                           /*  DVUCR_DVU0_2    */
+    volatile uint32_t  ZCMCR_DVU0_2;                           /*  ZCMCR_DVU0_2    */
+    volatile uint32_t  VRCTR_DVU0_2;                           /*  VRCTR_DVU0_2    */
+    volatile uint32_t  VRPDR_DVU0_2;                           /*  VRPDR_DVU0_2    */
+    volatile uint32_t  VRDBR_DVU0_2;                           /*  VRDBR_DVU0_2    */
+    volatile uint32_t  VRWTR_DVU0_2;                           /*  VRWTR_DVU0_2    */
+    volatile uint32_t  VOL0R_DVU0_2;                           /*  VOL0R_DVU0_2    */
+    volatile uint32_t  VOL1R_DVU0_2;                           /*  VOL1R_DVU0_2    */
+    volatile uint32_t  VOL2R_DVU0_2;                           /*  VOL2R_DVU0_2    */
+    volatile uint32_t  VOL3R_DVU0_2;                           /*  VOL3R_DVU0_2    */
+    volatile uint32_t  VOL4R_DVU0_2;                           /*  VOL4R_DVU0_2    */
+    volatile uint32_t  VOL5R_DVU0_2;                           /*  VOL5R_DVU0_2    */
+    volatile uint32_t  VOL6R_DVU0_2;                           /*  VOL6R_DVU0_2    */
+    volatile uint32_t  VOL7R_DVU0_2;                           /*  VOL7R_DVU0_2    */
+    volatile uint32_t  DVUER_DVU0_2;                           /*  DVUER_DVU0_2    */
+    volatile uint32_t  DVUSR_DVU0_2;                           /*  DVUSR_DVU0_2    */
+    volatile uint32_t  VEVMR_DVU0_2;                           /*  VEVMR_DVU0_2    */
+    volatile uint8_t   dummy293[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_2;                           /*  VEVCR_DVU0_2    */
+
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy294[168];                          /*                  */
+
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_3;                           /*  DVUIR_DVU0_3    */
+    volatile uint32_t  VADIR_DVU0_3;                           /*  VADIR_DVU0_3    */
+    volatile uint32_t  DVUBR_DVU0_3;                           /*  DVUBR_DVU0_3    */
+    volatile uint32_t  DVUCR_DVU0_3;                           /*  DVUCR_DVU0_3    */
+    volatile uint32_t  ZCMCR_DVU0_3;                           /*  ZCMCR_DVU0_3    */
+    volatile uint32_t  VRCTR_DVU0_3;                           /*  VRCTR_DVU0_3    */
+    volatile uint32_t  VRPDR_DVU0_3;                           /*  VRPDR_DVU0_3    */
+    volatile uint32_t  VRDBR_DVU0_3;                           /*  VRDBR_DVU0_3    */
+    volatile uint32_t  VRWTR_DVU0_3;                           /*  VRWTR_DVU0_3    */
+    volatile uint32_t  VOL0R_DVU0_3;                           /*  VOL0R_DVU0_3    */
+    volatile uint32_t  VOL1R_DVU0_3;                           /*  VOL1R_DVU0_3    */
+    volatile uint32_t  VOL2R_DVU0_3;                           /*  VOL2R_DVU0_3    */
+    volatile uint32_t  VOL3R_DVU0_3;                           /*  VOL3R_DVU0_3    */
+    volatile uint32_t  VOL4R_DVU0_3;                           /*  VOL4R_DVU0_3    */
+    volatile uint32_t  VOL5R_DVU0_3;                           /*  VOL5R_DVU0_3    */
+    volatile uint32_t  VOL6R_DVU0_3;                           /*  VOL6R_DVU0_3    */
+    volatile uint32_t  VOL7R_DVU0_3;                           /*  VOL7R_DVU0_3    */
+    volatile uint32_t  DVUER_DVU0_3;                           /*  DVUER_DVU0_3    */
+    volatile uint32_t  DVUSR_DVU0_3;                           /*  DVUSR_DVU0_3    */
+    volatile uint32_t  VEVMR_DVU0_3;                           /*  VEVMR_DVU0_3    */
+    volatile uint8_t   dummy295[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_3;                           /*  VEVCR_DVU0_3    */
+
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy296[168];                          /*                  */
+    volatile uint32_t  MIXIR_MIX0_0;                           /*  MIXIR_MIX0_0    */
+    volatile uint32_t  MADIR_MIX0_0;                           /*  MADIR_MIX0_0    */
+    volatile uint32_t  MIXBR_MIX0_0;                           /*  MIXBR_MIX0_0    */
+    volatile uint32_t  MIXMR_MIX0_0;                           /*  MIXMR_MIX0_0    */
+    volatile uint32_t  MVPDR_MIX0_0;                           /*  MVPDR_MIX0_0    */
+    volatile uint32_t  MDBAR_MIX0_0;                           /*  MDBAR_MIX0_0    */
+    volatile uint32_t  MDBBR_MIX0_0;                           /*  MDBBR_MIX0_0    */
+    volatile uint32_t  MDBCR_MIX0_0;                           /*  MDBCR_MIX0_0    */
+    volatile uint32_t  MDBDR_MIX0_0;                           /*  MDBDR_MIX0_0    */
+    volatile uint32_t  MDBER_MIX0_0;                           /*  MDBER_MIX0_0    */
+    volatile uint32_t  MIXSR_MIX0_0;                           /*  MIXSR_MIX0_0    */
+    volatile uint8_t   dummy297[212];                          /*                  */
+    volatile uint32_t  SWRSR_CIM;                              /*  SWRSR_CIM       */
+    volatile uint32_t  DMACR_CIM;                              /*  DMACR_CIM       */
+
+/* #define SCUX_DMATDnCIM_COUNT (4) */
+    union iodefine_reg32_16_t  DMATD0_CIM;                 /*  DMATD0_CIM      */
+    union iodefine_reg32_16_t  DMATD1_CIM;                 /*  DMATD1_CIM      */
+    union iodefine_reg32_16_t  DMATD2_CIM;                 /*  DMATD2_CIM      */
+    union iodefine_reg32_16_t  DMATD3_CIM;                 /*  DMATD3_CIM      */
+
+/* #define SCUX_DMATUnCIM_COUNT (4) */
+    union iodefine_reg32_16_t  DMATU0_CIM;                 /*  DMATU0_CIM      */
+    union iodefine_reg32_16_t  DMATU1_CIM;                 /*  DMATU1_CIM      */
+    union iodefine_reg32_16_t  DMATU2_CIM;                 /*  DMATU2_CIM      */
+    union iodefine_reg32_16_t  DMATU3_CIM;                 /*  DMATU3_CIM      */
+    
+    volatile uint8_t   dummy298[16];                           /*                  */
+    volatile uint32_t  SSIRSEL_CIM;                            /*  SSIRSEL_CIM     */
+
+/* #define SCUX_FDTSELnCIM_COUNT (4) */
+    volatile uint32_t  FDTSEL0_CIM;                            /*  FDTSEL0_CIM     */
+    volatile uint32_t  FDTSEL1_CIM;                            /*  FDTSEL1_CIM     */
+    volatile uint32_t  FDTSEL2_CIM;                            /*  FDTSEL2_CIM     */
+    volatile uint32_t  FDTSEL3_CIM;                            /*  FDTSEL3_CIM     */
+
+/* #define SCUX_FUTSELnCIM_COUNT (4) */
+    volatile uint32_t  FUTSEL0_CIM;                            /*  FUTSEL0_CIM     */
+    volatile uint32_t  FUTSEL1_CIM;                            /*  FUTSEL1_CIM     */
+    volatile uint32_t  FUTSEL2_CIM;                            /*  FUTSEL2_CIM     */
+    volatile uint32_t  FUTSEL3_CIM;                            /*  FUTSEL3_CIM     */
+    volatile uint32_t  SSIPMD_CIM;                             /*  SSIPMD_CIM      */
+    volatile uint32_t  SSICTRL_CIM;                            /*  SSICTRL_CIM     */
+
+/* #define SCUX_SRCRSELnCIM_COUNT (4) */
+    volatile uint32_t  SRCRSEL0_CIM;                           /*  SRCRSEL0_CIM    */
+    volatile uint32_t  SRCRSEL1_CIM;                           /*  SRCRSEL1_CIM    */
+    volatile uint32_t  SRCRSEL2_CIM;                           /*  SRCRSEL2_CIM    */
+    volatile uint32_t  SRCRSEL3_CIM;                           /*  SRCRSEL3_CIM    */
+    volatile uint32_t  MIXRSEL_CIM;                            /*  MIXRSEL_CIM     */
+} r_io_scux_t;
+
+
+typedef struct st_scux_from_ipcir_ipc0_n
+{
+ 
+    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
+    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
+    volatile uint8_t   dummy1[248];                            /*                  */
+} r_io_scux_from_ipcir_ipc0_n_t;
+
+
+typedef struct st_scux_from_opcir_opc0_n
+{
+ 
+    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
+    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
+    volatile uint8_t   dummy1[248];                            /*                  */
+} r_io_scux_from_opcir_opc0_n_t;
+
+
+typedef struct st_scux_from_ffdir_ffd0_n
+{
+ 
+    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
+    volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
+    volatile uint32_t  DRQSR_FFD0_0;                           /*  DRQSR_FFD0_0    */
+    volatile uint32_t  FFDPR_FFD0_0;                           /*  FFDPR_FFD0_0    */
+    volatile uint32_t  FFDBR_FFD0_0;                           /*  FFDBR_FFD0_0    */
+    volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
+} r_io_scux_from_ffdir_ffd0_n_t;
+
+
+typedef struct st_scux_from_ffuir_ffu0_n
+{
+ 
+    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
+    volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
+    volatile uint32_t  URQSR_FFU0_0;                           /*  URQSR_FFU0_0    */
+    volatile uint32_t  FFUPR_FFU0_0;                           /*  FFUPR_FFU0_0    */
+    volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
+} r_io_scux_from_ffuir_ffu0_n_t;
+
+
+typedef struct st_scux_from_srcir0_2src0_n
+{
+ 
+    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
+    volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
+    volatile uint32_t  SRCBR0_2SRC0_0;                         /*  SRCBR0_2SRC0_0  */
+    volatile uint32_t  IFSCR0_2SRC0_0;                         /*  IFSCR0_2SRC0_0  */
+    volatile uint32_t  IFSVR0_2SRC0_0;                         /*  IFSVR0_2SRC0_0  */
+    volatile uint32_t  SRCCR0_2SRC0_0;                         /*  SRCCR0_2SRC0_0  */
+    volatile uint32_t  MNFSR0_2SRC0_0;                         /*  MNFSR0_2SRC0_0  */
+    volatile uint32_t  BFSSR0_2SRC0_0;                         /*  BFSSR0_2SRC0_0  */
+    volatile uint32_t  SC2SR0_2SRC0_0;                         /*  SC2SR0_2SRC0_0  */
+    volatile uint32_t  WATSR0_2SRC0_0;                         /*  WATSR0_2SRC0_0  */
+    volatile uint32_t  SEVMR0_2SRC0_0;                         /*  SEVMR0_2SRC0_0  */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  SEVCR0_2SRC0_0;                         /*  SEVCR0_2SRC0_0  */
+    volatile uint32_t  SRCIR1_2SRC0_0;                         /*  SRCIR1_2SRC0_0  */
+    volatile uint32_t  SADIR1_2SRC0_0;                         /*  SADIR1_2SRC0_0  */
+    volatile uint32_t  SRCBR1_2SRC0_0;                         /*  SRCBR1_2SRC0_0  */
+    volatile uint32_t  IFSCR1_2SRC0_0;                         /*  IFSCR1_2SRC0_0  */
+    volatile uint32_t  IFSVR1_2SRC0_0;                         /*  IFSVR1_2SRC0_0  */
+    volatile uint32_t  SRCCR1_2SRC0_0;                         /*  SRCCR1_2SRC0_0  */
+    volatile uint32_t  MNFSR1_2SRC0_0;                         /*  MNFSR1_2SRC0_0  */
+    volatile uint32_t  BFSSR1_2SRC0_0;                         /*  BFSSR1_2SRC0_0  */
+    volatile uint32_t  SC2SR1_2SRC0_0;                         /*  SC2SR1_2SRC0_0  */
+    volatile uint32_t  WATSR1_2SRC0_0;                         /*  WATSR1_2SRC0_0  */
+    volatile uint32_t  SEVMR1_2SRC0_0;                         /*  SEVMR1_2SRC0_0  */
+    volatile uint8_t   dummy2[4];                              /*                  */
+    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
+    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
+} r_io_scux_from_srcir0_2src0_n_t;
+
+
+typedef struct st_scux_from_dvuir_dvu0_n
+{
+ 
+    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
+    volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
+    volatile uint32_t  DVUBR_DVU0_0;                           /*  DVUBR_DVU0_0    */
+    volatile uint32_t  DVUCR_DVU0_0;                           /*  DVUCR_DVU0_0    */
+    volatile uint32_t  ZCMCR_DVU0_0;                           /*  ZCMCR_DVU0_0    */
+    volatile uint32_t  VRCTR_DVU0_0;                           /*  VRCTR_DVU0_0    */
+    volatile uint32_t  VRPDR_DVU0_0;                           /*  VRPDR_DVU0_0    */
+    volatile uint32_t  VRDBR_DVU0_0;                           /*  VRDBR_DVU0_0    */
+    volatile uint32_t  VRWTR_DVU0_0;                           /*  VRWTR_DVU0_0    */
+    volatile uint32_t  VOL0R_DVU0_0;                           /*  VOL0R_DVU0_0    */
+    volatile uint32_t  VOL1R_DVU0_0;                           /*  VOL1R_DVU0_0    */
+    volatile uint32_t  VOL2R_DVU0_0;                           /*  VOL2R_DVU0_0    */
+    volatile uint32_t  VOL3R_DVU0_0;                           /*  VOL3R_DVU0_0    */
+    volatile uint32_t  VOL4R_DVU0_0;                           /*  VOL4R_DVU0_0    */
+    volatile uint32_t  VOL5R_DVU0_0;                           /*  VOL5R_DVU0_0    */
+    volatile uint32_t  VOL6R_DVU0_0;                           /*  VOL6R_DVU0_0    */
+    volatile uint32_t  VOL7R_DVU0_0;                           /*  VOL7R_DVU0_0    */
+    volatile uint32_t  DVUER_DVU0_0;                           /*  DVUER_DVU0_0    */
+    volatile uint32_t  DVUSR_DVU0_0;                           /*  DVUSR_DVU0_0    */
+    volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
+} r_io_scux_from_dvuir_dvu0_n_t;
+
+
+/* Channel array defines of SCUX (2)*/
+#ifdef  DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_dvuir_dvu0_n*  SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_srcir0_2src0_n*  SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffuir_ffu0_n*  SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffdir_ffd0_n*  SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_opcir_opc0_n*  SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ipcir_ipc0_n*  SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
+/* End of channel array defines of SCUX (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h	(revision 374)
@@ -0,0 +1,107 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : sdg_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef SDG_IODEFINE_H
+#define SDG_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define SDG0    (*(struct st_sdg     *)0xFCFF4800uL) /* SDG0 */
+#define SDG1    (*(struct st_sdg     *)0xFCFF4A00uL) /* SDG1 */
+#define SDG2    (*(struct st_sdg     *)0xFCFF4C00uL) /* SDG2 */
+#define SDG3    (*(struct st_sdg     *)0xFCFF4E00uL) /* SDG3 */
+
+
+/* Start of channel array defines of SDG */
+
+/* Channel array defines of SDG */
+/*(Sample) value = SDG[ channel ]->SGCR1; */
+#define SDG_COUNT  (4)
+#define SDG_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SDG0, &SDG1, &SDG2, &SDG3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SDG */
+
+
+#define SGCR1_0 (SDG0.SGCR1)
+#define SGCSR_0 (SDG0.SGCSR)
+#define SGCR2_0 (SDG0.SGCR2)
+#define SGLR_0 (SDG0.SGLR)
+#define SGTFR_0 (SDG0.SGTFR)
+#define SGSFR_0 (SDG0.SGSFR)
+#define SGCR1_1 (SDG1.SGCR1)
+#define SGCSR_1 (SDG1.SGCSR)
+#define SGCR2_1 (SDG1.SGCR2)
+#define SGLR_1 (SDG1.SGLR)
+#define SGTFR_1 (SDG1.SGTFR)
+#define SGSFR_1 (SDG1.SGSFR)
+#define SGCR1_2 (SDG2.SGCR1)
+#define SGCSR_2 (SDG2.SGCSR)
+#define SGCR2_2 (SDG2.SGCR2)
+#define SGLR_2 (SDG2.SGLR)
+#define SGTFR_2 (SDG2.SGTFR)
+#define SGSFR_2 (SDG2.SGSFR)
+#define SGCR1_3 (SDG3.SGCR1)
+#define SGCSR_3 (SDG3.SGCSR)
+#define SGCR2_3 (SDG3.SGCR2)
+#define SGLR_3 (SDG3.SGLR)
+#define SGTFR_3 (SDG3.SGTFR)
+#define SGSFR_3 (SDG3.SGSFR)
+
+
+typedef struct st_sdg
+{
+                                                           /* SDG              */
+    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
+    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
+    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
+    volatile uint8_t   SGLR;                                   /*  SGLR            */
+    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
+    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
+} r_io_sdg_t;
+
+
+/* Channel array defines of SDG (2)*/
+#ifdef  DECLARE_SDG_CHANNELS
+volatile struct st_sdg*  SDG[ SDG_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SDG_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SDG_CHANNELS */
+/* End of channel array defines of SDG (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h	(revision 374)
@@ -0,0 +1,79 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spdif_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef SPDIF_IODEFINE_H
+#define SPDIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
+
+
+#define SPDIFTLCA (SPDIF.TLCA)
+#define SPDIFTRCA (SPDIF.TRCA)
+#define SPDIFTLCS (SPDIF.TLCS)
+#define SPDIFTRCS (SPDIF.TRCS)
+#define SPDIFTUI (SPDIF.TUI)
+#define SPDIFRLCA (SPDIF.RLCA)
+#define SPDIFRRCA (SPDIF.RRCA)
+#define SPDIFRLCS (SPDIF.RLCS)
+#define SPDIFRRCS (SPDIF.RRCS)
+#define SPDIFRUI (SPDIF.RUI)
+#define SPDIFCTRL (SPDIF.CTRL)
+#define SPDIFSTAT (SPDIF.STAT)
+#define SPDIFTDAD (SPDIF.TDAD)
+#define SPDIFRDAD (SPDIF.RDAD)
+
+
+typedef struct st_spdif
+{
+                                                           /* SPDIF            */
+    volatile uint32_t  TLCA;                                   /*  TLCA            */
+    volatile uint32_t  TRCA;                                   /*  TRCA            */
+    volatile uint32_t  TLCS;                                   /*  TLCS            */
+    volatile uint32_t  TRCS;                                   /*  TRCS            */
+    volatile uint32_t  TUI;                                    /*  TUI             */
+    volatile uint32_t  RLCA;                                   /*  RLCA            */
+    volatile uint32_t  RRCA;                                   /*  RRCA            */
+    volatile uint32_t  RLCS;                                   /*  RLCS            */
+    volatile uint32_t  RRCS;                                   /*  RRCS            */
+    volatile uint32_t  RUI;                                    /*  RUI             */
+    volatile uint32_t  CTRL;                                   /*  CTRL            */
+    volatile uint32_t  STAT;                                   /*  STAT            */
+    volatile uint32_t  TDAD;                                   /*  TDAD            */
+    volatile uint32_t  RDAD;                                   /*  RDAD            */
+} r_io_spdif_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h	(revision 374)
@@ -0,0 +1,199 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spibsc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef SPIBSC_IODEFINE_H
+#define SPIBSC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
+#define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
+
+
+/* Start of channel array defines of SPIBSC */
+
+/* Channel array defines of SPIBSC */
+/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
+#define SPIBSC_COUNT  (2)
+#define SPIBSC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SPIBSC0, &SPIBSC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SPIBSC */
+
+
+#define CMNCR_0 (SPIBSC0.CMNCR)
+#define SSLDR_0 (SPIBSC0.SSLDR)
+#define SPBCR_0 (SPIBSC0.SPBCR)
+#define DRCR_0 (SPIBSC0.DRCR)
+#define DRCMR_0 (SPIBSC0.DRCMR)
+#define DREAR_0 (SPIBSC0.DREAR)
+#define DROPR_0 (SPIBSC0.DROPR)
+#define DRENR_0 (SPIBSC0.DRENR)
+#define SMCR_0 (SPIBSC0.SMCR)
+#define SMCMR_0 (SPIBSC0.SMCMR)
+#define SMADR_0 (SPIBSC0.SMADR)
+#define SMOPR_0 (SPIBSC0.SMOPR)
+#define SMENR_0 (SPIBSC0.SMENR)
+#define SMRDR0_0   (SPIBSC0.SMRDR0.UINT32)
+#define SMRDR0_0L  (SPIBSC0.SMRDR0.UINT16[R_IO_L])
+#define SMRDR0_0H  (SPIBSC0.SMRDR0.UINT16[R_IO_H])
+#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL])
+#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH])
+#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL])
+#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH])
+#define SMRDR1_0   (SPIBSC0.SMRDR1.UINT32)
+#define SMRDR1_0L  (SPIBSC0.SMRDR1.UINT16[R_IO_L])
+#define SMRDR1_0H  (SPIBSC0.SMRDR1.UINT16[R_IO_H])
+#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL])
+#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH])
+#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL])
+#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH])
+#define SMWDR0_0   (SPIBSC0.SMWDR0.UINT32)
+#define SMWDR0_0L  (SPIBSC0.SMWDR0.UINT16[R_IO_L])
+#define SMWDR0_0H  (SPIBSC0.SMWDR0.UINT16[R_IO_H])
+#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL])
+#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH])
+#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL])
+#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH])
+#define SMWDR1_0   (SPIBSC0.SMWDR1.UINT32)
+#define SMWDR1_0L  (SPIBSC0.SMWDR1.UINT16[R_IO_L])
+#define SMWDR1_0H  (SPIBSC0.SMWDR1.UINT16[R_IO_H])
+#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL])
+#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH])
+#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL])
+#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH])
+#define CMNSR_0 (SPIBSC0.CMNSR)
+#define CKDLY_0 (SPIBSC0.CKDLY)
+#define DRDMCR_0 (SPIBSC0.DRDMCR)
+#define DRDRENR_0 (SPIBSC0.DRDRENR)
+#define SMDMCR_0 (SPIBSC0.SMDMCR)
+#define SMDRENR_0 (SPIBSC0.SMDRENR)
+#define SPODLY_0 (SPIBSC0.SPODLY)
+#define CMNCR_1 (SPIBSC1.CMNCR)
+#define SSLDR_1 (SPIBSC1.SSLDR)
+#define SPBCR_1 (SPIBSC1.SPBCR)
+#define DRCR_1 (SPIBSC1.DRCR)
+#define DRCMR_1 (SPIBSC1.DRCMR)
+#define DREAR_1 (SPIBSC1.DREAR)
+#define DROPR_1 (SPIBSC1.DROPR)
+#define DRENR_1 (SPIBSC1.DRENR)
+#define SMCR_1 (SPIBSC1.SMCR)
+#define SMCMR_1 (SPIBSC1.SMCMR)
+#define SMADR_1 (SPIBSC1.SMADR)
+#define SMOPR_1 (SPIBSC1.SMOPR)
+#define SMENR_1 (SPIBSC1.SMENR)
+#define SMRDR0_1   (SPIBSC1.SMRDR0.UINT32)
+#define SMRDR0_1L  (SPIBSC1.SMRDR0.UINT16[R_IO_L])
+#define SMRDR0_1H  (SPIBSC1.SMRDR0.UINT16[R_IO_H])
+#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL])
+#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH])
+#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL])
+#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH])
+#define SMRDR1_1   (SPIBSC1.SMRDR1.UINT32)
+#define SMRDR1_1L  (SPIBSC1.SMRDR1.UINT16[R_IO_L])
+#define SMRDR1_1H  (SPIBSC1.SMRDR1.UINT16[R_IO_H])
+#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL])
+#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH])
+#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL])
+#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH])
+#define SMWDR0_1   (SPIBSC1.SMWDR0.UINT32)
+#define SMWDR0_1L  (SPIBSC1.SMWDR0.UINT16[R_IO_L])
+#define SMWDR0_1H  (SPIBSC1.SMWDR0.UINT16[R_IO_H])
+#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL])
+#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH])
+#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL])
+#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH])
+#define SMWDR1_1   (SPIBSC1.SMWDR1.UINT32)
+#define SMWDR1_1L  (SPIBSC1.SMWDR1.UINT16[R_IO_L])
+#define SMWDR1_1H  (SPIBSC1.SMWDR1.UINT16[R_IO_H])
+#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL])
+#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH])
+#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL])
+#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH])
+#define CMNSR_1 (SPIBSC1.CMNSR)
+#define CKDLY_1 (SPIBSC1.CKDLY)
+#define DRDMCR_1 (SPIBSC1.DRDMCR)
+#define DRDRENR_1 (SPIBSC1.DRDRENR)
+#define SMDMCR_1 (SPIBSC1.SMDMCR)
+#define SMDRENR_1 (SPIBSC1.SMDRENR)
+#define SPODLY_1 (SPIBSC1.SPODLY)
+
+
+typedef struct st_spibsc
+{
+                                                           /* SPIBSC           */
+    volatile uint32_t  CMNCR;                                  /*  CMNCR           */
+    volatile uint32_t  SSLDR;                                  /*  SSLDR           */
+    volatile uint32_t  SPBCR;                                  /*  SPBCR           */
+    volatile uint32_t  DRCR;                                   /*  DRCR            */
+    volatile uint32_t  DRCMR;                                  /*  DRCMR           */
+    volatile uint32_t  DREAR;                                  /*  DREAR           */
+    volatile uint32_t  DROPR;                                  /*  DROPR           */
+    volatile uint32_t  DRENR;                                  /*  DRENR           */
+    volatile uint32_t  SMCR;                                   /*  SMCR            */
+    volatile uint32_t  SMCMR;                                  /*  SMCMR           */
+    volatile uint32_t  SMADR;                                  /*  SMADR           */
+    volatile uint32_t  SMOPR;                                  /*  SMOPR           */
+    volatile uint32_t  SMENR;                                  /*  SMENR           */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    union iodefine_reg32_t  SMRDR0;                        /*  SMRDR0          */
+    union iodefine_reg32_t  SMRDR1;                        /*  SMRDR1          */
+    union iodefine_reg32_t  SMWDR0;                        /*  SMWDR0          */
+    union iodefine_reg32_t  SMWDR1;                        /*  SMWDR1          */
+    
+    volatile uint32_t  CMNSR;                                  /*  CMNSR           */
+    volatile uint8_t   dummy2[4];                              /*                  */
+    volatile uint32_t  CKDLY;                                  /*  CKDLY           */
+    volatile uint8_t   dummy3[4];                              /*                  */
+    volatile uint32_t  DRDMCR;                                 /*  DRDMCR          */
+    volatile uint32_t  DRDRENR;                                /*  DRDRENR         */
+    volatile uint32_t  SMDMCR;                                 /*  SMDMCR          */
+    volatile uint32_t  SMDRENR;                                /*  SMDRENR         */
+    volatile uint32_t  SPODLY;                                 /*  SPODLY          */
+} r_io_spibsc_t;
+
+
+/* Channel array defines of SPIBSC (2)*/
+#ifdef  DECLARE_SPIBSC_CHANNELS
+volatile struct st_spibsc*  SPIBSC[ SPIBSC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SPIBSC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SPIBSC_CHANNELS */
+/* End of channel array defines of SPIBSC (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h	(revision 374)
@@ -0,0 +1,150 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ssif_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef SSIF_IODEFINE_H
+#define SSIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
+#define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
+#define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
+#define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
+#define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
+#define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
+
+
+/* Start of channel array defines of SSIF */
+
+/* Channel array defines of SSIF */
+/*(Sample) value = SSIF[ channel ]->SSICR; */
+#define SSIF_COUNT  (6)
+#define SSIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SSIF */
+
+
+#define SSICR_0 (SSIF0.SSICR)
+#define SSISR_0 (SSIF0.SSISR)
+#define SSIFCR_0 (SSIF0.SSIFCR)
+#define SSIFSR_0 (SSIF0.SSIFSR)
+#define SSIFTDR_0 (SSIF0.SSIFTDR)
+#define SSIFRDR_0 (SSIF0.SSIFRDR)
+#define SSITDMR_0 (SSIF0.SSITDMR)
+#define SSIFCCR_0 (SSIF0.SSIFCCR)
+#define SSIFCMR_0 (SSIF0.SSIFCMR)
+#define SSIFCSR_0 (SSIF0.SSIFCSR)
+#define SSICR_1 (SSIF1.SSICR)
+#define SSISR_1 (SSIF1.SSISR)
+#define SSIFCR_1 (SSIF1.SSIFCR)
+#define SSIFSR_1 (SSIF1.SSIFSR)
+#define SSIFTDR_1 (SSIF1.SSIFTDR)
+#define SSIFRDR_1 (SSIF1.SSIFRDR)
+#define SSITDMR_1 (SSIF1.SSITDMR)
+#define SSIFCCR_1 (SSIF1.SSIFCCR)
+#define SSIFCMR_1 (SSIF1.SSIFCMR)
+#define SSIFCSR_1 (SSIF1.SSIFCSR)
+#define SSICR_2 (SSIF2.SSICR)
+#define SSISR_2 (SSIF2.SSISR)
+#define SSIFCR_2 (SSIF2.SSIFCR)
+#define SSIFSR_2 (SSIF2.SSIFSR)
+#define SSIFTDR_2 (SSIF2.SSIFTDR)
+#define SSIFRDR_2 (SSIF2.SSIFRDR)
+#define SSITDMR_2 (SSIF2.SSITDMR)
+#define SSIFCCR_2 (SSIF2.SSIFCCR)
+#define SSIFCMR_2 (SSIF2.SSIFCMR)
+#define SSIFCSR_2 (SSIF2.SSIFCSR)
+#define SSICR_3 (SSIF3.SSICR)
+#define SSISR_3 (SSIF3.SSISR)
+#define SSIFCR_3 (SSIF3.SSIFCR)
+#define SSIFSR_3 (SSIF3.SSIFSR)
+#define SSIFTDR_3 (SSIF3.SSIFTDR)
+#define SSIFRDR_3 (SSIF3.SSIFRDR)
+#define SSITDMR_3 (SSIF3.SSITDMR)
+#define SSIFCCR_3 (SSIF3.SSIFCCR)
+#define SSIFCMR_3 (SSIF3.SSIFCMR)
+#define SSIFCSR_3 (SSIF3.SSIFCSR)
+#define SSICR_4 (SSIF4.SSICR)
+#define SSISR_4 (SSIF4.SSISR)
+#define SSIFCR_4 (SSIF4.SSIFCR)
+#define SSIFSR_4 (SSIF4.SSIFSR)
+#define SSIFTDR_4 (SSIF4.SSIFTDR)
+#define SSIFRDR_4 (SSIF4.SSIFRDR)
+#define SSITDMR_4 (SSIF4.SSITDMR)
+#define SSIFCCR_4 (SSIF4.SSIFCCR)
+#define SSIFCMR_4 (SSIF4.SSIFCMR)
+#define SSIFCSR_4 (SSIF4.SSIFCSR)
+#define SSICR_5 (SSIF5.SSICR)
+#define SSISR_5 (SSIF5.SSISR)
+#define SSIFCR_5 (SSIF5.SSIFCR)
+#define SSIFSR_5 (SSIF5.SSIFSR)
+#define SSIFTDR_5 (SSIF5.SSIFTDR)
+#define SSIFRDR_5 (SSIF5.SSIFRDR)
+#define SSITDMR_5 (SSIF5.SSITDMR)
+#define SSIFCCR_5 (SSIF5.SSIFCCR)
+#define SSIFCMR_5 (SSIF5.SSIFCMR)
+#define SSIFCSR_5 (SSIF5.SSIFCSR)
+
+
+typedef struct st_ssif
+{
+                                                           /* SSIF             */
+    volatile uint32_t  SSICR;                                  /*  SSICR           */
+    volatile uint32_t  SSISR;                                  /*  SSISR           */
+    volatile uint8_t   dummy1[8];                              /*                  */
+    volatile uint32_t  SSIFCR;                                 /*  SSIFCR          */
+    volatile uint32_t  SSIFSR;                                 /*  SSIFSR          */
+    volatile uint32_t  SSIFTDR;                                /*  SSIFTDR         */
+    volatile uint32_t  SSIFRDR;                                /*  SSIFRDR         */
+    volatile uint32_t  SSITDMR;                                /*  SSITDMR         */
+    volatile uint32_t  SSIFCCR;                                /*  SSIFCCR         */
+    volatile uint32_t  SSIFCMR;                                /*  SSIFCMR         */
+    volatile uint32_t  SSIFCSR;                                /*  SSIFCSR         */
+} r_io_ssif_t;
+
+
+/* Channel array defines of SSIF (2)*/
+#ifdef  DECLARE_SSIF_CHANNELS
+volatile struct st_ssif*  SSIF[ SSIF_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SSIF_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SSIF_CHANNELS */
+/* End of channel array defines of SSIF (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h	(revision 374)
@@ -0,0 +1,622 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb20_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef USB20_IODEFINE_H
+#define USB20_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
+#define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
+
+
+/* Start of channel array defines of USB20 */
+
+/* Channel array defines of USB20 */
+/*(Sample) value = USB20[ channel ]->SYSCFG0; */
+#define USB20_COUNT  (2)
+#define USB20_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &USB200, &USB201 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channel array defines of USB20_FROM_D0FIFOB0 */
+/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
+#define USB20_FROM_D0FIFOB0_COUNT  (2)
+#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
+    &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
+#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
+#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
+#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
+
+
+
+
+/* Channel array defines of USB20_FROM_PIPE1ATRE */
+/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
+#define USB20_FROM_PIPE1ATRE_COUNT  (5)
+#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
+    &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
+#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
+#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
+#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
+#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
+#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
+#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
+#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
+#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
+#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
+
+
+
+
+/* Channel array defines of USB20_FROM_D0FIFOSEL */
+/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
+#define USB20_FROM_D0FIFOSEL_COUNT  (2)
+#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
+    &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
+#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
+#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
+#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
+
+
+/* End of channel array defines of USB20 */
+
+
+#define SYSCFG0_0 (USB200.SYSCFG0)
+#define BUSWAIT_0 (USB200.BUSWAIT)
+#define SYSSTS0_0 (USB200.SYSSTS0)
+#define DVSTCTR0_0 (USB200.DVSTCTR0)
+#define TESTMODE_0 (USB200.TESTMODE)
+#define D0FBCFG_0 (USB200.D0FBCFG)
+#define D1FBCFG_0 (USB200.D1FBCFG)
+#define CFIFO_0   (USB200.CFIFO.UINT32)
+#define CFIFO_0L  (USB200.CFIFO.UINT16[R_IO_L])
+#define CFIFO_0H  (USB200.CFIFO.UINT16[R_IO_H])
+#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL])
+#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH])
+#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL])
+#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH])
+#define D0FIFO_0   (USB200.D0FIFO.UINT32)
+#define D0FIFO_0L  (USB200.D0FIFO.UINT16[R_IO_L])
+#define D0FIFO_0H  (USB200.D0FIFO.UINT16[R_IO_H])
+#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL])
+#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH])
+#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL])
+#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH])
+#define D1FIFO_0   (USB200.D1FIFO.UINT32)
+#define D1FIFO_0L  (USB200.D1FIFO.UINT16[R_IO_L])
+#define D1FIFO_0H  (USB200.D1FIFO.UINT16[R_IO_H])
+#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL])
+#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH])
+#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL])
+#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH])
+#define CFIFOSEL_0 (USB200.CFIFOSEL)
+#define CFIFOCTR_0 (USB200.CFIFOCTR)
+#define D0FIFOSEL_0 (USB200.D0FIFOSEL)
+#define D0FIFOCTR_0 (USB200.D0FIFOCTR)
+#define D1FIFOSEL_0 (USB200.D1FIFOSEL)
+#define D1FIFOCTR_0 (USB200.D1FIFOCTR)
+#define INTENB0_0 (USB200.INTENB0)
+#define INTENB1_0 (USB200.INTENB1)
+#define BRDYENB_0 (USB200.BRDYENB)
+#define NRDYENB_0 (USB200.NRDYENB)
+#define BEMPENB_0 (USB200.BEMPENB)
+#define SOFCFG_0 (USB200.SOFCFG)
+#define INTSTS0_0 (USB200.INTSTS0)
+#define INTSTS1_0 (USB200.INTSTS1)
+#define BRDYSTS_0 (USB200.BRDYSTS)
+#define NRDYSTS_0 (USB200.NRDYSTS)
+#define BEMPSTS_0 (USB200.BEMPSTS)
+#define FRMNUM_0 (USB200.FRMNUM)
+#define UFRMNUM_0 (USB200.UFRMNUM)
+#define USBADDR_0 (USB200.USBADDR)
+#define USBREQ_0 (USB200.USBREQ)
+#define USBVAL_0 (USB200.USBVAL)
+#define USBINDX_0 (USB200.USBINDX)
+#define USBLENG_0 (USB200.USBLENG)
+#define DCPCFG_0 (USB200.DCPCFG)
+#define DCPMAXP_0 (USB200.DCPMAXP)
+#define DCPCTR_0 (USB200.DCPCTR)
+#define PIPESEL_0 (USB200.PIPESEL)
+#define PIPECFG_0 (USB200.PIPECFG)
+#define PIPEBUF_0 (USB200.PIPEBUF)
+#define PIPEMAXP_0 (USB200.PIPEMAXP)
+#define PIPEPERI_0 (USB200.PIPEPERI)
+#define PIPE1CTR_0 (USB200.PIPE1CTR)
+#define PIPE2CTR_0 (USB200.PIPE2CTR)
+#define PIPE3CTR_0 (USB200.PIPE3CTR)
+#define PIPE4CTR_0 (USB200.PIPE4CTR)
+#define PIPE5CTR_0 (USB200.PIPE5CTR)
+#define PIPE6CTR_0 (USB200.PIPE6CTR)
+#define PIPE7CTR_0 (USB200.PIPE7CTR)
+#define PIPE8CTR_0 (USB200.PIPE8CTR)
+#define PIPE9CTR_0 (USB200.PIPE9CTR)
+#define PIPEACTR_0 (USB200.PIPEACTR)
+#define PIPEBCTR_0 (USB200.PIPEBCTR)
+#define PIPECCTR_0 (USB200.PIPECCTR)
+#define PIPEDCTR_0 (USB200.PIPEDCTR)
+#define PIPEECTR_0 (USB200.PIPEECTR)
+#define PIPEFCTR_0 (USB200.PIPEFCTR)
+#define PIPE1TRE_0 (USB200.PIPE1TRE)
+#define PIPE1TRN_0 (USB200.PIPE1TRN)
+#define PIPE2TRE_0 (USB200.PIPE2TRE)
+#define PIPE2TRN_0 (USB200.PIPE2TRN)
+#define PIPE3TRE_0 (USB200.PIPE3TRE)
+#define PIPE3TRN_0 (USB200.PIPE3TRN)
+#define PIPE4TRE_0 (USB200.PIPE4TRE)
+#define PIPE4TRN_0 (USB200.PIPE4TRN)
+#define PIPE5TRE_0 (USB200.PIPE5TRE)
+#define PIPE5TRN_0 (USB200.PIPE5TRN)
+#define PIPEBTRE_0 (USB200.PIPEBTRE)
+#define PIPEBTRN_0 (USB200.PIPEBTRN)
+#define PIPECTRE_0 (USB200.PIPECTRE)
+#define PIPECTRN_0 (USB200.PIPECTRN)
+#define PIPEDTRE_0 (USB200.PIPEDTRE)
+#define PIPEDTRN_0 (USB200.PIPEDTRN)
+#define PIPEETRE_0 (USB200.PIPEETRE)
+#define PIPEETRN_0 (USB200.PIPEETRN)
+#define PIPEFTRE_0 (USB200.PIPEFTRE)
+#define PIPEFTRN_0 (USB200.PIPEFTRN)
+#define PIPE9TRE_0 (USB200.PIPE9TRE)
+#define PIPE9TRN_0 (USB200.PIPE9TRN)
+#define PIPEATRE_0 (USB200.PIPEATRE)
+#define PIPEATRN_0 (USB200.PIPEATRN)
+#define DEVADD0_0 (USB200.DEVADD0)
+#define DEVADD1_0 (USB200.DEVADD1)
+#define DEVADD2_0 (USB200.DEVADD2)
+#define DEVADD3_0 (USB200.DEVADD3)
+#define DEVADD4_0 (USB200.DEVADD4)
+#define DEVADD5_0 (USB200.DEVADD5)
+#define DEVADD6_0 (USB200.DEVADD6)
+#define DEVADD7_0 (USB200.DEVADD7)
+#define DEVADD8_0 (USB200.DEVADD8)
+#define DEVADD9_0 (USB200.DEVADD9)
+#define DEVADDA_0 (USB200.DEVADDA)
+#define SUSPMODE_0 (USB200.SUSPMODE)
+#define D0FIFOB0_0 (USB200.D0FIFOB0)
+#define D0FIFOB1_0 (USB200.D0FIFOB1)
+#define D0FIFOB2_0 (USB200.D0FIFOB2)
+#define D0FIFOB3_0 (USB200.D0FIFOB3)
+#define D0FIFOB4_0 (USB200.D0FIFOB4)
+#define D0FIFOB5_0 (USB200.D0FIFOB5)
+#define D0FIFOB6_0 (USB200.D0FIFOB6)
+#define D0FIFOB7_0 (USB200.D0FIFOB7)
+#define D1FIFOB0_0 (USB200.D1FIFOB0)
+#define D1FIFOB1_0 (USB200.D1FIFOB1)
+#define D1FIFOB2_0 (USB200.D1FIFOB2)
+#define D1FIFOB3_0 (USB200.D1FIFOB3)
+#define D1FIFOB4_0 (USB200.D1FIFOB4)
+#define D1FIFOB5_0 (USB200.D1FIFOB5)
+#define D1FIFOB6_0 (USB200.D1FIFOB6)
+#define D1FIFOB7_0 (USB200.D1FIFOB7)
+#define SYSCFG0_1 (USB201.SYSCFG0)
+#define BUSWAIT_1 (USB201.BUSWAIT)
+#define SYSSTS0_1 (USB201.SYSSTS0)
+#define DVSTCTR0_1 (USB201.DVSTCTR0)
+#define TESTMODE_1 (USB201.TESTMODE)
+#define D0FBCFG_1 (USB201.D0FBCFG)
+#define D1FBCFG_1 (USB201.D1FBCFG)
+#define CFIFO_1   (USB201.CFIFO.UINT32)
+#define CFIFO_1L  (USB201.CFIFO.UINT16[R_IO_L])
+#define CFIFO_1H  (USB201.CFIFO.UINT16[R_IO_H])
+#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL])
+#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH])
+#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL])
+#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH])
+#define D0FIFO_1   (USB201.D0FIFO.UINT32)
+#define D0FIFO_1L  (USB201.D0FIFO.UINT16[R_IO_L])
+#define D0FIFO_1H  (USB201.D0FIFO.UINT16[R_IO_H])
+#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL])
+#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH])
+#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL])
+#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH])
+#define D1FIFO_1   (USB201.D1FIFO.UINT32)
+#define D1FIFO_1L  (USB201.D1FIFO.UINT16[R_IO_L])
+#define D1FIFO_1H  (USB201.D1FIFO.UINT16[R_IO_H])
+#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL])
+#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH])
+#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL])
+#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH])
+#define CFIFOSEL_1 (USB201.CFIFOSEL)
+#define CFIFOCTR_1 (USB201.CFIFOCTR)
+#define D0FIFOSEL_1 (USB201.D0FIFOSEL)
+#define D0FIFOCTR_1 (USB201.D0FIFOCTR)
+#define D1FIFOSEL_1 (USB201.D1FIFOSEL)
+#define D1FIFOCTR_1 (USB201.D1FIFOCTR)
+#define INTENB0_1 (USB201.INTENB0)
+#define INTENB1_1 (USB201.INTENB1)
+#define BRDYENB_1 (USB201.BRDYENB)
+#define NRDYENB_1 (USB201.NRDYENB)
+#define BEMPENB_1 (USB201.BEMPENB)
+#define SOFCFG_1 (USB201.SOFCFG)
+#define INTSTS0_1 (USB201.INTSTS0)
+#define INTSTS1_1 (USB201.INTSTS1)
+#define BRDYSTS_1 (USB201.BRDYSTS)
+#define NRDYSTS_1 (USB201.NRDYSTS)
+#define BEMPSTS_1 (USB201.BEMPSTS)
+#define FRMNUM_1 (USB201.FRMNUM)
+#define UFRMNUM_1 (USB201.UFRMNUM)
+#define USBADDR_1 (USB201.USBADDR)
+#define USBREQ_1 (USB201.USBREQ)
+#define USBVAL_1 (USB201.USBVAL)
+#define USBINDX_1 (USB201.USBINDX)
+#define USBLENG_1 (USB201.USBLENG)
+#define DCPCFG_1 (USB201.DCPCFG)
+#define DCPMAXP_1 (USB201.DCPMAXP)
+#define DCPCTR_1 (USB201.DCPCTR)
+#define PIPESEL_1 (USB201.PIPESEL)
+#define PIPECFG_1 (USB201.PIPECFG)
+#define PIPEBUF_1 (USB201.PIPEBUF)
+#define PIPEMAXP_1 (USB201.PIPEMAXP)
+#define PIPEPERI_1 (USB201.PIPEPERI)
+#define PIPE1CTR_1 (USB201.PIPE1CTR)
+#define PIPE2CTR_1 (USB201.PIPE2CTR)
+#define PIPE3CTR_1 (USB201.PIPE3CTR)
+#define PIPE4CTR_1 (USB201.PIPE4CTR)
+#define PIPE5CTR_1 (USB201.PIPE5CTR)
+#define PIPE6CTR_1 (USB201.PIPE6CTR)
+#define PIPE7CTR_1 (USB201.PIPE7CTR)
+#define PIPE8CTR_1 (USB201.PIPE8CTR)
+#define PIPE9CTR_1 (USB201.PIPE9CTR)
+#define PIPEACTR_1 (USB201.PIPEACTR)
+#define PIPEBCTR_1 (USB201.PIPEBCTR)
+#define PIPECCTR_1 (USB201.PIPECCTR)
+#define PIPEDCTR_1 (USB201.PIPEDCTR)
+#define PIPEECTR_1 (USB201.PIPEECTR)
+#define PIPEFCTR_1 (USB201.PIPEFCTR)
+#define PIPE1TRE_1 (USB201.PIPE1TRE)
+#define PIPE1TRN_1 (USB201.PIPE1TRN)
+#define PIPE2TRE_1 (USB201.PIPE2TRE)
+#define PIPE2TRN_1 (USB201.PIPE2TRN)
+#define PIPE3TRE_1 (USB201.PIPE3TRE)
+#define PIPE3TRN_1 (USB201.PIPE3TRN)
+#define PIPE4TRE_1 (USB201.PIPE4TRE)
+#define PIPE4TRN_1 (USB201.PIPE4TRN)
+#define PIPE5TRE_1 (USB201.PIPE5TRE)
+#define PIPE5TRN_1 (USB201.PIPE5TRN)
+#define PIPEBTRE_1 (USB201.PIPEBTRE)
+#define PIPEBTRN_1 (USB201.PIPEBTRN)
+#define PIPECTRE_1 (USB201.PIPECTRE)
+#define PIPECTRN_1 (USB201.PIPECTRN)
+#define PIPEDTRE_1 (USB201.PIPEDTRE)
+#define PIPEDTRN_1 (USB201.PIPEDTRN)
+#define PIPEETRE_1 (USB201.PIPEETRE)
+#define PIPEETRN_1 (USB201.PIPEETRN)
+#define PIPEFTRE_1 (USB201.PIPEFTRE)
+#define PIPEFTRN_1 (USB201.PIPEFTRN)
+#define PIPE9TRE_1 (USB201.PIPE9TRE)
+#define PIPE9TRN_1 (USB201.PIPE9TRN)
+#define PIPEATRE_1 (USB201.PIPEATRE)
+#define PIPEATRN_1 (USB201.PIPEATRN)
+#define DEVADD0_1 (USB201.DEVADD0)
+#define DEVADD1_1 (USB201.DEVADD1)
+#define DEVADD2_1 (USB201.DEVADD2)
+#define DEVADD3_1 (USB201.DEVADD3)
+#define DEVADD4_1 (USB201.DEVADD4)
+#define DEVADD5_1 (USB201.DEVADD5)
+#define DEVADD6_1 (USB201.DEVADD6)
+#define DEVADD7_1 (USB201.DEVADD7)
+#define DEVADD8_1 (USB201.DEVADD8)
+#define DEVADD9_1 (USB201.DEVADD9)
+#define DEVADDA_1 (USB201.DEVADDA)
+#define SUSPMODE_1 (USB201.SUSPMODE)
+#define D0FIFOB0_1 (USB201.D0FIFOB0)
+#define D0FIFOB1_1 (USB201.D0FIFOB1)
+#define D0FIFOB2_1 (USB201.D0FIFOB2)
+#define D0FIFOB3_1 (USB201.D0FIFOB3)
+#define D0FIFOB4_1 (USB201.D0FIFOB4)
+#define D0FIFOB5_1 (USB201.D0FIFOB5)
+#define D0FIFOB6_1 (USB201.D0FIFOB6)
+#define D0FIFOB7_1 (USB201.D0FIFOB7)
+#define D1FIFOB0_1 (USB201.D1FIFOB0)
+#define D1FIFOB1_1 (USB201.D1FIFOB1)
+#define D1FIFOB2_1 (USB201.D1FIFOB2)
+#define D1FIFOB3_1 (USB201.D1FIFOB3)
+#define D1FIFOB4_1 (USB201.D1FIFOB4)
+#define D1FIFOB5_1 (USB201.D1FIFOB5)
+#define D1FIFOB6_1 (USB201.D1FIFOB6)
+#define D1FIFOB7_1 (USB201.D1FIFOB7)
+
+#define USB20_D0FBCFG_COUNT (2)
+#define USB20_D0FIFO_COUNT (2)
+#define USB20_INTENB0_COUNT (2)
+#define USB20_INTSTS0_COUNT (2)
+#define USB20_PIPE1CTR_COUNT (0xF)
+#define USB20_DEVADD0_COUNT (0xB)
+#define USB20_D0FIFOB0_COUNT (0x8)
+
+
+typedef struct st_usb20
+{
+                                                           /* USB20            */
+    volatile uint16_t SYSCFG0;                                /*  SYSCFG0         */
+    volatile uint16_t BUSWAIT;                                /*  BUSWAIT         */
+    volatile uint16_t SYSSTS0;                                /*  SYSSTS0         */
+    volatile uint8_t   dummy1[2];                              /*                  */
+    volatile uint16_t DVSTCTR0;                               /*  DVSTCTR0        */
+    volatile uint8_t   dummy2[2];                              /*                  */
+    volatile uint16_t TESTMODE;                               /*  TESTMODE        */
+    volatile uint8_t   dummy3[2];                              /*                  */
+
+/* #define USB20_D0FBCFG_COUNT (2) */
+    volatile uint16_t D0FBCFG;                                /*  D0FBCFG         */
+    volatile uint16_t D1FBCFG;                                /*  D1FBCFG         */
+    union iodefine_reg32_t  CFIFO;                         /*  CFIFO           */
+
+/* #define USB20_D0FIFO_COUNT (2) */
+    union iodefine_reg32_t  D0FIFO;                        /*  D0FIFO          */
+    union iodefine_reg32_t  D1FIFO;                        /*  D1FIFO          */
+    
+    volatile uint16_t CFIFOSEL;                               /*  CFIFOSEL        */
+    volatile uint16_t CFIFOCTR;                               /*  CFIFOCTR        */
+    volatile uint8_t   dummy4[4];                              /*                  */
+
+/* start of struct st_usb20_from_d0fifosel */
+    volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
+    volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
+
+/* end of struct st_usb20_from_d0fifosel */
+
+/* start of struct st_usb20_from_d0fifosel */
+    volatile uint16_t D1FIFOSEL;                              /*  D1FIFOSEL       */
+    volatile uint16_t D1FIFOCTR;                              /*  D1FIFOCTR       */
+
+/* end of struct st_usb20_from_d0fifosel */
+
+/* #define USB20_INTENB0_COUNT (2) */
+    volatile uint16_t INTENB0;                                /*  INTENB0         */
+    volatile uint16_t INTENB1;                                /*  INTENB1         */
+    volatile uint8_t   dummy5[2];                              /*                  */
+    volatile uint16_t BRDYENB;                                /*  BRDYENB         */
+    volatile uint16_t NRDYENB;                                /*  NRDYENB         */
+    volatile uint16_t BEMPENB;                                /*  BEMPENB         */
+    volatile uint16_t SOFCFG;                                 /*  SOFCFG          */
+    volatile uint8_t   dummy6[2];                              /*                  */
+
+/* #define USB20_INTSTS0_COUNT (2) */
+    volatile uint16_t INTSTS0;                                /*  INTSTS0         */
+    volatile uint16_t INTSTS1;                                /*  INTSTS1         */
+    volatile uint8_t   dummy7[2];                              /*                  */
+    volatile uint16_t BRDYSTS;                                /*  BRDYSTS         */
+    volatile uint16_t NRDYSTS;                                /*  NRDYSTS         */
+    volatile uint16_t BEMPSTS;                                /*  BEMPSTS         */
+    volatile uint16_t FRMNUM;                                 /*  FRMNUM          */
+    volatile uint16_t UFRMNUM;                                /*  UFRMNUM         */
+    volatile uint16_t USBADDR;                                /*  USBADDR         */
+    volatile uint8_t   dummy8[2];                              /*                  */
+    volatile uint16_t USBREQ;                                 /*  USBREQ          */
+    volatile uint16_t USBVAL;                                 /*  USBVAL          */
+    volatile uint16_t USBINDX;                                /*  USBINDX         */
+    volatile uint16_t USBLENG;                                /*  USBLENG         */
+    volatile uint16_t DCPCFG;                                 /*  DCPCFG          */
+    volatile uint16_t DCPMAXP;                                /*  DCPMAXP         */
+    volatile uint16_t DCPCTR;                                 /*  DCPCTR          */
+    volatile uint8_t   dummy9[2];                              /*                  */
+    volatile uint16_t PIPESEL;                                /*  PIPESEL         */
+    volatile uint8_t   dummy10[2];                             /*                  */
+    volatile uint16_t PIPECFG;                                /*  PIPECFG         */
+    volatile uint16_t PIPEBUF;                                /*  PIPEBUF         */
+    volatile uint16_t PIPEMAXP;                               /*  PIPEMAXP        */
+    volatile uint16_t PIPEPERI;                               /*  PIPEPERI        */
+
+/* #define USB20_PIPE1CTR_COUNT (0xF) */
+    volatile uint16_t PIPE1CTR;                               /*  PIPE1CTR        */
+    volatile uint16_t PIPE2CTR;                               /*  PIPE2CTR        */
+    volatile uint16_t PIPE3CTR;                               /*  PIPE3CTR        */
+    volatile uint16_t PIPE4CTR;                               /*  PIPE4CTR        */
+    volatile uint16_t PIPE5CTR;                               /*  PIPE5CTR        */
+    volatile uint16_t PIPE6CTR;                               /*  PIPE6CTR        */
+    volatile uint16_t PIPE7CTR;                               /*  PIPE7CTR        */
+    volatile uint16_t PIPE8CTR;                               /*  PIPE8CTR        */
+    volatile uint16_t PIPE9CTR;                               /*  PIPE9CTR        */
+    volatile uint16_t PIPEACTR;                               /*  PIPEACTR        */
+    volatile uint16_t PIPEBCTR;                               /*  PIPEBCTR        */
+    volatile uint16_t PIPECCTR;                               /*  PIPECCTR        */
+    volatile uint16_t PIPEDCTR;                               /*  PIPEDCTR        */
+    volatile uint16_t PIPEECTR;                               /*  PIPEECTR        */
+    volatile uint16_t PIPEFCTR;                               /*  PIPEFCTR        */
+    volatile uint8_t   dummy11[2];                             /*                  */
+
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
+    volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
+
+/* end of struct st_usb20_from_pipe1tre */
+
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE2TRE;                               /*  PIPE2TRE        */
+    volatile uint16_t PIPE2TRN;                               /*  PIPE2TRN        */
+
+/* end of struct st_usb20_from_pipe1tre */
+
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE3TRE;                               /*  PIPE3TRE        */
+    volatile uint16_t PIPE3TRN;                               /*  PIPE3TRN        */
+
+/* end of struct st_usb20_from_pipe1tre */
+
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE4TRE;                               /*  PIPE4TRE        */
+    volatile uint16_t PIPE4TRN;                               /*  PIPE4TRN        */
+
+/* end of struct st_usb20_from_pipe1tre */
+
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE5TRE;                               /*  PIPE5TRE        */
+    volatile uint16_t PIPE5TRN;                               /*  PIPE5TRN        */
+
+/* end of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPEBTRE;                               /*  PIPEBTRE        */
+    volatile uint16_t PIPEBTRN;                               /*  PIPEBTRN        */
+    volatile uint16_t PIPECTRE;                               /*  PIPECTRE        */
+    volatile uint16_t PIPECTRN;                               /*  PIPECTRN        */
+    volatile uint16_t PIPEDTRE;                               /*  PIPEDTRE        */
+    volatile uint16_t PIPEDTRN;                               /*  PIPEDTRN        */
+    volatile uint16_t PIPEETRE;                               /*  PIPEETRE        */
+    volatile uint16_t PIPEETRN;                               /*  PIPEETRN        */
+    volatile uint16_t PIPEFTRE;                               /*  PIPEFTRE        */
+    volatile uint16_t PIPEFTRN;                               /*  PIPEFTRN        */
+    volatile uint16_t PIPE9TRE;                               /*  PIPE9TRE        */
+    volatile uint16_t PIPE9TRN;                               /*  PIPE9TRN        */
+    volatile uint16_t PIPEATRE;                               /*  PIPEATRE        */
+    volatile uint16_t PIPEATRN;                               /*  PIPEATRN        */
+    volatile uint8_t   dummy12[16];                            /*                  */
+
+/* #define USB20_DEVADD0_COUNT (0xB) */
+    volatile uint16_t DEVADD0;                                /*  DEVADD0         */
+    volatile uint16_t DEVADD1;                                /*  DEVADD1         */
+    volatile uint16_t DEVADD2;                                /*  DEVADD2         */
+    volatile uint16_t DEVADD3;                                /*  DEVADD3         */
+    volatile uint16_t DEVADD4;                                /*  DEVADD4         */
+    volatile uint16_t DEVADD5;                                /*  DEVADD5         */
+    volatile uint16_t DEVADD6;                                /*  DEVADD6         */
+    volatile uint16_t DEVADD7;                                /*  DEVADD7         */
+    volatile uint16_t DEVADD8;                                /*  DEVADD8         */
+    volatile uint16_t DEVADD9;                                /*  DEVADD9         */
+    volatile uint16_t DEVADDA;                                /*  DEVADDA         */
+    volatile uint8_t   dummy13[28];                            /*                  */
+    volatile uint16_t SUSPMODE;                               /*  SUSPMODE        */
+    volatile uint8_t   dummy14[92];                            /*                  */
+
+/* start of struct st_usb20_from_dmfifob0 */
+    volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
+    volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
+    volatile uint32_t  D0FIFOB2;                               /*  D0FIFOB2        */
+    volatile uint32_t  D0FIFOB3;                               /*  D0FIFOB3        */
+    volatile uint32_t  D0FIFOB4;                               /*  D0FIFOB4        */
+    volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
+    volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
+    volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
+
+/* end of struct st_usb20_from_dmfifob0 */
+
+/* start of struct st_usb20_from_dmfifob0 */
+    volatile uint32_t  D1FIFOB0;                               /*  D1FIFOB0        */
+    volatile uint32_t  D1FIFOB1;                               /*  D1FIFOB1        */
+    volatile uint32_t  D1FIFOB2;                               /*  D1FIFOB2        */
+    volatile uint32_t  D1FIFOB3;                               /*  D1FIFOB3        */
+    volatile uint32_t  D1FIFOB4;                               /*  D1FIFOB4        */
+    volatile uint32_t  D1FIFOB5;                               /*  D1FIFOB5        */
+    volatile uint32_t  D1FIFOB6;                               /*  D1FIFOB6        */
+    volatile uint32_t  D1FIFOB7;                               /*  D1FIFOB7        */
+
+/* end of struct st_usb20_from_dmfifob0 */
+} r_io_usb20_t;
+
+
+typedef struct st_usb20_from_d0fifosel
+{
+ 
+    volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
+    volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
+} r_io_usb20_from_d0fifosel_t;
+
+
+typedef struct st_usb20_from_pipe1tre
+{
+ 
+    volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
+    volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
+} r_io_usb20_from_pipe1tre_t;
+
+
+typedef struct st_usb20_from_dmfifob0
+{
+ 
+
+/* #define USB20_D0FIFOB0_COUNT (0x8) */
+    volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
+    volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
+    volatile uint32_t  D0FIFOB2;                               /*  D0FIFOB2        */
+    volatile uint32_t  D0FIFOB3;                               /*  D0FIFOB3        */
+    volatile uint32_t  D0FIFOB4;                               /*  D0FIFOB4        */
+    volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
+    volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
+    volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
+} r_io_usb20_from_dmfifob0_t;
+
+
+/* Channel array defines of USB20 (2)*/
+#ifdef  DECLARE_USB20_CHANNELS
+volatile struct st_usb20*  USB20[ USB20_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_D0FIFOB0_CHANNELS
+volatile struct st_usb20_from_dmfifob0*  USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_D0FIFOB0_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS
+volatile struct st_usb20_from_pipe1tre*  USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_PIPE1ATRE_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS
+volatile struct st_usb20_from_d0fifosel*  USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_D0FIFOSEL_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */
+/* End of channel array defines of USB20 (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h	(revision 374)
@@ -0,0 +1,1788 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : vdc5_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef VDC5_IODEFINE_H
+#define VDC5_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
+#define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
+
+
+/* Start of channel array defines of VDC5 */
+
+/* Channel array defines of VDC5 */
+/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
+#define VDC5_COUNT  (2)
+#define VDC5_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &VDC50, &VDC51 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */
+/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC50_FROM_GR2_AB7_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
+    &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
+#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
+#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
+#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
+    &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
+#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
+#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
+#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */
+/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
+#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  (2)
+#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
+    &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
+#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
+#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
+#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
+#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
+    &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
+#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
+#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
+#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
+#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
+    &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
+#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
+#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
+#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */
+/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC50_FROM_GR0_AB7_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
+    &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
+#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
+#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
+#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
+    &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
+#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
+#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
+#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
+
+
+/* End of channel array defines of VDC5 */
+
+
+#define VDC50INP_UPDATE (VDC50.INP_UPDATE)
+#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT)
+#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT)
+#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ)
+#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ)
+#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE)
+#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0)
+#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1)
+#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE)
+#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0)
+#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1)
+#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0)
+#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1)
+#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0)
+#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1)
+#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG)
+#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE)
+#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1)
+#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2)
+#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3)
+#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4)
+#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5)
+#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6)
+#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7)
+#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9)
+#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0)
+#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT)
+#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1)
+#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2)
+#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3)
+#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4)
+#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5)
+#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6)
+#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7)
+#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1)
+#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2)
+#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3)
+#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4)
+#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5)
+#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6)
+#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7)
+#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8)
+#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1)
+#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE)
+#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1)
+#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2)
+#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3)
+#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4)
+#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5)
+#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6)
+#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7)
+#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8)
+#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9)
+#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10)
+#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11)
+#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1)
+#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0)
+#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1)
+#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2)
+#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3)
+#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD)
+#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT)
+#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE)
+#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD)
+#define VDC50GR0_FLM1 (VDC50.GR0_FLM1)
+#define VDC50GR0_FLM2 (VDC50.GR0_FLM2)
+#define VDC50GR0_FLM3 (VDC50.GR0_FLM3)
+#define VDC50GR0_FLM4 (VDC50.GR0_FLM4)
+#define VDC50GR0_FLM5 (VDC50.GR0_FLM5)
+#define VDC50GR0_FLM6 (VDC50.GR0_FLM6)
+#define VDC50GR0_AB1 (VDC50.GR0_AB1)
+#define VDC50GR0_AB2 (VDC50.GR0_AB2)
+#define VDC50GR0_AB3 (VDC50.GR0_AB3)
+#define VDC50GR0_AB7 (VDC50.GR0_AB7)
+#define VDC50GR0_AB8 (VDC50.GR0_AB8)
+#define VDC50GR0_AB9 (VDC50.GR0_AB9)
+#define VDC50GR0_AB10 (VDC50.GR0_AB10)
+#define VDC50GR0_AB11 (VDC50.GR0_AB11)
+#define VDC50GR0_BASE (VDC50.GR0_BASE)
+#define VDC50GR0_CLUT (VDC50.GR0_CLUT)
+#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE)
+#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET)
+#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1)
+#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2)
+#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3)
+#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1)
+#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2)
+#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3)
+#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4)
+#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5)
+#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6)
+#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1)
+#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2)
+#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE)
+#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0)
+#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1)
+#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0)
+#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1)
+#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0)
+#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1)
+#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE)
+#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD)
+#define VDC50GR2_FLM1 (VDC50.GR2_FLM1)
+#define VDC50GR2_FLM2 (VDC50.GR2_FLM2)
+#define VDC50GR2_FLM3 (VDC50.GR2_FLM3)
+#define VDC50GR2_FLM4 (VDC50.GR2_FLM4)
+#define VDC50GR2_FLM5 (VDC50.GR2_FLM5)
+#define VDC50GR2_FLM6 (VDC50.GR2_FLM6)
+#define VDC50GR2_AB1 (VDC50.GR2_AB1)
+#define VDC50GR2_AB2 (VDC50.GR2_AB2)
+#define VDC50GR2_AB3 (VDC50.GR2_AB3)
+#define VDC50GR2_AB4 (VDC50.GR2_AB4)
+#define VDC50GR2_AB5 (VDC50.GR2_AB5)
+#define VDC50GR2_AB6 (VDC50.GR2_AB6)
+#define VDC50GR2_AB7 (VDC50.GR2_AB7)
+#define VDC50GR2_AB8 (VDC50.GR2_AB8)
+#define VDC50GR2_AB9 (VDC50.GR2_AB9)
+#define VDC50GR2_AB10 (VDC50.GR2_AB10)
+#define VDC50GR2_AB11 (VDC50.GR2_AB11)
+#define VDC50GR2_BASE (VDC50.GR2_BASE)
+#define VDC50GR2_CLUT (VDC50.GR2_CLUT)
+#define VDC50GR2_MON (VDC50.GR2_MON)
+#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE)
+#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD)
+#define VDC50GR3_FLM1 (VDC50.GR3_FLM1)
+#define VDC50GR3_FLM2 (VDC50.GR3_FLM2)
+#define VDC50GR3_FLM3 (VDC50.GR3_FLM3)
+#define VDC50GR3_FLM4 (VDC50.GR3_FLM4)
+#define VDC50GR3_FLM5 (VDC50.GR3_FLM5)
+#define VDC50GR3_FLM6 (VDC50.GR3_FLM6)
+#define VDC50GR3_AB1 (VDC50.GR3_AB1)
+#define VDC50GR3_AB2 (VDC50.GR3_AB2)
+#define VDC50GR3_AB3 (VDC50.GR3_AB3)
+#define VDC50GR3_AB4 (VDC50.GR3_AB4)
+#define VDC50GR3_AB5 (VDC50.GR3_AB5)
+#define VDC50GR3_AB6 (VDC50.GR3_AB6)
+#define VDC50GR3_AB7 (VDC50.GR3_AB7)
+#define VDC50GR3_AB8 (VDC50.GR3_AB8)
+#define VDC50GR3_AB9 (VDC50.GR3_AB9)
+#define VDC50GR3_AB10 (VDC50.GR3_AB10)
+#define VDC50GR3_AB11 (VDC50.GR3_AB11)
+#define VDC50GR3_BASE (VDC50.GR3_BASE)
+#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT)
+#define VDC50GR3_MON (VDC50.GR3_MON)
+#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE)
+#define VDC50GAM_SW (VDC50.GAM_SW)
+#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1)
+#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2)
+#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3)
+#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4)
+#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5)
+#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6)
+#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7)
+#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8)
+#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9)
+#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10)
+#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11)
+#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12)
+#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13)
+#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14)
+#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15)
+#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16)
+#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1)
+#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2)
+#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3)
+#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4)
+#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5)
+#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6)
+#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7)
+#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8)
+#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE)
+#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1)
+#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2)
+#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3)
+#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4)
+#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5)
+#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6)
+#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7)
+#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8)
+#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9)
+#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10)
+#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11)
+#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12)
+#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13)
+#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14)
+#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15)
+#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16)
+#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1)
+#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2)
+#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3)
+#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4)
+#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5)
+#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6)
+#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7)
+#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8)
+#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE)
+#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1)
+#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2)
+#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3)
+#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4)
+#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5)
+#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6)
+#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7)
+#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8)
+#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9)
+#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10)
+#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11)
+#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12)
+#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13)
+#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14)
+#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15)
+#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16)
+#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1)
+#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2)
+#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3)
+#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4)
+#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5)
+#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6)
+#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7)
+#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8)
+#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE)
+#define VDC50TCON_TIM (VDC50.TCON_TIM)
+#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1)
+#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2)
+#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1)
+#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2)
+#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1)
+#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2)
+#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1)
+#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2)
+#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1)
+#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2)
+#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1)
+#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2)
+#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1)
+#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2)
+#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE)
+#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE)
+#define VDC50OUT_SET (VDC50.OUT_SET)
+#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1)
+#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2)
+#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST)
+#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA)
+#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE)
+#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1)
+#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2)
+#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3)
+#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4)
+#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5)
+#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6)
+#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK)
+#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT)
+#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE)
+#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1)
+#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2)
+#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3)
+#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4)
+#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5)
+#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6)
+#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7)
+#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9)
+#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0)
+#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT)
+#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1)
+#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2)
+#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3)
+#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4)
+#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5)
+#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6)
+#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7)
+#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1)
+#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2)
+#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3)
+#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4)
+#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5)
+#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6)
+#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7)
+#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8)
+#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1)
+#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE)
+#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1)
+#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2)
+#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3)
+#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4)
+#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5)
+#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6)
+#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7)
+#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8)
+#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9)
+#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10)
+#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11)
+#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1)
+#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0)
+#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1)
+#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2)
+#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3)
+#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD)
+#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT)
+#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE)
+#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD)
+#define VDC50GR1_FLM1 (VDC50.GR1_FLM1)
+#define VDC50GR1_FLM2 (VDC50.GR1_FLM2)
+#define VDC50GR1_FLM3 (VDC50.GR1_FLM3)
+#define VDC50GR1_FLM4 (VDC50.GR1_FLM4)
+#define VDC50GR1_FLM5 (VDC50.GR1_FLM5)
+#define VDC50GR1_FLM6 (VDC50.GR1_FLM6)
+#define VDC50GR1_AB1 (VDC50.GR1_AB1)
+#define VDC50GR1_AB2 (VDC50.GR1_AB2)
+#define VDC50GR1_AB3 (VDC50.GR1_AB3)
+#define VDC50GR1_AB4 (VDC50.GR1_AB4)
+#define VDC50GR1_AB5 (VDC50.GR1_AB5)
+#define VDC50GR1_AB6 (VDC50.GR1_AB6)
+#define VDC50GR1_AB7 (VDC50.GR1_AB7)
+#define VDC50GR1_AB8 (VDC50.GR1_AB8)
+#define VDC50GR1_AB9 (VDC50.GR1_AB9)
+#define VDC50GR1_AB10 (VDC50.GR1_AB10)
+#define VDC50GR1_AB11 (VDC50.GR1_AB11)
+#define VDC50GR1_BASE (VDC50.GR1_BASE)
+#define VDC50GR1_CLUT (VDC50.GR1_CLUT)
+#define VDC50GR1_MON (VDC50.GR1_MON)
+#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE)
+#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET)
+#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1)
+#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2)
+#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3)
+#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1)
+#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2)
+#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3)
+#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4)
+#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5)
+#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6)
+#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1)
+#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2)
+#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE)
+#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0)
+#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1)
+#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0)
+#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1)
+#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0)
+#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1)
+#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE)
+#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1)
+#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2)
+#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3)
+#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4)
+#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5)
+#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6)
+#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7)
+#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE)
+#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON)
+#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE)
+#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1)
+#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2)
+#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3)
+#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4)
+#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5)
+#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6)
+#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7)
+#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1)
+#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2)
+#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3)
+#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7)
+#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1)
+#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2)
+#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3)
+#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8)
+#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1)
+#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE)
+#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1)
+#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2)
+#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3)
+#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4)
+#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5)
+#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6)
+#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7)
+#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE)
+#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD)
+#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1)
+#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2)
+#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3)
+#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4)
+#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5)
+#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6)
+#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1)
+#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2)
+#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3)
+#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7)
+#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8)
+#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9)
+#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10)
+#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11)
+#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE)
+#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT)
+#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON)
+#define VDC51INP_UPDATE (VDC51.INP_UPDATE)
+#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT)
+#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT)
+#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ)
+#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ)
+#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE)
+#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0)
+#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1)
+#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE)
+#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0)
+#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1)
+#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0)
+#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1)
+#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0)
+#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1)
+#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG)
+#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE)
+#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1)
+#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2)
+#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3)
+#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4)
+#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5)
+#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6)
+#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7)
+#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9)
+#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0)
+#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT)
+#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1)
+#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2)
+#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3)
+#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4)
+#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5)
+#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6)
+#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7)
+#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1)
+#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2)
+#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3)
+#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4)
+#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5)
+#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6)
+#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7)
+#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8)
+#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1)
+#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE)
+#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1)
+#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2)
+#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3)
+#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4)
+#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5)
+#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6)
+#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7)
+#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8)
+#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9)
+#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10)
+#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11)
+#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1)
+#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0)
+#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1)
+#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2)
+#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3)
+#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD)
+#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT)
+#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE)
+#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD)
+#define VDC51GR0_FLM1 (VDC51.GR0_FLM1)
+#define VDC51GR0_FLM2 (VDC51.GR0_FLM2)
+#define VDC51GR0_FLM3 (VDC51.GR0_FLM3)
+#define VDC51GR0_FLM4 (VDC51.GR0_FLM4)
+#define VDC51GR0_FLM5 (VDC51.GR0_FLM5)
+#define VDC51GR0_FLM6 (VDC51.GR0_FLM6)
+#define VDC51GR0_AB1 (VDC51.GR0_AB1)
+#define VDC51GR0_AB2 (VDC51.GR0_AB2)
+#define VDC51GR0_AB3 (VDC51.GR0_AB3)
+#define VDC51GR0_AB7 (VDC51.GR0_AB7)
+#define VDC51GR0_AB8 (VDC51.GR0_AB8)
+#define VDC51GR0_AB9 (VDC51.GR0_AB9)
+#define VDC51GR0_AB10 (VDC51.GR0_AB10)
+#define VDC51GR0_AB11 (VDC51.GR0_AB11)
+#define VDC51GR0_BASE (VDC51.GR0_BASE)
+#define VDC51GR0_CLUT (VDC51.GR0_CLUT)
+#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE)
+#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET)
+#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1)
+#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2)
+#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3)
+#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1)
+#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2)
+#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3)
+#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4)
+#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5)
+#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6)
+#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1)
+#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2)
+#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE)
+#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0)
+#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1)
+#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0)
+#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1)
+#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0)
+#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1)
+#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE)
+#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD)
+#define VDC51GR2_FLM1 (VDC51.GR2_FLM1)
+#define VDC51GR2_FLM2 (VDC51.GR2_FLM2)
+#define VDC51GR2_FLM3 (VDC51.GR2_FLM3)
+#define VDC51GR2_FLM4 (VDC51.GR2_FLM4)
+#define VDC51GR2_FLM5 (VDC51.GR2_FLM5)
+#define VDC51GR2_FLM6 (VDC51.GR2_FLM6)
+#define VDC51GR2_AB1 (VDC51.GR2_AB1)
+#define VDC51GR2_AB2 (VDC51.GR2_AB2)
+#define VDC51GR2_AB3 (VDC51.GR2_AB3)
+#define VDC51GR2_AB4 (VDC51.GR2_AB4)
+#define VDC51GR2_AB5 (VDC51.GR2_AB5)
+#define VDC51GR2_AB6 (VDC51.GR2_AB6)
+#define VDC51GR2_AB7 (VDC51.GR2_AB7)
+#define VDC51GR2_AB8 (VDC51.GR2_AB8)
+#define VDC51GR2_AB9 (VDC51.GR2_AB9)
+#define VDC51GR2_AB10 (VDC51.GR2_AB10)
+#define VDC51GR2_AB11 (VDC51.GR2_AB11)
+#define VDC51GR2_BASE (VDC51.GR2_BASE)
+#define VDC51GR2_CLUT (VDC51.GR2_CLUT)
+#define VDC51GR2_MON (VDC51.GR2_MON)
+#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE)
+#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD)
+#define VDC51GR3_FLM1 (VDC51.GR3_FLM1)
+#define VDC51GR3_FLM2 (VDC51.GR3_FLM2)
+#define VDC51GR3_FLM3 (VDC51.GR3_FLM3)
+#define VDC51GR3_FLM4 (VDC51.GR3_FLM4)
+#define VDC51GR3_FLM5 (VDC51.GR3_FLM5)
+#define VDC51GR3_FLM6 (VDC51.GR3_FLM6)
+#define VDC51GR3_AB1 (VDC51.GR3_AB1)
+#define VDC51GR3_AB2 (VDC51.GR3_AB2)
+#define VDC51GR3_AB3 (VDC51.GR3_AB3)
+#define VDC51GR3_AB4 (VDC51.GR3_AB4)
+#define VDC51GR3_AB5 (VDC51.GR3_AB5)
+#define VDC51GR3_AB6 (VDC51.GR3_AB6)
+#define VDC51GR3_AB7 (VDC51.GR3_AB7)
+#define VDC51GR3_AB8 (VDC51.GR3_AB8)
+#define VDC51GR3_AB9 (VDC51.GR3_AB9)
+#define VDC51GR3_AB10 (VDC51.GR3_AB10)
+#define VDC51GR3_AB11 (VDC51.GR3_AB11)
+#define VDC51GR3_BASE (VDC51.GR3_BASE)
+#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT)
+#define VDC51GR3_MON (VDC51.GR3_MON)
+#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE)
+#define VDC51GAM_SW (VDC51.GAM_SW)
+#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1)
+#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2)
+#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3)
+#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4)
+#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5)
+#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6)
+#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7)
+#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8)
+#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9)
+#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10)
+#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11)
+#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12)
+#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13)
+#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14)
+#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15)
+#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16)
+#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1)
+#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2)
+#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3)
+#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4)
+#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5)
+#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6)
+#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7)
+#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8)
+#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE)
+#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1)
+#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2)
+#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3)
+#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4)
+#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5)
+#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6)
+#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7)
+#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8)
+#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9)
+#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10)
+#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11)
+#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12)
+#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13)
+#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14)
+#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15)
+#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16)
+#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1)
+#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2)
+#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3)
+#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4)
+#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5)
+#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6)
+#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7)
+#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8)
+#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE)
+#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1)
+#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2)
+#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3)
+#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4)
+#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5)
+#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6)
+#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7)
+#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8)
+#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9)
+#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10)
+#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11)
+#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12)
+#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13)
+#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14)
+#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15)
+#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16)
+#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1)
+#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2)
+#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3)
+#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4)
+#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5)
+#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6)
+#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7)
+#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8)
+#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE)
+#define VDC51TCON_TIM (VDC51.TCON_TIM)
+#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1)
+#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2)
+#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1)
+#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2)
+#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1)
+#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2)
+#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1)
+#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2)
+#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1)
+#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2)
+#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1)
+#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2)
+#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1)
+#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2)
+#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE)
+#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE)
+#define VDC51OUT_SET (VDC51.OUT_SET)
+#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1)
+#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2)
+#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST)
+#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA)
+#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE)
+#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1)
+#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2)
+#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3)
+#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4)
+#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5)
+#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6)
+#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK)
+#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT)
+#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE)
+#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1)
+#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2)
+#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3)
+#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4)
+#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5)
+#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6)
+#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7)
+#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9)
+#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0)
+#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT)
+#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1)
+#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2)
+#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3)
+#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4)
+#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5)
+#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6)
+#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7)
+#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1)
+#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2)
+#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3)
+#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4)
+#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5)
+#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6)
+#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7)
+#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8)
+#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1)
+#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE)
+#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1)
+#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2)
+#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3)
+#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4)
+#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5)
+#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6)
+#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7)
+#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8)
+#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9)
+#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10)
+#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11)
+#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1)
+#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0)
+#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1)
+#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2)
+#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3)
+#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD)
+#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT)
+#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE)
+#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD)
+#define VDC51GR1_FLM1 (VDC51.GR1_FLM1)
+#define VDC51GR1_FLM2 (VDC51.GR1_FLM2)
+#define VDC51GR1_FLM3 (VDC51.GR1_FLM3)
+#define VDC51GR1_FLM4 (VDC51.GR1_FLM4)
+#define VDC51GR1_FLM5 (VDC51.GR1_FLM5)
+#define VDC51GR1_FLM6 (VDC51.GR1_FLM6)
+#define VDC51GR1_AB1 (VDC51.GR1_AB1)
+#define VDC51GR1_AB2 (VDC51.GR1_AB2)
+#define VDC51GR1_AB3 (VDC51.GR1_AB3)
+#define VDC51GR1_AB4 (VDC51.GR1_AB4)
+#define VDC51GR1_AB5 (VDC51.GR1_AB5)
+#define VDC51GR1_AB6 (VDC51.GR1_AB6)
+#define VDC51GR1_AB7 (VDC51.GR1_AB7)
+#define VDC51GR1_AB8 (VDC51.GR1_AB8)
+#define VDC51GR1_AB9 (VDC51.GR1_AB9)
+#define VDC51GR1_AB10 (VDC51.GR1_AB10)
+#define VDC51GR1_AB11 (VDC51.GR1_AB11)
+#define VDC51GR1_BASE (VDC51.GR1_BASE)
+#define VDC51GR1_CLUT (VDC51.GR1_CLUT)
+#define VDC51GR1_MON (VDC51.GR1_MON)
+#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE)
+#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET)
+#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1)
+#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2)
+#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3)
+#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1)
+#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2)
+#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3)
+#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4)
+#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5)
+#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6)
+#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1)
+#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2)
+#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE)
+#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0)
+#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1)
+#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0)
+#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1)
+#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0)
+#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1)
+#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE)
+#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1)
+#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2)
+#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3)
+#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4)
+#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5)
+#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6)
+#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7)
+#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE)
+#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON)
+#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE)
+#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1)
+#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2)
+#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3)
+#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4)
+#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5)
+#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6)
+#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7)
+#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1)
+#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2)
+#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3)
+#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7)
+#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1)
+#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2)
+#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3)
+#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8)
+#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1)
+#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE)
+#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1)
+#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2)
+#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3)
+#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4)
+#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5)
+#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6)
+#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7)
+#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE)
+#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD)
+#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1)
+#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2)
+#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3)
+#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4)
+#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5)
+#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6)
+#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1)
+#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2)
+#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3)
+#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7)
+#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8)
+#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9)
+#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10)
+#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11)
+#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE)
+#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT)
+#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON)
+
+#define VDC5_IMGCNT_NR_CNT0_COUNT (2)
+#define VDC5_SC0_SCL0_FRC1_COUNT (7)
+#define VDC5_SC0_SCL0_DS1_COUNT (7)
+#define VDC5_SC0_SCL0_US1_COUNT (8)
+#define VDC5_SC0_SCL1_WR1_COUNT (4)
+#define VDC5_SC0_SCL1_PBUF0_COUNT (4)
+#define VDC5_GR0_FLM1_COUNT (6)
+#define VDC5_GR0_AB1_COUNT (3)
+#define VDC5_ADJ0_ENH_TIM1_COUNT (3)
+#define VDC5_ADJ0_ENH_SHP1_COUNT (6)
+#define VDC5_ADJ0_ENH_LTI1_COUNT (2)
+#define VDC5_GR2_FLM1_COUNT (6)
+#define VDC5_GR2_AB1_COUNT (3)
+#define VDC5_GR3_FLM1_COUNT (6)
+#define VDC5_GR3_AB1_COUNT (3)
+#define VDC5_GAM_G_LUT1_COUNT (16)
+#define VDC5_GAM_G_AREA1_COUNT (8)
+#define VDC5_GAM_B_LUT1_COUNT (16)
+#define VDC5_GAM_B_AREA1_COUNT (8)
+#define VDC5_GAM_R_LUT1_COUNT (16)
+#define VDC5_GAM_R_AREA1_COUNT (8)
+#define VDC5_TCON_TIM_STVA1_COUNT (2)
+#define VDC5_TCON_TIM_STVB1_COUNT (2)
+#define VDC5_TCON_TIM_STH1_COUNT (2)
+#define VDC5_TCON_TIM_STB1_COUNT (2)
+#define VDC5_TCON_TIM_CPV1_COUNT (2)
+#define VDC5_TCON_TIM_POLA1_COUNT (2)
+#define VDC5_TCON_TIM_POLB1_COUNT (2)
+#define VDC5_OUT_BRIGHT1_COUNT (2)
+#define VDC5_SYSCNT_INT1_COUNT (6)
+#define VDC5_SC1_SCL0_FRC1_COUNT (7)
+#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7)
+#define VDC5_SC1_SC1_SCL0_US1_COUNT (8)
+#define VDC5_SC1_SCL1_WR1_COUNT (4)
+#define VDC5_SC1_SCL1_PBUF0_COUNT (4)
+#define VDC5_GR1_FLM1_COUNT (6)
+#define VDC5_GR1_AB1_COUNT (3)
+#define VDC5_ADJ1_ENH_TIM1_COUNT (3)
+#define VDC5_ADJ1_ENH_SHP1_COUNT (6)
+#define VDC5_ADJ1_ENH_LTI1_COUNT (2)
+#define VDC5_GR_VIN_AB1_COUNT (7)
+#define VDC5_OIR_SCL0_FRC1_COUNT (7)
+#define VDC5_OIR_SCL0_DS1_COUNT (3)
+#define VDC5_OIR_SCL1_WR1_COUNT (4)
+#define VDC5_GR_OIR_FLM1_COUNT (6)
+#define VDC5_GR_OIR_AB1_COUNT (3)
+
+
+typedef struct st_vdc5
+{
+                                                           /* VDC5             */
+    volatile uint32_t  INP_UPDATE;                             /*  INP_UPDATE      */
+    volatile uint32_t  INP_SEL_CNT;                            /*  INP_SEL_CNT     */
+    volatile uint32_t  INP_EXT_SYNC_CNT;                       /*  INP_EXT_SYNC_CNT */
+    volatile uint32_t  INP_VSYNC_PH_ADJ;                       /*  INP_VSYNC_PH_ADJ */
+    volatile uint32_t  INP_DLY_ADJ;                            /*  INP_DLY_ADJ     */
+    volatile uint8_t   dummy1[108];                            /*                  */
+    volatile uint32_t  IMGCNT_UPDATE;                          /*  IMGCNT_UPDATE   */
+
+/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */
+    volatile uint32_t  IMGCNT_NR_CNT0;                         /*  IMGCNT_NR_CNT0  */
+    volatile uint32_t  IMGCNT_NR_CNT1;                         /*  IMGCNT_NR_CNT1  */
+    volatile uint8_t   dummy2[20];                             /*                  */
+    volatile uint32_t  IMGCNT_MTX_MODE;                        /*  IMGCNT_MTX_MODE */
+    volatile uint32_t  IMGCNT_MTX_YG_ADJ0;                     /*  IMGCNT_MTX_YG_ADJ0 */
+    volatile uint32_t  IMGCNT_MTX_YG_ADJ1;                     /*  IMGCNT_MTX_YG_ADJ1 */
+    volatile uint32_t  IMGCNT_MTX_CBB_ADJ0;                    /*  IMGCNT_MTX_CBB_ADJ0 */
+    volatile uint32_t  IMGCNT_MTX_CBB_ADJ1;                    /*  IMGCNT_MTX_CBB_ADJ1 */
+    volatile uint32_t  IMGCNT_MTX_CRR_ADJ0;                    /*  IMGCNT_MTX_CRR_ADJ0 */
+    volatile uint32_t  IMGCNT_MTX_CRR_ADJ1;                    /*  IMGCNT_MTX_CRR_ADJ1 */
+    volatile uint8_t   dummy3[4];                              /*                  */
+    volatile uint32_t  IMGCNT_DRC_REG;                         /*  IMGCNT_DRC_REG  */
+    volatile uint8_t   dummy4[60];                             /*                  */
+
+/* start of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
+
+/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */
+    volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
+    volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
+    volatile uint32_t  SC0_SCL0_FRC3;                          /*  SC0_SCL0_FRC3   */
+    volatile uint32_t  SC0_SCL0_FRC4;                          /*  SC0_SCL0_FRC4   */
+    volatile uint32_t  SC0_SCL0_FRC5;                          /*  SC0_SCL0_FRC5   */
+    volatile uint32_t  SC0_SCL0_FRC6;                          /*  SC0_SCL0_FRC6   */
+    volatile uint32_t  SC0_SCL0_FRC7;                          /*  SC0_SCL0_FRC7   */
+    volatile uint8_t   dummy5[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_FRC9;                          /*  SC0_SCL0_FRC9   */
+    volatile uint16_t SC0_SCL0_MON0;                          /*  SC0_SCL0_MON0   */
+    volatile uint16_t SC0_SCL0_INT;                           /*  SC0_SCL0_INT    */
+
+/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */
+    volatile uint32_t  SC0_SCL0_DS1;                           /*  SC0_SCL0_DS1    */
+    volatile uint32_t  SC0_SCL0_DS2;                           /*  SC0_SCL0_DS2    */
+    volatile uint32_t  SC0_SCL0_DS3;                           /*  SC0_SCL0_DS3    */
+    volatile uint32_t  SC0_SCL0_DS4;                           /*  SC0_SCL0_DS4    */
+    volatile uint32_t  SC0_SCL0_DS5;                           /*  SC0_SCL0_DS5    */
+    volatile uint32_t  SC0_SCL0_DS6;                           /*  SC0_SCL0_DS6    */
+    volatile uint32_t  SC0_SCL0_DS7;                           /*  SC0_SCL0_DS7    */
+
+/* #define VDC5_SC0_SCL0_US1_COUNT (8) */
+    volatile uint32_t  SC0_SCL0_US1;                           /*  SC0_SCL0_US1    */
+    volatile uint32_t  SC0_SCL0_US2;                           /*  SC0_SCL0_US2    */
+    volatile uint32_t  SC0_SCL0_US3;                           /*  SC0_SCL0_US3    */
+    volatile uint32_t  SC0_SCL0_US4;                           /*  SC0_SCL0_US4    */
+    volatile uint32_t  SC0_SCL0_US5;                           /*  SC0_SCL0_US5    */
+    volatile uint32_t  SC0_SCL0_US6;                           /*  SC0_SCL0_US6    */
+    volatile uint32_t  SC0_SCL0_US7;                           /*  SC0_SCL0_US7    */
+    volatile uint32_t  SC0_SCL0_US8;                           /*  SC0_SCL0_US8    */
+    volatile uint8_t   dummy6[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_OVR1;                          /*  SC0_SCL0_OVR1   */
+    volatile uint8_t   dummy7[16];                             /*                  */
+    volatile uint32_t  SC0_SCL1_UPDATE;                        /*  SC0_SCL1_UPDATE */
+    volatile uint8_t   dummy8[4];                              /*                  */
+
+/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */
+    volatile uint32_t  SC0_SCL1_WR1;                           /*  SC0_SCL1_WR1    */
+    volatile uint32_t  SC0_SCL1_WR2;                           /*  SC0_SCL1_WR2    */
+    volatile uint32_t  SC0_SCL1_WR3;                           /*  SC0_SCL1_WR3    */
+    volatile uint32_t  SC0_SCL1_WR4;                           /*  SC0_SCL1_WR4    */
+    volatile uint8_t   dummy9[4];                              /*                  */
+    volatile uint32_t  SC0_SCL1_WR5;                           /*  SC0_SCL1_WR5    */
+    volatile uint32_t  SC0_SCL1_WR6;                           /*  SC0_SCL1_WR6    */
+    volatile uint32_t  SC0_SCL1_WR7;                           /*  SC0_SCL1_WR7    */
+    volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
+    volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
+    volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
+
+/* end of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC0_SCL1_WR11;                          /*  SC0_SCL1_WR11   */
+    volatile uint32_t  SC0_SCL1_MON1;                          /*  SC0_SCL1_MON1   */
+
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+
+/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */
+    volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
+    volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
+    volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
+    volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
+    volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
+    volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
+
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+    volatile uint8_t   dummy10[44];                            /*                  */
+
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
+    volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
+
+/* #define VDC5_GR0_FLM1_COUNT (6) */
+    volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
+    volatile uint32_t  GR0_FLM2;                               /*  GR0_FLM2        */
+    volatile uint32_t  GR0_FLM3;                               /*  GR0_FLM3        */
+    volatile uint32_t  GR0_FLM4;                               /*  GR0_FLM4        */
+    volatile uint32_t  GR0_FLM5;                               /*  GR0_FLM5        */
+    volatile uint32_t  GR0_FLM6;                               /*  GR0_FLM6        */
+
+/* #define VDC5_GR0_AB1_COUNT (3) */
+    volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
+    volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
+    volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
+
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint8_t   dummy11[12];                            /*                  */
+
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
+    volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
+    volatile uint32_t  GR0_AB9;                                /*  GR0_AB9         */
+    volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
+    volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
+    volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
+
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR0_CLUT;                               /*  GR0_CLUT        */
+    volatile uint8_t   dummy12[44];                            /*                  */
+
+/* start of struct st_vdc5_from_adj0_update */
+    volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
+    volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
+
+/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */
+    volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
+    volatile uint32_t  ADJ0_ENH_TIM2;                          /*  ADJ0_ENH_TIM2   */
+    volatile uint32_t  ADJ0_ENH_TIM3;                          /*  ADJ0_ENH_TIM3   */
+
+/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */
+    volatile uint32_t  ADJ0_ENH_SHP1;                          /*  ADJ0_ENH_SHP1   */
+    volatile uint32_t  ADJ0_ENH_SHP2;                          /*  ADJ0_ENH_SHP2   */
+    volatile uint32_t  ADJ0_ENH_SHP3;                          /*  ADJ0_ENH_SHP3   */
+    volatile uint32_t  ADJ0_ENH_SHP4;                          /*  ADJ0_ENH_SHP4   */
+    volatile uint32_t  ADJ0_ENH_SHP5;                          /*  ADJ0_ENH_SHP5   */
+    volatile uint32_t  ADJ0_ENH_SHP6;                          /*  ADJ0_ENH_SHP6   */
+
+/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */
+    volatile uint32_t  ADJ0_ENH_LTI1;                          /*  ADJ0_ENH_LTI1   */
+    volatile uint32_t  ADJ0_ENH_LTI2;                          /*  ADJ0_ENH_LTI2   */
+    volatile uint32_t  ADJ0_MTX_MODE;                          /*  ADJ0_MTX_MODE   */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ0;                       /*  ADJ0_MTX_YG_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ1;                       /*  ADJ0_MTX_YG_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ0;                      /*  ADJ0_MTX_CBB_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
+
+/* end of struct st_vdc5_from_adj0_update */
+    volatile uint8_t   dummy13[48];                            /*                  */
+
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR2_UPDATE;                             /*  GR2_UPDATE      */
+    volatile uint32_t  GR2_FLM_RD;                             /*  GR2_FLM_RD      */
+
+/* #define VDC5_GR2_FLM1_COUNT (6) */
+    volatile uint32_t  GR2_FLM1;                               /*  GR2_FLM1        */
+    volatile uint32_t  GR2_FLM2;                               /*  GR2_FLM2        */
+    volatile uint32_t  GR2_FLM3;                               /*  GR2_FLM3        */
+    volatile uint32_t  GR2_FLM4;                               /*  GR2_FLM4        */
+    volatile uint32_t  GR2_FLM5;                               /*  GR2_FLM5        */
+    volatile uint32_t  GR2_FLM6;                               /*  GR2_FLM6        */
+
+/* #define VDC5_GR2_AB1_COUNT (3) */
+    volatile uint32_t  GR2_AB1;                                /*  GR2_AB1         */
+    volatile uint32_t  GR2_AB2;                                /*  GR2_AB2         */
+    volatile uint32_t  GR2_AB3;                                /*  GR2_AB3         */
+
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR2_AB4;                                /*  GR2_AB4         */
+    volatile uint32_t  GR2_AB5;                                /*  GR2_AB5         */
+    volatile uint32_t  GR2_AB6;                                /*  GR2_AB6         */
+
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR2_AB7;                                /*  GR2_AB7         */
+    volatile uint32_t  GR2_AB8;                                /*  GR2_AB8         */
+    volatile uint32_t  GR2_AB9;                                /*  GR2_AB9         */
+    volatile uint32_t  GR2_AB10;                               /*  GR2_AB10        */
+    volatile uint32_t  GR2_AB11;                               /*  GR2_AB11        */
+    volatile uint32_t  GR2_BASE;                               /*  GR2_BASE        */
+
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR2_CLUT;                               /*  GR2_CLUT        */
+    volatile uint32_t  GR2_MON;                                /*  GR2_MON         */
+    volatile uint8_t   dummy14[40];                            /*                  */
+
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR3_UPDATE;                             /*  GR3_UPDATE      */
+    volatile uint32_t  GR3_FLM_RD;                             /*  GR3_FLM_RD      */
+
+/* #define VDC5_GR3_FLM1_COUNT (6) */
+    volatile uint32_t  GR3_FLM1;                               /*  GR3_FLM1        */
+    volatile uint32_t  GR3_FLM2;                               /*  GR3_FLM2        */
+    volatile uint32_t  GR3_FLM3;                               /*  GR3_FLM3        */
+    volatile uint32_t  GR3_FLM4;                               /*  GR3_FLM4        */
+    volatile uint32_t  GR3_FLM5;                               /*  GR3_FLM5        */
+    volatile uint32_t  GR3_FLM6;                               /*  GR3_FLM6        */
+
+/* #define VDC5_GR3_AB1_COUNT (3) */
+    volatile uint32_t  GR3_AB1;                                /*  GR3_AB1         */
+    volatile uint32_t  GR3_AB2;                                /*  GR3_AB2         */
+    volatile uint32_t  GR3_AB3;                                /*  GR3_AB3         */
+
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR3_AB4;                                /*  GR3_AB4         */
+    volatile uint32_t  GR3_AB5;                                /*  GR3_AB5         */
+    volatile uint32_t  GR3_AB6;                                /*  GR3_AB6         */
+
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR3_AB7;                                /*  GR3_AB7         */
+    volatile uint32_t  GR3_AB8;                                /*  GR3_AB8         */
+    volatile uint32_t  GR3_AB9;                                /*  GR3_AB9         */
+    volatile uint32_t  GR3_AB10;                               /*  GR3_AB10        */
+    volatile uint32_t  GR3_AB11;                               /*  GR3_AB11        */
+    volatile uint32_t  GR3_BASE;                               /*  GR3_BASE        */
+
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR3_CLUT_INT;                           /*  GR3_CLUT_INT    */
+    volatile uint32_t  GR3_MON;                                /*  GR3_MON         */
+    volatile uint8_t   dummy15[40];                            /*                  */
+    volatile uint32_t  GAM_G_UPDATE;                           /*  GAM_G_UPDATE    */
+    volatile uint32_t  GAM_SW;                                 /*  GAM_SW          */
+
+/* #define VDC5_GAM_G_LUT1_COUNT (16) */
+    volatile uint32_t  GAM_G_LUT1;                             /*  GAM_G_LUT1      */
+    volatile uint32_t  GAM_G_LUT2;                             /*  GAM_G_LUT2      */
+    volatile uint32_t  GAM_G_LUT3;                             /*  GAM_G_LUT3      */
+    volatile uint32_t  GAM_G_LUT4;                             /*  GAM_G_LUT4      */
+    volatile uint32_t  GAM_G_LUT5;                             /*  GAM_G_LUT5      */
+    volatile uint32_t  GAM_G_LUT6;                             /*  GAM_G_LUT6      */
+    volatile uint32_t  GAM_G_LUT7;                             /*  GAM_G_LUT7      */
+    volatile uint32_t  GAM_G_LUT8;                             /*  GAM_G_LUT8      */
+    volatile uint32_t  GAM_G_LUT9;                             /*  GAM_G_LUT9      */
+    volatile uint32_t  GAM_G_LUT10;                            /*  GAM_G_LUT10     */
+    volatile uint32_t  GAM_G_LUT11;                            /*  GAM_G_LUT11     */
+    volatile uint32_t  GAM_G_LUT12;                            /*  GAM_G_LUT12     */
+    volatile uint32_t  GAM_G_LUT13;                            /*  GAM_G_LUT13     */
+    volatile uint32_t  GAM_G_LUT14;                            /*  GAM_G_LUT14     */
+    volatile uint32_t  GAM_G_LUT15;                            /*  GAM_G_LUT15     */
+    volatile uint32_t  GAM_G_LUT16;                            /*  GAM_G_LUT16     */
+
+/* #define VDC5_GAM_G_AREA1_COUNT (8) */
+    volatile uint32_t  GAM_G_AREA1;                            /*  GAM_G_AREA1     */
+    volatile uint32_t  GAM_G_AREA2;                            /*  GAM_G_AREA2     */
+    volatile uint32_t  GAM_G_AREA3;                            /*  GAM_G_AREA3     */
+    volatile uint32_t  GAM_G_AREA4;                            /*  GAM_G_AREA4     */
+    volatile uint32_t  GAM_G_AREA5;                            /*  GAM_G_AREA5     */
+    volatile uint32_t  GAM_G_AREA6;                            /*  GAM_G_AREA6     */
+    volatile uint32_t  GAM_G_AREA7;                            /*  GAM_G_AREA7     */
+    volatile uint32_t  GAM_G_AREA8;                            /*  GAM_G_AREA8     */
+    volatile uint8_t   dummy16[24];                            /*                  */
+    volatile uint32_t  GAM_B_UPDATE;                           /*  GAM_B_UPDATE    */
+    volatile uint8_t   dummy17[4];                             /*                  */
+
+/* #define VDC5_GAM_B_LUT1_COUNT (16) */
+    volatile uint32_t  GAM_B_LUT1;                             /*  GAM_B_LUT1      */
+    volatile uint32_t  GAM_B_LUT2;                             /*  GAM_B_LUT2      */
+    volatile uint32_t  GAM_B_LUT3;                             /*  GAM_B_LUT3      */
+    volatile uint32_t  GAM_B_LUT4;                             /*  GAM_B_LUT4      */
+    volatile uint32_t  GAM_B_LUT5;                             /*  GAM_B_LUT5      */
+    volatile uint32_t  GAM_B_LUT6;                             /*  GAM_B_LUT6      */
+    volatile uint32_t  GAM_B_LUT7;                             /*  GAM_B_LUT7      */
+    volatile uint32_t  GAM_B_LUT8;                             /*  GAM_B_LUT8      */
+    volatile uint32_t  GAM_B_LUT9;                             /*  GAM_B_LUT9      */
+    volatile uint32_t  GAM_B_LUT10;                            /*  GAM_B_LUT10     */
+    volatile uint32_t  GAM_B_LUT11;                            /*  GAM_B_LUT11     */
+    volatile uint32_t  GAM_B_LUT12;                            /*  GAM_B_LUT12     */
+    volatile uint32_t  GAM_B_LUT13;                            /*  GAM_B_LUT13     */
+    volatile uint32_t  GAM_B_LUT14;                            /*  GAM_B_LUT14     */
+    volatile uint32_t  GAM_B_LUT15;                            /*  GAM_B_LUT15     */
+    volatile uint32_t  GAM_B_LUT16;                            /*  GAM_B_LUT16     */
+
+/* #define VDC5_GAM_B_AREA1_COUNT (8) */
+    volatile uint32_t  GAM_B_AREA1;                            /*  GAM_B_AREA1     */
+    volatile uint32_t  GAM_B_AREA2;                            /*  GAM_B_AREA2     */
+    volatile uint32_t  GAM_B_AREA3;                            /*  GAM_B_AREA3     */
+    volatile uint32_t  GAM_B_AREA4;                            /*  GAM_B_AREA4     */
+    volatile uint32_t  GAM_B_AREA5;                            /*  GAM_B_AREA5     */
+    volatile uint32_t  GAM_B_AREA6;                            /*  GAM_B_AREA6     */
+    volatile uint32_t  GAM_B_AREA7;                            /*  GAM_B_AREA7     */
+    volatile uint32_t  GAM_B_AREA8;                            /*  GAM_B_AREA8     */
+    volatile uint8_t   dummy18[24];                            /*                  */
+    volatile uint32_t  GAM_R_UPDATE;                           /*  GAM_R_UPDATE    */
+    volatile uint8_t   dummy19[4];                             /*                  */
+
+/* #define VDC5_GAM_R_LUT1_COUNT (16) */
+    volatile uint32_t  GAM_R_LUT1;                             /*  GAM_R_LUT1      */
+    volatile uint32_t  GAM_R_LUT2;                             /*  GAM_R_LUT2      */
+    volatile uint32_t  GAM_R_LUT3;                             /*  GAM_R_LUT3      */
+    volatile uint32_t  GAM_R_LUT4;                             /*  GAM_R_LUT4      */
+    volatile uint32_t  GAM_R_LUT5;                             /*  GAM_R_LUT5      */
+    volatile uint32_t  GAM_R_LUT6;                             /*  GAM_R_LUT6      */
+    volatile uint32_t  GAM_R_LUT7;                             /*  GAM_R_LUT7      */
+    volatile uint32_t  GAM_R_LUT8;                             /*  GAM_R_LUT8      */
+    volatile uint32_t  GAM_R_LUT9;                             /*  GAM_R_LUT9      */
+    volatile uint32_t  GAM_R_LUT10;                            /*  GAM_R_LUT10     */
+    volatile uint32_t  GAM_R_LUT11;                            /*  GAM_R_LUT11     */
+    volatile uint32_t  GAM_R_LUT12;                            /*  GAM_R_LUT12     */
+    volatile uint32_t  GAM_R_LUT13;                            /*  GAM_R_LUT13     */
+    volatile uint32_t  GAM_R_LUT14;                            /*  GAM_R_LUT14     */
+    volatile uint32_t  GAM_R_LUT15;                            /*  GAM_R_LUT15     */
+    volatile uint32_t  GAM_R_LUT16;                            /*  GAM_R_LUT16     */
+
+/* #define VDC5_GAM_R_AREA1_COUNT (8) */
+    volatile uint32_t  GAM_R_AREA1;                            /*  GAM_R_AREA1     */
+    volatile uint32_t  GAM_R_AREA2;                            /*  GAM_R_AREA2     */
+    volatile uint32_t  GAM_R_AREA3;                            /*  GAM_R_AREA3     */
+    volatile uint32_t  GAM_R_AREA4;                            /*  GAM_R_AREA4     */
+    volatile uint32_t  GAM_R_AREA5;                            /*  GAM_R_AREA5     */
+    volatile uint32_t  GAM_R_AREA6;                            /*  GAM_R_AREA6     */
+    volatile uint32_t  GAM_R_AREA7;                            /*  GAM_R_AREA7     */
+    volatile uint32_t  GAM_R_AREA8;                            /*  GAM_R_AREA8     */
+    volatile uint8_t   dummy20[24];                            /*                  */
+    volatile uint32_t  TCON_UPDATE;                            /*  TCON_UPDATE     */
+    volatile uint32_t  TCON_TIM;                               /*  TCON_TIM        */
+
+/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */
+    volatile uint32_t  TCON_TIM_STVA1;                         /*  TCON_TIM_STVA1  */
+    volatile uint32_t  TCON_TIM_STVA2;                         /*  TCON_TIM_STVA2  */
+
+/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */
+    volatile uint32_t  TCON_TIM_STVB1;                         /*  TCON_TIM_STVB1  */
+    volatile uint32_t  TCON_TIM_STVB2;                         /*  TCON_TIM_STVB2  */
+
+/* #define VDC5_TCON_TIM_STH1_COUNT (2) */
+    volatile uint32_t  TCON_TIM_STH1;                          /*  TCON_TIM_STH1   */
+    volatile uint32_t  TCON_TIM_STH2;                          /*  TCON_TIM_STH2   */
+
+/* #define VDC5_TCON_TIM_STB1_COUNT (2) */
+    volatile uint32_t  TCON_TIM_STB1;                          /*  TCON_TIM_STB1   */
+    volatile uint32_t  TCON_TIM_STB2;                          /*  TCON_TIM_STB2   */
+
+/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */
+    volatile uint32_t  TCON_TIM_CPV1;                          /*  TCON_TIM_CPV1   */
+    volatile uint32_t  TCON_TIM_CPV2;                          /*  TCON_TIM_CPV2   */
+
+/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */
+    volatile uint32_t  TCON_TIM_POLA1;                         /*  TCON_TIM_POLA1  */
+    volatile uint32_t  TCON_TIM_POLA2;                         /*  TCON_TIM_POLA2  */
+
+/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */
+    volatile uint32_t  TCON_TIM_POLB1;                         /*  TCON_TIM_POLB1  */
+    volatile uint32_t  TCON_TIM_POLB2;                         /*  TCON_TIM_POLB2  */
+    volatile uint32_t  TCON_TIM_DE;                            /*  TCON_TIM_DE     */
+    volatile uint8_t   dummy21[60];                            /*                  */
+    volatile uint32_t  OUT_UPDATE;                             /*  OUT_UPDATE      */
+    volatile uint32_t  OUT_SET;                                /*  OUT_SET         */
+
+/* #define VDC5_OUT_BRIGHT1_COUNT (2) */
+    volatile uint32_t  OUT_BRIGHT1;                            /*  OUT_BRIGHT1     */
+    volatile uint32_t  OUT_BRIGHT2;                            /*  OUT_BRIGHT2     */
+    volatile uint32_t  OUT_CONTRAST;                           /*  OUT_CONTRAST    */
+    volatile uint32_t  OUT_PDTHA;                              /*  OUT_PDTHA       */
+    volatile uint8_t   dummy22[12];                            /*                  */
+    volatile uint32_t  OUT_CLK_PHASE;                          /*  OUT_CLK_PHASE   */
+    volatile uint8_t   dummy23[88];                            /*                  */
+
+/* #define VDC5_SYSCNT_INT1_COUNT (6) */
+    volatile uint32_t  SYSCNT_INT1;                            /*  SYSCNT_INT1     */
+    volatile uint32_t  SYSCNT_INT2;                            /*  SYSCNT_INT2     */
+    volatile uint32_t  SYSCNT_INT3;                            /*  SYSCNT_INT3     */
+    volatile uint32_t  SYSCNT_INT4;                            /*  SYSCNT_INT4     */
+    volatile uint32_t  SYSCNT_INT5;                            /*  SYSCNT_INT5     */
+    volatile uint32_t  SYSCNT_INT6;                            /*  SYSCNT_INT6     */
+    volatile uint16_t SYSCNT_PANEL_CLK;                       /*  SYSCNT_PANEL_CLK */
+    volatile uint16_t SYSCNT_CLUT;                            /*  SYSCNT_CLUT     */
+    volatile uint8_t   dummy24[356];                           /*                  */
+
+/* start of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC1_SCL0_UPDATE;                        /*  SC1_SCL0_UPDATE */
+
+/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */
+    volatile uint32_t  SC1_SCL0_FRC1;                          /*  SC1_SCL0_FRC1   */
+    volatile uint32_t  SC1_SCL0_FRC2;                          /*  SC1_SCL0_FRC2   */
+    volatile uint32_t  SC1_SCL0_FRC3;                          /*  SC1_SCL0_FRC3   */
+    volatile uint32_t  SC1_SCL0_FRC4;                          /*  SC1_SCL0_FRC4   */
+    volatile uint32_t  SC1_SCL0_FRC5;                          /*  SC1_SCL0_FRC5   */
+    volatile uint32_t  SC1_SCL0_FRC6;                          /*  SC1_SCL0_FRC6   */
+    volatile uint32_t  SC1_SCL0_FRC7;                          /*  SC1_SCL0_FRC7   */
+    volatile uint8_t   dummy25[4];                             /*                  */
+    volatile uint32_t  SC1_SCL0_FRC9;                          /*  SC1_SCL0_FRC9   */
+    volatile uint16_t SC1_SCL0_MON0;                          /*  SC1_SCL0_MON0   */
+    volatile uint16_t SC1_SCL0_INT;                           /*  SC1_SCL0_INT    */
+
+/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */
+    volatile uint32_t  SC1_SCL0_DS1;                           /*  SC1_SCL0_DS1    */
+    volatile uint32_t  SC1_SCL0_DS2;                           /*  SC1_SCL0_DS2    */
+    volatile uint32_t  SC1_SCL0_DS3;                           /*  SC1_SCL0_DS3    */
+    volatile uint32_t  SC1_SCL0_DS4;                           /*  SC1_SCL0_DS4    */
+    volatile uint32_t  SC1_SCL0_DS5;                           /*  SC1_SCL0_DS5    */
+    volatile uint32_t  SC1_SCL0_DS6;                           /*  SC1_SCL0_DS6    */
+    volatile uint32_t  SC1_SCL0_DS7;                           /*  SC1_SCL0_DS7    */
+
+/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */
+    volatile uint32_t  SC1_SCL0_US1;                           /*  SC1_SCL0_US1    */
+    volatile uint32_t  SC1_SCL0_US2;                           /*  SC1_SCL0_US2    */
+    volatile uint32_t  SC1_SCL0_US3;                           /*  SC1_SCL0_US3    */
+    volatile uint32_t  SC1_SCL0_US4;                           /*  SC1_SCL0_US4    */
+    volatile uint32_t  SC1_SCL0_US5;                           /*  SC1_SCL0_US5    */
+    volatile uint32_t  SC1_SCL0_US6;                           /*  SC1_SCL0_US6    */
+    volatile uint32_t  SC1_SCL0_US7;                           /*  SC1_SCL0_US7    */
+    volatile uint32_t  SC1_SCL0_US8;                           /*  SC1_SCL0_US8    */
+    volatile uint8_t   dummy26[4];                             /*                  */
+    volatile uint32_t  SC1_SCL0_OVR1;                          /*  SC1_SCL0_OVR1   */
+    volatile uint8_t   dummy27[16];                            /*                  */
+    volatile uint32_t  SC1_SCL1_UPDATE;                        /*  SC1_SCL1_UPDATE */
+    volatile uint8_t   dummy28[4];                             /*                  */
+
+/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */
+    volatile uint32_t  SC1_SCL1_WR1;                           /*  SC1_SCL1_WR1    */
+    volatile uint32_t  SC1_SCL1_WR2;                           /*  SC1_SCL1_WR2    */
+    volatile uint32_t  SC1_SCL1_WR3;                           /*  SC1_SCL1_WR3    */
+    volatile uint32_t  SC1_SCL1_WR4;                           /*  SC1_SCL1_WR4    */
+    volatile uint8_t   dummy29[4];                             /*                  */
+    volatile uint32_t  SC1_SCL1_WR5;                           /*  SC1_SCL1_WR5    */
+    volatile uint32_t  SC1_SCL1_WR6;                           /*  SC1_SCL1_WR6    */
+    volatile uint32_t  SC1_SCL1_WR7;                           /*  SC1_SCL1_WR7    */
+    volatile uint32_t  SC1_SCL1_WR8;                           /*  SC1_SCL1_WR8    */
+    volatile uint32_t  SC1_SCL1_WR9;                           /*  SC1_SCL1_WR9    */
+    volatile uint32_t  SC1_SCL1_WR10;                          /*  SC1_SCL1_WR10   */
+
+/* end of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC1_SCL1_WR11;                          /*  SC1_SCL1_WR11   */
+    volatile uint32_t  SC1_SCL1_MON1;                          /*  SC1_SCL1_MON1   */
+
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+
+/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */
+    volatile uint32_t  SC1_SCL1_PBUF0;                         /*  SC1_SCL1_PBUF0  */
+    volatile uint32_t  SC1_SCL1_PBUF1;                         /*  SC1_SCL1_PBUF1  */
+    volatile uint32_t  SC1_SCL1_PBUF2;                         /*  SC1_SCL1_PBUF2  */
+    volatile uint32_t  SC1_SCL1_PBUF3;                         /*  SC1_SCL1_PBUF3  */
+    volatile uint32_t  SC1_SCL1_PBUF_FLD;                      /*  SC1_SCL1_PBUF_FLD */
+    volatile uint32_t  SC1_SCL1_PBUF_CNT;                      /*  SC1_SCL1_PBUF_CNT */
+
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+    volatile uint8_t   dummy30[44];                            /*                  */
+
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR1_UPDATE;                             /*  GR1_UPDATE      */
+    volatile uint32_t  GR1_FLM_RD;                             /*  GR1_FLM_RD      */
+
+/* #define VDC5_GR1_FLM1_COUNT (6) */
+    volatile uint32_t  GR1_FLM1;                               /*  GR1_FLM1        */
+    volatile uint32_t  GR1_FLM2;                               /*  GR1_FLM2        */
+    volatile uint32_t  GR1_FLM3;                               /*  GR1_FLM3        */
+    volatile uint32_t  GR1_FLM4;                               /*  GR1_FLM4        */
+    volatile uint32_t  GR1_FLM5;                               /*  GR1_FLM5        */
+    volatile uint32_t  GR1_FLM6;                               /*  GR1_FLM6        */
+
+/* #define VDC5_GR1_AB1_COUNT (3) */
+    volatile uint32_t  GR1_AB1;                                /*  GR1_AB1         */
+    volatile uint32_t  GR1_AB2;                                /*  GR1_AB2         */
+    volatile uint32_t  GR1_AB3;                                /*  GR1_AB3         */
+
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR1_AB4;                                /*  GR1_AB4         */
+    volatile uint32_t  GR1_AB5;                                /*  GR1_AB5         */
+    volatile uint32_t  GR1_AB6;                                /*  GR1_AB6         */
+
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR1_AB7;                                /*  GR1_AB7         */
+    volatile uint32_t  GR1_AB8;                                /*  GR1_AB8         */
+    volatile uint32_t  GR1_AB9;                                /*  GR1_AB9         */
+    volatile uint32_t  GR1_AB10;                               /*  GR1_AB10        */
+    volatile uint32_t  GR1_AB11;                               /*  GR1_AB11        */
+    volatile uint32_t  GR1_BASE;                               /*  GR1_BASE        */
+
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR1_CLUT;                               /*  GR1_CLUT        */
+    volatile uint32_t  GR1_MON;                                /*  GR1_MON         */
+    volatile uint8_t   dummy31[40];                            /*                  */
+
+/* start of struct st_vdc5_from_adj0_update */
+    volatile uint32_t  ADJ1_UPDATE;                            /*  ADJ1_UPDATE     */
+    volatile uint32_t  ADJ1_BKSTR_SET;                         /*  ADJ1_BKSTR_SET  */
+
+/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */
+    volatile uint32_t  ADJ1_ENH_TIM1;                          /*  ADJ1_ENH_TIM1   */
+    volatile uint32_t  ADJ1_ENH_TIM2;                          /*  ADJ1_ENH_TIM2   */
+    volatile uint32_t  ADJ1_ENH_TIM3;                          /*  ADJ1_ENH_TIM3   */
+
+/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */
+    volatile uint32_t  ADJ1_ENH_SHP1;                          /*  ADJ1_ENH_SHP1   */
+    volatile uint32_t  ADJ1_ENH_SHP2;                          /*  ADJ1_ENH_SHP2   */
+    volatile uint32_t  ADJ1_ENH_SHP3;                          /*  ADJ1_ENH_SHP3   */
+    volatile uint32_t  ADJ1_ENH_SHP4;                          /*  ADJ1_ENH_SHP4   */
+    volatile uint32_t  ADJ1_ENH_SHP5;                          /*  ADJ1_ENH_SHP5   */
+    volatile uint32_t  ADJ1_ENH_SHP6;                          /*  ADJ1_ENH_SHP6   */
+
+/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */
+    volatile uint32_t  ADJ1_ENH_LTI1;                          /*  ADJ1_ENH_LTI1   */
+    volatile uint32_t  ADJ1_ENH_LTI2;                          /*  ADJ1_ENH_LTI2   */
+    volatile uint32_t  ADJ1_MTX_MODE;                          /*  ADJ1_MTX_MODE   */
+    volatile uint32_t  ADJ1_MTX_YG_ADJ0;                       /*  ADJ1_MTX_YG_ADJ0 */
+    volatile uint32_t  ADJ1_MTX_YG_ADJ1;                       /*  ADJ1_MTX_YG_ADJ1 */
+    volatile uint32_t  ADJ1_MTX_CBB_ADJ0;                      /*  ADJ1_MTX_CBB_ADJ0 */
+    volatile uint32_t  ADJ1_MTX_CBB_ADJ1;                      /*  ADJ1_MTX_CBB_ADJ1 */
+    volatile uint32_t  ADJ1_MTX_CRR_ADJ0;                      /*  ADJ1_MTX_CRR_ADJ0 */
+    volatile uint32_t  ADJ1_MTX_CRR_ADJ1;                      /*  ADJ1_MTX_CRR_ADJ1 */
+
+/* end of struct st_vdc5_from_adj0_update */
+    volatile uint8_t   dummy32[48];                            /*                  */
+    volatile uint32_t  GR_VIN_UPDATE;                          /*  GR_VIN_UPDATE   */
+    volatile uint8_t   dummy33[28];                            /*                  */
+
+/* #define VDC5_GR_VIN_AB1_COUNT (7) */
+    volatile uint32_t  GR_VIN_AB1;                             /*  GR_VIN_AB1      */
+    volatile uint32_t  GR_VIN_AB2;                             /*  GR_VIN_AB2      */
+    volatile uint32_t  GR_VIN_AB3;                             /*  GR_VIN_AB3      */
+    volatile uint32_t  GR_VIN_AB4;                             /*  GR_VIN_AB4      */
+    volatile uint32_t  GR_VIN_AB5;                             /*  GR_VIN_AB5      */
+    volatile uint32_t  GR_VIN_AB6;                             /*  GR_VIN_AB6      */
+    volatile uint32_t  GR_VIN_AB7;                             /*  GR_VIN_AB7      */
+    volatile uint8_t   dummy34[16];                            /*                  */
+    volatile uint32_t  GR_VIN_BASE;                            /*  GR_VIN_BASE     */
+    volatile uint8_t   dummy35[4];                             /*                  */
+    volatile uint32_t  GR_VIN_MON;                             /*  GR_VIN_MON      */
+    volatile uint8_t   dummy36[40];                            /*                  */
+    volatile uint32_t  OIR_SCL0_UPDATE;                        /*  OIR_SCL0_UPDATE */
+
+/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */
+    volatile uint32_t  OIR_SCL0_FRC1;                          /*  OIR_SCL0_FRC1   */
+    volatile uint32_t  OIR_SCL0_FRC2;                          /*  OIR_SCL0_FRC2   */
+    volatile uint32_t  OIR_SCL0_FRC3;                          /*  OIR_SCL0_FRC3   */
+    volatile uint32_t  OIR_SCL0_FRC4;                          /*  OIR_SCL0_FRC4   */
+    volatile uint32_t  OIR_SCL0_FRC5;                          /*  OIR_SCL0_FRC5   */
+    volatile uint32_t  OIR_SCL0_FRC6;                          /*  OIR_SCL0_FRC6   */
+    volatile uint32_t  OIR_SCL0_FRC7;                          /*  OIR_SCL0_FRC7   */
+    volatile uint8_t   dummy37[12];                            /*                  */
+
+/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */
+    volatile uint32_t  OIR_SCL0_DS1;                           /*  OIR_SCL0_DS1    */
+    volatile uint32_t  OIR_SCL0_DS2;                           /*  OIR_SCL0_DS2    */
+    volatile uint32_t  OIR_SCL0_DS3;                           /*  OIR_SCL0_DS3    */
+    volatile uint8_t   dummy38[12];                            /*                  */
+    volatile uint32_t  OIR_SCL0_DS7;                           /*  OIR_SCL0_DS7    */
+    volatile uint32_t  OIR_SCL0_US1;                           /*  OIR_SCL0_US1    */
+    volatile uint32_t  OIR_SCL0_US2;                           /*  OIR_SCL0_US2    */
+    volatile uint32_t  OIR_SCL0_US3;                           /*  OIR_SCL0_US3    */
+    volatile uint8_t   dummy39[16];                            /*                  */
+    volatile uint32_t  OIR_SCL0_US8;                           /*  OIR_SCL0_US8    */
+    volatile uint8_t   dummy40[4];                             /*                  */
+    volatile uint32_t  OIR_SCL0_OVR1;                          /*  OIR_SCL0_OVR1   */
+    volatile uint8_t   dummy41[16];                            /*                  */
+    volatile uint32_t  OIR_SCL1_UPDATE;                        /*  OIR_SCL1_UPDATE */
+    volatile uint8_t   dummy42[4];                             /*                  */
+
+/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */
+    volatile uint32_t  OIR_SCL1_WR1;                           /*  OIR_SCL1_WR1    */
+    volatile uint32_t  OIR_SCL1_WR2;                           /*  OIR_SCL1_WR2    */
+    volatile uint32_t  OIR_SCL1_WR3;                           /*  OIR_SCL1_WR3    */
+    volatile uint32_t  OIR_SCL1_WR4;                           /*  OIR_SCL1_WR4    */
+    volatile uint8_t   dummy43[4];                             /*                  */
+    volatile uint32_t  OIR_SCL1_WR5;                           /*  OIR_SCL1_WR5    */
+    volatile uint32_t  OIR_SCL1_WR6;                           /*  OIR_SCL1_WR6    */
+    volatile uint32_t  OIR_SCL1_WR7;                           /*  OIR_SCL1_WR7    */
+    volatile uint8_t   dummy44[88];                            /*                  */
+    volatile uint32_t  GR_OIR_UPDATE;                          /*  GR_OIR_UPDATE   */
+    volatile uint32_t  GR_OIR_FLM_RD;                          /*  GR_OIR_FLM_RD   */
+
+/* #define VDC5_GR_OIR_FLM1_COUNT (6) */
+    volatile uint32_t  GR_OIR_FLM1;                            /*  GR_OIR_FLM1     */
+    volatile uint32_t  GR_OIR_FLM2;                            /*  GR_OIR_FLM2     */
+    volatile uint32_t  GR_OIR_FLM3;                            /*  GR_OIR_FLM3     */
+    volatile uint32_t  GR_OIR_FLM4;                            /*  GR_OIR_FLM4     */
+    volatile uint32_t  GR_OIR_FLM5;                            /*  GR_OIR_FLM5     */
+    volatile uint32_t  GR_OIR_FLM6;                            /*  GR_OIR_FLM6     */
+
+/* #define VDC5_GR_OIR_AB1_COUNT (3) */
+    volatile uint32_t  GR_OIR_AB1;                             /*  GR_OIR_AB1      */
+    volatile uint32_t  GR_OIR_AB2;                             /*  GR_OIR_AB2      */
+    volatile uint32_t  GR_OIR_AB3;                             /*  GR_OIR_AB3      */
+    volatile uint8_t   dummy45[12];                            /*                  */
+    volatile uint32_t  GR_OIR_AB7;                             /*  GR_OIR_AB7      */
+    volatile uint32_t  GR_OIR_AB8;                             /*  GR_OIR_AB8      */
+    volatile uint32_t  GR_OIR_AB9;                             /*  GR_OIR_AB9      */
+    volatile uint32_t  GR_OIR_AB10;                            /*  GR_OIR_AB10     */
+    volatile uint32_t  GR_OIR_AB11;                            /*  GR_OIR_AB11     */
+    volatile uint32_t  GR_OIR_BASE;                            /*  GR_OIR_BASE     */
+    volatile uint32_t  GR_OIR_CLUT;                            /*  GR_OIR_CLUT     */
+    volatile uint32_t  GR_OIR_MON;                             /*  GR_OIR_MON      */
+} r_io_vdc5_t;
+
+
+typedef struct st_vdc5_from_gr0_update
+{
+ 
+    volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
+    volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
+    volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
+    volatile uint32_t  GR0_FLM2;                               /*  GR0_FLM2        */
+    volatile uint32_t  GR0_FLM3;                               /*  GR0_FLM3        */
+    volatile uint32_t  GR0_FLM4;                               /*  GR0_FLM4        */
+    volatile uint32_t  GR0_FLM5;                               /*  GR0_FLM5        */
+    volatile uint32_t  GR0_FLM6;                               /*  GR0_FLM6        */
+    volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
+    volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
+    volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
+} r_io_vdc5_from_gr0_update_t;
+
+
+typedef struct st_vdc5_from_gr0_ab7
+{
+ 
+    volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
+    volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
+    volatile uint32_t  GR0_AB9;                                /*  GR0_AB9         */
+    volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
+    volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
+    volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
+} r_io_vdc5_from_gr0_ab7_t;
+
+
+typedef struct st_vdc5_from_adj0_update
+{
+ 
+    volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
+    volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
+    volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
+    volatile uint32_t  ADJ0_ENH_TIM2;                          /*  ADJ0_ENH_TIM2   */
+    volatile uint32_t  ADJ0_ENH_TIM3;                          /*  ADJ0_ENH_TIM3   */
+    volatile uint32_t  ADJ0_ENH_SHP1;                          /*  ADJ0_ENH_SHP1   */
+    volatile uint32_t  ADJ0_ENH_SHP2;                          /*  ADJ0_ENH_SHP2   */
+    volatile uint32_t  ADJ0_ENH_SHP3;                          /*  ADJ0_ENH_SHP3   */
+    volatile uint32_t  ADJ0_ENH_SHP4;                          /*  ADJ0_ENH_SHP4   */
+    volatile uint32_t  ADJ0_ENH_SHP5;                          /*  ADJ0_ENH_SHP5   */
+    volatile uint32_t  ADJ0_ENH_SHP6;                          /*  ADJ0_ENH_SHP6   */
+    volatile uint32_t  ADJ0_ENH_LTI1;                          /*  ADJ0_ENH_LTI1   */
+    volatile uint32_t  ADJ0_ENH_LTI2;                          /*  ADJ0_ENH_LTI2   */
+    volatile uint32_t  ADJ0_MTX_MODE;                          /*  ADJ0_MTX_MODE   */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ0;                       /*  ADJ0_MTX_YG_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ1;                       /*  ADJ0_MTX_YG_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ0;                      /*  ADJ0_MTX_CBB_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
+} r_io_vdc5_from_adj0_update_t;
+
+
+typedef struct st_vdc5_from_sc0_scl0_update
+{
+ 
+    volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
+    volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
+    volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
+    volatile uint32_t  SC0_SCL0_FRC3;                          /*  SC0_SCL0_FRC3   */
+    volatile uint32_t  SC0_SCL0_FRC4;                          /*  SC0_SCL0_FRC4   */
+    volatile uint32_t  SC0_SCL0_FRC5;                          /*  SC0_SCL0_FRC5   */
+    volatile uint32_t  SC0_SCL0_FRC6;                          /*  SC0_SCL0_FRC6   */
+    volatile uint32_t  SC0_SCL0_FRC7;                          /*  SC0_SCL0_FRC7   */
+    volatile uint8_t   dummy5[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_FRC9;                          /*  SC0_SCL0_FRC9   */
+    volatile uint16_t SC0_SCL0_MON0;                          /*  SC0_SCL0_MON0   */
+    volatile uint16_t SC0_SCL0_INT;                           /*  SC0_SCL0_INT    */
+    volatile uint32_t  SC0_SCL0_DS1;                           /*  SC0_SCL0_DS1    */
+    volatile uint32_t  SC0_SCL0_DS2;                           /*  SC0_SCL0_DS2    */
+    volatile uint32_t  SC0_SCL0_DS3;                           /*  SC0_SCL0_DS3    */
+    volatile uint32_t  SC0_SCL0_DS4;                           /*  SC0_SCL0_DS4    */
+    volatile uint32_t  SC0_SCL0_DS5;                           /*  SC0_SCL0_DS5    */
+    volatile uint32_t  SC0_SCL0_DS6;                           /*  SC0_SCL0_DS6    */
+    volatile uint32_t  SC0_SCL0_DS7;                           /*  SC0_SCL0_DS7    */
+    volatile uint32_t  SC0_SCL0_US1;                           /*  SC0_SCL0_US1    */
+    volatile uint32_t  SC0_SCL0_US2;                           /*  SC0_SCL0_US2    */
+    volatile uint32_t  SC0_SCL0_US3;                           /*  SC0_SCL0_US3    */
+    volatile uint32_t  SC0_SCL0_US4;                           /*  SC0_SCL0_US4    */
+    volatile uint32_t  SC0_SCL0_US5;                           /*  SC0_SCL0_US5    */
+    volatile uint32_t  SC0_SCL0_US6;                           /*  SC0_SCL0_US6    */
+    volatile uint32_t  SC0_SCL0_US7;                           /*  SC0_SCL0_US7    */
+    volatile uint32_t  SC0_SCL0_US8;                           /*  SC0_SCL0_US8    */
+    volatile uint8_t   dummy6[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_OVR1;                          /*  SC0_SCL0_OVR1   */
+    volatile uint8_t   dummy7[16];                             /*                  */
+    volatile uint32_t  SC0_SCL1_UPDATE;                        /*  SC0_SCL1_UPDATE */
+    volatile uint8_t   dummy8[4];                              /*                  */
+    volatile uint32_t  SC0_SCL1_WR1;                           /*  SC0_SCL1_WR1    */
+    volatile uint32_t  SC0_SCL1_WR2;                           /*  SC0_SCL1_WR2    */
+    volatile uint32_t  SC0_SCL1_WR3;                           /*  SC0_SCL1_WR3    */
+    volatile uint32_t  SC0_SCL1_WR4;                           /*  SC0_SCL1_WR4    */
+    volatile uint8_t   dummy9[4];                              /*                  */
+    volatile uint32_t  SC0_SCL1_WR5;                           /*  SC0_SCL1_WR5    */
+    volatile uint32_t  SC0_SCL1_WR6;                           /*  SC0_SCL1_WR6    */
+    volatile uint32_t  SC0_SCL1_WR7;                           /*  SC0_SCL1_WR7    */
+    volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
+    volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
+    volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
+} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */;
+
+
+typedef struct st_vdc5_from_sc0_scl1_pbuf0
+{
+ 
+    volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
+    volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
+    volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
+    volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
+    volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
+    volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
+} r_io_vdc5_from_sc0_scl1_pbuf0_t;
+
+
+/* Channel array defines of VDC5 (2)*/
+#ifdef  DECLARE_VDC5_CHANNELS
+volatile struct st_vdc5*  VDC5[ VDC5_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC5_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC5_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS
+volatile struct st_vdc5_from_sc0_scl1_pbuf0*  VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_sc0_scl0_update*  VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_adj0_update*  VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */
+/* End of channel array defines of VDC5 (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h	(revision 374)
@@ -0,0 +1,57 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : wdt_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef WDT_IODEFINE_H
+#define WDT_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+#define WDT     (*(struct st_wdt     *)0xFCFE0000uL) /* WDT */
+
+
+#define WDTWTCSR (WDT.WTCSR)
+#define WDTWTCNT (WDT.WTCNT)
+#define WDTWRCSR (WDT.WRCSR)
+
+
+typedef struct st_wdt
+{
+                                                           /* WDT              */
+    volatile uint16_t WTCSR;                                  /*  WTCSR           */
+    volatile uint16_t WTCNT;                                  /*  WTCNT           */
+    volatile uint16_t WRCSR;                                  /*  WRCSR           */
+} r_io_wdt_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/reg32_t.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/reg32_t.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/reg32_t.h	(revision 374)
@@ -0,0 +1,11 @@
+#ifndef __REG32_T
+#define __REG32_T
+
+union reg32_t {
+    volatile uint32_t UINT32;
+    volatile uint16_t UINT16[2];
+    volatile uint8_t  UINT8[4];
+};
+
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c	(revision 374)
@@ -0,0 +1,828 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         mbed_sf_boot.c
+* $Rev: $
+* $Date::                           $
+* @brief        RZ_A1 serial flash boot loader
+******************************************************************************/
+#if defined  (__CC_ARM)
+#pragma arm section rodata = "BOOT_LOADER"
+const char boot_loader[]  __attribute__((used)) =
+
+#elif defined (__ICCARM__)
+__root const char boot_loader[] @ 0x18000000 =
+#else
+const char boot_loader[]  __attribute__ ((section(".boot_loader"), used)) =
+
+#endif
+{
+    0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+    0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+    0x00,0x30,0x00,0x18,0x74,0x30,0x00,0x18,0x78,0x30,0x00,0x18,0x7C,0x30,0x00,0x18,
+    0x80,0x30,0x00,0x18,0x84,0x30,0x00,0x18,0x88,0x30,0x00,0x18,0x8C,0x30,0x00,0x18,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,
+    0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,
+    0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,
+    0x10,0x80,0xBD,0xE8,0x97,0x28,0x00,0x00,0x00,0x04,0x00,0x18,0x00,0x02,0x02,0x20,
+    0x70,0x40,0x2D,0xE9,0x02,0x29,0xA0,0xE3,0xC8,0x40,0x9F,0xE5,0x0F,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x4C,0x00,0x00,0xEB,0x01,0x00,0x50,0xE3,0x06,0x00,0x00,0x1A,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0x33,0x00,0x00,0xEB,0x08,0x00,0x44,0xE2,0xB8,0x00,0xD0,0xE1,0x01,0x34,0xA0,0xE3,
+    0x94,0x50,0x9F,0xE5,0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+    0x32,0x00,0x00,0xEB,0x3C,0x40,0x85,0xE2,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x3C,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,
+    0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x36,0x00,0x00,0xEB,
+    0x01,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,0x00,0x00,0xA0,0xE3,0x4C,0x10,0x9F,0xE5,
+    0x04,0x00,0x81,0xE5,0x00,0x20,0xA0,0xE1,0x44,0x40,0x9F,0xE5,0x00,0x10,0xA0,0xE1,
+    0x03,0x30,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x1C,0x00,0x00,0xEB,0xFF,0x3C,0xA0,0xE3,
+    0x08,0x20,0xA0,0xE3,0x02,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x17,0x00,0x00,0xEB,
+    0x05,0x00,0xA0,0xE1,0x01,0x3C,0xA0,0xE3,0x70,0x40,0xBD,0xE8,0x08,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x11,0x00,0x00,0xEA,0x08,0x18,0xFF,0xFC,0x0C,0xA0,0xEF,0x3F,
+    0x00,0xA0,0xEF,0x3F,0x08,0xA0,0xEF,0x3F,0x10,0x40,0x2D,0xE9,0x00,0x40,0xD0,0xE5,
+    0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0x00,0x10,0xC0,0xE5,
+    0x10,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9,0xB0,0x40,0xD0,0xE1,0x11,0x12,0xA0,0xE1,
+    0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0xB0,0x10,0xC0,0xE1,0x10,0x80,0xBD,0xE8,
+    0x10,0x40,0x2D,0xE9,0x00,0x40,0x90,0xE5,0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,
+    0x02,0x10,0x81,0xE1,0x00,0x10,0x80,0xE5,0x10,0x80,0xBD,0xE8,0x00,0x00,0xD0,0xE5,
+    0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xB0,0x00,0xD0,0xE1,
+    0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x90,0xE5,
+    0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0x10,0xFF,0x2F,0xE1,0x10,0x40,0x2D,0xE9,0x00,0x00,0xA0,0xE3,0x7D,0x03,0x00,0xEB,
+    0x2C,0x10,0x9F,0xE5,0x00,0x00,0xA0,0xE3,0x7B,0x03,0x00,0xEB,0x20,0x20,0x9F,0xE5,
+    0x00,0x10,0xA0,0xE3,0x01,0x00,0xA0,0xE1,0x51,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3,
+    0x00,0x00,0x00,0x0A,0xFE,0xFF,0xFF,0xEA,0x10,0x40,0xBD,0xE8,0x04,0x00,0x9F,0xE5,
+    0xEE,0xFF,0xFF,0xEA,0x94,0x2A,0x02,0x20,0x00,0x40,0x00,0x18,0xF0,0x41,0x2D,0xE9,
+    0x00,0x40,0xA0,0xE1,0x03,0x70,0xA0,0xE1,0x02,0x50,0xA0,0xE1,0x18,0x60,0x9D,0xE5,
+    0x01,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE1,0xD9,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,
+    0xF0,0x81,0xBD,0x18,0x00,0x00,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0F,0x00,0x56,0xE3,
+    0x54,0x16,0x9F,0xE5,0x18,0x30,0x81,0xE2,0x00,0x00,0x81,0xE5,0x08,0x00,0x81,0xE5,
+    0x14,0x20,0x81,0xE5,0xD8,0x20,0xA0,0x13,0x41,0x00,0x83,0xE8,0xDC,0x20,0xA0,0x03,
+    0x20,0x00,0x81,0xE5,0x01,0x00,0x55,0xE3,0x24,0x00,0x81,0xE5,0x28,0x00,0x81,0xE5,
+    0x2C,0x00,0x81,0xE5,0x30,0x00,0x81,0xE5,0x46,0x20,0xC1,0xE5,0xA4,0x20,0xA0,0x01,
+    0x48,0x20,0x81,0x05,0x48,0x40,0x81,0x15,0x34,0x00,0x81,0xE5,0x38,0x00,0x81,0xE5,
+    0x3C,0x00,0x81,0xE5,0x40,0x00,0x81,0xE5,0x08,0x00,0xA0,0xE1,0xF8,0x15,0x9F,0xE5,
+    0x91,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x07,0x20,0xA0,0xE1,
+    0x05,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x9E,0x01,0x00,0xEA,
+    0xFF,0x5F,0x2D,0xE9,0x00,0xB0,0xA0,0xE1,0x02,0x70,0xA0,0xE1,0x01,0x60,0xA0,0xE1,
+    0x0C,0x00,0x9D,0xE5,0x40,0x80,0x9D,0xE5,0x3C,0x90,0x9D,0xE5,0x38,0xA0,0x9D,0xE5,
+    0xAB,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,0x7A,0x00,0x00,0x1A,0x00,0x50,0xA0,0xE3,
+    0xA4,0x45,0x9F,0xE5,0x01,0x00,0xA0,0xE3,0x00,0x00,0x59,0xE3,0x14,0x10,0x84,0xE2,
+    0x00,0x50,0x84,0xE5,0x08,0x50,0x84,0xE5,0x21,0x01,0x81,0xE8,0x28,0x10,0x84,0xE2,
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+    0x08,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,
+    0xA1,0xFF,0xFF,0xEA,0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x50,0x43,0x9F,0xE5,
+    0x03,0x60,0xB0,0xE1,0x00,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x70,0xA0,0xE1,
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+    0x08,0x00,0xDD,0xE5,0x07,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x01,0x10,0xC0,0xE3,
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+    0x01,0x00,0x55,0xE3,0x04,0x00,0xDD,0xE5,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
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+    0x14,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+    0x03,0x50,0xA0,0xE1,0x02,0x60,0xA0,0xE1,0x01,0x70,0xA0,0xE1,0x01,0x00,0xA0,0xE1,
+    0x57,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x10,0xA0,0xE3,
+    0x01,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,0xC4,0x01,0x9F,0xE5,0x1C,0x80,0x80,0xE2,
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+    0xF0,0x40,0x2D,0xE9,0x03,0x40,0xA0,0xE1,0x1C,0xD0,0x4D,0xE2,0x02,0x50,0xA0,0xE1,
+    0x01,0x60,0xA0,0xE1,0x00,0x70,0xA0,0xE1,0x00,0x20,0xA0,0xE1,0x00,0x30,0x8D,0xE5,
+    0x01,0x30,0xA0,0xE1,0x0C,0x10,0x8D,0xE2,0x08,0x00,0x8D,0xE2,0xEB,0xFE,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x1F,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
+    0x10,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x68,0xFF,0xFF,0xEB,
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+    0x18,0x10,0x8D,0xE2,0x14,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x13,0x00,0x00,0xEB,
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+    0x00,0x40,0x8D,0xE5,0x19,0xFF,0xFF,0xEB,0x1C,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8,
+    0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x84,0x40,0x9F,0xE5,0x03,0x80,0xA0,0xE1,
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+    0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,0x21,0x00,0x83,0xE8,
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+    0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+    0xA7,0xFE,0xFF,0xEB,0x50,0x10,0xD4,0xE5,0x00,0x00,0x58,0xE3,0x00,0x10,0xC7,0xE5,
+    0xB0,0x15,0xD4,0x11,0x00,0x50,0xC6,0x05,0x21,0x14,0xA0,0x11,0x00,0x10,0xC6,0x15,
+    0xF0,0x81,0xBD,0xE8,0xA4,0x2A,0x02,0x20,0x89,0x05,0x00,0xEA,0x9D,0x05,0x00,0xEA,
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+    0x0C,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x2E,0x04,0x00,0xEB,0x00,0x00,0x50,0xE3,
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+    0x04,0x30,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0x00,0x50,0x8D,0xE5,
+    0x32,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,
+    0x02,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,
+    0x00,0x00,0x51,0xE3,0x00,0x10,0xA0,0x03,0x01,0x10,0xA0,0x13,0x0B,0x20,0xD4,0xE5,
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+    0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0x9D,0x04,0x00,0xEA,0x01,0x20,0xD1,0xE5,
+    0x02,0x00,0x52,0xE3,0x0E,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x12,0x00,0x00,0x8A,
+    0x06,0x00,0xD1,0xE5,0x0F,0x00,0x50,0xE3,0x07,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,
+    0x0D,0x00,0x00,0x8A,0x08,0x00,0xD1,0xE5,0x07,0x00,0x50,0xE3,0x09,0x00,0xD1,0x95,
+    0x01,0x00,0x50,0x93,0x08,0x00,0x00,0x8A,0x0A,0x00,0xD1,0xE5,0x02,0x00,0x50,0xE3,
+    0x0B,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x03,0x00,0x00,0x8A,0x0D,0x00,0xD1,0xE5,
+    0x03,0x00,0x50,0xE3,0x00,0x00,0xA0,0x93,0x1E,0xFF,0x2F,0x91,0x00,0x00,0xE0,0xE3,
+    0x1E,0xFF,0x2F,0xE1,0xF8,0x40,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0x02,0x40,0xA0,0xE1,
+    0x00,0x60,0xA0,0xE1,0x02,0x10,0xA0,0xE1,0xDF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+    0x1B,0x00,0x00,0x1A,0x05,0x10,0xA0,0xE1,0x0B,0x00,0xD4,0xE5,0x00,0x00,0x8D,0xE5,
+    0x06,0x00,0xA0,0xE1,0x0D,0x30,0xD4,0xE5,0x0C,0x20,0xD4,0xE5,0xE5,0x03,0x00,0xEB,
+    0x00,0x00,0x50,0xE3,0x12,0x00,0x00,0x1A,0x0B,0x30,0xD4,0xE5,0x00,0x00,0x53,0xE3,
+    0x02,0x20,0xA0,0x03,0x03,0x00,0x00,0x0A,0x02,0x00,0x53,0xE3,0x03,0x20,0xA0,0x03,
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+    0x00,0x00,0x8D,0xE5,0x06,0x00,0xA0,0xE1,0xE8,0xFE,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+    0x03,0x00,0x00,0x1A,0x04,0x20,0xA0,0xE1,0x05,0x10,0xA0,0xE1,0x06,0x00,0xA0,0xE1,
+    0xB0,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x52,0x04,0x00,0xEA,0x70,0x40,0x2D,0xE9,
+    0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x7F,0x06,0x00,0xEB,0x04,0x10,0xA0,0xE1,
+    0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0xB7,0xFF,0xFF,0xEA,0xF7,0x4F,0x2D,0xE9,
+    0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x92,0x03,0x00,0x8A,
+    0x00,0x00,0x50,0xE3,0xE5,0x00,0x00,0x0A,0x01,0x3A,0xA0,0xE3,0x3C,0x5E,0x9F,0xE5,
+    0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x38,0xFC,0xFF,0xEB,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x62,0x85,0xE1,
+    0x06,0x00,0xA0,0xE1,0x32,0xFC,0xFF,0xEB,0x3D,0x7C,0x45,0xE2,0x01,0x3A,0xA0,0xE3,
+    0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFC,0xFF,0xEB,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x82,0x87,0xE0,
+    0x08,0x00,0xA0,0xE1,0x26,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x02,0x93,0x26,0xE0,0x09,0x00,0xA0,0xE1,0x20,0xFC,0xFF,0xEB,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0x1B,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x82,0xA3,0x27,0xE0,0x0A,0x00,0xA0,0xE1,0x15,0xFC,0xFF,0xEB,0x01,0x10,0xA0,0xE3,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xB4,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,
+    0x0F,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x82,0x03,0x88,0xE0,0x0A,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x05,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,
+    0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x00,0xFC,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+    0xFB,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x06,0x00,0xA0,0xE1,0xF6,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF1,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xEC,0xFB,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0xE7,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x06,0x00,0xA0,0xE1,0xE2,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xDD,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xD8,0xFB,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0xC3,0x01,0x8B,0xE0,
+    0xD3,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0xCE,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xC9,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xC4,0xFB,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xBF,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xBA,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xB5,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB0,0xFB,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xAB,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0A,0x00,0xA0,0xE1,0xA6,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xA1,0xFB,0xFF,0xEB,0x0E,0x20,0xA0,0xE3,
+    0x01,0x39,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x03,0x87,0xE0,0x9C,0xFB,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x97,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x92,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x8D,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+    0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x88,0xFB,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+    0x83,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x7E,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x79,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+    0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x74,0xFB,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+    0x6F,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x0B,0x00,0xA0,0xE1,0x6A,0xFB,0xFF,0xEB,0x0F,0x20,0xA0,0xE3,0x02,0x39,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x02,0x04,0x2A,0xE0,0x65,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+    0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x60,0xFB,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x5B,0xFB,0xFF,0xEB,0x02,0x00,0x54,0xE3,0x3B,0x02,0x00,0x0A,0xA9,0x02,0x00,0xEA,
+    0xAC,0x5A,0x9F,0xE5,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x52,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0x63,0x85,0xE1,0x06,0x00,0xA0,0xE1,0x4C,0xFB,0xFF,0xEB,
+    0x3D,0x7C,0x45,0xE2,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0x46,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0x83,0x87,0xE0,0x08,0x00,0xA0,0xE1,0x40,0xFB,0xFF,0xEB,
+    0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x93,0x86,0xE0,
+    0x09,0x00,0xA0,0xE1,0x3A,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x35,0xFB,0xFF,0xEB,0x01,0x10,0xA0,0xE3,
+    0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0xA4,0x88,0xE1,0x0A,0x00,0xA0,0xE1,
+    0x2F,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x82,0xB3,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,0x29,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,
+    0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x04,0x8B,0xE0,0x24,0xFB,0xFF,0xEB,
+    0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x1F,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x1A,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x15,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x10,0xFB,0xFF,0xEB,
+    0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+    0x0B,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x06,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x01,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+    0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xFC,0xFA,0xFF,0xEB,
+    0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+    0xF7,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0B,0x00,0xA0,0xE1,0xF2,0xFA,0xFF,0xEB,0x03,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0x04,0x88,0xE0,0xED,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+    0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xE8,0xFA,0xFF,0xEB,
+    0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0xE3,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0xDE,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xD9,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+    0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xD4,0xFA,0xFF,0xEB,
+    0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0xCF,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0xCA,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xC5,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+    0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xC0,0xFA,0xFF,0xEB,
+    0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0xBB,0xFA,0xFF,0xEB,0x04,0x20,0xA0,0xE3,0x10,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x02,0x04,0x8B,0xE0,0xB6,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB1,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+    0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xAC,0xFA,0xFF,0xEB,
+    0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+    0xA7,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x06,0x00,0xA0,0xE1,0xA2,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x9D,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+    0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x98,0xFA,0xFF,0xEB,
+    0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x93,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x06,0x00,0xA0,0xE1,0x8E,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x89,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+    0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x84,0xFA,0xFF,0xEB,
+    0x05,0x20,0xA0,0xE3,0x20,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x04,0x8A,0xE0,
+    0x7F,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0x7A,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x75,0xFA,0xFF,0xEB,0x02,0x00,0x54,0xE3,
+    0xC4,0x01,0x00,0x1A,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x6E,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x69,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+    0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x64,0xFA,0xFF,0xEB,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x5F,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0x5A,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x55,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+    0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x50,0xFA,0xFF,0xEB,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0x4B,0xFA,0xFF,0xEB,0x06,0x20,0xA0,0xE3,0x40,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x02,0x44,0x88,0xE0,0x04,0x00,0xA0,0xE1,0x45,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+    0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x40,0xFA,0xFF,0xEB,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x3B,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x36,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x31,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+    0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFA,0xFF,0xEB,
+    0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x27,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0x22,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x1D,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+    0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x18,0xFA,0xFF,0xEB,
+    0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0x13,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x0E,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x09,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+    0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x04,0xFA,0xFF,0xEB,
+    0x08,0x00,0x9D,0xE5,0x01,0x00,0x50,0xE3,0x52,0x01,0x00,0x1A,0x1C,0x40,0x45,0xE2,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0xFB,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x43,0x52,0x84,0xE1,0x05,0x00,0xA0,0xE1,0xF5,0xF9,0xFF,0xEB,0x3D,0x6C,0x44,0xE2,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xEF,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x43,0x72,0x86,0xE0,0x07,0x00,0xA0,0xE1,0xE9,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,
+    0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x83,0x25,0xE0,0x08,0x00,0xA0,0xE1,
+    0xE3,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0xDE,0xF9,0xFF,0xEB,0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+    0x0C,0x20,0xA0,0xE3,0x01,0x94,0x87,0xE1,0x09,0x00,0xA0,0xE1,0xD8,0xF9,0xFF,0xEB,
+    0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xA4,0x89,0xE0,
+    0x0A,0x00,0xA0,0xE1,0xD2,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0xB3,0x87,0xE0,0x0B,0x00,0xA0,0xE1,0xCC,0xF9,0xFF,0xEB,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0xC7,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xC2,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xBD,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xB8,0xF9,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xB3,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xAE,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xA9,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xA4,0xF9,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x9F,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x0A,0x00,0xA0,0xE1,0x9A,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x95,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x90,0xF9,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+    0x8B,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x86,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x81,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x7C,0xF9,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+    0x77,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x72,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x6D,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x68,0xF9,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+    0x63,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0B,0x00,0xA0,0xE1,0x5E,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x59,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x54,0xF9,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0x4F,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x4A,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x45,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+    0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x40,0xF9,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x3B,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x36,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x31,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+    0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x2C,0xF9,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0x27,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x22,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6D,0x00,0x00,0xEA,0x01,0x3B,0xA0,0xE3,
+    0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x18,0xF9,0xFF,0xEB,
+    0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0x13,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0x0E,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x09,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,
+    0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x04,0xF9,0xFF,0xEB,
+    0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xFF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0A,0x00,0xA0,0xE1,0xFA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xF5,0xF8,0xFF,0xEB,0x24,0x41,0x9F,0xE5,
+    0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0xEF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0xEA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xE5,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+    0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xE0,0xF8,0xFF,0xEB,
+    0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xDB,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xD6,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xD1,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+    0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xCC,0xF8,0xFF,0xEB,
+    0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xC7,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0A,0x00,0xA0,0xE1,0xC2,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xBD,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+    0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xB8,0xF8,0xFF,0xEB,
+    0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0xB3,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0xAE,0xF8,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0xFE,0x8F,0xBD,0xE8,
+    0x20,0x70,0xFE,0xFC,0x24,0x70,0xFE,0xFC,0x20,0x3A,0xFE,0xFC,0xF0,0x41,0x2D,0xE9,
+    0x01,0x00,0x50,0xE3,0x02,0x70,0xA0,0xE1,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1,
+    0x15,0x00,0x00,0x8A,0x54,0x6B,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x04,0x01,0x96,0xE7,0x48,0x00,0x80,0xE2,0xB3,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,
+    0x0D,0x00,0x00,0x1A,0x04,0x01,0x96,0xE7,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0xAD,0xF8,0xFF,0xEB,0x05,0x00,0x50,0xE1,0x14,0x00,0x00,0x0A,0x01,0x00,0x55,0xE3,
+    0x07,0x00,0x00,0x1A,0x05,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,
+    0x49,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0xAA,0x00,0x00,0xE0,0xE3,
+    0xF0,0x81,0xBD,0xE8,0x04,0x01,0x96,0xE7,0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+    0x05,0x10,0xA0,0xE1,0x8D,0xF8,0xFF,0xEB,0x04,0x01,0x96,0xE7,0x02,0x3C,0xA0,0xE3,
+    0x09,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0x87,0xF8,0xFF,0xEB,
+    0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,0xF0,0x47,0x2D,0xE9,0x01,0x00,0x50,0xE3,
+    0x03,0x70,0xA0,0xE1,0x02,0x80,0xA0,0xE1,0x20,0x60,0x9D,0xE5,0x01,0x90,0xA0,0xE1,
+    0x00,0x40,0xA0,0xE1,0x71,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,
+    0x2D,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x6C,0x00,0x00,0xBA,0x01,0x20,0xA0,0xE3,
+    0x88,0x5A,0x9F,0xE5,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,
+    0x81,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x64,0x00,0x00,0x1A,0x04,0x01,0x95,0xE7,
+    0x03,0x35,0xA0,0xE3,0x16,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x6B,0xF8,0xFF,0xEB,
+    0x04,0x01,0x95,0xE7,0x03,0x36,0xA0,0xE3,0x14,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+    0x66,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x37,0xA0,0xE3,0x12,0x20,0xA0,0xE3,
+    0x03,0x10,0xA0,0xE3,0x61,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x38,0xA0,0xE3,
+    0x10,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x5C,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x03,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x57,0xF8,0xFF,0xEB,
+    0x04,0x01,0x95,0xE7,0x03,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+    0x52,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x03,0x10,0xA0,0xE3,0x4D,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x34,0xA0,0xE3,
+    0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0xF8,0xFF,0xEB,
+    0x04,0x01,0x95,0xE7,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x3E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x39,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x08,0x30,0xA0,0xE3,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x34,0xF8,0xFF,0xEB,0x06,0x20,0xA0,0xE1,
+    0x09,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,0x7F,0xFF,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x07,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,
+    0x2A,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x07,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,0x24,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x00,0x20,0xA0,0xE3,0x07,0x30,0xA0,0xE3,0x02,0x10,0xA0,0xE1,0x04,0x00,0x80,0xE2,
+    0x1E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0xFF,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x08,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,0x18,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x07,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,
+    0x12,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x48,0x00,0x80,0xE2,0x1C,0xF8,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,
+    0x00,0x00,0xE0,0xE3,0xF0,0x87,0xBD,0xE8,0x04,0x11,0x95,0xE7,0x08,0x05,0x0A,0xE3,
+    0x50,0x00,0x81,0xE5,0x04,0x11,0x95,0xE7,0xC4,0x08,0x9F,0xE5,0x68,0x00,0x81,0xE5,
+    0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+    0xA8,0x58,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x48,0x00,0x80,0xE2,0x08,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+    0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x01,0x60,0xA0,0xE1,
+    0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE3,0x6C,0x58,0x9F,0xE5,
+    0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,0xFA,0xF7,0xFF,0xEB,
+    0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0x70,0x80,0xBD,0xE8,
+    0x04,0x01,0x95,0xE7,0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0xE2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x0F,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0xDC,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,
+    0xD6,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+    0x03,0x10,0xA0,0xE1,0x0C,0x00,0x80,0xE2,0xD0,0xF7,0xFF,0xEB,0x00,0x10,0xD6,0xE5,
+    0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x00,0x80,0xE2,
+    0xCA,0xF7,0xFF,0xEB,0x01,0x10,0xD6,0xE5,0x03,0x31,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x1E,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xC4,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0xBE,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0xFF,0x30,0xA0,0xE3,
+    0x02,0x10,0xA0,0xE1,0x10,0x00,0x80,0xE2,0xB8,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x03,0x32,0xA0,0xE3,0x1C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0xB2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xAC,0xF7,0xFF,0xEB,0x0E,0x10,0xD6,0xE5,
+    0x03,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x18,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0xA6,0xF7,0xFF,0xEB,0x0F,0x10,0xD6,0xE5,0x0F,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x08,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xA0,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0xFF,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x14,0x00,0x80,0xE2,
+    0x9A,0xF7,0xFF,0xEB,0x02,0x10,0xD6,0xE5,0xFF,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x18,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x94,0xF7,0xFF,0xEB,0x03,0x10,0xD6,0xE5,
+    0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+    0x8E,0xF7,0xFF,0xEB,0x04,0x10,0xD6,0xE5,0xFF,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x08,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x88,0xF7,0xFF,0xEB,0x05,0x10,0xD6,0xE5,
+    0xFF,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+    0x82,0xF7,0xFF,0xEB,0x07,0x10,0xD6,0xE5,0x03,0x36,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x14,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x7C,0xF7,0xFF,0xEB,0x06,0x10,0xD6,0xE5,
+    0xF0,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x04,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0x76,0xF7,0xFF,0xEB,0x0B,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x10,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x70,0xF7,0xFF,0xEB,0x09,0x10,0xD6,0xE5,
+    0x02,0x39,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x0F,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0x6A,0xF7,0xFF,0xEB,0x0A,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x10,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,0x64,0xF7,0xFF,0xEB,0x08,0x10,0xD6,0xE5,
+    0x07,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,
+    0x5E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,0x58,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,
+    0x52,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3,
+    0x02,0x10,0xA0,0xE1,0x5C,0x00,0x80,0xE2,0x4C,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,
+    0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x00,0x40,0xA0,0xE1,
+    0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,0x01,0x34,0xA0,0xE3,0x18,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0xB4,0x55,0x9F,0xE5,0x04,0x01,0x95,0xE7,0x0C,0x00,0x80,0xE2,
+    0x3E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x48,0x00,0x80,0xE2,0x48,0xF7,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+    0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,0x7C,0x55,0x9F,0xE5,
+    0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x3E,0xF7,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,0xE0,0xFF,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,0x02,0x31,0xA0,0xE3,
+    0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x23,0xF7,0xFF,0xEB,
+    0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+    0x28,0x55,0x9F,0xE5,0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x29,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,
+    0xCB,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,
+    0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x0E,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,
+    0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x19,0x00,0x00,0x8A,
+    0x02,0x21,0xA0,0xE3,0xC4,0x64,0x9F,0xE5,0x1F,0x10,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+    0x11,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+    0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0x0A,0xF7,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A,0x05,0x01,0x96,0xE7,0x02,0x31,0xA0,0xE3,
+    0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0xF4,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0xFE,0xF6,0xFF,0xEB,
+    0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0xF0,0x81,0xBD,0xE8,
+    0x05,0x01,0x96,0xE7,0x01,0x39,0xA0,0xE3,0x14,0x10,0x94,0xE5,0x0E,0x20,0xA0,0xE3,
+    0x30,0x00,0x80,0xE2,0xE5,0xF6,0xFF,0xEB,0x14,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,
+    0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x46,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+    0x24,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,0xDC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0x03,0x31,0xA0,0xE3,0x00,0x10,0x94,0xE5,0x1E,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+    0xD6,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3A,0xA0,0xE3,0x18,0x10,0x94,0xE5,
+    0x0C,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xD0,0xF6,0xFF,0xEB,0x18,0x00,0x94,0xE5,
+    0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x47,0x10,0xD4,0xE5,
+    0xFF,0x30,0xA0,0xE3,0x24,0x00,0x80,0xE2,0x00,0x20,0xA0,0xE3,0xC7,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x03,0x32,0xA0,0xE3,0x04,0x10,0x94,0xE5,0x1C,0x20,0xA0,0xE3,
+    0x30,0x00,0x80,0xE2,0xC1,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x0F,0x3C,0xA0,0xE3,
+    0x1C,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xBB,0xF6,0xFF,0xEB,
+    0x1C,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+    0x48,0x10,0x94,0xE5,0x00,0x30,0xE0,0xE3,0x00,0x20,0xA0,0xE3,0x28,0x00,0x80,0xE2,
+    0xB2,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x03,0x34,0xA0,0xE3,0x08,0x10,0x94,0xE5,
+    0x18,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xAC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0xF0,0x30,0xA0,0xE3,0x20,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+    0xA6,0xF6,0xFF,0xEB,0x20,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x1D,0x00,0x00,0x0A,
+    0x05,0x01,0x96,0xE7,0x4C,0x10,0xD4,0xE5,0xFF,0x34,0xA0,0xE3,0x2C,0x00,0x80,0xE2,
+    0x18,0x20,0xA0,0xE3,0x9D,0xF6,0xFF,0xEB,0x4D,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+    0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x97,0xF6,0xFF,0xEB,
+    0x4E,0x10,0xD4,0xE5,0xFF,0x3C,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x08,0x20,0xA0,0xE3,
+    0x2C,0x00,0x80,0xE2,0x91,0xF6,0xFF,0xEB,0x4F,0x10,0xD4,0xE5,0xFF,0x30,0xA0,0xE3,
+    0x05,0x01,0x96,0xE7,0x00,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x8B,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x03,0x36,0xA0,0xE3,0x0C,0x10,0x94,0xE5,0x14,0x20,0xA0,0xE3,
+    0x30,0x00,0x80,0xE2,0x85,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x02,0x39,0xA0,0xE3,
+    0x34,0x10,0x94,0xE5,0x0F,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0x7F,0xF6,0xFF,0xEB,
+    0x34,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+    0x44,0x10,0xD4,0xE5,0x03,0x38,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,
+    0x76,0xF6,0xFF,0xEB,0x45,0x10,0xD4,0xE5,0x07,0x30,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+    0x00,0x20,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x70,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0x0F,0x30,0xA0,0xE3,0x24,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+    0x6A,0xF6,0xFF,0xEB,0x24,0x00,0x94,0xE5,0x58,0x72,0x9F,0xE5,0x00,0x00,0x50,0xE3,
+    0x2C,0x00,0x00,0x0A,0x08,0x00,0x50,0xE3,0x04,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+    0x0C,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x14,0x00,0x00,0x0A,0x1F,0x00,0x00,0xEA,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6A,0xF6,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x58,0x00,0xD4,0x05,0x05,0x11,0x96,0x07,0x40,0x00,0xC1,0x05,
+    0x06,0x00,0x00,0x1A,0x15,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0x60,0xF6,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x53,0x00,0x00,0x1A,
+    0x05,0x11,0x96,0xE7,0xB8,0x05,0xD4,0xE1,0xB0,0x04,0xC1,0xE1,0x0B,0x00,0x00,0xEA,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x56,0xF6,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x49,0x00,0x00,0x0A,0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,
+    0x40,0x00,0x81,0xE5,0x05,0x01,0x96,0xE7,0x5C,0x10,0x94,0xE5,0x44,0x10,0x80,0xE5,
+    0x03,0x38,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x10,0x94,0xE5,
+    0x30,0x00,0x80,0xE2,0x39,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+    0x28,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x33,0xF6,0xFF,0xEB,
+    0x10,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x24,0x00,0x94,0x15,0x00,0x00,0x50,0x13,
+    0x04,0x00,0x00,0x0A,0x2C,0x00,0x94,0xE5,0x01,0x00,0x50,0xE3,0x30,0x00,0x94,0x05,
+    0x01,0x00,0x50,0x03,0x3B,0xFF,0xFF,0x0A,0x05,0x01,0x96,0xE7,0x2C,0x10,0x94,0xE5,
+    0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x23,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x02,0x30,0xA0,0xE3,0x30,0x10,0x94,0xE5,0x01,0x20,0xA0,0xE3,
+    0x20,0x00,0x80,0xE2,0x1D,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+    0x38,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x17,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x10,0x30,0xA0,0xE3,0x3C,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,
+    0x64,0x00,0x80,0xE2,0x11,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,
+    0x40,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x0B,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE1,
+    0x20,0x00,0x80,0xE2,0x05,0xF6,0xFF,0xEB,0x05,0x00,0xA0,0xE1,0xAD,0xF9,0xFF,0xEB,
+    0x24,0x00,0x94,0xE5,0x08,0x00,0x50,0xE3,0x08,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+    0x11,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x16,0x00,0x00,0x0A,0x21,0x00,0x00,0xEA,
+    0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,0x40,0x00,0x81,0xE5,0xB7,0xFF,0xFF,0xEA,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x02,0xF6,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x05,0x01,0x96,0x07,0x38,0x00,0xD0,0x05,0x19,0x00,0x00,0x0A,
+    0x05,0x01,0x96,0xE7,0xB8,0x03,0xD0,0xE1,0x16,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF7,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+    0x0E,0x00,0x00,0x1A,0xF5,0xFF,0xFF,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xF0,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x07,0x00,0x00,0x0A,
+    0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0x05,0x01,0x96,0xE7,
+    0x3C,0x00,0x90,0xE5,0x54,0x00,0x84,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,
+    0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0xF9,0xFF,0xFF,0xEA,
+    0x8C,0x2A,0x02,0x20,0x63,0x63,0x00,0xA5,0x00,0xA0,0xEF,0x3F,0xF0,0x40,0x2D,0xE9,
+    0xEB,0xC0,0xA0,0xE3,0x00,0xC0,0xC1,0xE5,0x08,0x70,0xA0,0xE3,0x06,0x70,0xC1,0xE5,
+    0x03,0x60,0xA0,0xE3,0x08,0x60,0xC1,0xE5,0x55,0x50,0xA0,0xE3,0x02,0x50,0xC1,0xE5,
+    0x01,0x40,0xA0,0xE3,0x09,0x40,0xC1,0xE5,0x02,0x30,0xA0,0xE3,0x0E,0x30,0xC1,0xE5,
+    0x00,0x20,0xA0,0xE3,0x07,0x30,0xC1,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x30,0xC1,0xE5,
+    0x07,0x00,0xA0,0xE3,0x01,0x20,0xC1,0xE5,0x03,0x20,0xC1,0xE5,0x04,0x20,0xC1,0xE5,
+    0x05,0x20,0xC1,0xE5,0x0A,0x20,0xC1,0xE5,0x0C,0x40,0xC1,0x05,0x0C,0x30,0xC1,0x15,
+    0x0D,0x20,0xC1,0xE5,0x0F,0x00,0xC1,0xE5,0xF0,0x80,0xBD,0xE8,0x00,0xA0,0xEF,0x3F,
+    0x00,0xB0,0xEF,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0x5C,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0x00,0x10,0x80,0xE5,0x00,0x00,0x90,0xE5,
+    0x50,0x00,0x9F,0xE5,0x35,0x10,0x01,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+    0x44,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+    0x10,0x0F,0x11,0xEE,0x02,0x0A,0xC0,0xE3,0x01,0x0A,0xC0,0xE3,0x04,0x00,0xC0,0xE3,
+    0x01,0x00,0xC0,0xE3,0x10,0x0F,0x01,0xEE,0x26,0x00,0x00,0xEB,0x1C,0xD0,0x9F,0xE5,
+    0x14,0x00,0x00,0xEB,0x0D,0x00,0x00,0xEB,0x0E,0x00,0x00,0xEB,0x0F,0x00,0x00,0xEB,
+    0xFE,0xFF,0xFF,0xEA,0x80,0xFF,0xFF,0x3F,0x10,0x00,0xFE,0xFC,0x14,0x00,0xFE,0xFC,
+    0x00,0x00,0x03,0x20,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+    0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+    0x04,0xF0,0x1F,0xE5,0x40,0x00,0x02,0x20,0x04,0xF0,0x1F,0xE5,0x00,0x00,0x02,0x20,
+    0x04,0xF0,0x1F,0xE5,0x04,0x02,0x02,0x20,0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,
+    0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,
+    0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,
+    0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,0x10,0x80,0xBD,0xE8,0xAF,0x01,0x00,0x00,
+    0x00,0x02,0x00,0x18,0x00,0x00,0x02,0x20,0x04,0x00,0x9F,0xE5,0x10,0x0F,0x0C,0xEE,
+    0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x00,0x18,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+};
+#if defined  (__CC_ARM)
+#pragma arm section
+#endif
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c	(revision 374)
@@ -0,0 +1,281 @@
+/**************************************************************************//**
+ * @file     mmu_RZ_A1H.c
+ * @brief    MMU Configuration for RZ_A1H Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |        Peripherals       |                Device
+0xfcf00000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0xe8300000 |--------------------------|             ------------
+           |        Peripherals       |                Device
+0xe8000000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0x60A00000 |--------------------------|             ------------
+           | On Chip RAM (10M) Mirror |                Fault
+0x60000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                Fault
+0x5c000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                Fault
+0x58000000 |--------------------------|             ------------
+           |        CS5 Mirror        |                Fault
+0x54000000 |--------------------------|             ------------
+           |        CS4 Mirror        |                Fault
+0x50000000 |--------------------------|             ------------
+           |        CS3 Mirror        |                Fault
+0x4c000000 |--------------------------|             ------------
+           |        CS2 Mirror        |                Fault
+0x48000000 |--------------------------|             ------------
+           |        CS1 Mirror        |                Fault
+0x44000000 |--------------------------|             ------------
+           |        CS0 Mirror        |                Fault
+0x40000000 |--------------------------|             ------------
+           |          BSC             |                 RW
+0x3ff00000 |--------------------------|             ------------
+           |      SPI_MIO_BASE        |                 RW
+0x3fe00000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0x20A00000 |--------------------------|             ------------
+           |    On Chip RAM (10M)     |                 RW
+0x20000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                 RO
+0x1c000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                 RO
+0x18000000 |--------------------------|             ------------
+           |  CS5 User Area 64MB      |                 RW
+0x14000000 |--------------------------|             ------------
+           |  CS4 User Area 64MB      |                 RW
+0x10000000 |--------------------------|             ------------
+           |      CS3 SDRAM 64MB      |                 RW
+0x0c000000 |--------------------------|             ------------
+           |      CS2 SDRAM 64MB      |                 RW
+0x08000000 |--------------------------|             ------------
+           |  CS1 NOR Flash 64MB      |                 RO
+0x04000000 |--------------------------|             ------------
+           |  CS0 NOR Flash 64MB      |                 RO
+0x00000000 |--------------------------|             ------------
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+//There are no restrictions by privilege level (PL0 can access all memory)
+
+
+#include "RZ_A1H.h"
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RO_DATA$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$RW_IRAM1$$Base;
+#if !defined ( __ICCARM__ )
+extern uint32_t Image$$TTB$$ZI$$Base;
+#endif 
+
+#if defined( __CC_ARM )
+#elif defined( __ICCARM__ )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Base;
+extern uint32_t Image$$ZI_DATA_NC$$Base;
+#endif
+
+extern uint32_t Image$$VECTORS$$Limit;
+extern uint32_t Image$$RO_DATA$$Limit;
+extern uint32_t Image$$RW_DATA$$Limit;
+extern uint32_t Image$$RW_IRAM1$$Limit;
+#if defined( __CC_ARM )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Limit;
+extern uint32_t Image$$ZI_DATA_NC$$Limit;
+#endif
+
+#if defined( __ICCARM__ )
+#define VECTORS_SIZE    (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
+#define RW_IRAM1_SIZE   (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
+#else
+#define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
+#define RW_IRAM1_SIZE   (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
+#endif
+
+#if defined( __CC_ARM )
+#else
+#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
+#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
+#endif
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_NC;  //non-shareable, non-executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+#if defined ( __ICCARM__ )
+__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
+uint32_t Image$$VECTORS$$Base;
+uint32_t Image$$RO_DATA$$Base;
+uint32_t Image$$RW_DATA$$Base;
+uint32_t Image$$RW_IRAM1$$Base;
+
+uint32_t Image$$VECTORS$$Limit;
+uint32_t Image$$RO_DATA$$Limit;
+uint32_t Image$$RW_DATA$$Limit;
+uint32_t Image$$RW_IRAM1$$Limit;
+#endif
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+#if defined ( __ICCARM__ )
+#pragma section=".intvec"
+#pragma section=".rodata"
+#pragma section=".rwdata"
+#pragma section=".bss"
+
+    Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
+    Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
+    Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
+    Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
+    Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); 
+    Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
+    Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");  
+    Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
+#endif
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    section_normal_nc(Sect_Normal_NC, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    // R7S72100 memory map.
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
+
+#if defined( __ICCARM__ )
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
+#else
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
+#endif
+
+#if defined( __CC_ARM )
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
+#elif defined ( __ICCARM__ ) 
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
+
+#else
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
+#endif
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c	(revision 374)
@@ -0,0 +1,162 @@
+/******************************************************************************
+ * @file     system_RZ_A1H_H.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <RZ_A1H.h>
+#include "RZ_A1_Init.h"
+#include "irq_ctrl.h"
+
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
+
+/*
+ Port 0 (P0) MD pin assignment
+ P0_0: MD_BOOT0
+ P0_1: MD_BOOT1
+ P0_2: MD_CLK
+ P0_3: MD_CLKS
+ */
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  uint32_t freq;
+  uint16_t mode;
+  uint16_t ifc;
+
+  mode = (GPIO.PPR0 >> 2U) & 0x01U;
+
+  if (mode == 0) {
+    /* Clock Mode 0 */
+    /* CLKIN is between 10MHz and 13.33MHz */
+    /* Divider 1 uses 1/1 ratio, PLL x30 is ON */
+    freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
+  } else {
+    /* Clock Mode 1 */
+    /* CLKIN is 48MHz */
+    /* Divider 1 uses 1/4 ratio, PLL x32 is ON */
+    freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
+  }
+
+  /* Get CPG.FRQCR[IFC] bits */
+  ifc = (CPG.FRQCR >> 8U) & 0x03U;
+
+  /* Determine Divider 2 output clock */
+  if (ifc == 0x03U) {
+    /* Division ratio is 1/3 */
+    freq = (freq / 3U);
+  }
+  else {
+    if (ifc == 0x01U) {
+      /* Division ratio is 2/3 */
+      freq = (freq * 2U) / 3U;
+    }
+  }
+
+  SystemCoreClock = freq;
+}
+
+/*----------------------------------------------------------------------------
+  IRQ Handler Register/Unregister
+ *----------------------------------------------------------------------------*/
+uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
+{
+    return IRQ_SetHandler(irq, handler);
+}
+
+uint32_t InterruptHandlerUnregister (IRQn_Type irq)
+{
+    return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/*       do not use global variables because this function is called before
+         reaching pre-main. RW section may be overwritten afterwards.          */
+  
+  // Enable SRAM write access
+  CPG.SYSCR3 = 0x0F;
+
+  RZ_A1_InitClock();
+  RZ_A1_InitBus();
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  L2C_InvAllByWay();
+  // Enable L2C
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}
+
+void mbed_sdk_init(void) {
+    L1C_CleanDCacheAll();
+    L1C_InvalidateICacheAll();
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h	(revision 374)
@@ -0,0 +1,81 @@
+/******************************************************************************
+ * @file     system_RZ_A1H.h
+ * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_RZ_A1H_H
+#define __SYSTEM_RZ_A1H_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+typedef void(*IRQHandler)();         /*!< Type Definition for Interrupt Handlers */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Interrupt Handler Register.
+
+   Registers an Interrupt Handler into the IRQ Table.
+ */
+extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+
+/**
+  \brief  Interrupt Handler Unregister.
+
+   Unregisters an Interrupt Handler from the IRQ Table.
+ */
+extern uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_RZ_A1H_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/mbed_drv_cfg.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/mbed_drv_cfg.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/mbed_drv_cfg.h	(revision 374)
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_DRV_CFG_H
+#define MBED_DRV_CFG_H
+
+/* can_api.c */
+#define CAN_TEST_GLOBAL_CH  1
+
+/* gpio_api.c */
+#define GPIO_GROUP_MAX      11
+
+/* pwmout_api.c */
+#define FUNC_MOTOR_CTL_PWM
+#define FUMC_MTU2_PWM
+
+/* rtc_api.c */
+//#define USE_RTCX1_CLK
+#define USE_EXTAL_CLK
+//#define USE_RTCX3_CLK
+
+#define RENESAS_RZ_A1_P0_CLK   CM0_RENESAS_RZ_A1_P0_CLK
+
+#define LP_TICKER_MTU2_CH      3
+
+/* flash (MX25L6433FM2I) */
+#define FLASH_BASE                 (0x18000000UL) /**< Flash Base Address */
+#define FLASH_SIZE                 (0x00800000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE            256            /**< Flash Memory page size (interleaving off) */
+                                                  /**< Maximum size per one writing is 256 byte and minimum size per one writing is 1 byte */
+#define FLASH_SECTOR_SIZE          4096           /**< Flash Memory sector size (interleaving off) */
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/trng_api_esp32.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/trng_api_esp32.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/trng_api_esp32.c	(revision 374)
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_TRNG)
+#include "mbed.h"
+
+#define ESP32_I2C_ADDR    (0x28<<1)
+
+void trng_init_esp32(void) {
+    /* P3_10(EN), P3_9(IO0) */
+    if (((GPIOP3   & 0x0400) == 0)
+     || ((GPIOPMC3 & 0x0400) != 0)
+     || ((GPIOPM3  & 0x0400) != 0)
+
+     || ((GPIOP3   & 0x0200) == 0)
+     || ((GPIOPMC3 & 0x0200) != 0)
+     || ((GPIOPM3  & 0x0200) != 0)) {
+
+        /* P3_10(EN) */
+        GPIOP3   &= ~0x0400;         /* Outputs low level */
+        GPIOPMC3 &= ~0x0400;         /* Port mode */
+        GPIOPM3  &= ~0x0400;         /* Output mode */
+
+        /* P3_9(IO0) */
+        GPIOP3   &= ~0x0200;         /* Outputs low level */
+        GPIOPMC3 &= ~0x0200;         /* Port mode */
+        GPIOPM3  &= ~0x0200;         /* Output mode */
+
+        GPIOP3   |=  0x2000;         /* Outputs hi level */
+        wait_ms(5);
+        GPIOP3   |=  0x0400;         /* Outputs hi level */
+    }
+}
+
+void trng_free_esp32(void) {
+    // do nothing
+}
+
+int trng_get_bytes_esp32(uint8_t *output, size_t length, size_t *output_length) {
+    I2C mI2c(I2C_SDA, I2C_SCL);
+    int ret;
+    char send_data[1];
+    char recv_data[4];
+    size_t idx = 0;
+    int i;
+    int err_cnt = 0;
+
+    while (idx < length) {
+        send_data[0] = 0;
+        ret = mI2c.write(ESP32_I2C_ADDR, send_data, 1);
+        if (ret == 0) {
+            mI2c.read(ESP32_I2C_ADDR, recv_data, sizeof(recv_data));
+            for (i = 0; (i < 4) && (idx < length); i++) {
+                output[idx++] = recv_data[i];
+            }
+        } else {
+            err_cnt++;
+            if (err_cnt >= 20) {
+                break;
+            }
+            wait_ms(100);
+        }
+    }
+    if (output_length != NULL) {
+        *output_length = idx;
+    }
+
+    return (idx != 0 ? 0 : -1);
+}
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/analogin_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/analogin_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/analogin_api.c	(revision 374)
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#include "cmsis.h"
+#include "PeripheralPins.h"
+
+#include "iodefine.h"
+
+#define ANALOGIN_MEDIAN_FILTER      0
+
+static volatile uint16_t *ADCDR[] = {
+    &ADCADDRA,
+    &ADCADDRB,
+    &ADCADDRC,
+    &ADCADDRD,
+    &ADCADDRE,
+    &ADCADDRF,
+    &ADCADDRG,
+    &ADCADDRH,
+};
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    CPGSTBCR3 &= ~(1 << 1);
+    CPGSTBCR6 &= ~(1 << 7);
+
+    // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 
+    //    [8:6] CKS 010 :: 340tclk 
+    //    [5:3] MDS 000 :: single mode 
+    //    [2:0] CH  000 :: AN0 
+    ADCADCSR = 0x0080; 
+
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    volatile uint16_t data;
+
+    // Select the appropriate channel and start conversion
+    ADCADCSR &= 0xfff8;
+    ADCADCSR |= (1 << 13 | (obj->adc & 0x7));
+
+    // Wait end of conversion
+    do {
+        data = ADCADCSR;
+    } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0));
+
+    // clear flag
+    ADCADCSR &= ~(1 << 15);
+
+    return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF;   // 12 bits range
+}
+
+#if ANALOGIN_MEDIAN_FILTER
+static inline void order(uint32_t *a, uint32_t *b) {
+    if (*a > *b) {
+        uint32_t t = *a;
+        *a = *b;
+        *b = t;
+    }
+}
+#endif
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+    uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+    uint32_t v1 = adc_read(obj);
+    uint32_t v2 = adc_read(obj);
+    uint32_t v3 = adc_read(obj);
+    order(&v1, &v2);
+    order(&v2, &v3);
+    order(&v1, &v2);
+    value = v2;
+#else
+    value = adc_read(obj);
+#endif
+    return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+
+    return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion
+}
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+
+    return (float)value * (1.0f / (float)0x0FFF);  // 12 bits range
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/can_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/can_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/can_api.c	(revision 374)
@@ -0,0 +1,1035 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "mbed_assert.h"
+#include "can_api.h"
+#include "RZ_A1_Init.h"
+#include "cmsis.h"
+#include "PeripheralPins.h"
+#include "iodefine.h"
+#include "r_typedefs.h"
+#include "mbed_drv_cfg.h"
+
+#if defined(TARGET_RZA1H)
+#define CAN_NUM         5
+#else
+#define CAN_NUM         2
+#endif
+#define CAN_SND_RCV     2
+#define IRQ_NUM         8
+
+static void can_rec_irq(uint32_t ch);
+static void can_trx_irq(uint32_t ch);
+static void can_err_irq(uint32_t ch, CanIrqType type);
+static void can0_rec_irq(void);
+static void can0_trx_irq(void);
+static void can0_err_warning_irq(void);
+static void can0_overrun_irq(void);
+static void can0_passive_irq(void);
+static void can0_arb_lost_irq(void);
+static void can0_bus_err_irq(void);
+static void can1_rec_irq(void);
+static void can1_trx_irq(void);
+static void can1_err_warning_irq(void);
+static void can1_overrun_irq(void);
+static void can1_passive_irq(void);
+static void can1_arb_lost_irq(void);
+static void can1_bus_err_irq(void);
+#if defined(TARGET_RZA1H)
+static void can2_rec_irq(void);
+static void can2_trx_irq(void);
+static void can2_err_warning_irq(void);
+static void can2_overrun_irq(void);
+static void can2_passive_irq(void);
+static void can2_arb_lost_irq(void);
+static void can2_bus_err_irq(void);
+static void can3_rec_irq(void);
+static void can3_trx_irq(void);
+static void can3_err_warning_irq(void);
+static void can3_overrun_irq(void);
+static void can3_passive_irq(void);
+static void can3_arb_lost_irq(void);
+static void can3_bus_err_irq(void);
+static void can4_rec_irq(void);
+static void can4_trx_irq(void);
+static void can4_err_warning_irq(void);
+static void can4_overrun_irq(void);
+static void can4_passive_irq(void);
+static void can4_arb_lost_irq(void);
+static void can4_bus_err_irq(void);
+#endif
+
+static void can_reset_reg(can_t *obj);
+static void can_reset_recv_rule(can_t *obj);
+static void can_reset_buffer(can_t *obj);
+static void can_reconfigure_channel(void);
+static void can_set_frequency(can_t *obj, int f);
+static void can_set_global_mode(int mode);
+static void can_set_channel_mode(uint32_t ch, int mode);
+
+typedef enum {
+    CAN_SEND = 0,
+    CAN_RECV
+} CANfunc;
+
+typedef enum {
+    GL_OPE = 0,
+    GL_RESET,
+    GL_TEST
+} Globalmode;
+
+typedef enum {
+    CH_COMM = 0,
+    CH_RESET,
+    CH_HOLD
+} Channelmode;
+
+typedef struct {
+    IRQn_Type   int_num;    /* Interrupt number */
+    IRQHandler  handler;    /* Interrupt handler */
+} can_info_int_t;
+
+static can_irq_handler irq_handler;
+static uint32_t can_irq_id[CAN_NUM];
+static int can_initialized[CAN_NUM] = {0};
+
+
+static __IO uint32_t *CTR_MATCH[] = {
+    &RSCAN0C0CTR,
+    &RSCAN0C1CTR,
+#if defined(TARGET_RZA1H)
+    &RSCAN0C2CTR,
+    &RSCAN0C3CTR,
+    &RSCAN0C4CTR,
+#endif
+};
+
+static __IO uint32_t *CFG_MATCH[] = {
+    &RSCAN0C0CFG,
+    &RSCAN0C1CFG,
+#if defined(TARGET_RZA1H)
+    &RSCAN0C2CFG,
+    &RSCAN0C3CFG,
+    &RSCAN0C4CFG,
+#endif
+};
+
+static __IO uint32_t *RFCC_MATCH[] = {
+    &RSCAN0RFCC0,
+    &RSCAN0RFCC1,
+    &RSCAN0RFCC2,
+    &RSCAN0RFCC3,
+    &RSCAN0RFCC4,
+    &RSCAN0RFCC5,
+    &RSCAN0RFCC6,
+    &RSCAN0RFCC7
+};
+
+static __IO uint32_t *TXQCC_MATCH[] = {
+    &RSCAN0TXQCC0,
+    &RSCAN0TXQCC1,
+#if defined(TARGET_RZA1H)
+    &RSCAN0TXQCC2,
+    &RSCAN0TXQCC3,
+    &RSCAN0TXQCC4,
+#endif
+};
+
+static __IO uint32_t *THLCC_MATCH[] = {
+    &RSCAN0THLCC0,
+    &RSCAN0THLCC1,
+#if defined(TARGET_RZA1H)
+    &RSCAN0THLCC2,
+    &RSCAN0THLCC3,
+    &RSCAN0THLCC4,
+#endif
+};
+
+static __IO uint32_t *STS_MATCH[] = {
+    &RSCAN0C0STS,
+    &RSCAN0C1STS,
+#if defined(TARGET_RZA1H)
+    &RSCAN0C2STS,
+    &RSCAN0C3STS,
+    &RSCAN0C4STS,
+#endif
+};
+
+static __IO uint32_t *ERFL_MATCH[] = {
+    &RSCAN0C0ERFL,
+    &RSCAN0C1ERFL,
+#if defined(TARGET_RZA1H)
+    &RSCAN0C2ERFL,
+    &RSCAN0C3ERFL,
+    &RSCAN0C4ERFL,
+#endif
+};
+
+static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFCC0 , &RSCAN0CFCC1  },
+    { &RSCAN0CFCC3 , &RSCAN0CFCC4  },
+#if defined(TARGET_RZA1H)
+    { &RSCAN0CFCC6 , &RSCAN0CFCC7  },
+    { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
+    { &RSCAN0CFCC12, &RSCAN0CFCC13 },
+#endif
+};
+
+static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFSTS0 , &RSCAN0CFSTS1  },
+    { &RSCAN0CFSTS3 , &RSCAN0CFSTS4  },
+#if defined(TARGET_RZA1H)
+    { &RSCAN0CFSTS6 , &RSCAN0CFSTS7  },
+    { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
+    { &RSCAN0CFSTS12, &RSCAN0CFSTS13 },
+#endif
+};
+
+static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1  },
+    { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4  },
+#if defined(TARGET_RZA1H)
+    { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7  },
+    { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
+    { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 },
+#endif
+};
+
+static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFID0 , &RSCAN0CFID1  },
+    { &RSCAN0CFID3 , &RSCAN0CFID4  },
+#if defined(TARGET_RZA1H)
+    { &RSCAN0CFID6 , &RSCAN0CFID7  },
+    { &RSCAN0CFID9 , &RSCAN0CFID10 },
+    { &RSCAN0CFID12, &RSCAN0CFID13 },
+#endif
+};
+
+static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFPTR0 , &RSCAN0CFPTR1  },
+    { &RSCAN0CFPTR3 , &RSCAN0CFPTR4  },
+#if defined(TARGET_RZA1H)
+    { &RSCAN0CFPTR6 , &RSCAN0CFPTR7  },
+    { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
+    { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
+#endif
+};
+
+static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFDF00 , &RSCAN0CFDF01  },
+    { &RSCAN0CFDF03 , &RSCAN0CFDF04  },
+#if defined(TARGET_RZA1H)
+    { &RSCAN0CFDF06 , &RSCAN0CFDF07  },
+    { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
+    { &RSCAN0CFDF012, &RSCAN0CFDF013 },
+#endif
+};
+
+static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFDF10 , &RSCAN0CFDF11  },
+    { &RSCAN0CFDF13 , &RSCAN0CFDF14  },
+#if defined(TARGET_RZA1H)
+    { &RSCAN0CFDF16 , &RSCAN0CFDF17  },
+    { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
+    { &RSCAN0CFDF112, &RSCAN0CFDF113 },
+#endif
+};
+
+static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = 
+{
+    {   /* ch0 */
+        { INTRCAN0REC_IRQn, can0_rec_irq         }, /* RxIrq */
+        { INTRCAN0TRX_IRQn, can0_trx_irq         }, /* TxIrq */
+        { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */
+        { INTRCAN0ERR_IRQn, can0_overrun_irq     }, /* DoIrq */
+        { INTRCAN0ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN0ERR_IRQn, can0_passive_irq     }, /* EpIrq */
+        { INTRCAN0ERR_IRQn, can0_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN0ERR_IRQn, can0_bus_err_irq     }  /* BeIrq */
+    },
+    {   /* ch1 */
+        { INTRCAN1REC_IRQn, can1_rec_irq         }, /* RxIrq */
+        { INTRCAN1TRX_IRQn, can1_trx_irq         }, /* TxIrq */
+        { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */
+        { INTRCAN1ERR_IRQn, can1_overrun_irq     }, /* DoIrq */
+        { INTRCAN1ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN1ERR_IRQn, can1_passive_irq     }, /* EpIrq */
+        { INTRCAN1ERR_IRQn, can1_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN1ERR_IRQn, can1_bus_err_irq     }  /* BeIrq */
+    },
+#if defined(TARGET_RZA1H)
+    {   /* ch2 */
+        { INTRCAN2REC_IRQn, can2_rec_irq         }, /* RxIrq */
+        { INTRCAN2TRX_IRQn, can2_trx_irq         }, /* TxIrq */
+        { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */
+        { INTRCAN2ERR_IRQn, can2_overrun_irq     }, /* DoIrq */
+        { INTRCAN2ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN2ERR_IRQn, can2_passive_irq     }, /* EpIrq */
+        { INTRCAN2ERR_IRQn, can2_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN2ERR_IRQn, can2_bus_err_irq     }  /* BeIrq */
+    },
+    {   /* ch3 */
+        { INTRCAN3REC_IRQn, can3_rec_irq         }, /* RxIrq */
+        { INTRCAN3TRX_IRQn, can3_trx_irq         }, /* TxIrq */
+        { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */
+        { INTRCAN3ERR_IRQn, can3_overrun_irq     }, /* DoIrq */
+        { INTRCAN3ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN3ERR_IRQn, can3_passive_irq     }, /* EpIrq */
+        { INTRCAN3ERR_IRQn, can3_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN3ERR_IRQn, can3_bus_err_irq     }  /* BeIrq */
+    },
+    {   /* ch4 */
+        { INTRCAN4REC_IRQn, can4_rec_irq         }, /* RxIrq */
+        { INTRCAN4TRX_IRQn, can4_trx_irq         }, /* TxIrq */
+        { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */
+        { INTRCAN4ERR_IRQn, can4_overrun_irq     }, /* DoIrq */
+        { INTRCAN4ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN4ERR_IRQn, can4_passive_irq     }, /* EpIrq */
+        { INTRCAN4ERR_IRQn, can4_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN4ERR_IRQn, can4_bus_err_irq     }  /* BeIrq */
+    },
+#endif
+};
+
+static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
+static __IO uint32_t *dmy_gaflm  = &RSCAN0GAFLM0;
+static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00;
+static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10;
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    can_irq_id[obj->ch] = id;
+}
+
+void can_irq_free(can_t *obj) {
+    can_irq_id[obj->ch] = 0;
+}
+
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
+    __IO uint32_t *dmy_ctr;
+
+    /* Wake-up Irq is not supported */
+    if (type != IRQ_WAKEUP) {
+        if (enable) {
+            dmy_ctr = CTR_MATCH[obj->ch];
+            if (type == IRQ_ERROR) {
+                /* EWIE interrupts is enable */
+                *dmy_ctr |= 0x00000200;
+            } else if (type == IRQ_OVERRUN) {
+                /* OLIE interrupts is enable */
+                *dmy_ctr |= 0x00002000;
+            } else if (type == IRQ_PASSIVE) {
+                /* EPIE interrupts is enable */
+                *dmy_ctr |= 0x00000400;
+            } else if (type == IRQ_ARB) {
+                /* ALIE interrupts is enable */
+                *dmy_ctr |= 0x00008000;
+            } else if (type == IRQ_BUS) {
+                /* BEIE interrupts is enable */
+                *dmy_ctr |= 0x00000100;
+            }
+            InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
+            GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
+            GIC_SetConfiguration(can_int_info[obj->ch][type].int_num, 1);
+            GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
+        } else {
+            GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
+        }
+    }
+}
+
+static void can_rec_irq(uint32_t ch) {
+    __IO uint32_t *dmy_cfsts;
+
+    dmy_cfsts = CFSTS_TBL[ch][CAN_RECV];
+    *dmy_cfsts &= 0xFFFFFFF7;           // Clear CFRXIF
+
+    irq_handler(can_irq_id[ch], IRQ_RX);
+}
+
+static void can_trx_irq(uint32_t ch) {
+    __IO uint32_t *dmy_cfsts;
+
+    dmy_cfsts = CFSTS_TBL[ch][CAN_SEND];
+    *dmy_cfsts &= 0xFFFFFFEF;           // Clear CFTXIF
+
+    irq_handler(can_irq_id[ch], IRQ_TX);
+}
+
+static void can_err_irq(uint32_t ch, CanIrqType type) {
+    __IO uint32_t *dmy_erfl;
+    int val = 1;
+    
+    dmy_erfl = ERFL_MATCH[ch];
+    switch (type) {
+        case IRQ_ERROR:
+            *dmy_erfl &= 0xFFFFFFFD;    // Clear EWF
+            break;
+        case IRQ_OVERRUN:
+            *dmy_erfl &= 0xFFFFFFDF;    // Clear OVLF
+            break;
+        case IRQ_PASSIVE:
+            *dmy_erfl &= 0xFFFFFFFB;    // Clear EPF
+            break;
+        case IRQ_ARB:
+            *dmy_erfl &= 0xFFFFFF7F;    // Clear ALF
+            break;
+        case IRQ_BUS:
+            *dmy_erfl &= 0xFFFF00FF;    // Clear ADERR、B0ERR、B1ERR、CERR、AERR、FERR、SERR
+            *dmy_erfl &= 0xFFFFFFFE;    // Clear BEF
+            break;
+        case IRQ_WAKEUP:
+            /* not supported */
+            /* fall through */
+        default:
+            val = 0;
+            break;
+    }
+    if (val == 1) {
+        irq_handler(can_irq_id[ch], type);
+    }
+}
+
+static void can0_rec_irq(void) {
+    can_rec_irq(CAN_0);
+}
+
+static void can0_trx_irq(void) {
+    can_trx_irq(CAN_0);
+}
+
+static void can0_err_warning_irq(void) {
+    can_err_irq(CAN_0, IRQ_ERROR);
+}
+
+static void can0_overrun_irq(void) {
+    can_err_irq(CAN_0, IRQ_OVERRUN);
+}
+
+static void can0_passive_irq(void) {
+    can_err_irq(CAN_0, IRQ_PASSIVE);
+}
+
+static void can0_arb_lost_irq(void) {
+    can_err_irq(CAN_0, IRQ_ARB);
+}
+
+static void can0_bus_err_irq(void) {
+    can_err_irq(CAN_0, IRQ_BUS);
+}
+
+static void can1_rec_irq(void) {
+    can_rec_irq(CAN_1);
+}
+
+static void can1_trx_irq(void) {
+    can_trx_irq(CAN_1);
+}
+
+static void can1_err_warning_irq(void) {
+    can_err_irq(CAN_1, IRQ_ERROR);
+}
+
+static void can1_overrun_irq(void) {
+    can_err_irq(CAN_1, IRQ_OVERRUN);
+}
+
+static void can1_passive_irq(void) {
+    can_err_irq(CAN_1, IRQ_PASSIVE);
+}
+
+static void can1_arb_lost_irq(void) {
+    can_err_irq(CAN_1, IRQ_ARB);
+}
+
+static void can1_bus_err_irq(void) {
+    can_err_irq(CAN_1, IRQ_BUS);
+}
+
+#if defined(TARGET_RZA1H)
+static void can2_rec_irq(void) {
+    can_rec_irq(CAN_2);
+}
+
+static void can2_trx_irq(void) {
+    can_trx_irq(CAN_2);
+}
+
+static void can2_err_warning_irq(void) {
+    can_err_irq(CAN_2, IRQ_ERROR);
+}
+
+static void can2_overrun_irq(void) {
+    can_err_irq(CAN_2, IRQ_OVERRUN);
+}
+
+static void can2_passive_irq(void) {
+    can_err_irq(CAN_2, IRQ_PASSIVE);
+}
+
+static void can2_arb_lost_irq(void) {
+    can_err_irq(CAN_2, IRQ_ARB);
+}
+
+static void can2_bus_err_irq(void) {
+    can_err_irq(CAN_2, IRQ_BUS);
+}
+
+static void can3_rec_irq(void) {
+    can_rec_irq(CAN_3);
+}
+
+static void can3_trx_irq(void) {
+    can_trx_irq(CAN_3);
+}
+
+static void can3_err_warning_irq(void) {
+    can_err_irq(CAN_3, IRQ_ERROR);
+}
+
+static void can3_overrun_irq(void) {
+    can_err_irq(CAN_3, IRQ_OVERRUN);
+}
+
+static void can3_passive_irq(void) {
+    can_err_irq(CAN_3, IRQ_PASSIVE);
+}
+
+static void can3_arb_lost_irq(void) {
+    can_err_irq(CAN_3, IRQ_ARB);
+}
+
+static void can3_bus_err_irq(void) {
+    can_err_irq(CAN_3, IRQ_BUS);
+}
+
+static void can4_rec_irq(void) {
+    can_rec_irq(CAN_4);
+}
+
+static void can4_trx_irq(void) {
+    can_trx_irq(CAN_4);
+}
+
+static void can4_err_warning_irq(void) {
+    can_err_irq(CAN_4, IRQ_ERROR);
+}
+
+static void can4_overrun_irq(void) {
+    can_err_irq(CAN_4, IRQ_OVERRUN);
+}
+
+static void can4_passive_irq(void) {
+    can_err_irq(CAN_4, IRQ_PASSIVE);
+}
+
+static void can4_arb_lost_irq(void) {
+    can_err_irq(CAN_4, IRQ_ARB);
+}
+
+static void can4_bus_err_irq(void) {
+    can_err_irq(CAN_4, IRQ_BUS);
+}
+#endif
+
+void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) {
+    __IO uint32_t *dmy_ctr;
+
+    /* determine the CAN to use */
+    uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
+    uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
+    obj->ch = pinmap_merge(can_tx, can_rx);
+    MBED_ASSERT((int)obj->ch != NC);
+
+    /* enable CAN clock */
+    CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32);
+    /* Has CAN RAM initialisation completed ? */
+    while ((RSCAN0GSTS & 0x08) == 0x08) {
+        __NOP();
+    }
+    /* clear Global Stop mode bit */
+    RSCAN0GCTR &= 0xFFFFFFFB;
+    /* clear Channel Stop mode bit */
+    dmy_ctr = CTR_MATCH[obj->ch];
+    *dmy_ctr &= 0xFFFFFFFB;
+    /* Enter global reset mode */
+    can_set_global_mode(GL_RESET);
+    /* Enter channel reset mode */
+    can_set_channel_mode(obj->ch, CH_RESET);
+    /* reset register */
+    can_reset_reg(obj);
+
+    can_initialized[obj->ch] = 1;
+    /* reconfigure channel which is already initialized */
+    can_reconfigure_channel();
+    
+    /* pin out the can pins */
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    pinmap_pinout(td, PinMap_CAN_TD);
+
+    /* set can frequency */
+    can_frequency(obj, hz);
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+    can_init_freq(obj, rd, td, 100000);
+}
+
+void can_free(can_t *obj) {
+    /* disable CAN clock */
+    CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32;
+}
+
+int can_frequency(can_t *obj, int f) {
+    __IO uint32_t *dmy_cfcc;
+    int retval = 0;
+    
+    if (f <= 1000000) {
+        /* less than 1Mhz */
+        /* set Channel Reset mode */
+        can_set_channel_mode(obj->ch, CH_RESET);
+        can_set_frequency(obj, f);
+        /* set Channel Communication mode */
+        can_set_channel_mode(obj->ch, CH_COMM);
+        /* restore  CFE bit since it is cleared */
+        /* Use send/receive FIFO buffer */
+        dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+        *dmy_cfcc |= 0x01;
+        dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+        *dmy_cfcc |= 0x01;
+        retval = 1;
+    }
+
+    return retval;
+}
+
+void can_reset(can_t *obj) {
+    /* Enter global reset mode */
+    can_set_global_mode(GL_RESET);
+    /* Enter channel reset mode */
+    can_set_channel_mode(obj->ch, CH_RESET);
+    /* reset register */
+    can_reset_reg(obj);
+    /* reconfigure channel which is already initialized */
+    can_reconfigure_channel();
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+    __IO uint32_t *dmy_sts;
+    __IO uint32_t *dmy_cfsts;
+    __IO uint32_t *dmy_cfid;
+    __IO uint32_t *dmy_cfptr;
+    __IO uint32_t *dmy_cfdf0;
+    __IO uint32_t *dmy_cfdf1;
+    __IO uint32_t *dmy_cfpctr;
+    int retval = 0;
+
+    /* Wait to become channel communication mode */
+    dmy_sts = STS_MATCH[obj->ch];
+    while ((*dmy_sts & 0x07) != 0) {
+        __NOP();
+    }
+    
+    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) {
+        /* send/receive FIFO buffer isn't full */
+        dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
+        if ((*dmy_cfsts & 0x02) != 0x02) {
+            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
+            dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
+            *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
+            if (msg.format == CANStandard) {
+                *dmy_cfid |= (msg.id & 0x07FF);
+            } else {
+                *dmy_cfid |= (msg.id & 0x1FFFFFFF);
+            }
+            /* set length */
+            dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
+            *dmy_cfptr = msg.len << 28;
+            /* set data */
+            dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND];
+            memcpy((void *)dmy_cfdf0, &msg.data[0], 4);
+            dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND];
+            memcpy((void *)dmy_cfdf1, &msg.data[4], 4);
+            /* send request */
+            dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND];
+            *dmy_cfpctr = 0xFF;
+            retval = 1;
+        }
+    }
+    
+    return retval;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle) {
+    __IO uint32_t *dmy_sts;
+    __IO uint32_t *dmy_cfsts;
+    __IO uint32_t *dmy_cfid;
+    __IO uint32_t *dmy_cfptr;
+    __IO uint32_t *dmy_cfdf0;
+    __IO uint32_t *dmy_cfdf1;
+    __IO uint32_t *dmy_cfpctr;
+    int retval = 0;
+
+    /* Wait to become channel communication mode */
+    dmy_sts = STS_MATCH[obj->ch];
+    while ((*dmy_sts & 0x07) != 0) {
+        __NOP();
+    }
+    
+    /* send/receive FIFO buffer isn't empty */
+    dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
+    while ((*dmy_cfsts & 0x01) != 0x01) {
+        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
+        dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
+        msg->format = (CANFormat)(*dmy_cfid >> 31);
+        msg->type = (CANType)((*dmy_cfid >> 30) & 0x1);
+        if (msg->format == CANStandard) {
+            msg->id = (*dmy_cfid & 0x07FF);
+        } else {
+            msg->id = (*dmy_cfid & 0x1FFFFFFF);
+        }
+        /* get length */
+        dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
+        msg->len = (unsigned char)(*dmy_cfptr >> 28);
+        /* get data */
+        dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV];
+        memcpy(&msg->data[0], (void *)dmy_cfdf0, 4);
+        dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV];
+        memcpy(&msg->data[4], (void *)dmy_cfdf1, 4);
+        /* receive(next data) request */
+        dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV];
+        *dmy_cfpctr = 0xFF;
+        retval = 1;
+    }
+    
+    return retval;
+}
+
+unsigned char can_rderror(can_t *obj) {
+    __IO uint32_t *dmy_sts;
+    
+    dmy_sts = STS_MATCH[obj->ch];
+    return (unsigned char)((*dmy_sts >> 16) & 0xFF);
+}
+
+unsigned char can_tderror(can_t *obj) {
+    __IO uint32_t *dmy_sts;
+    
+    dmy_sts = STS_MATCH[obj->ch];
+    return (unsigned char)((*dmy_sts >> 24) & 0xFF);
+}
+
+int can_mode(can_t *obj, CanMode mode) {
+    __IO uint32_t *dmy_ctr;
+    __IO uint32_t *dmy_sts;
+    __IO uint32_t *dmy_cfcc;
+    int ch_cnt;
+    can_t *tmp_obj;
+    tmp_obj = obj;
+    int retval = 1;
+    
+    switch (mode) {
+        case MODE_RESET:
+            can_set_global_mode(GL_RESET);
+            can_set_channel_mode(obj->ch, CH_RESET);
+            for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
+                can_initialized[ch_cnt] = 0;
+            }
+            break;
+        case MODE_NORMAL:
+            can_set_global_mode(GL_OPE);
+            can_set_channel_mode(obj->ch, CH_COMM);
+            break;
+        case MODE_SILENT:
+            can_set_channel_mode(obj->ch, CH_HOLD);
+            /* set listen only mode, enable communication test mode */
+            dmy_ctr = CTR_MATCH[obj->ch];
+            *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
+            can_set_channel_mode(obj->ch, CH_COMM);
+            break;
+        case MODE_TEST_LOCAL:
+            can_set_channel_mode(obj->ch, CH_HOLD);
+            /* set self test mode 0, enable communication test mode */
+            dmy_ctr = CTR_MATCH[obj->ch];
+            *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000);
+            can_set_channel_mode(obj->ch, CH_COMM);
+            break;
+        case MODE_TEST_GLOBAL:
+            /* set the channel between the communication test on CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */
+            /* set Channel Hold mode */
+            for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) {
+                dmy_sts = STS_MATCH[tmp_obj->ch];
+                if ((*dmy_sts & 0x04) == 0x04) {
+                    /* Channel Stop mode */
+                    /* clear Channel Stop mode bit */
+                    dmy_ctr = CTR_MATCH[tmp_obj->ch];
+                    *dmy_ctr &= 0xFFFFFFFB;
+                    can_set_channel_mode(tmp_obj->ch, CH_RESET);
+                }
+                can_set_channel_mode(tmp_obj->ch, CH_HOLD);
+            }
+            can_set_global_mode(GL_TEST);
+            /* enable communication test between CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */
+            RSCAN0GTSTCFG = 0x06;
+            RSCAN0GTSTCTR = 0x01;
+            /* send and receive setting of channel1 and channel2 */
+            for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) {
+                can_reset_buffer(tmp_obj);
+                /* set global interrrupt */
+                /* THLEIE, MEIE and DEIE interrupts are disable */
+                RSCAN0GCTR &= 0xFFFFF8FF;
+                /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */
+                /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */
+                dmy_ctr = CTR_MATCH[tmp_obj->ch];
+                *dmy_ctr &= 0x00018700;
+                can_set_global_mode(GL_OPE);
+                can_set_channel_mode(tmp_obj->ch, CH_COMM);
+                /* Use send/receive FIFO buffer */
+                dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND];
+                *dmy_cfcc |= 0x01;
+                dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV];
+                *dmy_cfcc |= 0x01;
+            }
+            break;
+        case MODE_TEST_SILENT:
+            /* not supported */
+            /* fall through */
+        default:
+            retval = 0;
+            break;
+    }
+    
+    return retval;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
+    int retval = 0;
+    
+    if ((format == CANStandard) || (format == CANExtended)) {
+        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) {
+            /* set Global Reset mode and Channel Reset mode */
+            can_set_global_mode(GL_RESET);
+            can_set_channel_mode(obj->ch, CH_RESET);
+            /* enable receive rule table writing */
+            RSCAN0GAFLECTR = 0x00000100;
+            /* set the page number of receive rule table(page number = 0) */
+            RSCAN0GAFLECTR |= (obj->ch * 4);
+            /* set IDE format */
+            *dmy_gaflid = (format << 31);
+            if (format == CANExtended) {
+                /* set receive rule ID for bit28-0 */
+                *dmy_gaflid |= (id & 0x1FFFFFFF);
+            } else {
+                /* set receive rule ID for bit10-0 */
+                *dmy_gaflid |= (id & 0x07FF);
+            }
+            /* set ID mask bit */
+            *dmy_gaflm = (0xC0000000 | mask);
+            /* disable receive rule table writing */
+            RSCAN0GAFLECTR &= 0xFFFFFEFF;
+            /* reconfigure channel which is already initialized */
+            can_reconfigure_channel();
+            retval = 1;
+        }
+    }
+    
+    return retval;
+}
+
+void can_monitor(can_t *obj, int silent) {
+    __IO uint32_t *dmy_ctr;
+
+    /* set Channel Hold mode */
+    can_set_channel_mode(obj->ch, CH_HOLD);
+    if (silent) {
+        /* set listen only mode, enable communication test mode */
+        dmy_ctr = CTR_MATCH[obj->ch];
+        *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
+        can_set_channel_mode(obj->ch, CH_COMM);
+    } else {
+        /* set normal test mode, disable communication test mode */
+        dmy_ctr = CTR_MATCH[obj->ch];
+        *dmy_ctr &= 0x00FFFFFF;
+        /* reset register */
+        can_reset_reg(obj);
+        /* reconfigure channel which is already initialized */
+        can_reconfigure_channel();
+    }
+}
+
+static void can_reset_reg(can_t *obj) {
+    __IO uint32_t *dmy_ctr;
+
+    /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2),           */
+    /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */
+    RSCAN0GCFG = 0x00000003;
+    /* set default frequency at 100k */
+    can_set_frequency(obj, 100000);
+    /* set receive rule */
+    can_reset_recv_rule(obj);
+    /* set buffer */
+    can_reset_buffer(obj);
+    /* set global interrrupt */
+    /* THLEIE, MEIE and DEIE interrupts are disable */
+    RSCAN0GCTR &= 0xFFFFF8FF;
+    /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */
+    dmy_ctr = CTR_MATCH[obj->ch];
+    *dmy_ctr &= 0xFFFF00FF;
+}
+
+static void can_reset_recv_rule(can_t *obj) {
+    /* number of receive rules of each chanel = 64 */
+    RSCAN0GAFLCFG0 = 0x40404040;
+#if defined(TARGET_RZA1H)
+    RSCAN0GAFLCFG1 = 0x40000000;
+#endif
+    /* enable receive rule table writing */
+    RSCAN0GAFLECTR = 0x00000100;
+    /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
+    RSCAN0GAFLECTR |= (obj->ch * 4);
+    /* set standard ID, data frame and receive rule ID */
+    *dmy_gaflid = 0x07FF;
+    /* IDE bit, RTR bit and ID bit(28-0) are not compared */
+    *dmy_gaflm = 0;
+    /* DLC check is 1 bytes, not use a receive buffer */
+    *dmy_gaflp0 = 0x10000000;
+    /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */
+    *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3));
+    /* disable receive rule table writing */
+    RSCAN0GAFLECTR &= 0xFFFFFEFF;
+}
+
+static void can_reset_buffer(can_t *obj) {
+    __IO uint32_t *dmy_rfcc;
+    __IO uint32_t *dmy_cfcc;
+    __IO uint32_t *dmy_txqcc;
+    __IO uint32_t *dmy_thlcc;
+    int cnt;
+    
+    /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */
+    /* number of rows of send/receive FIFO buffer = 4 */
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+    *dmy_cfcc = 0x00011100;                 /* send/receive FIFO mode is send */
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+    *dmy_cfcc = 0x00001100;                 /* send/receive FIFO mode is receive */
+    /* receive buffer is not used */
+    RSCAN0RMNB = 0;
+    /* receive FIFO buffer is not used */
+    for (cnt = 0; cnt < 8; cnt++) {
+        dmy_rfcc = RFCC_MATCH[cnt];
+        *dmy_rfcc = 0;
+    }
+    /* send queue is not used */
+    dmy_txqcc = TXQCC_MATCH[obj->ch];
+    *dmy_txqcc = 0;
+    /* send history is not used */
+    dmy_thlcc = THLCC_MATCH[obj->ch];
+    *dmy_thlcc = 0;
+
+    /* CFTXIE and CFRXIE interrupts are enable */
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+    *dmy_cfcc |= 0x04;
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+    *dmy_cfcc |= 0x02;
+    /* TMIEp interrupt is disable */
+    RSCAN0TMIEC0 = 0x00000000;
+#if defined(TARGET_RZA1H)
+    RSCAN0TMIEC1 = 0x00000000;
+    RSCAN0TMIEC2 = 0x00000000;
+#endif
+}
+
+static void can_reconfigure_channel(void) {
+    __IO uint32_t *dmy_cfcc;
+    int ch_cnt;
+
+    for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
+        if (can_initialized[ch_cnt] == 1) {
+            /* set Global Operation mode and Channel Communication mode */
+            can_set_global_mode(GL_OPE);
+            can_set_channel_mode(ch_cnt, CH_COMM);
+            /* Use send/receive FIFO buffer */
+            dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND];
+            *dmy_cfcc |= 0x01;
+            dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV];
+            *dmy_cfcc |= 0x01;
+        }
+    }
+}
+
+static void can_set_frequency(can_t *obj, int f) {
+    __IO uint32_t *dmy_cfg;
+    int oldfreq = 0;
+    int newfreq = 0;
+    uint32_t  clkc_val;
+    uint8_t tmp_tq;
+    uint8_t tq = 0;
+    uint8_t tmp_brp;
+    uint8_t brp = 0;
+    uint8_t tseg1 = 0;
+    uint8_t tseg2 = 0;
+    uint8_t sjw = 0;
+    
+    /* set clkc */
+    if (RZ_A1_IsClockMode0() == false) {
+        clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
+    } else {
+        clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
+    }
+    /* calculate BRP bit and Choose max value of calculated frequency */
+    for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
+        /* f = fCAN / ((BRP+1) * Tq) */
+        /* BRP = (fCAN / (f * Tq)) - 1 */
+        tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1;   // carry(decimal point is carry)
+        newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
+        if (newfreq >= oldfreq) {
+            oldfreq  = newfreq;
+            tq       = tmp_tq;
+            brp      = tmp_brp;
+        }
+    }
+    /* calculate TSEG1 bit and TSEG2 bit */
+    tseg1 = (tq - 1) * 0.666666667;
+    tseg2 = (tq - 1) - tseg1;
+    sjw = (tseg2 > 4)? 4 : tseg2;
+    /* set RSCAN0CmCFG register */
+    dmy_cfg = CFG_MATCH[obj->ch];
+    *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
+}
+
+static void can_set_global_mode(int mode) {
+    /* set Global mode */
+    RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | (uint32_t)mode);
+    /* Wait to cahnge into Global XXXX mode */
+    while ((RSCAN0GSTS & 0x07) != (uint32_t)mode) {
+        __NOP();
+    }
+}
+
+static void can_set_channel_mode(uint32_t ch, int mode) {
+    __IO uint32_t *dmy_ctr;
+    __IO uint32_t *dmy_sts;
+
+    /* set Channel mode */
+    dmy_ctr = CTR_MATCH[ch];
+    *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | (uint32_t)mode);
+    /* Wait to cahnge into Channel XXXX mode */
+    dmy_sts = STS_MATCH[ch];
+    while ((*dmy_sts & 0x07) != (uint32_t)mode) {
+        __NOP();
+    }
+}
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/RZ_A1_Init.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/RZ_A1_Init.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/RZ_A1_Init.h	(revision 374)
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          RZ_A1_Init.h
+* $Rev: 531 $
+* $Date:: 2013-04-16 13:07:35 +0900#$
+* @brief         RZ_A1 Initialize
+******************************************************************************/
+
+#ifndef RZ_A1_INIT_H
+#define RZ_A1_INIT_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <stdbool.h>
+#include "iodefine.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+void    RZ_A1_SetSramWriteEnable(void);
+void    RZ_A1_InitClock(void);
+int     RZ_A1_IsClockMode0(void);
+void    RZ_A1_InitBus(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RZ_A1_INIT_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/cmsis_nvic.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/cmsis_nvic.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/cmsis_nvic.c	(revision 374)
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis.h"
+#include "irq_ctrl.h"
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    InterruptHandlerRegister(IRQn, (IRQHandler)vector);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn);
+    return vectors;
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/cmsis_nvic.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/cmsis_nvic.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/cmsis_nvic.h	(revision 374)
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/dev_drv.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/dev_drv.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/dev_drv.h	(revision 374)
@@ -0,0 +1,85 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name    : dev_drv.h
+* $Rev: 809 $
+* $Date:: 2014-04-09 15:06:36 +0900#$
+* Description  : Device driver header
+******************************************************************************/
+#ifndef DEV_DRV_H
+#define DEV_DRV_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ==== Arguments, Return values ==== */
+#define DEVDRV_SUCCESS      (0)     /* Success */
+#define DEVDRV_ERROR        (-1)    /* Failure */
+
+/* ==== Flags ==== */
+#define DEVDRV_FLAG_OFF     (0)     /* Flag OFF */
+#define DEVDRV_FLAG_ON      (1)     /* Flag ON  */
+
+/* ==== Channels ==== */
+typedef enum devdrv_ch
+{
+    DEVDRV_CH_0,            /* Channel 0  */
+    DEVDRV_CH_1,            /* Channel 1  */
+    DEVDRV_CH_2,            /* Channel 2  */
+    DEVDRV_CH_3,            /* Channel 3  */
+    DEVDRV_CH_4,            /* Channel 4  */
+    DEVDRV_CH_5,            /* Channel 5  */
+    DEVDRV_CH_6,            /* Channel 6  */
+    DEVDRV_CH_7,            /* Channel 7  */
+    DEVDRV_CH_8,            /* Channel 8  */
+    DEVDRV_CH_9,            /* Channel 9  */
+    DEVDRV_CH_10,           /* Channel 10 */
+    DEVDRV_CH_11,           /* Channel 11 */
+    DEVDRV_CH_12,           /* Channel 12 */
+    DEVDRV_CH_13,           /* Channel 13 */
+    DEVDRV_CH_14,           /* Channel 14 */
+    DEVDRV_CH_15            /* Channel 15 */
+} devdrv_ch_t;
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif  /* DEV_DRV_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/nvic_wrapper.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/nvic_wrapper.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/nvic_wrapper.c	(revision 374)
@@ -0,0 +1,230 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         nvic_wrapper.c
+* $Rev:  $
+* $Date:: $
+* @brief        Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis.h"
+#include "wdt_iodefine.h"
+#include "nvic_wrapper.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define PRIO_BITS            (7)   /* Set binary point to 0 in gic.c */
+#define WDT_WTCNT_WRITE      (0x5A00)
+#define WDT_WTCSR_WRITE      (0xA500)
+#define WDT_WRCSR_WOVF_WRITE (0xA500)
+#define WDT_WRCSR_RSTE_WRITE (0x5A00)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    GIC_SetBinaryPoint(PriorityGroup);
+}
+
+
+uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return GIC_GetBinaryPoint();
+}
+
+
+void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    GIC_EnableIRQ(IRQn);
+}
+
+
+void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    GIC_DisableIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    uint32_t pending;
+    
+    pending = GIC_GetIRQStatus(IRQn);
+    pending = (pending & 0x00000001);
+    
+    return pending;
+}
+
+
+void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    GIC_SetPendingIRQ(IRQn);
+}
+
+
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    GIC_ClearPendingIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    uint32_t active;
+    
+    active = GIC_GetIRQStatus(IRQn);
+    active = ((active >> 1) & 0x00000001);
+    
+    return active;
+}
+
+
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    GIC_SetPriority(IRQn, (priority << 3));
+}
+
+
+uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+    uint32_t priority_field;
+    
+    priority_field = GIC_GetPriority(IRQn);
+    priority_field = (priority_field >> 3);
+    return priority_field;
+}
+
+
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+    return (
+             ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+             ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+void NVIC_SystemReset(void)
+{
+    uint16_t reg;
+    uint8_t  dummy_read;
+    /* Use Watch Dog Timer to system reset */
+    
+    /* Set WT/IT bit of WTCSR to 1 = Watch Dog */
+    /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */
+    reg = (WDT_WTCSR_WRITE | 0x0058);
+    WDTWTCSR = reg;
+    
+    /* Clear Count reg */
+    reg = (WDT_WTCNT_WRITE | 0x0000);
+    WDTWTCNT = reg;
+    
+    /* Clear WOVF flag */
+    dummy_read = WDTWRCSR;
+    reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000));
+    WDTWRCSR = reg;
+    /* Enable Internal Reset */
+    reg = (WDT_WRCSR_RSTE_WRITE | 0x005F);
+    WDTWRCSR = reg;
+    
+    /* Watch Dog start */
+    reg = (WDT_WTCSR_WRITE | 0x0078);
+    WDTWTCSR = reg;
+    
+    while(1);                      /* wait Internal Reset */
+}
+
+/* ##################################    SysTick function  ############################################ */
+uint32_t SysTick_Config(uint32_t ticks)
+{
+    /* Not support this function */
+    /* Use mbed Ticker */
+    return (1);     /* impossible */
+}
+
+
+/* ##################################### Debug In/Output function ########################################### */
+uint32_t ITM_SendChar (uint32_t ch)
+{
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (ch);
+}
+
+
+int32_t ITM_ReceiveChar (void)
+{
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (-1);    /* no character available */
+}
+
+
+int32_t ITM_CheckChar (void)
+{
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (0);                                 /* no character available */
+}
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/nvic_wrapper.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/nvic_wrapper.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/nvic_wrapper.h	(revision 374)
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         nvic_wrapper.h
+* $Rev:  $
+* $Date:: $
+* @brief        Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+#ifndef NVIC_WRAPPER_H
+#define NVIC_WRAPPER_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/* NVIC functions */
+void     NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+uint32_t NVIC_GetPriorityGrouping(void);
+void     NVIC_EnableIRQ(IRQn_Type IRQn);
+void     NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void     NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void     NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetActive(IRQn_Type IRQn);
+void     NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+uint32_t NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
+void     NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+void     NVIC_SystemReset(void);
+/* SysTick function */
+uint32_t SysTick_Config(uint32_t ticks);
+/* Debug In/Output function */
+uint32_t ITM_SendChar (uint32_t ch);
+int32_t  ITM_ReceiveChar (void);
+int32_t  ITM_CheckChar (void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* NVIC_WRAPPER_H */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/r_typedefs.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/r_typedefs.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/r_typedefs.h	(revision 374)
@@ -0,0 +1,63 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : r_typedefs.h
+* $Rev: 788 $
+* $Date:: 2014-04-07 18:57:13 +0900#$
+* Description : basic type definition
+******************************************************************************/
+#ifndef R_TYPEDEFS_H
+#define R_TYPEDEFS_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+#if defined(__ARM_NEON__)
+#include <arm_neon.h>
+#endif /* __ARM_NEON__ */
+
+#ifndef float32_t
+typedef float               float32_t;
+#endif
+#ifndef float64_t
+typedef double              float64_t;
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef char                char_t;
+#ifndef bool_t
+typedef bool                bool_t;
+#endif
+typedef int                 int_t;
+typedef long double         float128_t;
+typedef signed long         long_t;
+typedef unsigned long       ulong_t;
+
+#endif /* R_TYPEDEFS_H */
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/rza_io_regrw.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/rza_io_regrw.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/rza_io_regrw.c	(revision 374)
@@ -0,0 +1,200 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : rza_io_regrw.c
+* $Rev: 1121 $
+* $Date:: 2014-08-06 17:09:53 +0900#$
+* Description : Low level register read/write
+*******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+
+#ifdef __CC_ARM
+#pragma arm section code   = "CODE_IO_REGRW"
+#pragma arm section rodata = "CONST_IO_REGRW"
+#pragma arm section rwdata = "DATA_IO_REGRW"
+#pragma arm section zidata = "BSS_IO_REGRW"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_8
+* Description  : IO register 8-bit write
+* Arguments    : volatile uint8_t * ioreg : IO register for writing
+*              :                          : Use register definition name of the
+*              :                          : iodefine.h
+*              : uint8_t write_value      : Write value for the IO register
+*              : uint8_t shift            : The number of left shifts to the 
+*              :                          : target bit
+*              : uint8_t mask             : Mask value for the IO register
+*              :                          : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask)
+{
+    uint8_t reg_value;
+
+    reg_value = *ioreg;                                         /* Read from register */
+    reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value       */
+    *ioreg    = reg_value;                                      /* Write to register  */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_16
+* Description  : IO register 16-bit write
+* Arguments    : volatile uint16_t * ioreg : IO register for writing
+*              :                           : Use register definition name of the
+*              :                           : iodefine.h
+*              : uint16_t write_value      : Write value for the IO register
+*              : uint16_t shift            : The number of left shifts to the 
+*              :                           : target bit
+*              : uint16_t mask             : Mask value for the IO register
+*              :                           : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask)
+{
+    uint16_t reg_value;
+
+    reg_value = *ioreg;                                         /* Read from register */
+    reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value       */
+    *ioreg    = reg_value;                                      /* Write to register  */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_32
+* Description  : IO register 32-bit write
+* Arguments    : volatile uint32_t * ioreg : IO register for writing
+*              :                           : Use register definition name of the
+*              :                           : iodefine.h
+*              : uint32_t write_value      : Write value for the IO register
+*              : uint32_t shift            : The number of left shifts to the 
+*              :                           : target bit
+*              : uint32_t mask             : Mask value for the IO register
+*              :                           : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
+{
+    uint32_t reg_value;
+
+    reg_value = *ioreg;                                         /* Read from register */
+    reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value       */
+    *ioreg    = reg_value;                                      /* Write to register  */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_8
+* Description  : IO register 8-bit read
+* Arguments    : volatile uint8_t * ioreg : IO register for reading
+*              :                          : Use register definition name of the 
+*              :                          : iodefine.h
+*              : uint8_t shift            : The number of right shifts to the 
+*              :                          : target bit
+*              : uint8_t mask             : Mask bit for the IO register
+*              :                          : (Target bit: "1")
+* Return Value : uint8_t : Value of the obtained target bit
+******************************************************************************/
+uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask)
+{
+    uint8_t reg_value;
+
+    reg_value = *ioreg;                         /* Read from register            */
+    reg_value = (reg_value & mask) >> shift;    /* Clear other bit and Bit shift */
+
+    return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_16
+* Description  : IO register 16-bit read
+* Arguments    : volatile uint16_t * ioreg : IO register for reading
+*              :                           : Use register definition name of the 
+*              :                           : iodefine.h
+*              : uint16_t shift            : The number of right shifts to the 
+*              :                           : target bit
+*              : uint16_t mask             : Mask bit for the IO register
+*              :                           : (Target bit: "1")
+* Return Value : uint16_t : Value of the obtained target bit
+******************************************************************************/
+uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask)
+{
+    uint16_t reg_value;
+
+    reg_value = *ioreg;                         /* Read from register            */
+    reg_value = (reg_value & mask) >> shift;    /* Clear other bit and Bit shift */
+
+    return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_32
+* Description  : IO register 32-bit read
+* Arguments    : volatile uint32_t * ioreg : IO register for reading
+*              :                           : Use register definition name of the 
+*              :                           : iodefine.h
+*              : uint32_t shift            : The number of right shifts to the 
+*              :                           : target bit
+*              : uint32_t mask             : Mask bit for the IO register
+*              :                           : (Target bit: "1")
+* Return Value : uint32_t : Value of the obtained target bit
+******************************************************************************/
+uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
+{
+    uint32_t reg_value;
+
+    reg_value = *ioreg;                         /* Read from register            */
+    reg_value = (reg_value & mask) >> shift;    /* Clear other bit and Bit shift */
+
+    return reg_value;
+}
+
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/rza_io_regrw.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/rza_io_regrw.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/rza_io_regrw.h	(revision 374)
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : rza_io_regrw.h
+* $Rev: 1135 $
+* $Date:: 2014-08-08 10:11:30 +0900#$
+* Description : Low level register read/write header
+*******************************************************************************/
+#ifndef RZA_IO_REGRW_H
+#define RZA_IO_REGRW_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+/* ==== includes each bit mask header ==== */
+#include "cpg_iobitmask.h"
+#include "intc_iobitmask.h"
+#include "bsc_iobitmask.h"
+#include "dmac_iobitmask.h"
+#include "mtu2_iobitmask.h"
+#include "ostm_iobitmask.h"
+#include "scif_iobitmask.h"
+#include "rspi_iobitmask.h"
+#include "riic_iobitmask.h"
+#include "usb_iobitmask.h"
+#include "spibsc_iobitmask.h"
+#include "gpio_iobitmask.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void     RZA_IO_RegWrite_8 (volatile uint8_t  * ioreg, uint8_t  write_value, uint8_t  shift, uint8_t  mask);
+void     RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask);
+void     RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
+uint8_t  RZA_IO_RegRead_8  (volatile uint8_t  * ioreg, uint8_t  shift, uint8_t  mask);
+uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask);
+uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* RZA_IO_REGRW_H */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/vfp_neon_push_pop.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/vfp_neon_push_pop.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/common/vfp_neon_push_pop.h	(revision 374)
@@ -0,0 +1,166 @@
+#ifndef __VFP_NEON_PUSH_POP_H__
+#define __VFP_NEON_PUSH_POP_H__
+
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#pragma push
+#pragma arm
+static __asm void __vfp_neon_push(void) {
+    ARM
+
+    VMRS    R2,FPSCR
+    STMDB   SP!,{R2,R4}         ; Push FPSCR, maintain 8-byte alignment
+    VSTMDB  SP!,{D0-D15}
+    VSTMDB  SP!,{D16-D31}
+    BX      LR
+}
+#pragma pop
+
+#pragma push
+#pragma arm
+static __asm void __vfp_neon_pop(void) {
+    ARM
+
+    VLDMIA  SP!,{D16-D31}
+    VLDMIA  SP!,{D0-D15}
+    LDR     R2,[SP]
+    VMSR    FPSCR,R2
+    ADD     SP,SP,#8
+    BX      LR
+}
+#pragma pop
+
+
+#pragma push
+#pragma arm
+static __asm void __vfp_push(void) {
+    ARM
+
+    VMRS    R2,FPSCR
+    STMDB   SP!,{R2,R4}         ; Push FPSCR, maintain 8-byte alignment
+    VSTMDB  SP!,{D0-D15}
+    BX      LR
+}
+#pragma pop
+
+#pragma push
+#pragma arm
+static __asm void __vfp_pop(void) {
+    ARM
+
+    VLDMIA  SP!,{D0-D15}
+    LDR     R2,[SP]
+    VMSR    FPSCR,R2
+    ADD     SP,SP,#8
+    BX      LR
+}
+#pragma pop
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+
+__arm static inline void __vfp_neon_push(void) {
+__asm(
+    "ARM \n"
+    "VMRS    R2,FPSCR \n"
+    "STMDB   SP!,{R2,R4} \n"    // Push FPSCR, maintain 8-byte alignment
+    "VSTMDB  SP!,{D0-D15} \n"
+    "VSTMDB  SP!,{D16-D31} \n"
+    "BX      lr \n" );
+}
+
+__arm static inline void __vfp_neon_pop(void) {
+__asm(
+    "ARM \n"
+    "VLDMIA  SP!,{D16-D31} \n"
+    "VLDMIA  SP!,{D0-D15} \n"
+    "LDR     R2,[SP] \n"
+    "VMSR    FPSCR,R2 \n"
+    "ADD     SP,SP,#8 \n"
+    "BX      lr \n" );
+}
+
+__arm static inline void __vfp_push(void) {
+__asm(
+    "ARM \n"
+    "VMRS    R2,FPSCR \n"
+    "STMDB   SP!,{R2,R4} \n"    // Push FPSCR, maintain 8-byte alignment
+    "VSTMDB  SP!,{D0-D15} \n"
+    "BX      lr \n" );
+}
+
+__arm static inline void __vfp_pop(void) {
+__asm(
+    "ARM \n"
+    "VLDMIA  SP!,{D0-D15} \n"
+    "LDR     R2,[SP] \n"
+    "VMSR    FPSCR,R2 \n"
+    "ADD     SP,SP,#8 \n"
+    "BX      lr \n" );
+}
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_push(void)
+{
+    __asm__ volatile (
+    ".ARM;"
+
+    "VMRS    R2,FPSCR;"
+    "STMDB   SP!,{R2,R4};"      // Push FPSCR, maintain 8-byte alignment
+    "VSTMDB  SP!,{D0-D15};"
+    "VSTMDB  SP!,{D16-D31};"
+    :
+    :
+    : );
+    return;
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_pop(void)
+{
+    __asm__ volatile (
+    ".ARM;"
+
+    "VLDMIA  SP!,{D16-D31};"
+    "VLDMIA  SP!,{D0-D15};"
+    "LDR     R2,[SP];"
+    "VMSR    FPSCR,R2;"
+    "ADD     SP,SP,#8;"
+    :
+    :
+    : );
+    return;
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_push(void)
+{
+    __asm__ volatile (
+    ".ARM;"
+
+    "VMRS    R2,FPSCR;"
+    "STMDB   SP!,{R2,R4};"      // Push FPSCR, maintain 8-byte alignment
+    "VSTMDB  SP!,{D0-D15};"
+    :
+    :
+    : );
+    return;
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_pop(void)
+{
+    __asm__ volatile (
+    ".ARM;"
+
+    "VLDMIA  SP!,{D0-D15};"
+    "LDR     R2,[SP];"
+    "VMSR    FPSCR,R2;"
+    "ADD     SP,SP,#8;"
+    :
+    :
+    : );
+    return;
+}
+
+#endif
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/ethernet_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/ethernet_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/ethernet_api.c	(revision 374)
@@ -0,0 +1,794 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "mbed_toolchain.h"
+#include "mbed_error.h"
+#include "iodefine.h"
+#include "ethernetext_api.h"
+
+#if DEVICE_ETHERNET
+
+/* Descriptor info */
+#define SIZE_OF_BUFFER          (1600)     /* Must be an integral multiple of 32 */
+#define MAX_SEND_SIZE           (1514)
+/* Ethernet Descriptor Value Define */
+#define TD0_TFP_TOP_BOTTOM      (0x30000000)
+#define TD0_TACT                (0x80000000)
+#define TD0_TDLE                (0x40000000)
+#define RD0_RACT                (0x80000000)
+#define RD0_RDLE                (0x40000000)
+#define RD0_RFE                 (0x08000000)
+#define RD0_RCSE                (0x04000000)
+#define RD0_RFS                 (0x03FF0000)
+#define RD0_RCS                 (0x0000FFFF)
+#define RD0_RFS_RFOF            (0x02000000)
+#define RD0_RFS_RUAF            (0x00400000)
+#define RD0_RFS_RRF             (0x00100000)
+#define RD0_RFS_RTLF            (0x00080000)
+#define RD0_RFS_RTSF            (0x00040000)
+#define RD0_RFS_PRE             (0x00020000)
+#define RD0_RFS_CERF            (0x00010000)
+#define RD0_RFS_ERROR           (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
+                                 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
+#define RD1_RDL_MSK             (0x0000FFFF)
+/* PHY Register */
+#define BASIC_MODE_CONTROL_REG  (0)
+#define BASIC_MODE_STATUS_REG   (1)
+#define PHY_IDENTIFIER1_REG     (2)
+#define PHY_IDENTIFIER2_REG     (3)
+#define PHY_SP_CTL_STS_REG      (31)
+/* MII management interface access */
+#define PHY_ADDR                (0)        /* Confirm the pin connection of the PHY-LSI */
+#define PHY_ST                  (1)
+#define PHY_WRITE               (1)
+#define PHY_READ                (2)
+#define MDC_WAIT                (6)        /* 400ns/4 */
+#define BASIC_STS_MSK_LINK      (0x0004)   /* Link Status */
+#define BASIC_STS_MSK_AUTO_CMP  (0x0020)   /* Auto-Negotiate Complete */
+#define M_PHY_ID                (0xFFFFFFF0)
+#define PHY_ID_LAN8710A         (0x0007C0F0)
+/* ETHERPIR0 */
+#define PIR0_MDI                (0x00000008)
+#define PIR0_MDO                (0x00000004)
+#define PIR0_MMD                (0x00000002)
+#define PIR0_MDC                (0x00000001)
+#define PIR0_MDC_HIGH           (0x00000001)
+#define PIR0_MDC_LOW            (0x00000000)
+/* ETHEREDRRR0 */
+#define EDRRR0_RR               (0x00000001)
+/* ETHEREDTRR0 */
+#define EDTRR0_TR               (0x00000003)
+/* software wait */
+#define LOOP_100us              (6700)     /* Loop counter for software wait  6666=100us/((1/400MHz)*6cyc) */
+
+#define EDMAC_EESIPR_INI_RECV   (0x0205001F)    /* 0x02000000 : Detect reception suspended */
+                                                /* 0x00040000 : Detect frame reception */
+                                                /* 0x00010000 : Receive FIFO overflow */
+                                                /* 0x00000010 : Residual bit frame reception */
+                                                /* 0x00000008 : Long frame reception */
+                                                /* 0x00000004 : Short frame reception */
+                                                /* 0x00000002 : PHY-LSI reception error */
+                                                /* 0x00000001 : Receive frame CRC error */
+#define EDMAC_EESIPR_INI_EtherC (0x00400000)    /* 0x00400000 : E-MAC status register */
+
+void ethernet_address(char *);
+void ethernet_set_link(int, int);
+
+
+/* Send descriptor */
+typedef struct tag_edmac_send_desc {
+    uint32_t    td0;
+    uint32_t    td1;
+    uint8_t     *td2;
+    uint32_t    padding4;
+} edmac_send_desc_t;
+
+/* Receive descriptor */
+typedef struct tag_edmac_recv_desc {
+    uint32_t    rd0;
+    uint32_t    rd1;
+    uint8_t     *rd2;
+    uint32_t    padding4;
+} edmac_recv_desc_t;
+
+/* memory */
+/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
+/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
+#if defined(__ICCARM__)
+#pragma data_alignment=16
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+                                 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+                                 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+                                 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]  //16 bytes aligned!
+                                 @ ".mirrorram";
+#else
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+                                 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+                                 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+                                 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
+                                 __attribute((section("NC_BSS"),aligned(16)));  //16 bytes aligned!
+#endif
+static int32_t            rx_read_offset;   /* read offset */
+static int32_t            tx_wite_offset;   /* write offset */
+static uint32_t           send_top_index;
+static uint32_t           recv_top_index;
+static int32_t            Interrupt_priority;
+static edmac_send_desc_t  *p_eth_desc_dsend = NULL;
+static edmac_recv_desc_t  *p_eth_desc_drecv = NULL;
+static edmac_recv_desc_t  *p_recv_end_desc  = NULL;
+static ethernetext_cb_fnc *p_recv_cb_fnc    = NULL;
+static char               mac_addr[6]       = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
+static uint32_t           phy_id            = 0;
+static uint32_t           start_stop        = 1;  /* 0:stop  1:start */
+static uint32_t           tsu_ten_tmp       = 0;
+
+volatile struct st_ether_from_tsu_adrh0*  ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+
+/* function */
+static void lan_reg_reset(void);
+static void lan_desc_create(void);
+static void lan_reg_set(int32_t link);
+static uint16_t phy_reg_read(uint16_t reg_addr);
+static void phy_reg_write(uint16_t reg_addr, uint16_t data);
+static void mii_preamble(void);
+static void mii_cmd(uint16_t reg_addr, uint32_t option);
+static void mii_reg_read(uint16_t *data);
+static void mii_reg_write(uint16_t data);
+static void mii_z(void);
+static void mii_write_1(void);
+static void mii_write_0(void);
+static void set_ether_pir(uint32_t set_data);
+static void wait_100us(int32_t wait_cnt);
+
+
+int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
+    int32_t  i;
+    uint16_t val;
+
+    CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74);  /* enable ETHER clock */
+
+    /* P4_2(PHY Reset) */
+    GPIOP4      &= ~0x0004;         /* Outputs low level */
+    GPIOPMC4    &= ~0x0004;         /* Port mode */
+    GPIOPM4     &= ~0x0004;         /* Output mode */
+
+    /* GPIO P1  P1_14(ET_COL) */
+    GPIOPMC1    |=  0x4000;
+    GPIOPFCAE1  &= ~0x4000;
+    GPIOPFCE1   |=  0x4000;
+    GPIOPFC1    |=  0x4000;
+
+    /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
+    GPIOPMC3    |=  0x0079;
+    GPIOPFCAE3  &= ~0x0079;
+    GPIOPFCE3   &= ~0x0079;
+    GPIOPFC3    |=  0x0079;
+    GPIOPIPC3   |=  0x0079;
+
+    /* P5_9(ET_MDC) */
+    GPIOPMC5    |=  0x0200;
+    GPIOPFCAE5  &= ~0x0200;
+    GPIOPFCE5   &= ~0x0200;
+    GPIOPFC5    |=  0x0200;
+    GPIOPIPC5   |=  0x0200;
+
+    /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
+    /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
+    GPIOPMC10   |=  0x0FFE;
+    GPIOPFCAE10 &= ~0x0FFE;
+    GPIOPFCE10  |=  0x0FFE;
+    GPIOPFC10   |=  0x0FFE;
+    GPIOPIPC10  |=  0x0FFE;
+
+    /* Resets the E-MAC,E-DMAC */
+    lan_reg_reset();
+
+    /* PHY Reset */
+    GPIOP4      &= ~0x0004;         /* P4_2 Outputs low level */
+    wait_100us(250);                /* 25msec */
+    GPIOP4      |=  0x0004;         /* P4_2 Outputs high level */
+    wait_100us(100);                /* 10msec */
+
+    /* Resets the PHY-LSI */
+    phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
+    for (i = 10000; i > 0; i--) {
+        val = phy_reg_read(BASIC_MODE_CONTROL_REG);
+        if (((uint32_t)val & 0x8000uL) == 0) {
+            break;                  /* Reset complete */
+        }
+    }
+
+    phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
+           |  (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
+
+    Interrupt_priority = p_ethcfg->int_priority;
+    p_recv_cb_fnc      = p_ethcfg->recv_cb;
+    start_stop         = 1;
+
+    if (p_ethcfg->ether_mac != NULL) {
+        (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
+    } else {
+        ethernet_address(mac_addr); /* Get MAC Address */
+    }
+
+    return 0;
+}
+
+void ethernetext_start_stop(int32_t mode) {
+    if (mode == 1) {
+        /* start */
+        ETHEREDTRR0 |= EDTRR0_TR;
+        ETHEREDRRR0 |= EDRRR0_RR;
+        start_stop   = 1;
+    } else {
+        /* stop */
+        ETHEREDTRR0 &= ~EDTRR0_TR;
+        ETHEREDRRR0 &= ~EDRRR0_RR;
+        start_stop   = 0;
+    }
+}
+
+int ethernetext_chk_link_mode(void) {
+    int32_t  link;
+    uint16_t data;
+
+    if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
+        data = phy_reg_read(PHY_SP_CTL_STS_REG);
+        switch (((uint32_t)data >> 2) & 0x00000007) {
+            case 0x0001:
+                link = HALF_10M;
+                break;
+            case 0x0005:
+                link = FULL_10M;
+                break;
+            case 0x0002:
+                link = HALF_TX;
+                break;
+            case 0x0006:
+                link = FULL_TX;
+                break;
+            default:
+                link = NEGO_FAIL;
+                break;
+        }
+    } else {
+        link = NEGO_FAIL;
+    }
+
+    return link;
+}
+
+void ethernetext_set_link_mode(int32_t link) {
+    lan_reg_reset();            /* Resets the E-MAC,E-DMAC */
+    lan_desc_create();          /* Initialize of buffer memory */
+    lan_reg_set(link);          /* E-DMAC, E-MAC initialization */
+}
+
+void ethernetext_add_multicast_group(const uint8_t *addr) {
+    uint32_t cnt;
+    uint32_t tmp_data_h;
+    uint32_t tmp_data_l;
+
+    if (tsu_ten_tmp == 0xFFFFFFFF) {
+        ethernetext_set_all_multicast(1);
+    } else {
+        tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]);
+        tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]);
+
+        for (cnt = 0; cnt < 32; cnt++) {
+            if ((tsu_ten_tmp & (0x80000000 >> cnt)) == 0) {
+                while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
+                    ;
+                }
+                ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = tmp_data_h;
+                while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
+                    ;
+                }
+                ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = tmp_data_l;
+                if ((ETHERECMR0 & 0x00002000) != 0) {
+                    ETHERTSU_TEN |= (0x80000000 >> cnt);
+                }
+                tsu_ten_tmp  |= (0x80000000 >> cnt);
+                break;
+            }
+        }
+    }
+}
+
+void ethernetext_remove_multicast_group(const uint8_t *addr) {
+    uint32_t cnt;
+    uint32_t tmp_data_h;
+    uint32_t tmp_data_l;
+
+    tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]);
+    tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]);
+
+    for (cnt = 0; cnt< 32; cnt++) {
+        if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0  == tmp_data_h) && 
+            (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0  == tmp_data_l)) {
+            while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
+                ;
+            }
+            ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = 0;
+            while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
+                ;
+            }
+            ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = 0;
+
+            ETHERTSU_TEN &= ~(0x80000000 >> cnt);
+            tsu_ten_tmp  &= ~(0x80000000 >> cnt);
+            break;
+        }
+    }
+}
+
+void ethernetext_set_all_multicast(int all) {
+    if (all != 0) {
+        ETHERECMR0 &= ~(0x00002000);
+        ETHERTSU_TEN = 0x00000000;
+    } else {
+        ETHERECMR0 |= 0x00002000;
+        ETHERTSU_TEN = tsu_ten_tmp;
+    }
+}
+
+
+int ethernet_init() {
+    ethernet_cfg_t ethcfg;
+
+    ethcfg.int_priority = 5;
+    ethcfg.recv_cb      = NULL;
+    ethcfg.ether_mac    = NULL;
+    ethernetext_init(&ethcfg);
+    ethernet_set_link(-1, 0);   /* Auto-Negotiation */
+
+    return 0;
+}
+
+void ethernet_free() {
+    ETHERARSTR |= 0x00000001;            /* ETHER software reset */
+    CPGSTBCR7  |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
+}
+
+int ethernet_write(const char *data, int slen) {
+    edmac_send_desc_t *p_send_desc;
+    int32_t           copy_size;
+
+    if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
+     || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
+        copy_size = 0;
+    } else {
+        p_send_desc = &p_eth_desc_dsend[send_top_index];   /* Current descriptor */
+        if ((p_send_desc->td0 & TD0_TACT) != 0) {
+            copy_size = 0;
+        } else {
+            copy_size = MAX_SEND_SIZE - tx_wite_offset;
+            if (copy_size > slen) {
+                copy_size = slen;
+            }
+            (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
+            tx_wite_offset += copy_size;
+        }
+    }
+
+    return copy_size;
+}
+
+int ethernet_send() {
+    edmac_send_desc_t *p_send_desc;
+    int32_t           ret;
+
+    if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
+        ret = 0;
+    } else {
+        /* Transfer 1 frame */
+        p_send_desc = &p_eth_desc_dsend[send_top_index];   /* Current descriptor */
+
+        /* Sets the frame length */
+        p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
+        tx_wite_offset   = 0;
+
+        /* Sets the transmit descriptor to transmit again */
+        p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
+        p_send_desc->td0 |= TD0_TACT;
+        if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
+            ETHEREDTRR0 |= EDTRR0_TR;
+        }
+
+        /* Update the current descriptor */
+        send_top_index++;
+        if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
+            send_top_index = 0;
+        }
+        ret = 1;
+    }
+
+    return ret;
+}
+
+int ethernet_receive() {
+    edmac_recv_desc_t *p_recv_desc;
+    int32_t           receive_size = 0;
+
+    if (p_eth_desc_drecv != NULL) {
+        if (p_recv_end_desc != NULL) {
+            /* Sets the receive descriptor to receive again */
+            p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
+            p_recv_end_desc->rd0 |= RD0_RACT;
+            if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
+                ETHEREDRRR0 |= EDRRR0_RR;
+            }
+            p_recv_end_desc = NULL;
+        }
+
+        p_recv_desc = &p_eth_desc_drecv[recv_top_index];   /* Current descriptor */
+        if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
+            /* Receives 1 frame */
+            if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
+                /* Receive frame error */
+                /* Sets the receive descriptor to receive again */
+                p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
+                p_recv_desc->rd0 |= RD0_RACT;
+                if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
+                    ETHEREDRRR0 |= EDRRR0_RR;
+                }
+            } else {
+                /* Copies the received frame */
+                rx_read_offset  = 0;
+                p_recv_end_desc = p_recv_desc;
+                receive_size    = (p_recv_desc->rd1 & RD1_RDL_MSK);    /* number of bytes received */
+            }
+
+            /* Update the current descriptor */
+            recv_top_index++;
+            if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
+                recv_top_index = 0;
+            }
+        }
+    }
+
+    return receive_size;
+}
+
+int ethernet_read(char *data, int dlen) {
+    edmac_recv_desc_t *p_recv_desc = p_recv_end_desc;                   /* Read top descriptor */
+    int32_t           copy_size;
+
+    if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
+        copy_size = 0;
+    } else {
+        copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
+        if (copy_size > dlen) {
+            copy_size = dlen;
+        }
+        (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
+        rx_read_offset += copy_size;
+    }
+
+    return copy_size;
+}
+
+void ethernet_address(char *mac) {
+    if (mac != NULL) {
+        mbed_mac_address(mac); /* Get MAC Address */
+    }
+}
+
+int ethernet_link(void) {
+    int32_t  ret;
+    uint16_t data;
+
+    data = phy_reg_read(BASIC_MODE_STATUS_REG);
+    if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
+        ret = 1;
+    } else {
+        ret = 0;
+    }
+
+    return ret;
+}
+
+void ethernet_set_link(int speed, int duplex) {
+    uint16_t data;
+    int32_t  i;
+    int32_t  link;
+
+    if ((speed < 0) || (speed > 1)) {
+        data = 0x1000;      /* Auto-Negotiation Enable */
+        phy_reg_write(BASIC_MODE_CONTROL_REG, data);
+        for (i = 0; i < 1000; i++) {
+            data = phy_reg_read(BASIC_MODE_STATUS_REG);
+            if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
+                break;
+            }
+            wait_100us(10);
+        }
+    } else {
+        data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
+        phy_reg_write(BASIC_MODE_CONTROL_REG, data);
+        wait_100us(1);
+    }
+
+    link = ethernetext_chk_link_mode();
+    ethernetext_set_link_mode(link);
+}
+
+void INT_Ether(void) {
+    uint32_t stat_edmac;
+    uint32_t stat_etherc;
+
+    /* Clear the interrupt request flag */
+    stat_edmac = (ETHEREESR0 & ETHEREESIPR0);       /* Targets are restricted to allowed interrupts */
+    ETHEREESR0 = stat_edmac;
+    /* Reception-related */
+    if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
+        if (p_recv_cb_fnc != NULL) {
+            p_recv_cb_fnc();
+        }
+    }
+    /* E-MAC-related */
+    if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
+        /* Clear the interrupt request flag */
+        stat_etherc = (ETHERECSR0 & ETHERECSIPR0);  /* Targets are restricted to allowed interrupts */
+        ETHERECSR0  = stat_etherc;
+    }
+}
+
+static void lan_reg_reset(void) {
+    volatile int32_t j = 400;    /* Wait for B dia 256 cycles  ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
+
+    ETHERARSTR      |= 0x00000001;      /* ETHER software reset */
+    while (j--) {
+        /* Do Nothing */
+    }
+
+    ETHEREDSR0      |= 0x00000003;      /* E-DMAC software reset */
+    ETHEREDMR0      |= 0x00000003;      /* Set SWRR and SWRT simultaneously */
+
+    /* Check clear software reset */
+    while ((ETHEREDMR0 & 0x00000003) != 0) {
+        /* Do Nothing */
+    }
+}
+
+static void lan_desc_create(void) {
+    int32_t i;
+    uint8_t *p_memory_top;
+
+    (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
+    p_memory_top = ethernet_nc_memory;
+
+    /* Descriptor area configuration */
+    p_eth_desc_dsend  = (edmac_send_desc_t *)p_memory_top;
+    p_memory_top     += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
+    p_eth_desc_drecv  = (edmac_recv_desc_t *)p_memory_top;
+    p_memory_top     += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
+
+    /* Transmit descriptor */
+    for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
+        p_eth_desc_dsend[i].td2  = p_memory_top;                     /* TD2 TBA */
+        p_memory_top            += SIZE_OF_BUFFER;
+        p_eth_desc_dsend[i].td1  = 0;                                /* TD1 TDL */
+        p_eth_desc_dsend[i].td0  = TD0_TFP_TOP_BOTTOM;               /* TD0:1frame/1buf1buf, transmission disabled */
+    }
+    p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE;                         /* Set the last descriptor */
+
+    /* Receive descriptor */
+    for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
+        p_eth_desc_drecv[i].rd2  = p_memory_top;                     /* RD2 RBA */
+        p_memory_top            += SIZE_OF_BUFFER;
+        p_eth_desc_drecv[i].rd1  = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
+        p_eth_desc_drecv[i].rd0  = RD0_RACT;                         /* RD0:reception enabled */
+    }
+    p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE;                         /* Set the last descriptor */
+
+    /* Initialize descriptor management information */
+    send_top_index  = 0;
+    recv_top_index  = 0;
+    rx_read_offset  = 0;
+    tx_wite_offset  = 0;
+    p_recv_end_desc = NULL;
+}
+
+static void lan_reg_set(int32_t link) {
+    int32_t prm = link & PROMISCUOUS_MODE;
+    link &= ~PROMISCUOUS_MODE;
+
+    /* MAC address setting */
+    ETHERMAHR0      = ((uint8_t)mac_addr[0] << 24)
+                    | ((uint8_t)mac_addr[1] << 16)
+                    | ((uint8_t)mac_addr[2] << 8)
+                    |  (uint8_t)mac_addr[3];
+    ETHERMALR0      = ((uint8_t)mac_addr[4] << 8)
+                    |  (uint8_t)mac_addr[5];
+
+    /* E-DMAC */
+    ETHERTDLAR0     = (uint32_t)&p_eth_desc_dsend[0];
+    ETHERRDLAR0     = (uint32_t)&p_eth_desc_drecv[0];
+    ETHERTDFAR0     = (uint32_t)&p_eth_desc_dsend[0];
+    ETHERRDFAR0     = (uint32_t)&p_eth_desc_drecv[0];
+    ETHERTDFXR0     = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
+    ETHERRDFXR0     = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
+    ETHERTDFFR0    |=  0x00000001;      /* TDLF  Transmit Descriptor Queue Last Flag : Last descriptor (1) */
+    ETHERRDFFR0    |=  0x00000001;      /* RDLF  Receive Descriptor Queue Last Flag : Last descriptor (1) */
+    ETHEREDMR0     |=  0x00000040;      /* Little endian */
+    ETHERTRSCER0   &= ~0x0003009F;      /* All clear */
+    ETHERTFTR0     &= ~0x000007FF;      /* TFT[10:0]  Transmit FIFO Threshold : Store and forward modes (H'000) */
+    ETHERFDR0      |=  0x00000707;      /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
+    ETHERRMCR0     |=  0x00000001;      /* RNC  Receive Enable Control : Continuous reception enabled (1) */
+    ETHERFCFTR0    &= ~0x001F00FF;
+    ETHERFCFTR0    |=  0x00070007;
+    ETHERRPADIR0   &= ~0x001FFFFF;      /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
+
+    /* E-MAC */
+    ETHERECMR0     &= ~0x04BF2063;      /* All clear */
+    ETHERRFLR0     &= ~0x0003FFFF;      /* RFL[17:0]  Receive Frame Length : 1518 bytes (H'00000) */
+    ETHERAPR0      &= ~0x0000FFFF;      /* AP[15:0]   Automatic PAUSE : Flow control is disabled (H'0000) */
+    ETHERMPR0      &= ~0x0000FFFF;      /* MP[15:0]   Manual PAUSE : Flow control is disabled (H'0000) */
+    ETHERTPAUSER0  &= ~0x0000FFFF;      /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
+    ETHERCSMR      &= ~0xC000003F;      /* The result of checksum is not written back to the receive descriptor */
+    if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
+        ETHERECMR0 |= 0x00000002;       /* Set to full-duplex mode */
+    } else {
+        ETHERECMR0 &= ~0x00000002;      /* Set to half-duplex mode */
+    }
+    ETHERECMR0     |=  0x00002000;      /* MCT = 1 */
+
+    /* Interrupt-related */
+    if (p_recv_cb_fnc != NULL) {
+        ETHEREESR0     |=  0xFF7F009F;                     /* Clear all status (by writing 1) */
+        ETHEREESIPR0   |=  0x00040000;                     /* FR  Frame Reception (1) */
+        ETHERECSR0     |=  0x00000011;                     /* Clear all status (clear by writing 1) */
+        ETHERECSIPR0   &= ~0x00000011;                     /* PFROIP Disable, ICDIP Disable */
+        /*InterruptHandlerRegister(ETHERI_IRQn, INT_Ether);  /* Ethernet interrupt handler registration */
+        GIC_SetPriority(ETHERI_IRQn, Interrupt_priority);  /* Ethernet interrupt priority */
+        GIC_SetConfiguration(ETHERI_IRQn, 1);
+        GIC_EnableIRQ(ETHERI_IRQn);                        /* Enables the E-DMAC interrupt */
+    }
+
+    if (prm) {
+        ETHERECMR0     |=  0x00000001;  /* Promiscuous Mode */
+    }
+
+    ETHERECMR0     |=  0x00000060;      /* RE Enable, TE Enable */
+
+    /* Enable transmission/reception */
+    if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
+        ETHEREDRRR0 |= 0x00000001;       /* RR */
+    }
+}
+
+static uint16_t phy_reg_read(uint16_t reg_addr) {
+    uint16_t data;
+
+    mii_preamble();
+    mii_cmd(reg_addr, PHY_READ);
+    mii_z();
+    mii_reg_read(&data);
+    mii_z();
+
+    return data;
+}
+
+static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
+    mii_preamble();
+    mii_cmd(reg_addr, PHY_WRITE);
+    mii_write_1();
+    mii_write_0();
+    mii_reg_write(data);
+    mii_z();
+}
+
+static void mii_preamble(void) {
+    int32_t i = 32;
+
+    for (i = 32; i > 0; i--) {
+        /* 1 is output via the MII (Media Independent Interface) block. */
+        mii_write_1();
+    }
+}
+
+static void mii_cmd(uint16_t reg_addr, uint32_t option) {
+    int32_t  i;
+    uint16_t data = 0;
+
+    data |= (PHY_ST << 14);             /* ST code      */
+    data |= (option << 12);             /* OP code      */
+    data |= (PHY_ADDR << 7);            /* PHY Address  */
+    data |= (uint16_t)(reg_addr << 2);  /* Reg Address  */
+    for (i = 14; i > 0; i--) {
+        if ((data & 0x8000) == 0) {
+            mii_write_0();
+        } else {
+            mii_write_1();
+        }
+        data <<= 1;
+    }
+}
+
+static void mii_reg_read(uint16_t *data) {
+    int32_t  i;
+    uint16_t reg_data = 0;
+
+    /* Data are read in one bit at a time */
+    for (i = 16; i > 0; i--) {
+        set_ether_pir(PIR0_MDC_LOW);
+        set_ether_pir(PIR0_MDC_HIGH);
+        reg_data <<= 1;
+        reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3);  /* MDI read */
+        set_ether_pir(PIR0_MDC_HIGH);
+        set_ether_pir(PIR0_MDC_LOW);
+    }
+    *data = reg_data;
+}
+
+static void mii_reg_write(uint16_t data) {
+    int32_t i;
+
+    /* Data are written one bit at a time */
+    for (i = 16; i > 0; i--) {
+        if ((data & 0x8000) == 0) {
+            mii_write_0();
+        } else {
+            mii_write_1();
+        }
+        data <<= 1;
+    }
+}
+
+static void mii_z(void) {
+    set_ether_pir(PIR0_MDC_LOW);
+    set_ether_pir(PIR0_MDC_HIGH);
+    set_ether_pir(PIR0_MDC_HIGH);
+    set_ether_pir(PIR0_MDC_LOW);
+}
+
+static void mii_write_1(void) {
+    set_ether_pir(PIR0_MDO | PIR0_MMD);
+    set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MDO | PIR0_MMD);
+}
+
+static void mii_write_0(void) {
+    set_ether_pir(PIR0_MMD);
+    set_ether_pir(PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MMD);
+}
+
+static void set_ether_pir(uint32_t set_data) {
+    int32_t i;
+
+    for (i = MDC_WAIT; i > 0; i--) {
+        ETHERPIR0 = set_data;
+    }
+}
+
+static void wait_100us(int32_t wait_cnt) {
+    volatile int32_t j = LOOP_100us * wait_cnt;
+
+    while (--j) {
+        /* Do Nothing */
+    }
+}
+#endif /* DEVICE_ETHERNET */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/ethernetext_api.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/ethernetext_api.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/ethernetext_api.h	(revision 374)
@@ -0,0 +1,37 @@
+
+#ifndef ETHERNETEXT_H
+#define ETHERNETEXT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* PHY link mode */
+#define NEGO_FAIL               (0)
+#define HALF_10M                (1)
+#define FULL_10M                (2)
+#define HALF_TX                 (3)
+#define FULL_TX                 (4)
+
+#define PROMISCUOUS_MODE        (0x80000000)
+
+typedef void (ethernetext_cb_fnc)(void);
+
+typedef struct tag_ethernet_cfg {
+    int                  int_priority;
+    ethernetext_cb_fnc   *recv_cb;
+    char                 *ether_mac;
+} ethernet_cfg_t;
+
+extern int ethernetext_init(ethernet_cfg_t *p_ethcfg);
+extern void ethernetext_start_stop(int32_t mode);
+extern int ethernetext_chk_link_mode(void);
+extern void ethernetext_set_link_mode(int32_t link);
+extern void ethernetext_add_multicast_group(const uint8_t *addr);
+extern void ethernetext_remove_multicast_group(const uint8_t *addr);
+extern void ethernetext_set_all_multicast(int all);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/flash_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/flash_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/flash_api.c	(revision 374)
@@ -0,0 +1,749 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+#include "iodefine.h"
+#include "spibsc_iobitmask.h"
+#include "spibsc.h"
+#include "mbed_drv_cfg.h"
+
+/* ---- serial flash command ---- */
+#define SFLASHCMD_SECTOR_ERASE       (0x20u)    /* SE     3-byte address(1bit)             */
+#define SFLASHCMD_PAGE_PROGRAM       (0x02u)    /* PP     3-byte address(1bit), data(1bit) */
+#define SFLASHCMD_READ_STATUS_REG    (0x05u)    /* RDSR                         data(1bit) */
+#define SFLASHCMD_WRITE_ENABLE       (0x06u)    /* WREN                                    */
+/* ---- serial flash register definitions ---- */
+#define STREG_BUSY_BIT               (0x01u)    /* SR.[0]BUSY Erase/Write In Progress (RO) */
+
+/* Definition of the base address for the MMU translation table */
+#if defined(__CC_ARM) || defined(__GNUC__)
+extern uint32_t Image$$TTB$$ZI$$Base;
+#define TTB         ((uint32_t)&Image$$TTB$$ZI$$Base)   /* using linker symbol */
+#elif defined(__ICCARM__)
+#pragma section="TTB"
+#define TTB         ((uint32_t)__section_begin("TTB"))
+#endif
+
+typedef struct {
+    uint32_t cdb;       /* bit-width : command */
+    uint32_t ocdb;      /* bit-width : optional command */
+    uint32_t adb;       /* bit-width : address */
+    uint32_t opdb;      /* bit-width : option data */
+    uint32_t spidb;     /* bit-width : data */
+
+    uint32_t cde;       /* Enable : command */
+    uint32_t ocde;      /* Enable : optional command */
+    uint32_t ade;       /* Enable : address */
+    uint32_t opde;      /* Enable : option data */
+    uint32_t spide;     /* Enable : data */
+
+    uint32_t sslkp;     /* SPBSSL level */
+    uint32_t spire;     /* Enable data read */
+    uint32_t spiwe;     /* Enable data write */
+
+    uint32_t dme;       /* Enable : dummy cycle */
+
+    uint32_t addre;     /* DDR enable : address  */
+    uint32_t opdre;     /* DDR enable : option data */
+    uint32_t spidre;    /* DDR enable : data */
+
+    uint8_t dmdb;       /* bit-width : dummy cycle */
+    uint8_t dmcyc;      /* number of dummy cycles */
+
+    uint8_t  cmd;       /* command */
+    uint8_t  ocmd;      /* optional command */
+    uint32_t addr;      /* address */
+    uint8_t  opd[4];    /* option data 3/2/1/0 */
+    uint32_t smrdr[2];  /* read data */
+    uint32_t smwdr[2];  /* write data */
+} st_spibsc_spimd_reg_t;
+
+/*  SPI Multi-I/O bus address space address definitions */
+#define SPIBSC_ADDR_START  (0x18000000uL)
+#define SPIBSC_ADDR_END    (0x1BFFFFFFuL)
+
+typedef struct {
+    uint32_t b0             : 1 ;       /* bit 0        : -         (0)                                   */
+    uint32_t b1             : 1 ;       /* bit 1        : -         (1)                                   */
+    uint32_t B              : 1 ;       /* bit 2        : B         Memory region attribute bit           */
+    uint32_t C              : 1 ;       /* bit 3        : C         Memory region attribute bit           */
+    uint32_t XN             : 1 ;       /* bit 4        : XN        Execute-never bit                     */
+    uint32_t Domain         : 4 ;       /* bit 8-5      : Domain    Domain field                          */
+    uint32_t b9             : 1 ;       /* bit 9        : IMP       IMPLEMENTATION DEFINED                */
+    uint32_t AP1_0          : 2 ;       /* bit 11-10    : AP[1:0]   Access permissions bits:bit1-0        */
+    uint32_t TEX            : 3 ;       /* bit 14-12    : TEX[2:0]  Memory region attribute bits          */
+    uint32_t AP2            : 1 ;       /* bit 15       : AP[2]     Access permissions bits:bit2          */
+    uint32_t S              : 1 ;       /* bit 16       : S         Shareable bit                         */
+    uint32_t nG             : 1 ;       /* bit 17       : nG        Not global bit                        */
+    uint32_t b18            : 1 ;       /* bit 18       : -         (0)                                   */
+    uint32_t NS             : 1 ;       /* bit 19       : NS        Non-secure bit                        */
+    uint32_t base_addr      : 12;       /* bit 31-20    : PA[31:20] PA(physical address) bits:bit31-20    */
+} mmu_ttbl_desc_section_t;
+
+static mmu_ttbl_desc_section_t desc_tbl[(SPIBSC_ADDR_END >> 20) - (SPIBSC_ADDR_START >> 20) + 1];
+static volatile struct st_spibsc*  SPIBSC = &SPIBSC0;
+static st_spibsc_spimd_reg_t spimd_reg;
+
+#if defined(__ICCARM__)
+#define RAM_CODE_SEC    __ramfunc
+#else
+#define RAM_CODE_SEC    __attribute__((section("RAM_CODE")))
+#endif
+
+/* Global function for optimization */
+RAM_CODE_SEC int32_t _sector_erase(uint32_t addr);
+RAM_CODE_SEC int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size);
+
+static RAM_CODE_SEC int32_t write_enable(void);
+static RAM_CODE_SEC int32_t busy_wait(void);
+static RAM_CODE_SEC int32_t read_register(uint8_t cmd, uint8_t * status);
+static RAM_CODE_SEC int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size);
+static RAM_CODE_SEC void spi_mode(void);
+static RAM_CODE_SEC void ex_mode(void);
+static RAM_CODE_SEC void clear_spimd_reg(st_spibsc_spimd_reg_t * regset);
+static RAM_CODE_SEC int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset);
+static RAM_CODE_SEC uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
+static RAM_CODE_SEC void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
+static RAM_CODE_SEC void change_mmu_ttbl_spibsc(uint32_t type);
+static RAM_CODE_SEC void spibsc_stop(void);
+static RAM_CODE_SEC void cache_control(void);
+
+int32_t flash_init(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    int32_t ret;
+
+    core_util_critical_section_enter();
+    ret = _sector_erase(address - FLASH_BASE);
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    int32_t ret;
+
+    core_util_critical_section_enter();
+    ret = _page_program(address - FLASH_BASE, data, size);
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+        return MBED_FLASH_INVALID_SIZE;
+    }
+
+    return FLASH_SECTOR_SIZE;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return 1;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return FLASH_BASE;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return FLASH_SIZE;
+}
+
+int32_t _sector_erase(uint32_t addr)
+{
+    int32_t ret;
+
+    spi_mode();
+
+    /* ---- Write enable   ---- */
+    ret = write_enable();      /* WREN Command */
+    if (ret != 0) {
+        ex_mode();
+        return ret;
+    }
+
+    /* ---- spimd_reg init ---- */
+    clear_spimd_reg(&spimd_reg);
+
+    /* ---- command ---- */
+    spimd_reg.cde    = SPIBSC_OUTPUT_ENABLE;
+    spimd_reg.cdb    = SPIBSC_1BIT;
+    spimd_reg.cmd    = SFLASHCMD_SECTOR_ERASE;
+
+    /* ---- address ---- */
+    spimd_reg.ade    = SPIBSC_OUTPUT_ADDR_24;
+    spimd_reg.addre  = SPIBSC_SDR_TRANS;       /* SDR */
+    spimd_reg.adb    = SPIBSC_1BIT;
+    spimd_reg.addr   = addr;
+
+    ret = spibsc_transfer(&spimd_reg);
+    if (ret != 0) {
+        ex_mode();
+        return ret;
+    }
+
+    ret = busy_wait();
+
+    ex_mode();
+    return ret;
+}
+
+int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size)
+{
+    int32_t ret;
+    int32_t program_size;
+    int32_t remainder;
+    int32_t idx = 0;
+
+    spi_mode();
+
+    while (size > 0) {
+        if (size > FLASH_PAGE_SIZE) {
+            program_size = FLASH_PAGE_SIZE;
+        } else {
+            program_size = size;
+        }
+        remainder = FLASH_PAGE_SIZE - (addr % FLASH_PAGE_SIZE);
+        if ((remainder != 0) && (program_size > remainder)) {
+            program_size = remainder;
+        }
+
+        /* ---- Write enable   ---- */
+        ret = write_enable();      /* WREN Command */
+        if (ret != 0) {
+            ex_mode();
+            return ret;
+        }
+
+        /* ----------- 1. Command, Address ---------------*/
+        /* ---- spimd_reg init ---- */
+        clear_spimd_reg(&spimd_reg);
+
+        /* ---- command ---- */
+        spimd_reg.cde    = SPIBSC_OUTPUT_ENABLE;
+        spimd_reg.cdb    = SPIBSC_1BIT;
+        spimd_reg.cmd    = SFLASHCMD_PAGE_PROGRAM;
+
+        /* ---- address ---- */
+        spimd_reg.ade    = SPIBSC_OUTPUT_ADDR_24;
+        spimd_reg.addre  = SPIBSC_SDR_TRANS;       /* SDR */
+        spimd_reg.adb    = SPIBSC_1BIT;
+        spimd_reg.addr   = addr;
+
+        /* ---- Others ---- */
+        spimd_reg.sslkp  = SPIBSC_SPISSL_KEEP;     /* SPBSSL level */
+
+        ret = spibsc_transfer(&spimd_reg);         /* Command,Address */
+        if (ret != 0) {
+            ex_mode();
+            return ret;
+        }
+
+        /* ----------- 2. Data ---------------*/
+        ret = data_send(SPIBSC_1BIT, SPIBSC_SPISSL_NEGATE, &buf[idx], program_size);
+        if (ret != 0) {
+            ex_mode();
+            return ret;
+        }
+
+        ret = busy_wait();
+        if (ret != 0) {
+            ex_mode();
+            return ret;
+        }
+
+        addr += program_size;
+        idx  += program_size;
+        size -= program_size;
+    }
+
+    ex_mode();
+    return ret;
+}
+
+static int32_t write_enable(void)
+{
+    int32_t ret;
+
+    /* ---- spimd_reg init ---- */
+    clear_spimd_reg(&spimd_reg);
+
+    /* ---- command ---- */
+    spimd_reg.cde    = SPIBSC_OUTPUT_ENABLE;
+    spimd_reg.cdb    = SPIBSC_1BIT;
+    spimd_reg.cmd    = SFLASHCMD_WRITE_ENABLE;
+
+    ret = spibsc_transfer(&spimd_reg);
+
+    return ret;
+}
+
+static int32_t busy_wait(void)
+{
+    int32_t ret;
+    uint8_t st_reg;
+
+    while (1) {
+        ret = read_register(SFLASHCMD_READ_STATUS_REG, &st_reg);
+        if (ret != 0) {
+            break;
+        }
+        if ((st_reg & STREG_BUSY_BIT) == 0) {
+            break;
+        }
+    }
+
+    return ret;
+}
+
+static int32_t read_register(uint8_t cmd, uint8_t * status)
+{
+    int32_t ret;
+
+    /* ---- spimd_reg init ---- */
+    clear_spimd_reg(&spimd_reg);
+
+    /* ---- command ---- */
+    spimd_reg.cde    = SPIBSC_OUTPUT_ENABLE;
+    spimd_reg.cdb    = SPIBSC_1BIT;
+    spimd_reg.cmd    = cmd;
+
+    /* ---- Others ---- */
+    spimd_reg.sslkp  = SPIBSC_SPISSL_NEGATE;   /* SPBSSL level */
+    spimd_reg.spire  = SPIBSC_SPIDATA_ENABLE;  /* read enable/disable */
+    spimd_reg.spiwe  = SPIBSC_SPIDATA_ENABLE;  /* write enable/disable */
+
+    /* ---- data ---- */
+    spimd_reg.spide  = SPIBSC_OUTPUT_SPID_8;   /* Enable(8bit) */
+    spimd_reg.spidre = SPIBSC_SDR_TRANS;       /* SDR */
+    spimd_reg.spidb  = SPIBSC_1BIT;
+    spimd_reg.smwdr[0] = 0x00;                 /* Output 0 in read status */
+    spimd_reg.smwdr[1] = 0x00;                 /* Output 0 in read status */
+
+    ret = spibsc_transfer(&spimd_reg);
+    if (ret == 0) {
+        *status = (uint8_t)(spimd_reg.smrdr[0]);   /* Data[7:0]  */
+    }
+
+    return ret;
+}
+
+static int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size)
+{
+    int32_t ret = 0;
+    int32_t unit;
+    uint8_t  *buf_b;
+    uint16_t *buf_s;
+    uint32_t *buf_l;
+
+    /* ---- spimd_reg init ---- */
+    clear_spimd_reg(&spimd_reg);
+
+    /* ---- Others ---- */
+    spimd_reg.sslkp  = SPIBSC_SPISSL_KEEP;     /* SPBSSL level */
+    spimd_reg.spiwe  = SPIBSC_SPIDATA_ENABLE;  /* write enable/disable */
+
+    /* ---- data ---- */
+    spimd_reg.spidb = bit_width;
+    spimd_reg.spidre= SPIBSC_SDR_TRANS;        /* SDR */
+
+    if (((uint32_t)size & 0x3)  == 0) {
+        spimd_reg.spide = SPIBSC_OUTPUT_SPID_32;  /* Enable(32bit) */
+        unit = 4;
+    } else if (((uint32_t)size & 0x1) == 0) {
+        spimd_reg.spide = SPIBSC_OUTPUT_SPID_16;  /* Enable(16bit) */
+        unit = 2;
+    } else {
+        spimd_reg.spide = SPIBSC_OUTPUT_SPID_8;   /* Enable(8bit) */
+        unit = 1;
+    }
+
+    while (size > 0) {
+        if (unit == 1) {
+            buf_b = (uint8_t *)buf;
+            spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_b) & 0x000000FF);
+        } else if (unit == 2) {
+            buf_s = (uint16_t *)buf;
+            spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_s) & 0x0000FFFF);
+        } else if (unit == 4) {
+            buf_l = (uint32_t *)buf;
+            spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)(*buf_l)) & 0xfffffffful);
+        } else {
+            /* Do Nothing */
+        }
+
+        buf  += unit;
+        size -= unit;
+
+        if (size <= 0) {
+            spimd_reg.sslkp = spbssl_level;
+        }
+
+        ret = spibsc_transfer(&spimd_reg);    /* Data */
+        if (ret != 0) {
+            return ret;
+        }
+    }
+
+    return ret;
+}
+
+static void spi_mode(void)
+{
+    volatile uint32_t dummy_read_32;
+
+    if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) {
+        /* ==== Change the MMU translation table SPI Multi-I/O bus space settings
+                for use in SPI operating mode ==== */
+        change_mmu_ttbl_spibsc(0);
+
+        /* ==== Cleaning and invalidation of cache ==== */
+        cache_control();
+
+        /* ==== Switch to SPI operating mode ==== */
+        spibsc_stop();
+
+        dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
+        /* SPI Mode */
+        RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
+        dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
+
+    }
+    (void)dummy_read_32;
+}
+
+static void ex_mode(void)
+{
+    volatile uint32_t dummy_read_32;
+
+    if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_EXTRD) {
+        /* ==== Switch to external address space read mode and clear SPIBSC read cache ==== */
+        spibsc_stop();
+
+        /* Flush SPIBSC's read cache */
+        RegWwrite_32(&SPIBSC->DRCR, SPIBSC_DRCR_RCF_EXE, SPIBSC_DRCR_RCF_SHIFT, SPIBSC_DRCR_RCF);
+        dummy_read_32 = SPIBSC->DRCR;  /* dummy read */
+
+        /* External address space read mode */
+        RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_EXTRD, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
+        dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
+
+        /* ==== Change the MMU translation table SPI Multi-I/O bus space settings
+                for use in external address space read mode ==== */
+        change_mmu_ttbl_spibsc(1);
+
+        /* ==== Cleaning and invalidation of cache ==== */
+        cache_control();
+    }
+    (void)dummy_read_32;
+}
+
+static void clear_spimd_reg(st_spibsc_spimd_reg_t * regset)
+{
+    /* ---- command ---- */
+    regset->cde    = SPIBSC_OUTPUT_DISABLE;
+    regset->cdb    = SPIBSC_1BIT;
+    regset->cmd    = 0x00;
+
+    /* ---- optional command ---- */
+    regset->ocde   = SPIBSC_OUTPUT_DISABLE;
+    regset->ocdb   = SPIBSC_1BIT;
+    regset->ocmd   = 0x00;
+
+    /* ---- address ---- */
+    regset->ade    = SPIBSC_OUTPUT_DISABLE;
+    regset->addre  = SPIBSC_SDR_TRANS;       /* SDR */
+    regset->adb    = SPIBSC_1BIT;
+    regset->addr   = 0x00000000;
+
+    /* ---- option data ---- */
+    regset->opde   = SPIBSC_OUTPUT_DISABLE;
+    regset->opdre  = SPIBSC_SDR_TRANS;       /* SDR */
+    regset->opdb   = SPIBSC_1BIT;
+    regset->opd[0] = 0x00;    /* OPD3 */
+    regset->opd[1] = 0x00;    /* OPD2 */
+    regset->opd[2] = 0x00;    /* OPD1 */
+    regset->opd[3] = 0x00;    /* OPD0 */
+
+    /* ---- dummy cycle ---- */
+    regset->dme    = SPIBSC_DUMMY_CYC_DISABLE;
+    regset->dmdb   = SPIBSC_1BIT;
+    regset->dmcyc  = SPIBSC_DUMMY_1CYC;
+
+    /* ---- data ---- */
+    regset->spide  = SPIBSC_OUTPUT_DISABLE;
+    regset->spidre = SPIBSC_SDR_TRANS;       /* SDR */
+    regset->spidb  = SPIBSC_1BIT;
+
+    /* ---- Others ---- */
+    regset->sslkp  = SPIBSC_SPISSL_NEGATE;   /* SPBSSL level */
+    regset->spire  = SPIBSC_SPIDATA_DISABLE; /* read enable/disable */
+    regset->spiwe  = SPIBSC_SPIDATA_DISABLE; /* write enable/disable */
+}
+
+static int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset)
+{
+    if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) {
+        if (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) {
+            return -1;
+        }
+        /* SPI Mode */
+        RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
+    }
+
+    if (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
+        return -1;
+    }
+
+    /* ---- Command ---- */
+    /* Enable/Disable */
+    RegWwrite_32(&SPIBSC->SMENR, regset->cde, SPIBSC_SMENR_CDE_SHIFT, SPIBSC_SMENR_CDE);
+    if (regset->cde != SPIBSC_OUTPUT_DISABLE) {
+        /* Command */
+        RegWwrite_32(&SPIBSC->SMCMR, regset->cmd, SPIBSC_SMCMR_CMD_SHIFT, SPIBSC_SMCMR_CMD);
+        /* Single/Dual/Quad */
+        RegWwrite_32(&SPIBSC->SMENR, regset->cdb, SPIBSC_SMENR_CDB_SHIFT, SPIBSC_SMENR_CDB);
+    }
+
+    /* ---- Option Command ---- */
+    /* Enable/Disable */
+    RegWwrite_32(&SPIBSC->SMENR, regset->ocde, SPIBSC_SMENR_OCDE_SHIFT, SPIBSC_SMENR_OCDE);
+    if (regset->ocde != SPIBSC_OUTPUT_DISABLE) {
+        /* Option Command */
+        RegWwrite_32(&SPIBSC->SMCMR, regset->ocmd, SPIBSC_SMCMR_OCMD_SHIFT, SPIBSC_SMCMR_OCMD);
+        /* Single/Dual/Quad */
+        RegWwrite_32(&SPIBSC->SMENR, regset->ocdb, SPIBSC_SMENR_OCDB_SHIFT, SPIBSC_SMENR_OCDB);
+    }
+
+    /* ---- Address ---- */
+    /* Enable/Disable */
+    RegWwrite_32(&SPIBSC->SMENR, regset->ade, SPIBSC_SMENR_ADE_SHIFT, SPIBSC_SMENR_ADE);
+    if (regset->ade != SPIBSC_OUTPUT_DISABLE) {
+        /* Address */
+        RegWwrite_32(&SPIBSC->SMADR, regset->addr, SPIBSC_SMADR_ADR_SHIFT, SPIBSC_SMADR_ADR);
+        /* Single/Dual/Quad */
+        RegWwrite_32(&SPIBSC->SMENR, regset->adb, SPIBSC_SMENR_ADB_SHIFT, SPIBSC_SMENR_ADB);
+    }
+
+    /* ---- Option Data ---- */
+    /* Enable/Disable */
+    RegWwrite_32(&SPIBSC->SMENR, regset->opde, SPIBSC_SMENR_OPDE_SHIFT, SPIBSC_SMENR_OPDE);
+    if (regset->opde != SPIBSC_OUTPUT_DISABLE) {
+        /* Option Data */
+        RegWwrite_32(&SPIBSC->SMOPR, regset->opd[0], SPIBSC_SMOPR_OPD3_SHIFT, SPIBSC_SMOPR_OPD3);
+        RegWwrite_32(&SPIBSC->SMOPR, regset->opd[1], SPIBSC_SMOPR_OPD2_SHIFT, SPIBSC_SMOPR_OPD2);
+        RegWwrite_32(&SPIBSC->SMOPR, regset->opd[2], SPIBSC_SMOPR_OPD1_SHIFT, SPIBSC_SMOPR_OPD1);
+        RegWwrite_32(&SPIBSC->SMOPR, regset->opd[3], SPIBSC_SMOPR_OPD0_SHIFT, SPIBSC_SMOPR_OPD0);
+        /* Single/Dual/Quad */
+        RegWwrite_32(&SPIBSC->SMENR, regset->opdb, SPIBSC_SMENR_OPDB_SHIFT, SPIBSC_SMENR_OPDB);
+    }
+
+    /* ---- Dummy ---- */
+     /* Enable/Disable */
+     RegWwrite_32(&SPIBSC->SMENR, regset->dme, SPIBSC_SMENR_DME_SHIFT, SPIBSC_SMENR_DME);
+     if (regset->dme != SPIBSC_DUMMY_CYC_DISABLE) {
+         RegWwrite_32(&SPIBSC->SMDMCR, regset->dmdb, SPIBSC_SMDMCR_DMDB_SHIFT, SPIBSC_SMDMCR_DMDB);
+         /* Dummy Cycle */
+         RegWwrite_32(&SPIBSC->SMDMCR, regset->dmcyc, SPIBSC_SMDMCR_DMCYC_SHIFT, SPIBSC_SMDMCR_DMCYC);
+     }
+
+    /* ---- Data ---- */
+    /* Enable/Disable */
+    RegWwrite_32(&SPIBSC->SMENR, regset->spide, SPIBSC_SMENR_SPIDE_SHIFT, SPIBSC_SMENR_SPIDE);
+    if (regset->spide != SPIBSC_OUTPUT_DISABLE) {
+        if (SPIBSC_OUTPUT_SPID_8 == regset->spide) {
+            if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
+                SPIBSC->SMWDR0.UINT8[0] = (uint8_t)(regset->smwdr[0]);
+            } else {
+                SPIBSC->SMWDR0.UINT16[0] = (uint16_t)(regset->smwdr[0]);
+            }
+        } else if (regset->spide == SPIBSC_OUTPUT_SPID_16) {
+            if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
+                SPIBSC->SMWDR0.UINT16[0] = (uint16_t)(regset->smwdr[0]);
+            } else {
+                SPIBSC->SMWDR0.UINT32 = regset->smwdr[0];
+            }
+        } else if (regset->spide == SPIBSC_OUTPUT_SPID_32) {
+            if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
+                SPIBSC->SMWDR0.UINT32 = (uint32_t)(regset->smwdr[0]);
+            } else {
+                SPIBSC->SMWDR0.UINT32 = (uint32_t)(regset->smwdr[0]);
+                SPIBSC->SMWDR1.UINT32 = (uint32_t)(regset->smwdr[1]);  /* valid in two serial-flash */
+            }
+        } else {
+            /* none */
+        }
+
+        /* Single/Dual/Quad */
+        RegWwrite_32(&SPIBSC->SMENR, regset->spidb, SPIBSC_SMENR_SPIDB_SHIFT, SPIBSC_SMENR_SPIDB);
+    }
+
+    RegWwrite_32(&SPIBSC->SMCR, regset->sslkp, SPIBSC_SMCR_SSLKP_SHIFT, SPIBSC_SMCR_SSLKP);
+
+    if ((regset->spidb != SPIBSC_1BIT) && (regset->spide != SPIBSC_OUTPUT_DISABLE)) {
+        if ((regset->spire == SPIBSC_SPIDATA_ENABLE) && (regset->spiwe == SPIBSC_SPIDATA_ENABLE)) {
+            /* not set in same time */
+            return -1;
+        }
+    }
+
+    RegWwrite_32(&SPIBSC->SMCR, regset->spire, SPIBSC_SMCR_SPIRE_SHIFT, SPIBSC_SMCR_SPIRE);
+    RegWwrite_32(&SPIBSC->SMCR, regset->spiwe, SPIBSC_SMCR_SPIWE_SHIFT, SPIBSC_SMCR_SPIWE);
+
+    /* SDR Transmission/DDR Transmission Setting */
+    RegWwrite_32(&SPIBSC->SMDRENR, regset->addre, SPIBSC_SMDRENR_ADDRE_SHIFT, SPIBSC_SMDRENR_ADDRE);
+    RegWwrite_32(&SPIBSC->SMDRENR, regset->opdre, SPIBSC_SMDRENR_OPDRE_SHIFT, SPIBSC_SMDRENR_OPDRE);
+    RegWwrite_32(&SPIBSC->SMDRENR, regset->spidre, SPIBSC_SMDRENR_SPIDRE_SHIFT, SPIBSC_SMDRENR_SPIDRE);
+
+    /* execute after setting SPNDL bit */
+    RegWwrite_32(&SPIBSC->SMCR, SPIBSC_SPI_ENABLE, SPIBSC_SMCR_SPIE_SHIFT, SPIBSC_SMCR_SPIE);
+
+    /* wait for transfer-start */
+    while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
+        /* wait for transfer-end */
+    }
+
+    if (SPIBSC_OUTPUT_SPID_8 == regset->spide) {
+        if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
+            regset->smrdr[0] = SPIBSC->SMRDR0.UINT8[0];
+        } else {
+            regset->smrdr[0] = SPIBSC->SMRDR0.UINT16[0];        /* valid in two serial-flash  */
+        }
+    } else if (regset->spide == SPIBSC_OUTPUT_SPID_16) {
+        if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
+            regset->smrdr[0] = SPIBSC->SMRDR0.UINT16[0];
+        } else {
+            regset->smrdr[0] = SPIBSC->SMRDR0.UINT32;           /* valid in two serial-flash  */
+        }
+    } else if (regset->spide == SPIBSC_OUTPUT_SPID_32) {
+        if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
+            regset->smrdr[0] = SPIBSC->SMRDR0.UINT32;
+        } else {
+            regset->smrdr[0] = SPIBSC->SMRDR0.UINT32;           /* valid in two serial-flash  */
+            regset->smrdr[1] = SPIBSC->SMRDR1.UINT32;
+        }
+    } else {
+        /* none */
+    }
+
+    return 0;
+}
+
+static uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
+{
+    uint32_t reg_value;
+
+    reg_value = *ioreg;                        /* Read from register            */
+    reg_value = (reg_value & mask) >> shift;   /* Clear other bit and Bit shift */
+
+    return reg_value;
+}
+
+static void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
+{
+    uint32_t reg_value;
+
+    reg_value = *ioreg;                                         /* Read from register */
+    reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value       */
+    *ioreg    = reg_value;                                      /* Write to register  */
+}
+
+static void change_mmu_ttbl_spibsc(uint32_t type)
+{
+    uint32_t index;               /* Loop variable: table index */
+    mmu_ttbl_desc_section_t desc; /* Loop variable: descriptor */
+    mmu_ttbl_desc_section_t * table = (mmu_ttbl_desc_section_t *)TTB;
+
+    /* ==== Modify SPI Multi-I/O bus space settings in the MMU translation table ==== */
+    for (index = (SPIBSC_ADDR_START >> 20); index <= (SPIBSC_ADDR_END >> 20); index++) {
+        /* Modify memory attribute descriptor */
+        if (type == 0) {         /* Spi */
+            desc = table[index];
+            desc_tbl[index - (SPIBSC_ADDR_START >> 20)] = desc;
+            desc.AP1_0 = 0x0u;   /* AP[2:0] = b'000 (No access) */
+            desc.AP2   = 0x0u;
+            desc.XN    = 0x1u;   /* XN = 1 (Execute never) */
+        } else {                 /* Xip */
+            desc = desc_tbl[index - (SPIBSC_ADDR_START >> 20)];
+        }
+        /* Write descriptor back to translation table */
+        table[index] = desc;
+    }
+}
+
+static void spibsc_stop(void)
+{
+    if (((SPIBSC->DRCR & SPIBSC_DRCR_RBE)  != 0) &&
+        ((SPIBSC->DRCR & SPIBSC_DRCR_SSLE) != 0)) {
+        RegWwrite_32(&SPIBSC->DRCR, 1, SPIBSC_DRCR_SSLN_SHIFT, SPIBSC_DRCR_SSLN);
+    }
+
+    while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) {
+        ;
+    }
+
+    while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
+        ;
+    }
+}
+
+static void cache_control(void)
+{
+    unsigned int assoc;
+
+    /* ==== Cleaning and invalidation of the L1 data cache ==== */
+    L1C_CleanInvalidateDCacheAll();
+    __DSB();
+
+    /* ==== Cleaning and invalidation of the L2 cache ==== */
+    if (L2C_310->AUX_CNT & (1U << 16U)) {
+        assoc = 16U;
+    } else {
+        assoc =  8U;
+    }
+    L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
+    while (L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); // poll invalidate
+    L2C_310->CACHE_SYNC = 0x0;
+
+    /* ==== Invalidate all TLB entries ==== */
+    __set_TLBIALL(0);
+    __DSB();     // ensure completion of the invalidation
+    __ISB();     // ensure instruction fetch path sees new state
+
+    /* ==== Invalidate the L1 instruction cache ==== */
+    __set_ICIALLU(0);
+    __DSB();     // ensure completion of the invalidation
+    __ISB();     // ensure instruction fetch path sees new I cache state
+}
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_addrdefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_addrdefine.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_addrdefine.h	(revision 374)
@@ -0,0 +1,22 @@
+#ifndef __GPIO_ADDRDEFINE__
+#define __GPIO_ADDRDEFINE__
+
+#define GPIO_BASE  ((long)0xFCFE3000uL) /* GPIO */
+
+#define PORT(n)    (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4))
+#define PSR(n)     (volatile unsigned  long *)(GPIO_BASE + 0x100 + ((n)*4))
+#define PPR(n)     (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4))
+#define PM(n)      (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4))
+#define PMC(n)     (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4))
+#define PFC(n)     (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4))
+#define PFCE(n)    (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4))
+#define PNOT(n)    (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4))
+#define PMSR(n)    (volatile unsigned  long *)(GPIO_BASE + 0x800 + ((n)*4))
+#define PMCSR(n)   (volatile unsigned  long *)(GPIO_BASE + 0x900 + ((n)*4))
+#define PFCAE(n)   (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4))
+#define PIBC(n)    (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4))
+#define PBDC(n)    (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4))
+#define PIPC(n)    (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4))
+
+#endif/*__GPIO_ADDRDEFINE__*/
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_api.c	(revision 374)
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "gpio_addrdefine.h"
+#include "mbed_drv_cfg.h"
+
+
+uint32_t gpio_set(PinName pin) {
+    pin_function(pin, 0);
+    return (1 << PINNO(pin));
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+    int group ;
+    obj->pin = pin;
+    if(pin == NC) return;
+    
+    obj->mask = gpio_set(pin);
+
+    group = PINGROUP(pin);
+    if (group > GPIO_GROUP_MAX) return;
+
+    obj->reg_set = (volatile uint32_t *) PSR(group);
+    obj->reg_in  = (volatile uint32_t *) PPR(group);
+    obj->reg_dir = (volatile uint32_t *)PMSR(group);
+    obj->reg_buf = (volatile uint32_t *)PIBC(group);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT :
+            *obj->reg_dir = (obj->mask << 16) | obj->mask;
+            *obj->reg_buf |=  obj->mask;
+            break;
+        case PIN_OUTPUT:
+            *obj->reg_dir = (obj->mask << 16) | 0;
+            *obj->reg_buf &= ~obj->mask;
+            break;
+    }
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_irq_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_irq_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_irq_api.c	(revision 374)
@@ -0,0 +1,189 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "gpio_irq_api.h"
+#include "iodefine.h"
+#include "PeripheralPins.h"
+#include "cmsis.h"
+#include "gpio_addrdefine.h"
+
+#define CHANNEL_NUM     8
+
+static void gpio_irq0(void);
+static void gpio_irq1(void);
+static void gpio_irq2(void);
+static void gpio_irq3(void);
+static void gpio_irq4(void);
+static void gpio_irq5(void);
+static void gpio_irq6(void);
+static void gpio_irq7(void);
+
+static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL};
+static gpio_irq_handler irq_handler;
+static const int nIRQn_h = 32;
+extern PinName gpio_multi_guard;
+
+static const IRQHandler irq_tbl[CHANNEL_NUM] = {
+    &gpio_irq0,
+    &gpio_irq1,
+    &gpio_irq2,
+    &gpio_irq3,
+    &gpio_irq4,
+    &gpio_irq5,
+    &gpio_irq6,
+    &gpio_irq7,
+};
+
+static void handle_interrupt_in(int irq_num) {
+    uint16_t irqs;
+    uint16_t edge_req;
+    gpio_irq_t *obj;
+    gpio_irq_event irq_event;
+
+    irqs = INTCIRQRR;
+    if (irqs & (1 << irq_num)) {
+        obj = channel_obj[irq_num];
+        if (obj != NULL) {
+            edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3);
+            if (edge_req == 1) {
+                irq_event = IRQ_FALL;
+            } else if (edge_req == 2) {
+                irq_event = IRQ_RISE;
+            } else {
+                uint32_t      mask    = (1 << (obj->pin & 0x0F));
+                __I  uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin));
+
+                if ((*reg_in & mask) == 0) {
+                    irq_event = IRQ_FALL;
+                } else {
+                    irq_event = IRQ_RISE;
+                }
+	        }
+            irq_handler(obj->port, irq_event);
+        }
+        INTCIRQRR &= ~(1 << irq_num);
+    }
+}
+
+static void gpio_irq0(void) {
+    handle_interrupt_in(0);
+}
+
+static void gpio_irq1(void) {
+    handle_interrupt_in(1);
+}
+
+static void gpio_irq2(void) {
+    handle_interrupt_in(2);
+}
+
+static void gpio_irq3(void) {
+    handle_interrupt_in(3);
+}
+
+static void gpio_irq4(void) {
+    handle_interrupt_in(4);
+}
+
+static void gpio_irq5(void) {
+    handle_interrupt_in(5);
+}
+
+static void gpio_irq6(void) {
+    handle_interrupt_in(6);
+}
+
+static void gpio_irq7(void) {
+    handle_interrupt_in(7);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    int shift;
+    if (pin == NC) return -1;
+
+    obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
+    obj->pin = (int)pin ;
+    obj->port = (int)id ;
+
+    shift = obj->ch*2;
+    channel_obj[obj->ch] = obj;
+    irq_handler = handler;
+    
+    pinmap_pinout(pin, PinMap_IRQ);
+    gpio_multi_guard = pin;           /* Set multi guard */
+
+    // INTC settings
+    InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
+    INTCICR1 &= ~(0x3 << shift);
+    GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
+    GIC_SetConfiguration((IRQn_Type)(nIRQn_h + obj->ch), 1);
+    obj->int_enable = 1;
+    __enable_irq();
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_obj[obj->ch] = NULL;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    int shift = obj->ch*2;
+    uint16_t val = event == IRQ_RISE ? 2 : 
+                   event == IRQ_FALL ? 1 : 0;
+    uint16_t work_icr_val;
+
+    /* check edge interrupt setting */
+    work_icr_val = INTCICR1;
+    if (enable == 1) {
+        /* Set interrupt serect */
+        work_icr_val |=  (val << shift);
+    } else {
+        /* Clear interrupt serect */
+        work_icr_val &= ~(val << shift);
+    }
+
+    if ((work_icr_val & (3 << shift)) == 0) {
+        /* No edge interrupt setting */
+        GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
+        /* Clear Interrupt flags */
+        INTCIRQRR &= ~(1 << obj->ch);
+        INTCICR1  = work_icr_val;
+    } else if (obj->int_enable == 1) {
+        INTCICR1  = work_icr_val;
+        GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+    } else {
+        INTCICR1  = work_icr_val;
+    }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+    int shift = obj->ch*2;
+    uint16_t work_icr_val = INTCICR1;
+
+    /* check edge interrupt setting */
+    if ((work_icr_val & (3 << shift)) != 0) {
+        GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+    }
+    obj->int_enable = 1;
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+    GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+    obj->int_enable = 0;
+}
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_object.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_object.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_object.h	(revision 374)
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "platform/mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __I  uint32_t *reg_in;
+    __IO uint32_t *reg_buf;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0);
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/i2c_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/i2c_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/i2c_api.c	(revision 374)
@@ -0,0 +1,1137 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "dma_api.h"
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "PeripheralPins.h"
+#include "r_typedefs.h"
+
+#include "iodefine.h"
+#include "RZ_A1_Init.h"
+
+volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
+
+#define REG(N) \
+    RIIC[obj->i2c.i2c]->RIICn##N
+
+/* RIICnCR1 */
+#define CR1_RST   (1 << 6)
+#define CR1_ICE   (1 << 7)
+
+/* RIICnCR2 */
+#define CR2_ST    (1 << 1)
+#define CR2_RS    (1 << 2)
+#define CR2_SP    (1 << 3)
+#define CR2_TRS   (1 << 5)
+#define CR2_BBSY  (1 << 7)
+
+/* RIICnMR3 */
+#define MR3_ACKBT (1 << 3)
+#define MR3_ACKWP (1 << 4)
+#define MR3_WAIT  (1 << 6)
+
+/* RIICnSER */
+#define SER_SAR0E (1 << 0)
+
+/* RIICnSR1 */
+#define SR1_AAS0  (1 << 0)
+
+/* RIICnSR2 */
+#define SR2_START (1 << 2)
+#define SR2_STOP  (1 << 3)
+#define SR2_NACKF (1 << 4)
+#define SR2_RDRF  (1 << 5)
+#define SR2_TEND  (1 << 6)
+#define SR2_TDRE  (1 << 7)
+
+#define WAIT_TIMEOUT    (3600000)  /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
+
+static inline int i2c_status(i2c_t *obj) {
+    return REG(SR2.UINT8[0]);
+}
+
+static void i2c_reg_reset(i2c_t *obj) {
+    /* full reset */
+    REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
+    REG(CR1.UINT8[0]) |=  CR1_RST; // CR1.IICRST on
+    REG(CR1.UINT8[0]) |=  CR1_ICE; // CR1.ICE on
+
+    REG(MR1.UINT8[0])  =  0x08;    // P_phi /x  9bit (including Ack)
+    REG(SER.UINT8[0])  =  0x00;    // no slave addr enabled
+
+    /* set frequency */
+    REG(MR1.UINT8[0]) |=  obj->i2c.pclk_bit;
+    REG(BRL.UINT8[0])  =  obj->i2c.width_low;
+    REG(BRH.UINT8[0])  =  obj->i2c.width_hi;
+
+    REG(MR2.UINT8[0])  =  0x07;
+    REG(MR3.UINT8[0])  =  0x00;
+
+    REG(FER.UINT8[0])  =  0x72;    // SCLE, NFE enabled, TMOT
+    REG(IER.UINT8[0])  =  0x00;    // no interrupt
+
+    REG(CR1.UINT32) &= ~CR1_RST;   // CR1.IICRST negate reset
+}
+
+static inline int i2c_wait_RDRF(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_RDRF) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_wait_TDRE(i2c_t *obj) {
+    int timeout = 0;
+
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_TDRE) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_wait_TEND(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_TEND) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+
+static int i2c_wait_START(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_START) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_wait_STOP(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_STOP) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_set_STOP(i2c_t *obj) {
+    /* SR2.STOP = 0 */
+    REG(SR2.UINT32) &= ~SR2_STOP;
+    /* Stop condition */
+    REG(CR2.UINT32) |= CR2_SP;
+
+    return 0;
+}
+
+static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
+    /* SR2.NACKF = 0 */
+    REG(SR2.UINT32) &= ~SR2_NACKF;
+    /* SR2.STOP = 0 */
+    REG(SR2.UINT32) &= ~SR2_STOP;
+}
+
+static void i2c_set_MR3_NACK(i2c_t *obj) {
+    /* send a NOT ACK */
+    REG(MR3.UINT32) |=  MR3_ACKWP;
+    REG(MR3.UINT32) |=  MR3_ACKBT;
+    REG(MR3.UINT32) &= ~MR3_ACKWP;
+}
+
+static void i2c_set_MR3_ACK(i2c_t *obj) {
+    /* send a ACK */
+    REG(MR3.UINT32) |=  MR3_ACKWP;
+    REG(MR3.UINT32) &= ~MR3_ACKBT;
+    REG(MR3.UINT32) &= ~MR3_ACKWP;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    volatile uint8_t dummy;
+    switch ((int)obj->i2c.i2c) {
+        case I2C_0:
+            CPGSTBCR9 &= ~(0x80);
+            break;
+        case I2C_1:
+            CPGSTBCR9 &= ~(0x40);
+            break;
+        case I2C_2:
+            CPGSTBCR9 &= ~(0x20);
+            break;
+        case I2C_3:
+            CPGSTBCR9 &= ~(0x10);
+            break;
+    }
+    dummy = CPGSTBCR9;
+    (void)dummy;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    /* determine the I2C to use */
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c.i2c = pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)obj->i2c.i2c != NC);
+
+    /* enable power */
+    i2c_power_enable(obj);
+
+    /* set default frequency at 100k */
+    i2c_frequency(obj, 100000);
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    
+    obj->i2c.last_stop_flag = 1;
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int timeout = 0;
+
+    while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
+        timeout ++;
+        if (timeout >= obj->i2c.bbsy_wait_cnt) {
+            break;
+        }
+    }
+    /* Start Condition */
+    REG(CR2.UINT8[0]) |= CR2_ST;
+
+    return 0;
+}
+
+static inline int i2c_restart(i2c_t *obj) {
+    /* SR2.START = 0 */
+    REG(SR2.UINT32) &= ~SR2_START;
+    /* ReStart condition */
+    REG(CR2.UINT32) |= CR2_RS;
+
+    return 0;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    (void)i2c_set_STOP(obj);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+    
+    return 0;
+}
+
+static void i2c_set_err_noslave(i2c_t *obj) {
+    (void)i2c_set_STOP(obj);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+    obj->i2c.last_stop_flag = 1;
+}
+
+static inline int i2c_do_write(i2c_t *obj, int value) {
+    int timeout = 0;
+
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_TDRE) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+    /* write the data */
+    REG(DRT.UINT32) = value;
+
+    return 0;
+}
+
+static inline int i2c_read_address_write(i2c_t *obj, int value) {
+    int status;
+    
+    status = i2c_wait_TDRE(obj);
+    if (status == 0) {
+        /* write the data */
+        REG(DRT.UINT32) = value;
+    }
+    
+    return status;
+
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    if (last == 2) {
+        /* this time is befor last byte read */
+        /* Set MR3 WAIT bit is 1 */;
+        REG(MR3.UINT32) |= MR3_WAIT;
+    } else if (last == 1) {
+        i2c_set_MR3_NACK(obj);
+    } else {
+        i2c_set_MR3_ACK(obj);
+    }
+
+    /* return the data */
+    return (REG(DRR.UINT32) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    float64_t pclk_val;
+    float64_t wait_utime;
+    volatile float64_t bps;
+    volatile float64_t L_time;         /* H Width period */
+    volatile float64_t H_time;         /* L Width period */
+    uint32_t tmp_L_width;
+    uint32_t tmp_H_width;
+    uint32_t remainder;
+    uint32_t wk_cks = 0;
+
+    /* set PCLK */
+    if (false == RZ_A1_IsClockMode0()) {
+        pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
+    } else {
+        pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
+    }
+
+    /* Min 10kHz, Max 400kHz */
+    if (hz < 10000) {
+        bps = 10000;
+    } else if (hz > 400000) {
+        bps = 400000;
+    } else {
+        bps = (float64_t)hz;
+    }
+
+    /* Calculation L width time */
+    L_time = (1 / (2 * bps));   /* Harf period of frequency */
+    H_time = L_time;
+
+    /* Check I2C mode of Speed */
+    if (bps > 100000) {
+        /* Fast-mode */
+        L_time -= 102E-9;    /* Falling time of SCL clock. */
+        H_time -= 138E-9;    /* Rising time of SCL clock. */
+        /* Check L wideth */
+        if (L_time < 1.3E-6) {
+            /* Wnen L width less than 1.3us */
+            /* Subtract Rise up and down time for SCL from H/L width */
+            L_time = 1.3E-6;
+            H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
+        }
+    }
+
+    tmp_L_width   = (uint32_t)(L_time * pclk_val * 10);
+    tmp_L_width >>= 1;
+    wk_cks++;
+    while (tmp_L_width >= 341) {
+        tmp_L_width >>= 1;
+        wk_cks++;
+    }
+    remainder   = tmp_L_width % 10;
+    tmp_L_width = ((tmp_L_width + 9) / 10) - 3;       /* carry */
+
+    tmp_H_width   = (uint32_t)(H_time * pclk_val * 10);
+    tmp_H_width >>= wk_cks;
+    if (remainder == 0) {
+        tmp_H_width   = ((tmp_H_width + 9) / 10) - 3; /* carry */
+    } else {
+        remainder    += tmp_H_width % 10;
+        tmp_H_width   = (tmp_H_width / 10) - 3;
+        if (remainder > 10) {
+            tmp_H_width += 1;                         /* fine adjustment */
+        }
+    }
+    /* timeout of BBSY bit is minimum low width by frequency */
+    /* so timeout calculates "(low width) * 2" by frequency */
+    wait_utime = (L_time * 2) * 1000000;
+    /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
+    if (wait_utime <= 0.3) {
+        obj->i2c.bbsy_wait_cnt = 1;
+    } else {
+        obj->i2c.bbsy_wait_cnt = (int)(wait_utime / 0.3);
+    }
+
+
+    /* I2C Rate */
+    obj->i2c.pclk_bit  = (uint8_t)(0x10 * wk_cks);        /* P_phi / xx */
+    obj->i2c.width_low = (uint8_t)(tmp_L_width | 0x000000E0);
+    obj->i2c.width_hi  = (uint8_t)(tmp_H_width | 0x000000E0);
+
+    /* full reset */
+    i2c_reg_reset(obj);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count = 0;
+    int status;
+    int value;
+
+    i2c_set_MR3_ACK(obj);
+    /* There is a STOP condition for last processing */
+    if (obj->i2c.last_stop_flag != 0) {
+        status = i2c_start(obj);
+        if (status != 0) {
+            i2c_set_err_noslave(obj);
+            return I2C_ERROR_BUS_BUSY;
+        }
+    }
+    obj->i2c.last_stop_flag = stop;
+    /*  Send Slave address */
+    status = i2c_read_address_write(obj, (address | 0x01));
+    if (status != 0) {
+        i2c_set_err_noslave(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    /* wait RDRF */
+    status = i2c_wait_RDRF(obj);
+    /* check ACK/NACK */
+    if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+        /* Slave sends NACK */
+        (void)i2c_set_STOP(obj);
+        /* dummy read */
+        value = REG(DRR.UINT32);
+        (void)i2c_wait_STOP(obj);
+        i2c_set_SR2_NACKF_STOP(obj);
+        obj->i2c.last_stop_flag = 1;
+        return I2C_ERROR_NO_SLAVE;
+    }
+    if (length != 0) {
+        /* Read in all except last byte */
+        if (length > 2) {
+            /* dummy read */
+            value = REG(DRR.UINT32);
+            for (count = 0; count < (length - 1); count++) {
+                /* wait for it to arrive */
+                status = i2c_wait_RDRF(obj);
+                if (status != 0) {
+                    i2c_set_err_noslave(obj);
+                    return I2C_ERROR_NO_SLAVE;
+                }
+                /* Recieve the data */
+                if (count == (length - 2)) {
+                    value = i2c_do_read(obj, 1);
+                } else if ((length >= 3) && (count == (length - 3))) {
+                    value = i2c_do_read(obj, 2);
+                } else {
+                    value = i2c_do_read(obj, 0);
+                }
+                data[count] = (char)value;
+            }
+        } else if (length == 2) {
+            /* Set MR3 WAIT bit is 1 */
+            REG(MR3.UINT32) |= MR3_WAIT;
+            /* dummy read */
+            value = REG(DRR.UINT32);
+            /* wait for it to arrive */
+            status = i2c_wait_RDRF(obj);
+            if (status != 0) {
+                i2c_set_err_noslave(obj);
+                return I2C_ERROR_NO_SLAVE;
+            }
+            i2c_set_MR3_NACK(obj);
+            data[count] = (char)REG(DRR.UINT32);
+            count++;
+        } else {
+            /* length == 1 */
+            /* Set MR3 WAIT bit is 1 */;
+            REG(MR3.UINT32) |=  MR3_WAIT;
+            i2c_set_MR3_NACK(obj);
+            /* dummy read */
+            value = REG(DRR.UINT32);
+        }
+        /* wait for it to arrive */
+        status = i2c_wait_RDRF(obj);
+        if (status != 0) {
+            i2c_set_err_noslave(obj);
+            return I2C_ERROR_NO_SLAVE;
+        }
+
+        /* If not repeated start, send stop. */
+        if (stop) {
+            (void)i2c_set_STOP(obj);
+            /* RIICnDRR read */
+            value = (REG(DRR.UINT32) & 0xFF);
+            data[count] = (char)value;
+            /* RIICnMR3.WAIT = 0 */
+            REG(MR3.UINT32) &= ~MR3_WAIT;
+            (void)i2c_wait_STOP(obj);
+            i2c_set_SR2_NACKF_STOP(obj);
+        } else {
+            (void)i2c_restart(obj);
+            /* RIICnDRR read */
+            value = (REG(DRR.UINT32) & 0xFF);
+            data[count] = (char)value;
+            /* RIICnMR3.WAIT = 0 */
+            REG(MR3.UINT32) &= ~MR3_WAIT;
+            (void)i2c_wait_START(obj);
+            /* SR2.START = 0 */
+            REG(SR2.UINT32) &= ~SR2_START;
+        }
+    } else {
+        /* If not repeated start, send stop. */
+        if (stop) {
+            (void)i2c_set_STOP(obj);
+            (void)i2c_wait_STOP(obj);
+            i2c_set_SR2_NACKF_STOP(obj);
+        } else {
+            (void)i2c_restart(obj);
+            (void)i2c_wait_START(obj);
+            /* SR2.START = 0 */
+            REG(SR2.UINT32) &= ~SR2_START;
+        }
+    }
+
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int cnt;
+    int status;
+
+    /* There is a STOP condition for last processing */
+    if (obj->i2c.last_stop_flag != 0) {
+        status = i2c_start(obj);
+        if (status != 0) {
+            i2c_set_err_noslave(obj);
+            return I2C_ERROR_BUS_BUSY;
+        }
+    }
+    obj->i2c.last_stop_flag = stop;
+    /*  Send Slave address */
+    status = i2c_do_write(obj, address);
+    if (status != 0) {
+        i2c_set_err_noslave(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    /* Wait send end */
+    status = i2c_wait_TEND(obj);
+    if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+        /* Slave sends NACK */
+        i2c_set_err_noslave(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    /* Send Write data */
+    for (cnt=0; cnt<length; cnt++) {
+        status = i2c_do_write(obj, data[cnt]);
+        if(status != 0) {
+            i2c_set_err_noslave(obj);
+            return cnt;
+        } else {
+            /* Wait send end */
+            status = i2c_wait_TEND(obj);
+            if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+                /* Slave sends NACK */
+                i2c_set_err_noslave(obj);
+                return I2C_ERROR_NO_SLAVE;
+            }
+        }
+    }
+    /* If not repeated start, send stop. */
+    if (stop) {
+        (void)i2c_set_STOP(obj);
+        (void)i2c_wait_STOP(obj);
+        i2c_set_SR2_NACKF_STOP(obj);
+    } else {
+        (void)i2c_restart(obj);
+        (void)i2c_wait_START(obj);
+        /* SR2.START = 0 */
+        REG(SR2.UINT32) &= ~SR2_START;
+
+    }
+    
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    (void)i2c_set_STOP(obj);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    int status;
+    int data;
+
+    data = i2c_do_read(obj, last);
+    /* wait for it to arrive */
+    status = i2c_wait_RDRF(obj);
+    if (status != 0) {
+        i2c_set_SR2_NACKF_STOP(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack = 0;
+    int status;
+    int timeout = 0;
+    
+    status = i2c_do_write(obj, (data & 0xFF));
+    if (status != 0) {
+        i2c_set_SR2_NACKF_STOP(obj);
+    } else {
+        while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
+            timeout++;
+            if (timeout >= WAIT_TIMEOUT) {
+                return ack;
+            }
+        }
+        /* check ACK/NACK */
+        if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
+            /* NACK */
+            i2c_set_SR2_NACKF_STOP(obj);
+        } else {
+            ack = 1;
+        }
+    }
+
+    return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave != 0) {
+        REG(SER.UINT32) |= SER_SAR0E;   // only slave addr 0 is enabled
+    } else {
+        REG(SER.UINT32) &= ~SER_SAR0E;  // no slave addr enabled
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    int status;
+    int retval;
+
+    status = (REG(SR1.UINT8[0]) & SR1_AAS0);
+    status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
+
+    switch(status) {
+        case 0x01:
+            /* the master is writing to this slave */
+            retval = 3;
+            break;
+        case 0x02:
+            /* the master is writing to all slave  */
+            retval = 2;
+            break;
+        case 0x03:
+            /* the master has requested a read from this slave */
+            retval = 1;
+            break;
+        default :
+            /* no data */
+            retval = 0;
+            break;
+    }
+
+    return retval;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    int timeout = 0;
+    int count;
+    int break_flg = 0;
+
+    if(length <= 0) {
+        return 0;
+    }
+    for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
+        /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+        while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
+            if ((i2c_status(obj) & SR2_STOP) != 0) {
+                break_flg = 1;
+                break;
+            }
+            timeout ++;
+            if (timeout >= WAIT_TIMEOUT) {
+                return -1;
+            }
+        }
+        if (break_flg == 0) {
+            if (count == 0) {
+                /* dummy read */
+                (void)REG(DRR.UINT32);
+            } else {
+                data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
+            }
+        }
+    }
+    if (break_flg == 0) {
+        (void)i2c_wait_STOP(obj);
+    } else {
+        if ((i2c_status(obj) & SR2_RDRF) != 0) {
+            if (count <= 1) {
+                /* fail safe */
+                /* dummy read */
+                (void)REG(DRR.UINT32);
+            } else {
+                data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
+            }
+        }
+    }
+    /* SR2.STOP = 0 */
+    REG(SR2.UINT32) &= ~SR2_STOP;
+
+    return (count - 1);
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    int count = 0;
+    int status = 0;
+
+    if(length <= 0) {
+        return 0;
+    }
+
+    while ((count < length) && (status == 0)) {
+        status = i2c_do_write(obj, data[count]);
+        if(status == 0) {
+            /* Wait send end */
+            status = i2c_wait_TEND(obj);
+            if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
+                /* NACK */
+                break;
+            }
+        }
+        count++;
+    }
+    /* dummy read */
+    (void)REG(DRR.UINT32);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+
+    return count;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    REG(SAR0.UINT32) = (address & 0xfffffffe);
+}
+
+#if DEVICE_I2C_ASYNCH
+
+#define IRQ_NUM 4
+#define IRQ_TX 0
+#define IRQ_RX 1
+#define IRQ_ERR1 2
+#define IRQ_ERR2 3
+
+static void i2c_irqs_set(i2c_t *obj, uint32_t enable);
+
+static void i2c0_tx_irq(void);
+static void i2c1_tx_irq(void);
+static void i2c2_tx_irq(void);
+static void i2c3_tx_irq(void);
+static void i2c0_rx_irq(void);
+static void i2c1_rx_irq(void);
+static void i2c2_rx_irq(void);
+static void i2c3_rx_irq(void);
+static void i2c0_al_irq(void);
+static void i2c1_al_irq(void);
+static void i2c2_al_irq(void);
+static void i2c3_al_irq(void);
+static void i2c0_to_irq(void);
+static void i2c1_to_irq(void);
+static void i2c2_to_irq(void);
+static void i2c3_to_irq(void);
+
+static const IRQn_Type irq_set_tbl[RIIC_COUNT][IRQ_NUM] = {
+    {INTIICTEI0_IRQn, INTIICRI0_IRQn, INTIICALI0_IRQn, INTIICTMOI0_IRQn},
+    {INTIICTEI1_IRQn, INTIICRI1_IRQn, INTIICALI1_IRQn, INTIICTMOI1_IRQn},
+    {INTIICTEI2_IRQn, INTIICRI2_IRQn, INTIICALI2_IRQn, INTIICTMOI2_IRQn},
+    {INTIICTEI3_IRQn, INTIICRI3_IRQn, INTIICALI3_IRQn, INTIICTMOI3_IRQn},
+};
+
+static const IRQHandler hander_set_tbl[RIIC_COUNT][IRQ_NUM] = {
+    {i2c0_tx_irq, i2c0_rx_irq, i2c0_al_irq, i2c0_to_irq},
+    {i2c1_tx_irq, i2c1_rx_irq, i2c1_al_irq, i2c1_to_irq},
+    {i2c2_tx_irq, i2c2_rx_irq, i2c2_al_irq, i2c2_to_irq},
+    {i2c3_tx_irq, i2c3_rx_irq, i2c3_al_irq, i2c3_to_irq},
+};
+
+struct i2c_global_data_s {
+    i2c_t *async_obj;
+    uint32_t async_callback, event, shouldStop, address;
+};
+
+static struct i2c_global_data_s i2c_data[RIIC_COUNT];
+
+static void i2c_transfer_finished(i2c_t *obj)
+{
+    i2c_irqs_set(obj, 0);
+    uint32_t index = obj->i2c.i2c;
+    i2c_data[index].event = I2C_EVENT_TRANSFER_COMPLETE;
+    i2c_data[index].async_obj = NULL;
+    ((void (*)())i2c_data[index].async_callback)();
+}
+
+static void i2c_tx_irq(IRQn_Type irq_num, uint32_t index)
+{
+    i2c_t *obj = i2c_data[index].async_obj;
+    if ((REG(SR2.UINT32) & SR2_NACKF)) {
+        /* Slave sends NACK */
+        i2c_set_err_noslave(obj);
+        i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
+        i2c_abort_asynch(obj);
+        ((void (*)())i2c_data[index].async_callback)();
+        return;
+    }
+    if (obj->tx_buff.pos == obj->tx_buff.length) {
+        /* All datas have tranferred */
+        
+        /* Clear TEND */
+        REG(SR2.UINT32) &= ~(SR2_TEND);
+        
+        /* If not repeated start, send stop. */
+        if (i2c_data[index].shouldStop && obj->rx_buff.length == 0) {
+            (void)i2c_set_STOP(obj);
+            (void)i2c_wait_STOP(obj);
+            i2c_set_SR2_NACKF_STOP(obj);
+            i2c_transfer_finished(obj);
+        } else {
+            (void)i2c_restart(obj);
+            (void)i2c_wait_START(obj);
+            /* SR2.START = 0 */
+            REG(SR2.UINT32) &= ~SR2_START;
+            if (obj->rx_buff.length) {
+                /* Ready to read */
+                i2c_set_MR3_ACK(obj);
+                
+                /* Disable INTRIICTEI */
+                REG(IER.UINT8[0]) &= ~(1 << 6);
+                
+                /*  Send Slave address */
+                if (i2c_read_address_write(obj, (i2c_data[index].address | 0x01)) != 0) {
+                    i2c_set_err_noslave(obj);
+                    i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+                    i2c_abort_asynch(obj);
+                    ((void (*)())i2c_data[index].async_callback)();
+                    return;
+                }
+            } else {
+                i2c_transfer_finished(obj);
+            }
+        }
+    } else {
+        /* Send next 1 byte */
+        if (i2c_do_write(obj, *(uint8_t *)obj->tx_buff.buffer) != 0) {
+            i2c_set_err_noslave(obj);
+            i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+            i2c_abort_asynch(obj);
+            ((void (*)())i2c_data[index].async_callback)();
+            return;
+        }
+        obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
+        ++obj->tx_buff.pos;
+    }
+}
+
+static void i2c_rx_irq(IRQn_Type irq_num, uint32_t index)
+{
+    i2c_t *obj = i2c_data[index].async_obj;
+    if (obj->rx_buff.pos == SIZE_MAX) {
+        if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
+            /* Slave sends NACK */
+            (void)i2c_set_STOP(obj);
+            /* dummy read */
+            if (REG(DRR.UINT32)) {}
+            (void)i2c_wait_STOP(obj);
+            i2c_set_SR2_NACKF_STOP(obj);
+            obj->i2c.last_stop_flag = 1;
+            
+            i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
+            i2c_abort_asynch(obj);
+            ((void (*)())i2c_data[index].async_callback)();
+            return;
+        }
+        if (obj->rx_buff.length == 1) {
+            /* length == 1 */
+            /* Set MR3 WAIT bit is 1 */;
+            REG(MR3.UINT32) |=  MR3_WAIT;
+            i2c_set_MR3_NACK(obj);
+        } else if (obj->rx_buff.length == 2) {
+            /* Set MR3 WAIT bit is 1 */
+            REG(MR3.UINT32) |= MR3_WAIT;
+        }
+        /* dummy read */
+        if (REG(DRR.UINT32)) {}
+        obj->rx_buff.pos = 0;
+        return;
+    }
+    if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
+        /* Slave sends NACK */
+        i2c_set_err_noslave(obj);
+        i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
+        i2c_abort_asynch(obj);
+        ((void (*)())i2c_data[index].async_callback)();
+        return;
+    } else {
+        switch (obj->rx_buff.length - obj->rx_buff.pos) {
+            case 1:
+                /* Finished */
+                /* If not repeated start, send stop. */
+                if (i2c_data[index].shouldStop) {
+                    (void)i2c_set_STOP(obj);
+                    /* RIICnDRR read */
+                    *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
+                    /* RIICnMR3.WAIT = 0 */
+                    REG(MR3.UINT32) &= ~MR3_WAIT;
+                    (void)i2c_wait_STOP(obj);
+                    i2c_set_SR2_NACKF_STOP(obj);
+                } else {
+                    (void)i2c_restart(obj);
+                    /* RIICnDRR read */
+                    *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
+                    /* RIICnMR3.WAIT = 0 */
+                    REG(MR3.UINT32) &= ~MR3_WAIT;
+                    (void)i2c_wait_START(obj);
+                    /* SR2.START = 0 */
+                    REG(SR2.UINT32) &= ~SR2_START;
+                }
+                
+                i2c_transfer_finished(obj);
+                return;
+                
+            case 2:
+                i2c_set_MR3_NACK(obj);
+                break;
+                
+            case 3:
+                /* this time is befor last byte read */
+                /* Set MR3 WAIT bit is 1 */
+                REG(MR3.UINT32) |= MR3_WAIT;
+                break;
+                
+            default:
+                i2c_set_MR3_ACK(obj);
+                break;
+        }
+        *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
+        obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + 1;
+        ++obj->rx_buff.pos;
+    }
+}
+
+static void i2c_err_irq(IRQn_Type irq_num, uint32_t index)
+{
+    i2c_t *obj = i2c_data[index].async_obj;
+    i2c_abort_asynch(obj);
+    i2c_data[index].event = I2C_EVENT_ERROR;
+    ((void (*)())i2c_data[index].async_callback)();
+}
+
+/* TX handler */
+static void i2c0_tx_irq(void)
+{
+    i2c_tx_irq(INTIICTEI0_IRQn, 0);
+}
+
+static void i2c1_tx_irq(void)
+{
+    i2c_tx_irq(INTIICTEI1_IRQn, 1);
+}
+
+static void i2c2_tx_irq(void)
+{
+    i2c_tx_irq(INTIICTEI2_IRQn, 2);
+}
+
+static void i2c3_tx_irq(void)
+{
+    i2c_tx_irq(INTIICTEI3_IRQn, 3);
+}
+
+/* RX handler */
+static void i2c0_rx_irq(void)
+{
+    i2c_rx_irq(INTIICRI0_IRQn, 0);
+}
+
+static void i2c1_rx_irq(void)
+{
+    i2c_rx_irq(INTIICRI1_IRQn, 1);
+}
+
+static void i2c2_rx_irq(void)
+{
+    i2c_rx_irq(INTIICRI2_IRQn, 2);
+}
+
+static void i2c3_rx_irq(void)
+{
+    i2c_rx_irq(INTIICRI3_IRQn, 3);
+}
+
+/* Arbitration Lost handler */
+static void i2c0_al_irq(void)
+{
+    i2c_err_irq(INTIICALI0_IRQn, 0);
+}
+
+static void i2c1_al_irq(void)
+{
+    i2c_err_irq(INTIICALI1_IRQn, 1);
+}
+
+static void i2c2_al_irq(void)
+{
+    i2c_err_irq(INTIICALI2_IRQn, 2);
+}
+
+static void i2c3_al_irq(void)
+{
+    i2c_err_irq(INTIICALI3_IRQn, 3);
+}
+
+/* Timeout handler */
+static void i2c0_to_irq(void)
+{
+    i2c_err_irq(INTIICTMOI0_IRQn, 0);
+}
+
+static void i2c1_to_irq(void)
+{
+    i2c_err_irq(INTIICTMOI1_IRQn, 1);
+}
+
+static void i2c2_to_irq(void)
+{
+    i2c_err_irq(INTIICTMOI2_IRQn, 2);
+}
+
+static void i2c3_to_irq(void)
+{
+    i2c_err_irq(INTIICTMOI3_IRQn, 3);
+}
+
+static void i2c_irqs_set(i2c_t *obj, uint32_t enable)
+{
+    int i;
+    const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.i2c];
+    const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.i2c];
+    for (i = 0; i < IRQ_NUM; ++i) {
+        if (enable) {
+            InterruptHandlerRegister(irqTable[i], handlerTable[i]);
+            GIC_SetPriority(irqTable[i], 5);
+            if (i == 1) {
+                GIC_SetConfiguration(irqTable[i], 3);
+            } else {
+                GIC_SetConfiguration(irqTable[i], 1);
+            }
+            GIC_EnableIRQ(irqTable[i]);
+        } else {
+            GIC_DisableIRQ(irqTable[i]);
+        }
+    }
+    REG(IER.UINT8[0]) = enable ? 0x63 : 0x00;
+}
+
+/******************************************************************************
+ * ASYNCHRONOUS HAL
+ ******************************************************************************/
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    MBED_ASSERT(obj);
+    MBED_ASSERT(tx ? tx_length : 1);
+    MBED_ASSERT(rx ? rx_length : 1);
+    MBED_ASSERT((REG(SER.UINT32) & SER_SAR0E) == 0); /* Slave mode */
+    
+    obj->tx_buff.buffer = (void *)tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = 8;
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = SIZE_MAX;
+    obj->rx_buff.width = 8;
+    i2c_data[obj->i2c.i2c].async_obj = obj;
+    i2c_data[obj->i2c.i2c].async_callback = handler;
+    i2c_data[obj->i2c.i2c].event = 0;
+    i2c_data[obj->i2c.i2c].shouldStop = stop;
+    i2c_data[obj->i2c.i2c].address = address;
+    i2c_irqs_set(obj, 1);
+    
+    /* There is a STOP condition for last processing */
+    if (obj->i2c.last_stop_flag != 0) {
+        if (i2c_start(obj) != 0) {
+            i2c_set_err_noslave(obj);
+            i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+            i2c_abort_asynch(obj);
+            ((void (*)())handler)();
+            return;
+        }
+    }
+    obj->i2c.last_stop_flag = stop;
+    
+    if (rx_length && tx_length == 0) {
+        /* Ready to read */
+        i2c_set_MR3_ACK(obj);
+        
+        /* Disable INTRIICTEI */
+        REG(IER.UINT8[0]) &= ~(1 << 6);
+        
+        address |= 0x01;
+    }
+    /* Send Slave address */
+    if (i2c_do_write(obj, address) != 0) {
+        i2c_set_err_noslave(obj);
+        i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+        i2c_abort_asynch(obj);
+        ((void (*)())handler)();
+        return;
+    }
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+    return i2c_data[obj->i2c.i2c].event;
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{
+    return i2c_data[obj->i2c.i2c].async_obj != NULL;
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+    i2c_data[obj->i2c.i2c].async_obj = NULL;
+    i2c_irqs_set(obj, 0);
+    i2c_reg_reset(obj);
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/lp_ticker.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/lp_ticker.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/lp_ticker.c	(revision 374)
@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#if DEVICE_LPTICKER
+#include "lp_ticker_api.h"
+#include "mtu2_iodefine.h"
+#include "mtu2_iobitmask.h"
+#include "mbed_drv_cfg.h"
+#include "mtu2.h"
+
+#if (LP_TICKER_MTU2_CH == 2)
+ #define LP_TICKER_TIMER_IRQn (TGI2A_IRQn)
+ #define MTU2TCR              (MTU2TCR_2)
+ #define MTU2TCNT             (MTU2TCNT_2)
+ #define MTU2TIER             (MTU2TIER_2)
+ #define MTU2TGRA             (MTU2TGRA_2)
+ #define MTU2TSR              (MTU2TSR_2)
+ #define MTU2_TSTR_CST        MTU2_TSTR_CST2
+ #define MTU2_TCR_TPSC        (0x07)
+#elif (LP_TICKER_MTU2_CH == 3)
+ #define LP_TICKER_TIMER_IRQn (TGI3A_IRQn)
+ #define MTU2TCR              (MTU2TCR_3)
+ #define MTU2TCNT             (MTU2TCNT_3)
+ #define MTU2TIER             (MTU2TIER_3)
+ #define MTU2TGRA             (MTU2TGRA_3)
+ #define MTU2TSR              (MTU2TSR_3)
+ #define MTU2_TSTR_CST        MTU2_TSTR_CST3
+ #define MTU2_TCR_TPSC        (0x05)
+#elif (LP_TICKER_MTU2_CH == 4)
+ #define LP_TICKER_TIMER_IRQn (TGI4A_IRQn)
+ #define MTU2TCR              (MTU2TCR_4)
+ #define MTU2TCNT             (MTU2TCNT_4)
+ #define MTU2TIER             (MTU2TIER_4)
+ #define MTU2TGRA             (MTU2TGRA_4)
+ #define MTU2TSR              (MTU2TSR_4)
+ #define MTU2_TSTR_CST        MTU2_TSTR_CST4
+ #define MTU2_TCR_TPSC        (0x05)
+#else
+ #error "Invalid number : LP_TICKER_MTU2_CH (2-4)"
+#endif
+
+static int lp_ticker_inited = 0;
+
+void lp_ticker_init(void)
+{
+    GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
+    GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
+
+    /* Power Control for Peripherals      */
+    mtu2_init();
+
+    if (lp_ticker_inited) return;
+    lp_ticker_inited = 1;
+
+    MTU2TCR   = MTU2_TCR_TPSC;
+    MTU2TSTR  |= MTU2_TSTR_CST;
+    MTU2TIER  |= MTU2_TIER_n_TGIEA;
+
+    // INTC settings
+    InterruptHandlerRegister(LP_TICKER_TIMER_IRQn, (void (*)(uint32_t))lp_ticker_irq_handler);
+    GIC_SetPriority(LP_TICKER_TIMER_IRQn, 5);
+    GIC_SetConfiguration(LP_TICKER_TIMER_IRQn, 3);
+}
+
+void lp_ticker_free(void)
+{
+    GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
+    GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
+
+    MTU2TIER  &= ~MTU2_TIER_n_TGIEA;
+    lp_ticker_inited = 0;
+    mtu2_free();
+}
+
+uint32_t lp_ticker_read()
+{
+    return (uint32_t)MTU2TCNT;
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    MTU2TSR = (MTU2TSR & 0xFE);
+    MTU2TGRA = (uint16_t)timestamp;
+    GIC_EnableIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+    GIC_SetPendingIRQ(LP_TICKER_TIMER_IRQn);
+    GIC_EnableIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+    MTU2TSR = (MTU2TSR & 0xFE);
+    GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+const ticker_info_t* lp_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        (uint32_t)((float)RENESAS_RZ_A1_P0_CLK / 1024.0f + 0.5f),
+        16
+    };
+    return &info;
+}
+
+#endif // DEVICE_LPTICKER
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/mtu2.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/mtu2.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/mtu2.c	(revision 374)
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_drv_cfg.h"
+
+#if (defined(FUMC_MTU2_PWM) || defined(DEVICE_LPTICKER))
+#include "mtu2.h"
+
+static int mtu2_used_cnt = 0;
+
+void mtu2_init(void)
+{
+    if (mtu2_used_cnt == 0) {
+        CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
+    }
+    if (mtu2_used_cnt < 256) {
+        mtu2_used_cnt++;
+    }
+}
+
+void mtu2_free(void)
+{
+    if (mtu2_used_cnt > 0) {
+        mtu2_used_cnt--;
+    }
+    if (mtu2_used_cnt == 0) {
+        CPGSTBCR3 |= (CPG_STBCR3_BIT_MSTP33);
+    }
+}
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/mtu2.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/mtu2.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/mtu2.h	(revision 374)
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MTU2_H
+#define MTU2_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void mtu2_init(void);
+void mtu2_free(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/objects.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/objects.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/objects.h	(revision 374)
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include <stdint.h>
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct i2c_s {
+    uint32_t i2c;
+    uint32_t dummy;
+    uint8_t  pclk_bit;
+    uint8_t  width_low;
+    uint8_t  width_hi;
+    int      bbsy_wait_cnt;
+    int      last_stop_flag;
+};
+
+struct spi_s {
+    struct st_rspi *spi;
+    uint32_t       bits;
+    int            index;
+};
+
+struct gpio_irq_s {
+    uint32_t port;
+    uint32_t pin;
+    uint32_t ch;
+    uint8_t  int_enable;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+    __IO uint32_t *reg_buf;
+    PortName port;
+    uint32_t mask;
+};
+
+struct serial_s {
+    struct st_scif *uart;
+    int index;
+};
+
+struct pwmout_s {
+    uint32_t ch;
+    PWMName pwm;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+struct can_s {
+    uint32_t ch;
+};
+
+struct trng_s {
+    uint8_t dummy;
+};
+
+struct flash_s {
+    uint8_t dummy;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/pinmap.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/pinmap.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/pinmap.c	(revision 374)
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "PeripheralPins.h"
+#include "mbed_error.h"
+#include "gpio_addrdefine.h"
+
+PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
+
+void pin_function(PinName pin, int function) {
+    if (pin == (PinName)NC) return;
+    
+    int n = pin >> 4;
+    int bitmask = 1<<(pin  & 0xf);
+    const PinFunc * Pipc_0_func = PIPC_0_tbl;
+    int pipc_data = 1;
+    
+    if (gpio_multi_guard != pin) {
+        if (function == 0) {
+            // means GPIO mode
+            *PMC(n) &= ~bitmask;
+        } else {
+            // alt-function mode
+            --function;
+
+            if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else  { *PFCAE(n) &= ~bitmask;}
+            if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else  { *PFCE(n) &= ~bitmask;}
+            if (function & (1 << 0)) { *PFC(n) |= bitmask;}else  { *PFC(n) &= ~bitmask;}
+
+            while (Pipc_0_func->pin != NC) {
+                if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) {
+                    pipc_data = 0;
+                    if (Pipc_0_func->pm == 0) {
+                        *PMSR(n) = (bitmask << 16) | 0;
+                    } else if (Pipc_0_func->pm == 1) {
+                        *PMSR(n) = (bitmask << 16) | bitmask;
+                    } else {
+                        // Do Nothing
+                    }
+                    break;
+                }
+                Pipc_0_func++;
+            }
+            if (pipc_data == 1) {
+            *PIPC(n) |= bitmask;
+            } else {
+                *PIPC(n) &= ~bitmask;
+            }
+
+            if (P1_0 <= pin && pin <= P1_7 && function == 0) {
+                *PBDC(n) |= bitmask;
+            }
+            *PMC(n) |= bitmask;
+        }
+    } else {
+        gpio_multi_guard = (PinName)NC;
+    }
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+//    if (pin == (PinName)NC) { return; }
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/port_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/port_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/port_api.c	(revision 374)
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "gpio_addrdefine.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)((port*0x10)+pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    uint32_t i;
+
+    obj->port = port;
+    obj->mask = mask;
+    obj->reg_dir = (volatile uint32_t *)PMSR(port);
+    obj->reg_out = (volatile uint32_t *)PORT(port);
+    obj->reg_in  = (volatile uint32_t *)PPR(port);
+    obj->reg_buf = (volatile uint32_t *)PIBC(port);
+    // Do not use masking, because it prevents the use of the unmasked pins
+    // port_reg->FIOMASK = ~mask;
+    
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir = (obj->mask << 16) | obj->mask;
+             *obj->reg_buf |=  obj->mask;
+        break;
+        case PIN_OUTPUT: *obj->reg_dir = (obj->mask << 16) | ~obj->mask;
+             *obj->reg_buf &= ~obj->mask;
+        break;
+        default:
+            // do nothing
+        break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_out = (obj->mask << 16) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_in & obj->mask);
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/pwmout_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/pwmout_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/pwmout_api.c	(revision 374)
@@ -0,0 +1,569 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "PeripheralPins.h"
+#include "RZ_A1_Init.h"
+#include "iodefine.h"
+#include "gpio_addrdefine.h"
+#include "mbed_drv_cfg.h"
+#include "mtu2.h"
+
+#define MTU2_PWM_OFFSET         0x20
+
+#ifdef FUNC_MOTOR_CTL_PWM
+typedef enum {
+    PWM1A  = 0,
+    PWM1B,
+    PWM1C,
+    PWM1D,
+    PWM1E,
+    PWM1F,
+    PWM1G,
+    PWM1H,
+    PWM2A  = 0x10,
+    PWM2B,
+    PWM2C,
+    PWM2D,
+    PWM2E,
+    PWM2F,
+    PWM2G,
+    PWM2H,
+} PWMType;
+
+static const PWMType PORT[] = {
+     PWM1A,          // PWM_PWM1A
+     PWM1B,          // PWM_PWM1B
+     PWM1C,          // PWM_PWM1C
+     PWM1D,          // PWM_PWM1D
+     PWM1E,          // PWM_PWM1E
+     PWM1F,          // PWM_PWM1F
+     PWM1G,          // PWM_PWM1G
+     PWM1H,          // PWM_PWM1H
+     PWM2A,          // PWM_PWM2A
+     PWM2B,          // PWM_PWM2B
+     PWM2C,          // PWM_PWM2C
+     PWM2D,          // PWM_PWM2D
+     PWM2E,          // PWM_PWM2E
+     PWM2F,          // PWM_PWM2F
+     PWM2G,          // PWM_PWM2G
+     PWM2H,          // PWM_PWM2H
+};
+
+static __IO uint16_t *PWM_MATCH[] = {
+    &PWMPWBFR_1A,    // PWM_PWM1A
+    &PWMPWBFR_1A,    // PWM_PWM1B
+    &PWMPWBFR_1C,    // PWM_PWM1C
+    &PWMPWBFR_1C,    // PWM_PWM1D
+    &PWMPWBFR_1E,    // PWM_PWM1E
+    &PWMPWBFR_1E,    // PWM_PWM1F
+    &PWMPWBFR_1G,    // PWM_PWM1G
+    &PWMPWBFR_1G,    // PWM_PWM1H
+    &PWMPWBFR_2A,    // PWM_PWM2A
+    &PWMPWBFR_2A,    // PWM_PWM2B
+    &PWMPWBFR_2C,    // PWM_PWM2C
+    &PWMPWBFR_2C,    // PWM_PWM2D
+    &PWMPWBFR_2E,    // PWM_PWM2E
+    &PWMPWBFR_2E,    // PWM_PWM2F
+    &PWMPWBFR_2G,    // PWM_PWM2G
+    &PWMPWBFR_2G,    // PWM_PWM2H
+};
+
+static uint16_t init_period_ch1 = 0;
+static uint16_t init_period_ch2 = 0;
+static int32_t  period_ch1 = 1;
+static int32_t  period_ch2 = 1;
+#endif
+
+#ifdef FUMC_MTU2_PWM
+#define MTU2_PWM_SIGNAL         2
+
+typedef enum {
+    TIOC0A  = 0,
+    TIOC0B,
+    TIOC0C,
+    TIOC0D,
+    TIOC1A = 0x10,
+    TIOC1B,
+    TIOC2A = 0x20,
+    TIOC2B,
+    TIOC3A = 0x30,
+    TIOC3B,
+    TIOC3C,
+    TIOC3D,
+    TIOC4A = 0x40,
+    TIOC4B,
+    TIOC4C,
+    TIOC4D,
+} MTU2_PWMType;
+
+static const MTU2_PWMType MTU2_PORT[] = {
+     TIOC0A,         // PWM_TIOC0A
+     TIOC0C,         // PWM_TIOC0C
+     TIOC1A,         // PWM_TIOC1A
+     TIOC2A,         // PWM_TIOC2A
+     TIOC3A,         // PWM_TIOC3A
+     TIOC3C,         // PWM_TIOC3C
+     TIOC4A,         // PWM_TIOC4A
+     TIOC4C,         // PWM_TIOC4C
+};
+
+static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = {
+    { &MTU2TGRA_0, &MTU2TGRB_0 },       // PWM_TIOC0A
+    { &MTU2TGRC_0, &MTU2TGRD_0 },       // PWM_TIOC0C
+    { &MTU2TGRA_1, &MTU2TGRB_1 },       // PWM_TIOC1A
+    { &MTU2TGRA_2, &MTU2TGRB_2 },       // PWM_TIOC2A
+    { &MTU2TGRA_3, &MTU2TGRB_3 },       // PWM_TIOC3A
+    { &MTU2TGRC_3, &MTU2TGRD_3 },       // PWM_TIOC3C
+    { &MTU2TGRA_4, &MTU2TGRB_4 },       // PWM_TIOC4A
+    { &MTU2TGRC_4, &MTU2TGRD_4 },       // PWM_TIOC4C
+};
+
+static __IO uint8_t *TCR_MATCH[] = {
+    &MTU2TCR_0,
+    &MTU2TCR_1,
+    &MTU2TCR_2,
+    &MTU2TCR_3,
+    &MTU2TCR_4,
+};
+
+static __IO uint8_t *TIORH_MATCH[] = {
+    &MTU2TIORH_0,
+    &MTU2TIOR_1,
+    &MTU2TIOR_2,
+    &MTU2TIORH_3,
+    &MTU2TIORH_4,
+};
+
+static __IO uint8_t *TIORL_MATCH[] = {
+    &MTU2TIORL_0,
+    NULL,
+    NULL,
+    &MTU2TIORL_3,
+    &MTU2TIORL_4,
+};
+
+static __IO uint16_t *TGRA_MATCH[] = {
+    &MTU2TGRA_0,
+    &MTU2TGRA_1,
+    &MTU2TGRA_2,
+    &MTU2TGRA_3,
+    &MTU2TGRA_4,
+};
+
+static __IO uint16_t *TGRC_MATCH[] = {
+    &MTU2TGRC_0,
+    NULL,
+    NULL,
+    &MTU2TGRC_3,
+    &MTU2TGRC_4,
+};
+
+static __IO uint8_t *TMDR_MATCH[] = {
+    &MTU2TMDR_0,
+    &MTU2TMDR_1,
+    &MTU2TMDR_2,
+    &MTU2TMDR_3,
+    &MTU2TMDR_4,
+};
+
+static int MAX_PERIOD[] = {
+    125000,
+    503000,
+    2000000,
+    2000000,
+    2000000,
+};
+
+typedef enum {
+    MTU2_PULSE = 0,
+    MTU2_PERIOD
+} MTU2Signal;
+
+static uint16_t init_mtu2_period_ch[5] = {0};
+static int32_t  mtu2_period_ch[5] = {1, 1, 1, 1, 1};
+#endif
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // determine the channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    MBED_ASSERT(pwm != (PWMName)NC);
+
+    if (pwm >= MTU2_PWM_OFFSET) {
+#ifdef FUMC_MTU2_PWM
+        /* PWM by MTU2 */
+        int tmp_pwm;
+        
+        // power on
+        mtu2_init();
+        
+        obj->pwm = pwm;
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
+            obj->ch  = 4;
+            MTU2TOER |= 0x36;
+        } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
+            obj->ch  = 3;
+            MTU2TOER |= 0x09;
+        } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
+            obj->ch  = 2;
+        } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
+            obj->ch  = 1;
+        } else {
+            obj->ch  = 0;
+        }
+        // Wire pinout
+        pinmap_pinout(pin, PinMap_PWM);
+
+        int bitmask = 1 << (pin  & 0xf);
+
+        *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0;
+
+        // default duty 0.0f
+        pwmout_write(obj, 0);
+        if (init_mtu2_period_ch[obj->ch] == 0) {
+            // default period 1ms
+            pwmout_period_us(obj, 1000);
+            init_mtu2_period_ch[obj->ch] = 1;
+        }
+#endif
+    } else {
+#ifdef FUNC_MOTOR_CTL_PWM
+        /* PWM */
+        // power on
+        CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
+
+        obj->pwm = pwm;
+        if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
+            obj->ch  = 2;
+            PWMPWPR_2 = 0x00;
+        } else {
+            obj->ch  = 1;
+            PWMPWPR_1 = 0x00;
+        }
+
+        // Wire pinout
+        pinmap_pinout(pin, PinMap_PWM);
+
+        // default to 491us: standard for servos, and fine for e.g. brightness control
+        pwmout_write(obj, 0);
+        if ((obj->ch == 2) && (init_period_ch2 == 0)) {
+            pwmout_period_us(obj, 491);
+            init_period_ch2 = 1;
+        }
+        if ((obj->ch == 1) && (init_period_ch1 == 0)) {
+            pwmout_period_us(obj, 491);
+            init_period_ch1 = 1;
+        }
+#endif
+    }
+}
+
+void pwmout_free(pwmout_t* obj) {
+    pwmout_write(obj, 0);
+    mtu2_free();
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    uint32_t wk_cycle;
+
+    if (obj->pwm >= MTU2_PWM_OFFSET) {
+#ifdef FUMC_MTU2_PWM
+        /* PWM by MTU2 */
+        int tmp_pwm;
+        
+        if (value < 0.0f) {
+            value = 0.0f;
+        } else if (value > 1.0f) {
+            value = 1.0f;
+        } else {
+            // Do Nothing
+        }
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+        // set channel match to percentage
+        if (value == 1.0f) {
+            *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1);
+        } else {
+        *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
+        }
+#endif
+    } else {
+#ifdef FUNC_MOTOR_CTL_PWM
+        uint16_t v;
+
+        /* PWM */
+        if (value < 0.0f) {
+            value = 0.0f;
+        } else if (value > 1.0f) {
+            value = 1.0f;
+        } else {
+            // Do Nothing
+        }
+
+        if (obj->ch == 2) {
+            wk_cycle = PWMPWCYR_2 & 0x03ff;
+        } else {
+            wk_cycle = PWMPWCYR_1 & 0x03ff;
+        }
+
+        // set channel match to percentage
+        v = (uint16_t)((float)wk_cycle * value);
+        *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
+#endif
+    }
+}
+
+float pwmout_read(pwmout_t* obj) {
+    uint32_t wk_cycle;
+    float value;
+
+    if (obj->pwm >= MTU2_PWM_OFFSET) {
+#ifdef FUMC_MTU2_PWM
+        /* PWM by MTU2 */
+        uint32_t wk_pulse;
+        int tmp_pwm;
+        
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+        wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
+        value = ((float)wk_pulse / (float)wk_cycle);
+#endif
+    } else {
+#ifdef FUNC_MOTOR_CTL_PWM
+        /* PWM */
+        if (obj->ch == 2) {
+            wk_cycle = PWMPWCYR_2 & 0x03ff;
+        } else {
+            wk_cycle = PWMPWCYR_1 & 0x03ff;
+        }
+        value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
+#endif
+    }
+
+    return (value > 1.0f) ? (1.0f) : (value);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+#ifdef FUNC_MOTOR_CTL_PWM
+static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
+    uint16_t wk_pwmpbfr;
+    float    value;
+    uint16_t v;
+
+    wk_pwmpbfr = *p_pwmpbfr;
+    value      = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
+    v          = (uint16_t)((float)new_cycle * value);
+    *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
+}
+#endif
+
+#ifdef FUMC_MTU2_PWM
+static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
+    uint16_t wk_pwmpbfr;
+    float    value;
+
+    wk_pwmpbfr = *p_pwmpbfr;
+    value      = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
+    *p_pwmpbfr = (uint16_t)((float)new_cycle * value);
+}
+#endif
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    uint32_t pclk_base;
+    uint32_t wk_cycle;
+    uint32_t wk_cks = 0;
+    uint16_t wk_last_cycle;
+
+    if (obj->pwm >= MTU2_PWM_OFFSET) {
+#ifdef FUMC_MTU2_PWM
+        uint64_t wk_cycle_mtu2;
+        int      max_us = 0;
+
+        /* PWM by MTU2 */
+        int tmp_pwm;
+        uint8_t tmp_tcr_up;
+        uint8_t tmp_tstr_sp;
+        uint8_t tmp_tstr_st;
+        
+        max_us = MAX_PERIOD[obj->ch];
+        if (us > max_us) {
+            us = max_us;
+        } else if (us < 1) {
+            us = 1;
+        } else {
+            // Do Nothing
+        }
+
+        if (RZ_A1_IsClockMode0() == false) {
+            pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
+        } else {
+            pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
+        }
+
+        wk_cycle_mtu2 = (uint64_t)pclk_base * us;
+        while (wk_cycle_mtu2 >= 65535000000) {
+            if ((obj->ch == 1) && (wk_cks == 3)) {
+                wk_cks+=2;
+            } else if ((obj->ch == 2) && (wk_cks == 3)) {
+                wk_cycle_mtu2 >>= 2;
+                wk_cks+=3;
+            }
+            wk_cycle_mtu2 >>= 2;
+            wk_cks++;
+        }
+        wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
+        
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
+            tmp_tcr_up = 0xC0;
+        } else {
+            tmp_tcr_up = 0x40;
+        }
+        if ((obj->ch == 4) || (obj->ch == 3)) {
+            tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
+            tmp_tstr_st = (1 << (obj->ch + 3));
+        } else {
+            tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
+            tmp_tstr_st = (1 << obj->ch);
+        }
+        // Counter Stop
+        MTU2TSTR &= tmp_tstr_sp;
+        wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+        *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
+        *TIORH_MATCH[obj->ch] = 0x21;
+        if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
+            *TIORL_MATCH[obj->ch] = 0x21;
+        }
+        *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle;     // Set period
+
+        // Set duty again(TGRA)
+        set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
+        if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
+            // Set duty again(TGRC)
+            set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
+        }
+        *TMDR_MATCH[obj->ch] = 0x02;                                    // PWM mode 1
+
+        // Counter Start
+        MTU2TSTR |= tmp_tstr_st;
+        // Save for future use
+        mtu2_period_ch[obj->ch] = us;
+#endif
+    } else {
+#ifdef FUNC_MOTOR_CTL_PWM
+        /* PWM */
+        if (us > 491) {
+            us = 491;
+        } else if (us < 1) {
+            us = 1;
+        } else {
+            // Do Nothing
+        }
+
+        if (RZ_A1_IsClockMode0() == false) {
+            pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
+        } else {
+            pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
+        }
+
+        wk_cycle = pclk_base * us;
+        while (wk_cycle >= 102350) {
+            wk_cycle >>= 1;
+            wk_cks++;
+        }
+        wk_cycle = (wk_cycle + 50) / 100;
+
+        if (obj->ch == 2) {
+            wk_last_cycle    = PWMPWCYR_2 & 0x03ff;
+            PWMPWCR_2        = 0xc0 | wk_cks;
+            PWMPWCYR_2       = (uint16_t)wk_cycle;
+
+            // Set duty again
+            set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
+
+            // Counter Start
+            PWMPWCR_2 |= 0x08;
+
+            // Save for future use
+            period_ch2 = us;
+        } else {
+            wk_last_cycle    = PWMPWCYR_1 & 0x03ff;
+            PWMPWCR_1        = 0xc0 | wk_cks;
+            PWMPWCYR_1       = (uint16_t)wk_cycle;
+
+            // Set duty again
+            set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
+
+            // Counter Start
+            PWMPWCR_1 |= 0x08;
+
+            // Save for future use
+            period_ch1 = us;
+        }
+#endif
+    }
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    float value = 0;
+
+    if (obj->pwm >= MTU2_PWM_OFFSET) {
+#ifdef FUMC_MTU2_PWM
+        /* PWM by MTU2 */
+        if (mtu2_period_ch[obj->ch] != 0) {
+            value = (float)us / (float)mtu2_period_ch[obj->ch];
+        }
+#endif
+    } else {
+#ifdef FUNC_MOTOR_CTL_PWM
+        /* PWM */
+        if (obj->ch == 2) {
+            if (period_ch2 != 0) {
+                value = (float)us / (float)period_ch2;
+            }
+        } else {
+            if (period_ch1 != 0) {
+                value = (float)us / (float)period_ch1;
+            }
+        }
+#endif
+    }
+    pwmout_write(obj, value);
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/rtc_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/rtc_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/rtc_api.c	(revision 374)
@@ -0,0 +1,365 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include "rtc_api.h"
+#include "iodefine.h"
+#include "mbed_drv_cfg.h"
+#include "mbed_mktime.h"
+
+#define RCR1_VAL_ON      (0x08u) // AIE = 1
+#define RCR1_VAL_OFF     (0x00u)
+#define RCR3_VAL         (0x00u)
+#define RCR5_VAL		 (0x00u)
+
+#ifdef USE_RTCX1_CLK
+#define RCR2_VAL_ALLSTOP (0x08u)
+#define RCR2_VAL_START   (0x09u) // START = 1
+#define RCR2_VAL_RESET   (0x0Au) // RESET = 1
+#define RCR5_VAL_RTCX1   (0x00u) // RCKSEL = clock rtc from RTCX1(32.768 kHz)
+#elif defined(USE_EXTAL_CLK)
+#define RCR2_VAL_ALLSTOP (0x00u)
+#define RCR2_VAL_START   (0x01u) // START = 1
+#define RCR2_VAL_RESET   (0x02u) // RESET = 1
+#define RCR5_VAL_EXTAL   (0x01u) // RCKSEL = clock rtc from EXTAL
+#define RFRH_VAL_13333   (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) 
+#define RFRL_VAL_13333   (0x2DCDu) //
+#elif defined(USE_RTCX3_CLK)
+#define RCR2_VAL_ALLSTOP (0x08u)
+#define RCR2_VAL_START   (0x09u) // START = 1
+#define RCR2_VAL_RESET   (0x0Au) // RESET = 1
+#define RCR5_VAL_RTCX3	 (0x02u) // RCKSEL = clock rtc from RTCX3(4.000 MHz)
+#define RFRH_VAL_4000   (0x8000u) // 4.000MHz (= 64Hz * 0xF424)
+#define RFRL_VAL_4000   (0xF424u) //
+#else
+#error Select RTC clock input !
+#endif
+
+#define RFRH_VAL_MAX     (0x0007u) // MAX value (= 128Hz * 0x7FFFF)
+#define RFRL_VAL_MAX     (0xFFFFu) //
+
+#define MASK_00_03_POS   (0x000Fu)
+#define MASK_04_07_POS   (0x00F0u)
+#define MASK_08_11_POS   (0x0F00u)
+#define MASK_12_15_POS   (0xF000u)
+#define MASK_16_20_POS   (0x000F0000u)
+#define SHIFT_1_HBYTE    (4u)
+#define SHIFT_2_HBYTE    (8u)
+#define SHIFT_3_HBYTE    (12u)
+#define SHIFT_1BYTE      (8u)
+#define SHIFT_2BYTE      (16u)
+
+#define TIME_ERROR_VAL   (0u)
+
+static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val);
+static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val);
+static uint8_t rtc_hex8_to_dec(uint8_t hex_val);
+static uint16_t rtc_hex16_to_dec(uint16_t hex_val);
+
+
+/*
+ * Setup the RTC based on a time structure.
+ * The rtc_init function should be executed first.
+ * [in]
+ * None.
+ * [out]
+ * None.
+ */
+void rtc_init(void)
+{
+    volatile uint8_t dummy_read;
+
+    CPG.STBCR6 &= ~(CPG_STBCR6_BIT_MSTP60);
+
+    // Set control register
+    RTC.RCR2 = RCR2_VAL_ALLSTOP;
+    RTC.RCR1 = RCR1_VAL_ON;
+    RTC.RCR3 = RCR3_VAL;
+
+#ifdef USE_RTCX1_CLK
+    RTC.RCR5 = RCR5_VAL_RTCX1;
+    RTC.RFRH = 0;
+    RTC.RFRL = 0;
+#elif defined(USE_EXTAL_CLK)
+    RTC.RCR5 = RCR5_VAL_EXTAL;
+    RTC.RFRH = RFRH_VAL_13333;
+    RTC.RFRL = RFRL_VAL_13333;
+#else
+    RTC.RCR5 = RCR5_VAL_RTCX3;
+    RTC.RFRH = RFRH_VAL_4000;
+    RTC.RFRL = RFRL_VAL_4000;
+#endif
+    // Dummy read
+    dummy_read = RTC.RCR2;
+    dummy_read = RTC.RCR2;
+
+    RTC.RCR2 = RCR2_VAL_START; // SRART = 1
+
+    // Dummy read
+    dummy_read = RTC.RCR2;
+    dummy_read = RTC.RCR2;
+
+    (void)dummy_read;
+
+}
+
+
+/*
+ * Release the RTC based on a time structure.
+ * @note This function does not stop the RTC from counting 
+ * [in]
+ * None.
+ * [out]
+ * None.
+ */
+void rtc_free(void)
+{
+}
+
+
+/*
+ * Check the RTC has been enabled.
+ * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled.
+ * [in]
+ * None.
+ * [out]
+ * 0:Disabled, 1:Enabled.
+ */
+int rtc_isenabled(void)
+{
+    int ret_val = 0;
+
+    if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ?
+        ret_val = 1;
+    }
+
+    return ret_val;
+}
+
+
+/*
+ * RTC read function.
+ * [in]
+ * None.
+ * [out]
+ * UNIX timestamp value.
+ */
+time_t rtc_read(void)
+{
+
+    struct tm timeinfo;
+    int    err = 0;
+    uint8_t tmp_regdata;
+    time_t t;
+
+    if (rtc_isenabled() != 0) {
+        RTC.RCR1 &= ~0x10u; // CIE = 0
+        do {
+            // before reading process
+            tmp_regdata  = RTC.RCR1;
+            tmp_regdata &= ~0x80u; // CF = 0
+            tmp_regdata |= 0x01u;  // AF = 1
+            RTC.RCR1 = tmp_regdata;
+
+            // Read RTC register
+            err  = rtc_dec8_to_hex(RTC.RSECCNT , 0    , &timeinfo.tm_sec);
+            err += rtc_dec8_to_hex(RTC.RMINCNT , 0    , &timeinfo.tm_min);
+            err += rtc_dec8_to_hex(RTC.RHRCNT  , 0    , &timeinfo.tm_hour);
+            err += rtc_dec8_to_hex(RTC.RDAYCNT , 0    , &timeinfo.tm_mday);
+            err += rtc_dec8_to_hex(RTC.RMONCNT , 1    , &timeinfo.tm_mon);
+            err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year);
+        } while ((RTC.RCR1 & 0x80u) != 0);
+    } else {
+        err = 1;
+    }
+
+    if (err == 0) {
+        // Convert to timestamp
+        if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
+            return TIME_ERROR_VAL;
+        }
+    } else {
+        // Error
+        t = TIME_ERROR_VAL;
+    }
+
+    return t;
+}
+
+/*
+ * Dec(8bit) to Hex function for RTC.
+ * [in]
+ * dec_val:Decimal value (from 0x00 to 0x99).
+ * offset:Subtract offset from dec_val.
+ * hex_val:Pointer of output hexadecimal value.
+ * [out]
+ * 0:Success
+ * 1:Error
+ */
+static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val)
+{
+    int err = 0;
+    uint8_t ret_val;
+
+    if (hex_val != NULL) {
+        if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
+            ((dec_val & MASK_00_03_POS) >=  0x0A)) {
+            err = 1;
+        } else {
+            ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 +
+                       (dec_val & MASK_00_03_POS);
+            if (ret_val < offset) {
+                err = 1;
+            } else {
+                *hex_val = ret_val - offset;
+            }
+        }
+    } else {
+        err = 1;
+    }
+
+    return err;
+}
+
+/*
+ * Dec(16bit) to Hex function for RTC
+ * [in]
+ * dec_val:Decimal value (from 0x0000 to 0x9999).
+ * offset:Subtract offset from dec_val.
+ * hex_val:Pointer of output hexadecimal value.
+ * [out]
+ * 0:Success
+ * 1:Error
+ */
+static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val)
+{
+    int err = 0;
+    uint16_t ret_val;
+
+    if (hex_val != NULL) {
+        if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) ||
+            ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) ||
+            ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
+            ((dec_val & MASK_00_03_POS) >=  0x0A)) {
+            err = 1;
+            *hex_val = 0;
+        } else {
+            ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 +
+                      (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 +
+                      (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 +
+                        (dec_val & MASK_00_03_POS);
+            if (ret_val < offset) {
+                err = 1;
+            } else {
+                *hex_val = ret_val - offset;
+            }
+        }
+    } else {
+        err = 1;
+    }
+    return err;
+}
+
+/*
+ * RTC write function
+ * [in]
+ * t:UNIX timestamp value
+ * [out]
+ * None.
+ */
+void rtc_write(time_t t)
+{
+
+    struct tm timeinfo;
+    if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
+        return;
+    }
+
+    volatile uint16_t dummy_read;
+
+    if (rtc_isenabled() != 0) {
+        RTC.RCR2    = RCR2_VAL_ALLSTOP;
+        dummy_read  = (uint16_t)RTC.RCR2;
+        dummy_read  = (uint16_t)RTC.RCR2;
+        RTC.RCR2    = RCR2_VAL_RESET; // RESET = 1
+        dummy_read  = (uint16_t)RTC.RCR2;
+        dummy_read  = (uint16_t)RTC.RCR2;
+
+        RTC.RSECCNT = rtc_hex8_to_dec(timeinfo.tm_sec);
+        RTC.RMINCNT = rtc_hex8_to_dec(timeinfo.tm_min);
+        RTC.RHRCNT  = rtc_hex8_to_dec(timeinfo.tm_hour);
+        RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo.tm_mday);
+        RTC.RMONCNT = rtc_hex8_to_dec(timeinfo.tm_mon + 1);
+        RTC.RYRCNT  = rtc_hex16_to_dec(timeinfo.tm_year + 1900);
+        dummy_read  = (uint16_t)RTC.RYRCNT;
+        dummy_read  = (uint16_t)RTC.RYRCNT;
+
+        RTC.RCR2    = RCR2_VAL_START; // START = 1
+
+        dummy_read  = (uint16_t)RTC.RCR2;
+        dummy_read  = (uint16_t)RTC.RCR2;
+        (void)dummy_read;
+    }
+}
+
+/*
+ * HEX to Dec(8bit) function for RTC.
+ * [in]
+ * hex_val:Hexadecimal value.
+ * [out]
+ * decimal value:From 0x00 to 0x99.
+ */
+static uint8_t rtc_hex8_to_dec(uint8_t hex_val)
+{
+    uint32_t calc_data;
+
+    calc_data  = hex_val / 10 * 0x10;
+    calc_data += hex_val % 10;
+
+    if (calc_data > 0x99) {
+        calc_data = 0;
+    }
+
+    return (uint8_t)calc_data;
+}
+
+/*
+ * HEX to Dec(16bit) function for RTC.
+ * [in]
+ * hex_val:Hexadecimal value.
+ * [out]
+ * decimal value:From 0x0000 to 0x9999.
+ */
+static uint16_t rtc_hex16_to_dec(uint16_t hex_val)
+{
+    uint32_t calc_data;
+    calc_data  =   hex_val / 1000       * 0x1000;
+    calc_data += ((hex_val / 100) % 10) * 0x100;
+    calc_data += ((hex_val / 10)  % 10) * 0x10;
+    calc_data +=   hex_val        % 10;
+
+    if (calc_data > 0x9999) {
+        calc_data = 0;
+    }
+    return (uint16_t)calc_data;
+
+}
+
+#endif /* DEVICE_RTC */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/serial_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/serial_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/serial_api.c	(revision 374)
@@ -0,0 +1,773 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include "mbed_assert.h"
+#include <math.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "PeripheralPins.h"
+#include "gpio_api.h"
+#include "RZ_A1_Init.h"
+
+#include "iodefine.h"
+#include "mbed_drv_cfg.h"
+#include "mbed_critical.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#if defined(TARGET_RZA1H)
+#define UART_NUM    8
+#else
+#define UART_NUM    5
+#endif
+#define IRQ_NUM     4
+
+static void uart0_tx_irq(void);
+static void uart0_rx_irq(void);
+static void uart0_er_irq(void);
+static void uart1_tx_irq(void);
+static void uart1_rx_irq(void);
+static void uart1_er_irq(void);
+static void uart2_tx_irq(void);
+static void uart2_rx_irq(void);
+static void uart2_er_irq(void);
+static void uart3_tx_irq(void);
+static void uart3_rx_irq(void);
+static void uart3_er_irq(void);
+static void uart4_tx_irq(void);
+static void uart4_rx_irq(void);
+static void uart4_er_irq(void);
+#if defined(TARGET_RZA1H)
+static void uart5_tx_irq(void);
+static void uart5_rx_irq(void);
+static void uart5_er_irq(void);
+static void uart6_tx_irq(void);
+static void uart6_rx_irq(void);
+static void uart6_er_irq(void);
+static void uart7_tx_irq(void);
+static void uart7_rx_irq(void);
+static void uart7_er_irq(void);
+#endif
+
+static void serial_put_done(serial_t *obj);
+static uint8_t serial_available_buffer(serial_t *obj);
+static void serial_irq_err_set(serial_t *obj, uint32_t enable);
+
+static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
+//static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+struct serial_global_data_s {
+    /*add*/uart_irq_handler irq_handler;
+    uint32_t serial_irq_id;
+    gpio_t sw_rts, sw_cts;
+    serial_t *tranferring_obj, *receiving_obj;
+    uint32_t async_tx_callback, async_rx_callback;
+    int event, wanted_rx_events;
+};
+
+static struct serial_global_data_s uart_data[UART_NUM];
+
+static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
+    {SCIFRXI0_IRQn, SCIFTXI0_IRQn, SCIFBRI0_IRQn, SCIFERI0_IRQn},
+    {SCIFRXI1_IRQn, SCIFTXI1_IRQn, SCIFBRI1_IRQn, SCIFERI1_IRQn},
+    {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn},
+    {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn},
+    {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn},
+#if defined(TARGET_RZA1H)
+    {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn},
+    {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn},
+    {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn},
+#endif
+};
+
+static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
+    {uart0_rx_irq, uart0_tx_irq, uart0_er_irq, uart0_er_irq},
+    {uart1_rx_irq, uart1_tx_irq, uart1_er_irq, uart1_er_irq},
+    {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq},
+    {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq},
+    {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq},
+#if defined(TARGET_RZA1H)
+    {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq},
+    {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq},
+    {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq},
+#endif
+};
+
+static __IO uint16_t *SCSCR_MATCH[] = {
+    &SCSCR_0,
+    &SCSCR_1,
+    &SCSCR_2,
+    &SCSCR_3,
+    &SCSCR_4,
+#if defined(TARGET_RZA1H)
+    &SCSCR_5,
+    &SCSCR_6,
+    &SCSCR_7,
+#endif
+};
+
+static __IO uint16_t *SCFSR_MATCH[] = {
+    &SCFSR_0,
+    &SCFSR_1,
+    &SCFSR_2,
+    &SCFSR_3,
+    &SCFSR_4,
+#if defined(TARGET_RZA1H)
+    &SCFSR_5,
+    &SCFSR_6,
+    &SCFSR_7,
+#endif
+};
+
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    volatile uint8_t dummy ;
+    int is_stdio_uart = 0;
+    // determine the UART to use
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+    uint32_t uart = pinmap_merge(uart_tx, uart_rx);
+
+    MBED_ASSERT((int)uart != NC);
+
+    obj->serial.uart = (struct st_scif *)SCIF[uart];
+    // enable power
+    CPG.STBCR4 &= ~(1 << (7 - uart));
+    dummy = CPG.STBCR4;
+
+    /* ==== SCIF initial setting ==== */
+    /* ---- Serial control register (SCSCR) setting ---- */
+    /* B'00 : Internal CLK */
+    obj->serial.uart->SCSCR = 0x0000u;          /* SCIF transmitting and receiving operations stop */
+
+    /* ---- FIFO control register (SCFCR) setting ---- */
+    /* Transmit FIFO reset & Receive FIFO data register reset */
+    obj->serial.uart->SCFCR = 0x0006u;
+
+    /* ---- Serial status register (SCFSR) setting ---- */
+    dummy = obj->serial.uart->SCFSR;
+    obj->serial.uart->SCFSR = (dummy & 0xFF6Cu);         /* ER,BRK,DR bit clear */
+
+    /* ---- Line status register (SCLSR) setting ---- */
+    /* ORER bit clear */
+    obj->serial.uart->SCLSR = 0;
+
+    /* ---- Serial extension mode register (SCEMR) setting ----
+    b7 BGDM - Baud rate generator double-speed mode  : Normal mode
+    b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
+    obj->serial.uart->SCEMR = 0x0000u;
+
+    /* ---- Bit rate register (SCBRR) setting ---- */
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+
+    /* ---- FIFO control register (SCFCR) setting ---- */
+    obj->serial.uart->SCFCR = 0x0030u;
+
+    /* ---- Serial port register (SCSPTR) setting ----
+    b1 SPB2IO - Serial port break output : disabled
+    b0 SPB2DT - Serial port break data   : High-level */
+    obj->serial.uart->SCSPTR = 0x0003u;    // SPB2IO = 1, SPB2DT = 1
+
+    /* ---- Line status register (SCLSR) setting ----
+    b0 ORER - Overrun error detect : clear */
+
+    if (obj->serial.uart->SCLSR & 0x0001) {
+        obj->serial.uart->SCLSR = 0u;      // ORER clear
+    }
+
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    obj->serial.index = uart;
+
+    uart_data[obj->serial.index].sw_rts.pin = NC;
+    uart_data[obj->serial.index].sw_cts.pin = NC;
+
+    /* ---- Serial control register (SCSCR) setting ---- */
+    /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
+    obj->serial.uart->SCSCR = 0x0070;
+
+    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    uart_data[obj->serial.index].serial_irq_id = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    uint32_t pclk_base;
+    uint32_t bgdm = 1;
+    uint32_t cks = 0;
+    uint32_t DL;
+
+    if (RZ_A1_IsClockMode0() == false) {
+        pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
+    } else {
+        pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
+    }
+
+    if (baudrate > (int)(pclk_base / 0x800)) {
+        obj->serial.uart->SCSMR &= ~0x0003;
+        obj->serial.uart->SCEMR = 0x0081;  // BGDM = 1, ABCS = 1
+        DL = (pclk_base + (4 * baudrate)) / (8 * baudrate);  // Rounding
+        if (DL > 0) {
+            DL--;
+        }
+        obj->serial.uart->SCBRR = (uint8_t)DL;
+    } else if (baudrate < (int)(pclk_base / 0x80000)) {
+        obj->serial.uart->SCSMR |= 0x0003;
+        obj->serial.uart->SCEMR = 0x0000;
+        obj->serial.uart->SCBRR = 0xFFu;
+    } else {
+        DL = (pclk_base + (8 * baudrate)) / (16 * baudrate);  // Rounding
+        while (DL > 256) {
+            DL >>= 1;
+            if (bgdm == 1) {
+                bgdm = 0;
+            } else {
+                bgdm = 1;
+                cks++;
+            }
+        }
+        obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0003) | (uint8_t)cks;
+        obj->serial.uart->SCEMR = (uint8_t)(bgdm << 7);
+        obj->serial.uart->SCBRR = (uint8_t)(DL - 1);
+    }
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    int parity_enable;
+    int parity_select;
+
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
+    MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
+                (parity == ParityForced1) || (parity == ParityForced0));
+
+    stop_bits = (stop_bits == 1)? 0:
+                (stop_bits == 2)? 1:
+                0; // must not to be
+
+    data_bits = (data_bits == 8)? 0:
+                (data_bits == 7)? 1:
+                0; // must not to be
+
+    switch (parity) {
+    case ParityNone:
+        parity_enable = 0;
+        parity_select = 0;
+        break;
+    case ParityOdd:
+        parity_enable = 1;
+        parity_select = 1;
+        break;
+    case ParityEven:
+        parity_enable = 1;
+        parity_select = 0;
+        break;
+    case ParityForced1:
+    case ParityForced0:
+    default:
+        parity_enable = 0;
+        parity_select = 0;
+        break;
+    }
+
+    obj->serial.uart->SCSMR = data_bits   << 6
+                       | parity_enable    << 5
+                       | parity_select    << 4
+                       | stop_bits        << 3;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
+    __IO uint16_t *dmy_rd_scscr;
+    __IO uint16_t *dmy_rd_scfsr;
+    serial_t *obj;
+    int i;
+    
+    dmy_rd_scscr = SCSCR_MATCH[index];
+    *dmy_rd_scscr &= 0x007B;                    // Clear TIE and Write to bit15~8,2 is always 0
+    dmy_rd_scfsr = SCFSR_MATCH[index];
+    *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020);  // Set TEND
+    
+    obj = uart_data[index].tranferring_obj;
+    if (obj) {
+        i = obj->tx_buff.length - obj->tx_buff.pos;
+        if (0 < i) {
+            if (serial_available_buffer(obj) < i) {
+                i = serial_available_buffer(obj);
+            }
+            do {
+                uint8_t c = *(uint8_t *)obj->tx_buff.buffer;
+                obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
+                ++obj->tx_buff.pos;
+                obj->serial.uart->SCFTDR = c;
+            } while (--i);
+            serial_put_done(obj);
+        } else {
+            uart_data[index].tranferring_obj = NULL;
+            uart_data[index].event = SERIAL_EVENT_TX_COMPLETE;
+            ((void (*)())uart_data[index].async_tx_callback)();
+        }
+    }
+    
+    if (uart_data[index].irq_handler != NULL)
+        uart_data[index].irq_handler(uart_data[index].serial_irq_id, TxIrq);
+}
+
+static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
+    __IO uint16_t *dmy_rd_scscr;
+    __IO uint16_t *dmy_rd_scfsr;
+    serial_t *obj;
+    int c;
+    
+    dmy_rd_scscr = SCSCR_MATCH[index];
+    *dmy_rd_scscr &= 0x00B3;                    // Clear RIE,REIE and Write to bit15~8,2 is always 0
+    dmy_rd_scfsr = SCFSR_MATCH[index];
+    *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003);  // Clear RDF,DR
+    
+    obj = uart_data[index].receiving_obj;
+    if (obj) {
+        if (obj->serial.uart->SCLSR & 1) {
+            if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+                serial_rx_abort_asynch(obj);
+                uart_data[index].event = SERIAL_EVENT_RX_OVERRUN_ERROR;
+                ((void (*)())uart_data[index].async_rx_callback)();
+            }
+            return;
+        }
+        c = serial_getc(obj);
+        if (c != -1) {
+            ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos] = c;
+            ++obj->rx_buff.pos;
+            if (c == obj->char_match && ! obj->char_found) {
+                obj->char_found = 1;
+                if (obj->rx_buff.pos == obj->rx_buff.length) {
+                    if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
+                        uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
+                    }
+                }
+                if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+                    uart_data[index].event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+                }
+                if (uart_data[index].event) {
+                    uart_data[index].receiving_obj = NULL;
+                    ((void (*)())uart_data[index].async_rx_callback)();
+                }
+            } else if (obj->rx_buff.pos == obj->rx_buff.length) {
+                uart_data[index].receiving_obj = NULL;
+                if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
+                    uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
+                    ((void (*)())uart_data[index].async_rx_callback)();
+                }
+            }
+        } else {
+            serial_rx_abort_asynch(obj);
+            if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
+                uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
+                if (obj->serial.uart->SCFSR & 1 << 2) {
+                    uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
+                } else if (obj->serial.uart->SCFSR & 1 << 3) {
+                    uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
+                }
+                ((void (*)())uart_data[index].async_rx_callback)();
+            }
+            return;
+        }
+    }
+    
+    if (uart_data[index].irq_handler != NULL)
+        uart_data[index].irq_handler(uart_data[index].serial_irq_id, RxIrq);
+}
+
+static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
+    serial_t *obj = uart_data[index].receiving_obj;
+    int err_read;
+    
+    if (obj) {
+        serial_irq_err_set(obj, 0);
+        if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
+            uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
+            if (obj->serial.uart->SCFSR & 1 << 2) {
+                uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
+            } else if (obj->serial.uart->SCFSR & 1 << 3) {
+                uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
+            }
+            ((void (*)())uart_data[index].async_rx_callback)();
+        }
+        serial_rx_abort_asynch(obj);
+        
+        core_util_critical_section_enter();
+        if (obj->serial.uart->SCFSR & 0x93) {
+            err_read = obj->serial.uart->SCFSR;
+            obj->serial.uart->SCFSR = (err_read & ~0x93);
+        }
+        if (obj->serial.uart->SCLSR & 1) {
+            obj->serial.uart->SCLSR = 0;
+        }
+        core_util_critical_section_exit();
+        }
+    }
+
+static void uart0_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI0_IRQn, 0);
+}
+static void uart0_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI0_IRQn, 0);
+}
+static void uart0_er_irq(void) {
+    uart_err_irq(SCIFERI0_IRQn, 0);
+}
+
+static void uart1_tx_irq(void) {
+    uart_tx_irq(SCIFTXI1_IRQn, 1);
+}
+static void uart1_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI1_IRQn, 1);
+}
+static void uart1_er_irq(void) {
+    uart_err_irq(SCIFERI1_IRQn, 1);
+}
+
+static void uart2_tx_irq(void) {
+    uart_tx_irq(SCIFTXI2_IRQn, 2);
+}
+static void uart2_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI2_IRQn, 2);
+}
+static void uart2_er_irq(void) {
+    uart_err_irq(SCIFERI2_IRQn, 2);
+}
+
+static void uart3_tx_irq(void) {
+    uart_tx_irq(SCIFTXI3_IRQn, 3);
+}
+static void uart3_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI3_IRQn, 3);
+}
+static void uart3_er_irq(void) {
+    uart_err_irq(SCIFERI3_IRQn, 3);
+}
+
+static void uart4_tx_irq(void) {
+    uart_tx_irq(SCIFTXI4_IRQn, 4);
+}
+static void uart4_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI4_IRQn, 4);
+}
+static void uart4_er_irq(void) {
+    uart_err_irq(SCIFERI4_IRQn, 4);
+}
+
+#if defined(TARGET_RZA1H)
+static void uart5_tx_irq(void) {
+    uart_tx_irq(SCIFTXI5_IRQn, 5);
+}
+static void uart5_rx_irq(void) {
+    uart_rx_irq(SCIFRXI5_IRQn, 5);
+}
+static void uart5_er_irq(void) {
+    uart_err_irq(SCIFERI5_IRQn, 5);
+}
+
+static void uart6_tx_irq(void) {
+    uart_tx_irq(SCIFTXI6_IRQn, 6);
+}
+static void uart6_rx_irq(void) {
+    uart_rx_irq(SCIFRXI6_IRQn, 6);
+}
+static void uart6_er_irq(void) {
+    uart_err_irq(SCIFERI6_IRQn, 6);
+}
+
+static void uart7_tx_irq(void) {
+    uart_tx_irq(SCIFTXI7_IRQn, 7);
+}
+static void uart7_rx_irq(void) {
+    uart_rx_irq(SCIFRXI7_IRQn, 7);
+}
+static void uart7_er_irq(void) {
+    uart_err_irq(SCIFERI7_IRQn, 7);
+}
+#endif
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    uart_data[obj->serial.index].irq_handler = handler;
+    uart_data[obj->serial.index].serial_irq_id = id;
+}
+
+static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable)
+{
+    if (enable) {
+        InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+        GIC_SetPriority(IRQn, 5);
+        GIC_EnableIRQ(IRQn);
+    } else {
+        GIC_DisableIRQ(IRQn);
+    }
+}
+
+static void serial_irq_err_set(serial_t *obj, uint32_t enable)
+{
+    serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);
+    serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type IRQn;
+    IRQHandler handler;
+
+    IRQn = irq_set_tbl[obj->serial.index][irq];
+    handler = hander_set_tbl[obj->serial.index][irq];
+
+    if ((obj->serial.index >= 0) && (obj->serial.index <= 7)) {
+        serial_irq_set_irq(IRQn, handler, enable);
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    uint16_t err_read;
+    int data;
+
+    core_util_critical_section_enter();
+    if (obj->serial.uart->SCFSR & 0x93) {
+        err_read = obj->serial.uart->SCFSR;
+        obj->serial.uart->SCFSR = (err_read & ~0x93);
+    }
+    obj->serial.uart->SCSCR |= 0x0040;     // Set RIE
+    core_util_critical_section_exit();
+
+    if (obj->serial.uart->SCLSR & 0x0001) {
+        obj->serial.uart->SCLSR = 0u;      // ORER clear
+    }
+
+    while (!serial_readable(obj));
+    data = obj->serial.uart->SCFRDR & 0xff;
+
+    core_util_critical_section_enter();
+    err_read = obj->serial.uart->SCFSR;
+    obj->serial.uart->SCFSR = (err_read & 0xfffD);     // Clear RDF
+    core_util_critical_section_exit();
+
+    if (err_read & 0x80) {
+        data = -1;  //err
+    }
+    return data;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    obj->serial.uart->SCFTDR = c;
+    serial_put_done(obj);
+}
+
+static void serial_put_done(serial_t *obj)
+{
+    volatile uint16_t dummy_read;
+    
+    core_util_critical_section_enter();
+    dummy_read = obj->serial.uart->SCFSR;
+    obj->serial.uart->SCFSR = (dummy_read & 0xff9f);  // Clear TEND/TDFE
+    obj->serial.uart->SCSCR |= 0x0080;     // Set TIE
+    core_util_critical_section_exit();
+    }
+
+int serial_readable(serial_t *obj) {
+    return ((obj->serial.uart->SCFSR & 0x02) != 0);  // RDF
+}
+
+int serial_writable(serial_t *obj) {
+    return ((obj->serial.uart->SCFSR & 0x20) != 0);  // TDFE
+}
+
+void serial_clear(serial_t *obj) {
+    core_util_critical_section_enter();
+
+    obj->serial.uart->SCFCR |=  0x0006u;       // TFRST = 1, RFRST = 1
+    obj->serial.uart->SCFCR &= ~0x0006u;       // TFRST = 0, RFRST = 0
+    obj->serial.uart->SCFSR &= ~0x0093u;       // ER, BRK, RDF, DR = 0
+
+    core_util_critical_section_exit();
+    }
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    core_util_critical_section_enter();
+    // TxD Output(L)
+    obj->serial.uart->SCSPTR &= ~0x0001u;  // SPB2DT = 0
+    obj->serial.uart->SCSCR &= ~0x0020u;   // TE = 0 (Output disable)
+    core_util_critical_section_exit();
+    }
+
+void serial_break_clear(serial_t *obj) {
+    core_util_critical_section_enter();
+    obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
+    obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1
+    core_util_critical_section_exit();
+    }
+
+#if DEVICE_SERIAL_FC
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
+    // determine the UART to use
+
+    if (type == FlowControlRTSCTS) {
+        core_util_critical_section_enter();
+        obj->serial.uart->SCFCR |= 0x0008u;   // CTS/RTS enable
+        core_util_critical_section_exit();
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+    } else {
+        core_util_critical_section_enter();
+        obj->serial.uart->SCFCR &= ~0x0008u; // CTS/RTS diable
+        core_util_critical_section_exit();
+    }
+}
+#endif
+
+static uint8_t serial_available_buffer(serial_t *obj)
+{
+    return 1;
+    /* Faster but unstable way */
+    /*
+     uint16_t ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
+     while (ret == 0) {
+     ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
+     }
+     MBED_ASSERT(0 < ret && ret <= 16);
+     return ret;
+     */
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+/******************************************************************************
+ * ASYNCHRONOUS HAL
+ ******************************************************************************/
+
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    int i;
+    buffer_t *buf = &obj->tx_buff;
+    struct serial_global_data_s *data = uart_data + obj->serial.index;
+    
+    if (tx_length == 0) {
+        return 0;
+    }
+    
+    buf->buffer = (void *)tx;
+    buf->length = tx_length * tx_width / 8;
+    buf->pos = 0;
+    buf->width = tx_width;
+    data->tranferring_obj = obj;
+    data->async_tx_callback = handler;
+    serial_irq_set(obj, TxIrq, 1);
+    
+    while (!serial_writable(obj));
+    i = buf->length;
+    if (serial_available_buffer(obj) < i) {
+        i = serial_available_buffer(obj);
+    }
+    do {
+        uint8_t c = *(uint8_t *)buf->buffer;
+        obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
+        ++buf->pos;
+        obj->serial.uart->SCFTDR = c;
+    } while (--i);
+    serial_put_done(obj);
+    
+    return buf->length;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+    buffer_t *buf = &obj->rx_buff;
+    struct serial_global_data_s *data = uart_data + obj->serial.index;
+    
+    if (rx_length == 0) {
+        return;
+    }
+    
+    buf->buffer = rx;
+    buf->length = rx_length * rx_width / 8;
+    buf->pos = 0;
+    buf->width = rx_width;
+    obj->char_match = char_match;
+    obj->char_found = 0;
+    data->receiving_obj = obj;
+    data->async_rx_callback = handler;
+    data->event = 0;
+    data->wanted_rx_events = event;
+    
+    serial_irq_set(obj, RxIrq, 1);
+    serial_irq_err_set(obj, 1);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+    return uart_data[obj->serial.index].tranferring_obj != NULL;
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+    return uart_data[obj->serial.index].receiving_obj != NULL;
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+    return uart_data[obj->serial.index].event;
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+    uart_data[obj->serial.index].tranferring_obj = NULL;
+    obj->serial.uart->SCFCR |= 1 << 2;
+    obj->serial.uart->SCFCR &= ~(1 << 2);
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+    uart_data[obj->serial.index].receiving_obj = NULL;
+    obj->serial.uart->SCFCR |= 1 << 1;
+    obj->serial.uart->SCFCR &= ~(1 << 1);
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/sleep.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/sleep.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/sleep.c	(revision 374)
@@ -0,0 +1,199 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "mbed_critical.h"
+#include "iodefine.h"
+#include "cpg_iobitmask.h"
+
+#if DEVICE_SLEEP
+static volatile uint8_t wk_CPGSTBCR3;
+static volatile uint8_t wk_CPGSTBCR4;
+static volatile uint8_t wk_CPGSTBCR5;
+static volatile uint8_t wk_CPGSTBCR6;
+static volatile uint8_t wk_CPGSTBCR7;
+static volatile uint8_t wk_CPGSTBCR8;
+static volatile uint8_t wk_CPGSTBCR9;
+static volatile uint8_t wk_CPGSTBCR10;
+static volatile uint8_t wk_CPGSTBCR11;
+static volatile uint8_t wk_CPGSTBCR12;
+#if defined(TARGET_RZA1H)  || defined(TARGET_VK_RZ_A1H)
+static volatile uint8_t wk_CPGSTBCR13;
+#endif
+static volatile uint8_t wk_CPGSTBREQ1;
+static volatile uint8_t wk_CPGSTBREQ2;
+
+typedef struct {
+    volatile uint8_t * p_wk_stbcr;
+    volatile uint8_t * p_stbcr;
+    volatile uint8_t * p_stbreq;
+    volatile uint8_t * p_stback;
+    uint8_t mstp;
+    uint8_t stbrq;
+} module_stanby_t;
+
+static const module_stanby_t module_stanby[] = {
+    {&wk_CPGSTBCR6,  &CPGSTBCR6,  &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_MSTP61,   CPG_STBREQ1_STBRQ13}, /* JCU */
+    {&wk_CPGSTBCR6,  &CPGSTBCR6,  &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR6_MSTP66,   CPG_STBREQ1_STBRQ10}, /* CEU */
+    {&wk_CPGSTBCR6,  &CPGSTBCR8,  &CPGSTBREQ1, &CPGSTBACK1, CPG_STBCR8_MSTP82,   CPG_STBREQ1_STBRQ12}, /* EthernetAVB */
+    {&wk_CPGSTBCR7,  &CPGSTBCR7,  &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR7_MSTP74,   CPG_STBREQ2_STBRQ26}, /* Ethernet */
+    {&wk_CPGSTBCR8,  &CPGSTBCR8,  &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP83,   CPG_STBREQ2_STBRQ27}, /* MediaLB */
+    {&wk_CPGSTBCR9,  &CPGSTBCR9,  &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_MSTP91,   CPG_STBREQ2_STBRQ25}, /* VDC5_0 */
+#if defined(TARGET_RZA1H)  || defined(TARGET_VK_RZ_A1H)
+    {&wk_CPGSTBCR8,  &CPGSTBCR8,  &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP85,   CPG_STBREQ2_STBRQ21}, /* IMR-LSD */
+    {&wk_CPGSTBCR8,  &CPGSTBCR8,  &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP86,   CPG_STBREQ2_STBRQ22}, /* IMR-LS2_1 */
+    {&wk_CPGSTBCR8,  &CPGSTBCR8,  &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_MSTP87,   CPG_STBREQ2_STBRQ23}, /* IMR-LS2_0 */
+    {&wk_CPGSTBCR9,  &CPGSTBCR9,  &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_MSTP90,   CPG_STBREQ2_STBRQ24}, /* VDC5_1 */
+    {&wk_CPGSTBCR10, &CPGSTBCR10, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR10_MSTP100, CPG_STBREQ2_STBRQ20}, /* OpenVG */
+#endif
+    {0, 0, 0, 0, 0}  /* None */
+};
+
+static void module_standby_in(void) {
+    volatile uint32_t cnt;
+    volatile uint8_t dummy_8;
+    const module_stanby_t * p_module = &module_stanby[0];
+
+    while (p_module->p_wk_stbcr != 0) {
+        if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
+            *p_module->p_stbreq |= p_module->stbrq;
+            dummy_8             = *p_module->p_stbreq;
+            for (cnt = 0; cnt < 1000; cnt++) {      // wait time
+                if ((*p_module->p_stback & p_module->stbrq) != 0) {
+                    break;
+                }
+            }
+            *p_module->p_stbcr |= p_module->mstp;
+            dummy_8            = *p_module->p_stbcr;
+        }
+        p_module++;
+    }
+    (void)dummy_8;
+}
+
+static void module_standby_out(void) {
+    volatile uint32_t cnt;
+    volatile uint8_t dummy_8;
+    const module_stanby_t * p_module = &module_stanby[0];
+
+    while (p_module->p_wk_stbcr != 0) {
+        if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) {
+            *p_module->p_stbreq &= ~(p_module->stbrq);
+            dummy_8             = *p_module->p_stbreq;
+            for (cnt = 0; cnt < 1000; cnt++) {
+                if ((*p_module->p_stback & p_module->stbrq) == 0) {
+                    break;
+                }
+            }
+        }
+        p_module++;
+    }
+    (void)dummy_8;
+}
+
+void hal_sleep(void) {
+    // Transition to Sleep Mode
+    __WFI();
+}
+
+void hal_deepsleep(void) {
+    volatile uint8_t dummy_8;
+
+    core_util_critical_section_enter();
+    /* For powerdown the peripheral module, save current standby control register values(just in case) */
+    wk_CPGSTBCR3  = CPGSTBCR3;
+    wk_CPGSTBCR4  = CPGSTBCR4;
+    wk_CPGSTBCR5  = CPGSTBCR5;
+    wk_CPGSTBCR6  = CPGSTBCR6;
+    wk_CPGSTBCR7  = CPGSTBCR7;
+    wk_CPGSTBCR8  = CPGSTBCR8;
+    wk_CPGSTBCR9  = CPGSTBCR9;
+    wk_CPGSTBCR10 = CPGSTBCR10;
+    wk_CPGSTBCR11 = CPGSTBCR11;
+    wk_CPGSTBCR12 = CPGSTBCR12;
+#if defined(TARGET_RZA1H)  || defined(TARGET_VK_RZ_A1H)
+    wk_CPGSTBCR13 = CPGSTBCR13;
+#endif
+
+    /* MTU2 (for low power ticker) */
+    CPGSTBCR3  |= ~(CPG_STBCR3_MSTP33);
+    dummy_8    = CPGSTBCR3;
+    CPGSTBCR4  = 0xFF;
+    dummy_8    = CPGSTBCR4;
+    CPGSTBCR5  = 0xFF;
+    dummy_8    = CPGSTBCR5;
+    /* Realtime Clock, JCU, CEU */
+    CPGSTBCR6  |= ~(CPG_STBCR6_MSTP60 | CPG_STBCR6_MSTP61 | CPG_STBCR6_MSTP66);
+    dummy_8    = CPGSTBCR6;
+    /* Video Decoder0, Video Decoder1, Ethernet */
+    CPGSTBCR7  |= ~(CPG_STBCR7_MSTP77 | CPG_STBCR7_MSTP76 | CPG_STBCR7_MSTP74);
+    dummy_8    = CPGSTBCR7;
+    /* EthernetAVB, MediaLB, IMR-LSD, IMR-LS2_1, IMR-LS2_0 */
+    CPGSTBCR8  |= ~(CPG_STBCR8_MSTP82 | CPG_STBCR8_MSTP83 | CPG_STBCR8_MSTP85 | CPG_STBCR8_MSTP86 | CPG_STBCR8_MSTP87);
+    dummy_8    = CPGSTBCR8;
+    /* VDC5_1, SPI Multi I/O Bus Controller0 */
+    CPGSTBCR9  |= ~(CPG_STBCR9_MSTP90 | CPG_STBCR9_MSTP93);
+    dummy_8    = CPGSTBCR9;
+    /* OpenVG */
+    CPGSTBCR10 |= ~(CPG_STBCR10_MSTP100);
+    dummy_8    = CPGSTBCR10;
+    CPGSTBCR11 = 0xFF;
+    dummy_8    = CPGSTBCR11;
+    CPGSTBCR12 = 0xFF;
+    dummy_8    = CPGSTBCR12;
+#if defined(TARGET_RZA1H)  || defined(TARGET_VK_RZ_A1H)
+    CPGSTBCR13 = 0xFF;
+    dummy_8    = CPGSTBCR13;
+#endif
+
+    module_standby_in();
+
+    // Transition to Sleep Mode
+    __WFI();
+
+    /* Revert standby control register values */
+    CPGSTBCR3  = wk_CPGSTBCR3;
+    dummy_8    = CPGSTBCR3;
+    CPGSTBCR4  = wk_CPGSTBCR4;
+    dummy_8    = CPGSTBCR4;
+    CPGSTBCR5  = wk_CPGSTBCR5;
+    dummy_8    = CPGSTBCR5;
+    CPGSTBCR6  = wk_CPGSTBCR6;
+    dummy_8    = CPGSTBCR6;
+    CPGSTBCR7  = wk_CPGSTBCR7;
+    dummy_8    = CPGSTBCR7;
+    CPGSTBCR8  = wk_CPGSTBCR8;
+    dummy_8    = CPGSTBCR8;
+    CPGSTBCR9  = wk_CPGSTBCR9;
+    dummy_8    = CPGSTBCR9;
+    CPGSTBCR10 = wk_CPGSTBCR10;
+    dummy_8    = CPGSTBCR10;
+    CPGSTBCR11 = wk_CPGSTBCR11;
+    dummy_8    = CPGSTBCR11;
+    CPGSTBCR12 = wk_CPGSTBCR12;
+    dummy_8    = CPGSTBCR12;
+#if defined(TARGET_RZA1H)  || defined(TARGET_VK_RZ_A1H)
+    CPGSTBCR13 = wk_CPGSTBCR13;
+    dummy_8    = CPGSTBCR13;
+#endif
+
+    module_standby_out();
+    core_util_critical_section_exit();
+
+    (void)dummy_8;
+}
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/spi_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/spi_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/spi_api.c	(revision 374)
@@ -0,0 +1,536 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "PeripheralPins.h"
+#include "mbed_error.h"
+#include "RZ_A1_Init.h"
+#include "mbed_drv_cfg.h"
+
+static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
+
+static inline void spi_disable(spi_t *obj);
+static inline void spi_enable(spi_t *obj);
+static inline int spi_readable(spi_t *obj);
+static inline void spi_write(spi_t *obj, int value);
+static inline int spi_read(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    volatile uint8_t dummy;
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+    uint32_t spi      = pinmap_merge(spi_data, spi_cntl);
+    
+    MBED_ASSERT((int)spi != NC);
+    
+    obj->spi.spi = (struct st_rspi *)RSPI[spi];
+    obj->spi.index = spi;
+    
+    // enable power and clocking
+    CPGSTBCR10 &= ~(0x80 >> spi);
+    dummy = CPGSTBCR10;
+    (void)dummy;
+    
+    obj->spi.spi->SPCR   = 0x00;  // CTRL to 0
+    obj->spi.spi->SPSCR  = 0x00;  // no sequential operation
+    obj->spi.spi->SSLP   = 0x00;  // SSL 'L' active
+    obj->spi.spi->SPDCR  = 0x20;  // byte access
+    obj->spi.spi->SPCKD  = 0x00;  // SSL -> enable CLK delay : 1RSPCK
+    obj->spi.spi->SSLND  = 0x00;  // CLK end -> SSL neg delay : 1RSPCK
+    obj->spi.spi->SPND   = 0x00;  // delay between CMD : 1RSPCK + 2P1CLK
+    obj->spi.spi->SPPCR  = 0x20;  // MOSI Idle fixed value equals 0
+    obj->spi.spi->SPBFCR = 0xf0;  // and set trigger count: read 1, write 1
+    obj->spi.spi->SPBFCR = 0x30;  // and reset buffer
+    
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if ((int)ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    int      DSS;      // DSS (data select size)
+    int      polarity  = (mode & 0x2) ? 1 : 0;
+    int      phase     = (mode & 0x1) ? 1 : 0;
+    uint16_t tmp       = 0;
+    uint16_t mask      = 0xf03;
+    uint16_t wk_spcmd0;
+    uint8_t  splw;
+    
+    switch (mode) {
+        case 0:
+        case 1:
+        case 2:
+        case 3:
+            // Do Nothing
+            break;
+        default:
+            error("SPI format error");
+            return;
+    }
+    
+    switch (bits) {
+        case 8:
+            DSS  = 0x7;
+            splw = 0x20;
+            break;
+        case 16:
+            DSS  = 0xf;
+            splw = 0x40;
+            break;
+        case 32:
+            DSS  = 0x2;
+            splw = 0x60;
+            break;
+        default:
+            error("SPI module don't support other than 8/16/32bits");
+            return;
+    }
+    tmp |= phase;
+    tmp |= (polarity << 1);
+    tmp |= (DSS << 8);
+    obj->spi.bits = bits;
+    
+    spi_disable(obj);
+    wk_spcmd0 = obj->spi.spi->SPCMD0;
+    wk_spcmd0 &= ~mask;
+    wk_spcmd0 |= (mask & tmp);
+    obj->spi.spi->SPCMD0 = wk_spcmd0;
+    obj->spi.spi->SPDCR   = splw;
+    if (slave) {
+        obj->spi.spi->SPCR &=~(1 << 3);  // MSTR to 0
+    } else {
+        obj->spi.spi->SPCR |= (1 << 3);  // MSTR to 1
+    }
+    spi_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    uint32_t  pclk_base;
+    uint32_t  div;
+    uint32_t  brdv = 0;
+    uint32_t  hz_max;
+    uint32_t  hz_min;
+    uint16_t  mask = 0x000c;
+    uint16_t  wk_spcmd0;
+    
+    /* set PCLK */
+    if (RZ_A1_IsClockMode0() == false) {
+        pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
+    } else {
+        pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
+    }
+    
+    hz_min = pclk_base / 2 / 256 / 8;
+    hz_max = pclk_base / 2;
+    if (((uint32_t)hz < hz_min) || ((uint32_t)hz > hz_max)) {
+        error("Couldn't setup requested SPI frequency");
+        return;
+    }
+    
+    div = (pclk_base / hz / 2);
+    while (div > 256) {
+        div >>= 1;
+        brdv++;
+    }
+    div  -= 1;
+    brdv  = (brdv << 2);
+    
+    spi_disable(obj);
+    obj->spi.spi->SPBR = div;
+    wk_spcmd0 = obj->spi.spi->SPCMD0;
+    wk_spcmd0 &= ~mask;
+    wk_spcmd0 |= (mask & brdv);
+    obj->spi.spi->SPCMD0 = wk_spcmd0;
+    spi_enable(obj);
+}
+
+static inline void spi_disable(spi_t *obj) {
+    obj->spi.spi->SPCR &= ~(1 << 6);       // SPE to 0
+}
+
+static inline void spi_enable(spi_t *obj) {
+    obj->spi.spi->SPCR |=  (1 << 6);       // SPE to 1
+}
+
+static inline int spi_readable(spi_t *obj) {
+    return obj->spi.spi->SPSR & (1 << 7);  // SPRF
+}
+
+static inline int spi_tend(spi_t *obj) {
+    return obj->spi.spi->SPSR & (1 << 6);  // TEND
+}
+
+static inline void spi_write(spi_t *obj, int value) {
+    if (obj->spi.bits == 8) {
+        obj->spi.spi->SPDR.UINT8[0]  = (uint8_t)value;
+    } else if (obj->spi.bits == 16) {
+        obj->spi.spi->SPDR.UINT16[0] = (uint16_t)value;
+    } else {
+        obj->spi.spi->SPDR.UINT32    = (uint32_t)value;
+    }
+}
+
+static inline int spi_read(spi_t *obj) {
+    int read_data;
+    
+    if (obj->spi.bits == 8) {
+        read_data = obj->spi.spi->SPDR.UINT8[0];
+    } else if (obj->spi.bits == 16) {
+        read_data = obj->spi.spi->SPDR.UINT16[0];
+    } else {
+        read_data = obj->spi.spi->SPDR.UINT32;
+    }
+    
+    return read_data;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    spi_write(obj, value);
+    while(!spi_tend(obj));
+    return spi_read(obj);
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
+    int total = (tx_length > rx_length) ? tx_length : rx_length;
+
+    for (int i = 0; i < total; i++) {
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+        char in = spi_master_write(obj, out);
+        if (i < rx_length) {
+            rx_buffer[i] = in;
+        }
+    }
+
+    return total;
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+    return spi_read(obj);
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    spi_write(obj, value);
+}
+
+int spi_busy(spi_t *obj) {
+    return 0;
+}
+
+#if DEVICE_SPI_ASYNCH
+
+#define SPI_NUM         5
+#define IRQ_NUM         2
+
+static void spi_irqs_set(spi_t *obj, uint32_t enable);
+static void spi_async_write(spi_t *obj);
+static void spi_async_read(spi_t *obj);
+
+static void spi0_rx_irq(void);
+static void spi0_er_irq(void);
+static void spi1_rx_irq(void);
+static void spi1_er_irq(void);
+static void spi2_rx_irq(void);
+static void spi2_er_irq(void);
+static void spi3_rx_irq(void);
+static void spi3_er_irq(void);
+static void spi4_rx_irq(void);
+static void spi4_er_irq(void);
+
+static const IRQn_Type irq_set_tbl[SPI_NUM][IRQ_NUM] = {
+    {RSPISPRI0_IRQn, RSPISPEI0_IRQn},
+    {RSPISPRI1_IRQn, RSPISPEI1_IRQn},
+    {RSPISPRI2_IRQn, RSPISPEI2_IRQn},
+    {RSPISPRI3_IRQn, RSPISPEI3_IRQn},
+    {RSPISPRI4_IRQn, RSPISPEI4_IRQn},
+};
+
+static const IRQHandler hander_set_tbl[SPI_NUM][IRQ_NUM] = {
+    {spi0_rx_irq, spi0_er_irq},
+    {spi1_rx_irq, spi1_er_irq},
+    {spi2_rx_irq, spi2_er_irq},
+    {spi3_rx_irq, spi3_er_irq},
+    {spi4_rx_irq, spi4_er_irq},
+};
+
+struct spi_global_data_s {
+    spi_t *async_obj;
+    uint32_t async_callback, event, wanted_events;
+};
+
+static struct spi_global_data_s spi_data[SPI_NUM];
+
+static void spi_rx_irq(IRQn_Type irq_num, uint32_t index)
+{
+    spi_t *obj = spi_data[index].async_obj;
+    if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+        spi_async_read(obj);
+    } else {
+        if (obj->rx_buff.buffer && obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+            spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+            if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
+                spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
+            }
+            spi_irqs_set(obj, 0);
+            spi_data[obj->spi.index].async_obj = NULL;
+            ((void (*)())spi_data[obj->spi.index].async_callback)();
+            return;
+        }
+        spi_read(obj);
+    }
+    if (obj->tx_buff.buffer) {
+        if (obj->tx_buff.pos == obj->tx_buff.length) {
+            spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+            if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
+                spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
+            }
+            spi_irqs_set(obj, 0);
+            spi_data[obj->spi.index].async_obj = NULL;
+            ((void (*)())spi_data[obj->spi.index].async_callback)();
+        } else {
+            spi_async_write(obj);
+        }
+    } else {
+        if (obj->rx_buff.pos == obj->rx_buff.length) {
+            spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+            if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
+                spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
+            }
+            spi_irqs_set(obj, 0);
+            spi_data[obj->spi.index].async_obj = NULL;
+            ((void (*)())spi_data[obj->spi.index].async_callback)();
+        } else {
+            spi_async_write(obj);
+        }
+    }
+}
+
+static void spi_err_irq(IRQn_Type irq_num, uint32_t index)
+{
+    spi_t *obj = spi_data[index].async_obj;
+    spi_abort_asynch(obj);
+    spi_data[index].event = SPI_EVENT_ERROR;
+    if (spi_data[index].wanted_events & SPI_EVENT_ERROR) {
+        ((void (*)())spi_data[index].async_callback)();
+    }
+}
+
+static void spi0_rx_irq(void) {
+    spi_rx_irq(RSPISPRI0_IRQn, 0);
+}
+static void spi0_er_irq(void) {
+    spi_err_irq(RSPISPEI0_IRQn, 0);
+}
+static void spi1_rx_irq(void) {
+    spi_rx_irq(RSPISPRI1_IRQn, 1);
+}
+static void spi1_er_irq(void) {
+    spi_err_irq(RSPISPEI1_IRQn, 1);
+}
+static void spi2_rx_irq(void) {
+    spi_rx_irq(RSPISPRI2_IRQn, 2);
+}
+static void spi2_er_irq(void) {
+    spi_err_irq(RSPISPEI2_IRQn, 2);
+}
+static void spi3_rx_irq(void) {
+    spi_rx_irq(RSPISPRI3_IRQn, 3);
+}
+static void spi3_er_irq(void) {
+    spi_err_irq(RSPISPEI3_IRQn, 3);
+}
+static void spi4_rx_irq(void) {
+    spi_rx_irq(RSPISPRI4_IRQn, 4);
+}
+static void spi4_er_irq(void) {
+    spi_err_irq(RSPISPEI4_IRQn, 4);
+}
+
+static void spi_irqs_set(spi_t *obj, uint32_t enable)
+{
+    int i;
+    const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index];
+    const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index];
+    for (i = 0; i < IRQ_NUM; ++i) {
+        if (enable) {
+            InterruptHandlerRegister(irqTable[i], handlerTable[i]);
+            GIC_SetPriority(irqTable[i], 5);
+            GIC_SetConfiguration(irqTable[i], 1);
+            GIC_EnableIRQ(irqTable[i]);
+        } else {
+            GIC_DisableIRQ(irqTable[i]);
+        }
+    }
+    if (enable) {
+        obj->spi.spi->SPCR |= (1 << 4) | (1 << 7);
+    } else {
+        obj->spi.spi->SPCR &= ~((1 << 4) | (1 << 7));
+    }
+}
+
+static void spi_async_write(spi_t *obj)
+{
+    uint8_t **width8;
+    uint16_t **width16;
+    uint32_t **width32;
+    
+    if (obj->tx_buff.buffer) {
+        switch (obj->tx_buff.width) {
+            case 8:
+                width8 = (uint8_t **)&obj->tx_buff.buffer;
+                spi_write(obj, **width8);
+                ++*width8;
+                obj->tx_buff.pos += sizeof(uint8_t);
+                break;
+                
+            case 16:
+                width16 = (uint16_t **)&obj->tx_buff.buffer;
+                spi_write(obj, **width16);
+                ++*width16;
+                obj->tx_buff.pos += sizeof(uint16_t);
+                break;
+                
+            case 32:
+                width32 = (uint32_t **)&obj->tx_buff.buffer;
+                spi_write(obj, **width32);
+                ++*width32;
+                obj->tx_buff.pos += sizeof(uint32_t);
+                break;
+                
+            default:
+                MBED_ASSERT(0);
+                break;
+        }
+    } else {
+        spi_write(obj, SPI_FILL_WORD);
+    }
+}
+
+static void spi_async_read(spi_t *obj)
+{
+    uint8_t **width8;
+    uint16_t **width16;
+    uint32_t **width32;
+    
+    switch (obj->rx_buff.width) {
+        case 8:
+            width8 = (uint8_t **)&obj->rx_buff.buffer;
+            **width8 = spi_read(obj);
+            ++*width8;
+            obj->rx_buff.pos += sizeof(uint8_t);
+            break;
+            
+        case 16:
+            width16 = (uint16_t **)&obj->rx_buff.buffer;
+            **width16 = spi_read(obj);
+            ++*width16;
+            obj->rx_buff.pos += sizeof(uint16_t);
+            break;
+            
+        case 32:
+            width32 = (uint32_t **)&obj->rx_buff.buffer;
+            **width32 = spi_read(obj);
+            ++*width32;
+            obj->rx_buff.pos += sizeof(uint32_t);
+            break;
+            
+        default:
+            MBED_ASSERT(0);
+            break;
+    }
+}
+
+/******************************************************************************
+ * ASYNCHRONOUS HAL
+ ******************************************************************************/
+
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    int i;
+    MBED_ASSERT(obj);
+    MBED_ASSERT(tx || rx);
+    MBED_ASSERT(tx && ! rx ? tx_length : 1);
+    MBED_ASSERT(rx && ! tx ? rx_length : 1);
+    MBED_ASSERT(obj->spi.spi->SPCR & (1 << 3)); /* Slave mode */
+    MBED_ASSERT(bit_width == 8 || bit_width == 16 || bit_width == 32);
+    
+    if (tx_length) {
+        obj->tx_buff.buffer = (void *)tx;
+    } else {
+        obj->tx_buff.buffer = NULL;
+    }
+    obj->tx_buff.length = tx_length * bit_width / 8;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = bit_width;
+    if (rx_length) {
+        obj->rx_buff.buffer = rx;
+    } else {
+        obj->rx_buff.buffer = NULL;
+    }
+    obj->rx_buff.length = rx_length * bit_width / 8;
+    obj->rx_buff.pos = 0;
+    obj->rx_buff.width = bit_width;
+    for (i = 0; i < (int)obj->rx_buff.length; i++) {
+        ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD;
+    }
+    
+    spi_data[obj->spi.index].async_callback = handler;
+    spi_data[obj->spi.index].async_obj = obj;
+    spi_data[obj->spi.index].event = 0;
+    spi_data[obj->spi.index].wanted_events = event;
+    
+    spi_irqs_set(obj, 1);
+    
+    spi_async_write(obj);
+}
+
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+    return spi_data[obj->spi.index].event;
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+    return spi_data[obj->spi.index].async_obj != NULL;
+}
+
+void spi_abort_asynch(spi_t *obj)
+{
+    spi_disable(obj);
+    spi_irqs_set(obj, 0);
+    spi_data[obj->spi.index].async_obj = NULL;
+    spi_enable(obj);
+}
+
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/spibsc.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/spibsc.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/spibsc.h	(revision 374)
@@ -0,0 +1,154 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name    : spibsc.h
+* $Rev: 12 $
+* $Date:: 2016-05-19 17:26:37 +0900#$
+* Description  : 
+******************************************************************************/
+#ifndef _SPIBSC_H_
+#define _SPIBSC_H_
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "iodefine.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define SPIBSC_CMNCR_MD_EXTRD       (0u)
+#define SPIBSC_CMNCR_MD_SPI         (1u)
+
+#define SPIBSC_OUTPUT_LOW           (0u)
+#define SPIBSC_OUTPUT_HIGH          (1u)
+#define SPIBSC_OUTPUT_LAST          (2u)
+#define SPIBSC_OUTPUT_HiZ           (3u)
+
+#define SPIBSC_CMNCR_CPHAT_EVEN     (0u)
+#define SPIBSC_CMNCR_CPHAT_ODD      (1u)
+
+#define SPIBSC_CMNCR_CPHAR_ODD      (0u)
+#define SPIBSC_CMNCR_CPHAR_EVEN     (1u)
+
+#define SPIBSC_CMNCR_SSLP_LOW       (0u)
+#define SPIBSC_CMNCR_SSLP_HIGH      (1u)
+
+#define SPIBSC_CMNCR_CPOL_LOW       (0u)
+#define SPIBSC_CMNCR_CPOL_HIGH      (1u)
+
+#define SPIBSC_CMNCR_BSZ_SINGLE     (0u)
+#define SPIBSC_CMNCR_BSZ_DUAL       (1u)
+
+#define SPIBSC_DELAY_1SPBCLK        (0u)
+#define SPIBSC_DELAY_2SPBCLK        (1u)
+#define SPIBSC_DELAY_3SPBCLK        (2u)
+#define SPIBSC_DELAY_4SPBCLK        (3u)
+#define SPIBSC_DELAY_5SPBCLK        (4u)
+#define SPIBSC_DELAY_6SPBCLK        (5u)
+#define SPIBSC_DELAY_7SPBCLK        (6u)
+#define SPIBSC_DELAY_8SPBCLK        (7u)
+
+
+#define SPIBSC_BURST_1              (0x00u)
+#define SPIBSC_BURST_2              (0x01u)
+#define SPIBSC_BURST_3              (0x02u)
+#define SPIBSC_BURST_4              (0x03u)
+#define SPIBSC_BURST_5              (0x04u)
+#define SPIBSC_BURST_6              (0x05u)
+#define SPIBSC_BURST_7              (0x06u)
+#define SPIBSC_BURST_8              (0x07u)
+#define SPIBSC_BURST_9              (0x08u)
+#define SPIBSC_BURST_10             (0x09u)
+#define SPIBSC_BURST_11             (0x0au)
+#define SPIBSC_BURST_12             (0x0bu)
+#define SPIBSC_BURST_13             (0x0cu)
+#define SPIBSC_BURST_14             (0x0du)
+#define SPIBSC_BURST_15             (0x0eu)
+#define SPIBSC_BURST_16             (0x0fu)
+
+#define SPIBSC_BURST_DISABLE        (0u)
+#define SPIBSC_BURST_ENABLE         (1u)
+
+#define SPIBSC_DRCR_RCF_EXE         (1u)
+
+#define SPIBSC_SSL_NEGATE           (0u)
+#define SPIBSC_TRANS_END            (1u)
+
+#define SPIBSC_1BIT                 (0u)
+#define SPIBSC_2BIT                 (1u)
+#define SPIBSC_4BIT                 (2u)
+
+#define SPIBSC_OUTPUT_DISABLE       (0u)
+#define SPIBSC_OUTPUT_ENABLE        (1u)
+#define SPIBSC_OUTPUT_ADDR_24       (0x07u)
+#define SPIBSC_OUTPUT_ADDR_32       (0x0fu)
+#define SPIBSC_OUTPUT_OPD_3         (0x08u)
+#define SPIBSC_OUTPUT_OPD_32        (0x0cu)
+#define SPIBSC_OUTPUT_OPD_321       (0x0eu)
+#define SPIBSC_OUTPUT_OPD_3210      (0x0fu)
+
+#define SPIBSC_OUTPUT_SPID_8        (0x08u)
+#define SPIBSC_OUTPUT_SPID_16       (0x0cu)
+#define SPIBSC_OUTPUT_SPID_32       (0x0fu)
+
+#define SPIBSC_SPISSL_NEGATE        (0u)
+#define SPIBSC_SPISSL_KEEP          (1u)
+
+#define SPIBSC_SPIDATA_DISABLE      (0u)
+#define SPIBSC_SPIDATA_ENABLE       (1u)
+
+#define SPIBSC_SPI_DISABLE          (0u)
+#define SPIBSC_SPI_ENABLE           (1u)
+
+
+/* Use for setting of the DME bit of "data read enable register"(DRENR) */
+#define SPIBSC_DUMMY_CYC_DISABLE    (0u)
+#define SPIBSC_DUMMY_CYC_ENABLE     (1u)
+
+/* Use for setting of the DMCYC [2:0] bit of "data read dummy cycle register"(DRDMCR) */
+#define SPIBSC_DUMMY_1CYC           (0u)
+#define SPIBSC_DUMMY_2CYC           (1u)
+#define SPIBSC_DUMMY_3CYC           (2u)
+#define SPIBSC_DUMMY_4CYC           (3u)
+#define SPIBSC_DUMMY_5CYC           (4u)
+#define SPIBSC_DUMMY_6CYC           (5u)
+#define SPIBSC_DUMMY_7CYC           (6u)
+#define SPIBSC_DUMMY_8CYC           (7u)
+
+/* Use for setting of "data read DDR enable register"(DRDRENR) */
+#define SPIBSC_SDR_TRANS            (0u)
+#define SPIBSC_DDR_TRANS            (1u)
+
+/* Use for setting the CKDLY regsiter */
+#define SPIBSC_CKDLY_DEFAULT        (0x0000A504uL)    /* Initial value */
+#define SPIBSC_CKDLY_TUNING         (0x0000A50AuL)    /* Shorten the data input setup time and extend the data hold time */
+
+/* Use for setting the SPODLY regsiter */
+#define SPIBSC_SPODLY_DEFAULT       (0xA5000000uL)    /* Initial value */
+#define SPIBSC_SPODLY_TUNING        (0xA5001111uL)    /* Delay the data output delay/hold/buffer-on/buffer-off time */
+
+#endif /* _SPIBSC_H_ */
+
+/* End of File */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/trng_api.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/trng_api.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/trng_api.c	(revision 374)
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_TRNG)
+#include "trng_api.h"
+
+#if defined(TARGET_GR_LYCHEE) || defined(TARGET_RZA1H)
+
+extern void trng_init_esp32(void);
+extern void trng_free_esp32(void);
+extern int trng_get_bytes_esp32(uint8_t *output, size_t length, size_t *output_length);
+
+void trng_init(trng_t *obj)
+{
+    trng_init_esp32();
+}
+
+void trng_free(trng_t *obj)
+{
+    trng_free_esp32();
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    return trng_get_bytes_esp32(output, length, output_length);
+}
+#else
+#error "There is no initialization processing."
+#endif
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/us_ticker.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/us_ticker.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/us_ticker.c	(revision 374)
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "us_ticker_api.h"
+#include "mbed_drv_cfg.h"
+
+#define SHIFT_NUM      5  /* P0/32 */
+
+static int us_ticker_inited = 0;
+
+void us_ticker_init(void)
+{
+    GIC_DisableIRQ(OSTMI1TINT_IRQn);
+    GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
+
+    /* Power Control for Peripherals      */
+    CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
+
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+
+    // timer settings
+    OSTM1TT   = 0x01;    /* Stop the counter and clears the OSTM1TE bit.     */
+    OSTM1CTL  = 0x02;    /* Free running timer mode. Interrupt disabled when star counter  */
+
+    OSTM1TS   = 0x1;     /* Start the counter and sets the OSTM0TE bit.     */
+
+    // INTC settings
+    InterruptHandlerRegister(OSTMI1TINT_IRQn, (void (*)(uint32_t))us_ticker_irq_handler);
+    GIC_SetPriority(OSTMI1TINT_IRQn, 5);
+    GIC_SetConfiguration(OSTMI1TINT_IRQn, 3);
+}
+
+void us_ticker_free(void)
+{
+    GIC_DisableIRQ(OSTMI1TINT_IRQn);
+    GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
+
+    /* Power Control for Peripherals      */
+    CPGSTBCR5 |= (CPG_STBCR5_BIT_MSTP50); /* disable OSTM1 clock */
+}
+
+uint32_t us_ticker_read()
+{
+    return (uint32_t)(OSTM1CNT >> SHIFT_NUM);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    OSTM1CMP = (uint32_t)(timestamp << SHIFT_NUM);
+    GIC_EnableIRQ(OSTMI1TINT_IRQn);
+}
+
+void us_ticker_fire_interrupt(void)
+{
+    GIC_SetPendingIRQ(OSTMI1TINT_IRQn);
+    GIC_EnableIRQ(OSTMI1TINT_IRQn);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    GIC_DisableIRQ(OSTMI1TINT_IRQn);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
+}
+
+const ticker_info_t* us_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        (uint32_t)((float)RENESAS_RZ_A1_P0_CLK / (float)(1 << SHIFT_NUM) + 0.5f),
+        (32 - SHIFT_NUM)
+    };
+    return &info;
+}
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/mbed_rtx.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/mbed_rtx.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/mbed_rtx.h	(revision 374)
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_MBED_RTX_H
+#define MBED_MBED_RTX_H
+
+#include <stdint.h>
+
+#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE)
+
+#if defined(__CC_ARM)
+    extern char Image$$ARM_LIB_STACK$$Base[];
+    extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+    extern char Image$$ARM_LIB_HEAP$$Base[];
+    #define ISR_STACK_START       ((unsigned char*)Image$$ARM_LIB_STACK$$Base)
+    #define ISR_STACK_SIZE        ((uint32_t)((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - (uint32_t)Image$$ARM_LIB_STACK$$Base))
+    #define INITIAL_SP            (Image$$ARM_LIB_STACK$$ZI$$Limit)
+    #define HEAP_START            ((unsigned char*)Image$$ARM_LIB_HEAP$$Base)
+    #define HEAP_SIZE             ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START))
+#elif defined(__GNUC__)
+    extern uint32_t               __StackTop;
+    extern uint32_t               __StackLimit;
+    extern uint32_t               __end__;
+    #define ISR_STACK_START       ((unsigned char*)&__StackLimit)
+    #define ISR_STACK_SIZE        ((uint32_t)((uint32_t)&__StackTop - (uint32_t)&__StackLimit))
+    #define INITIAL_SP            (&__StackTop)
+    #define HEAP_START            ((unsigned char*)&__end__)
+    #define HEAP_SIZE             ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START))
+#elif defined(__ICCARM__)
+    /* No region declarations needed */
+#else
+    #error "no toolchain defined"
+#endif
+#endif
+
+#endif  // MBED_MBED_RTX_H
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/sample/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/sample/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/sample/Makefile	(revision 374)
@@ -191,5 +191,5 @@
 	APPL_COBJS := @(APPLOBJS)
 endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_CFLAGS := $(APPL_CFLAGS)
 ifdef APPLDIRS
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/sample/sample1.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/sample/sample1.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/sample/sample1.cfg	(revision 374)
@@ -5,4 +5,5 @@
  */
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 
 #include "sample1.h"
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/Makefile.target
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/Makefile.target	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/Makefile.target	(revision 374)
@@ -30,4 +30,7 @@
 endif
 
+CDEFS := $(CDEFS) -DUSE_ARM_FPU
+COPTS := $(COPTS) -mfloat-abi=hard
+
 #
 #  MPCoreの種類の定義
@@ -55,5 +58,5 @@
 	CDEFS := $(CDEFS) -DTOPPERS_EXECUTE_ON_ROM
 	#LDSCRIPT = $(TARGETDIR)/gr_peach_rom.ld
-	LDSCRIPT = $(SRCDIR)/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld
+	LDSCRIPT = $(SRCDIR)/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld
 else
 	CDEFS := $(CDEFS) -DTOPPERS_EXECUTE_ON_RAM
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/cfg_dmy.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/cfg_dmy.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/cfg_dmy.c	(revision 374)
@@ -1,5 +1,6 @@
 #include "MBRZA1H.h"
+#include <stdlib.h>
 
-IRQHandler _kernel_inh_table[Renesas_RZ_A1_IRQ_MAX+1];
+IRQHandler _kernel_inh_table[RZ_A1_IRQ_MAX+1];
 uint32_t _kernel_excpt_nest_count = 0;
 
@@ -23,4 +24,5 @@
 {
 }
+
 void _kernel_irq_handler()
 {
@@ -31,5 +33,23 @@
 }
 
-void _start()
+void __libc_init_array()
 {
 }
+
+void *memset(void *dst, int c, size_t size)
+{
+	return NULL;
+}
+
+void *memcpy(void *dst, void * src, size_t size)
+{
+	return NULL;
+}
+
+int main()
+{
+}
+
+void exit(int exitcd)
+{
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/tSIOPortGRPeach.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/tSIOPortGRPeach.cdl	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/tSIOPortGRPeach.cdl	(revision 374)
@@ -50,10 +50,10 @@
  */
 import_C("gr_peach.h");
-import_C("rza1.h");
+import_C("device.h");
 
 /*
  *  FIFO内蔵シリアルコミュニケーションインタフェース用 簡易SIOドライバ
  */
-import("tSCIF.cdl");
+import("tMbedSerial.cdl");
 
 /*
@@ -73,10 +73,4 @@
 	call			sSIOPort	cSIOPort;
 	[inline] entry	siSIOCBR	eiSIOCBR;
-
-	/*
-	 *  割込み要求ライン操作のための結合
-	 */
-	call	sInterruptRequest	cRxInterruptRequest;
-	call	sInterruptRequest	cTxInterruptRequest;
 };
 
@@ -85,5 +79,4 @@
  *  ト）のセルタイプ
  */
-[active]
 composite tSIOPortGRPeach {
 	/*
@@ -97,9 +90,6 @@
 	 */
 	attr {
-		uintptr_t	baseAddress;				/* ベースアドレス */
-		INTNO		rxInterruptNumber;			/* 受信割込み番号 */
-		INTNO		txInterruptNumber;			/* 送信割込み番号 */
-		PRI			isrPriority = 1;			/* ISR優先度 */
-		PRI			interruptPriority = -4;		/* 割込み優先度 */
+		int32_t tx;								/* 送信Pin */
+		int32_t rx;								/* 受信Pin */
 		uint32_t	baudRate = 115200;			/* ボーレートの設定値 */
 	};
@@ -108,6 +98,7 @@
 	 *  SIOドライバ
 	 */
-	cell tSCIF SCIF {
-		baseAddress = composite.baseAddress;
+	cell tMbedSerial MbedSerial {
+		tx          = composite.tx;
+		rx          = composite.rx;
 		baudRate    = composite.baudRate;
 		ciSIOCBR    = SIOPortMain.eiSIOCBR;
@@ -119,35 +110,7 @@
 	cell tSIOPortGRPeachMain SIOPortMain {
 		ciSIOCBR            => composite.ciSIOCBR;
-		cSIOPort            = SCIF.eSIOPort;
-		cRxInterruptRequest = RxInterruptRequest.eInterruptRequest;
-		cTxInterruptRequest = TxInterruptRequest.eInterruptRequest;
+		cSIOPort            = MbedSerial.eSIOPort;
 	};
 	composite.eSIOPort => SIOPortMain.eSIOPort;
-
-	/*
-	 *  SIOの受信割込みサービスルーチンと割込み要求ライン
-	 */
-	cell tISR RxISRInstance {
-		interruptNumber = composite.rxInterruptNumber;
-		isrPriority     = composite.isrPriority;
-		ciISRBody       = SCIF.eiRxISR;
-	};
-	cell tInterruptRequest RxInterruptRequest {
-		interruptNumber   = composite.rxInterruptNumber;
-		interruptPriority = composite.interruptPriority;
-	};
-
-	/*
-	 *  SIOの受信割込みサービスルーチンと割込み要求ライン
-	 */
-	cell tISR TxISRInstance {
-		interruptNumber = composite.txInterruptNumber;
-		isrPriority     = composite.isrPriority;
-		ciISRBody       = SCIF.eiTxISR;
-	};
-	cell tInterruptRequest TxInterruptRequest {
-		interruptNumber   = composite.txInterruptNumber;
-		interruptPriority = composite.interruptPriority;
-	};
 };
 
@@ -157,13 +120,12 @@
  *  サンプルプログラムが使うポートが，SIOPortTarget1に固定されているた
  *  め，ポート1とポート3を入れ換えている．具体的には，SIOPortTarget1は
- *  SCIFのチャネル2（チャネル番号は0から始まるので，ポート3のこと）に，
- *  SIOPortTarget3はSCIFのチャネル0につながっている．
+ *  MbedSerialのチャネル2（チャネル番号は0から始まるので，ポート3のこと）に，
+ *  SIOPortTarget3はMbedSerialのチャネル0につながっている．
  */
 [prototype]
 cell tSIOPortGRPeach SIOPortTarget1 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF2_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF2_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF2_TXI");
+	tx = C_EXP("P6_3");
+	rx = C_EXP("P6_2");
 };
 
@@ -171,7 +133,6 @@
 cell tSIOPortGRPeach SIOPortTarget2 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF1_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF1_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF1_TXI");
+	tx = C_EXP("P2_5");
+	rx = C_EXP("P2_6");
 };
 
@@ -179,7 +140,6 @@
 cell tSIOPortGRPeach SIOPortTarget3 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF0_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF0_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF0_TXI");
+	tx = C_EXP("P4_12");
+	rx = C_EXP("P4_13");
 };
 
@@ -187,7 +147,6 @@
 cell tSIOPortGRPeach SIOPortTarget4 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF3_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF3_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF3_TXI");
+	tx = C_EXP("P2_14");
+	rx = C_EXP("P2_15");
 };
 
@@ -195,7 +154,6 @@
 cell tSIOPortGRPeach SIOPortTarget5 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF4_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF4_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF4_TXI");
+	tx = C_EXP("P4_14");
+	rx = C_EXP("P4_15");
 };
 
@@ -203,7 +161,6 @@
 cell tSIOPortGRPeach SIOPortTarget6 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF5_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF5_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF5_TXI");
+	tx = C_EXP("P5_3");
+	rx = C_EXP("P5_4");
 };
 
@@ -211,7 +168,6 @@
 cell tSIOPortGRPeach SIOPortTarget7 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF6_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF6_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF6_TXI");
+	tx = C_EXP("P8_8");
+	rx = C_EXP("P8_9");
 };
 
@@ -219,6 +175,54 @@
 cell tSIOPortGRPeach SIOPortTarget8 {
 	/* 属性の設定 */
-	baseAddress       = C_EXP("SCIF7_BASE");
-	rxInterruptNumber = C_EXP("INTNO_SCIF7_RXI");
-	txInterruptNumber = C_EXP("INTNO_SCIF7_TXI");
-};
+	tx = C_EXP("P5_0");
+	rx = C_EXP("P5_1");
+};
+
+[prototype]
+cell tSIOPortGRPeach SIOPortTarget9 {
+	/* 属性の設定 */
+	tx = C_EXP("P8_14");
+	rx = C_EXP("P8_15");
+};
+
+[prototype]
+cell tSIOPortGRPeach SIOPortTarget10 {
+	/* 属性の設定 */
+	tx = C_EXP("P8_13");
+	rx = C_EXP("P8_11");
+};
+
+[prototype]
+cell tSIOPortGRPeach SIOPortTarget11 {
+	/* 属性の設定 */
+	tx = C_EXP("P11_10");
+	rx = C_EXP("P11_11");
+};
+
+[prototype]
+cell tSIOPortGRPeach SIOPortTarget12 {
+	/* 属性の設定 */
+	tx = C_EXP("P6_6");
+	rx = C_EXP("P6_7");
+};
+
+[prototype]
+cell tSIOPortGRPeach SIOPortTarget13 {
+	/* 属性の設定 */
+	tx = C_EXP("P5_6");
+	rx = C_EXP("P5_7");
+};
+
+[prototype]
+cell tSIOPortGRPeach SIOPortTarget14 {
+	/* 属性の設定 */
+	tx = C_EXP("P11_1");
+	rx = C_EXP("P11_2");
+};
+
+[prototype]
+cell tSIOPortGRPeach SIOPortTarget15 {
+	/* 属性の設定 */
+	tx = C_EXP("P7_4");
+	rx = C_EXP("P7_5");
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/tSIOPortGRPeachMain_inline.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/tSIOPortGRPeachMain_inline.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/tSIOPortGRPeachMain_inline.h	(revision 374)
@@ -57,10 +57,4 @@
 	 */
 	cSIOPort_open();
-
-	/*
-	 *  SIOの割込みマスクを解除する．
-	 */
-	cRxInterruptRequest_enable();
-	cTxInterruptRequest_enable();
 }
 
@@ -77,10 +71,4 @@
 	 */
 	cSIOPort_close();
-
-	/*
-	 *  SIOの割込みをマスクする．
-	 */
-	cRxInterruptRequest_disable();
-	cTxInterruptRequest_disable();
 }
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/target_kernel_impl.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/target_kernel_impl.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/target/gr_peach_gcc/target_kernel_impl.c	(revision 374)
@@ -47,7 +47,13 @@
 #include "arm.h"
 #include "rza1.h"
-#include "scif.h"
-#include "core_pl310.h"
-#include "us_ticker_api.h"
+
+/*
+ * C++のグローバルコンストラクタ呼び出し
+ */
+void __libc_init_array()
+{
+	/* グローバルコンストラクタでOS APIを呼び出す場合は、
+	   タスクが起動してから行う */
+}
 
 /*
@@ -209,5 +215,5 @@
  *  セルタイプtPutLogGRPeach内に実装されている関数を直接呼び出す．
  */
-extern void	tPutLogGRPeach_initialize(void);
+extern void tPutLogGRPeach_initialize(void);
 
 /*
@@ -294,98 +300,2 @@
 	rza1_config_port(RZA1_PORT_P(6), led, set);
 }
-
-void us_ticker_init(void)
-{
-}
-
-uint32_t us_ticker_read()
-{
-	ER ret;
-	SYSTIM now;
-
-	ret = get_tim(&now);
-	if(ret != E_OK)
-		return 0;
-
-	return now;
-}
-
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
-	Asm("bkpt #0");
-}
-
-void us_ticker_disable_interrupt(void)
-{
-}
-
-void us_ticker_clear_interrupt(void)
-{
-}
-
-void wait(float s)
-{
-	wait_us(s * 1000000.0f);
-}
-
-void wait_ms(int ms)
-{
-	wait_us(ms * 1000);
-}
-
-void wait_us(int us)
-{
-	ER ret;
-
-	ret = dly_tsk(us);
-	if (ret == E_CTX){
-		uint32_t start = us_ticker_read();
-		while ((us_ticker_read() - start) < (uint32_t)us);
-	}
-}
-
-//#include <errno.h>
-#define ENOSYS          38
-
-__attribute__((weak))
-long SYS_poll()
-{
-	return -ENOSYS;
-}
-
-__attribute__((weak))
-long SYS_open()
-{
-	return -ENOSYS;
-}
-
-__attribute__((weak))
-void SYS_set_tid_address()
-{
-	return 0;//-ENOSYS;
-}
-
-__attribute__((weak))
-void SYS_mmap2()
-{
-	return 0;//-ENOSYS;
-}
-
-__attribute__((weak))
-void ARM_SYS_set_tls(long a)
-{
-	__asm__ __volatile__("mcr p15,0,%0,c13,c0,3" :: "r"(a));
-	return 0;
-}
-
-__attribute__((weak))
-void SYS_exit_group()
-{
-	ext_ker();
-}
-
-__attribute__((weak))
-void SYS_exit()
-{
-	ext_ker();
-}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/MANIFEST_for_asp3
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/MANIFEST_for_asp3	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/MANIFEST_for_asp3	(revision 374)
@@ -0,0 +1,106 @@
+MANIFEST_for_asp3
+
+tecsgen
+tecsgen.rb
+tecsmerge
+tecsmerge.rb
+
+tecslib/version.rb
+
+tecslib/core/C_parser.tab.rb
+tecslib/core/C_parser.y.rb
+tecslib/core/bnf.tab.rb
+tecslib/core/bnf.y.rb
+tecslib/core/componentobj.rb
+tecslib/core/ctypes.rb
+tecslib/core/expression.rb
+tecslib/core/gen_xml.rb
+tecslib/core/generate.rb
+tecslib/core/location.rb
+tecslib/core/messages.rb
+tecslib/core/optimize.rb
+tecslib/core/plugin.rb
+tecslib/core/pluginModule.rb
+tecslib/core/syntaxobj.rb
+tecslib/core/tecs_lang.rb
+tecslib/core/tecsgen.rb
+tecslib/core/tecsinfo.rb
+tecslib/core/tool_info.rb
+tecslib/core/types.rb
+tecslib/core/unjoin_plugin.rb
+tecslib/core/value.rb
+
+tecslib/messages/messages_console_en_US.rb
+tecslib/messages/messages_console_ja_JP.rb
+tecslib/messages/messages_file_en_US.rb
+tecslib/messages/messages_file_ja_JP.rb
+
+tecslib/plugin/C2TECSBridgePlugin.rb
+tecslib/plugin/CellPlugin.rb
+tecslib/plugin/CelltypePlugin.rb
+tecslib/plugin/CompositePlugin.rb
+tecslib/plugin/DomainPlugin.rb
+tecslib/plugin/Mruby2CBridgePlugin.rb
+tecslib/plugin/MrubyBridgePlugin.rb
+tecslib/plugin/MultiPlugin.rb
+tecslib/plugin/NotifierPlugin.rb
+tecslib/plugin/RPCPlugin.rb
+tecslib/plugin/SignaturePlugin.rb
+tecslib/plugin/TECS2CBridgePlugin.rb
+tecslib/plugin/ThroughPlugin.rb
+tecslib/plugin/TracePlugin.rb
+tecslib/plugin/lib/GenParamCopy.rb
+tecslib/plugin/lib/GenTransparentMarshaler.rb
+
+tecs/tecs.h
+tecs/tecs.xsd
+
+tecs/mruby/TECSPointer.h
+tecs/mruby/TECSStruct.h
+tecs/mruby/mruby.cdl
+tecs/mruby/mrubyInitializer.cdl
+tecs/mruby/mrubyPointers.cdl
+tecs/mruby/mrubyVMs.cdl
+tecs/mruby/nMruby_tBoolPointer.c
+tecs/mruby/nMruby_tCharPointer.c
+tecs/mruby/nMruby_tDouble64Pointer.c
+tecs/mruby/nMruby_tFloat32Pointer.c
+tecs/mruby/nMruby_tInt16Pointer.c
+tecs/mruby/nMruby_tInt32Pointer.c
+tecs/mruby/nMruby_tInt64Pointer.c
+tecs/mruby/nMruby_tInt8Pointer.c
+tecs/mruby/nMruby_tIntPointer.c
+tecs/mruby/nMruby_tLongPointer.c
+tecs/mruby/nMruby_tMruby.c
+tecs/mruby/nMruby_tSCharPointer.c
+tecs/mruby/nMruby_tShortPointer.c
+tecs/mruby/nMruby_tTECSInitializer.c
+tecs/mruby/nMruby_tUCharPointer.c
+tecs/mruby/nMruby_tUInt16Pointer.c
+tecs/mruby/nMruby_tUInt32Pointer.c
+tecs/mruby/nMruby_tUInt64Pointer.c
+tecs/mruby/nMruby_tUInt8Pointer.c
+tecs/mruby/nMruby_tUIntPointer.c
+tecs/mruby/nMruby_tULongPointer.c
+tecs/mruby/nMruby_tUShortPointer.c
+tecs/mruby/tMruby.cdl
+tecs/mruby/tecs_mruby.h
+
+tecs/posix/posix.cdl
+
+tecs/rpc/PPAllocator.cdl
+tecs/rpc/RPCTask.cdl
+tecs/rpc/TDR.cdl
+tecs/rpc/rpc.cdl
+tecs/rpc/rpc_string.h
+tecs/rpc/sChannel.cdl
+tecs/rpc/sRPCErrorHandler.cdl
+tecs/rpc/tDataqueueAdaptor_inline.h
+tecs/rpc/tDataqueueOWChannel.cdl
+tecs/rpc/tPPAllocator.c
+tecs/rpc/tRPCDedicatedTaskMain.c
+tecs/rpc/tTDR_inline.h
+tecs/rpc/tecs_rpc.h
+tecs/rpc/tMessageBufferCEP.cdl
+tecs/rpc/tMessageBufferCEP_inline.h
+tecs/rpc/tMessageBufferChannel.cdl
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/MANIFEST_tecsgen_body
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/MANIFEST_tecsgen_body	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/MANIFEST_tecsgen_body	(revision 374)
@@ -1,5 +1,12 @@
 MANIFEST_tecsgen_body
+
 Makefile
-
+tecscde
+tecscde.rb
+tecsgen
+tecsgen.rb
+tecsgen_rcov.rb
+tecsmerge
+tecsmerge.rb
 cdelib/Makefile
 cdelib/cell_plugin_dialog.rb
@@ -11,8 +18,7 @@
 cdelib/tview.rb
 cdelib/version.rb
-
 tecs/TECSInfo/TECSInfo.cdl
+tecs/TECSInfo/TECSInfoAccessor.cdl
 tecs/TECSInfo/nTECSInfo_tArrayTypeInfo.c
-tecs/TECSInfo/nTECSInfo_tAttrVarInfo.c
 tecs/TECSInfo/nTECSInfo_tBoolTypeInfo.c
 tecs/TECSInfo/nTECSInfo_tCallInfo.c
@@ -28,7 +34,9 @@
 tecs/TECSInfo/nTECSInfo_tParamInfo.c
 tecs/TECSInfo/nTECSInfo_tPtrTypeInfo.c
+tecs/TECSInfo/nTECSInfo_tRawEntryDescriptorInfo.c
 tecs/TECSInfo/nTECSInfo_tRegionInfo.c
 tecs/TECSInfo/nTECSInfo_tSignatureInfo.c
 tecs/TECSInfo/nTECSInfo_tStructTypeInfo.c
+tecs/TECSInfo/nTECSInfo_tTECSInfoAccessor.c
 tecs/TECSInfo/nTECSInfo_tTECSInfoSub.c
 tecs/TECSInfo/nTECSInfo_tTECSInfo_inline.h
@@ -36,4 +44,5 @@
 tecs/TECSInfo/nTECSInfo_tVarDeclInfo.c
 tecs/TECSInfo/nTECSInfo_tVoidTypeInfo.c
+tecs/TECSInfo/tTECSInfoAccessor.c
 tecs/TLSFMalloc/README-TLSF.txt
 tecs/TLSFMalloc/tTLSFMalloc.cdl
@@ -61,4 +70,5 @@
 tecs/mruby/nMruby_tMruby.c
 tecs/mruby/nMruby_tMrubyCyclicTaskBody.c
+tecs/mruby/nMruby_tMrubyProc.c
 tecs/mruby/nMruby_tMrubyTaskBody.c
 tecs/mruby/nMruby_tMrubyVM.c
@@ -87,4 +97,7 @@
 tecs/rpc/tDataqueueAdaptor_inline.h
 tecs/rpc/tDataqueueOWChannel.cdl
+tecs/rpc/tMessageBufferCEP.cdl
+tecs/rpc/tMessageBufferCEP_inline.h
+tecs/rpc/tMessageBufferChannel.cdl
 tecs/rpc/tNBOTDR_inline.h
 tecs/rpc/tPPAllocator.c
@@ -105,11 +118,4 @@
 tecs/tecs.h
 tecs/tecs.xsd
-
-tecscde
-tecscde.rb
-tecsgen
-tecsgen.rb
-tecsgen_rcov
-tecsgen_rcov.rb
 tecslib/core/C_parser.tab.rb
 tecslib/core/C_parser.y.rb
@@ -132,4 +138,5 @@
 tecslib/core/tool_info.rb
 tecslib/core/types.rb
+tecslib/core/unjoin_plugin.rb
 tecslib/core/value.rb
 tecslib/messages/messages_console_en_US.rb
@@ -165,7 +172,16 @@
 tecslib/plugin/HRP2SemaphorePlugin.rb
 tecslib/plugin/HRP2TaskPlugin.rb
+tecslib/plugin/HRPHandlerPlugin.rb
+tecslib/plugin/HRPKernelObjectManager.rb
+tecslib/plugin/HRPKernelObjectPlugin.rb
+tecslib/plugin/HRPObjectPlugin.rb
+tecslib/plugin/HRPPlugin.rb
+tecslib/plugin/HRPRPCPlugin.rb
+tecslib/plugin/HRPSVCPlugin.rb
+tecslib/plugin/HRPTaskPlugin.rb
 tecslib/plugin/Mruby2CBridgePlugin.rb
 tecslib/plugin/MrubyBridgeCellPlugin.rb
 tecslib/plugin/MrubyBridgeCelltypePlugin.rb
+tecslib/plugin/MrubyBridgeCompositePlugin.rb
 tecslib/plugin/MrubyBridgePlugin.rb
 tecslib/plugin/MrubyBridgeSignaturePlugin.rb
@@ -175,4 +191,6 @@
 tecslib/plugin/OpaqueRPCPlugin.rb
 tecslib/plugin/RPCPlugin.rb
+tecslib/plugin/RepeatCellPlugin.rb
+tecslib/plugin/RepeatJoinPlugin.rb
 tecslib/plugin/SharedOpaqueRPCPlugin.rb
 tecslib/plugin/SharedRPCPlugin.rb
@@ -186,6 +204,4 @@
 tecslib/plugin/lib/GenParamCopy.rb
 tecslib/plugin/lib/GenTransparentMarshaler.rb
+tecslib/plugin/lib/MrubyBridgeCelltypePluginModule.rb
 tecslib/version.rb
-
-tecsmerge
-tecsmerge.rb
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/in_exerb.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/in_exerb.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/in_exerb.rb	(revision 374)
@@ -0,0 +1,131 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2015 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#++
+
+# exerb çã§æåã«èª­ã¿ãã¾ãããã¡ã¤ã«
+# ãã®ãã¡ã¤ã«ãã generate.rb ãèª­ã¿ãã¾ãã
+
+$IN_EXERB=true
+
+# ãã®å¤æ°ã¯ exerb çã®ã¿
+$path = ENV[ 'PATH' ]
+
+#=== cygwin ã®ãã¹ã Windows ãã¹ã«å¤æ
+# cygpath ã³ãã³ããæ¢ãã¦ãè¦ã¤ããã°å¤æãã
+# å¤æã§ããªãã£ããã¾ãã¯å¤æå¾ã®ãã¹ãè¦ã¤ãããªãå ´åãdefault ãè¿ã
+def cygpath( path, default = nil )
+  if ! $IN_EXERB then
+    return default
+  end
+  if File.exist? path then
+    return default
+  end
+
+  found = false
+  $path.split( ";" ).each{ |path2|
+    cygpath_path = "#{path2}\\cygpath.exe"
+    if File.exist?( cygpath_path )  then
+      path3 = nil
+      dbgPrint "in_exerb: cygpath: found\n"
+      IO.popen( "cygpath -m #{path}", "r"){ |io|
+        path3 = io.gets.chomp!
+      }
+      dbgPrint "in_exerb: cygpath: '#{path}' => '#{path3}'\n"
+      # File.stat( path3.to_s )
+
+      if File.exist?( path3 )
+        dbgPrint "in_exerb: cygpath: '#{path3}' found\n"
+        return path3
+      else
+        break
+      end
+    end
+  }
+  dbgPrint "cygpath '#{path}' not found\n"
+  return default
+end
+
+# gcc ã®ãã¹ãè¨­å®ãã
+#  cygwin ã®ãããã¼ã¸ã§ã³ã§ã¯ gcc ã¯ gcc-3.exe ã¾ãã¯ gcc-4.exe ã¸ã®ã·ã³ããªãã¯ãªã³ã¯ã¨ãªã£ã¦ãã
+#  exerb çã§ã¯ã·ã³ããªãã¯ãªã³ã¯ãè¾¿ããªããã gcc ã® exe ãæ¢ã
+#  cygwin ã®ãªã³ã¯ã¯ãã·ã¹ãã å±æ§ãä»ããããã³ãã³ããã­ã³ããä¸ã§ã¯ dir /A:S ãæå®ããªãã¨è¡¨ç¤ºãããªã
+#  (cygwin ã®ãã¼ã¸ã§ã³ã§å®è£
+ãç°ãªããããããªã)
+#  ãã¡ã¤ã«ã®å
+é ­2ãã¤ããèª­åºã PE ãã©ã¼ãããã®ãã¸ãã¯ã«ä¸è´ãããèª¿ã¹ã
+$gcc = "gcc"
+$path.split( ";" ).each{ |path|
+  found = false
+  [ "gcc.exe", "gcc-3.exe", "gcc-4.exe" ].each{ |gcc|
+    gcc_path = "#{path}\\#{gcc}"
+    if File.exist?( gcc_path )  then
+      begin
+        magic = File.read( gcc_path, 2 )
+        if magic == "MZ"                  # ãã¸ãã¯ããã§ãã¯
+          $gcc = gcc
+          found = true
+          break
+        end
+      rescue
+        # magic ã®èª­åºãã«å¤±æãç¡è¦
+      end
+    end
+  }
+  break if found
+}
+
+# cpp ã³ãã³ããè¨­å®ãã
+$cpp = "#{$gcc} -E -D TECSGEN"
+
+# exerb ç TECS ã¸ã§ãã¬ã¼ã¿ã®å®è¡ãéå§
+require "tecsgen.rb"
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/TECSInfo.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/TECSInfo.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/TECSInfo.cdl	(revision 374)
@@ -0,0 +1,652 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+import_C( "t_stddef.h" );
+
+/* Constants of Kinds */
+const int8_t TECSTypeKind_BoolType    = 1;
+const int8_t TECSTypeKind_IntType     = 2;
+const int8_t TECSTypeKind_FloatType   = 3;
+const int8_t TECSTypeKind_PtrType     = 4;
+const int8_t TECSTypeKind_ArrayType   = 5;
+const int8_t TECSTypeKind_DefinedType = 6;
+const int8_t TECSTypeKind_StructType  = 7;
+const int8_t TECSTypeKind_EnumType    = 8;
+const int8_t TECSTypeKind_VoidType    = 9;
+const int8_t TECSTypeKind_DescriptorType = 10;
+
+/* Parameter Direction */
+const int8_t PARAM_DIR_IN         = 1;
+const int8_t PARAM_DIR_OUT        = 2;
+const int8_t PARAM_DIR_INOUT      = 3;
+const int8_t PARAM_DIR_SEND       = 4;
+const int8_t PARAM_DIR_RECEIVE    = 5;
+
+/* VarDecl declType */
+const int8_t DECLTYPE_STMEMBER    = 1;  /* Struct Member */
+const int8_t DECLTYPE_ATTR        = 2;
+const int8_t DECLTYPE_VAR         = 3;
+
+/* VarDecl place info */
+const int8_t VARDECL_PLACE_STRUCT = 1;
+const int8_t VARDECL_PLACE_NON    = 2;
+const int8_t VARDECL_PLACE_CB     = 3;
+const int8_t VARDECL_PLACE_INIB   = 4;
+
+/* CallInfo place info */
+const int8_t CALL_PLACE_NON       = 1;
+const int8_t CALL_PLACE_INIB_DES  = 2;
+const int8_t CALL_PLACE_CB_DES    = 3;
+const int8_t CALL_PLACE_INIB_IDX  = 4;
+const int8_t CALL_PLACE_CB_IDX    = 5;
+
+namespace nTECSInfo {
+
+    /*******   SIGNATURES   *******/
+
+    /* Type Information of attr, var, param, return */
+    signature sTypeInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1] = NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        uint32_t   getSize(void);    // size of the value in bytes
+        int8_t     getKind(void);    // see Constants of Kinds
+        uint32_t   getNType(void);
+           // kind == ARRAY ã®å ´åãµã¤ãºãPOINTER, TYPEDEF ã®å ´å1ãããä»¥å¤ã¯0
+        ER     getTypeInfo( [out]Descriptor(sTypeInfo) *desc );
+           // kind == POINTER, TYPEDEF ã®å ´åãdesc ã«æå¹ãªå¤ãè¿ã
+        uint32_t   getNMember(void);
+           // STRUCT ã®å ´åã¡ã³ãã¼æ°
+        ER     getMemberInfo( [in]uint32_t ith, [out]Descriptor(sVarDeclInfo) *desc );
+           // kind == STRUCT ã®å ´åãdesc ã«æå¹ãªå¤ãè¿ã
+           // ith ã¯ã¡ã³ãã¼ã®æ·»æ° 0<=ith<*num
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+//        void   getSignatureInfo( [out]Descriptor(sSignatureInfo) *desc );
+//           // kind == DESCRIPTOR ã®å ´åãdesc ã«æå¹ãªå¤ãè¿ã
+    };
+
+    /* ATTR, VAR, struct member Information */
+    signature sVarDeclInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1] = NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        void       getLocationInfo(  [out]uint32_t *offset,
+                                     [out]int8_t   *place );            // VARDECL_PLACE_*
+        void       getTypeInfo( [out]Descriptor( sTypeInfo ) *desc );
+        void       getSizeIsExpr( [out,string(max_len)]char_t *expr_str, [in]int32_t max_len );
+          // size_is è¨ç®å¼ãæå­åã§è¿ã. size_is æªæå®ã®å ´å *expr_str = NULL ãè¿ããã
+        ER         getSizeIs( [out]uint32_t *size, [in]const void *p_cb);
+          // p_cb ãä¸ããã¨ãsize ãè¿ã (size_is æå®ããªãå ´åï¼E_NOSPT ãè¿ã)
+    };
+
+    /* PARAM Information */
+    signature sParamInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1] = NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        ER         getTypeInfo( [out]Descriptor(sTypeInfo) *desc);
+        ER         getDir( [out]int8_t *dir );
+    };
+
+    /* FUNCTION Information */
+    signature sFunctionInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1] = NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        void       getReturnTypeInfo( [out]Descriptor( sTypeInfo ) *desc );
+        uint32_t   getNParam(void);
+        ER         getParamInfo( [in]uint32_t ith, [out]Descriptor(sParamInfo) *param );
+           // 0 <= ith < *num
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+    };
+
+    /* SIGNATURE Information */
+    signature sSignatureInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1] = NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        uint32_t   getNFunction(void);
+        ER         getFunctionInfo( [in]uint32_t ith, [out]Descriptor( sFunctionInfo ) *desc );
+           // 0 <= ith < *num
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+    };
+
+    /* CALL Information */
+    signature sCallInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1]= NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        void       getSignatureInfo( [out]Descriptor( sSignatureInfo ) *desc );
+        uint32_t   getArraySize(void);
+        void       getSpecifierInfo( [out]bool_t   *b_optional,
+                                     [out]bool_t   *b_dynamic,
+                                     [out]bool_t   *b_ref_desc,
+                                     [out]bool_t   *b_omit );
+        void       getInternalInfo(  [out]bool_t   *b_allocator_port,
+                                     [out]bool_t   *b_require_port );
+        void       getLocationInfo(  [out]uint32_t *offset,             // CALL_PLACE_*
+                                     [out]int8_t   *place );            // CALL_PLACE_*
+        void       getOptimizeInfo(  [out]bool_t   *b_VMT_useless,      // VMT (é¢æ°ãã¼ãã«) ä¸è¦æé©å (é¢æ°ç´æ¥å¼åºã)
+                                     [out]bool_t   *b_skelton_useless,  // ã¹ã±ã«ãã³é¢æ°ä¸è¦ (
+                                     [out]bool_t   *b_cell_unique );    // åä¸ã®ã»ã«
+    };
+
+    /* ENTRY Information */
+    signature sEntryInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1]=NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        void       getSignatureInfo( [out]Descriptor( sSignatureInfo ) *desc );
+        uint32_t   getArraySize(void);
+        bool_t     isInline(void);
+    };
+
+    /* CELLTYPE Information */
+    signature sCelltypeInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1]=NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        uint32_t   getNAttr(void);
+        ER         getAttrInfo( [in]uint32_t ith, [out]Descriptor(sVarDeclInfo)*desc );
+        uint32_t   getNVar(void);
+        ER         getVarInfo( [in]uint32_t ith,  [out]Descriptor(sVarDeclInfo)*desc );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+        uint32_t   getNCall(void);
+        ER         getCallInfo( [in]uint32_t ith, [out]Descriptor(sCallInfo)*desc );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+        uint32_t   getNEntry(void);
+        ER         getEntryInfo( [in]uint32_t ith, [out]Descriptor(sEntryInfo)*desc );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+        bool_t     isSingleton(void);
+        bool_t     isIDX_is_ID(void);
+        uint32_t   sizeOfCB(void);
+        uint32_t   sizeOfINIB(void);
+    };
+
+    /* CELL Information */
+    [deviate]
+    signature sCellInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1]=NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        uint32_t   getNRawEntryDescriptorInfo( void );
+        ER         getRawEntryDescriptorInfo( [in]int_t index, [out]Descriptor(sRawEntryDescriptorInfo) *desc );
+           // index ã¯ãåãå£ãæå® (CelltypeInfo ã® cEntryInfo ã®åºæ°ã«ä¸è´ãã)
+        void       getCelltypeInfo( [out]Descriptor( sCelltypeInfo ) *desc );
+        void       getCBP( [out]void **cbp );      // out: é¸è±
+        void       getINIBP( [out]void **inibp );  // out: é¸è±
+    };
+
+    [deviate]
+    signature sRawEntryDescriptorInfo {
+        uint16_t   getNRawEntryDescriptorInfo( void );         // åãå£é
+åã®å ´åãè¦ç´ æ°ãè¿ããéé
+åã®å ´å 1ã
+        ER         getRawDescriptor( [in]int_t ith, [out]void **rawDesc );
+                        // ith ãé
+åç¯å²å¤ã®å ´åãE_NOEXS ãè¿ã
+    };
+
+    /* NAMESPACE Information */
+    signature sNamespaceInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1]=NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        uint32_t   getNNamespace(void);
+        ER         getNamespaceInfo( [in]uint32_t ith, [out]Descriptor(sNamespaceInfo) *des );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+        uint32_t   getNSignature(void);
+        ER         getSignatureInfo( [in]uint32_t ith, [out]Descriptor(sSignatureInfo) *des );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+        uint32_t   getNCelltype(void);
+        ER     getCelltypeInfo( [in]uint32_t ith,  [out]Descriptor(sCelltypeInfo) *des );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+    };
+
+    /* REGION Information */
+    signature sRegionInfo {
+        ER         getName( [out,string(max_len)]char_t *name, [in]int_t max_len );
+           // é·ãã max_len ãè¶
+ããå ´åã¯ E_NOMEM ãè¿ã.
+           // (max_len-1) æå­ã³ãã¼ãããname[max_len-1]=NULL
+        uint16_t   getNameLength(void);
+           //  çµç«¯æå­ (NULL) ãå«ãé·ã (strlen ã¨ä»æ§ãç°ãªããã¨ã«æ³¨æ)
+        uint32_t   getNCell(void);
+        ER         getCellInfo( [in]uint32_t ith,    [out]Descriptor(sCellInfo) *des );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+        uint32_t   getNRegion(void);
+        ER         getRegionInfo( [in]uint32_t ith,  [out]Descriptor(sRegionInfo) *des );
+           // ith ãç¯å²å¤ã®å ´å E_NORES ãè¿ã
+    };
+
+    /* TECS Information */
+    signature sTECSInfo {
+        ER     findNamespace([in,string]const char_t *namespace_path, [out]Descriptor( sNamespaceInfo )*nsDesc);
+        ER     findRegion(   [in,string]const char_t *namespace_path, [out]Descriptor( sRegionInfo )*regionDesc);
+        ER     findSignature([in,string]const char_t *namespace_path, [out]Descriptor( sSignatureInfo )*signatureDesc);
+        ER     findCelltype( [in,string]const char_t *namespace_path, [out]Descriptor( sCelltypeInfo )*celltypeDesc);
+        ER     findCell(     [in,string]const char_t *namespace_path, [out]Descriptor( sCellInfo )*cellDesc);
+        ER     findRawEntryDescriptor(
+                             [in,string]const char_t *namespace_path,
+                             [in]             int_t  ith,
+                             [out]Descriptor( sRawEntryDescriptorInfo )*rawEntryDescDesc,
+                             [out]Descriptor( sEntryInfo )*entryDesc);
+        ER     findRawEntryDescriptor_unsafe(           // ãã®ã¡ã½ããã¯ãéé
+åã®å ´åã®ã¿ãããã§ãã
+                             [in,string]const char_t *namespace_path,
+                             [out]void **rawDesc );
+    };
+
+    /*******   CELLTYPES   *******/
+
+    /*
+     * tTECSInfo ã»ã«ã¿ã¤ãã®ã»ã«ã¯ãã¦ã¼ã¶ã¼ãè¨­ç½®ããï¼
+     *
+     * ãã®ã»ã«ãããtTECSInfoSub ã¸ã®çµåã¯ããã©ã°ã¤ã³ã«ããèªåçã«
+     * è¡ããããããã¦ã¼ã¶ã¼ã¯ããã®ã»ã«ãè¨­ç½®ããã ãã§ããï¼
+     * (ãã­ãã¿ã¤ããç¨ãã¦ããªãã®ã¯ããã®ã»ã«ãä»»æã®ãªã¼ã¸ã§ã³ã«ç½®
+     * ããã¨ãæ³å®ãã¦ã®ãã®)
+     */
+    [singleton,
+     generate( TECSInfoPlugin, "" )]
+    celltype tTECSInfo {
+        [inline]
+            entry sTECSInfo eTECSInfo;
+        call  sTECSInfo cTECSInfo;
+        FACTORY{
+            write( "global_tecsgen.h", "#define setRawEntryDescriptor( callDesc, callPortSignature, rawEntryDesc )   (callDesc).vdes = (struct tag_ ## callPortSignature ## _VDES *) rawEntryDesc" );
+        };
+    };
+
+    /*
+     * tTECSInfoSub ã»ã«ã¿ã¤ãã®ã»ã«ã¯ããã©ã°ã¤ã³ã«ããèªåçæãããï¼
+     * ãã©ã°ã¤ã³ã¯ãçæãè¡ãåã«ã¨ã©ã¼ãçºçãã¦ããå ´åãã»ã«ãçæããªãï¼
+     * (TECSInfoSub ã»ã«ãæªå®ç¾©ã®ã¨ã©ã¼ãåºããã¨ã«ãªããä¸å®å
+¨ãªç¶æ
+
+     * ã§çæãããã¨ããã¨ãRuby ä¾å¤ãçºçããå¯è½æ§ããããããçæ
+     * ããªã)
+     */
+    [singleton]
+    celltype tTECSInfoSub {
+        entry sTECSInfo eTECSInfo;
+        [ref_desc]
+            call sNamespaceInfo cNamespaceInfo;   // root namespace
+        [ref_desc]
+            call sRegionInfo    cRegionInfo;      // root region
+        // å
+é¨å¦çç¨ã®å¼ã³å£ (ä½åº¦ãä½¿ãã¾ããã®ã§ãä½¿ãç´åã«(å)è¨­å®ãããã¨ï¼
+        [dynamic,optional]
+            call sNamespaceInfo cNamespaceInfoTemp;
+        [dynamic,optional]
+            call sRegionInfo    cRegionInfoTemp;
+        [dynamic,optional]
+            call sSignatureInfo cSignatureInfoTemp;
+        [dynamic,optional]
+            call sCelltypeInfo  cCelltypeInfoTemp;
+        [dynamic,optional]
+            call sCellInfo      cCellInfoTemp;
+        [dynamic,optional]
+            call sEntryInfo     cEntryInfoTemp;
+        [dynamic,optional]
+            call sRawEntryDescriptorInfo cRawEntryDescriptorInfoTemp;
+
+        attr {
+            int32_t name_len = 256;
+            int32_t path_len = 1024;
+        };
+        var {
+            [size_is(name_len)]
+                char_t  *name1;
+            [size_is(name_len)]
+                char_t  *name2;
+            [size_is(path_len)]
+                char_t  *path;
+        };
+    };
+
+    celltype tNamespaceInfo {
+        attr {
+            char *name;
+        };
+
+        entry sNamespaceInfo eNamespaceInfo;
+        [ref_desc,optional]
+            call  sSignatureInfo cSignatureInfo[];
+        [ref_desc,optional]
+            call  sCelltypeInfo  cCelltypeInfo[];
+        [ref_desc,optional]
+            call  sNamespaceInfo cNamespaceInfo[];
+    };
+
+    /* SIGNATURE information */
+    celltype tSignatureInfo{
+        attr {
+            char *name;
+        };
+
+        entry sSignatureInfo   eSignatureInfo;
+        [ref_desc,optional]
+            call sFunctionInfo cFunctionInfo[];
+    };
+    celltype tFunctionInfo {
+        attr {
+            char_t *name;
+            bool_t  bOneway;
+        };
+        entry sFunctionInfo eFunctionInfo;
+        [ref_desc,optional]
+            call sParamInfo cParamInfo[];
+        [ref_desc]
+            call sTypeInfo  cReturnTypeInfo;
+    };
+    celltype tParamInfo {
+        attr {
+            char_t *name;
+            int8_t dir;
+            char_t *sizeIsExpr;
+            char_t *countIsExpr;
+            char_t *stringExpr;
+        };
+        entry sParamInfo eParamInfo;
+        [ref_desc]
+            call sTypeInfo cTypeInfo;
+    };
+
+    /* CELLTYPE information */
+    celltype tCelltypeInfo{
+        attr {
+            char_t   *name;
+            bool_t   b_singleton;
+            bool_t   b_IDX_is_ID_act;
+            uint32_t sizeOfCB;         // size in bytes, 0 if not exist
+            uint32_t sizeOfINIB;       // size in bytes, 0 if not exist
+            uint32_t n_cellInLinkUnit; // CellInLinkUnit == 0 ã®æ ã»ã«ã¿ã¤ãã³ã¼ãã¯ããªã³ã¯ããã¦ããªã
+            uint32_t n_cellInSystem;   // ãã¹ã¦ã®ãªã³ã¯ã¦ããããå«ããã»ã«ã®åæ°ï¼
+                                       // ãã®æ°ã 0ã«ãªããã®ã¯ãCelltypeInfo ã¯çç¥ãããï¼
+        };
+        [ref_desc,optional]
+            call  sEntryInfo   cEntryInfo[];
+        [ref_desc,optional]
+            call  sCallInfo    cCallInfo[];
+        [ref_desc,optional]
+            call  sVarDeclInfo cAttrInfo[];
+        [ref_desc,optional]
+            call  sVarDeclInfo cVarInfo[];
+
+        entry sCelltypeInfo    eCelltypeInfo;
+    };
+    celltype tCallInfo {
+        attr {
+            char_t   *name;
+            uint32_t offset;
+            uint32_t array_size;
+            bool_t   b_optional;
+            bool_t   b_omit;
+            bool_t   b_dynamic;
+            bool_t   b_ref_desc;
+            bool_t   b_allocator_port;
+            bool_t   b_require_port;
+            int8_t   place;
+            bool_t   b_VMT_useless;        // VMT (é¢æ°ãã¼ãã«) ä¸è¦æé©å (é¢æ°ç´æ¥å¼åºã)
+            bool_t   b_skelton_useless;    // ã¹ã±ã«ãã³é¢æ°ä¸è¦ (
+            bool_t   b_cell_unique;        // åä¸ã®ã»ã«
+        };
+        entry sCallInfo eCallInfo;
+        [ref_desc]
+            call sSignatureInfo cSignatureInfo;
+        FACTORY {
+            write( "$ct_global$_factory.h", "#include \"include_all_signature_header.h\"" );
+        };
+    };
+    celltype tEntryInfo {
+        attr {
+            char_t *name;
+            bool_t b_inline;
+            uint32_t array_size;
+        };
+        entry sEntryInfo eEntryInfo;
+        [ref_desc]
+            call sSignatureInfo cSignatureInfo;
+        FACTORY {
+            write( "$ct_global$_factory.h", "#include \"include_all_signature_header.h\"" );
+        };
+    };
+    /* Variable Declarator (attr, var, struct member) */
+    celltype tVarDeclInfo {
+        attr {
+            char_t   *name;
+            char_t   *sizeIsExpr;
+            int8_t   declType;        /* valid when attr, var */
+            int8_t   place;
+            uint32_t offset;
+        };
+        entry sVarDeclInfo eVarDeclInfo;
+        [ref_desc]
+            call sTypeInfo cTypeInfo;
+    };
+
+    /* REGION & CELL information */
+    celltype tRegionInfo {
+        attr {
+            char *name;
+        };
+
+        entry sRegionInfo eRegionInfo;
+        [ref_desc,optional]
+            call  sCellInfo   cCellInfo[];
+        [ref_desc,optional]
+            call  sRegionInfo cRegionInfo[];
+    };
+    celltype tCellInfo {
+        attr {
+            char_t *name;
+            void   *cbp;
+            void   *inibp;
+        };
+        [ref_desc]
+            call  sCelltypeInfo cCelltypeInfo;
+        [ref_desc,optional]
+            call  sRawEntryDescriptorInfo cRawEntryDescriptor[];
+        entry sCellInfo eCellInfo;
+    };
+    celltype tRawEntryDescriptorInfo {
+        attr {
+            int_t size;   // éé
+åã®å ´å 0
+            [size_is(size)]
+                void  **rawEntryDescriptor;
+        };
+        entry sRawEntryDescriptorInfo eRawEntryDescriptor;
+        // [ref_desc]
+        //    call  sEntryInfo             cEntryInfo;
+    };
+
+    /* celltypes of TYPEs */
+    celltype tVoidTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+    };
+    celltype tBoolTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+    };
+    celltype tIntTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+    };
+    celltype tFloatTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+    };
+    celltype tStructTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+        [ref_desc]
+            call sVarDeclInfo cVarDeclInfo[];
+    };
+    celltype tPtrTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+        [ref_desc]
+            call sTypeInfo cTypeInfo;
+        FACTORY {
+            write( "$ct_global$_factory.h", "#include \"include_all_signature_header.h\"" );
+        };
+    };
+    celltype tArrayTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+        [ref_desc]
+            call sTypeInfo cTypeInfo;
+        FACTORY {
+            write( "$ct_global$_factory.h", "#include \"include_all_signature_header.h\"" );
+        };
+    };
+    celltype tDefinedTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+        [ref_desc]
+            call sTypeInfo cTypeInfo;
+    };
+    celltype tDescriptorTypeInfo {
+        attr {
+            char_t   *name;
+            int8_t   typeKind;
+            uint32_t size;     /* bytes */
+            bool_t   b_const;
+            bool_t   b_volatile;
+        };
+        entry sTypeInfo eTypeInfo;
+        [ref_desc]
+            call sSignatureInfo cSignatureInfo;
+        FACTORY {
+            write( "$ct_global$_factory.h", "#include \"include_all_signature_header.h\"" );
+        };
+    };
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/TECSInfoAccessor.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/TECSInfoAccessor.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/TECSInfoAccessor.cdl	(revision 374)
@@ -0,0 +1,179 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+// mruby ããã¢ã¯ã»ã¹ã§ãããããªã·ã°ããã£ã«ãããã¢ã¯ã»ã¹ç¨ã»ã«ã¿ã¤ãã®å®ç¾©
+// ã¤ã¾ããã·ã°ããã£ãã Descriptor åããªãããååãæå®ãã¦åççµåãããã»ã«ã¿ã¤ããç¨æãã
+
+import( <TECSInfo.cdl> );
+
+//namespace nTECSInfo {
+    signature sAccessor{
+        ER   selectNamespaceInfoByName( [in,string]const char_t *namespacePath );
+        ER   selectCelltypeInfoByName(  [in,string]const char_t *namespacePath );
+        ER   selectSignatureInfoByName( [in,string]const char_t *namespacePath );
+        ER   selectRegionInfoByName(    [in,string]const char_t *regionPath );
+        ER   selectCellInfoByName(      [in,string]const char_t *cellPath );
+
+        // namespace
+        ER   getSelectedNamespaceInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int_t *num_namespace, [out]int_t *num_celltype, [out]int_t *num_signature );
+        ER   selectCelltypeInfo( [in]int_t ith );
+        ER   selectSignatureInfo( [in]int_t ith );
+
+        // celltype
+        ER   getSelectedCelltypeInfo( [out,string(max_len)]char_t *name, [in]int_t max_len,
+                                      [out]int_t *num_attr, [out]int_t *num_var, [out]int_t *num_call, [out]int_t *num_entry );
+        ER   selectCallInfo( [in]int_t ith );
+        ER   selectEntryInfo( [in]int_t ith );
+        ER   selectAttrInfo( [in]int_t ith );
+        ER   selectVarInfo( [in]int_t ith );
+
+        // attr
+        ER   getSelectedAttrInfo( [out,string(max_len)]char_t *name, [in]int_t max_len );
+        ER   getSizeIsExprOfAttr( [out,string(max_len)]char_t *expr_str, [in]int32_t max_len );
+        ER   selectTypeInfoOfAttr(void);
+
+        // var
+        ER   getSelectedVarInfo( [out,string(max_len)]char_t *name, [in]int_t max_len );
+        ER   getSizeIsExprOfVar( [out,string(max_len)]char_t *expr_str, [in]int32_t max_len );
+        ER   selectTypeInfoOfVar(void);
+
+        // call
+        ER   getSelectedCallInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int_t *array_size );
+        ER   selectSignatureOfCall(void);
+        ER   getSelectedCallSpecifierInfo( [out]bool_t   *b_optional,  [out]bool_t   *b_dynamic,
+                                           [out]bool_t   *b_ref_desc,  [out]bool_t   *b_omit );
+        ER   getSelectedCallInternalInfo(  [out]bool_t   *b_allocator_port, [out]bool_t   *b_require_port );
+        ER   getSelectedCallLocationInfo(  [out]uint32_t *offset,             // offset in CALL_PLACE_*
+                                           [out]int8_t   *place );            // CALL_PLACE_*
+        ER   getSelectedCallOptimizeInfo(  [out]bool_t   *b_VMT_useless,      // VMT (é¢æ°ãã¼ãã«) ä¸è¦æé©å (é¢æ°ç´æ¥å¼åºã)
+                                           [out]bool_t   *b_skelton_useless,  // ã¹ã±ã«ãã³é¢æ°ä¸è¦ (
+                                           [out]bool_t   *b_cell_unique );    // åä¸ã®ã»ã«
+
+        // entry
+        ER   getSelectedEntryInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int_t *array_size );
+        ER   selectSignatureOfEntry(void);
+        ER   getSelectedEntryInlineInfo([out]bool_t *b_inline);
+
+        // signature
+        ER   getSelectedSignatureInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int_t *num_function );
+        ER   selectFunctionInfoByIndex( [in]int_t ith );
+
+        // function
+        ER   getSelectedFunctionInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int_t *num_args );
+        ER   selectTypeInfoOfReturn(void);
+
+        // parameter of function
+        ER   getSelectedParamInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int8_t *dir );
+        ER   selectParamInfo( [in]int_t ith );
+        ER   selectTypeInfoOfParam(void);
+
+        // type of function return and parameter, celltype attr and var
+        ER   getSelectedTypeInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int8_t *kind );
+        ER   selectTypeInfoOfType(void);
+
+        // region
+        ER   getSelectedRegionInfo( [out,string(max_len)]char_t *name, [in]int_t max_len, [out]int_t *num_cell );
+        ER   selectCellInfo( [in]int_t ith );
+
+        // cell
+        ER   getSelectedCellInfo( [out,string(max_len)]char_t *name, [in]int_t max_len);
+        ER   selectCelltypeInfoOfCell(void); // é¸æä¸­ã»ã«ã®ã»ã«ã¿ã¤ããé¸æ (ã»ã«ã¿ã¤ãã®é¢æ°ãä½¿ç¨ã§ãã)
+        ER   getAttrValueInStr([out,string(max_len)]char_t *buf, [in]int_t max_len);  // äºåã«ãã»ã«ãã»ã«ã¿ã¤ããå±æ§ãé¸æãã¦ãããã¨ï¼cTypeInfo ãå¤æ´ããã
+        ER   getAttrSizeIsValue(void);       // äºåã«ãã»ã«ãã»ã«ã¿ã¤ããå±æ§ãé¸æãã¦ãããã¨ï¼cTypeInfo ãå¤æ´ããã
+        ER   getVarValueInStr([out,string(max_len)]char_t *buf, [in]int_t max_len);   // äºåã«ãã»ã«ãã»ã«ã¿ã¤ããå¤æ°ãé¸æãã¦ãããã¨ï¼cTypeInfo ãå¤æ´ããã
+        ER   getVarSizeIsValue(void);        // äºåã«ãã»ã«ãã»ã«ã¿ã¤ããå¤æ°ãé¸æãã¦ãããã¨ï¼cTypeInfo ãå¤æ´ããã
+    };
+
+    celltype tTECSInfoAccessor {
+
+        entry sAccessor eSelector;
+
+        call  nTECSInfo::sTECSInfo cTECSInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sNamespaceInfo cNSInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sCelltypeInfo  cCelltypeInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sSignatureInfo cSignatureInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sFunctionInfo  cFunctionInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sParamInfo     cParamInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sCallInfo      cCallInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sEntryInfo     cEntryInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sVarDeclInfo   cAttrInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sVarDeclInfo   cVarInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sTypeInfo      cTypeInfo;
+
+        [dynamic,optional]
+            call  nTECSInfo::sRegionInfo    cRegionInfo;
+        [dynamic,optional]
+            call  nTECSInfo::sCellInfo      cCellInfo;
+
+        attr{
+            int16_t NAME_LEN = 256;
+        };
+        var{
+            [size_is(NAME_LEN)]
+                char_t  *name;
+            [size_is(NAME_LEN)]
+                char_t  *name2;
+            int8_t      *selectedCbp;
+            int8_t      *selectedInibp;
+        };
+    };
+//};
+
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tArrayTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tArrayTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tArrayTypeInfo.c	(revision 374)
@@ -0,0 +1,269 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cTypeInfo_getNameLength( );
+ *   uint32_t       cTypeInfo_getSize( );
+ *   int8_t         cTypeInfo_getKind( );
+ *   uint32_t       cTypeInfo_getNType( );
+ *   ER             cTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cTypeInfo_getNMember( );
+ *   ER             cTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tArrayTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return TECSTypeKind_ArrayType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return ATTR_size / cTypeInfo_getSize();  /* é
+åè¦ç´ æ° = ãµã¤ãº / è¦ç´ ãµã¤ãº */
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+  ER      ercd = E_OK;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *desc = cTypeInfo_refer_to_descriptor();
+  return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tArrayTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tBoolTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tBoolTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tBoolTypeInfo.c	(revision 374)
@@ -0,0 +1,252 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tBoolTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return TECSTypeKind_ArrayType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return 0;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return E_NOEXS;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tBoolTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCallInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCallInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCallInfo.c	(revision 374)
@@ -0,0 +1,275 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * offset           uint32_t         ATTR_offset     
+ * array_size       uint32_t         ATTR_array_size 
+ * b_optional       bool_t           ATTR_b_optional 
+ * b_omit           bool_t           ATTR_b_omit     
+ * b_dynamic        bool_t           ATTR_b_dynamic  
+ * b_ref_desc       bool_t           ATTR_b_ref_desc 
+ * b_allocator_port bool_t           ATTR_b_allocator_port
+ * b_require_port   bool_t           ATTR_b_require_port
+ * place            int8_t           ATTR_place      
+ * b_VMT_useless    bool_t           ATTR_b_VMT_useless
+ * b_skelton_useless bool_t           ATTR_b_skelton_useless
+ * b_cell_unique    bool_t           ATTR_b_cell_unique
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cSignatureInfo signature: nTECSInfo_sSignatureInfo context:task
+ *   ER             cSignatureInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cSignatureInfo_getNameLength( );
+ *   uint32_t       cSignatureInfo_getNFunction( );
+ *   ER             cSignatureInfo_getFunctionInfo( uint32_t ith, Descriptor( nTECSInfo_sFunctionInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tCallInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eCallInfo
+ * entry port: eCallInfo
+ * signature:  nTECSInfo_sCallInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getName
+ * name:         eCallInfo_getName
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCallInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getNameLength
+ * name:         eCallInfo_getNameLength
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eCallInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getSignatureInfo
+ * name:         eCallInfo_getSignatureInfo
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getSignatureInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCallInfo_getSignatureInfo(CELLIDX idx, Descriptor( nTECSInfo_sSignatureInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *desc = cSignatureInfo_refer_to_descriptor();
+}
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getArraySize
+ * name:         eCallInfo_getArraySize
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getArraySize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCallInfo_getArraySize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return ATTR_array_size;
+}
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getSpecifierInfo
+ * name:         eCallInfo_getSpecifierInfo
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getSpecifierInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCallInfo_getSpecifierInfo(CELLIDX idx, bool_t* b_optional, bool_t* b_dynamic, bool_t* b_ref_desc, bool_t* b_omit)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *b_optional = ATTR_b_optional;
+  *b_dynamic  = ATTR_b_dynamic;
+  *b_ref_desc = ATTR_b_ref_desc;
+  *b_omit     = ATTR_b_omit;
+}
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getInternalInfo
+ * name:         eCallInfo_getInternalInfo
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getInternalInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCallInfo_getInternalInfo(CELLIDX idx, bool_t* b_allocator_port, bool_t* b_require_port)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *b_allocator_port = ATTR_b_allocator_port;
+  *b_require_port   = ATTR_b_require_port;
+}
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getLocationInfo
+ * name:         eCallInfo_getLocationInfo
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getLocationInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCallInfo_getLocationInfo(CELLIDX idx, uint32_t* offset, int8_t* place)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *offset = ATTR_offset;
+  *place  = ATTR_place;
+}
+
+/* #[<ENTRY_FUNC>]# eCallInfo_getOptimizeInfo
+ * name:         eCallInfo_getOptimizeInfo
+ * global_name:  nTECSInfo_tCallInfo_eCallInfo_getOptimizeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCallInfo_getOptimizeInfo(CELLIDX idx, bool_t* b_VMT_useless, bool_t* b_skelton_useless, bool_t* b_cell_unique)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *b_VMT_useless     = ATTR_b_VMT_useless;
+  *b_skelton_useless = ATTR_b_skelton_useless;
+  *b_cell_unique     = ATTR_b_cell_unique;
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCellInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCellInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCellInfo.c	(revision 374)
@@ -0,0 +1,266 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * cbp              void*            ATTR_cbp        
+ * inibp            void*            ATTR_inibp      
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cCelltypeInfo signature: nTECSInfo_sCelltypeInfo context:task
+ *   ER             cCelltypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCelltypeInfo_getNameLength( );
+ *   uint32_t       cCelltypeInfo_getNAttr( );
+ *   ER             cCelltypeInfo_getAttrInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNVar( );
+ *   ER             cCelltypeInfo_getVarInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNCall( );
+ *   ER             cCelltypeInfo_getCallInfo( uint32_t ith, Descriptor( nTECSInfo_sCallInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNEntry( );
+ *   ER             cCelltypeInfo_getEntryInfo( uint32_t ith, Descriptor( nTECSInfo_sEntryInfo )* desc );
+ *   bool_t         cCelltypeInfo_isSingleton( );
+ *   bool_t         cCelltypeInfo_isIDX_is_ID( );
+ *   uint32_t       cCelltypeInfo_sizeOfCB( );
+ *   uint32_t       cCelltypeInfo_sizeOfINIB( );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sCelltypeInfo ) cCelltypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sCelltypeInfo ) cCelltypeInfo_ref_desc()      (same as above; abbreviated version);
+ * call port: cRawEntryDescriptor signature: nTECSInfo_sRawEntryDescriptorInfo context:task optional:true
+ *   bool_t     is_cRawEntryDescriptor_joined(int subscript)        check if joined
+ *   uint16_t       cRawEntryDescriptor_getNRawEntryDescriptorInfo( subscript );
+ *   ER             cRawEntryDescriptor_getRawDescriptor( subscript, const char_t* signatureName, int_t ith, void** rawDesc );
+ *       subscript:  0...(NCP_cRawEntryDescriptor-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sRawEntryDescriptorInfo ) cRawEntryDescriptor_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sRawEntryDescriptorInfo ) cRawEntryDescriptor_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tCellInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eCellInfo
+ * entry port: eCellInfo
+ * signature:  nTECSInfo_sCellInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eCellInfo_getName
+ * name:         eCellInfo_getName
+ * global_name:  nTECSInfo_tCellInfo_eCellInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCellInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eCellInfo_getNameLength
+ * name:         eCellInfo_getNameLength
+ * global_name:  nTECSInfo_tCellInfo_eCellInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eCellInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eCellInfo_getNRawEntryDescriptorInfo
+ * name:         eCellInfo_getNRawEntryDescriptorInfo
+ * global_name:  nTECSInfo_tCellInfo_eCellInfo_getNRawEntryDescriptorInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCellInfo_getNRawEntryDescriptorInfo(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return NCP_cRawEntryDescriptor;
+}
+
+/* #[<ENTRY_FUNC>]# eCellInfo_getRawEntryDescriptorInfo
+ * name:         eCellInfo_getRawEntryDescriptorInfo
+ * global_name:  nTECSInfo_tCellInfo_eCellInfo_getRawEntryDescriptorInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCellInfo_getRawEntryDescriptorInfo(CELLIDX idx, int_t index, Descriptor( nTECSInfo_sRawEntryDescriptorInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+  ER      ercd = E_OK;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( 0 <= index && index < NCP_cRawEntryDescriptor ){
+      if( is_cRawEntryDescriptor_joined( index ) )
+          *desc = cRawEntryDescriptor_refer_to_descriptor( index );
+      else
+          ercd = E_NOEXS;
+  }
+  else
+      ercd = E_ID;
+
+  return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eCellInfo_getCelltypeInfo
+ * name:         eCellInfo_getCelltypeInfo
+ * global_name:  nTECSInfo_tCellInfo_eCellInfo_getCelltypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCellInfo_getCelltypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sCelltypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *desc = cCelltypeInfo_refer_to_descriptor();
+}
+
+/* #[<ENTRY_FUNC>]# eCellInfo_getCBP
+ * name:         eCellInfo_getCBP
+ * global_name:  nTECSInfo_tCellInfo_eCellInfo_getCBP
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCellInfo_getCBP(CELLIDX idx, void** cbp)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *cbp = ATTR_cbp;
+}
+
+/* #[<ENTRY_FUNC>]# eCellInfo_getINIBP
+ * name:         eCellInfo_getINIBP
+ * global_name:  nTECSInfo_tCellInfo_eCellInfo_getINIBP
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eCellInfo_getINIBP(CELLIDX idx, void** inibp)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *inibp = ATTR_inibp;
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCelltypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCelltypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tCelltypeInfo.c	(revision 374)
@@ -0,0 +1,461 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * b_singleton      bool_t           ATTR_b_singleton
+ * b_IDX_is_ID_act  bool_t           ATTR_b_IDX_is_ID_act
+ * sizeOfCB         uint32_t         ATTR_sizeOfCB   
+ * sizeOfINIB       uint32_t         ATTR_sizeOfINIB 
+ * n_cellInLinkUnit uint32_t         ATTR_n_cellInLinkUnit
+ * n_cellInSystem   uint32_t         ATTR_n_cellInSystem
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cEntryInfo signature: nTECSInfo_sEntryInfo context:task optional:true
+ *   bool_t     is_cEntryInfo_joined(int subscript)        check if joined
+ *   ER             cEntryInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cEntryInfo_getNameLength( subscript );
+ *   void           cEntryInfo_getSignatureInfo( subscript, Descriptor( nTECSInfo_sSignatureInfo )* desc );
+ *   uint32_t       cEntryInfo_getArraySize( subscript );
+ *   bool_t         cEntryInfo_isInline( subscript );
+ *       subscript:  0...(NCP_cEntryInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sEntryInfo ) cEntryInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sEntryInfo ) cEntryInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ * call port: cCallInfo signature: nTECSInfo_sCallInfo context:task optional:true
+ *   bool_t     is_cCallInfo_joined(int subscript)        check if joined
+ *   ER             cCallInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cCallInfo_getNameLength( subscript );
+ *   void           cCallInfo_getSignatureInfo( subscript, Descriptor( nTECSInfo_sSignatureInfo )* desc );
+ *   uint32_t       cCallInfo_getArraySize( subscript );
+ *   void           cCallInfo_getSpecifierInfo( subscript, bool_t* b_optional, bool_t* b_dynamic, bool_t* b_ref_desc, bool_t* b_omit );
+ *   void           cCallInfo_getInternalInfo( subscript, bool_t* b_allocator_port, bool_t* b_require_port );
+ *   void           cCallInfo_getLocationInfo( subscript, uint32_t* offset, int8_t* place );
+ *   void           cCallInfo_getOptimizeInfo( subscript, bool_t* b_VMT_useless, bool_t* b_skelton_useless, bool_t* b_cell_unique );
+ *       subscript:  0...(NCP_cCallInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sCallInfo ) cCallInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sCallInfo ) cCallInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ * call port: cAttrInfo signature: nTECSInfo_sVarDeclInfo context:task optional:true
+ *   bool_t     is_cAttrInfo_joined(int subscript)        check if joined
+ *   ER             cAttrInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cAttrInfo_getNameLength( subscript );
+ *   uint32_t       cAttrInfo_getOffset( subscript );
+ *   void           cAttrInfo_getTypeInfo( subscript, Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   void           cAttrInfo_getSizeIsExpr( subscript, char_t* expr_str, int32_t max_len );
+ *   ER             cAttrInfo_getSizeIs( subscript, uint32_t* size, const void* p_cb );
+ *       subscript:  0...(NCP_cAttrInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sVarDeclInfo ) cAttrInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sVarDeclInfo ) cAttrInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ * call port: cVarInfo signature: nTECSInfo_sVarDeclInfo context:task optional:true
+ *   bool_t     is_cVarInfo_joined(int subscript)        check if joined
+ *   ER             cVarInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cVarInfo_getNameLength( subscript );
+ *   uint32_t       cVarInfo_getOffset( subscript );
+ *   void           cVarInfo_getTypeInfo( subscript, Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   void           cVarInfo_getSizeIsExpr( subscript, char_t* expr_str, int32_t max_len );
+ *   ER             cVarInfo_getSizeIs( subscript, uint32_t* size, const void* p_cb );
+ *       subscript:  0...(NCP_cVarInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sVarDeclInfo ) cVarInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sVarDeclInfo ) cVarInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tCelltypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eCelltypeInfo
+ * entry port: eCelltypeInfo
+ * signature:  nTECSInfo_sCelltypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getName
+ * name:         eCelltypeInfo_getName
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCelltypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+    ER		ercd = E_OK;
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        return(E_ID);
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    name[ max_len - 1 ] = '\0';
+    strncpy( name, ATTR_name, max_len );
+    if( name[ max_len - 1 ] ){
+        name[ max_len - 1 ] = '\0';
+        ercd = E_NOMEM;
+    }
+
+    return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getNameLength
+ * name:         eCelltypeInfo_getNameLength
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eCelltypeInfo_getNameLength(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getNAttr
+ * name:         eCelltypeInfo_getNAttr
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getNAttr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCelltypeInfo_getNAttr(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    return NCP_cAttrInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getAttrInfo
+ * name:         eCelltypeInfo_getAttrInfo
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getAttrInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCelltypeInfo_getAttrInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+    CELLCB	*p_cellcb;
+    ER      ercd = E_OK;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    if( 0 <= ith && ith < NCP_cAttrInfo ){
+        if( is_cAttrInfo_joined( ith ) )
+            *desc = cAttrInfo_refer_to_descriptor( ith );
+        else
+            ercd = E_NOEXS;
+    }
+    else
+        ercd = E_ID;
+    return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getNVar
+ * name:         eCelltypeInfo_getNVar
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getNVar
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCelltypeInfo_getNVar(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    return NCP_cVarInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getVarInfo
+ * name:         eCelltypeInfo_getVarInfo
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getVarInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCelltypeInfo_getVarInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+    CELLCB	*p_cellcb;
+    ER      ercd = E_OK;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    if( 0 <= ith &&  ith < NCP_cVarInfo ){
+        if( is_cVarInfo_joined( ith ) )
+            *desc = cVarInfo_refer_to_descriptor( ith );
+        else
+            ercd = E_NOEXS;
+    }
+    else
+        ercd = E_ID;
+    return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getNCall
+ * name:         eCelltypeInfo_getNCall
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getNCall
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCelltypeInfo_getNCall(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    return NCP_cCallInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getCallInfo
+ * name:         eCelltypeInfo_getCallInfo
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getCallInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCelltypeInfo_getCallInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sCallInfo )* desc)
+{
+    CELLCB	*p_cellcb;
+    ER      ercd = E_OK;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    if( 0 <= ith && ith < NCP_cCallInfo ){
+        if( is_cCallInfo_joined( ith ) )
+            *desc = cCallInfo_refer_to_descriptor( ith );
+        else
+            ercd = E_NOEXS;
+    }
+    else
+        ercd = E_ID;
+
+    return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getNEntry
+ * name:         eCelltypeInfo_getNEntry
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getNEntry
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCelltypeInfo_getNEntry(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    return NCP_cEntryInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_getEntryInfo
+ * name:         eCelltypeInfo_getEntryInfo
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_getEntryInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eCelltypeInfo_getEntryInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sEntryInfo )* desc)
+{
+    CELLCB	*p_cellcb;
+    ER      ercd = E_OK;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    if( 0 <= ith && ith < NCP_cEntryInfo ){
+        if( is_cEntryInfo_joined( ith ) )
+            *desc = cEntryInfo_refer_to_descriptor( ith );
+        else
+            ercd = E_NOEXS;
+    }
+    else
+        ercd = E_ID;
+
+    return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_isSingleton
+ * name:         eCelltypeInfo_isSingleton
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_isSingleton
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+bool_t
+eCelltypeInfo_isSingleton(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    return ATTR_b_singleton;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_isIDX_is_ID
+ * name:         eCelltypeInfo_isIDX_is_ID
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_isIDX_is_ID
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+bool_t
+eCelltypeInfo_isIDX_is_ID(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* Write error processing code here */
+    } /* end if VALID_IDX(idx) */
+
+    /* Put statements here #_TEFB_# */
+    return ATTR_b_IDX_is_ID_act;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_sizeOfCB
+ * name:         eCelltypeInfo_sizeOfCB
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_sizeOfCB
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCelltypeInfo_sizeOfCB(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+    } /* end if VALID_IDX(idx) */
+
+    /* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+    return ATTR_sizeOfCB;
+}
+
+/* #[<ENTRY_FUNC>]# eCelltypeInfo_sizeOfINIB
+ * name:         eCelltypeInfo_sizeOfINIB
+ * global_name:  nTECSInfo_tCelltypeInfo_eCelltypeInfo_sizeOfINIB
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eCelltypeInfo_sizeOfINIB(CELLIDX idx)
+{
+    CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+        p_cellcb = GET_CELLCB(idx);
+    }
+    else {
+        /* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+    } /* end if VALID_IDX(idx) */
+
+    /* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+    return ATTR_sizeOfINIB;
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tDefinedTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tDefinedTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tDefinedTypeInfo.c	(revision 374)
@@ -0,0 +1,270 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cTypeInfo_getNameLength( );
+ *   uint32_t       cTypeInfo_getSize( );
+ *   int8_t         cTypeInfo_getKind( );
+ *   uint32_t       cTypeInfo_getNType( );
+ *   ER             cTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cTypeInfo_getNMember( );
+ *   ER             cTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tDefinedTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return cTypeInfo_getSize();
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return TECSTypeKind_DefinedType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  /*
+   * ith == 0 is valid, others are invalid.
+   * but this function always returns valid value
+   */
+  *desc = cTypeInfo_refer_to_descriptor();
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tDefinedTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tDescriptorTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tDescriptorTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tDescriptorTypeInfo.c	(revision 374)
@@ -0,0 +1,262 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cSignatureInfo signature: nTECSInfo_sSignatureInfo context:task
+ *   ER             cSignatureInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cSignatureInfo_getNameLength( );
+ *   uint32_t       cSignatureInfo_getNFunction( );
+ *   ER             cSignatureInfo_getFunctionInfo( uint32_t ith, Descriptor( nTECSInfo_sFunctionInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tDescriptorTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return TECSTypeKind_DescriptorType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return 0;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return E_NOEXS;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tDescriptorTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tEntryInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tEntryInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tEntryInfo.c	(revision 374)
@@ -0,0 +1,198 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * b_inline         bool_t           ATTR_b_inline   
+ * array_size       uint32_t         ATTR_array_size 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cSignatureInfo signature: nTECSInfo_sSignatureInfo context:task
+ *   ER             cSignatureInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cSignatureInfo_getNameLength( );
+ *   uint32_t       cSignatureInfo_getNFunction( );
+ *   ER             cSignatureInfo_getFunctionInfo( uint32_t ith, Descriptor( nTECSInfo_sFunctionInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tEntryInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eEntryInfo
+ * entry port: eEntryInfo
+ * signature:  nTECSInfo_sEntryInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eEntryInfo_getName
+ * name:         eEntryInfo_getName
+ * global_name:  nTECSInfo_tEntryInfo_eEntryInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eEntryInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eEntryInfo_getNameLength
+ * name:         eEntryInfo_getNameLength
+ * global_name:  nTECSInfo_tEntryInfo_eEntryInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eEntryInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eEntryInfo_getSignatureInfo
+ * name:         eEntryInfo_getSignatureInfo
+ * global_name:  nTECSInfo_tEntryInfo_eEntryInfo_getSignatureInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eEntryInfo_getSignatureInfo(CELLIDX idx, Descriptor( nTECSInfo_sSignatureInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *desc = cSignatureInfo_refer_to_descriptor();
+}
+
+/* #[<ENTRY_FUNC>]# eEntryInfo_getArraySize
+ * name:         eEntryInfo_getArraySize
+ * global_name:  nTECSInfo_tEntryInfo_eEntryInfo_getArraySize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eEntryInfo_getArraySize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return ATTR_array_size;
+}
+
+/* #[<ENTRY_FUNC>]# eEntryInfo_isInline
+ * name:         eEntryInfo_isInline
+ * global_name:  nTECSInfo_tEntryInfo_eEntryInfo_isInline
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+bool_t
+eEntryInfo_isInline(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return ATTR_b_inline;
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tFloatTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tFloatTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tFloatTypeInfo.c	(revision 374)
@@ -0,0 +1,252 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tFloatTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return TECSTypeKind_FloatType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return 0;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return E_NOEXS;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tFloatTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tFunctionInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tFunctionInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tFunctionInfo.c	(revision 374)
@@ -0,0 +1,215 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * bOneway          bool_t           ATTR_bOneway    
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cParamInfo signature: nTECSInfo_sParamInfo context:task optional:true
+ *   bool_t     is_cParamInfo_joined(int subscript)        check if joined
+ *   ER             cParamInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cParamInfo_getNameLength( subscript );
+ *   ER             cParamInfo_getTypeInfo( subscript, Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *       subscript:  0...(NCP_cParamInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sParamInfo ) cParamInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sParamInfo ) cParamInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ * call port: cReturnTypeInfo signature: nTECSInfo_sTypeInfo context:task
+ *   ER             cReturnTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cReturnTypeInfo_getNameLength( );
+ *   uint32_t       cReturnTypeInfo_getSize( );
+ *   int8_t         cReturnTypeInfo_getKind( );
+ *   uint32_t       cReturnTypeInfo_getNType( );
+ *   ER             cReturnTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cReturnTypeInfo_getNMember( );
+ *   ER             cReturnTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sTypeInfo ) cReturnTypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sTypeInfo ) cReturnTypeInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tFunctionInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eFunctionInfo
+ * entry port: eFunctionInfo
+ * signature:  nTECSInfo_sFunctionInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eFunctionInfo_getName
+ * name:         eFunctionInfo_getName
+ * global_name:  nTECSInfo_tFunctionInfo_eFunctionInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eFunctionInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eFunctionInfo_getNameLength
+ * name:         eFunctionInfo_getNameLength
+ * global_name:  nTECSInfo_tFunctionInfo_eFunctionInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eFunctionInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eFunctionInfo_getReturnTypeInfo
+ * name:         eFunctionInfo_getReturnTypeInfo
+ * global_name:  nTECSInfo_tFunctionInfo_eFunctionInfo_getReturnTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eFunctionInfo_getReturnTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *desc = cReturnTypeInfo_refer_to_descriptor();
+}
+
+/* #[<ENTRY_FUNC>]# eFunctionInfo_getNParam
+ * name:         eFunctionInfo_getNParam
+ * global_name:  nTECSInfo_tFunctionInfo_eFunctionInfo_getNParam
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eFunctionInfo_getNParam(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return NCP_cParamInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eFunctionInfo_getParamInfo
+ * name:         eFunctionInfo_getParamInfo
+ * global_name:  nTECSInfo_tFunctionInfo_eFunctionInfo_getParamInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eFunctionInfo_getParamInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sParamInfo )* param)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  if( ith >= NCP_cParamInfo )
+      ercd = E_NOEXS;
+  else
+      *param = cParamInfo_refer_to_descriptor( ith );
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tIntTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tIntTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tIntTypeInfo.c	(revision 374)
@@ -0,0 +1,252 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tIntTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return TECSTypeKind_IntType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return 0;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return E_NOEXS;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tIntTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tNamespaceInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tNamespaceInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tNamespaceInfo.c	(revision 374)
@@ -0,0 +1,292 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char*            ATTR_name       
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cSignatureInfo signature: nTECSInfo_sSignatureInfo context:task optional:true
+ *   bool_t     is_cSignatureInfo_joined(int subscript)        check if joined
+ *   ER             cSignatureInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cSignatureInfo_getNameLength( subscript );
+ *   uint32_t       cSignatureInfo_getNFunction( subscript );
+ *   ER             cSignatureInfo_getFunctionInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sFunctionInfo )* desc );
+ *       subscript:  0...(NCP_cSignatureInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sSignatureInfo ) cSignatureInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ * call port: cCelltypeInfo signature: nTECSInfo_sCelltypeInfo context:task optional:true
+ *   bool_t     is_cCelltypeInfo_joined(int subscript)        check if joined
+ *   ER             cCelltypeInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cCelltypeInfo_getNameLength( subscript );
+ *   uint32_t       cCelltypeInfo_getNAttr( subscript );
+ *   ER             cCelltypeInfo_getAttrInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNVar( subscript );
+ *   ER             cCelltypeInfo_getVarInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNCall( subscript );
+ *   ER             cCelltypeInfo_getCallInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sCallInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNEntry( subscript );
+ *   ER             cCelltypeInfo_getEntryInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sEntryInfo )* desc );
+ *   bool_t         cCelltypeInfo_isSingleton( subscript );
+ *   bool_t         cCelltypeInfo_isIDX_is_ID( subscript );
+ *   uint32_t       cCelltypeInfo_sizeOfCB( subscript );
+ *   uint32_t       cCelltypeInfo_sizeOfINIB( subscript );
+ *       subscript:  0...(NCP_cCelltypeInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sCelltypeInfo ) cCelltypeInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sCelltypeInfo ) cCelltypeInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ * call port: cNamespaceInfo signature: nTECSInfo_sNamespaceInfo context:task optional:true
+ *   bool_t     is_cNamespaceInfo_joined(int subscript)        check if joined
+ *   ER             cNamespaceInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cNamespaceInfo_getNameLength( subscript );
+ *   uint32_t       cNamespaceInfo_getNNamespace( subscript );
+ *   ER             cNamespaceInfo_getNamespaceInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sNamespaceInfo )* des );
+ *   uint32_t       cNamespaceInfo_getNSignature( subscript );
+ *   ER             cNamespaceInfo_getSignatureInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sSignatureInfo )* des );
+ *   uint32_t       cNamespaceInfo_getNCelltype( subscript );
+ *   ER             cNamespaceInfo_getCelltypeInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sCelltypeInfo )* des );
+ *       subscript:  0...(NCP_cNamespaceInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sNamespaceInfo ) cNamespaceInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sNamespaceInfo ) cNamespaceInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tNamespaceInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eNamespaceInfo
+ * entry port: eNamespaceInfo
+ * signature:  nTECSInfo_sNamespaceInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getName
+ * name:         eNamespaceInfo_getName
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eNamespaceInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getNameLength
+ * name:         eNamespaceInfo_getNameLength
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eNamespaceInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getNNamespace
+ * name:         eNamespaceInfo_getNNamespace
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getNNamespace
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eNamespaceInfo_getNNamespace(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return NCP_cNamespaceInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getNamespaceInfo
+ * name:         eNamespaceInfo_getNamespaceInfo
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getNamespaceInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eNamespaceInfo_getNamespaceInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sNamespaceInfo )* des)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *des = cNamespaceInfo_refer_to_descriptor( ith );
+}
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getNSignature
+ * name:         eNamespaceInfo_getNSignature
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getNSignature
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eNamespaceInfo_getNSignature(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return NCP_cSignatureInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getSignatureInfo
+ * name:         eNamespaceInfo_getSignatureInfo
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getSignatureInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eNamespaceInfo_getSignatureInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sSignatureInfo )* des)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	*des = cSignatureInfo_refer_to_descriptor( ith );
+}
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getNCelltype
+ * name:         eNamespaceInfo_getNCelltype
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getNCelltype
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eNamespaceInfo_getNCelltype(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return NCP_cCelltypeInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eNamespaceInfo_getCelltypeInfo
+ * name:         eNamespaceInfo_getCelltypeInfo
+ * global_name:  nTECSInfo_tNamespaceInfo_eNamespaceInfo_getCelltypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eNamespaceInfo_getCelltypeInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sCelltypeInfo )* des)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	*des = cCelltypeInfo_refer_to_descriptor( ith );
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tParamInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tParamInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tParamInfo.c	(revision 374)
@@ -0,0 +1,189 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * dir              int8_t           ATTR_dir        
+ * sizeIsExpr       char_t*          ATTR_sizeIsExpr 
+ * countIsExpr      char_t*          ATTR_countIsExpr
+ * stringExpr       char_t*          ATTR_stringExpr 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cTypeInfo_getNameLength( );
+ *   uint32_t       cTypeInfo_getSize( );
+ *   int8_t         cTypeInfo_getKind( );
+ *   uint32_t       cTypeInfo_getNType( );
+ *   ER             cTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cTypeInfo_getNMember( );
+ *   ER             cTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tParamInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eParamInfo
+ * entry port: eParamInfo
+ * signature:  nTECSInfo_sParamInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eParamInfo_getName
+ * name:         eParamInfo_getName
+ * global_name:  nTECSInfo_tParamInfo_eParamInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eParamInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eParamInfo_getNameLength
+ * name:         eParamInfo_getNameLength
+ * global_name:  nTECSInfo_tParamInfo_eParamInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eParamInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eParamInfo_getTypeInfo
+ * name:         eParamInfo_getTypeInfo
+ * global_name:  nTECSInfo_tParamInfo_eParamInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eParamInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *desc = cTypeInfo_refer_to_descriptor();
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eParamInfo_getDir
+ * name:         eParamInfo_getDir
+ * global_name:  nTECSInfo_tParamInfo_eParamInfo_getDir
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eParamInfo_getDir(CELLIDX idx, int8_t *dir)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *dir = ATTR_dir;
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tPtrTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tPtrTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tPtrTypeInfo.c	(revision 374)
@@ -0,0 +1,266 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cTypeInfo_getNameLength( );
+ *   uint32_t       cTypeInfo_getSize( );
+ *   int8_t         cTypeInfo_getKind( );
+ *   uint32_t       cTypeInfo_getNType( );
+ *   ER             cTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cTypeInfo_getNMember( );
+ *   ER             cTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tPtrTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return TECSTypeKind_PtrType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *desc = cTypeInfo_refer_to_descriptor();
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tPtrTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tRawEntryDescriptorInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tRawEntryDescriptorInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tRawEntryDescriptorInfo.c	(revision 374)
@@ -0,0 +1,75 @@
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * size             int_t            ATTR_size       
+ * rawEntryDescriptor void**           ATTR_rawEntryDescriptor
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include "nTECSInfo_tRawEntryDescriptorInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eRawEntryDescriptor
+ * entry port: eRawEntryDescriptor
+ * signature:  nTECSInfo_sRawEntryDescriptorInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eRawEntryDescriptor_getNRawEntryDescriptorInfo
+ * name:         eRawEntryDescriptor_getNRawEntryDescriptorInfo
+ * global_name:  nTECSInfo_tRawEntryDescriptorInfo_eRawEntryDescriptor_getNRawEntryDescriptorInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eRawEntryDescriptor_getNRawEntryDescriptorInfo(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eRawEntryDescriptor_getRawDescriptor
+ * name:         eRawEntryDescriptor_getRawDescriptor
+ * global_name:  nTECSInfo_tRawEntryDescriptorInfo_eRawEntryDescriptor_getRawDescriptor
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eRawEntryDescriptor_getRawDescriptor(CELLIDX idx, int_t ith, void** rawDesc)
+{
+	CELLCB	*p_cellcb;
+  ER      ercd = E_OK;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( 0 <= ith && ith < ATTR_size ){
+      *rawDesc = ATTR_rawEntryDescriptor[ ith ];
+  }
+  else {
+      ercd = E_ID;
+  }
+  return ercd;
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tRegionInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tRegionInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tRegionInfo.c	(revision 374)
@@ -0,0 +1,231 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char*            ATTR_name       
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cCellInfo signature: nTECSInfo_sCellInfo context:task optional:true
+ *   bool_t     is_cCellInfo_joined(int subscript)        check if joined
+ *   ER             cCellInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cCellInfo_getNameLength( subscript );
+ *   void           cCellInfo_getCelltypeInfo( subscript, Descriptor( nTECSInfo_sCelltypeInfo )* desc );
+ *   void           cCellInfo_getCBP( subscript, void** cbp );
+ *   void           cCellInfo_getINIBP( subscript, void** inibp );
+ *       subscript:  0...(NCP_cCellInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sCellInfo ) cCellInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sCellInfo ) cCellInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ * call port: cRegionInfo signature: nTECSInfo_sRegionInfo context:task optional:true
+ *   bool_t     is_cRegionInfo_joined(int subscript)        check if joined
+ *   ER             cRegionInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cRegionInfo_getNameLength( subscript );
+ *   uint32_t       cRegionInfo_getNCell( subscript );
+ *   ER             cRegionInfo_getCellInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sCellInfo )* des );
+ *   uint32_t       cRegionInfo_getNRegion( subscript );
+ *   ER             cRegionInfo_getRegionInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sRegionInfo )* des );
+ *       subscript:  0...(NCP_cRegionInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sRegionInfo ) cRegionInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sRegionInfo ) cRegionInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tRegionInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eRegionInfo
+ * entry port: eRegionInfo
+ * signature:  nTECSInfo_sRegionInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eRegionInfo_getName
+ * name:         eRegionInfo_getName
+ * global_name:  nTECSInfo_tRegionInfo_eRegionInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eRegionInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eRegionInfo_getNameLength
+ * name:         eRegionInfo_getNameLength
+ * global_name:  nTECSInfo_tRegionInfo_eRegionInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eRegionInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eRegionInfo_getNCell
+ * name:         eRegionInfo_getNCell
+ * global_name:  nTECSInfo_tRegionInfo_eRegionInfo_getNCell
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eRegionInfo_getNCell(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return NCP_cCellInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eRegionInfo_getCellInfo
+ * name:         eRegionInfo_getCellInfo
+ * global_name:  nTECSInfo_tRegionInfo_eRegionInfo_getCellInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eRegionInfo_getCellInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sCellInfo )* des)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *des = cCellInfo_refer_to_descriptor( ith );
+}
+
+/* #[<ENTRY_FUNC>]# eRegionInfo_getNRegion
+ * name:         eRegionInfo_getNRegion
+ * global_name:  nTECSInfo_tRegionInfo_eRegionInfo_getNRegion
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eRegionInfo_getNRegion(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return NCP_cRegionInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eRegionInfo_getRegionInfo
+ * name:         eRegionInfo_getRegionInfo
+ * global_name:  nTECSInfo_tRegionInfo_eRegionInfo_getRegionInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eRegionInfo_getRegionInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sRegionInfo )* des)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *des = cRegionInfo_refer_to_descriptor( ith );
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tSignatureInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tSignatureInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tSignatureInfo.c	(revision 374)
@@ -0,0 +1,180 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char*            ATTR_name       
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cFunctionInfo signature: nTECSInfo_sFunctionInfo context:task optional:true
+ *   bool_t     is_cFunctionInfo_joined(int subscript)        check if joined
+ *   ER             cFunctionInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cFunctionInfo_getNameLength( subscript );
+ *   void           cFunctionInfo_getReturnTypeInfo( subscript, Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cFunctionInfo_getNParam( subscript );
+ *   ER             cFunctionInfo_getParamInfo( subscript, uint32_t ith, Descriptor( nTECSInfo_sParamInfo )* param );
+ *       subscript:  0...(NCP_cFunctionInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sFunctionInfo ) cFunctionInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sFunctionInfo ) cFunctionInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tSignatureInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eSignatureInfo
+ * entry port: eSignatureInfo
+ * signature:  nTECSInfo_sSignatureInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eSignatureInfo_getName
+ * name:         eSignatureInfo_getName
+ * global_name:  nTECSInfo_tSignatureInfo_eSignatureInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSignatureInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSignatureInfo_getNameLength
+ * name:         eSignatureInfo_getNameLength
+ * global_name:  nTECSInfo_tSignatureInfo_eSignatureInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eSignatureInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+      /* çµç«¯æå­ (NULL) ãå«ã */
+}
+
+/* #[<ENTRY_FUNC>]# eSignatureInfo_getNFunction
+ * name:         eSignatureInfo_getNFunction
+ * global_name:  nTECSInfo_tSignatureInfo_eSignatureInfo_getNFunction
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eSignatureInfo_getNFunction(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return NCP_cFunctionInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eSignatureInfo_getFunctionInfo
+ * name:         eSignatureInfo_getFunctionInfo
+ * global_name:  nTECSInfo_tSignatureInfo_eSignatureInfo_getFunctionInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSignatureInfo_getFunctionInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sFunctionInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  *desc = cFunctionInfo_ref_desc( ith );
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tStructTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tStructTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tStructTypeInfo.c	(revision 374)
@@ -0,0 +1,270 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cVarDeclInfo signature: nTECSInfo_sVarDeclInfo context:task
+ *   ER             cVarDeclInfo_getName( subscript, char_t* name, int_t max_len );
+ *   uint16_t       cVarDeclInfo_getNameLength( subscript );
+ *   uint32_t       cVarDeclInfo_getOffset( subscript );
+ *   void           cVarDeclInfo_getTypeInfo( subscript, Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   void           cVarDeclInfo_getSizeIsExpr( subscript, char_t* expr_str, int32_t max_len );
+ *   ER             cVarDeclInfo_getSizeIs( subscript, uint32_t* size, const void* p_cb );
+ *       subscript:  0...(NCP_cVarDeclInfo-1)
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sVarDeclInfo ) cVarDeclInfo_refer_to_descriptor( int_t subscript );
+ *      Descriptor( nTECSInfo_sVarDeclInfo ) cVarDeclInfo_ref_desc( int_t subscript )      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tStructTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+      /* çµç«¯æå­ (NULL) ãå«ã */
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return TECSTypeKind_StructType;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return NCP_cVarDeclInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  // *desc = cTypeInfo_refer_to_descriptor( ith );
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return NCP_cVarDeclInfo;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tStructTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( ith >= NCP_cVarDeclInfo )
+      ercd = E_NOEXS;
+  else
+      *desc = cVarDeclInfo_refer_to_descriptor( ith );
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfoAccessor.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfoAccessor.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfoAccessor.c	(revision 374)
@@ -0,0 +1,1130 @@
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * NAME_LEN         int16_t          ATTR_NAME_LEN   
+ * name             char_t*          VAR_name        
+ * name2            char_t*          VAR_name2       
+ * selectedCbp      int8_t*          VAR_selectedCbp 
+ * selectedInibp    int8_t*          VAR_selectedInibp
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTECSInfo signature: nTECSInfo_sTECSInfo context:task
+ *   ER             cTECSInfo_findNamespace( const char_t* namespace_path, Descriptor( nTECSInfo_sNamespaceInfo )* NSdesc );
+ *   ER             cTECSInfo_findRegion( const char_t* namespace_path, Descriptor( nTECSInfo_sRegionInfo )* RGNdesc );
+ *   ER             cTECSInfo_findSignature( const char_t* namespace_path, Descriptor( nTECSInfo_sSignatureInfo )* SIGdesc );
+ *   ER             cTECSInfo_findCelltype( const char_t* namespace_path, Descriptor( nTECSInfo_sCelltypeInfo )* CTdesc );
+ *   ER             cTECSInfo_findCell( const char_t* namespace_path, Descriptor( nTECSInfo_sCellInfo )* CELLdesc );
+ * call port: cNSInfo signature: nTECSInfo_sNamespaceInfo context:task optional:true
+ *   bool_t     is_cNSInfo_joined()                     check if joined
+ *   ER             cNSInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cNSInfo_getNameLength( );
+ *   uint32_t       cNSInfo_getNNamespace( );
+ *   ER             cNSInfo_getNamespaceInfo( uint32_t ith, Descriptor( nTECSInfo_sNamespaceInfo )* des );
+ *   uint32_t       cNSInfo_getNSignature( );
+ *   ER             cNSInfo_getSignatureInfo( uint32_t ith, Descriptor( nTECSInfo_sSignatureInfo )* des );
+ *   uint32_t       cNSInfo_getNCelltype( );
+ *   ER             cNSInfo_getCelltypeInfo( uint32_t ith, Descriptor( nTECSInfo_sCelltypeInfo )* des );
+ *   [dynamic, optional]
+ *      void           cNSInfo_set_descriptor( Descriptor( nTECSInfo_sNamespaceInfo ) desc );
+ *      void           cNSInfo_unjoin(  );
+ * call port: cCelltypeInfo signature: nTECSInfo_sCelltypeInfo context:task optional:true
+ *   bool_t     is_cCelltypeInfo_joined()                     check if joined
+ *   ER             cCelltypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCelltypeInfo_getNameLength( );
+ *   uint32_t       cCelltypeInfo_getNAttr( );
+ *   ER             cCelltypeInfo_getAttrInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNVar( );
+ *   ER             cCelltypeInfo_getVarInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNCall( );
+ *   ER             cCelltypeInfo_getCallInfo( uint32_t ith, Descriptor( nTECSInfo_sCallInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNEntry( );
+ *   ER             cCelltypeInfo_getEntryInfo( uint32_t ith, Descriptor( nTECSInfo_sEntryInfo )* desc );
+ *   bool_t         cCelltypeInfo_isSingleton( );
+ *   bool_t         cCelltypeInfo_isIDX_is_ID( );
+ *   uint32_t       cCelltypeInfo_sizeOfCB( );
+ *   uint32_t       cCelltypeInfo_sizeOfINIB( );
+ *   [dynamic, optional]
+ *      void           cCelltypeInfo_set_descriptor( Descriptor( nTECSInfo_sCelltypeInfo ) desc );
+ *      void           cCelltypeInfo_unjoin(  );
+ * call port: cAttrInfo signature: nTECSInfo_sVarDeclInfo context:task optional:true
+ *   bool_t     is_cAttrInfo_joined()                     check if joined
+ *   ER             cAttrInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cAttrInfo_getNameLength( );
+ *   uint32_t       cAttrInfo_getOffset( );
+ *   void           cAttrInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   void           cAttrInfo_getSizeIsExpr( char_t* expr_str, int32_t max_len );
+ *   ER             cAttrInfo_getSizeIs( uint32_t* size, const void* p_cb );
+ *   [dynamic, optional]
+ *      void           cAttrInfo_set_descriptor( Descriptor( nTECSInfo_sVarDeclInfo ) desc );
+ *      void           cAttrInfo_unjoin(  );
+ * call port: cVarInfo signature: nTECSInfo_sVarDeclInfo context:task optional:true
+ *   bool_t     is_cVarInfo_joined()                     check if joined
+ *   ER             cVarInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cVarInfo_getNameLength( );
+ *   uint32_t       cVarInfo_getOffset( );
+ *   void           cVarInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   void           cVarInfo_getSizeIsExpr( char_t* expr_str, int32_t max_len );
+ *   ER             cVarInfo_getSizeIs( uint32_t* size, const void* p_cb );
+ *   [dynamic, optional]
+ *      void           cVarInfo_set_descriptor( Descriptor( nTECSInfo_sVarDeclInfo ) desc );
+ *      void           cVarInfo_unjoin(  );
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task optional:true
+ *   bool_t     is_cTypeInfo_joined()                     check if joined
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cTypeInfo_getNameLength( );
+ *   uint32_t       cTypeInfo_getSize( );
+ *   int8_t         cTypeInfo_getKind( );
+ *   uint32_t       cTypeInfo_getNType( );
+ *   ER             cTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cTypeInfo_getNMember( );
+ *   ER             cTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [dynamic, optional]
+ *      void           cTypeInfo_set_descriptor( Descriptor( nTECSInfo_sTypeInfo ) desc );
+ *      void           cTypeInfo_unjoin(  );
+ * call port: cRegionInfo signature: nTECSInfo_sRegionInfo context:task optional:true
+ *   bool_t     is_cRegionInfo_joined()                     check if joined
+ *   ER             cRegionInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cRegionInfo_getNameLength( );
+ *   uint32_t       cRegionInfo_getNCell( );
+ *   ER             cRegionInfo_getCellInfo( uint32_t ith, Descriptor( nTECSInfo_sCellInfo )* des );
+ *   uint32_t       cRegionInfo_getNRegion( );
+ *   ER             cRegionInfo_getRegionInfo( uint32_t ith, Descriptor( nTECSInfo_sRegionInfo )* des );
+ *   [dynamic, optional]
+ *      void           cRegionInfo_set_descriptor( Descriptor( nTECSInfo_sRegionInfo ) desc );
+ *      void           cRegionInfo_unjoin(  );
+ * call port: cCellInfo signature: nTECSInfo_sCellInfo context:task optional:true
+ *   bool_t     is_cCellInfo_joined()                     check if joined
+ *   ER             cCellInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCellInfo_getNameLength( );
+ *   void           cCellInfo_getCelltypeInfo( Descriptor( nTECSInfo_sCelltypeInfo )* desc );
+ *   void           cCellInfo_getCBP( void** cbp );
+ *   void           cCellInfo_getINIBP( void** inibp );
+ *   [dynamic, optional]
+ *      void           cCellInfo_set_descriptor( Descriptor( nTECSInfo_sCellInfo ) desc );
+ *      void           cCellInfo_unjoin(  );
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tTECSInfoAccessor_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eSelector
+ * entry port: eSelector
+ * signature:  nTECSInfo_sAccessor
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eSelector_selectNamespaceInfoByName
+ * name:         eSelector_selectNamespaceInfoByName
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectNamespaceInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectNamespaceInfoByName(CELLIDX idx, const char_t* namespacePath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sNamespaceInfo ) NSdesc;
+    if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+  /* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = cTECSInfo_findNamespace( namespacePath, &NSdesc );
+  if( ercd == E_OK ){
+      cNSInfo_set_descriptor( NSdesc );
+  }
+  else{
+      cNSInfo_unjoin();
+  }
+
+  return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCelltypeInfoByName
+ * name:         eSelector_selectCelltypeInfoByName
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectCelltypeInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCelltypeInfoByName(CELLIDX idx, const char_t* namespacePath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sCelltypeInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = cTECSInfo_findCelltype( namespacePath, &desc );
+  if( ercd == E_OK ){
+      cCelltypeInfo_set_descriptor( desc );
+  }
+  else{
+      cCelltypeInfo_unjoin();
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureInfoByName
+ * name:         eSelector_selectSignatureInfoByName
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectSignatureInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureInfoByName(CELLIDX idx, const char_t* namespacePath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectRegionInfoByName
+ * name:         eSelector_selectRegionInfoByName
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectRegionInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectRegionInfoByName(CELLIDX idx, const char_t* regionPath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCellInfoByName
+ * name:         eSelector_selectCellInfoByName
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectCellInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCellInfoByName(CELLIDX idx, const char_t* cellPath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedNamespaceInfo
+ * name:         eSelector_getSelectedNamespaceInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedNamespaceInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedNamespaceInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_celltype, int_t* num_signature)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCelltypeInfo
+ * name:         eSelector_selectCelltypeInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectCelltypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCelltypeInfo(CELLIDX idx, int_t i)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureInfo
+ * name:         eSelector_selectSignatureInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectSignatureInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureInfo(CELLIDX idx, int_t i)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCelltypeInfo
+ * name:         eSelector_getSelectedCelltypeInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedCelltypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCelltypeInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_attr, int_t* num_var, int_t* num_call, int_t* num_entry)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCallInfo
+ * name:         eSelector_selectCallInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectCallInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCallInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectEntryInfo
+ * name:         eSelector_selectEntryInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectEntryInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectEntryInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectAttrInfo
+ * name:         eSelector_selectAttrInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectAttrInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectAttrInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectVarInfo
+ * name:         eSelector_selectVarInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectVarInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectVarInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedAttrInfo
+ * name:         eSelector_getSelectedAttrInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedAttrInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedAttrInfo(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSizeIsExprOfAttr
+ * name:         eSelector_getSizeIsExprOfAttr
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSizeIsExprOfAttr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eSelector_getSizeIsExprOfAttr(CELLIDX idx, char_t* expr_str, int32_t max_len)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfAttr
+ * name:         eSelector_selectTypeInfoOfAttr
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectTypeInfoOfAttr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfAttr(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedVarInfo
+ * name:         eSelector_getSelectedVarInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedVarInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedVarInfo(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSizeIsExprOfVar
+ * name:         eSelector_getSizeIsExprOfVar
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSizeIsExprOfVar
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eSelector_getSizeIsExprOfVar(CELLIDX idx, char_t* expr_str, int32_t max_len)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfVar
+ * name:         eSelector_selectTypeInfoOfVar
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectTypeInfoOfVar
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfVar(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallInfo
+ * name:         eSelector_getSelectedCallInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedCallInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* array_size)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureOfCall
+ * name:         eSelector_selectSignatureOfCall
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectSignatureOfCall
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureOfCall(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallSpecifierInfo
+ * name:         eSelector_getSelectedCallSpecifierInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedCallSpecifierInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallSpecifierInfo(CELLIDX idx, bool_t* b_optional, bool_t* b_dynamic, bool_t* b_ref_desc, bool_t* b_omit)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallInternalInfo
+ * name:         eSelector_getSelectedCallInternalInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedCallInternalInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallInternalInfo(CELLIDX idx, bool_t* b_allocator_port, bool_t* b_require_port)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallLocationInfo
+ * name:         eSelector_getSelectedCallLocationInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedCallLocationInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallLocationInfo(CELLIDX idx, uint32_t* offset, int8_t* place)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallOptimizeInfo
+ * name:         eSelector_getSelectedCallOptimizeInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedCallOptimizeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallOptimizeInfo(CELLIDX idx, bool_t* b_VMT_useless, bool_t* b_skelton_useless, bool_t* b_cell_unique)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedEntryInfo
+ * name:         eSelector_getSelectedEntryInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedEntryInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedEntryInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* array_size)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureOfEntry
+ * name:         eSelector_selectSignatureOfEntry
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectSignatureOfEntry
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureOfEntry(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedEntryInlineInfo
+ * name:         eSelector_getSelectedEntryInlineInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedEntryInlineInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedEntryInlineInfo(CELLIDX idx, bool_t* b_inline)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedSignatureInfo
+ * name:         eSelector_getSelectedSignatureInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedSignatureInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedSignatureInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_function)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selecFunctionInfoByIndex
+ * name:         eSelector_selecFunctionInfoByIndex
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selecFunctionInfoByIndex
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selecFunctionInfoByIndex(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedFunctionInfo
+ * name:         eSelector_getSelectedFunctionInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedFunctionInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedFunctionInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_args)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfReturn
+ * name:         eSelector_selectTypeInfoOfReturn
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectTypeInfoOfReturn
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfReturn(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedParamInfo
+ * name:         eSelector_getSelectedParamInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedParamInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedParamInfo(CELLIDX idx, char_t* name, int_t max_len, int8_t* dir)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectParamInfo
+ * name:         eSelector_selectParamInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectParamInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectParamInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfParam
+ * name:         eSelector_selectTypeInfoOfParam
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectTypeInfoOfParam
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfParam(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedTypeInfo
+ * name:         eSelector_getSelectedTypeInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedTypeInfo(CELLIDX idx, char_t* name, int_t max_len, int8_t* kind)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfType
+ * name:         eSelector_selectTypeInfoOfType
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectTypeInfoOfType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfType(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedRegionInfo
+ * name:         eSelector_getSelectedRegionInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelectedRegionInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedRegionInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_cell)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCellInfo
+ * name:         eSelector_selectCellInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectCellInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCellInfo(CELLIDX idx, int_t i)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelecteCellInfo
+ * name:         eSelector_getSelecteCellInfo
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getSelecteCellInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelecteCellInfo(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCelltypeInfoOfCell
+ * name:         eSelector_selectCelltypeInfoOfCell
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_selectCelltypeInfoOfCell
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCelltypeInfoOfCell(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getAttrValue
+ * name:         eSelector_getAttrValue
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getAttrValue
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getAttrValue(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getAttrSizeIsValue
+ * name:         eSelector_getAttrSizeIsValue
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getAttrSizeIsValue
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getAttrSizeIsValue(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getVarValue
+ * name:         eSelector_getVarValue
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getVarValue
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getVarValue(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getVarSizeIsValue
+ * name:         eSelector_getVarSizeIsValue
+ * global_name:  nTECSInfo_tTECSInfoAccessor_eSelector_getVarSizeIsValue
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getVarSizeIsValue(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfoSub.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfoSub.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfoSub.c	(revision 374)
@@ -0,0 +1,543 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name_len         int32_t          ATTR_name_len   
+ * path_len         int32_t          ATTR_path_len   
+ * name1            char_t*          VAR_name1       
+ * name2            char_t*          VAR_name2       
+ * path             char_t*          VAR_path        
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cNamespaceInfo signature: nTECSInfo_sNamespaceInfo context:task
+ *   ER             cNamespaceInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cNamespaceInfo_getNameLength( );
+ *   uint32_t       cNamespaceInfo_getNNamespace( );
+ *   ER             cNamespaceInfo_getNamespaceInfo( uint32_t ith, Descriptor( nTECSInfo_sNamespaceInfo )* des );
+ *   uint32_t       cNamespaceInfo_getNSignature( );
+ *   ER             cNamespaceInfo_getSignatureInfo( uint32_t ith, Descriptor( nTECSInfo_sSignatureInfo )* des );
+ *   uint32_t       cNamespaceInfo_getNCelltype( );
+ *   ER             cNamespaceInfo_getCelltypeInfo( uint32_t ith, Descriptor( nTECSInfo_sCelltypeInfo )* des );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sNamespaceInfo ) cNamespaceInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sNamespaceInfo ) cNamespaceInfo_ref_desc()      (same as above; abbreviated version);
+ * call port: cRegionInfo signature: nTECSInfo_sRegionInfo context:task
+ *   ER             cRegionInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cRegionInfo_getNameLength( );
+ *   uint32_t       cRegionInfo_getNCell( );
+ *   ER             cRegionInfo_getCellInfo( uint32_t ith, Descriptor( nTECSInfo_sCellInfo )* des );
+ *   uint32_t       cRegionInfo_getNRegion( );
+ *   ER             cRegionInfo_getRegionInfo( uint32_t ith, Descriptor( nTECSInfo_sRegionInfo )* des );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sRegionInfo ) cRegionInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sRegionInfo ) cRegionInfo_ref_desc()      (same as above; abbreviated version);
+ * call port: cNamespaceInfoTemp signature: nTECSInfo_sNamespaceInfo context:task optional:true
+ *   bool_t     is_cNamespaceInfoTemp_joined()                     check if joined
+ *   ER             cNamespaceInfoTemp_getName( char_t* name, int_t max_len );
+ *   uint16_t       cNamespaceInfoTemp_getNameLength( );
+ *   uint32_t       cNamespaceInfoTemp_getNNamespace( );
+ *   ER             cNamespaceInfoTemp_getNamespaceInfo( uint32_t ith, Descriptor( nTECSInfo_sNamespaceInfo )* des );
+ *   uint32_t       cNamespaceInfoTemp_getNSignature( );
+ *   ER             cNamespaceInfoTemp_getSignatureInfo( uint32_t ith, Descriptor( nTECSInfo_sSignatureInfo )* des );
+ *   uint32_t       cNamespaceInfoTemp_getNCelltype( );
+ *   ER             cNamespaceInfoTemp_getCelltypeInfo( uint32_t ith, Descriptor( nTECSInfo_sCelltypeInfo )* des );
+ *   [dynamic, optional]
+ *      void           cNamespaceInfoTemp_set_descriptor( Descriptor( nTECSInfo_sNamespaceInfo ) desc );
+ *      void           cNamespaceInfoTemp_unjoin(  );
+ * call port: cRegionInfoTemp signature: nTECSInfo_sRegionInfo context:task optional:true
+ *   bool_t     is_cRegionInfoTemp_joined()                     check if joined
+ *   ER             cRegionInfoTemp_getName( char_t* name, int_t max_len );
+ *   uint16_t       cRegionInfoTemp_getNameLength( );
+ *   uint32_t       cRegionInfoTemp_getNCell( );
+ *   ER             cRegionInfoTemp_getCellInfo( uint32_t ith, Descriptor( nTECSInfo_sCellInfo )* des );
+ *   uint32_t       cRegionInfoTemp_getNRegion( );
+ *   ER             cRegionInfoTemp_getRegionInfo( uint32_t ith, Descriptor( nTECSInfo_sRegionInfo )* des );
+ *   [dynamic, optional]
+ *      void           cRegionInfoTemp_set_descriptor( Descriptor( nTECSInfo_sRegionInfo ) desc );
+ *      void           cRegionInfoTemp_unjoin(  );
+ * call port: cCelltypeInfoTemp signature: nTECSInfo_sCelltypeInfo context:task optional:true
+ *   bool_t     is_cCelltypeInfoTemp_joined()                     check if joined
+ *   ER             cCelltypeInfoTemp_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCelltypeInfoTemp_getNameLength( );
+ *   uint32_t       cCelltypeInfoTemp_getNAttr( );
+ *   ER             cCelltypeInfoTemp_getAttrInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfoTemp_getNVar( );
+ *   ER             cCelltypeInfoTemp_getVarInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfoTemp_getNCall( );
+ *   ER             cCelltypeInfoTemp_getCallInfo( uint32_t ith, Descriptor( nTECSInfo_sCallInfo )* desc );
+ *   uint32_t       cCelltypeInfoTemp_getNEntry( );
+ *   ER             cCelltypeInfoTemp_getEntryInfo( uint32_t ith, Descriptor( nTECSInfo_sEntryInfo )* desc );
+ *   bool_t         cCelltypeInfoTemp_isSingleton( );
+ *   bool_t         cCelltypeInfoTemp_isIDX_is_ID( );
+ *   uint32_t       cCelltypeInfoTemp_sizeOfCB( );
+ *   uint32_t       cCelltypeInfoTemp_sizeOfINIB( );
+ *   [dynamic, optional]
+ *      void           cCelltypeInfoTemp_set_descriptor( Descriptor( nTECSInfo_sCelltypeInfo ) desc );
+ *      void           cCelltypeInfoTemp_unjoin(  );
+ * call port: cCellInfoTemp signature: nTECSInfo_sCellInfo context:task optional:true
+ *   bool_t     is_cCellInfoTemp_joined()                     check if joined
+ *   ER             cCellInfoTemp_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCellInfoTemp_getNameLength( );
+ *   uint32_t       cCellInfoTemp_getNRawEntryDescriptorInfo( );
+ *   ER             cCellInfoTemp_getRawEntryDescriptorInfo( int_t index, Descriptor( nTECSInfo_sRawEntryDescriptorInfo )* desc );
+ *   void           cCellInfoTemp_getCelltypeInfo( Descriptor( nTECSInfo_sCelltypeInfo )* desc );
+ *   void           cCellInfoTemp_getCBP( void** cbp );
+ *   void           cCellInfoTemp_getINIBP( void** inibp );
+ *   [dynamic, optional]
+ *      void           cCellInfoTemp_set_descriptor( Descriptor( nTECSInfo_sCellInfo ) desc );
+ *      void           cCellInfoTemp_unjoin(  );
+ * call port: cEntryInfoTemp signature: nTECSInfo_sEntryInfo context:task optional:true
+ *   bool_t     is_cEntryInfoTemp_joined()                     check if joined
+ *   ER             cEntryInfoTemp_getName( char_t* name, int_t max_len );
+ *   uint16_t       cEntryInfoTemp_getNameLength( );
+ *   void           cEntryInfoTemp_getSignatureInfo( Descriptor( nTECSInfo_sSignatureInfo )* desc );
+ *   uint32_t       cEntryInfoTemp_getArraySize( );
+ *   bool_t         cEntryInfoTemp_isInline( );
+ *   [dynamic, optional]
+ *      void           cEntryInfoTemp_set_descriptor( Descriptor( nTECSInfo_sEntryInfo ) desc );
+ *      void           cEntryInfoTemp_unjoin(  );
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tTECSInfoSub_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+static ER
+separate_basename( const char_t **namespace_path, char_t **basename );
+
+
+/*
+ * VAR_name1 â¦ å¼æ°ã¨ãã¦æ¸¡ããããã®ãã³ãã¼ããããã ããéä¸­ã® '::' ã '\0' ã«æ¸ãæãããã¨ã¯ããã
+ * VAR_name2 â¦ é½åº¦ä¸æ¸ããã¦ä½¿ç¨ãã
+ */
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTECSInfo
+ * entry port: eTECSInfo
+ * signature:  nTECSInfo_sTECSInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findNamespace
+ * name:         eTECSInfo_findNamespace
+ * global_name:  nTECSInfo_tTECSInfoSub_eTECSInfo_findNamespace
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTECSInfo_findNamespace(const char_t* namespace_path, Descriptor( nTECSInfo_sNamespaceInfo )* nsDesc)
+{
+    const char_t  *p = namespace_path;
+    char_t  *p2;
+    Descriptor( nTECSInfo_sNamespaceInfo ) desc, desc2;
+    int     i;
+    int     n;
+
+    if( p[ 0 ] == ':' && p[ 1 ] == ':' ){
+        p += 2;
+    }
+    desc = cNamespaceInfo_refer_to_descriptor(); // root name space
+    while( *p != '\0' ){
+        p2 = VAR_name1;
+        for( i = 0; i < ATTR_name_len; i++ ){
+            if( *p == '\0' ||  *p == ':' ){
+                *p2 = '\0';
+                break;
+            }
+            *p2++ = *p++;
+        }
+        if( i == ATTR_name_len )
+            return E_NORES;
+
+        desc2 = desc;
+        cNamespaceInfoTemp_set_descriptor( desc2 );
+        n = cNamespaceInfoTemp_getNNamespace( );
+        for( i = 0; i < n; i++ ){
+            cNamespaceInfoTemp_set_descriptor( desc2 );
+            cNamespaceInfoTemp_getNamespaceInfo( i, &desc );
+            cNamespaceInfoTemp_set_descriptor( desc );
+            cNamespaceInfoTemp_getName( VAR_name2, ATTR_name_len );
+            if( strcmp( VAR_name1, VAR_name2 ) == 0 )
+                break;
+        }
+        if( i == n )
+            return E_NOID;
+
+        if( p[ 0 ] == ':' ){
+            if( p[ 1 ] == ':' )
+                p += 2;
+            else
+                return E_OBJ;
+        }
+    }
+    *nsDesc = desc;
+    return E_OK;
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findRegion
+ * name:         eTECSInfo_findRegion
+ * global_name:  nTECSInfo_tTECSInfoSub_eTECSInfo_findRegion
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTECSInfo_findRegion(const char_t* namespace_path, Descriptor( nTECSInfo_sRegionInfo )* regionDesc)
+{
+    const char_t  *p = namespace_path;
+    char_t  *p2;
+    Descriptor( nTECSInfo_sRegionInfo ) desc, desc2;
+    int     i;
+    int     n;
+
+    if( p[ 0 ] == ':' && p[ 1 ] == ':' ){
+        p += 2;
+    }
+    desc = cRegionInfo_refer_to_descriptor();
+    while( *p != '\0' ){
+        p2 = VAR_name1;
+        for( i = 0; i < ATTR_name_len; i++ ){
+            if( *p == '\0' ||  *p == ':' ){
+                *p2 = '\0';
+                break;
+            }
+            *p2++ = *p++;
+        }
+        if( i == ATTR_name_len )
+            return E_NORES;
+
+        desc2 = desc;
+        cRegionInfoTemp_set_descriptor( desc2 );
+        n = cRegionInfoTemp_getNRegion( );
+        for( i = 0; i < n; i++ ){
+            // syslog_3( LOG_NOTICE, "tTECSInfo.eTECSInfo.findRegion 2 %s i=%d n=%d", VAR_name1, i, n );
+            cRegionInfoTemp_set_descriptor( desc2 );
+            cRegionInfoTemp_getRegionInfo( i, &desc );
+            cRegionInfoTemp_set_descriptor( desc );
+            cRegionInfoTemp_getName( VAR_name2, ATTR_name_len );
+            if( strcmp( VAR_name1, VAR_name2 ) == 0 )
+                break;
+        }
+        if( i == n )
+            return E_NOID;
+
+        if( p[ 0 ] == ':' ){
+            if( p[ 1 ] == ':' )
+                p += 2;
+            else
+                return E_OBJ;
+        }
+    }
+    *regionDesc = desc;
+    return E_OK;
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findSignature
+ * name:         eTECSInfo_findSignature
+ * global_name:  nTECSInfo_tTECSInfoSub_eTECSInfo_findSignature
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTECSInfo_findSignature(const char_t* namespace_path, Descriptor( nTECSInfo_sSignatureInfo )* signatureDesc)
+{
+    Descriptor( nTECSInfo_sNamespaceInfo ) nsDesc;
+    Descriptor( nTECSInfo_sSignatureInfo ) desc;
+    ER        ercd;
+    char_t    *pname;
+    int       i, n;
+
+    ercd = separate_basename( &namespace_path, &pname );
+    if( ercd != E_OK )
+        return ercd;
+
+    ercd = eTECSInfo_findNamespace( namespace_path, &nsDesc);
+    if( ercd != E_OK )
+        return ercd;
+
+    // syslog_0( LOG_NOTICE, "tTECSInfo.eTECSInfo.findCell 4" );
+    cNamespaceInfoTemp_set_descriptor( nsDesc );
+    n = cNamespaceInfoTemp_getNSignature( );
+    for( i = 0; i < n; i++ ){
+        cNamespaceInfoTemp_getSignatureInfo( i, &desc );
+        cSignatureInfoTemp_set_descriptor( desc );
+        cSignatureInfoTemp_getName( VAR_name1, ATTR_name_len );
+        if( strcmp( pname, VAR_name1 ) == 0 )
+            break;
+    }
+    // syslog_0( LOG_NOTICE, "tTECSInfo.eTECSInfo.findCell 5" );
+    if( i == n )
+        return E_NOEXS;
+
+    *signatureDesc = desc;
+    return E_OK;
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findCelltype
+ * name:         eTECSInfo_findCelltype
+ * global_name:  nTECSInfo_tTECSInfoSub_eTECSInfo_findCelltype
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTECSInfo_findCelltype(const char_t* namespace_path, Descriptor( nTECSInfo_sCelltypeInfo )* celltypeDesc)
+{
+  return E_NOSPT;
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findCell
+ * name:         eTECSInfo_findCell
+ * global_name:  nTECSInfo_tTECSInfoSub_eTECSInfo_findCell
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTECSInfo_findCell(const char_t* namespace_path, Descriptor( nTECSInfo_sCellInfo )* cellDesc)
+{
+    char_t  *p, *pname;
+    Descriptor( nTECSInfo_sRegionInfo ) RegionDesc;
+    Descriptor( nTECSInfo_sCellInfo )   desc;
+    int     i, n, len;
+    ER      ercd;
+
+#if 0
+    // syslog_0( LOG_NOTICE, "tTECSInfo.eTECSInfo.findCell 1" );
+    len = strnlen( namespace_path, ATTR_path_len );
+    if( len >= ATTR_path_len ){
+        return E_NOMEM;
+    }
+    if( VAR_path != namespace_path )     // findRawEntryDescriptorInfo ããå¼ã°ããæãVAR_path ã«å
+¥ã£ã¦ããã®ã§ã³ãã¼ä¸è¦
+        strcpy( VAR_path, namespace_path );
+    p = &VAR_path[ len - 1 ];
+    while( p > VAR_path ){
+        if( *p == ':' )
+            break;
+        p--;
+    }
+    if( *p == ':' ){
+        p--;
+        if( p < VAR_path || *p != ':' )
+            return E_PAR;    // :: ã§ã¯ãªãã: ã§ãã£ã
+        if( p == VAR_path ){
+            namespace_path = "::";
+        }
+        else{
+            *p = '\0';
+            namespace_path = VAR_path;
+        }
+        pname = &p[2];
+    }
+    else{
+        namespace_path = "::";
+        pname = VAR_path;
+    }
+#endif
+    ercd = separate_basename( &namespace_path, &pname );
+    if( ercd != E_OK )
+        return ercd;
+
+    // syslog_2( LOG_NOTICE, "tTECSInfo.eTECSInfo.findCell 2 %s %s", namespace_path, pname );
+    
+    // syslog_0( LOG_NOTICE, "tTECSInfo.eTECSInfo.findCell 3" );
+    ercd = eTECSInfo_findRegion( namespace_path, &RegionDesc);
+    if( ercd != E_OK )
+        return ercd;
+
+    // syslog_0( LOG_NOTICE, "tTECSInfo.eTECSInfo.findCell 4" );
+    cRegionInfoTemp_set_descriptor( RegionDesc );
+    n = cRegionInfoTemp_getNCell( );
+    for( i = 0; i < n; i++ ){
+        cRegionInfoTemp_getCellInfo( i, &desc );
+        cCellInfoTemp_set_descriptor( desc );
+        cCellInfoTemp_getName( VAR_name1, ATTR_name_len );
+        if( strcmp( pname, VAR_name1 ) == 0 )
+            break;
+    }
+    // syslog_0( LOG_NOTICE, "tTECSInfo.eTECSInfo.findCell 5" );
+    if( i == n )
+        return E_NOEXS;
+
+    *cellDesc = desc;
+    return E_OK;
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findRawEntryDescriptor
+ * name:         eTECSInfo_findRawEntryDescriptor
+ * global_name:  nTECSInfo_tTECSInfoSub_eTECSInfo_findRawEntryDescriptor
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTECSInfo_findRawEntryDescriptor(const char_t* namespace_path, int_t ith, Descriptor( nTECSInfo_sRawEntryDescriptorInfo )* rawEntryDescDesc, Descriptor( nTECSInfo_sEntryInfo )* entryDesc)
+{
+    int_t  len;
+    Descriptor( nTECSInfo_sCelltypeInfo )  celltypeDesc;
+    Descriptor( nTECSInfo_sCellInfo )      cellDesc;
+    Descriptor( nTECSInfo_sEntryInfo )     entDesc;
+    char_t *p;
+    int_t  i, n;
+    ER     ercd;
+
+    len = strnlen( namespace_path, ATTR_path_len );
+    if( len >= ATTR_path_len ){
+        return E_NOMEM;
+    }
+    strcpy( VAR_path, namespace_path );
+    p = &VAR_path[len-1];
+    while( *p != '.' && p != &VAR_path[0] )
+        p--;
+    if( *p != '.' )
+        return E_PAR;    // '.' ãè¦ã¤ãããªã
+    *p = '\0';
+    ercd = eTECSInfo_findCell( VAR_path, &cellDesc);
+    if( ercd != E_OK )
+        return ercd;
+    cCellInfoTemp_set_descriptor( cellDesc );
+    cCellInfoTemp_getCelltypeInfo( &celltypeDesc  );
+    cCelltypeInfoTemp_set_descriptor( celltypeDesc );
+    n = cCelltypeInfoTemp_getNEntry();
+    p += 1;
+    //syslog_1( LOG_NOTICE, "tTECSInfo.eTECSInfo.findRawEntryDescriptor 4 n_entry=%d", n );
+    // dly_tsk( 10000 );
+    for( i = 0; i < n; i++ ){
+        ercd = cCelltypeInfoTemp_getEntryInfo( i, &entDesc ); // ã¨ã©ã¼ã¯ã¿ãªã
+        //syslog_2( LOG_NOTICE, "tTECSInfo.eTECSInfo.findRawEntryDescriptor 5 ercd=%d entDesc=%x", ercd, entDesc.vdes );
+        cEntryInfoTemp_set_descriptor( entDesc );
+        ercd = cEntryInfoTemp_getName( VAR_name1, ATTR_name_len );
+        //dly_tsk( 5 );
+        //syslog_4( LOG_NOTICE, "tTECSInfo.eTECSInfo.findRawEntryDescriptor 6 ercd=%d entDesc=%x nm=%s p=%s", ercd, entDesc.vdes, VAR_name1, p );
+        //dly_tsk( 5 );
+        if( ercd != E_OK )
+            return ercd;
+        if( strcmp( VAR_name1, p ) == 0 )
+            break;
+    }
+    if( i != n ){
+        cCellInfoTemp_getRawEntryDescriptorInfo( ith, rawEntryDescDesc );
+        *entryDesc = entDesc;
+    }
+    else{
+        ercd = E_NOEXS;
+    }
+    return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findRawEntryDescriptor_unsafe
+ * name:         eTECSInfo_findRawEntryDescriptor_unsafe
+ * global_name:  nTECSInfo_tTECSInfoSub_eTECSInfo_findRawEntryDescriptor_unsafe
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTECSInfo_findRawEntryDescriptor_unsafe(const char_t* namespace_path, void** rawDesc)
+{
+    ER   ercd;
+    Descriptor( nTECSInfo_sRawEntryDescriptorInfo ) rawEntryDescDesc;
+    Descriptor( nTECSInfo_sEntryInfo ) entryDesc;
+    ercd = eTECSInfo_findRawEntryDescriptor(namespace_path, 0, &rawEntryDescDesc, &entryDesc);
+    if( ercd != E_OK )
+        return ercd;
+    cRawEntryDescriptorInfoTemp_set_descriptor( rawEntryDescDesc );
+    ercd = cRawEntryDescriptorInfoTemp_getRawDescriptor( 0, rawDesc );
+    return ercd;
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
+
+/*
+ * namespace_path ã VAR_path ã¸ã³ãã¼ãããã£ã¬ã¯ããªãã¹é¨ã¨ãªãã¸ã§ã¯ãåé¨ã«åå²ãã
+ * namespace_path  "::namespace::subnamespace::object_name"
+ * VAR_path        "::namespace::subnamespace\0:object_name"   ä¸çªå³ã® '::' ã '\0:' ã«ç½®ãæãã
+ * basename        "object_name" ã¸ã®ãã¤ã³ã¿ãè¿ã
+ */
+static ER
+separate_basename( const char_t **namespace_path, char_t **basename )
+{
+    int     i, len;
+    char_t  *p;
+    static const char_t *root_namespacepath = "::";
+
+    len = strnlen( *namespace_path, ATTR_path_len );
+    if( len >= ATTR_path_len ){
+        return E_NOMEM;
+    }
+    if( VAR_path != *namespace_path )     // findRawEntryDescriptorInfo ããå¼ã°ããæãVAR_path ã«å
+¥ã£ã¦ããã®ã§ã³ãã¼ä¸è¦
+        strcpy( VAR_path, *namespace_path );
+    p = &VAR_path[ len - 1 ];
+    while( p > VAR_path ){
+        if( *p == ':' )
+            break;
+        p--;
+    }
+    if( *p == ':' ){
+        p--;
+        if( p < VAR_path || *p != ':' )
+            return E_PAR;    // :: ã§ã¯ãªãã: ã§ãã£ã
+        if( p == VAR_path ){
+            *namespace_path = root_namespacepath;
+        }
+        else{
+            *p = '\0';
+            *namespace_path = VAR_path;
+        }
+        *basename = &p[2];
+    }
+    else{
+        *namespace_path = root_namespacepath;
+        *basename = VAR_path;
+    }
+    return  E_OK;
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfo_inline.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfo_inline.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTECSInfo_inline.h	(revision 374)
@@ -0,0 +1,164 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+#ifndef nTECSInfo_tTECSInfo__INLINE_H
+#define nTECSInfo_tTECSInfo__INLINE_H
+
+/*
+ * This file was automatically generated by tecsgen.
+ * Move and rename like below before editing,
+ *   gen/tTECSInfo_inline_template.h => src/tTECSInfo_inline.h
+ * to avoid to be overwritten by tecsgen.
+ */
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTECSInfo signature: nTECSInfo_sTECSInfo context:task
+ *   ER             cTECSInfo_findNamespace( const char_t* namespace_path, Descriptor( nTECSInfo_sNamespaceInfo )* nsDesc );
+ *   ER             cTECSInfo_findRegion( const char_t* namespace_path, Descriptor( nTECSInfo_sRegionInfo )* regionDesc );
+ *   ER             cTECSInfo_findSignature( const char_t* namespace_path, Descriptor( nTECSInfo_sSignatureInfo )* signatureDesc );
+ *   ER             cTECSInfo_findCelltype( const char_t* namespace_path, Descriptor( nTECSInfo_sCelltypeInfo )* celltypeDesc );
+ *   ER             cTECSInfo_findCell( const char_t* namespace_path, Descriptor( nTECSInfo_sCellInfo )* cellDesc );
+ *   ER             cTECSInfo_findRawEntryDescriptor( const char_t* namespace_path, Descriptor( nTECSInfo_sRawEntryDescriptorInfo )* rawEntryDescDesc, Descriptor( nTECSInfo_sEntryInfo )* entryDesc );
+ *   ER             cTECSInfo_findRawEntryDescriptor_unsafe( const char_t* namespace_path, void** rawDesc );
+ *
+ * #[</PREAMBLE>]# */
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTECSInfo
+ * entry port: eTECSInfo
+ * signature:  nTECSInfo_sTECSInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findNamespace
+ * name:         eTECSInfo_findNamespace
+ * global_name:  nTECSInfo_tTECSInfo_eTECSInfo_findNamespace
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eTECSInfo_findNamespace(const char_t* namespace_path, Descriptor( nTECSInfo_sNamespaceInfo )* nsDesc)
+{
+    return cTECSInfo_findNamespace( namespace_path, nsDesc );
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findRegion
+ * name:         eTECSInfo_findRegion
+ * global_name:  nTECSInfo_tTECSInfo_eTECSInfo_findRegion
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eTECSInfo_findRegion(const char_t* namespace_path, Descriptor( nTECSInfo_sRegionInfo )* regionDesc)
+{
+    return cTECSInfo_findRegion( namespace_path, regionDesc );
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findSignature
+ * name:         eTECSInfo_findSignature
+ * global_name:  nTECSInfo_tTECSInfo_eTECSInfo_findSignature
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eTECSInfo_findSignature(const char_t* namespace_path, Descriptor( nTECSInfo_sSignatureInfo )* signatureDesc)
+{
+    return cTECSInfo_findSignature( namespace_path, signatureDesc );
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findCelltype
+ * name:         eTECSInfo_findCelltype
+ * global_name:  nTECSInfo_tTECSInfo_eTECSInfo_findCelltype
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eTECSInfo_findCelltype(const char_t* namespace_path, Descriptor( nTECSInfo_sCelltypeInfo )* celltypeDesc)
+{
+  return cTECSInfo_findCelltype( namespace_path, celltypeDesc );
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findCell
+ * name:         eTECSInfo_findCell
+ * global_name:  nTECSInfo_tTECSInfo_eTECSInfo_findCell
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eTECSInfo_findCell(const char_t* namespace_path, Descriptor( nTECSInfo_sCellInfo )* cellDesc)
+{
+  return cTECSInfo_findCell( namespace_path, cellDesc );
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findRawEntryDescriptor
+ * name:         eTECSInfo_findRawEntryDescriptor
+ * global_name:  nTECSInfo_tTECSInfo_eTECSInfo_findRawEntryDescriptor
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eTECSInfo_findRawEntryDescriptor(const char_t* namespace_path, int_t ith, Descriptor( nTECSInfo_sRawEntryDescriptorInfo )* rawEntryDescDesc, Descriptor( nTECSInfo_sEntryInfo )* entryDesc)
+{
+    return cTECSInfo_findRawEntryDescriptor(namespace_path, ith, rawEntryDescDesc, entryDesc);
+}
+
+/* #[<ENTRY_FUNC>]# eTECSInfo_findRawEntryDescriptor_unsafe
+ * name:         eTECSInfo_findRawEntryDescriptor_unsafe
+ * global_name:  nTECSInfo_tTECSInfo_eTECSInfo_findRawEntryDescriptor_unsafe
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eTECSInfo_findRawEntryDescriptor_unsafe(const char_t* namespace_path, void** rawDesc)
+{
+    return cTECSInfo_findRawEntryDescriptor_unsafe(namespace_path, rawDesc);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
+
+#endif /* nTECSInfo_tTECSInfo_INLINEH */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tTypeInfo.c	(revision 374)
@@ -0,0 +1,217 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * bitSize          int32_t          ATTR_bitSize    
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task optional:true
+ *   bool_t     is_cTypeInfo_joined()                     check if joined
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   void           cTypeInfo_getNameLength( uint16_t* len );
+ *   void           cTypeInfo_getSize( uint32_t* size );
+ *   void           cTypeInfo_getKind( int8_t* kind );
+ *   void           cTypeInfo_getNType( int32_t* num );
+ *   void           cTypeInfo_getTypeInfo( int32_t ith, Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eTypeInfo_getNameLength(CELLIDX idx, uint16_t* len)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eTypeInfo_getSize(CELLIDX idx, uint32_t* size)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eTypeInfo_getKind(CELLIDX idx, int8_t* kind)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eTypeInfo_getNType(CELLIDX idx, int32_t* num)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eTypeInfo_getTypeInfo(CELLIDX idx, int32_t ith, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tVarDeclInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tVarDeclInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tVarDeclInfo.c	(revision 374)
@@ -0,0 +1,228 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * sizeIsExpr       char_t*          ATTR_sizeIsExpr 
+ * declType         int8_t           ATTR_declType   
+ * place            int8_t           ATTR_place      
+ * offset           uint32_t         ATTR_offset     
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cTypeInfo_getNameLength( );
+ *   uint32_t       cTypeInfo_getSize( );
+ *   int8_t         cTypeInfo_getKind( );
+ *   uint32_t       cTypeInfo_getNType( );
+ *   ER             cTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cTypeInfo_getNMember( );
+ *   ER             cTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [ref_desc]
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_refer_to_descriptor();
+ *      Descriptor( nTECSInfo_sTypeInfo ) cTypeInfo_ref_desc()      (same as above; abbreviated version);
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tVarDeclInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eVarDeclInfo
+ * entry port: eVarDeclInfo
+ * signature:  nTECSInfo_sVarDeclInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eVarDeclInfo_getName
+ * name:         eVarDeclInfo_getName
+ * global_name:  nTECSInfo_tVarDeclInfo_eVarDeclInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eVarDeclInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eVarDeclInfo_getNameLength
+ * name:         eVarDeclInfo_getNameLength
+ * global_name:  nTECSInfo_tVarDeclInfo_eVarDeclInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eVarDeclInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eVarDeclInfo_getLocationInfo
+ * name:         eVarDeclInfo_getLocationInfo
+ * global_name:  nTECSInfo_tVarDeclInfo_eVarDeclInfo_getLocationInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eVarDeclInfo_getLocationInfo(CELLIDX idx, uint32_t* offset, int8_t* place)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *offset = ATTR_offset;
+  *place  = ATTR_place;
+}
+
+/* #[<ENTRY_FUNC>]# eVarDeclInfo_getTypeInfo
+ * name:         eVarDeclInfo_getTypeInfo
+ * global_name:  nTECSInfo_tVarDeclInfo_eVarDeclInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eVarDeclInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  *desc = cTypeInfo_refer_to_descriptor();
+}
+
+/* #[<ENTRY_FUNC>]# eVarDeclInfo_getSizeIsExpr
+ * name:         eVarDeclInfo_getSizeIsExpr
+ * global_name:  nTECSInfo_tVarDeclInfo_eVarDeclInfo_getSizeIsExpr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eVarDeclInfo_getSizeIsExpr(CELLIDX idx, char_t* expr_str, int32_t max_len)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  strncpy( expr_str, ATTR_sizeIsExpr, max_len - 1 );
+  expr_str[ max_len - 1 ] = '\0';
+}
+
+/* #[<ENTRY_FUNC>]# eVarDeclInfo_getSizeIs
+ * name:         eVarDeclInfo_getSizeIs
+ * global_name:  nTECSInfo_tVarDeclInfo_eVarDeclInfo_getSizeIs
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eVarDeclInfo_getSizeIs(CELLIDX idx, uint32_t* size, const void* p_cb)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = E_NOSPT;
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tVoidTypeInfo.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tVoidTypeInfo.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/nTECSInfo_tVoidTypeInfo.c	(revision 374)
@@ -0,0 +1,252 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * name             char_t*          ATTR_name       
+ * typeKind         int8_t           ATTR_typeKind   
+ * size             uint32_t         ATTR_size       
+ * b_const          bool_t           ATTR_b_const    
+ * b_volatile       bool_t           ATTR_b_volatile 
+ *
+ * #[</PREAMBLE>]# */
+
+/* Put prototype declaration and/or variale definition here #_PAC_# */
+#include <string.h>
+#include "nTECSInfo_tVoidTypeInfo_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* entry port function #_TEPF_# */
+/* #[<ENTRY_PORT>]# eTypeInfo
+ * entry port: eTypeInfo
+ * signature:  nTECSInfo_sTypeInfo
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getName
+ * name:         eTypeInfo_getName
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getName(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	name[ max_len - 1 ] = '\0';
+	strncpy( name, ATTR_name, max_len );
+  if( name[ max_len - 1 ] ){
+      name[ max_len - 1 ] = '\0';
+      ercd = E_NOMEM;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNameLength
+ * name:         eTypeInfo_getNameLength
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getNameLength
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint16_t
+eTypeInfo_getNameLength(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+	return strlen( ATTR_name ) + 1;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getSize
+ * name:         eTypeInfo_getSize
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getSize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getSize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return ATTR_size;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getKind
+ * name:         eTypeInfo_getKind
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getKind
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int8_t
+eTypeInfo_getKind(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return ATTR_typeKind;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNType
+ * name:         eTypeInfo_getNType
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getNType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNType(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return 0;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getTypeInfo
+ * name:         eTypeInfo_getTypeInfo
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getTypeInfo(CELLIDX idx, Descriptor( nTECSInfo_sTypeInfo )* desc)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* Write error processing code here */
+	} /* end if VALID_IDX(idx) */
+
+	/* Put statements here #_TEFB_# */
+  return E_NOEXS;
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getNMember
+ * name:         eTypeInfo_getNMember
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getNMember
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+uint32_t
+eTypeInfo_getNMember(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+}
+
+/* #[<ENTRY_FUNC>]# eTypeInfo_getMemberInfo
+ * name:         eTypeInfo_getMemberInfo
+ * global_name:  nTECSInfo_tVoidTypeInfo_eTypeInfo_getMemberInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eTypeInfo_getMemberInfo(CELLIDX idx, uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/tTECSInfoAccessor.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/tTECSInfoAccessor.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TECSInfo/tTECSInfoAccessor.c	(revision 374)
@@ -0,0 +1,1613 @@
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * NAME_LEN         int16_t          ATTR_NAME_LEN   
+ * name             char_t*          VAR_name        
+ * name2            char_t*          VAR_name2       
+ * selectedCbp      int8_t*          VAR_selectedCbp 
+ * selectedInibp    int8_t*          VAR_selectedInibp
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cTECSInfo signature: nTECSInfo_sTECSInfo context:task
+ *   ER             cTECSInfo_findNamespace( const char_t* namespace_path, Descriptor( nTECSInfo_sNamespaceInfo )* NSdesc );
+ *   ER             cTECSInfo_findRegion( const char_t* namespace_path, Descriptor( nTECSInfo_sRegionInfo )* RGNdesc );
+ *   ER             cTECSInfo_findSignature( const char_t* namespace_path, Descriptor( nTECSInfo_sSignatureInfo )* SIGdesc );
+ *   ER             cTECSInfo_findCelltype( const char_t* namespace_path, Descriptor( nTECSInfo_sCelltypeInfo )* CTdesc );
+ *   ER             cTECSInfo_findCell( const char_t* namespace_path, Descriptor( nTECSInfo_sCellInfo )* CELLdesc );
+ * call port: cNSInfo signature: nTECSInfo_sNamespaceInfo context:task optional:true
+ *   bool_t     is_cNSInfo_joined()                     check if joined
+ *   ER             cNSInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cNSInfo_getNameLength( );
+ *   uint32_t       cNSInfo_getNNamespace( );
+ *   ER             cNSInfo_getNamespaceInfo( uint32_t ith, Descriptor( nTECSInfo_sNamespaceInfo )* des );
+ *   uint32_t       cNSInfo_getNSignature( );
+ *   ER             cNSInfo_getSignatureInfo( uint32_t ith, Descriptor( nTECSInfo_sSignatureInfo )* des );
+ *   uint32_t       cNSInfo_getNCelltype( );
+ *   ER             cNSInfo_getCelltypeInfo( uint32_t ith, Descriptor( nTECSInfo_sCelltypeInfo )* des );
+ *   [dynamic, optional]
+ *      void           cNSInfo_set_descriptor( Descriptor( nTECSInfo_sNamespaceInfo ) desc );
+ *      void           cNSInfo_unjoin(  );
+ * call port: cCelltypeInfo signature: nTECSInfo_sCelltypeInfo context:task optional:true
+ *   bool_t     is_cCelltypeInfo_joined()                     check if joined
+ *   ER             cCelltypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCelltypeInfo_getNameLength( );
+ *   uint32_t       cCelltypeInfo_getNAttr( );
+ *   ER             cCelltypeInfo_getAttrInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNVar( );
+ *   ER             cCelltypeInfo_getVarInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNCall( );
+ *   ER             cCelltypeInfo_getCallInfo( uint32_t ith, Descriptor( nTECSInfo_sCallInfo )* desc );
+ *   uint32_t       cCelltypeInfo_getNEntry( );
+ *   ER             cCelltypeInfo_getEntryInfo( uint32_t ith, Descriptor( nTECSInfo_sEntryInfo )* desc );
+ *   bool_t         cCelltypeInfo_isSingleton( );
+ *   bool_t         cCelltypeInfo_isIDX_is_ID( );
+ *   uint32_t       cCelltypeInfo_sizeOfCB( );
+ *   uint32_t       cCelltypeInfo_sizeOfINIB( );
+ *   [dynamic, optional]
+ *      void           cCelltypeInfo_set_descriptor( Descriptor( nTECSInfo_sCelltypeInfo ) desc );
+ *      void           cCelltypeInfo_unjoin(  );
+ * call port: cSignatureInfo signature: nTECSInfo_sSignatureInfo context:task optional:true
+ *   bool_t     is_cSignatureInfo_joined()                     check if joined
+ *   ER             cSignatureInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cSignatureInfo_getNameLength( );
+ *   uint32_t       cSignatureInfo_getNFunction( );
+ *   ER             cSignatureInfo_getFunctionInfo( uint32_t ith, Descriptor( nTECSInfo_sFunctionInfo )* desc );
+ *   [dynamic, optional]
+ *      void           cSignatureInfo_set_descriptor( Descriptor( nTECSInfo_sSignatureInfo ) desc );
+ *      void           cSignatureInfo_unjoin(  );
+ * call port: cFunctionInfo signature: nTECSInfo_sFunctionInfo context:task optional:true
+ *   bool_t     is_cFunctionInfo_joined()                     check if joined
+ *   ER             cFunctionInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cFunctionInfo_getNameLength( );
+ *   void           cFunctionInfo_getReturnTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cFunctionInfo_getNParam( );
+ *   ER             cFunctionInfo_getParamInfo( uint32_t ith, Descriptor( nTECSInfo_sParamInfo )* param );
+ *   [dynamic, optional]
+ *      void           cFunctionInfo_set_descriptor( Descriptor( nTECSInfo_sFunctionInfo ) desc );
+ *      void           cFunctionInfo_unjoin(  );
+ * call port: cParamInfo signature: nTECSInfo_sParamInfo context:task optional:true
+ *   bool_t     is_cParamInfo_joined()                     check if joined
+ *   ER             cParamInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cParamInfo_getNameLength( );
+ *   ER             cParamInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   ER             cParamInfo_getDir( int8_t* dir );
+ *   [dynamic, optional]
+ *      void           cParamInfo_set_descriptor( Descriptor( nTECSInfo_sParamInfo ) desc );
+ *      void           cParamInfo_unjoin(  );
+ * call port: cCallInfo signature: nTECSInfo_sCallInfo context:task optional:true
+ *   bool_t     is_cCallInfo_joined()                     check if joined
+ *   ER             cCallInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCallInfo_getNameLength( );
+ *   void           cCallInfo_getSignatureInfo( Descriptor( nTECSInfo_sSignatureInfo )* desc );
+ *   uint32_t       cCallInfo_getArraySize( );
+ *   void           cCallInfo_getSpecifierInfo( bool_t* b_optional, bool_t* b_dynamic, bool_t* b_ref_desc, bool_t* b_omit );
+ *   void           cCallInfo_getInternalInfo( bool_t* b_allocator_port, bool_t* b_require_port );
+ *   void           cCallInfo_getLocationInfo( uint32_t* offset, int8_t* place );
+ *   void           cCallInfo_getOptimizeInfo( bool_t* b_VMT_useless, bool_t* b_skelton_useless, bool_t* b_cell_unique );
+ *   [dynamic, optional]
+ *      void           cCallInfo_set_descriptor( Descriptor( nTECSInfo_sCallInfo ) desc );
+ *      void           cCallInfo_unjoin(  );
+ * call port: cEntryInfo signature: nTECSInfo_sEntryInfo context:task optional:true
+ *   bool_t     is_cEntryInfo_joined()                     check if joined
+ *   ER             cEntryInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cEntryInfo_getNameLength( );
+ *   void           cEntryInfo_getSignatureInfo( Descriptor( nTECSInfo_sSignatureInfo )* desc );
+ *   uint32_t       cEntryInfo_getArraySize( );
+ *   bool_t         cEntryInfo_isInline( );
+ *   [dynamic, optional]
+ *      void           cEntryInfo_set_descriptor( Descriptor( nTECSInfo_sEntryInfo ) desc );
+ *      void           cEntryInfo_unjoin(  );
+ * call port: cAttrInfo signature: nTECSInfo_sVarDeclInfo context:task optional:true
+ *   bool_t     is_cAttrInfo_joined()                     check if joined
+ *   ER             cAttrInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cAttrInfo_getNameLength( );
+ *   void           cAttrInfo_getLocationInfo( uint32_t* offset, int8_t* place );
+ *   void           cAttrInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   void           cAttrInfo_getSizeIsExpr( char_t* expr_str, int32_t max_len );
+ *   ER             cAttrInfo_getSizeIs( uint32_t* size, const void* p_cb );
+ *   [dynamic, optional]
+ *      void           cAttrInfo_set_descriptor( Descriptor( nTECSInfo_sVarDeclInfo ) desc );
+ *      void           cAttrInfo_unjoin(  );
+ * call port: cVarInfo signature: nTECSInfo_sVarDeclInfo context:task optional:true
+ *   bool_t     is_cVarInfo_joined()                     check if joined
+ *   ER             cVarInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cVarInfo_getNameLength( );
+ *   void           cVarInfo_getLocationInfo( uint32_t* offset, int8_t* place );
+ *   void           cVarInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   void           cVarInfo_getSizeIsExpr( char_t* expr_str, int32_t max_len );
+ *   ER             cVarInfo_getSizeIs( uint32_t* size, const void* p_cb );
+ *   [dynamic, optional]
+ *      void           cVarInfo_set_descriptor( Descriptor( nTECSInfo_sVarDeclInfo ) desc );
+ *      void           cVarInfo_unjoin(  );
+ * call port: cTypeInfo signature: nTECSInfo_sTypeInfo context:task optional:true
+ *   bool_t     is_cTypeInfo_joined()                     check if joined
+ *   ER             cTypeInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cTypeInfo_getNameLength( );
+ *   uint32_t       cTypeInfo_getSize( );
+ *   int8_t         cTypeInfo_getKind( );
+ *   uint32_t       cTypeInfo_getNType( );
+ *   ER             cTypeInfo_getTypeInfo( Descriptor( nTECSInfo_sTypeInfo )* desc );
+ *   uint32_t       cTypeInfo_getNMember( );
+ *   ER             cTypeInfo_getMemberInfo( uint32_t ith, Descriptor( nTECSInfo_sVarDeclInfo )* desc );
+ *   [dynamic, optional]
+ *      void           cTypeInfo_set_descriptor( Descriptor( nTECSInfo_sTypeInfo ) desc );
+ *      void           cTypeInfo_unjoin(  );
+ * call port: cRegionInfo signature: nTECSInfo_sRegionInfo context:task optional:true
+ *   bool_t     is_cRegionInfo_joined()                     check if joined
+ *   ER             cRegionInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cRegionInfo_getNameLength( );
+ *   uint32_t       cRegionInfo_getNCell( );
+ *   ER             cRegionInfo_getCellInfo( uint32_t ith, Descriptor( nTECSInfo_sCellInfo )* des );
+ *   uint32_t       cRegionInfo_getNRegion( );
+ *   ER             cRegionInfo_getRegionInfo( uint32_t ith, Descriptor( nTECSInfo_sRegionInfo )* des );
+ *   [dynamic, optional]
+ *      void           cRegionInfo_set_descriptor( Descriptor( nTECSInfo_sRegionInfo ) desc );
+ *      void           cRegionInfo_unjoin(  );
+ * call port: cCellInfo signature: nTECSInfo_sCellInfo context:task optional:true
+ *   bool_t     is_cCellInfo_joined()                     check if joined
+ *   ER             cCellInfo_getName( char_t* name, int_t max_len );
+ *   uint16_t       cCellInfo_getNameLength( );
+ *   void           cCellInfo_getCelltypeInfo( Descriptor( nTECSInfo_sCelltypeInfo )* desc );
+ *   void           cCellInfo_getCBP( void** cbp );
+ *   void           cCellInfo_getINIBP( void** inibp );
+ *   [dynamic, optional]
+ *      void           cCellInfo_set_descriptor( Descriptor( nTECSInfo_sCellInfo ) desc );
+ *      void           cCellInfo_unjoin(  );
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include "tTECSInfoAccessor_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+static void
+getSelectedTypeValue( CELLCB *p_cellcb, void *ptr, char_t *buf, int_t max_len );
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eSelector
+ * entry port: eSelector
+ * signature:  sAccessor
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eSelector_selectNamespaceInfoByName
+ * name:         eSelector_selectNamespaceInfoByName
+ * global_name:  tTECSInfoAccessor_eSelector_selectNamespaceInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectNamespaceInfoByName(CELLIDX idx, const char_t* namespacePath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sNamespaceInfo ) NSdesc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = cTECSInfo_findNamespace( namespacePath, &NSdesc );
+  if( ercd == E_OK ){
+      cNSInfo_set_descriptor( NSdesc );
+  }
+  else {
+      cNSInfo_unjoin(  );
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCelltypeInfoByName
+ * name:         eSelector_selectCelltypeInfoByName
+ * global_name:  tTECSInfoAccessor_eSelector_selectCelltypeInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCelltypeInfoByName(CELLIDX idx, const char_t* namespacePath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sCelltypeInfo ) CTdesc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = cTECSInfo_findCelltype( namespacePath, &CTdesc );
+  if( ercd == E_OK ){
+      cCelltypeInfo_set_descriptor( CTdesc );
+  }
+  else {
+      cCelltypeInfo_unjoin(  );
+  }
+  
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureInfoByName
+ * name:         eSelector_selectSignatureInfoByName
+ * global_name:  tTECSInfoAccessor_eSelector_selectSignatureInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureInfoByName(CELLIDX idx, const char_t* namespacePath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sSignatureInfo ) SIGdesc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = cTECSInfo_findSignature( namespacePath, &SIGdesc );
+  if( ercd == E_OK ){
+      cSignatureInfo_set_descriptor( SIGdesc );
+  }
+  else {
+      cSignatureInfo_unjoin(  );
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectRegionInfoByName
+ * name:         eSelector_selectRegionInfoByName
+ * global_name:  tTECSInfoAccessor_eSelector_selectRegionInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectRegionInfoByName(CELLIDX idx, const char_t* regionPath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sRegionInfo ) RGNdesc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = cTECSInfo_findRegion( regionPath, &RGNdesc );
+  if( ercd == E_OK ){
+      cRegionInfo_set_descriptor( RGNdesc );
+  }
+  else {
+      cRegionInfo_unjoin(  );
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCellInfoByName
+ * name:         eSelector_selectCellInfoByName
+ * global_name:  tTECSInfoAccessor_eSelector_selectCellInfoByName
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCellInfoByName(CELLIDX idx, const char_t* cellPath)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sCellInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd = cTECSInfo_findCell( cellPath, &desc );
+  if( ercd == E_OK ){
+      cCellInfo_set_descriptor( desc );
+  }
+  else {
+      cCellInfo_unjoin(  );
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedNamespaceInfo
+ * name:         eSelector_getSelectedNamespaceInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedNamespaceInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedNamespaceInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_namespace, int_t* num_celltype, int_t* num_signature)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cNSInfo_joined() ){
+      cNSInfo_getName( name, max_len );
+      *num_namespace = cNSInfo_getNNamespace( );
+      *num_signature = cNSInfo_getNSignature( );
+      *num_celltype  = cNSInfo_getNCelltype( );
+  }
+  else {
+      ercd = E_OBJ;      // cNSInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCelltypeInfo
+ * name:         eSelector_selectCelltypeInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectCelltypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCelltypeInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sCelltypeInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  cCelltypeInfo_unjoin(  );
+  if( is_cNSInfo_joined() ){
+      if( 0 <= ith && ith < cNSInfo_getNCelltype() ){
+          cNSInfo_getCelltypeInfo( ith, &desc );
+          cCelltypeInfo_set_descriptor( desc );
+      }
+      else{
+          ercd = E_PAR;  // index out of range
+      }
+  }
+  else{
+      ercd = E_OBJ;      // cNSInfo not joined
+  }
+
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureInfo
+ * name:         eSelector_selectSignatureInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectSignatureInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sSignatureInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  cSignatureInfo_unjoin(  );
+  if( is_cNSInfo_joined() ){
+      if( 0 <= ith && ith < cNSInfo_getNSignature( ) ){
+          cNSInfo_getSignatureInfo( ith, &desc );
+          cSignatureInfo_set_descriptor( desc );
+      }
+      else{
+          ercd = E_PAR;  // index out of range
+      }
+  }
+  else{
+      ercd = E_OBJ;      // cNSInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCelltypeInfo
+ * name:         eSelector_getSelectedCelltypeInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedCelltypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCelltypeInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_attr, int_t* num_var, int_t* num_call, int_t* num_entry)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCelltypeInfo_joined() ){
+      cCelltypeInfo_getName( name, max_len );
+      *num_attr  = cCelltypeInfo_getNAttr( );
+      *num_var   = cCelltypeInfo_getNVar( );
+      *num_call  = cCelltypeInfo_getNCall( );
+      *num_entry = cCelltypeInfo_getNEntry( );
+  }
+  else {
+      ercd = E_OBJ;      // cCelltypeInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCallInfo
+ * name:         eSelector_selectCallInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectCallInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCallInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sCallInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  cCallInfo_unjoin(  );
+  if( is_cCelltypeInfo_joined() ){
+      if( 0 <= ith && ith < cCelltypeInfo_getNCall( ) ){
+          cCelltypeInfo_getCallInfo( ith, &desc );
+          cCallInfo_set_descriptor( desc );
+      }
+      else{
+          ercd = E_PAR;  // index out of range
+      }
+  }
+  else{
+      ercd = E_OBJ;      // cCelltypeInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectEntryInfo
+ * name:         eSelector_selectEntryInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectEntryInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectEntryInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sEntryInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  cEntryInfo_unjoin(  );
+  if( is_cCelltypeInfo_joined() ){
+      if( 0 <= ith && ith < cCelltypeInfo_getNEntry( ) ){
+          cCelltypeInfo_getEntryInfo( ith, &desc );
+          cEntryInfo_set_descriptor( desc );
+      }
+      else{
+          ercd = E_PAR;  // index out of range
+      }
+  }
+  else{
+      ercd = E_OBJ;      // cCelltypeInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectAttrInfo
+ * name:         eSelector_selectAttrInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectAttrInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectAttrInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sVarDeclInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  cAttrInfo_unjoin(  );
+  if( is_cCelltypeInfo_joined() ){
+      if( 0 <= ith && ith < cCelltypeInfo_getNAttr( ) ){
+          cCelltypeInfo_getAttrInfo( ith, &desc );
+          cAttrInfo_set_descriptor( desc );
+      }
+      else{
+          ercd = E_PAR;  // index out of range
+      }
+  }
+  else{
+      ercd = E_OBJ;      // cCelltypeInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectVarInfo
+ * name:         eSelector_selectVarInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectVarInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectVarInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sVarDeclInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  cVarInfo_unjoin(  );
+  if( is_cCelltypeInfo_joined() ){
+      if( 0 <= ith && ith < cCelltypeInfo_getNVar( ) ){
+          cCelltypeInfo_getVarInfo( ith, &desc );
+          cVarInfo_set_descriptor( desc );
+      }
+      else{
+          ercd = E_PAR;  // index out of range
+      }
+  }
+  else{
+      ercd = E_OBJ;      // cCelltypeInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedAttrInfo
+ * name:         eSelector_getSelectedAttrInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedAttrInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedAttrInfo(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cAttrInfo_joined() ){
+      cAttrInfo_getName( name, max_len );
+  }
+  else{
+      ercd = E_OBJ;      // cAttrInfo not joined
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSizeIsExprOfAttr
+ * name:         eSelector_getSizeIsExprOfAttr
+ * global_name:  tTECSInfoAccessor_eSelector_getSizeIsExprOfAttr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSizeIsExprOfAttr(CELLIDX idx, char_t* expr_str, int32_t max_len)
+{
+	CELLCB	*p_cellcb;
+  ER     ercd = E_OK;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cAttrInfo_joined() ){
+      cAttrInfo_getSizeIsExpr( expr_str, max_len );
+  }
+  else{
+      ercd = E_OBJ;      // cAttrInfo not joined
+  }
+  return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfAttr
+ * name:         eSelector_selectTypeInfoOfAttr
+ * global_name:  tTECSInfoAccessor_eSelector_selectTypeInfoOfAttr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfAttr(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sTypeInfo ) desc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cAttrInfo_joined() ){
+      cAttrInfo_getTypeInfo( &desc );
+      cTypeInfo_set_descriptor( desc );
+  }
+  else{
+      ercd = E_OBJ;      // cAttrInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedVarInfo
+ * name:         eSelector_getSelectedVarInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedVarInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedVarInfo(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cVarInfo_joined() ){
+      cVarInfo_getName( name, max_len );
+  }
+  else{
+      ercd = E_OBJ;      // cVarInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSizeIsExprOfVar
+ * name:         eSelector_getSizeIsExprOfVar
+ * global_name:  tTECSInfoAccessor_eSelector_getSizeIsExprOfVar
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSizeIsExprOfVar(CELLIDX idx, char_t* expr_str, int32_t max_len)
+{
+	CELLCB	*p_cellcb;
+  ER     ercd = E_OK;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  printf( "eSelector_getSizeIsExprOfVar not supported\n" );
+
+  return ercd;
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfVar
+ * name:         eSelector_selectTypeInfoOfVar
+ * global_name:  tTECSInfoAccessor_eSelector_selectTypeInfoOfVar
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfVar(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sTypeInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cVarInfo_joined() ){
+      cVarInfo_getTypeInfo( &desc );
+      cTypeInfo_set_descriptor( desc );
+  }
+  else{
+      ercd = E_OBJ;      // cVarInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallInfo
+ * name:         eSelector_getSelectedCallInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedCallInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* array_size)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+    if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCallInfo_joined() ){
+      cCallInfo_getName( name, max_len );
+      *array_size = cCallInfo_getArraySize();
+  }
+  else{
+      ercd = E_OBJ;      // cCallInfo not joined
+  }
+  return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureOfCall
+ * name:         eSelector_selectSignatureOfCall
+ * global_name:  tTECSInfoAccessor_eSelector_selectSignatureOfCall
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureOfCall(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sSignatureInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCallInfo_joined() ){
+      cCallInfo_getSignatureInfo( &desc );
+      cSignatureInfo_set_descriptor( desc );
+  }
+  else {
+      ercd = E_OBJ;      // cCallInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallSpecifierInfo
+ * name:         eSelector_getSelectedCallSpecifierInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedCallSpecifierInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallSpecifierInfo(CELLIDX idx, bool_t* b_optional, bool_t* b_dynamic, bool_t* b_ref_desc, bool_t* b_omit)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCallInfo_joined() ){
+      cCallInfo_getSpecifierInfo( b_optional, b_dynamic, b_ref_desc, b_omit );
+  }
+  else {
+      ercd = E_OBJ;      // cCallInfo not joined
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallInternalInfo
+ * name:         eSelector_getSelectedCallInternalInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedCallInternalInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallInternalInfo(CELLIDX idx, bool_t* b_allocator_port, bool_t* b_require_port)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCallInfo_joined() ){
+      cCallInfo_getInternalInfo( b_allocator_port, b_require_port );
+  }
+  else {
+      ercd = E_OBJ;      // cCallInfo not joined
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallLocationInfo
+ * name:         eSelector_getSelectedCallLocationInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedCallLocationInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallLocationInfo(CELLIDX idx, uint32_t* offset, int8_t* place)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCallInfo_joined() ){
+      cCallInfo_getLocationInfo( offset, place );
+  }
+  else {
+      ercd = E_OBJ;      // cCallInfo not joined
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCallOptimizeInfo
+ * name:         eSelector_getSelectedCallOptimizeInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedCallOptimizeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCallOptimizeInfo(CELLIDX idx, bool_t* b_VMT_useless, bool_t* b_skelton_useless, bool_t* b_cell_unique)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCallInfo_joined() ){
+      cCallInfo_getOptimizeInfo( b_VMT_useless, b_skelton_useless, b_cell_unique );
+  }
+  else {
+      ercd = E_OBJ;      // cCallInfo not joined
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedEntryInfo
+ * name:         eSelector_getSelectedEntryInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedEntryInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedEntryInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* array_size)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cEntryInfo_joined() ){
+      cEntryInfo_getName( name, max_len );
+      *array_size = cEntryInfo_getArraySize();
+  }
+  else{
+      ercd = E_OBJ;      // cEntryInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectSignatureOfEntry
+ * name:         eSelector_selectSignatureOfEntry
+ * global_name:  tTECSInfoAccessor_eSelector_selectSignatureOfEntry
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectSignatureOfEntry(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sSignatureInfo ) desc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cEntryInfo_joined() ){
+      cEntryInfo_getSignatureInfo( &desc );
+      cSignatureInfo_set_descriptor( desc );
+  }
+  else {
+      ercd = E_OBJ;      // cEntryInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedEntryInlineInfo
+ * name:         eSelector_getSelectedEntryInlineInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedEntryInlineInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedEntryInlineInfo(CELLIDX idx, bool_t* b_inline)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cEntryInfo_joined() ){
+      *b_inline = cEntryInfo_isInline( );
+  }
+  else {
+      ercd = E_OBJ;      // cEntryInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedSignatureInfo
+ * name:         eSelector_getSelectedSignatureInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedSignatureInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedSignatureInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_function)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cSignatureInfo_joined() ){
+      cSignatureInfo_getName( name, max_len );
+      *num_function = cSignatureInfo_getNFunction( );
+  }
+  else {
+      ercd = E_OBJ;      // cSignatureInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectFunctionInfoByIndex
+ * name:         eSelector_selectFunctionInfoByIndex
+ * global_name:  tTECSInfoAccessor_eSelector_selectFunctionInfoByIndex
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectFunctionInfoByIndex(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sFunctionInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cSignatureInfo_joined() ){
+      if( 0 <= ith && ith < cSignatureInfo_getNFunction( ) ){
+          cSignatureInfo_getFunctionInfo( ith, &desc );
+          cFunctionInfo_set_descriptor( desc );
+      }
+      else {
+      }
+  }
+  else {
+      ercd = E_OBJ;      // cSignatureInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedFunctionInfo
+ * name:         eSelector_getSelectedFunctionInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedFunctionInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedFunctionInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_args)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cFunctionInfo_joined() ){
+      cFunctionInfo_getName( name, max_len );
+      *num_args = cFunctionInfo_getNParam( );
+  }
+  else {
+      ercd = E_OBJ;      // cFunctionInfo not joined
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfReturn
+ * name:         eSelector_selectTypeInfoOfReturn
+ * global_name:  tTECSInfoAccessor_eSelector_selectTypeInfoOfReturn
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfReturn(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sTypeInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cFunctionInfo_joined() ){
+      cFunctionInfo_getReturnTypeInfo( &desc );
+      cTypeInfo_set_descriptor( desc );
+  }
+  else {
+      ercd = E_OBJ;      // cFunctionInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedParamInfo
+ * name:         eSelector_getSelectedParamInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedParamInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedParamInfo(CELLIDX idx, char_t* name, int_t max_len, int8_t* dir)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cParamInfo_joined() ){
+      cParamInfo_getName( name, max_len );
+      cParamInfo_getDir( dir );
+  }
+  else {
+      ercd = E_OBJ;      // cParamInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectParamInfo
+ * name:         eSelector_selectParamInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectParamInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectParamInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sParamInfo ) desc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cFunctionInfo_joined() ){
+      if( 0 <= ith && ith < cFunctionInfo_getNParam() ){
+          cFunctionInfo_getParamInfo( ith, &desc );
+          cParamInfo_set_descriptor( desc );
+      }
+      else{
+          ercd = E_PAR;  // index out of range
+      }
+  }
+  else {
+      ercd = E_OBJ;      // cFunctionInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfParam
+ * name:         eSelector_selectTypeInfoOfParam
+ * global_name:  tTECSInfoAccessor_eSelector_selectTypeInfoOfParam
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfParam(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sTypeInfo ) desc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cParamInfo_joined() ){
+      cParamInfo_getTypeInfo( &desc );
+      cTypeInfo_set_descriptor( desc );
+  }
+  else {
+      ercd = E_OBJ;      // cFunctionInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedTypeInfo
+ * name:         eSelector_getSelectedTypeInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedTypeInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedTypeInfo(CELLIDX idx, char_t* name, int_t max_len, int8_t* kind)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cTypeInfo_joined() ){
+      cTypeInfo_getName( name, max_len );
+      *kind = cTypeInfo_getKind( );
+  }
+  else {
+      ercd = E_OBJ;      // cTypeInfo not joined
+  }
+  return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectTypeInfoOfType
+ * name:         eSelector_selectTypeInfoOfType
+ * global_name:  tTECSInfoAccessor_eSelector_selectTypeInfoOfType
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectTypeInfoOfType(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sTypeInfo ) desc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cTypeInfo_joined() ){
+      cTypeInfo_getTypeInfo( &desc );
+      cTypeInfo_set_descriptor( desc );
+  }
+  else {
+      ercd = E_OBJ;      // cTypeInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedRegionInfo
+ * name:         eSelector_getSelectedRegionInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedRegionInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedRegionInfo(CELLIDX idx, char_t* name, int_t max_len, int_t* num_cell)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cRegionInfo_joined() ){
+      cRegionInfo_getName( name, max_len );
+      *num_cell = cRegionInfo_getNCell();
+  }
+  else {
+      ercd = E_OBJ;      // cNSInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCellInfo
+ * name:         eSelector_selectCellInfo
+ * global_name:  tTECSInfoAccessor_eSelector_selectCellInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCellInfo(CELLIDX idx, int_t ith)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sCellInfo ) desc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cRegionInfo_joined() ){
+      if( 0 <= ith && ith < cRegionInfo_getNCell() ){
+          cRegionInfo_getCellInfo( ith, &desc );
+          cCellInfo_set_descriptor( desc );
+      }
+      else {
+          ercd = E_PAR;
+      }
+  }
+  else {
+      ercd = E_OBJ;      // cNSInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getSelectedCellInfo
+ * name:         eSelector_getSelectedCellInfo
+ * global_name:  tTECSInfoAccessor_eSelector_getSelectedCellInfo
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getSelectedCellInfo(CELLIDX idx, char_t* name, int_t max_len)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCellInfo_joined() ){
+      cCellInfo_getName( name, max_len );
+  }
+  else {
+      ercd = E_OBJ;      // cNSInfo not joined
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_selectCelltypeInfoOfCell
+ * name:         eSelector_selectCelltypeInfoOfCell
+ * global_name:  tTECSInfoAccessor_eSelector_selectCelltypeInfoOfCell
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_selectCelltypeInfoOfCell(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+  Descriptor( nTECSInfo_sCelltypeInfo ) desc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCellInfo_joined() ){
+      cCellInfo_getCelltypeInfo( &desc );
+      cCelltypeInfo_set_descriptor( desc );
+  }
+  else {
+      ercd = E_OBJ;      // cNSInfo not joined
+  }
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getAttrValueInStr
+ * name:         eSelector_getAttrValueInStr
+ * global_name:  tTECSInfoAccessor_eSelector_getAttrValueInStr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getAttrValueInStr(CELLIDX idx, char_t* buf, int_t max_len)
+{
+	ER		  ercd = E_OK;
+	CELLCB	*p_cellcb;
+  uint32_t offset;
+  void     *base, *ptr;
+  int8_t   place;
+
+  Descriptor( nTECSInfo_sCelltypeInfo ) CTdesc;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( is_cCellInfo_joined() && is_cAttrInfo_joined() ){
+      cCellInfo_getCelltypeInfo( &CTdesc );
+      cCelltypeInfo_set_descriptor( CTdesc );
+      printf( "eSelector_getAttrValueInStr not supported\n" );
+      cAttrInfo_getLocationInfo( &offset, &place );
+      switch( place ){
+      case VARDECL_PLACE_CB:
+          cCellInfo_getCBP( &base );
+          break;
+      case VARDECL_PLACE_INIB:
+          cCellInfo_getINIBP( &base );
+          break;
+      default:
+          base = (void *)0;
+      };
+      if( base ){
+          ptr = base + offset;
+          eSelector_selectTypeInfoOfAttr(idx);
+          getSelectedTypeValue( p_cellcb, ptr, buf, max_len );
+      }
+      else {
+          strncpy( buf, "(OMITTED)", max_len );
+      }
+  }
+  else{
+      ercd = E_OBJ;
+  }
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getAttrSizeIsValue
+ * name:         eSelector_getAttrSizeIsValue
+ * global_name:  tTECSInfoAccessor_eSelector_getAttrSizeIsValue
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getAttrSizeIsValue(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  printf( "eSelector_getAttrSizeIsValue not supported\n" );
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getVarValueInStr
+ * name:         eSelector_getVarValueInStr
+ * global_name:  tTECSInfoAccessor_eSelector_getVarValueInStr
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getVarValueInStr(CELLIDX idx, char_t* buf, int_t max_len)
+{
+	ER        ercd = E_OK;
+	CELLCB    *p_cellcb;
+  int8_t    place;
+  void      *base, *ptr;
+  uint32_t  offset;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  cVarInfo_getLocationInfo( &offset, &place );
+  switch( place ){
+  case VARDECL_PLACE_CB:
+      cCellInfo_getCBP( &base );
+      break;
+  case VARDECL_PLACE_INIB:
+      cCellInfo_getINIBP( &base );
+      break;
+  default:
+      base = (void *)0;
+  };
+  if( base ){
+      ptr = base + offset;
+      eSelector_selectTypeInfoOfVar(idx);
+      getSelectedTypeValue( p_cellcb, ptr, buf, max_len );
+  }
+  else {
+      strncpy( buf, "(OMITTED)", max_len );
+  }
+  printf( "eSelector_getVarValueInStr not supported\n" );
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eSelector_getVarSizeIsValue
+ * name:         eSelector_getVarSizeIsValue
+ * global_name:  tTECSInfoAccessor_eSelector_getVarSizeIsValue
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+ER
+eSelector_getVarSizeIsValue(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  printf( "eSelector_getVarSizeIsValue not supported\n" );
+
+	return(ercd);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
+
+static void
+getSelectedTypeValue( CELLCB *p_cellcb, void *ptr, char_t *buf, int_t max_len )
+{
+    switch( cTypeInfo_getKind() ){
+    case TECSTypeKind_BoolType:
+        snprintf( buf, max_len, "%d", *(bool_t *)ptr );
+        break;
+    case TECSTypeKind_IntType:
+        switch( cTypeInfo_getSize() ){
+        case 8:
+            snprintf( buf, max_len, "%d", *(int8_t *)ptr );
+            break;
+        case 16:
+            snprintf( buf, max_len, "%d", *(int16_t *)ptr );
+            break;
+        case 32:
+            snprintf( buf, max_len, "%d", *(int32_t *)ptr );
+            break;
+        case 64:
+            snprintf( buf, max_len, "%lld", *(int64_t *)ptr );
+            break;
+        default:
+            snprintf( buf, max_len, "unknown int size(%d)", cTypeInfo_getSize() );
+        };
+    case TECSTypeKind_FloatType:
+        switch( cTypeInfo_getSize() ){
+        case 32:
+            snprintf( buf, max_len, "%g", *(float32_t *)ptr );
+            break;
+        case 64:
+            snprintf( buf, max_len, "%g", *(double64_t *)ptr );
+            break;
+        default:
+            snprintf( buf, max_len, "unknown double size(%d)", cTypeInfo_getSize() );
+        };
+    case TECSTypeKind_PtrType:
+        snprintf( buf, max_len, "%X", *(double64_t *)ptr );
+        break;
+    case TECSTypeKind_ArrayType:        break;
+    case TECSTypeKind_DefinedType:      break;
+    case TECSTypeKind_StructType:       break;
+    case TECSTypeKind_EnumType:         break;
+    case TECSTypeKind_VoidType:         break;
+    case TECSTypeKind_DescriptorType:   break;
+    default:                            break;
+    };
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/README-TLSF.txt
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/README-TLSF.txt	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/README-TLSF.txt	(revision 374)
@@ -0,0 +1,35 @@
+TLSF Malloc ã¢ã­ã±ã¼ã¿
+                                          2017.4.15
+                                          å¤§å±±
+1.æ¦è¦
+
+TLSF ã¯å¹çããããã©ã°ã¡ã³ããèµ·ãã«ããã¢ã­ã±ã¼ã¿ã§ãã OS éä¾å­ã«
+å®è£
+ããã¦ãããããçµè¾¼ã¿ã·ã¹ãã ã¸ã®å¿ç¨ã«é©ãã¦ãã¾ãããã®å®è£
+ã§ã¯
+æä»å¶å¾¡ãè¡ã£ã¦ãã¾ãããè¤æ°ã®ã¿ã¹ã¯ã§å
+±ç¨ããã«ã¯ãæä»å¶å¾¡ãè¡ãå¿
+
+è¦ãããã¾ãã
+
+2. å®è£
+ã«ã¤ãã¦
+
+1) TLSF ã¢ã­ã±ã¼ã¿ã®æ¬ä½ã¯ãTECS ã¸ã§ãã¬ã¼ã¿ããã±ã¼ã¸ã«ã¯å«ã¾ãã¦ãã¾ããã
+ä»¥ä¸ã«å
+¬éããã¦ãã TLSF ãå
+¥æããå¿
+è¦ãããã¾ãã
+ããã¯ GPL/LGPL ã©ã¤ã»ã³ã¹ã§å
+¬éããã¦ãã¾ãã
+  http://www.gii.upv.es/tlsf/main/docs
+
+2) TLSF ã«ã¯ãå¥ã«å®è£
+ãã MIT ã©ã¤ã»ã³ã¹ã§å
+¬éããã¦ãããã®ãããã¾ãã
+API ãè¥å¹²ç°ãªããããtTLSFMalloc_inline.h ãå°ãä¿®æ­£ããå¿
+è¦ãããã¾ãã
+  https://github.com/mattconte/tlsf
+
+3) ETã­ãã³ã³ç¨ããã±ã¼ã¸
+mruby-on-ev3rt+tecs_package (ev3rt) ã«ã¯ã1) ã® TLSF ãå«ã¾ãã¦ãã¾ãã
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/tTLSFMalloc.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/tTLSFMalloc.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/tTLSFMalloc.cdl	(revision 374)
@@ -0,0 +1,71 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+import( <sMalloc.cdl> );
+
+celltype tTLSFMalloc {
+    [inline]
+        entry  sMalloc  eMalloc;
+    attr {
+        /* memory pool size in bytes */
+        size_t  memoryPoolSize;
+    };
+    var {
+        /*
+         * ã¡ã¢ãªãã¼ã«
+         *
+         * size_is ã®å¼æ°ã«é¢ããè£è¶³èª¬æ
+         *  pool ã®åã uint64_t ã®ãã sizeof uint64_t (8) ã§å²ã£ã¦ãã
+         *  memoryPoolSize ã 8 ã®åæ°ã§ãªãå ´åãã¡ã¢ãªé åãä¸è¶³ããªããã +7 ãå ç®ãã¦ããé¤ãã
+         */
+        [size_is( (memoryPoolSize+7) / 8 )]
+            uint64_t   *pool;
+    };
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/tTLSFMalloc_inline.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/tTLSFMalloc_inline.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/TLSFMalloc/tTLSFMalloc_inline.h	(revision 374)
@@ -0,0 +1,167 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+#ifndef tTLSFMalloc__INLINE_H
+#define tTLSFMalloc__INLINE_H
+
+#include "tlsf.h"
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * memoryPoolSize   size_t           ATTR_memoryPoolSize
+ * pool             uint64_t*        VAR_pool        
+ *
+ * #[</PREAMBLE>]# */
+
+/* #[<ENTRY_PORT>]# eMalloc
+ * entry port: eMalloc
+ * signature:  sMalloc
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eMalloc_initializeMemoryPool
+ * name:         eMalloc_initializeMemoryPool
+ * global_name:  tTLSFMalloc_eMalloc_initializeMemoryPool
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline int
+eMalloc_initializeMemoryPool(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+	} /* end if VALID_IDX(idx) */
+
+  return init_memory_pool(ATTR_memoryPoolSize, VAR_pool);
+}
+
+/* #[<ENTRY_FUNC>]# eMalloc_calloc
+ * name:         eMalloc_calloc
+ * global_name:  tTLSFMalloc_eMalloc_calloc
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline void*
+eMalloc_calloc(CELLIDX idx, size_t nelem, size_t elem_size)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+	} /* end if VALID_IDX(idx) */
+
+  return calloc_ex( nelem, elem_size, VAR_pool);
+}
+
+/* #[<ENTRY_FUNC>]# eMalloc_malloc
+ * name:         eMalloc_malloc
+ * global_name:  tTLSFMalloc_eMalloc_malloc
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline void*
+eMalloc_malloc(CELLIDX idx, size_t size)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+	} /* end if VALID_IDX(idx) */
+
+  return malloc_ex(size, VAR_pool);
+
+}
+
+/* #[<ENTRY_FUNC>]# eMalloc_realloc
+ * name:         eMalloc_realloc
+ * global_name:  tTLSFMalloc_eMalloc_realloc
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline void*
+eMalloc_realloc(CELLIDX idx, const void* ptr, size_t new_size)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+	} /* end if VALID_IDX(idx) */
+
+  return realloc_ex((void *)ptr, new_size, VAR_pool);
+}
+
+/* #[<ENTRY_FUNC>]# eMalloc_free
+ * name:         eMalloc_free
+ * global_name:  tTLSFMalloc_eMalloc_free
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline void
+eMalloc_free(CELLIDX idx, const void* ptr)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+	} /* end if VALID_IDX(idx) */
+
+  return free_ex((void *)ptr, VAR_pool);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
+
+#endif /* tTLSFMalloc_INLINEH */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/README-mruby.txt
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/README-mruby.txt	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/README-mruby.txt	(revision 374)
@@ -0,0 +1,73 @@
+mruby
+                                              2017.4.17  æ°è¦
+                                              2017.11.4  
+                                              å¤§å±± åå¸
+
+â æ¦è¦
+
+mruby ãã£ã¬ã¯ããªã«ã¯ãçµè¾¼ã¿ç¨ mruby VM ã®ã»ã«ã¿ã¤ããããã³
+MrubyBridgePlugin ã«å¯¾å¿ããã¢ã¸ã¥ã¼ã«ãå«ã¾ãã¾ãï¼
+
+mruby V1.2.0 ã«å¯¾å¿ãã¦ãã¾ãï¼V1.1.0 ã§ããã«ããããã¨ã¯å¯è½ã§ãï¼
+
+ããã«ã¯ mruby ã®æ¬ä½ã¯å«ã¾ãã¾ããï¼ä»¥ä¸ãããã¦ã³ã­ã¼ãããå¿
+è¦ãããã¾ãï¼
+   http://forum.mruby.org/
+
+â TECS ã¸ã§ãã¬ã¼ã¿ V1.5 ã§ã®å¤æ´
+
+tMruby.cdl (ãã¹ï¼tecsgen/tecs/mruby/tMruby.cdl) ãæ°è¨­ããï¼
+ä»¥ä¸ãå¯è½ã«ããããã« tMruby ã composite ã«åè§£ããï¼
+ * mruby ã¹ã¯ãªããã®å¨æã¿ã¹ã¯å®è¡
+ * VM ãã¨ã«ç°ãªã TLSF ã¢ã­ã±ã¼ã¿ã³ã³ãã¼ãã³ããä½¿ç¨
+
+tMruby.cdl ã§ã¯ tMruby (ãã¼ã ã¹ãã¼ã¹ãã¹ï¼nMruby::tMruby) ã®å®è£
+ã
+æ°ããããä»ãå¨æã¿ã¹ã¯å®è¡ç¨ã® tMrubyCyclic (åï¼nMruby::tMrubyCyclic)
+ãæ°è¨­ããï¼tMruby ãåè§£ãããtMrubyVM ã»ã«ã¿ã¤ãã¨ããã®ã·ã°ããã£
+sMruby (sMruby.cdlå
+) ãæ°è¨­ããï¼
+
+tMruby.cdl ã«ç½®ãæãå¯è½ã ããä»¥ä¸ã®ç¹ã§ãã«ãç¨ Makefile ã®å¤æ´ãå¿
+è¦ï¼
+ * TLSF ããã tTLSFMalloc_inline.h ã¸ã®ãã¹ãè¿½å 
+ * TLSF ã®ãªãã¸ã§ã¯ãã®è¿½å  (mruby+TECS on EV3 ã«ã¯å®è£
+æ¸ã¿)
+
+ã¾ããä»¥ä¸ã®ç¹ã«çæããå¿
+è¦ãããï¼
+ * TLSF ã¯ãVM ãã¨ã« 1MB ãå²ãä»ãã 
+
+ãã®ãããååãªç©ºãã¡ã¢ãªãå¿
+è¦ã§ããï¼
+ãã®ãµã¤ãºã¯ VM ã»ã«ã®å®ç¾©ã§å¤æ´å¯è½ (å±æ§ memoryPoolSize)ï¼
+
+â  ã³ã³ãã¼ãã³ãæ¦è¦
+
+tMruby.cdl: (TECS ã¸ã§ãã¬ã¼ã¿ V1.5.0 ä»¥é)
+ celltype  tMrubyVM
+    VM ãå®è£
+ããããã®ã»ã«ã¿ã¤ãï¼ã¡ã¢ãªã¢ã­ã±ã¼ã¿ TLSFMalloc ãå«ã¾
+    ãªã. åãå£ eMrubyVM ã®ã·ã°ããã£ã¯ sMrubyï¼
+
+ composite tMruby
+    åãå£ eMrubyBody ã®ã·ã°ããã£ã sTaskBody ã¨ããï¼tTLSFMalloc ã
+    çµã¿å
+¥ã.
+
+ composite tMrubyCyclic
+    åãå£ eMrubyBody ã®ã·ã°ããã£ã sTaskBody ã¨ããï¼tTLSFMalloc ã
+    çµã¿å
+¥ã.
+    å¨æã¿ã¹ã¯èµ·åºãåæã¨ãã¦ããï¼
+    ä¸åç®ã®å¼åºãã§ã¯ mrb_open ããããªãã¸ã»ã«ãç»é²å¾ãmrb_run ãå¼
+    ã³åºãã¦ã¹ã¯ãªããå®è¡ãè¡ãï¼ã¹ã¯ãªããçµäºå¾ã« mrb_close ã¯å¼ã³
+    åºãããªãï¼
+    äºåç®ä»¥éã®å¼åºãã§ã¯ mrb_run ã®ã¿å¼ã³åºãããï¼
+    çµäºå¦ç mrb_close ãå¼ã³ã ãææ®µã¯æä¾ãã¦ããªãï¼çªç¶é»æºãåã
+    ãããã¨ãåæã¨ãã¦ããï¼ (å°ãªãã¨ãæåã®å®è£
+ã§ã¯)ï¼
+
+sMruby.cdlï¼
+ signature sMruby
+   åæåãå®è¡ãçµäºå¦çã«åè§£ããã·ã°ããã£
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/TECSPointer.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/TECSPointer.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/TECSPointer.h	(revision 374)
@@ -102,6 +102,6 @@
 	{																	\
 		if( sizeof( type ) > sizeof( mrb_int ) ){						\
-			if( val >= (((type)1) << (sizeof(mrb_int)*8-1))				\
-				|| val < -(((type)1) << (sizeof(mrb_int)*8-1)) )		\
+			if( val > TYPE ## _MAX				\
+				|| val < TYPE ## _MIN )		\
 				/* '=' unecessary for negative value	*/				\
 				/* ignore warning on int32_t */							\
@@ -126,5 +126,5 @@
 	{																	\
 		if( sizeof( type ) > sizeof( mrb_int ) ){						\
-			if( val >= (((type)1) << (sizeof(mrb_int)*8)))				\
+      if( val > TYPE ## _MAX )                        \
 				/* '=' unecessary for negative value	*/				\
 				/* ignore warning on int32_t */							\
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyBridge.txt
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyBridge.txt	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyBridge.txt	(revision 374)
@@ -0,0 +1,394 @@
+MrubyBridgePlugin ã«é¢ããã¡ã¢
+										2012å¹´11æ 7æ¥ãåçä½æ
+										2013å¹´ 5æ26æ¥ãè¦ç´ã
+                                                        å¤§å±±ãåå¸
+
+ãæ¦è¦ã
+
+MrubyBridgePlugin ã¯ãTECS CDL ã® signature è¨è¿°ã«åºã¥ããmruby ã¨ TECS 
+ã³ã³ãã¼ãã³ããããªãã¸ãããmruby ã® C è¨èªå®è£
+ã¯ã©ã¹ã§ãã TECS ã®ã»
+ã«ã¿ã¤ãã¨ãªãã³ã³ãã¼ãã³ããçæãããTECS ã®ã·ã°ããã£ãã©ã°ã¤ã³ã§ã
+ãã
+
+ãæ§é ã
+
+         +--------------------------+              +-------------------+
+         |     (ããªãã¸ã»ã«)         |              |    (ç®çã»ã«)      |
+         |                          |              |                   |
+mruby    | nMruby::tsSignatureBridge|  sSignature  |  tTargetCelltype  |
+ - - - > |       BridgeCell         |--------------|>   TargetCell     |
+         |                          |cTECS    eTest|                   |
+         | mruby ã¯ã©ã¹ï¼            |              |                   |
+         |  TECS::TSignatureBridge  |              |                   |
+         +--------------------------+              +-------------------+
+
+MrubyBridgePlugin ã¯ãmruby ãã TECS ã¸ããªãã¸ãããã»ã«ã¿ã¤ããçæ
+ãããmruby=>TECS ãããªãã¸ããã»ã«ã¯ããã®ã»ã«ã¿ã¤ãã®ã»ã«ã¨ãã¦ãã
+ã©ã°ã¤ã³ã®å©ç¨è
+ã CDL å
+ã«è¨­ç½®ããmruby ããæä½ãããã»ã«ãããªãã¡
+ç®çã»ã«ã«çµåããã
+
+ãã®ã»ã«ã¿ã¤ãã¯ãmruby ã®ã¯ã©ã¹ã®å®ç¾©ãè¡ããããªãã¸ã»ã«ã mruby ã®
+ã¤ã³ã¹ã¿ã³ã¹ã¨ãã¦åãæ±ããããã«ããmruby ã®ã¤ã³ã¹ã¿ã³ã¹ã¡ã½ããã®å¼
+ã³åºãã«å¿ãã¦ãç®çã»ã«ã®åãå£é¢æ°ãå¼ã³åºãåããæã¤ã
+
+ãç°¡åãªä½¿ç¨ä¾ã
+
+ç°¡åãªä½¿ç¨ä¾ã¯ãSimpleSample.cdl ããã³ SimpleSample.rb ã«ããã
+MrubyBrigePlugin ã¯ã·ã°ããã£ãã©ã°ã¤ã³ã§ãããã·ã°ããã£ãã©ã°ã¤ã³ã®
+ä½¿ç¨æ¹æ³ãçè§£ãã¦ããã°ããããã®ã½ã¼ã¹ãã¡ã¤ã«ã®ã³ã¡ã³ããåç
+§ããã
+ã¨ã§ãMrubyBrigePlugin ã®å¤§ããã®ä½¿ãæ¹ã¯çè§£ã§ããã¯ãã§ããã
+ä»¥ä¸ã®æ¹æ³ã§ããã«ãããã³å®è¡ã§ããã
+
+   % make                             # mruby æ¬ä½ã®ãã«ã (.a ãä½æ)
+   % cd MrubyBridge                   # MrubyBridge ã¸ç§»å
+   % make                             # ãã«ã
+   % ./mruby-Sample SimpleSample.rb   # å®è¡
+
+ãMakefile ã®æ§æã
+
+tecsgen ã«ããçæããã gen/Makefile.templ ã«å¯¾ããä»¥ä¸ã®å¤æ´ãå ããå¿
+è¦ãã
+ãã
+
+ã»gen/Makefile.temp ã¯ãä¸ã¤ä¸ã®ãã£ã¬ã¯ããªã¸ Makefile ã¨ããååã§ç½®
+  ãã°ãcygwin ãªã©ã® POSIX ç°å¢ã§è©¦é¨å®è¡ããå ´åã«ã¯ãç¡èª¿æ´ã§ä½¿ç¨ã§
+  ããããã«çæããã(ãã ã gnu make ãä½¿ç¨ãã)
+ã»tSysLog ãä½¿ãå ´åããªã­ã±ã¼ã¿ãã«ãªãã¸ã§ã¯ããè¿½å  (ä¸è¡åç
+§)
+   OTHER_OBJS = $(_TECS_OBJ_DIR)vasyslog.o
+
+ããã¼ã¿åã
+
+MrubyBridgePlugin ã¯ãä»¥ä¸ã® TECS ã®åãæ±ããã¨ãã§ãã (å¶éããã)ã
+ãã®å¶éã¯ãMrubyBridgePlugin ãé©ç¨ãããã¨ããã·ã°ããã£ã«å¯¾ãããã®ã§ããã
+ããä»¥å¤ã¸å¶éãããã¶ãã®ã§ã¯ãªãã
+
+ ã¹ã«ã©ã¼å			bool_t, char_t, intN_t, double64_t, float32_t
+									(N=8,16,32,64)
+					int, short, long, char (TECS éæ¨å¥¨ã®å)
+
+ ãã¤ã³ã¿å			bool_t*, char_t*, intN_t*, double64_t*, float32_t*
+					int*, short*, long*, char*
+					æ§é ä½åã¸ã®ãã¤ã³ã¿ï¼æ§é ä½åã¨åãå¶éããï¼
+
+                    ãããã¯ããã¤ã³ã¿ã®æãã¦ããå
+ã®å¤ãæ±ãããã®ã
+                    ã®ã§ããããã¤ã³ã¿å¤(ã¢ãã¬ã¹)ãæ¸¡ãããå ´åã«ã¯ã
+                    ããããä½¿ç¨ã§ããªããä»£ããã« intptr_t, uintptr_t 
+                    ãä½¿ç¨ããã
+
+ 					size_is, string æå®å­ãã/ãªãã®ããããæ±ããã
+					ãã ãæ§é ä½åã¸ã®ãã¤ã³ã¿ã« size_is æå®ãããã
+					ã®ã¯æ±ããªãã(ä»æ§æ¸ã«æè¨ããã¦ããªããæ§é ä½ã
+					ã¤ã³ã¿ã® string ã¯ãå
+ã
+ãµãã¼ããããªã)
+
+					string ã®é·ãæå®ããªãå ´åãin å¼æ°ã«å¯¾ãã¦ã®ã¿ç¨
+					ãããã¨ãã§ããã
+
+ æ§é ä½å			ã¡ã³ãã¯ãã¹ã«ã©ã¼åã§ãªãã¦ã¯ãªããªã
+
+ typedefå          ä¸è¨ã®ã¹ã«ã©ã¼åãæ§é ä½åããã¤ã³ã¿åã® typedef 
+                    ãããåãæ±ããã¨ãã§ãããå
+ã®åã¨ãã¦æ±ãããã
+					ãã®ãããã¤ã³ã¿åãæ§é ä½åã®å ´åãå
+ã®ååã«ãã
+					ããããæ±ãããã® mruby ã¯ã©ã¹ãæå®ããã
+
+ãå¯¾å¿ãã mruby ã®å(ã¯ã©ã¹)ã
+
+  bool_t			true ã¾ãã¯ falseã
+					mruby ã§ false ã¨è¦ãªããããã®(false ã¾ãã¯ nil) 
+					ã C ã® false ã¨ãã¦æ±ããmruby ã§ false ã¨è¦ãªã
+					ããªããã®ã C ã® true ã¨ãã¦æ±ããæ´æ°å¤ 0 ã¯ã
+					mruby ã§ã¯ false ã¨ã¯è¦ãªãããªãã
+  char_t			FIXNUM  (å¤ã¯ 0..255)		
+  schar_t			FIXNUM  (å¤ã¯ -128..127)		
+  uchar_t			FIXNUM  (å¤ã¯ 0..255)		
+  intN_t			FIXNUM
+  uintN_t			FIXNUM
+  double64_t		FLOAT (mruby ã® FLOAT ã double ã float ãã¯å®è£
+
+                          ã«ãã)
+  float32_t			FLOAT
+  int				FIXNUM
+  short				FIXNUM
+  long				FIXNUM
+  char				FIXNUM  (char_t ã¨åã)
+
+ã»TECS å°ç¨ã®ã¯ã©ã¹ãç¨ãããã®
+
+  bool_t*			TECS::BoolPointer
+  char_t*			TECS::CharPointer
+  uchar_t*			TECS::UCharPointer
+  schar_t*			TECS::SCharPointer
+  intN_t*			TECS::IntNPointer   N:8,16,32,64
+  uintN_t*			TECS::UIntNPointer  N:8,16,32,64
+  float32_t*		TECS::Float32Pointer
+  double64_t*		TECS::Double64Pointer
+  int*				TECS::IntPointer
+  short*			TECS::ShortPointer
+  long*				TECS::LongPointer
+  char*				TECS::CharPointer  (char_t* ã¨åã)
+
+  struct TAG		TECS:TECSStructTAG
+  struct TAG*		TECS:TECSStructTAG
+                    TAG ã®é¨åã¯ãæ§é ä½ã®ã¿ã°åã«ç½®ãæãããé¢æ°ã¸ã®
+                    å¼æ°ã¨ãã¦ãæ§é ä½ãæ¸¡ãããæ§é ä½ã¸ã®ãã¤ã³ã¿ãæ¸¡
+                    ããã¯ããã©ã°ã¤ã³ãèªåã§å¤å®ãããTAG åãä»ãã¦
+                    ããªãæ§é ä½ãæ±ããã¨ã¯ã§ããªããtypedef ããåå
+                    ã§æ§é ä½ãæ±ããã¨ã¯ã§ããªãã
+
+ã»ãã®ä»
+
+  void * ã¯æ±ããªã
+  intptr_t ã¯ãéå¸¸ stdint.h ã§ typedef ããã¦ããããå
+ã®åã¨ãã¦æ±ã
+
+ãã©ã°ã¤ã³å¼æ°ã¨ãã¦ ignoreUnsigned=true ãæå®ããã¨ãç¡ç¬¦å·æ´æ°åã¸
+ã®ãã¤ã³ã¿åãæç¬¦å·æ´æ°åã®ãã¤ã³ã¿åã¨ãã¦æ±ãï¼å¤ã®ç¯å²ãã§ãã¯ãå«
+ãï¼ããã¤ã³ã¿ãæ±ãã¯ã©ã¹ã®ã¡ã¢ãªä½¿ç¨éãæãããã¨ãæç¬¦å·ãç¡ç¬¦å·ã®
+ä½¿ãåããã«ã¼ãºã«ãããã¨ãã§ããã
+
+ãã«ãæã®ãªãã·ã§ã³ (C è¨èªã®ãã¯ã­å®ç¾©) TECS_NO_VAL_CHECK ãæå®ãã
+ãã¨ã§ãå¤ã®ç¯å²ãã§ãã¯ãè¡ããªãããã«ãããã¨ãã§ããã
+
+ãé¢æ°åã
+
+ã»é¢æ°åã«é¢æ°ããå¶é
+
+  é¢æ°å initialize ã¯ ruby ã§æ¢å®ã®ã¡ã½ããåã¨éè¤ãããããinitialize_cell
+ ã«ç½®æãããã
+
+  initialize ã¨ initialize_cell ã®ä¸¡æ¹ã signature å
+ã«å­å¨ããå ´åãã¨ã©ã¼ã¨
+  ãªããã¨ã©ã¼ãè§£æ¶ããã«ã¯ãå°ãªãã¨ãä¸æ¹ã®ååãå¤æ´ããå¿
+è¦ãããã
+
+ãæ»ãå¤ã
+
+æ»ãå¤ã§æ±ããã®ã¯ãä»¥ä¸ã®åã«éãããã
+
+   void, bool_t, char_t, intN_t, float32_t, double64_t
+   int, short, long, char
+   å
+ã®åãããããã§ãã typedef ãããå
+
+ãå¼æ°ã
+
+ã»é åºã®éãå¯¾å¿ãã mruby ã®åï¼ã¯ã©ã¹ï¼ã®å¤ãå¼æ°ã¨ãã¦æ¸¡ã
+ã»æå®å¯è½ãªåºæ¬æå®å­  in, inout, out  (send/receive ã¯ä¸å¯)
+ã»ä¾å¤ã®çºç
+  ã»æ´æ°ã®å¤ããå¼æ°ã®åã®ç¯å²ãè¶
+ãã¦ããå ´åãä¾å¤ãçºçããã
+    ç¡ç¬¦å·åã®å ´åãè² ã®å¤ãåããã¨ã¯ã§ããªãããã ããmrb_int ã¨åã
+    ã¾ãã¯ããä»¥ä¸ã®ãµã¤ãºã®å ´åã«ã¯ãè² ã®å¤ãæå®ããã¦ãä¾å¤ã¨ã¯ããª
+    ãããããªãã¨æä¸ä½ãããã 1 ã®å¤ãå
+¥åã§ããªãããã
+    char_t (char) ã¯ç¡ç¬¦å·ã¨è¦ãªãããã
+    ãªã uintptr_t ã« 0x80000000 ã«ãæ¸¡ãéã« RangeError ä¾å¤ãçºçã
+    ãããããã¯ mruby ã«ãããã®ã§ãããTECS ã«ããå¶éã§ã¯ãªã
+  ã»ãã¤ã³ã¿åãæ§é ä½åã«å¯¾å¿ãã mruby ã®å(ã¯ã©ã¹) ã¨ä¸è´ããªã
+  ã»size_is, string ã®ãµã¤ãºãå°ãã
+
+ãåèã
+
+ TECSPointer.txt
+
+  ä»¥ä¸ã® mruby ã¯ã©ã¹ãããªãã¡ TECS ã®ãã¤ã³ã¿å¤ãæ±ãããã®ã¯ã©ã¹ã«
+  ã¤ãã¦ã®èª¬æã
+ããããã®ã¯ã©ã¹ã¯å¿
+è¦ã«å¿ãã¦çæããããå¼æ°ã¨ãã¦ä½¿ç¨ããã¦ããªãã¯
+  ã©ã¹ã¯çæãããªãã
+
+  TECS::Int8Pointer,   TECS::Int16Pointer,   TECS::Int32Pointer
+  TECS::Int64Pointer,  TECS::UInt64Pointer
+  TECS::UInt8Pointer,  TECS::UInt16Pointer,  TECS::UInt32Pointer
+  TECS::CharPointer,   TECS::SCharPointer,   TECS::UCharPointer
+  TECS::IntPointer,    TECS::ShortPointer,   TECS::LongPointer
+  TECS::UIntPointer,   TECS::UShortPointer,  TECS::ULongPointer
+  TECS::BoolPointer,   TECS::Float32Pointer, TECS::Double64Pointer
+
+ TECSStruct.txt
+
+  ä»¥ä¸ã® mruby ã¯ã©ã¹ãããªãã¡ TECS ã®æ§é ä½ï¼ãã¤ã³ã¿ï¼å¤ãæ±ããã
+  ã®ã¯ã©ã¹ã«ã¤ãã¦ã®èª¬æã
+
+  TECS::StructTAG
+
+ãTECS CDLã«ããè¨è¿°ã
+
+ ããªãã¸ãã©ã°ã¤ã³ã«ãããããªãã¸ã»ã«ã¿ã¤ããèªåçæãããã
+ ããªãã¸ã»ã«ã¯ãCDL ã«è¨è¿°ãã¦è¨­ç½®ããå¿
+è¦ããã
+
+ã»ããªãã¸ãã©ã°ã¤ã³ã®å¼åºã
+
+mruby=>TECS ããªãã¸ãã©ã°ã¤ã³ã¯ãã·ã°ããã£ãã©ã°ã¤ã³ã§ãããCDL ä¸ã®ä»¥ä¸ã®ã
+ããªè¨è¿°ã«ãããmruby=>TECS ããªãã¸ãã©ã°ã¤ã³ãå¼ã³åºãã
+
+  ex)
+    generate( MrubyBridgePlugin, sSignature, "" );
+
+ ã·ã°ããã£ sSignature ã¯ããã®è¨è¿°ãããåã«å®ç¾©ããã¦ããªãã¦ã¯ãªããªãã
+ ãã® generate ã®è¨è¿°ã«ãããæ¬¡ã®ãããªããªãã¸ã»ã«ã¿ã¤ããçæãããã
+
+generate ã®ç¬¬3å¼æ°ã¯ããã©ã°ã¤ã³å¼æ°ï¼ãªãã·ã§ã³ï¼ã§ããã
+
+  ignoreUnsigned   true ãæå®ããã¨ç¡ç¬¦å·æ´æ°ã¸ã®ãã¤ã³ã¿åã«æç¬¦å·ã®ã
+                   ã¤ã³ã¿ã¯ã©ã¹ãä½¿ç¨ããï¼ã¡ã¢ãªãç¯ç´ã§ããï¼
+                   ããã©ã«ãã¯ false ã§ããã
+  include          ããªãã¸ã«å«ããé¢æ°ãæå®ãããexclude ã¨åææå®ä¸å¯ã
+  exclude          ããªãã¸ã«å«ããé¢æ°ãæå®ãããinclude ã¨åææå®ä¸å¯ã
+
+  ex)
+    generate( MrubyBridgePlugin, sSignature, "exclude=fun99" );
+
+å¤ãã®é¢æ°ãæå®ããå ´åãä»¥ä¸ã®ããã«ãåå²ããæå­åã®é£æ¥ã¨ãã¦å¸«å®
+ãããã¨ãã§ãã¾ãã
+
+  ex)
+    generate( MrubyBridgePlugin, sSignature,
+        "ignoreUnsigned=true, "
+        "include='func1,func2', "
+        "include='func3,func4', "
+     );
+
+ã»ããªãã¸ã»ã«ã¿ã¤ã
+
+ ããªãã¸ã»ã«ã¿ã¤ãã¯ããã¼ã ã¹ãã¼ã¹ nMruby ã®ä¸ã«ä½ããããããªãã¸
+ã»ã«ã¿ã¤ãã®ååã¯ãã·ã°ããã£åã« 't' ãåç½®ããããã®ã§ãããä»¥ä¸ã¯ã
+ããªãã¸ãã©ã°ã¤ã³ã«ããèªåçæãããã»ã«ã¿ã¤ãã®ã³ã¼ãã®ä¾ã§ãããã·
+ã°ããã£ sSignature ã«å¯¾ããããªãã¸ã»ã«ã¿ã¤ãåã¯ tsSignature ã§ããã
+å¼ã³å£cTECS ãæã¤ã
+
+  ex) èªåçæããã CDL ã³ã¼ãï¼å
+é¨ã§çæãããè§£éãããï¼
+
+   namespace nMruby {
+     celltype SSignature{
+       call sSignature cTECS;
+     };
+   };
+
+ã»ããªãã¸ã»ã«ã®è¨­ç½®
+
+ ããªãã¸ã»ã«ã¯ãããªãã¸ã»ã«ã¿ã¤ãã®ã»ã«ã¨ãã¦çæãããããªãã¸ã»ã«
+ ã®è¨­ç½®ã¯ CDL ã®è¨è¿°è
+ãè¡ããã®ã§ãããããªãã¸ã»ã«ã®å¼ã³å£ cTECS ã 
+ mRuby ããå¼ã³åºãããã»ã«ã¸çµåããã
+
+  ex) ããªãã¸ã»ã«ãè¨­ç½®ãã CDL è¨è¿°
+
+   cell nMruby::tsSignature BridgeCell {
+     cTECS = Cell.eEnt;
+   };
+
+  ex) ããªãã¸ã»ã«ãè¨­ç½®ãã CDL è¨è¿°(VM åæå®ãã)
+
+   cell nMruby::tsSignature BridgeCell {
+     cTECS = Cell.eEnt;
+	 VMname = "VM2";
+   };
+
+  VMname ã¯ mruby VM ã®ã»ã«ã®ååã®æå®ã§ãããVMname ãæå®ããªãå ´åã
+  "VM" ãä»®å®ããããVMname ã¯ãå®éã«ã¯ãVM_TECSInitializer ãªã©ã®ã
+  ãã«ãããªãã¸ãç»é²ããã»ã«ã®ãã»ã«åã«ç¨ãããããtecsgen å®è¡æã«
+  ä»¥ä¸ã®ãããªã¡ãã»ã¼ã¸ãåºåããããåãå£ 
+  VM_TECSInitializer.eInitialize ã¸ VM ã®åæåç¨å¼ã³å£ããçµåããã
+
+   MrubyBridgePlugin: join your VMs cInitialize to VM_TECSInitializer.eInitialize
+
+ãmruby ã³ã¼ãã
+
+ ããªãã¸ãã©ã°ã¤ã³ãé©ç¨ãããã·ã°ããã£ã«å¯¾å¿ãã mruby ã¯ã©ã¹ãçæ
+ ãããããããããªãã¸ã¯ã©ã¹ã¨å¼ã¶ã
+ ããªãã¸ã¯ã©ã¹ãéãã¦ã»ã«ã®åãå£é¢æ°ãå¼ã³åºããã¨ãã§ããã
+
+ã»ããªãã¸ã¯ã©ã¹
+
+ ããªãã¸ã¯ã©ã¹ã¯ãã¢ã¸ã¥ã¼ã« TECS ã®ä¸ã«ä½æããããããªãã¸ã¯ã©ã¹ã®
+ ååã¯ãã·ã°ããã£åã« 'T' ãåç½®ããããã®ã¨ãªãã
+
+ ex)  TECS::TsSignature
+
+ã»ããªãã¸ã®ã¤ã³ã¹ã¿ã³ã¹
+
+  ããªãã¸ã¯ã©ã¹ã«ã¦ãããªãã¸ã»ã«åãå¼æ°ã¨ãã¦ new ãããã¨ã§ãããªã
+  ã¸ã¯ã©ã¹ã®ã¤ã³ã¹ã¿ã³ã¹ãçæããããããªãã¸ã¯ã©ã¹ã®ã¤ã³ã¹ã¿ã³ã¹ã®ã
+  ã¨ããç­ããããªãã¸ã®ã¤ã³ã¹ã³ã¿ã³ã¹ã¨ãå¼ã¶ãããªãã¸ã®ã¤ã³ã¹ã¿ã³ã¹
+  ã¯ãããªãã¸ã»ã«ã¸ã®ãã¤ã³ã¿æ
+å ±ãä¿æããã ãã§ãããåä¸ã®ããªãã¸
+  ã®ã¤ã³ã¹ã¿ã³ã¹ã¯ä½åº¦ã§ãçæãããã¨ãã§ããã
+
+ ex)  brdige = TECS::TsSignature.new( "CellName" )
+
+ãæ®èª²é¡ã
+
+[æ¸] æ´æ°åã® unsigned ã®æ±ã
+   ã­ã£ã¹ãããã¦ããã®ã§ãã³ã³ãã¤ã«ã¯è­¦åãªãéãã
+   å¤ã®ç¯å²ãã§ãã¯ã¨æ´åãã¦ããªãã
+   ä»¥ä¸ãæ°ãã«è¨­ãããã
+   UInt8Pointer, UInt16Pointer, UInt32Pointer, UInt64Pointer
+   UIntPointer, UShortPointer, ULongPointer, UCharPointer, SCharPointer, 
+
+[æ¸] å¤ã®ç¯å²ã®ãã§ãã¯
+   TECSPointer, TECSStruct ã§ã¯æ´æ°å¤ãè¨­å®ããéã«ãç¯å²ãã§ãã¯ãããã
+   ã¡ã½ããã¸ã®ç´æ¥ã®å¼æ°ã¯ãã§ãã¯ãããªãã
+
+[æ¸] ç¾ç¶ã® so ã¨ãã¦ã®å®è£
+ã¯ãããã
+   éçã« mruby ã®æ¬ä½ãçµåããã¦ããã
+
+[æ¸] ãã¤ã³ã¿åãæ±ãã¯ã©ã¹ãå¤ããã
+   ä½¿ç¨ããã¯ã©ã¹ã ãã­ã¼ããããåæåãããä»çµã¿ãæ¬²ããã
+
+ã»ä»¥ä¸ã®æ¹æ³ã§ããªãã¸ãå²ãä»ãã¦ãããã
+    bridge = TsSample.new( "SimpleBridge" )
+ãä»¥ä¸ã®ããã«ãå®æ°ã¨ãã¦æ±ããã¨ãã§ããæ¹ãã¹ãã¼ãã§ããã
+    bridge = TECS::SimpleBridge
+  (ç¾ç¶ã®æ¹ããããªãã¸ã®ã»ã«ã¿ã¤ãããããç¹ãåªãã¦ãã)
+  â ããå®æ°ã¨ãã¦æ±ãã¨ãã¦ãå²ä»ãã C ã§è¡ãã ruby ã³ã¼ãã§è¡ãã
+     ã®éãã§ãããªããä»¥ä¸ã«ããã©ããã¼ã¯ã©ã¹ã«ããå®æ°ã®åæåãè¡
+     ãã°ããã
+  â å®æ°ã¨ãã¦æ±ãã¨ããªãã¸ã§ã¯ããæåããæå¾ã¾ã§æ¶ããªãã¨ããå
+     é¡ããã(ããã§ãå°éã§ããã)
+
+ã»ä¸è¨ã«é¢é£ãã¦ãVM ãç°ãªãå ´åã«ãä»ã® VM ã«å²ãä»ããããªãã¸åã
+  è¦ãã¦ãã¾ããã¢ã¯ã»ã¹å¶éãååã§ãªãã
+  ããªãã¸åã®ã¢ã¯ã»ã¹å¶éãå®ç¾ããã«ã¯ãVM ãè­å¥ããæ
+å ±ãå¿
+è¦ã«ãª
+  ããmrb_state ã« p_cellcb ãå ããæ¹æ³ãmrb_stateèªèº«ã§åºå¥ããæ¹æ³
+  ãèãããããè¦æ¤è¨ã
+  ãªããã»ã«ã¿ã¤ãåä½ã§ã®ã¢ã¯ã»ã¹å¶ éã¯ã§ãã¦ãã(ã¦ãã¦ããªãã®ã¯ã
+  åãã»ã«ã¿ã¤ãã§è¤æ°ã®ããªãã¸ã»ã«ãããå ´åã«ãããªãã¸åã®ã¢ã¯ã»ã¹
+  å¶é)ã
+
+ã»typedef ãããååã§ã¢ã¯ã»ã¹ã§ããã¨ä¾¿å©ã§ãã
+  TECSPointer ã TECSStruct ã®ã¯ã©ã¹ã«å¯¾ãã alias ã«ãããå¥åã¨ãã¦
+  ã¢ã¯ã»ã¹ã§ããã¨ããã
+   â ã¨ãããããMrubyBridgePlugin ã®ã¡ãã»ã¼ã¸ã¨ãã¦ãããããã«ããã
+
+ã»send/receive ã¸ã®å¯¾å¿
+  mruby ã¨å
+±éã®ã¢ã­ã±ã¼ã¿ãæå®å¯è½ã¨ãã (ã¢ã­ã±ã¼ã¿ã³ã³ãã¼ã¿ãã©ã°ã¤ã³ãæ°è¦ã«è¨­ãã¦ã¯?)
+
+ã»æ§é ä½ã¡ã³ãã¼ã®åå¶éã®ç·©å
+   strign or size_is æå®ããã char* ãªã©
+
+ã»ruby ããããã­ã°ã©ã ãã mruby â TECS ããªãã¸ã®ã¯ã©ã¹ã¸ã®èªåå¤æããã©ããã¼ã¯ã©ã¹ã®çæ
+  (ruby's Array => TECS::Pointer, ruby's Struct => TECS::StructTAG)
+
+[æ¸]ããªãã¸ã¯ã©ã¹ã® new ã§ã»ã«ãè¦ã¤ãããªãã£ãå ´åãruby ä¾å¤ãçºçãããã
+  ããã free ããæ®µéã§ SEGV ãçºçãããã DATA_SET ãæ©ãã«è¡ãããã«å¤æ´ã
+  ãªããåã¡ã½ããã®é¢æ°ã§ DATA_PTR ã null ãã©ããããã§ãã¯ããªããã
+  ä¾å¤ãçºçãããã¨ã«ããä¸å®å
+¨ãªããªãã¸ã¯å¤æ°ã«è¨æ¶ãããªãï¼ã¯ãï¼
+  ãããåé¡ãªãã
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyTECSPointer.txt
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyTECSPointer.txt	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyTECSPointer.txt	(revision 374)
@@ -0,0 +1,109 @@
+TECS::Int8Pointer       TECS::UInt8Pointer
+TECS::Int16Pointer      TECS::UInt16Pointer
+TECS::Int32Pointer      TECS::UInt32Pointer
+TECS::Int64Pointer      TECS::UInt64Pointer
+TECS::CharPointer       TECS::SCharPointer      TECS::UCharPointer
+TECS::IntPointer	    TECS::UIntPointer
+TECS::ShortPointer	    TECS::UShortPointer
+TECS::LongPointer       TECS::ULongPointer
+TECS::BoolPointer
+TECS::Float32Pointer
+TECS::Double64Pointer
+
+TECS ã®ãã¤ã³ã¿åã®æ´æ°ãã¼ã¿ãæµ®åå°æ°ç¹ãã¼ã¿ãæå­ãã¼ã¿ãæ±ããã
+ã®è¨æ¶åãæ±ãã¾ãããããã®ã¯ã©ã¹ã¯ãã·ã°ããã£ã§ä½¿ç¨ããã¦ãããã®ã 
+MrubyBridgePlugin ãã©ã°ã¤ã³ãèªåå¤å¥ãã¦çæãã¾ãã
+
+ãã¤ã³ã¿å¤ãã®ãã®ãæ¸¡ãã«ã¯ intptr_t åã¨ãã¦æ¸¡ãã®ãå¦¥å½ã§ãã
+
+C è¨èªã®åã¨ã¯ãä»¥ä¸ã®ããã«å¯¾å¿ãã¾ãã
+
+   int8_t                 TECS::Int8Pointer
+   int16_t                TECS::Int16Pointer
+   int32_t                TECS::Int32Pointer
+   int64_t                TECS::Int64Pointer
+   char_t                 TECS::CharPointer
+   schar_t                TECS::SCharPointer
+   uchar_t                TECS::UCharPointer
+   uint8_t                TECS::UInt8Pointer
+   uint16_t               TECS::UInt16Pointer
+   uint32_t               TECS::UInt32Pointer
+   uint64_t               TECS::UInt64Pointer
+   bool_t                 TECS::BoolPointer
+   float32_t              TECS::Float32Pointer
+   double64_t             TECS::Double64Pointer
+
+ éæ¨å¥¨ã®å
+   char                   TECS::CharPointer
+   int                    TECS::IntPointer
+   short                  TECS::ShortPointer
+   long                   TECS::LongPointer
+   signed char            TECS::SCharPointer
+   unsigned char          TECS::UCharPointer
+   unsigned int           TECS::UIntPointer
+   unsigned short         TECS::UShortPointer
+   unsigned long          TECS::ULongPointer
+   float                  TECS::Float32Pointer
+   double                 TECS::Double64Pointer
+
+char, signed char, unsgined char ã¯ char_t, schar_t, uchar_t ã¨è¦ãªããã¾ãã
+
+ãåèã
+ã¿ã¼ã²ããç°å¢ã«ããã¦ char, singed char, unsigned char ã®ãµã¤ãºã 1 ãã¤ãã§ã¯ç¡ãå ´åã«ã¯ãç¸éãçããã
+
+== ã¹ã¼ãã¼ã¯ã©ã¹ ==
+
+Object
+
+== ã¯ã©ã¹ã¡ã½ãã ==
+
+new( size )
+
+  size ã®å¤§ãããæã¤è¨æ¶åãæããã¤ã³ã¿ãçæãã¦è¿ãã¾ãã
+  size ã®åä½ã¯ãè¦ç´ ã®åæ°ã§ãã
+
+== ã¡ã½ãã ==
+
+self[ nth ]
+
+  nth çªç®ã®è¦ç´ ãè¿ãã¾ããnth ã¯ 0..(length-1) ã®æ´æ°ã§ãã
+  '=' ã®å·¦è¾ºã§ã¯ãnth çªç®ã®è¦ç´ ãå³è¾ºã®å¤ã«ç½®ãæãã¾ãã
+
+  nth ã«æ´æ°ã¾ãã¯æµ®åå°æ°ä»¥å¤ãæ¸¡ããå ´åãä¾å¤ãçºçãã¾ãã
+
+self[ nth ] = val
+
+  æ´æ°åã®ãã¤ã³ã¿ã®å ´åãå¤ã®ç¯å²ããã§ãã¯ããã¾ãã
+  val ã®å¤ãç¯å²ãè¶
+ããå ´åãä¾å¤ãçºçãã¾ãã
+
+value
+
+  ãã¤ã³ã¿ã®æãå
+ã®å¤ãåãåºãã¾ãã
+  self[0] ã¨åãã§ãã
+
+value = val
+
+  ãã¤ã³ã¿ã®æãå
+ã«å¤ãè¨­å®ãã¾ãã
+  self[0] = val ã¨åãã§ãã
+
+length
+size
+
+  ãã¤ã³ã¿ãæãè¦ç´ ã®åæ°ãè¿ãã¾ãã
+
+to_s
+
+  CharPointer ã¯ã©ã¹ã§ã®ã¿ä½¿ç¨ã§ãã¾ãã
+  mruby ã® String ã¯ã©ã¹ã®ã¤ã³ã¹ã¿ã³ã¹ã«å¤æãã¦è¿ãã¾ãã
+
+from_s
+
+  CharPointer ã¯ã©ã¹ã§ã®ã¿ä½¿ç¨ã§ãã¾ãã
+  mruby ã®æå­åãã CharPointer ã®æãè¨æ¶åã«æå­åãã³ãã¼ãã¾ãã
+  
+  new ã®éã«ç¢ºä¿ãããè¨æ¶åãç¨ãããã¾ããè¨æ¶åã®å¤§ãããæå­åãããç­ãå ´åã«ã¯ãè¨æ¶åã®å¤§ããã«åã¾ãããã«ã³ãã¼ããã¾ãã
+  è¨æ¶åãããæå­åãé·ãå ´åãè¨æ¶åã®æ«å°¾ã«çµç«¯æå­ '\0' ã¯ç½®ããã¾ããã
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyTECSStruct.txt
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyTECSStruct.txt	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyTECSStruct.txt	(revision 374)
@@ -0,0 +1,24 @@
+TECS::StructTAG
+
+  C è¨èªã®æ§é ä½ãæ±ãããã®ã¯ã©ã¹ã§ãããsignature ã«ç¾ããæ§é ä½ã«åããã¦ MrubyBridgePlugin ã«ããçæããã¾ãã
+  TAG ã®é¨åã¯ãæ§é ä½ã®ã¿ã°åã«ç½®ãæãã¾ãã
+
+== ã¹ã¼ãã¼ã¯ã©ã¹ ==
+
+Object
+
+== ã¯ã©ã¹ã¡ã½ãã ==
+
+new()
+
+== ã¡ã½ãã ==
+
+MEMBER
+
+  æ§é ä½ã¡ã³ãã®å¤ãèª­ã¿åºãã¾ãã
+  MEMBER ã¯ã¡ã³ãåã«ç½®ãæãã¾ãã
+
+MEMBER = val
+
+  æ§é ä½ã¡ã³ãã®å¤ãæ¸ãè¾¼ã¿ã¾ãã
+  MEMBER ã¯ã¡ã³ãåã«ç½®ãæãã¾ãã
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyVMs.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyVMs.cdl	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/mrubyVMs.cdl	(revision 374)
@@ -37,5 +37,6 @@
 
 /*
- * tools/mruby/mruby.c から cInit_initializeBridge( mrb ) を呼び出すように変更したもの
+ * POSIX 環境用の VM
+ * mrbgems の mrbgems/mruby-bin-mruby/tools/mruby/mruby.c を参考に作成したもの
  */
 namespace nMruby{
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyCyclicTaskBody.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyCyclicTaskBody.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyCyclicTaskBody.c	(revision 374)
@@ -0,0 +1,105 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cMrubyVM signature: nMruby_sMrubyVM context:task
+ *   bool_t         cMrubyVM_initialize( );
+ *   bool_t         cMrubyVM_run( );
+ *   void           cMrubyVM_funcall( const char_t* name );
+ *   void           cMrubyVM_finalize( );
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include "nMruby_tMrubyCyclicTaskBody_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eMrubyBody
+ * entry port: eMrubyBody
+ * signature:  sTaskBody
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eMrubyBody_main
+ * name:         eMrubyBody_main
+ * global_name:  nMruby_tMrubyCyclicTaskBody_eMrubyBody_main
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eMrubyBody_main(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( ! VAR_b_init ){
+      cMrubyVM_initialize( );
+      VAR_b_init = true;
+  }
+  cMrubyVM_run( );
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyProc.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyProc.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyProc.c	(revision 374)
@@ -0,0 +1,186 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/*
+ * ä»¥åã® nMruby_tMrubyProc.c ã¯ãmruby ã®æ¬ä½ã«å«ã¾ãã¦ãã 
+ *    mrbgems/mruby-bin-mruby/tools/mruby/mruby.c
+ * ããã¼ã¹ã« TECS ã®ã³ã¼ããè¶³ãã¦ããããTOPPERS ã©ã¤ã»ã³ã¹ã¨ç°ãªããã
+ * æ°ãã«æ¸ãä¸ããããï¼å°ããªã³ã¼ãã®ãããæ¦ã­ä¼¼ããããªãã®ã«ãªããã
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "mruby.h"
+#include "mruby/string.h"
+#include "mruby/array.h"
+#include "mruby/compile.h"
+#include "mruby/dump.h"
+#include "mruby/variable.h"
+
+/* #[<PREAMBLE>]#
+ * Don't edit the comments between #[<...>]# and #[</...>]#
+ * These comment are used by tecsmerege when merging.
+ *
+ * attr access macro #_CAAM_#
+ * mrb              mrb_state*       VAR_mrb         
+ *
+ * call port function #_TCPF_#
+ * call port: cInit signature: nMruby_sInitializeBridge context:task optional:true
+ *   bool_t     is_cInit_joined()                     check if joined
+ *   void           cInit_initializeBridge( const mrb_state* mrb );
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include "nMruby_tMrubyProc_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eMain
+ * entry port: eMain
+ * signature:  nPosix_sMain
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eMain_main
+ * name:         eMain_main
+ * global_name:  nMruby_tMrubyProc_eMain_main
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+int
+eMain_main(CELLIDX idx, int argc, const char** argv)
+{
+	CELLCB	*p_cellcb;
+  mrb_state *mrb;
+  mrbc_context* context;
+  if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+      return -1;
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if (argc != 2) {
+      printf("usage: %s script.rb\n", argv[0]);
+      goto error_return;
+  }
+  mrb = mrb_open();
+  if( mrb == 0 ){
+      printf("%s: mrb_open() failed\n", argv[0]);
+      goto error_return;
+  }
+  context = mrbc_context_new(mrb);
+  if (context == 0) {
+      printf("%s: mrbc_context_new() failed\n", argv[0]);
+      goto error_close;
+  }
+
+  /*--------   ARGV   ----------*/
+  {
+      mrb_value ARGV = mrb_ary_new_capa(mrb, argc);
+      int  i;
+      for (i = 0; i < argc; i++) {
+          mrb_ary_push(mrb, ARGV, mrb_str_new_cstr(mrb, argv[i]));
+      }
+      mrb_define_global_const(mrb, "ARGV", ARGV);
+  }
+  /*--------   $0   ----------*/
+  {
+      mrb_sym zero_sym = mrb_intern_lit(mrb, "$0");
+      mrbc_filename(mrb, context, argv[0]);
+      mrb_gv_set(mrb, zero_sym, mrb_str_new_cstr(mrb, argv[0]));
+  }
+
+  /* ------- register TECS bridge classes -------*/
+  if (is_cInit_joined()) {
+      cInit_initializeBridge(mrb);
+  }
+
+  /*--------  load .rb file -------*/
+  {
+      FILE *file = fopen(argv[1], "r");
+      if (file == NULL) {
+          printf("file not found: %s\n", argv[1]);
+          goto error_free;
+      }
+
+      mrb_value val = mrb_load_file_cxt(mrb, file, context);
+      if (mrb->exc) {
+          if(! mrb_undef_p(val)){
+              mrb_print_error(mrb);
+          }
+      }
+  }
+
+  /*---------- success case --------*/
+  mrbc_context_free(mrb, context);
+  mrb_close( mrb );
+  return 0;
+
+  /*---------- error case ----------*/
+error_free:
+  mrbc_context_free(mrb, context);
+error_close:
+  mrb_close( mrb );
+error_return:
+
+  return -1;
+}
+
+/* #[<POSTAMBLE>]#
+ *   Put non-entry functions below.
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyProc_1_0.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyProc_1_0.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyProc_1_0.c	(revision 374)
@@ -0,0 +1,306 @@
+/*
+ * This file comes from mruby. (renamed from tools/mruby/mruby.c)
+ * This file is distributed under ruby's license. (not under TOPPERS license)
+ *   see https://github.com/mruby/mruby
+ * A little modification is done to to call initializer registering TECS components.
+ *
+ * ãã®ãã¡ã¤ã«ã¯ãmruby ã®ãã®ã§ãã
+ * mruby ã®ã©ã¤ã»ã³ã¹ã®ãã¨ã§ãé
+å¸ããã¾ãã(TOPPERS ã©ã¤ã»ã³ã¹ã§ã¯ããã¾ãã)
+ *  åç
+§ï¼  https://github.com/mruby/mruby
+ * TECS ã³ã³ãã¼ãã³ããç»é²ããåæåå­ãå¼ã¶ãããå°ãã®ä¿®æ­£ããªããã¦ãã¾ãã
+ */
+
+#include "nMruby_tMrubyProc_tecsgen.h"
+
+#include "mruby.h"
+#include "mruby/proc.h"
+#include "mruby/array.h"
+#include "mruby/string.h"
+#include "mruby/compile.h"
+#include "mruby/dump.h"
+#include "mruby/variable.h"
+#include <stdio.h>
+#include <string.h>
+
+#ifndef ENABLE_STDIO
+static void
+p(mrb_state *mrb, mrb_value obj)
+{
+  obj = mrb_funcall(mrb, obj, "inspect", 0);
+  fwrite(RSTRING_PTR(obj), RSTRING_LEN(obj), 1, stdout);
+  putc('\n', stdout);
+}
+#else
+#define p(mrb,obj) mrb_p(mrb,obj)
+#endif
+
+void mrb_show_version(mrb_state *);
+void mrb_show_copyright(mrb_state *);
+
+struct _args {
+  FILE *rfp;
+  char* cmdline;
+  int fname        : 1;
+  int mrbfile      : 1;
+  int check_syntax : 1;
+  int verbose      : 1;
+  int argc;
+  char** argv;
+};
+
+static void
+usage(const char *name)
+{
+  static const char *const usage_msg[] = {
+  "switches:",
+  "-b           load and execute RiteBinary (mrb) file",
+  "-c           check syntax only",
+  "-e 'command' one line of script",
+  "-v           print version number, then run in verbose mode",
+  "--verbose    run in verbose mode",
+  "--version    print the version",
+  "--copyright  print the copyright",
+  NULL
+  };
+  const char *const *p = usage_msg;
+
+  printf("Usage: %s [switches] programfile\n", name);
+  while(*p)
+  printf("  %s\n", *p++);
+}
+
+static int
+parse_args(mrb_state *mrb, int argc, char **argv, struct _args *args)
+{
+  char **origargv = argv;
+  static const struct _args args_zero = { 0 };
+
+  *args = args_zero;
+
+  for (argc--,argv++; argc > 0; argc--,argv++) {
+    char *item;
+    if (argv[0][0] != '-') break;
+
+    if (strlen(*argv) <= 1) {
+      argc--; argv++;
+      args->rfp = stdin;
+      break;
+    }
+
+    item = argv[0] + 1;
+    switch (*item++) {
+    case 'b':
+      args->mrbfile = 1;
+      break;
+    case 'c':
+      args->check_syntax = 1;
+      break;
+    case 'e':
+      if (item[0]) {
+        goto append_cmdline;
+      }
+      else if (argc > 1) {
+        argc--; argv++;
+        item = argv[0];
+append_cmdline:
+        if (!args->cmdline) {
+          char *buf;
+
+          buf = (char *)mrb_malloc(mrb, strlen(item)+1);
+          strcpy(buf, item);
+          args->cmdline = buf;
+        }
+        else {
+          args->cmdline = (char *)mrb_realloc(mrb, args->cmdline, strlen(args->cmdline)+strlen(item)+2);
+          strcat(args->cmdline, "\n");
+          strcat(args->cmdline, item);
+        }
+      }
+      else {
+        printf("%s: No code specified for -e\n", *origargv);
+        return 0;
+      }
+      break;
+    case 'v':
+      mrb_show_version(mrb);
+      args->verbose = 1;
+      break;
+    case '-':
+      if (strcmp((*argv) + 2, "version") == 0) {
+        mrb_show_version(mrb);
+        exit(0);
+      }
+      else if (strcmp((*argv) + 2, "verbose") == 0) {
+        args->verbose = 1;
+        break;
+      }
+      else if (strcmp((*argv) + 2, "copyright") == 0) {
+        mrb_show_copyright(mrb);
+        exit(0);
+      }
+      else return -3;
+      return 0;
+    default:
+      return -4;
+    }
+  }
+
+  if (args->rfp == NULL && args->cmdline == NULL) {
+    if (*argv == NULL) args->rfp = stdin;
+    else {
+      args->rfp = fopen(argv[0], args->mrbfile ? "rb" : "r");
+      if (args->rfp == NULL) {
+        printf("%s: Cannot open program file. (%s)\n", *origargv, *argv);
+        return 0;
+      }
+      args->fname = 1;
+      args->cmdline = argv[0];
+      argc--; argv++;
+    }
+  }
+  args->argv = (char **)mrb_realloc(mrb, args->argv, sizeof(char*) * (argc + 1));
+  memcpy(args->argv, argv, (argc+1) * sizeof(char*));
+  args->argc = argc;
+
+  return 0;
+}
+
+static void
+cleanup(mrb_state *mrb, struct _args *args)
+{
+  if (args->rfp && args->rfp != stdin)
+    fclose(args->rfp);
+  if (args->cmdline && !args->fname)
+    mrb_free(mrb, args->cmdline);
+  if (args->argv)
+    mrb_free(mrb, args->argv);
+  mrb_close(mrb);
+}
+
+static void
+showcallinfo(mrb_state *mrb)
+{
+  mrb_callinfo *ci;
+  mrb_int ciidx;
+  const char *filename, *method, *sep;
+  int i, line;
+
+  printf("trace:\n");
+  ciidx = mrb_fixnum(mrb_obj_iv_get(mrb, mrb->exc, mrb_intern(mrb, "ciidx")));
+  if (ciidx >= mrb->ciend - mrb->cibase)
+    ciidx = 10; /* ciidx is broken... */
+
+  for (i = ciidx; i >= 0; i--) {
+    ci = &mrb->cibase[i];
+    filename = "(unknown)";
+    line = -1;
+
+    if (MRB_PROC_CFUNC_P(ci->proc)) {
+      continue;
+    }
+    else {
+      mrb_irep *irep = ci->proc->body.irep;
+      if (irep->filename != NULL)
+        filename = irep->filename;
+      if (irep->lines != NULL && i+1 <= ciidx) {
+        mrb_code *pc = mrb->cibase[i+1].pc;
+        if (irep->iseq <= pc && pc < irep->iseq + irep->ilen) {
+          line = irep->lines[pc - irep->iseq - 1];
+        }
+      }
+    }
+    if (ci->target_class == ci->proc->target_class)
+      sep = ".";
+    else
+      sep = "#";
+
+    method = mrb_sym2name(mrb, ci->mid);
+    printf("\t[%d] %s:%d%s%s%s%s\n",
+    	   i, filename, line,
+	   method ? ":in " : "",
+	   method ? mrb_class_name(mrb, ci->proc->target_class) : "",
+	   method ? sep : "",
+	   method ? method : "");
+  }
+}
+
+int
+eMain_main( CELLIDX idx, int argc, const char **argv)
+{
+  CELLCB   *p_cellcb = GET_CELLCB( idx );
+  mrb_state *mrb = mrb_open();
+  int n = -1;
+  int i;
+  struct _args args;
+  mrb_value ARGV;
+
+  cInit_initializeBridge( mrb );
+
+  if (mrb == NULL) {
+    fprintf(stderr, "Invalid mrb_state, exiting mruby\n");
+    return EXIT_FAILURE;
+  }
+
+  n = parse_args(mrb, argc, (char **)argv, &args);
+  if (n < 0 || (args.cmdline == NULL && args.rfp == NULL)) {
+    cleanup(mrb, &args);
+    usage(argv[0]);
+    return n;
+  }
+
+  ARGV = mrb_ary_new_capa(mrb, args.argc);
+  for (i = 0; i < args.argc; i++) {
+    mrb_ary_push(mrb, ARGV, mrb_str_new(mrb, args.argv[i], strlen(args.argv[i])));
+  }
+  mrb_define_global_const(mrb, "ARGV", ARGV);
+
+  if (args.mrbfile) {
+    n = mrb_load_irep(mrb, args.rfp);
+    if (n < 0) {
+      fprintf(stderr, "failed to load mrb file: %s\n", args.cmdline);
+    }
+    else if (!args.check_syntax) {
+      mrb_run(mrb, mrb_proc_new(mrb, mrb->irep[n]), mrb_top_self(mrb));
+      n = 0;
+      if (mrb->exc) {
+        showcallinfo(mrb);
+        p(mrb, mrb_obj_value(mrb->exc));
+        n = -1;
+      }
+    }
+  }
+  else {
+    mrbc_context *c = mrbc_context_new(mrb);
+    mrb_value v;
+
+    if (args.verbose)
+      c->dump_result = 1;
+    if (args.check_syntax)
+      c->no_exec = 1;
+
+    if (args.rfp) {
+      mrbc_filename(mrb, c, args.cmdline ? args.cmdline : "-");
+      v = mrb_load_file_cxt(mrb, args.rfp, c);
+    }
+    else {
+      mrbc_filename(mrb, c, "-e");
+      v = mrb_load_string_cxt(mrb, args.cmdline, c);
+    }
+    mrbc_context_free(mrb, c);
+    if (mrb->exc) {
+      if (!mrb_undef_p(v)) {
+        showcallinfo(mrb);
+        p(mrb, mrb_obj_value(mrb->exc));
+      }
+      n = -1;
+    }
+    else if (args.check_syntax) {
+      printf("Syntax OK\n");
+    }
+  }
+  cleanup(mrb, &args);
+
+  return n == 0 ? EXIT_SUCCESS : EXIT_FAILURE;
+}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyTaskBody.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyTaskBody.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyTaskBody.c	(revision 374)
@@ -0,0 +1,103 @@
+/*
+ *   Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cMrubyVM signature: nMruby_sMrubyVM context:task
+ *   bool_t         cMrubyVM_initialize( );
+ *   bool_t         cMrubyVM_run( );
+ *   void           cMrubyVM_finalize( );
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include "nMruby_tMrubyTaskBody_tecsgen.h"
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eMrubyBody
+ * entry port: eMrubyBody
+ * signature:  sTaskBody
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eMrubyBody_main
+ * name:         eMrubyBody_main
+ * global_name:  nMruby_tMrubyTaskBody_eMrubyBody_main
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eMrubyBody_main(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( cMrubyVM_initialize( ) ){
+    cMrubyVM_run( );
+    cMrubyVM_finalize( );
+  }
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyVM.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyVM.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/nMruby_tMrubyVM.c	(revision 374)
@@ -0,0 +1,252 @@
+/*
+ *  Copyright (C) 2008-2017 by TOPPERS Project
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å±æ§ã¢ã¯ã»ã¹ãã¯ã­ #_CAAM_#
+ * irep             uint8_t*         ATTR_irep       
+ * var_irep         mrb_irep*        VAR_var_irep    
+ * mrb              mrb_state*       VAR_mrb         
+ * rproc            struct RProc*    VAR_rproc       
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cInit signature: nMruby_sInitializeBridge context:task optional:true
+ *   bool_t     is_cInit_joined()                     check if joined
+ *   void           cInit_initializeBridge( const mrb_state* mrb );
+ * call port: cMalloc signature: sMalloc context:task
+ *   int            cMalloc_initializeMemoryPool( );
+ *   void*          cMalloc_calloc( size_t nelem, size_t elem_size );
+ *   void*          cMalloc_malloc( size_t size );
+ *   void*          cMalloc_realloc( const void* ptr, size_t new_size );
+ *   void           cMalloc_free( const void* ptr );
+ *
+ * #[</PREAMBLE>]# */
+
+/* ãã­ãã¿ã¤ãå®£è¨ãå¤æ°ã®å®ç¾©ãããã«æ¸ãã¾ã #_PAC_# */
+#include "nMruby_tMrubyVM_tecsgen.h"
+#include <string.h>
+
+#include <mruby.h>
+#include <mruby/proc.h>
+#include <mruby/data.h>
+#include <mruby/compile.h>
+#include "t_syslog.h"
+
+MRB_API mrb_state* mrb_open_TECS( CELLCB *p_cellcb);
+
+#ifndef E_OK
+#define	E_OK	0		/* success */
+#define	E_ID	(-18)	/* illegal ID */
+#endif
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eMrubyVM
+ * entry port: eMrubyVM
+ * signature:  nMruby_sMrubyVM
+ * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eMrubyVM_initialize
+ * name:         eMrubyVM_initialize
+ * global_name:  nMruby_tMrubyVM_eMrubyVM_initialize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+bool_t
+eMrubyVM_initialize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+    return false;
+	} /* end if VALID_IDX(idx) */
+
+  cMalloc_initializeMemoryPool();
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  /* new interpreter instance */
+  //VAR_mrb = mrb_open();
+  VAR_mrb = mrb_open_TECS(p_cellcb);
+  if (VAR_mrb == NULL) {
+    syslog(LOG_EMERG, "Invalid mrb_state, exiting test driver");
+//    cSerialPort_write("Invalid mrb_state, exiting test driver\n", 39);
+    return false;
+  }
+
+  if(is_cInit_joined()){
+    // TECS Bridge
+    cInit_initializeBridge( VAR_mrb );
+  }
+  VAR_var_irep = mrb_read_irep(VAR_mrb, ATTR_irep);
+  VAR_rproc = mrb_proc_new(VAR_mrb, VAR_var_irep);
+  return true;
+}
+
+/* #[<ENTRY_FUNC>]# eMrubyVM_run
+ * name:         eMrubyVM_run
+ * global_name:  nMruby_tMrubyVM_eMrubyVM_run
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+bool_t
+eMrubyVM_run(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  mrb_run(VAR_mrb, VAR_rproc, mrb_top_self(VAR_mrb));
+  if (VAR_mrb->exc) {
+    mrb_p(VAR_mrb, mrb_obj_value(VAR_mrb->exc));
+    return false;
+  }
+  return true;
+}
+
+/* #[<ENTRY_FUNC>]# eMrubyVM_funcall
+ * name:         eMrubyVM_funcall
+ * global_name:  nMruby_tMrubyVM_eMrubyVM_funcall
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eMrubyVM_funcall(CELLIDX idx, const char_t* name)
+{
+	CELLCB	*p_cellcb;
+  mrb_int  argc;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  argc = 0;
+  (void)mrb_funcall(VAR_mrb, mrb_top_self(VAR_mrb), name, argc );
+}
+
+/* #[<ENTRY_FUNC>]# eMrubyVM_finalize
+ * name:         eMrubyVM_finalize
+ * global_name:  nMruby_tMrubyVM_eMrubyVM_finalize
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+void
+eMrubyVM_finalize(CELLIDX idx)
+{
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		/* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿°ãã¾ã */
+	} /* end if VALID_IDX(idx) */
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+	syslog(LOG_EMERG, "end of mruby program");
+  mrb_close(VAR_mrb);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
+
+#include "tlsf.h"
+void*
+mrb_TECS_allocf(mrb_state *mrb, void *p, size_t size, void *ud)
+{
+	CELLCB	*p_cellcb= (CELLCB *)ud;
+  if (size == 0) {
+      cMalloc_free(p);
+      //tlsf_free(p);
+      return NULL;
+  }
+  else if (p){
+      //return tlsf_realloc(p,size);
+      return cMalloc_realloc(p, size);
+  }
+  else {
+      //return tlsf_malloc(size);
+      return cMalloc_malloc(size);
+  }
+}
+
+// p_cellcb ã¯ VM ã®ãã®
+// VM ã»ã«ã¿ã¤ãã«ãå¼ã³å£ call sMalloc cMalloc; ãè¨­ãã
+// mrb_TECS_allocf ãåç
+§
+MRB_API mrb_state*
+mrb_open_TECS( CELLCB *p_cellcb)
+{
+    return mrb_open_allocf(mrb_TECS_allocf, (void *)p_cellcb);
+};
+
+/*** ããã¼é¢æ° ***/
+#ifndef EV3_SOUND
+void _write(){}
+void _close(){}
+void _lseek(){}
+void _read(){}
+//void _fstat(){}
+//void _isatty(){}
+#endif
+
+//void _exit(){}
+//void _getpid(){}
+//void _kill(){}
+void _gettimeofday(){}
+void _fini(){}
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/sMruby.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/sMruby.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/sMruby.cdl	(revision 374)
@@ -0,0 +1,82 @@
+/*
+ *  Copyright (C) 2012 by Ubiquitous Computing and Networking Laboratory
+ *                Ritsumeikan Univ., JAPAN
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+namespace nMruby{
+  signature sMrubyVM {
+    /*
+     * åæåãã (ä»¥ä¸ã¾ã§å®äºãã)
+     *   mrb_open
+     *   VM_TECSInitializer  (TECS ããªãã¸ã®åæå)
+     *   mrb_read_irep       (ãã¤ãã³ã¼ãã®ç»é²)
+     */
+    bool_t initialize(void);
+
+    /*
+     * å®è¡ãã
+     * RETURN
+     *   true  æªå¦ç½®ã®ä¾å¤ããªã
+     *   false æªå¦ç½®ã®ä¾å¤ããã
+     *  initialize ã false ãè¿ããå ´åãrun, finalize ãå¼ã³åºãã¦ã¯ãªããªã
+     */
+    bool_t run(void);
+
+    /*
+     * é¢æ°ãå¼ã³ã ã
+     */
+    void funcall( [in,string]const char_t *name );
+
+    /*
+     * çµæåãã
+     *  run ã false ãè¿ããå ´åã§ãå¼ã³ã ããã¨
+     */
+    void finalize(void);
+
+  };
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/tecs_mruby.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/tecs_mruby.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/mruby/tecs_mruby.h	(revision 374)
@@ -1,4 +1,4 @@
 /*
- *  Copyright (C) 2008-2017 by TOPPERS Project
+ *  Copyright (C) 2008-2019 by TOPPERS Project
  *
  *  上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -46,30 +46,14 @@
 #include "mruby/irep.h"
 #include "mruby/dump.h"
+#include "mruby/proc.h"
 
 #include "TECSPointer.h"
 #include "TECSStruct.h"
 
-#if  ! defined( MRUBY_RELEASE_MAJOR ) || MRUBY_RELEASE_MAJOR == 1 && MRUBY_RELEASE_MINOR < 2
-#ifndef MRB_ARGS_REQ
-#define MRB_ARGS_REQ(n)     ARGS_REQ(n)
-#define MRB_ARGS_OPT(n)     ARGS_OPT(n)
-#define MRB_ARGS_ARG(n1,n2) ARGS_ARG(n1,n2)
-#define MRB_ARGS_REST()     ARGS_REST()
-#define MRB_ARGS_POST(n)    ARGS_POST(n)
-#define MRB_ARGS_KEY(n1,n2) ARGS_KEY(n1,n2)
-#define MRB_ARGS_BLOCK()    ARGS_BLOCK()
-#define MRB_ARGS_ANY()      ARGS_ANY()
-#define MRB_ARGS_NONE()     ARGS_NONE()
-#endif /* MRB_ARGS_REQ */
-#endif
 
-#if  ! defined( MRUBY_RELEASE_MAJOR )
-#define mrb_float_value( mrb, val )  mrb_float_value( val )
-#endif
-
-#else
+#else /* TECSGEN */
 
 /*
- * fake tecsgen because tecsgen cannot accept actual mruby.h in case of below.
+ * fake definition because tecsgen cannot accept actual mruby.h in case of below.
  *   types:   long long, long long int
  *   special keyword __attribute__(x), __extension__
@@ -78,8 +62,15 @@
 typedef int mrb_irep;
 typedef int mrb_context;
-struct  RClass {int dummy;};
-struct  RProc  {int dummy;};
+struct  RClass {uint32_t gcnext;};  // actual definition: struct RBasic *gcnext
+struct  RProc  {uint32_t gcnext;};  // actual definition: struct RBasic *gcnext
 
 typedef int CELLCB;
+
+#define GET_SET_BOOL( Type, type )
+#define GET_SET_CHAR( Type, type )
+#define GET_SET_INT( Type, type )
+#define GET_SET_FLOAT( Type, type )
+#define POINTER_CLASS( Type, type )
+#define CHECK_AND_GET_POINTER( Type, type )
 
 #endif /* TECSGEN */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/TDR.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/TDR.cdl	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/TDR.cdl	(revision 374)
@@ -68,9 +68,4 @@
 	ER	sendSOP( [in]bool_t b_client );     /* StartOfPacket magic を送信 */
 	ER	receiveSOP( [in]bool_t b_client );  /* StartOfPacket magic を受信 */
-						 /* b_client: クライアント側なら true, サーバー側なら false */
-
-	/* マジックコードの送受信 */
-	//	ER	sendSHSOP( [in]bool_t b_client );     /* StartOfPacket magic を送信 */
-	//	ER	receiveSHSOP( [in]bool_t b_client );  /* StartOfPacket magic を受信 */
 						 /* b_client: クライアント側なら true, サーバー側なら false */
 
@@ -150,5 +145,5 @@
 };
 
-// Straight Order TECS Data Representation (Straight means no endian-conversion is done)
+// Straight Byte Order TECS Data Representation (Data are always sent in native endian)
 celltype tTDR {
 	call	sChannel	cChannel;
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/sChannel.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/sChannel.cdl	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/sChannel.cdl	(revision 374)
@@ -58,2 +58,10 @@
 };
 
+/*
+ * size に uint16_t ではなく int16_t を用いるのは、下位層が ER_INT を返す場合を想定したもの．
+ *
+ * sChannel は TECS RPC の TDR の下位層である通信チャンネルとのインタフェースである．
+ * 通信チャンネルは、高水準 I/O のように、バッファリングされることを想定する．
+ * TDR からは、int8_t, int16_t, int32_t, int64_t, (int128_t), float32_t, double64_t bool_t, char_t のような基本型(無符号を含む)が渡される。
+ * 配列や構造体の場合であっても要素ごとに渡される。
+ */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferCEP.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferCEP.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferCEP.cdl	(revision 374)
@@ -0,0 +1,85 @@
+/*
+ *  TECS Generator
+ *      Generator for TOPPERS Embedded Component System
+ *  
+ *   Copyright (C) 2008-2013 by TOPPERS Project
+ *--
+ *   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *       ã¨ï¼
+ *     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *         å ±åãããã¨ï¼
+ *   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *       å
+è²¬ãããã¨ï¼
+ *  
+ *   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *   ã®è²¬ä»»ãè² ããªãï¼
+ *  
+ *   $Id$
+ */
+
+const uint16_t DEFAULT_MESSAGE_BUFFER_SIZE = 64;
+
+celltype tMessageBufferCEP {
+    [inline]
+        entry sChannel eChannel;
+    call  sMessageBuffer cMessageBuffer0;   /* Client(send) --> Server(receive) */
+    call  sMessageBuffer cMessageBuffer1;   /* Server(send) --> Client(receive) */
+
+    attr {
+        uint16_t  buf_size = DEFAULT_MESSAGE_BUFFER_SIZE;
+        /* ãã®å¤ã¯ maxMessageSize ã«åããããå°ããã¨ããããã¡ãªã¼ãã¼ã©ã³ã«ãªã */
+    };
+    var {
+        /*
+         * OpaqueMarshalerPlugin ã®çæãããã¼ã·ã£ã©ã¯ãåä¿¡ããããµã¤ãºä»¥ä¸ã®é åãç¢ºä¿ããªãï¼
+         * ä¸æ¹ãtMessageBuffer ã¯ãæå¤§ maxMessageSize èª­ã¿åºãããï¼
+         * åä¿¡ããå´ã¯ãå¿
+ã maxMessageSize ãç¨æãã¦ããå¿
+è¦ãããï¼
+         * ãã®ããããã£ãããããã¡ã¸åãåã£ã¦ã³ãã¼ããå¿
+è¦ãããï¼
+         */
+        [size_is(buf_size)]
+            int8_t *read_buf;
+        uint16_t   read_count;
+        uint16_t   n_read_buf_filled;
+
+        [size_is(buf_size)]
+            int8_t *write_buf;
+        uint16_t   write_count;
+    };
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferCEP_inline.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferCEP_inline.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferCEP_inline.h	(revision 374)
@@ -0,0 +1,203 @@
+#ifndef tMessageBufferCEP__INLINE_H
+#define tMessageBufferCEP__INLINE_H
+
+/* #[<PREAMBLE>]#
+ * #[<...>]# ãã #[</...>]# ã§å²ã¾ããã³ã¡ã³ãã¯ç·¨éããªãã§ãã ãã
+ * tecsmerge ã«ãããã¼ã¸ã«ä½¿ç¨ããã¾ã
+ *
+ * å¼ã³å£é¢æ° #_TCPF_#
+ * call port: cMessageBuffer0 signature: sMessageBuffer context:task
+ *   ER             cMessageBuffer0_send( const uint8_t* message, uint32_t size );
+ *   ER             cMessageBuffer0_sendPolling( const uint8_t* message, uint32_t size );
+ *   ER             cMessageBuffer0_sendTimeout( const uint8_t* message, uint32_t size, TMO timeout );
+ *   ER_UINT        cMessageBuffer0_receive( uint8_t* message );
+ *   ER_UINT        cMessageBuffer0_receivePolling( uint8_t* message );
+ *   ER_UINT        cMessageBuffer0_receiveTimeout( uint8_t* message, TMO timeout );
+ *   ER             cMessageBuffer0_initialize( );
+ *   ER             cMessageBuffer0_refer( T_RMBF* pk_messageBufferStatus );
+ * call port: cMessageBuffer1 signature: sMessageBuffer context:task
+ *   ER             cMessageBuffer1_send( const uint8_t* message, uint32_t size );
+ *   ER             cMessageBuffer1_sendPolling( const uint8_t* message, uint32_t size );
+ *   ER             cMessageBuffer1_sendTimeout( const uint8_t* message, uint32_t size, TMO timeout );
+ *   ER_UINT        cMessageBuffer1_receive( uint8_t* message );
+ *   ER_UINT        cMessageBuffer1_receivePolling( uint8_t* message );
+ *   ER_UINT        cMessageBuffer1_receiveTimeout( uint8_t* message, TMO timeout );
+ *   ER             cMessageBuffer1_initialize( );
+ *   ER             cMessageBuffer1_refer( T_RMBF* pk_messageBufferStatus );
+ *
+ * #[</PREAMBLE>]# */
+
+/* åãå£é¢æ° #_TEPF_# */
+/* #[<ENTRY_PORT>]# eChannel
+ * entry port: eChannel
+ * signature:  sChannel
+2 * context:    task
+ * #[</ENTRY_PORT>]# */
+
+/* #[<ENTRY_FUNC>]# eChannel_send
+ * name:         eChannel_send
+ * global_name:  tMessageBufferCEP_eChannel_send
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eChannel_send(CELLIDX idx, const int8_t* buf, int16_t size, TMO tmo)
+{
+	ER		ercd = E_OK;
+  int16_t write_count;
+    CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( size < 0 )
+      return E_PAR;
+  else if( size == 0 )
+      return E_OK;
+
+  write_count = 0;
+  while( write_count < size ){
+      VAR_write_buf[ VAR_write_count++ ] = buf[ write_count++ ];
+      if( VAR_write_count >= ATTR_buf_size ){
+          ercd = eChannel_flush( idx, tmo);
+          if( ercd != E_OK ){
+              break;
+          }
+      }
+  }
+
+  // syslog( LOG_INFO, "eChannel_send ercd=%d", ercd );
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eChannel_flush
+ * name:         eChannel_flush
+ * global_name:  tMessageBufferCEP_eChannel_flush
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eChannel_flush(CELLIDX idx, TMO tmo)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  /* flush ããªãã¦ãããã¤ãéããã */
+  if( VAR_write_count > 0 ){
+      ercd = cMessageBuffer0_sendTimeout( (const uint8_t *)VAR_write_buf, VAR_write_count, tmo );
+  }
+  // syslog( LOG_INFO, "eChannel_flush ercd=%d count=%d", ercd, VAR_write_count );
+  VAR_write_count = 0;
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eChannel_receive
+ * name:         eChannel_receive
+ * global_name:  tMessageBufferCEP_eChannel_receive
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER_UINT
+eChannel_receive(CELLIDX idx, int8_t* buf, int16_t size, TMO tmo)
+{
+	ER		   ercd = E_OK;
+	CELLCB	 *p_cellcb;
+  int16_t  count = 0;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  if( size == 0 )
+      return 0;
+
+  while( count < size ){
+      if( VAR_n_read_buf_filled == 0 ){
+          ercd = cMessageBuffer1_receiveTimeout( (uint8_t *)VAR_read_buf, tmo );
+          if( ercd < 0  )
+              break;
+          VAR_n_read_buf_filled = ercd;
+      }
+      while( count < size && VAR_read_count < VAR_n_read_buf_filled ){
+          buf[ count ] = VAR_read_buf[ VAR_read_count ];
+          count++;
+          VAR_read_count++;
+      }
+      if( VAR_read_count >= VAR_n_read_buf_filled ){
+          VAR_n_read_buf_filled = 0;
+          VAR_read_count = 0;
+      }
+      ercd = count;
+  }
+  // syslog( LOG_INFO, "eChannel_receive ercd=%d", ercd );
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eChannel_end_receive
+ * name:         eChannel_end_receive
+ * global_name:  tMessageBufferCEP_eChannel_end_receive
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eChannel_end_receive(CELLIDX idx)
+{
+	ER		ercd = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+
+	return(ercd);
+}
+
+/* #[<ENTRY_FUNC>]# eChannel_reset
+ * name:         eChannel_reset
+ * global_name:  tMessageBufferCEP_eChannel_reset
+ * oneway:       false
+ * #[</ENTRY_FUNC>]# */
+Inline ER
+eChannel_reset(CELLIDX idx)
+{
+  ER		ercd0 = E_OK, ercd1 = E_OK;
+	CELLCB	*p_cellcb;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
+
+	/* ããã«å¦çæ¬ä½ãè¨è¿°ãã¾ã #_TEFB_# */
+  ercd0 = cMessageBuffer0_initialize( );
+  ercd1 = cMessageBuffer1_initialize( );
+
+	return(ercd1 != E_OK ? ercd1 : ercd0);
+}
+
+/* #[<POSTAMBLE>]#
+ *   ããããä¸ã«éåãå£é¢æ°ãæ¸ãã¾ã
+ * #[</POSTAMBLE>]#*/
+
+#endif /* tMessageBufferCEP_INLINEH */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferChannel.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferChannel.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tMessageBufferChannel.cdl	(revision 374)
@@ -0,0 +1,88 @@
+/*
+ *  TECS Generator
+ *      Generator for TOPPERS Embedded Component System
+ *  
+ *   Copyright (C) 2014 by Embedded and Real-Time Systems Laboratory
+ *               Graduate School of Information Science, Nagoya Univ., JAPAN
+ *--
+ *   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *       ã¨ï¼
+ *     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *         å ±åãããã¨ï¼
+ *   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *       å
+è²¬ãããã¨ï¼
+ *  
+ *   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *   ã®è²¬ä»»ãè² ããªãï¼
+ *  
+ *   $Id$
+ */
+
+composite tMessagebufferChannel {
+    //entry sTDR       eTDR;
+    entry sEventflag eEventflag;
+    entry sSemaphore eSemaphore;
+    entry sMessageBuffer eMessageBuffer;
+
+    attr {
+        // Queue ã®ããã©ã«ãã®ãµã¤ãº
+        uint32_t	bufferSize = 256;
+    };
+
+    cell  tMessageBuffer Messagebuffer{
+        maxMessageSize = 128;
+        bufferSize = composite.bufferSize;
+    };
+    cell  tEventflag Eventflag{
+        flagPattern = 0;
+    };
+    cell tSemaphore Semaphore{
+        attribute = C_EXP("TA_NULL");
+        initialCount = 0;
+    };
+
+    //cell  tTDR TDR {
+    //	cChannel = MessagebufferAdaptor.eChannel;
+    //};
+
+    //composite.eTDR       => TDR.eTDR;
+    composite.eEventflag => Eventflag.eEventflag;
+    composite.eSemaphore => Semaphore.eSemaphore;
+    composite.eMessageBuffer => Messagebuffer.eMessageBuffer;
+
+};
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tTDR_inline.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tTDR_inline.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/rpc/tTDR_inline.h	(revision 374)
@@ -75,4 +75,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	syslog( LOG_INFO, "TDR: resetting channel" );
@@ -102,4 +103,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -151,4 +153,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -157,5 +160,5 @@
 #endif
 
-    if( b_client )
+  if( b_client )
 		p_sopMagic = &SOP_MAGIC2;
 	else
@@ -198,4 +201,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -234,4 +238,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -267,4 +272,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -287,4 +293,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -307,4 +314,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -327,4 +335,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -347,4 +356,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -368,4 +378,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -390,4 +401,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -412,4 +424,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -434,4 +447,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -456,4 +470,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -477,4 +492,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -497,4 +513,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -517,4 +534,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -537,4 +555,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -557,4 +576,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -578,4 +598,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -600,4 +621,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -622,4 +644,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -644,4 +667,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -666,4 +690,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -688,4 +713,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -705,11 +731,12 @@
 	ER		ercd = E_OK;
 	CELLCB	*p_cellcb;
-	uint8_t	val;
-	if (VALID_IDX(idx)) {
-		p_cellcb = GET_CELLCB(idx);
-	}
-	else {
-		return(E_ID);
-	} /* end if VALID_IDX(idx) */
+	uint8_t	val = 0;
+	if (VALID_IDX(idx)) {
+		p_cellcb = GET_CELLCB(idx);
+	}
+	else {
+		return(E_ID);
+	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -737,4 +764,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -757,4 +785,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -778,4 +807,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -800,4 +830,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -821,4 +852,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -863,4 +895,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -883,4 +916,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -903,4 +937,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -923,4 +958,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -944,4 +980,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -966,4 +1003,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -988,4 +1026,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1010,4 +1049,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1031,4 +1071,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1051,4 +1092,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1071,4 +1113,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1091,4 +1134,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1112,4 +1156,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1134,4 +1179,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1156,4 +1202,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1178,4 +1225,5 @@
 		return(E_ID);
 	} /* end if VALID_IDX(idx) */
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1199,4 +1247,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
@@ -1220,4 +1269,5 @@
 		return(E_ID);
 	}
+  (void)p_cellcb;   // to avoid unused warning
 
 	/* ここに処理本体を記述します #_TEFB_# */
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/sMalloc.cdl
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/sMalloc.cdl	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecs/sMalloc.cdl	(revision 374)
@@ -0,0 +1,61 @@
+/*
+ *  Copyright (C) 2012 by Ubiquitous Computing and Networking Laboratory
+ *                Ritsumeikan Univ., JAPAN
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id$
+ */
+
+import_C( "t_stddef.h" );
+
+[deviate]
+signature sMalloc {
+    int    initializeMemoryPool(void);
+    void   *calloc( [in]size_t nelem, [in]size_t elem_size );
+    void   *malloc( [in]size_t size );
+    void   *realloc( [in]const void *ptr, [in]size_t new_size );
+    void   free( [in]const void *ptr );
+};
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecsgen.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecsgen.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecsgen.rb	(revision 374)
@@ -5,5 +5,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2017 by TOPPERS Project
+#   Copyright (C) 2008-2019 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -54,5 +54,5 @@
 #  Authors list is in i-ro-ha order.
 #Version::   see version.rb
-$Copyright = "Copyright(c) 2008-2017, TOPPERS project. All rights reserved."
+$Copyright = "Copyright(c) 2008-2019, TOPPERS project. All rights reserved."
 $License   = "TOPPERS License"
 
@@ -223,5 +223,7 @@
     analyze_option addtional_option_parser
     load_modules
-    setup
+    if ! $TECSFLOW then
+      setup
+    end
         
     dbgPrint  "tecspath: #{$tecsgen_base_path}, __FILE__=#{__FILE__}\n"
@@ -284,5 +286,6 @@
     ARGV.each { |a| $arguments += " " + a }
 
-    $unopt     = false     # bool:   disable optimizing
+    $unopt     = false     # bool:   disable optimizing both call and entry port
+    $unopt_entry= false    # bool:   disable optimizing entry port
     $gen_base  = "gen"     # string: folder path to place generated files
     $gen       = $gen_base # string: folder path to place generated files
@@ -385,4 +388,7 @@
         $unopt = true
       }
+      parser.on('--unoptimize-entry', 'unoptimize entry port') {
+        $unopt_entry = true
+      }
       parser.on('-c', '--cpp=cpp_cmd', 'C pre-processor command used import_C (default: gcc -E -DTECSGEN), you can also specify by environment variable TECS_CPP' ){
         |arg|
@@ -465,5 +471,5 @@
     }
 
-    if ARGV.empty? && ! $print_version && ! $unit_test
+    if ARGV.empty? && ! $print_version && ! $unit_test && ! $TECSFLOW
       ARGV.options{|parser|
         puts parser.help
@@ -482,6 +488,6 @@
     # このファイルを誤って読み込むと、異なるバージョン名を表示してしまう
     require_tecsgen_lib 'tecslib/version.rb'
-    if $tecscde_version then
-      STDERR << "tecscde version #{$tecscde_version} (tecsgen version #{$version})  #{$Copyright}\n"
+    if $title then
+      STDERR << "#{$title} version #{$tool_version} (tecsgen version #{$version})  #{$Copyright}\n"
     elsif ! $no_banner || $print_version
       STDERR << "tecsgen  version #{$version}  #{$Copyright}\n"
@@ -490,5 +496,5 @@
       STDERR << "ruby #{RUBY_VERSION} (#{RUBY_RELEASE_DATE} patchlevel #{RUBY_PATCHLEVEL}) [#{RUBY_PLATFORM}]\n"
     end
-    if $print_version && ARGV.empty?
+    if $print_version && ARGV.empty? && ! $TECSFLOW
       exit
     end
@@ -518,4 +524,5 @@
     require_tecsgen_lib 'tecslib/core/tool_info.rb'
     require_tecsgen_lib 'tecslib/core/tecsinfo.rb'
+    require_tecsgen_lib 'tecslib/core/unjoin_plugin.rb'
     require_tecsgen_lib 'tecslib/plugin/CelltypePlugin.rb'
     require_tecsgen_lib 'tecslib/plugin/CompositePlugin.rb'
@@ -601,5 +608,5 @@
 #  クラス変数のリセットを確実に行う必要がある
 
-if $TECSCDE != true then
+if $TECSCDE != true && $TECSFLOW != true then
   begin
     TECSGEN.init
@@ -607,4 +614,5 @@
     tecsgen.run1
     tecsgen.run2
+    tecsgen.dump_tecsgen_rbdmp
   rescue => evar
     print_exception( evar )
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecsgen_rcov.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecsgen_rcov.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecsgen_rcov.rb	(revision 374)
@@ -44,6 +44,9 @@
 # Usage: tecsgen_rcov.rb [options] CDL-file.cdl
 #
+
+$:.unshift(File.dirname(__FILE__))
+
 require 'simplecov'
-SimpleCov.command_name "tecsgen#{$$}"
+SimpleCov.command_name "tecsgen#{Time.now.to_f}"
 SimpleCov.root File.dirname( File.expand_path __FILE__ )
 SimpleCov.at_exit do
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/C_parser.tab.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/C_parser.tab.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/C_parser.tab.rb	(revision 374)
@@ -1,5 +1,5 @@
 #
 # DO NOT MODIFY!!!!
-# This file is automatically generated by Racc 1.4.14
+# This file is automatically generated by Racc 1.4.9
 # from Racc grammer file "".
 #
@@ -8,293 +8,300 @@
 class C_parser < Racc::Parser
 
-module_eval(<<'...end C_parser.y.rb/module_eval...', 'C_parser.y.rb', 727)
-
-  RESERVED = {
-    # keyword
-    'typedef' => :TYPEDEF,
-    'struct' => :STRUCT,
-    'union' => :UNION,
-    'sizeof' => :SIZEOF,
-    'throw' => :THROW,
-
-    # specifier
-    # types
-    'void'    => :VOID,
-    'char'    => :CHAR,
-    'short'   => :SHORT,
-
-    'volatile'=> :VOLATILE,
-    'const'   => :CONST,
-    'extern'   => :EXTERN,
-
-    'long'    => :LONG,
-    'float'   => :FLOAT,
-    'double'  => :DOUBLE,
-    'signed'  => :SIGNED,
-    'unsigned'=> :UNSIGNED,
-
-    'int'     => :INT,
-    'enum'    => :ENUM,
-
-    'if'      => :IF,
-    'else'    => :ELSE,
-    'while'   => :WHILE,
-    'do'      => :DO,
-    'for'     => :FOR,
-    'case'    => :CASE,
-    'default' => :DEFAULT,
-    'goto'    => :GOTO,
-    'continue' => :CONTINUE,
-    'break'   => :BREAK,
-    'return'  => :RETURN,
-    '__inline__'  => :__INLINE__,
-    'inline'  => :INLINE,
-    '__inline'  => :__INLINE,
-    'Inline'  => :CINLINE,        # inline starting with Capital letter
-    'static'  => :STATIC,
-    'register' => :REGISTER,
-    'auto'    => :AUTO,
-    '__extension__'    => :EXTENSION,
-
-  }
-
-  @@generator_nest = -1
-  @@generator_stack = []
-  @@current_locale = []
-
-  def finalize
-
-    # mikan Namespace.pop
-    Celltype.pop
-    Cell.pop
-    CompositeCelltype.pop
-    Region.pop
-
-  end
-
-  def set_plugin( plugin )
-    @plugin = plugin
-  end
-
-  def self.get_plugin
-    @@generator_stack[@@generator_nest].get_plugin
-  end
-
-  def get_plugin
-    @plugin
-  end
-
-  def parse(files)
-
-    # mikan Namespace.push
-    Celltype.push
-    Cell.push
-    CompositeCelltype.push
-    Region.push
-
-    @@generator_nest += 1
-    @@generator_stack[@@generator_nest] = self
-    @b_no_type_name = false
-
-   begin
-
-    @q = []
-    comment = false
-
-    # euc のコメントを utf8 として扱うと、コメントの終わりを誤る問題の対策
-    TECS_LANG::set_kcode_binary
-
-    # 800U, 0xffLL など (整数リテラルに共通の修飾子)
-    integer_qualifier = "([Uu][Ll][Ll]|[Uu][Ll]|[Uu]|[Ll][Ll]|[Ll])?"
-
-    files.each {|file|
-      lineno = 1
-     begin
-#2.0       IO.foreach(file) {|line|
-       TECSIO.foreach(file) {|line|
-        col = 1
-        line.rstrip!
-
-        until line.empty?
-
-          if comment
-            case line
-            # コメント終了
-            when /\A\*\//
-              comment = false
-            when /\A./
-              ;
-            end
-          else
-            case line
-            # 空白、プリプロセスディレクティブ
-            when /\A\s+/
-              ;
-            # 識別子
-            when /\A[a-zA-Z_]\w*/
-              word = $&
-              @q << [RESERVED[word] || :IDENTIFIER, Token.new(word.intern, file, lineno, col)]
-            # 16 進数定数
-            when /\A0x[0-9A-Fa-f]+#{integer_qualifier}/
-              @q << [:HEX_CONSTANT, Token.new($&, file, lineno, col)]
-            # 8 進数定数
-            when /\A0[0-7]+#{integer_qualifier}/
-              @q << [:OCTAL_CONSTANT, Token.new($&, file, lineno, col)]
-            # 浮動小数定数
-            when /\A[0-9]+\.([0-9]*)?([Ee][+-]?[0-9]+)?/
-              @q << [:FLOATING_CONSTANT, Token.new($&, file, lineno, col)]
-            # 整数定数
-            when /\A\d+#{integer_qualifier}/
-            # when /\A\d+/
-              @q << [:INTEGER_CONSTANT, Token.new($&.to_i, file, lineno, col)]
-            # 文字
-            when /\A'(?:[^'\\]|\\.)'/
-              @q << [:CHARACTER_LITERAL, Token.new($&, file, lineno, col)]
-            # 文字列
-#              "#include  #include #include \"../systask/logtask.cfg\"       最後の " 忘れ)で無限ループ
-#            when /\A"(?:[^"\\]+|\\.)*"/
-            when /\A"(?:[^"\\]|\\.)*"/   # これはうまく行くようだ
-              @q << [:STRING_LITERAL, Token.new($&, file, lineno, col)]
-            # 行コメント
-            when /\A\/\/.*$/
-              # 読み飛ばすだけ
-            # コメント開始
-            when /\A\/\*/
-              comment = true
-            when /\A>>=/, /\A<<=/, /\A>>/,  /\A<</
-              @q << [$&, Token.new($&, file, lineno, col)]
-            when /\A\+=/, /\A\-=/, /\A\*=/, /\A\/=/, /\A%=/, /\A&=/, /\A\|=/, /\A\^=/
-              @q << [$&, Token.new($&, file, lineno, col)]
-            when /\A::/, /\A==/, /\A!=/, /\A>=/, /\A<=/, /\A\->/, /\A\+\+/, /\A\-\-/
-              @q << [$&, Token.new($&, file, lineno, col)]
-            when /\A./
-              @q << [$&, Token.new($&, file, lineno, col)]
-            else
-              raise
-            end
-          end
-
-          line = $'
-          col += $&.length
-        end
-
-        lineno += 1
-      }
-
-     rescue => evar
-       Generator.error( "B1002 while open or reading \'$1\'" , file )
-       print_exception( evar )
-     end
-    }
-
-    # 終了の印
-    @q << nil
-
-    @yydebug = true
-    do_parse
-
-   ensure
-    @@generator_nest -= 1
-    TECS_LANG::reset_kcode
-   end
-
-  end
-
-
-  def next_token
-    token = @q.shift
-
-    if token then
-      @@current_locale[@@generator_nest] = token[1].locale
-
-      case token[1].val
-      when ";", ":", ",", "(", ")", "{", "}"
-        set_no_type_name false
-      when ".", "->"
-        set_no_type_name true
-      end
-
-      # TYPE_NAME トークンへ置き換え
-      if @b_no_type_name == false
-        if token[0] == :IDENTIFIER && Namespace.is_typename?( token[1].val ) then
-          token[0] = :TYPE_NAME
-          locale = @@current_locale[@@generator_nest]
+module_eval(<<'...end C_parser.y.rb/module_eval...', 'C_parser.y.rb', 784)
+
+	RESERVED = {
+		# keyword
+		'typedef' => :TYPEDEF,
+		'struct' => :STRUCT,
+		'union' => :UNION,
+		'sizeof' => :SIZEOF,
+		'throw' => :THROW,
+
+		# specifier
+		# types
+		'void'    => :VOID,
+		'char'    => :CHAR,
+		'short'   => :SHORT,
+
+		'volatile'=> :VOLATILE,
+		'restrict'=> :RESTRICT,
+		'const'   => :CONST,
+		'extern'   => :EXTERN,
+
+		'long'    => :LONG,
+		'float'   => :FLOAT,
+		'double'  => :DOUBLE,
+		'signed'  => :SIGNED,
+		'unsigned'=> :UNSIGNED,
+
+		'int'     => :INT,
+		'enum'    => :ENUM,
+
+		'if'      => :IF,
+		'else'    => :ELSE,
+		'while'   => :WHILE,
+		'do'      => :DO,
+		'for'     => :FOR,
+		'switch'  => :SWITCH,
+		'case'    => :CASE,
+		'default' => :DEFAULT,
+		'goto'    => :GOTO,
+		'continue' => :CONTINUE,
+		'break'   => :BREAK,
+		'return'  => :RETURN,
+		'__inline__'  => :__INLINE__,
+		'inline'  => :INLINE,
+		'__inline'  => :__INLINE,
+		'Inline'  => :CINLINE,        # inline starting with Capital letter
+		'static'  => :STATIC,
+		'register' => :REGISTER,
+		'auto'    => :AUTO,
+		'__extension__'    => :EXTENSION,
+		'__asm__' => :_ASM,
+		'asm' =>     :_ASM
+
+	}
+
+	@@generator_nest = -1
+	@@generator_stack = []
+	@@current_locale = []
+
+	def finalize
+
+		# mikan Namespace.pop
+		Celltype.pop
+		Cell.pop
+		CompositeCelltype.pop
+		Region.pop
+
+	end
+
+	def set_plugin( plugin )
+		@plugin = plugin
+	end
+
+	def self.get_plugin
+		@@generator_stack[@@generator_nest].get_plugin
+	end
+
+	def get_plugin
+		@plugin
+	end
+
+	def parse(files)
+
+		# mikan Namespace.push
+		Celltype.push
+		Cell.push
+		CompositeCelltype.push
+		Region.push
+
+		@@generator_nest += 1
+		@@generator_stack[@@generator_nest] = self
+		@b_no_type_name = false
+
+	begin
+
+		@q = []
+		comment = false
+#		b_asm   = false
+
+		# euc のコメントを utf8 として扱うと、コメントの終わりを誤る問題の対策
+		TECS_LANG::set_kcode_binary
+
+		# 800U, 0xffLL など (整数リテラルに共通の修飾子)
+		integer_qualifier = "([Uu][Ll][Ll]|[Uu][Ll]|[Uu]|[Ll][Ll]|[Ll])?"
+
+		files.each {|file|
+			lineno = 1
+		begin
+#2.0		IO.foreach(file) {|line|
+			TECSIO.foreach(file) {|line|
+			col = 1
+			line.rstrip!
+
+			until line.empty?
+
+				if comment
+					case line
+					# コメント終了
+					when /\A\*\//
+						comment = false
+					when /\A./
+						;
+					end
+				else
+					case line
+					# 空白、プリプロセスディレクティブ
+					when /\A\s+/
+						;
+					# 識別子
+					when /\A[a-zA-Z_]\w*/
+						word = $&
+						@q << [RESERVED[word] || :IDENTIFIER, Token.new(word.intern, file, lineno, col)]
+					# 16 進数定数
+					when /\A0x[0-9A-Fa-f]+#{integer_qualifier}/
+						@q << [:HEX_CONSTANT, Token.new($&, file, lineno, col)]
+					# 8 進数定数
+					when /\A0[0-7]+#{integer_qualifier}/
+						@q << [:OCTAL_CONSTANT, Token.new($&, file, lineno, col)]
+					# 浮動小数定数
+					when /\A[0-9]+\.([0-9]*)?([Ee][+-]?[0-9]+)?/
+						@q << [:FLOATING_CONSTANT, Token.new($&, file, lineno, col)]
+					# 整数定数
+					when /\A\d+#{integer_qualifier}/
+					# when /\A\d+/
+						@q << [:INTEGER_CONSTANT, Token.new($&.to_i, file, lineno, col)]
+					# 文字
+					when /\A'(?:[^'\\]|\\.)'/
+						@q << [:CHARACTER_LITERAL, Token.new($&, file, lineno, col)]
+					# 文字列
+#					"#include  #include #include \"../systask/logtask.cfg\"       最後の " 忘れ)で無限ループ
+#					when /\A"(?:[^"\\]+|\\.)*"/
+					when /\A"(?:[^"\\]|\\.)*"/   # これはうまく行くようだ
+						@q << [:STRING_LITERAL, Token.new($&, file, lineno, col)]
+					# 行コメント
+					when /\A\/\/.*$/
+						# 読み飛ばすだけ
+					# コメント開始
+					when /\A\/\*/
+						comment = true
+					when /\A>>=/, /\A<<=/, /\A>>/,  /\A<</
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A\+=/, /\A\-=/, /\A\*=/, /\A\/=/, /\A%=/, /\A&=/, /\A\|=/, /\A\^=/
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A::/, /\A==/, /\A!=/, /\A>=/, /\A<=/, /\A\->/, /\A\+\+/, /\A\-\-/
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A\|\|/, /\A\&\&/
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A./
+						@q << [$&, Token.new($&, file, lineno, col)]
+					else
+						raise
+					end
+				end
+
+				line = $'
+				col += $&.length
+			end
+
+			lineno += 1
+		}
+
+		rescue => evar
+			Generator.error( "B1002 while open or reading \'$1\'" , file )
+			print_exception( evar )
+		end
+	}
+
+	# 終了の印
+	@q << nil
+
+	@yydebug = true
+	do_parse
+
+		ensure
+			@@generator_nest -= 1
+			TECS_LANG::reset_kcode
+		end
+
+	end
+
+
+	def next_token
+		token = @q.shift
+
+		if token then
+			@@current_locale[@@generator_nest] = token[1].locale
+
+			case token[1].val
+			when ";", ":", ",", "(", ")", "{", "}"
+			set_no_type_name false
+			when ".", "->"
+			set_no_type_name true
+			end
+
+			# TYPE_NAME トークンへ置き換え
+			if @b_no_type_name == false
+				if token[0] == :IDENTIFIER && Namespace.is_typename?( token[1].val ) then
+					token[0] = :TYPE_NAME
+					locale = @@current_locale[@@generator_nest]
 #print( "#{locale[0]}: line #{locale[1]} : #{token[0]} '#{token[1].val}: type_name'\n" )
-        end
-      end
-
-      if $debug then     # 070107 token 無効時ここを通さないようした (through 対応 -d の時に例外発生) 
-        locale = @@current_locale[@@generator_nest]
-        if token then
-          print( "#{locale[0]}: line #{locale[1]} : #{token[0]} '#{token[1].val}'\n" )
-        else
-          print( "#{locale[0]}: line #{locale[1]} : EOF\n" )
-        end
-      end
-    end
-
-    token
-  end
-
-  def on_error(t, v, vstack)
-    if v == "$" then
-     Generator.error( "B1003 Unexpected EOF"  )
-    else
-     Generator.error( "B1004 syntax error near \'$1\'" , v.val )
-    end
-
-  end
-
-  def self.current_locale
-    @@current_locale[ @@generator_nest ]
-  end
-
-  @@n_error = 0
-  @@n_warning = 0
-  @@n_info = 0
-
-  # このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でエラー発生は不適切）
-  def self.error( msg )
-    @@n_error += 1
-    locale = @@current_locale[ @@generator_nest ]
-
-    if locale then
-      Console.puts "error: #{locale[0]}: line #{locale[1]} #{msg}"
-    else
-      Console.puts "error: #{msg}"
-    end
-  end
-
-  # このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でウォーニング発生は不適切）
-  def self.warning( msg )
-    @@n_warning += 1
-    locale = @@current_locale[ @@generator_nest ]
-    Console.puts "warning: #{locale[0]}: line #{locale[1]} #{msg}"
-  end
-
-  # このメソッドは構文解析、意味解析からのみ呼出し可
-  def self.info( msg )
-    @@n_info += 1
-    locale = @@current_locale[ @@generator_nest ]
-    Console.puts "info: #{locale[0]}: line #{locale[1]} #{msg}"
-  end
-
-  def self.get_n_error
-    @@n_error
-  end
-
-  def self.get_n_warning
-    @@n_warning
-  end
-
-  def self.get_nest
-    @@generator_nest
-  end
-
-  def set_no_type_name b_no_type_name
-    locale = @@current_locale[ @@generator_nest ]
+				end
+			end
+
+			if $debug then     # 070107 token 無効時ここを通さないようした (through 対応 -d の時に例外発生) 
+				locale = @@current_locale[@@generator_nest]
+				if token then
+					print( "#{locale[0]}: line #{locale[1]} : #{token[0]} '#{token[1].val}'\n" )
+				else
+					print( "#{locale[0]}: line #{locale[1]} : EOF\n" )
+				end
+			end
+		end
+
+		token
+	end
+
+	def on_error(t, v, vstack)
+		if v == "$" then
+			Generator.error( "B1003 Unexpected EOF"  )
+		else
+			Generator.error( "B1004 syntax error near \'$1\'" , v.val )
+		end
+
+	end
+
+	def self.current_locale
+		@@current_locale[ @@generator_nest ]
+	end
+
+	@@n_error = 0
+	@@n_warning = 0
+	@@n_info = 0
+
+	# このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でエラー発生は不適切）
+	def self.error( msg )
+		@@n_error += 1
+		locale = @@current_locale[ @@generator_nest ]
+
+		if locale then
+			Console.puts "#{locale[0]}:#{locale[1]}: error: #{msg}"
+		else
+			Console.puts "error: #{msg}"
+		end
+	end
+
+	# このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でウォーニング発生は不適切）
+	def self.warning( msg )
+		@@n_warning += 1
+		locale = @@current_locale[ @@generator_nest ]
+		Console.puts "warning: #{locale[0]}: line #{locale[1]} #{msg}"
+	end
+
+	# このメソッドは構文解析、意味解析からのみ呼出し可
+	def self.info( msg )
+		@@n_info += 1
+		locale = @@current_locale[ @@generator_nest ]
+		Console.puts "info: #{locale[0]}: line #{locale[1]} #{msg}"
+	end
+
+	def self.get_n_error
+		@@n_error
+	end
+
+	def self.get_n_warning
+		@@n_warning
+	end
+
+	def self.get_nest
+		@@generator_nest
+	end
+
+	def set_no_type_name b_no_type_name
+		locale = @@current_locale[ @@generator_nest ]
 #print "b_no_type_name=#{b_no_type_name} #{locale[0]}: line #{locale[1]}\n"
-    @b_no_type_name = b_no_type_name
-  end
+		@b_no_type_name = b_no_type_name
+	end
 
 ...end C_parser.y.rb/module_eval...
@@ -302,127 +309,145 @@
 
 clist = [
-'106,107,108,109,110,112,70,113,68,181,302,143,55,118,119,208,117,120',
-'121,122,123,124,125,106,107,108,109,110,112,337,113,209,336,210,143',
-'76,118,119,170,117,120,121,122,123,124,125,305,69,301,67,350,28,29,106',
-'107,108,109,110,112,75,113,28,29,162,143,77,118,119,170,117,120,121',
-'122,123,124,125,169,79,205,206,353,306,307,308,309,310,311,312,313,314',
-'315,264,55,144,8,9,10,11,15,16,17,18,19,20,21,174,267,23,25,27,28,29',
-'197,198,375,263,144,106,107,108,109,110,112,346,113,342,197,198,143',
-'173,118,119,153,117,120,121,122,123,124,125,106,107,108,109,110,112',
-'144,113,357,341,3,143,274,118,119,253,117,120,121,122,123,124,125,106',
-'107,108,109,110,112,54,113,199,200,361,143,53,118,119,98,117,120,121',
-'122,123,124,125,106,107,108,109,110,112,345,113,363,83,364,143,82,118',
-'119,346,117,120,121,122,123,124,125,81,144,249,83,274,253,82,253,53',
-'106,107,108,109,110,112,337,113,55,336,365,236,366,118,119,144,117,120',
-'121,122,123,124,125,54,249,367,194,253,97,53,53,195,196,81,199,200,55',
-'55,144,230,89,8,9,10,11,15,16,17,18,19,20,21,79,372,23,25,27,28,29,199',
-'200,144,231,88,232,233,234,235,87,237,238,240,241,242,243,194,377,194',
-'199,200,195,196,195,196,378,39,40,41,42,43,44,45,46,144,106,107,108',
-'109,110,112,379,113,205,206,380,143,381,118,119,382,117,120,121,122',
-'123,124,125,106,107,108,109,110,112,384,113,197,198,385,143,386,118',
-'119,65,117,120,121,122,123,124,125,106,107,108,109,110,112,62,113,391',
-'37,392,143,393,118,119,394,117,120,121,122,123,124,125,106,107,108,109',
-'110,112,61,113,211,212,396,143,398,118,119,280,117,120,121,122,123,124',
-'125,47,144,279,36,277,8,9,10,11,15,16,17,18,19,20,21,271,37,23,25,27',
-'28,29,270,144,38,8,9,10,11,15,16,17,18,19,20,21,199,200,23,25,27,28',
-'29,269,97,256,144,255,39,40,41,42,43,44,45,46,36,247,8,9,10,11,15,16',
-'17,18,19,20,21,144,246,23,25,27,28,29,245,32,38,106,107,108,109,110',
-'112,216,113,215,210,209,143,208,118,119,207,117,120,121,122,123,124',
-'125,39,40,41,42,43,44,45,46,303,106,107,108,109,110,112,316,113,317',
-'319,320,236,321,118,119,323,117,120,121,122,123,124,125,54,54,54,324',
-'54,325,53,53,53,326,53,329,176,55,55,55,230,55,8,9,10,11,15,16,17,18',
-'19,20,21,79,175,23,25,27,28,29,77,97,144,231,171,232,233,234,235,163',
-'237,238,240,241,242,243,183,348,184,349,185,186,187,207,,,39,40,41,42',
-'43,44,45,46,144,106,107,108,109,110,112,,113,,,,143,,118,119,,117,120',
-'121,122,123,124,125,,,106,107,108,109,110,112,,113,,,,236,,118,119,',
-'117,120,121,122,123,124,125,54,54,54,,54,,53,53,53,,53,,,55,55,55,230',
-'55,8,9,10,11,15,16,17,18,19,20,21,79,,23,25,27,28,29,,,,231,,232,233',
-'234,235,144,237,238,240,241,242,243,201,202,203,204,201,202,203,204',
-',,39,40,41,42,43,44,45,46,144,106,107,108,109,110,112,,113,,,,236,,118',
-'119,,117,120,121,122,123,124,125,54,201,202,203,204,,53,,,,,,,55,,,230',
-',8,9,10,11,15,16,17,18,19,20,21,79,,23,25,27,28,29,,,,231,,232,233,234',
-'235,,237,238,240,241,242,243,,,,,,,,,,,39,40,41,42,43,44,45,46,144,106',
-'107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123,124,125',
-'106,107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123,124',
-'125,106,107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123',
-'124,125,106,107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122',
-'123,124,125,,144,,,,,,,,106,107,108,109,110,112,,113,,,,143,,118,119',
-'144,117,120,121,122,123,124,125,106,107,108,109,110,112,,113,,368,,143',
-',118,119,144,117,120,121,122,123,124,125,,,,,,,,106,107,108,109,110',
-'112,,113,144,,,236,,118,119,,117,120,121,122,123,124,125,,,,,,,,,,,',
-',,,,,230,144,8,9,10,11,15,16,17,18,19,20,21,79,,23,25,27,28,29,,,,231',
-'144,232,233,234,235,,237,238,240,241,242,243,,,,,,,,,,,39,40,41,42,43',
-'44,45,46,144,106,107,108,109,110,112,,113,,,,236,,118,119,,117,120,121',
-'122,123,124,125,,,,,,,,,,,,,,,,,230,,8,9,10,11,15,16,17,18,19,20,21',
-'79,,23,25,27,28,29,,,,231,,232,233,234,235,,237,238,240,241,242,243',
-',,,,,,,,,,39,40,41,42,43,44,45,46,144,106,107,108,109,110,112,,113,',
-',,236,,118,119,,117,120,121,122,123,124,125,,,,,,,,,,,,,,,,,230,,8,9',
-'10,11,15,16,17,18,19,20,21,79,,23,25,27,28,29,,,,231,,232,233,234,235',
-',237,238,240,241,242,243,,,,,,,,,,,39,40,41,42,43,44,45,46,144,106,107',
-'108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123,124,125,106',
-'107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123,124,125',
-'106,107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123,124',
-'125,106,107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123',
-'124,125,,144,,,,,141,,,,,,,142,106,107,108,109,110,112,,113,,147,144',
-'143,,118,119,,117,120,121,122,123,124,125,106,107,108,109,110,112,,113',
-',,144,143,,118,119,,117,120,121,122,123,124,125,106,107,108,109,110',
-'112,,113,,,144,143,,118,119,,117,120,121,122,123,124,125,106,107,108',
-'109,110,112,,113,,,,143,,118,119,,117,120,121,122,123,124,125,,144,',
-',,,,,,106,107,108,109,110,112,,113,,,,143,,118,119,144,117,120,121,122',
-'123,124,125,106,107,108,109,110,112,,113,,,,143,,118,119,144,117,120',
-'121,122,123,124,125,106,107,108,109,110,112,,113,,,,143,,118,119,144',
-'117,120,121,122,123,124,125,106,107,108,109,110,112,,113,,,,143,,118',
-'119,,117,120,121,122,123,124,125,,144,,,,,141,351,,,,,,142,106,107,108',
-'109,110,112,,113,,,144,143,,118,119,,117,120,121,122,123,124,125,106',
-'107,108,109,110,112,,113,,,144,143,,118,119,,117,120,121,122,123,124',
-'125,106,107,108,109,110,112,,113,,,144,143,,118,119,,117,120,121,122',
-'123,124,125,106,107,108,109,110,112,,113,,,,143,,118,119,,117,120,121',
-'122,123,124,125,,144,,,,,,,,106,107,108,109,110,112,,113,,,,143,,118',
-'119,144,117,120,121,122,123,124,125,106,107,108,109,110,112,,113,,,',
-'143,,118,119,144,117,120,121,122,123,124,125,106,107,108,109,110,112',
-',113,,,,143,,118,119,144,117,120,121,122,123,124,125,,,,,,,,,,106,107',
-'108,109,110,112,,113,,,,236,,118,119,144,117,120,121,122,123,124,125',
-',,,,,,,,,,,,,,,144,230,,8,9,10,11,15,16,17,18,19,20,21,79,239,23,25',
-'27,28,29,,,144,231,,232,233,234,235,,237,238,240,241,242,243,,,,,,,',
-',,,39,40,41,42,43,44,45,46,144,106,107,108,109,110,112,,113,,338,,143',
-',118,119,,117,120,121,122,123,124,125,106,107,108,109,110,112,,113,',
-',,143,,118,119,,117,120,121,122,123,124,125,8,9,10,11,15,16,17,18,19',
-'20,21,,,23,25,27,28,29,8,9,10,11,15,16,17,18,19,20,21,,,23,25,27,28',
-'29,,106,107,108,109,110,112,,113,,,144,143,,118,119,,117,120,121,122',
-'123,124,125,106,107,108,109,110,112,,113,,,144,143,,118,119,,117,120',
-'121,122,123,124,125,106,107,108,109,110,112,,113,,,,143,,118,119,,117',
-'120,121,122,123,124,125,106,107,108,109,110,189,,113,,,,143,,118,119',
-',117,120,121,122,123,124,125,,144,,,,,,,,106,107,108,109,110,191,,113',
-',,,143,,118,119,144,117,120,121,122,123,124,125,106,107,108,109,110',
-'191,,113,,,,143,,118,119,144,117,120,121,122,123,124,125,106,107,108',
-'109,110,112,,113,,,,143,,118,119,144,117,120,121,122,123,124,125,106',
-'107,108,109,110,112,,113,,,,143,,118,119,,117,120,121,122,123,124,125',
-',144,,,,,141,,,,,,,142,,,328,,106,107,108,109,110,112,144,113,,,,143',
-',118,119,,117,120,121,122,123,124,125,,,,,,,144,,,,,,,,,,,106,107,108',
-'109,110,112,,113,,,,236,144,118,119,,117,120,121,122,123,124,125,,,',
-',,,,,,,,,,,,,230,,8,9,10,11,15,16,17,18,19,20,21,79,144,23,25,27,28',
-'29,,,,231,,232,233,234,235,,237,238,240,241,242,243,,,,,,,274,334,,253',
-'39,40,41,42,43,44,45,46,144,55,,,,,249,334,,253,,,53,,,,,,,55,,,,,8',
-'9,10,11,15,16,17,18,19,20,21,,,23,25,27,28,29,8,9,10,11,15,16,17,18',
-'19,20,21,,,23,25,27,28,29,370,,,,,,,,39,40,41,42,43,44,45,46,,,149,',
-',,,,,,39,40,41,42,43,44,45,46,,8,9,10,11,15,16,17,18,19,20,21,,,23,25',
-'27,28,29,8,9,10,11,15,16,17,18,19,20,21,,,23,25,27,28,29,,,,330,,,,',
-'39,40,41,42,43,44,45,46,,,,,,,,,,,39,40,41,42,43,44,45,46,8,9,10,11',
-'15,16,17,18,19,20,21,,,23,25,27,28,29,8,9,10,11,15,16,17,18,19,20,21',
-',,23,25,27,28,29,,,,,,,,,39,40,41,42,43,44,45,46,,,,,,,,,,,39,40,41',
-'42,43,44,45,46,8,9,10,11,15,16,17,18,19,20,21,,340,23,25,27,28,29,8',
-'9,10,11,15,16,17,18,19,20,21,,164,23,25,27,28,29,,,,,,,,,39,40,41,42',
-'43,44,45,46,,,,,,,,,,,39,40,41,42,43,44,45,46,8,9,10,11,15,16,17,18',
-'19,20,21,,,23,25,27,28,29,8,9,10,11,15,16,17,18,19,20,21,,,23,25,27',
-'28,29,,,,,,,,,39,40,41,42,43,44,45,46,,,,,,,,,,,39,40,41,42,43,44,45',
-'46,8,9,10,11,15,16,17,18,19,20,21,,,23,25,27,28,29,8,9,10,11,15,16,17',
-'18,19,20,21,,257,23,25,27,28,29,,,,,,,,,39,40,41,42,43,44,45,46,,,,',
-',,,,,,39,40,41,42,43,44,45,46,8,9,10,11,15,16,17,18,19,20,21,,,23,25',
-'27,28,29,8,9,10,11,15,16,17,18,19,20,21,,262,23,25,27,28,29,,,,,,,,',
-'39,40,41,42,43,44,45,46,,,,,,,,,,,39,40,41,42,43,44,45,46,8,9,10,11',
-'15,16,17,18,19,20,21,,,23,25,27,28,29,8,9,10,11,15,16,17,18,19,20,21',
-',,23,25,27,28,29,,,,,,,,,39,40,41,42,43,44,45,46,,,,,,,,,,,39,40,41',
-'42,43,44,45,46,8,9,10,11,15,16,17,18,19,20,21,,,23,25,27,28,29' ]
-        racc_action_table = arr = ::Array.new(2875, nil)
+'111,112,113,114,115,117,294,118,56,298,55,163,54,123,124,82,54,262,122',
+'125,126,127,128,129,130,111,112,113,114,115,117,217,118,271,391,101',
+'163,91,123,124,82,271,271,122,125,126,127,128,129,130,56,70,171,72,82',
+'69,397,71,80,32,33,34,224,309,271,223,216,226,84,227,228,229,84,392',
+'101,325,272,171,298,312,80,164,165,172,393,173,174,175,176,177,178,179',
+'180,149,181,101,218,79,308,369,388,32,33,34,265,266,164,165,172,73,173',
+'174,175,176,177,178,179,180,149,181,111,112,113,114,115,117,384,118',
+'32,33,34,163,78,123,124,82,440,402,122,125,126,127,128,129,130,55,219',
+'271,271,383,101,54,332,248,325,387,55,298,249,250,56,382,54,111,112',
+'113,114,115,117,56,118,56,171,331,163,395,123,124,82,276,210,122,125',
+'126,127,128,129,130,420,55,378,210,248,377,396,54,330,249,250,393,92',
+'164,165,172,56,173,174,175,176,177,178,179,180,149,181,171,9,10,11,12',
+'13,14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,355,356',
+'213,164,165,172,204,173,174,175,176,177,178,179,180,149,181,111,112',
+'113,114,115,117,404,118,93,378,203,163,377,123,124,82,193,271,122,125',
+'126,127,128,129,130,111,112,113,114,115,117,290,118,101,86,55,163,85',
+'123,124,82,54,291,122,125,126,127,128,129,130,56,357,171,13,14,15,16',
+'17,18,19,20,21,22,26,28,30,31,32,33,34,248,86,322,438,85,249,250,171',
+'434,435,370,164,165,172,271,173,174,175,176,177,178,179,180,149,181',
+'259,260,261,321,255,256,257,258,315,316,262,164,165,172,271,173,174',
+'175,176,177,178,179,180,149,181,111,112,113,114,115,117,403,118,317',
+'318,263,163,264,123,124,82,320,271,122,125,126,127,128,129,130,13,14',
+'15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,437,111,112,113,114,115',
+'117,360,118,400,171,271,163,368,123,124,82,166,103,122,125,126,127,128',
+'129,130,102,55,255,256,257,258,310,54,255,256,257,258,405,164,165,172',
+'56,173,174,175,176,177,178,179,180,149,181,171,9,10,11,12,13,14,15,16',
+'17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,259,260,301,164,165',
+'172,300,173,174,175,176,177,178,179,180,149,181,111,112,113,114,115',
+'117,408,118,253,254,292,163,409,123,124,82,253,254,122,125,126,127,128',
+'129,130,111,112,113,114,115,117,410,118,253,254,55,163,289,123,124,82',
+'54,288,122,125,126,127,128,129,130,56,415,171,13,14,15,16,17,18,19,20',
+'21,22,26,28,30,31,32,33,34,253,254,253,254,251,252,261,171,211,212,285',
+'164,165,172,284,173,174,175,176,177,178,179,180,149,181,237,238,239',
+'240,241,242,243,244,245,246,247,164,165,172,283,173,174,175,176,177',
+'178,179,180,149,181,111,112,113,114,115,117,282,118,251,252,389,163',
+'389,123,124,82,251,252,122,125,126,127,128,129,130,111,112,113,114,115',
+'117,101,118,67,82,55,163,64,123,124,82,54,63,122,125,126,127,128,129',
+'130,56,55,171,55,55,294,280,54,298,54,54,54,279,430,431,432,56,433,56',
+'56,56,365,436,278,263,275,264,171,273,270,48,164,165,172,444,173,174',
+'175,176,177,178,179,180,149,181,269,3,,,,,,,,,,164,165,172,,173,174',
+'175,176,177,178,179,180,149,181,111,112,113,114,115,117,,118,,,,163',
+',123,124,82,,,122,125,126,127,128,129,130,111,112,113,114,115,117,,118',
+',,,148,,123,124,,,,122,125,126,127,128,129,130,,,171,111,112,113,114',
+'115,117,,118,,,,148,,123,124,,,,122,125,126,127,128,129,130,,,,164,165',
+'172,,173,174,175,176,177,178,179,180,149,181,,,,,,,111,112,113,114,115',
+'117,,118,,411,,148,,123,124,,,149,122,125,126,127,128,129,130,,,,111',
+'112,113,114,115,117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129',
+'130,111,112,113,114,115,117,,118,,,,148,,123,124,,,,122,125,126,127',
+'128,129,130,,,171,,,,,,,,,,,,,149,,111,112,113,114,115,117,,118,,,171',
+'148,,123,124,,,,122,125,126,127,128,129,130,,149,,,,,,,,111,112,113',
+'114,115,117,,118,,,,148,,123,124,146,398,149,122,125,126,127,128,129',
+'130,111,112,113,114,115,117,,118,,,,148,,123,124,,,,122,125,126,127',
+'128,129,130,111,112,113,114,115,117,,118,,149,,148,,123,124,389,,,122',
+'125,126,127,128,129,130,,,,147,,,111,112,113,114,115,117,,118,,,,148',
+'149,123,124,,,,122,125,126,127,128,129,130,111,112,113,114,115,117,',
+'118,,379,,148,149,123,124,,,,122,125,126,127,128,129,130,,,,,,,,,,,',
+',149,,,,,111,112,113,114,115,117,,118,,,,148,,123,124,,,,122,125,126',
+'127,128,129,130,,149,,,,,,,,,,,,,,,,,,,,,,,,,149,171,9,10,11,12,13,14',
+'15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,111,112,113',
+'114,115,117,,118,,,,148,,123,124,149,,,122,125,126,127,128,129,130,111',
+'112,113,114,115,117,,118,,,,148,,123,124,146,,,122,125,126,127,128,129',
+'130,111,112,113,114,115,117,,118,,,,148,,123,124,,,,122,125,126,127',
+'128,129,130,,111,112,113,114,115,117,,118,,,,148,,123,124,,,149,122',
+'125,126,127,128,129,130,,,147,,,111,112,113,114,115,117,,118,,,,148',
+'149,123,124,,,,122,125,126,127,128,129,130,111,112,113,114,115,117,',
+'118,,,,148,149,123,124,,,,122,125,126,127,128,129,130,,111,112,113,114',
+'115,117,,118,,,,148,149,123,124,,,,122,125,126,127,128,129,130,111,112',
+'113,114,115,117,,118,,,,148,,123,124,146,,149,122,125,126,127,128,129',
+'130,111,112,113,114,115,117,427,118,,,,148,,123,124,,,149,122,125,126',
+'127,128,129,130,,111,112,113,114,115,117,,118,,,,148,,123,124,,,149',
+'122,125,126,127,128,129,130,,,147,,,111,112,113,114,115,117,,118,,185',
+',148,149,123,124,,,,122,125,126,127,128,129,130,111,112,113,114,115',
+'117,,118,,,,148,149,123,124,,,,122,125,126,127,128,129,130,,111,112',
+'113,114,115,117,,118,,,,148,149,123,124,,,,122,125,126,127,128,129,130',
+'111,112,113,114,115,117,,118,,,,148,,123,124,,,149,122,125,126,127,128',
+'129,130,111,112,113,114,115,117,,118,,,,148,,123,124,,,149,122,125,126',
+'127,128,129,130,,111,112,113,114,115,117,,118,,,,148,,123,124,,,149',
+'122,125,126,127,128,129,130,111,112,113,114,115,117,,118,,,,148,,123',
+'124,,,149,122,125,126,127,128,129,130,111,112,113,114,115,117,,118,',
+',,148,,123,124,,,149,122,125,126,127,128,129,130,,111,112,113,114,115',
+'117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129,130,111,112,113',
+'114,115,117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129,130,111',
+'112,113,114,115,117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129',
+'130,,111,112,113,114,115,117,,118,,,,148,,123,124,,,149,122,125,126',
+'127,128,129,130,111,112,113,114,115,117,,118,,,,148,,123,124,,,149,122',
+'125,126,127,128,129,130,111,112,113,114,115,117,,118,,,,148,,123,124',
+',,149,122,125,126,127,128,129,130,,111,112,113,114,115,117,,118,,,,148',
+',123,124,,,149,122,125,126,127,128,129,130,111,112,113,114,115,117,',
+'118,,,,148,,123,124,,,149,122,125,126,127,128,129,130,111,112,113,114',
+'115,117,,118,,,,148,,123,124,146,,149,122,125,126,127,128,129,130,,111',
+'112,113,114,115,117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129',
+'130,,,,,,,,,,,,,,,,,,149,,,,,,,,,,147,,,111,112,113,114,115,117,,118',
+',,,148,149,123,124,,,,122,125,126,127,128,129,130,,111,112,113,114,115',
+'117,,118,,,,148,149,123,124,,,,122,125,126,127,128,129,130,,,,,,,13',
+'14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,,,111,112,113,114,115',
+'117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129,130,,111,112',
+'113,114,115,231,,118,,,,148,,123,124,,,149,122,125,126,127,128,129,130',
+'111,112,113,114,115,233,,118,,,,148,,123,124,,,,122,125,126,127,128',
+'129,130,111,112,113,114,115,233,,118,,,,148,,123,124,,,149,122,125,126',
+'127,128,129,130,,,,,,,,,,,,,111,112,113,114,115,117,149,118,,,,148,',
+'123,124,,,,122,125,126,127,128,129,130,111,112,113,114,115,117,149,118',
+',,,148,,123,124,,,,122,125,126,127,128,129,130,,,,,,,149,13,14,15,16',
+'17,18,19,20,21,22,26,28,30,31,32,33,34,,,111,112,113,114,115,117,,118',
+',,,148,,123,124,,,149,122,125,126,127,128,129,130,111,112,113,114,115',
+'117,327,118,,,,148,,123,124,,,149,122,125,126,127,128,129,130,,,,,,',
+',13,14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,,,111,112,113,114',
+'115,117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129,130,111,112',
+'113,114,115,117,,118,,,,148,,123,124,,,149,122,125,126,127,128,129,130',
+'111,112,113,114,115,117,,118,,,,148,,123,124,,,,122,125,126,127,128',
+'129,130,,111,112,113,114,115,117,429,118,,,,148,,123,124,,,149,122,125',
+'126,127,128,129,130,,287,,,,111,112,113,114,115,117,,118,,,,148,149',
+'123,124,146,442,,122,125,126,127,128,129,130,111,112,113,114,115,117',
+',118,,,,148,149,123,124,,,,122,125,126,127,128,129,130,,111,112,113',
+'114,115,117,,118,,,,148,149,123,124,,,,122,125,126,127,128,129,130,',
+',147,,,,,,,,,,,,,,46,149,,,,,,,,,,,,,,,,,,,,,,,,,149,,,46,,,,,,,,,,',
+',,,,,,,,,,,,149,45,9,10,11,12,13,14,15,16,17,18,19,20,21,22,26,28,30',
+'31,32,33,34,35,36,37,38,,,47,45,9,10,11,12,13,14,15,16,17,18,19,20,21',
+'22,26,28,30,31,32,33,34,35,36,37,38,,41,47,294,375,,298,,,54,,,,,,,',
+',56,,,,,,,,,,325,375,,298,,,,,,,,,,,,56,,,,,,,,9,10,11,12,13,14,15,16',
+'17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,9,10,11,12,13,14',
+'15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,188,,,,,192',
+',,,,,,,,,,,,,,,,,,,413,,,,,,,,,,,,,,,,,,,,,,9,10,11,12,13,14,15,16,17',
+'18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,9,10,11,12,13,14,15',
+'16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,371,9,10,11,12',
+'13,14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,,,,,',
+'205,,,,,,,,,,,,9,10,11,12,13,14,15,16,17,18,19,20,21,22,26,28,30,31',
+'32,33,34,35,36,37,38,9,10,11,12,13,14,15,16,17,18,19,20,21,22,26,28',
+'30,31,32,33,34,35,36,37,38,307,,,,,,,,,,,,,,,,,,,,,,,,,381,,,,,,,,,',
+',,9,10,11,12,13,14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36',
+'37,38,9,10,11,12,13,14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34',
+'35,36,37,38,302,9,10,11,12,13,14,15,16,17,18,19,20,21,22,26,28,30,31',
+'32,33,34,35,36,37,38,,,,,,,,,,,,9,10,11,12,13,14,15,16,17,18,19,20,21',
+'22,26,28,30,31,32,33,34,35,36,37,38,9,10,11,12,13,14,15,16,17,18,19',
+'20,21,22,26,28,30,31,32,33,34,35,36,37,38,9,10,11,12,13,14,15,16,17',
+'18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,9,10,11,12,13,14,15',
+'16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,9,10,11,12,13',
+'14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,9,10,11',
+'12,13,14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37,38,9',
+'10,11,12,13,14,15,16,17,18,19,20,21,22,26,28,30,31,32,33,34,35,36,37',
+'38' ]
+        racc_action_table = arr = ::Array.new(3198, nil)
         idx = 0
         clist.each do |str|
@@ -434,133 +459,147 @@
 
 clist = [
-'210,210,210,210,210,210,26,210,24,114,213,210,55,210,210,297,210,210',
-'210,210,210,210,210,211,211,211,211,211,211,332,211,298,332,299,211',
-'48,211,211,95,211,211,211,211,211,211,211,217,26,213,24,300,55,55,189',
-'189,189,189,189,189,48,189,114,114,90,189,50,189,189,172,189,189,189',
-'189,189,189,189,95,50,132,132,303,217,217,217,217,217,217,217,217,217',
-'217,166,85,210,189,189,189,189,189,189,189,189,189,189,189,101,172,189',
-'189,189,189,189,287,287,347,166,211,394,394,394,394,394,394,347,394',
-'259,288,288,394,101,394,394,84,394,394,394,394,394,394,394,181,181,181',
-'181,181,181,189,181,318,259,1,181,273,181,181,273,181,181,181,181,181',
-'181,181,194,194,194,194,194,194,51,194,289,289,322,194,51,194,194,70',
-'194,194,194,194,194,194,194,195,195,195,195,195,195,275,195,324,52,327',
-'195,52,195,195,275,195,195,195,195,195,195,195,51,394,248,80,180,248',
-'80,180,248,392,392,392,392,392,392,252,392,180,252,330,392,333,392,392',
-'181,392,392,392,392,392,392,392,342,152,335,286,152,69,342,152,286,286',
-'248,290,290,342,152,194,392,66,392,392,392,392,392,392,392,392,392,392',
-'392,392,339,392,392,392,392,392,291,291,195,392,64,392,392,392,392,63',
-'392,392,392,392,392,392,285,354,128,292,292,285,285,128,128,355,392',
-'392,392,392,392,392,392,392,392,381,381,381,381,381,381,356,381,295',
-'295,357,381,358,381,381,359,381,381,381,381,381,381,381,380,380,380',
-'380,380,380,365,380,129,129,369,380,371,380,380,22,380,380,380,380,380',
-'380,380,196,196,196,196,196,196,14,196,382,32,387,196,389,196,196,390',
-'196,196,196,196,196,196,196,197,197,197,197,197,197,12,197,137,137,393',
-'197,397,197,197,185,197,197,197,197,197,197,197,3,381,184,32,182,32',
-'32,32,32,32,32,32,32,32,32,32,178,2,32,32,32,32,32,177,380,32,72,72',
-'72,72,72,72,72,72,72,72,72,130,130,72,72,72,72,72,175,170,157,196,156',
-'32,32,32,32,32,32,32,32,2,150,2,2,2,2,2,2,2,2,2,2,2,197,148,2,2,2,2',
-'2,146,2,2,198,198,198,198,198,198,144,198,142,136,135,198,134,198,198',
-'133,198,198,198,198,198,198,198,2,2,2,2,2,2,2,2,215,379,379,379,379',
-'379,379,231,379,232,234,235,379,236,379,379,238,379,379,379,379,379',
-'379,379,160,94,54,240,264,241,160,94,54,242,264,244,111,160,94,54,379',
-'264,379,379,379,379,379,379,379,379,379,379,379,379,105,379,379,379',
-'379,379,104,98,198,379,97,379,379,379,379,91,379,379,379,379,379,379',
-'115,278,115,281,115,115,115,296,,,379,379,379,379,379,379,379,379,379',
-'171,171,171,171,171,171,,171,,,,171,,171,171,,171,171,171,171,171,171',
-'171,,,378,378,378,378,378,378,,378,,,,378,,378,378,,378,378,378,378',
-'378,378,378,76,4,74,,174,,76,4,74,,174,,,76,4,74,378,174,378,378,378',
-'378,378,378,378,378,378,378,378,378,,378,378,378,378,378,,,,378,,378',
-'378,378,378,171,378,378,378,378,378,378,294,294,294,294,131,131,131',
-'131,,,378,378,378,378,378,378,378,378,378,361,361,361,361,361,361,,361',
-',,,361,,361,361,,361,361,361,361,361,361,361,218,293,293,293,293,,218',
-',,,,,,218,,,361,,361,361,361,361,361,361,361,361,361,361,361,361,,361',
-'361,361,361,361,,,,361,,361,361,361,361,,361,361,361,361,361,361,,,',
-',,,,,,,361,361,361,361,361,361,361,361,361,199,199,199,199,199,199,',
-'199,,,,199,,199,199,,199,199,199,199,199,199,199,350,350,350,350,350',
-'350,,350,,,,350,,350,350,,350,350,350,350,350,350,350,346,346,346,346',
-'346,346,,346,,,,346,,346,346,,346,346,346,346,346,346,346,191,191,191',
-'191,191,191,,191,,,,191,,191,191,,191,191,191,191,191,191,191,,199,',
-',,,,,,200,200,200,200,200,200,,200,,,,200,,200,200,350,200,200,200,200',
-'200,200,200,336,336,336,336,336,336,,336,,336,,336,,336,336,346,336',
-'336,336,336,336,336,336,,,,,,,,323,323,323,323,323,323,,323,191,,,323',
-',323,323,,323,323,323,323,323,323,323,,,,,,,,,,,,,,,,,323,200,323,323',
-'323,323,323,323,323,323,323,323,323,323,,323,323,323,323,323,,,,323',
-'336,323,323,323,323,,323,323,323,323,323,323,,,,,,,,,,,323,323,323,323',
-'323,323,323,323,323,321,321,321,321,321,321,,321,,,,321,,321,321,,321',
-'321,321,321,321,321,321,,,,,,,,,,,,,,,,,321,,321,321,321,321,321,321',
-'321,321,321,321,321,321,,321,321,321,321,321,,,,321,,321,321,321,321',
-',321,321,321,321,321,321,,,,,,,,,,,321,321,321,321,321,321,321,321,321',
-'398,398,398,398,398,398,,398,,,,398,,398,398,,398,398,398,398,398,398',
-'398,,,,,,,,,,,,,,,,,398,,398,398,398,398,398,398,398,398,398,398,398',
-'398,,398,398,398,398,398,,,,398,,398,398,398,398,,398,398,398,398,398',
-'398,,,,,,,,,,,398,398,398,398,398,398,398,398,398,320,320,320,320,320',
-'320,,320,,,,320,,320,320,,320,320,320,320,320,320,320,319,319,319,319',
-'319,319,,319,,,,319,,319,319,,319,319,319,319,319,319,319,77,77,77,77',
-'77,77,,77,,,,77,,77,77,,77,77,77,77,77,77,77,317,317,317,317,317,317',
-',317,,,,317,,317,317,,317,317,317,317,317,317,317,,320,,,,,77,,,,,,',
-'77,82,82,82,82,82,82,,82,,82,319,82,,82,82,,82,82,82,82,82,82,82,183',
-'183,183,183,183,183,,183,,,77,183,,183,183,,183,183,183,183,183,183',
-'183,316,316,316,316,316,316,,316,,,317,316,,316,316,,316,316,316,316',
-'316,316,316,304,304,304,304,304,304,,304,,,,304,,304,304,,304,304,304',
-'304,304,304,304,,82,,,,,,,,201,201,201,201,201,201,,201,,,,201,,201',
-'201,183,201,201,201,201,201,201,201,202,202,202,202,202,202,,202,,,',
-'202,,202,202,316,202,202,202,202,202,202,202,302,302,302,302,302,302',
-',302,,,,302,,302,302,304,302,302,302,302,302,302,302,277,277,277,277',
-'277,277,,277,,,,277,,277,277,,277,277,277,277,277,277,277,,201,,,,,302',
-'302,,,,,,302,203,203,203,203,203,203,,203,,,202,203,,203,203,,203,203',
-'203,203,203,203,203,209,209,209,209,209,209,,209,,,302,209,,209,209',
-',209,209,209,209,209,209,209,212,212,212,212,212,212,,212,,,277,212',
-',212,212,,212,212,212,212,212,212,212,204,204,204,204,204,204,,204,',
-',,204,,204,204,,204,204,204,204,204,204,204,,203,,,,,,,,271,271,271',
-'271,271,271,,271,,,,271,,271,271,209,271,271,271,271,271,271,271,205',
-'205,205,205,205,205,,205,,,,205,,205,205,212,205,205,205,205,205,205',
-'205,206,206,206,206,206,206,,206,,,,206,,206,206,204,206,206,206,206',
-'206,206,206,,,,,,,,,,145,145,145,145,145,145,,145,,,,145,,145,145,271',
-'145,145,145,145,145,145,145,,,,,,,,,,,,,,,,205,145,,145,145,145,145',
-'145,145,145,145,145,145,145,145,145,145,145,145,145,145,,,206,145,,145',
-'145,145,145,,145,145,145,145,145,145,,,,,,,,,,,145,145,145,145,145,145',
-'145,145,145,253,253,253,253,253,253,,253,,253,,253,,253,253,,253,253',
-'253,253,253,253,253,112,112,112,112,112,112,,112,,,,112,,112,112,,112',
-'112,112,112,112,112,112,38,38,38,38,38,38,38,38,38,38,38,,,38,38,38',
-'38,38,112,112,112,112,112,112,112,112,112,112,112,,,112,112,112,112',
-'112,,207,207,207,207,207,207,,207,,,253,207,,207,207,,207,207,207,207',
-'207,207,207,208,208,208,208,208,208,,208,,,112,208,,208,208,,208,208',
-'208,208,208,208,208,116,116,116,116,116,116,,116,,,,116,,116,116,,116',
-'116,116,116,116,116,116,117,117,117,117,117,117,,117,,,,117,,117,117',
-',117,117,117,117,117,117,117,,207,,,,,,,,118,118,118,118,118,118,,118',
-',,,118,,118,118,208,118,118,118,118,118,118,118,119,119,119,119,119',
-'119,,119,,,,119,,119,119,116,119,119,119,119,119,119,119,141,141,141',
-'141,141,141,,141,,,,141,,141,141,117,141,141,141,141,141,141,141,243',
-'243,243,243,243,243,,243,,,,243,,243,243,,243,243,243,243,243,243,243',
-',118,,,,,141,,,,,,,141,,,243,,237,237,237,237,237,237,119,237,,,,237',
-',237,237,,237,237,237,237,237,237,237,,,,,,,141,,,,,,,,,,,233,233,233',
-'233,233,233,,233,,,,233,243,233,233,,233,233,233,233,233,233,233,,,',
-',,,,,,,,,,,,,233,,233,233,233,233,233,233,233,233,233,233,233,233,237',
-'233,233,233,233,233,,,,233,,233,233,233,233,,233,233,233,233,233,233',
-',,,,,,274,274,,274,233,233,233,233,233,233,233,233,233,274,,,,,249,249',
-',249,,,249,,,,,,,249,,,,,274,274,274,274,274,274,274,274,274,274,274',
-',,274,274,274,274,274,249,249,249,249,249,249,249,249,249,249,249,,',
-'249,249,249,249,249,337,,,,,,,,274,274,274,274,274,274,274,274,,,83',
-',,,,,,,249,249,249,249,249,249,249,249,,337,337,337,337,337,337,337',
-'337,337,337,337,,,337,337,337,337,337,83,83,83,83,83,83,83,83,83,83',
-'83,,,83,83,83,83,83,,,,247,,,,,337,337,337,337,337,337,337,337,,,,,',
-',,,,,83,83,83,83,83,83,83,83,247,247,247,247,247,247,247,247,247,247',
-'247,,,247,247,247,247,247,5,5,5,5,5,5,5,5,5,5,5,,,5,5,5,5,5,,,,,,,,',
-'247,247,247,247,247,247,247,247,,,,,,,,,,,5,5,5,5,5,5,5,5,254,254,254',
-'254,254,254,254,254,254,254,254,,254,254,254,254,254,254,92,92,92,92',
-'92,92,92,92,92,92,92,,92,92,92,92,92,92,,,,,,,,,254,254,254,254,254',
-'254,254,254,,,,,,,,,,,92,92,92,92,92,92,92,92,155,155,155,155,155,155',
-'155,155,155,155,155,,,155,155,155,155,155,89,89,89,89,89,89,89,89,89',
-'89,89,,,89,89,89,89,89,,,,,,,,,155,155,155,155,155,155,155,155,,,,,',
-',,,,,89,89,89,89,89,89,89,89,88,88,88,88,88,88,88,88,88,88,88,,,88,88',
-'88,88,88,158,158,158,158,158,158,158,158,158,158,158,,158,158,158,158',
-'158,158,,,,,,,,,88,88,88,88,88,88,88,88,,,,,,,,,,,158,158,158,158,158',
-'158,158,158,67,67,67,67,67,67,67,67,67,67,67,,,67,67,67,67,67,161,161',
-'161,161,161,161,161,161,161,161,161,,161,161,161,161,161,161,,,,,,,',
-',67,67,67,67,67,67,67,67,,,,,,,,,,,161,161,161,161,161,161,161,161,7',
-'7,7,7,7,7,7,7,7,7,7,,,7,7,7,7,7,6,6,6,6,6,6,6,6,6,6,6,,,6,6,6,6,6,,',
-',,,,,,7,7,7,7,7,7,7,7,,,,,,,,,,,6,6,6,6,6,6,6,6,73,73,73,73,73,73,73',
-'73,73,73,73,,,73,73,73,73,73' ]
-        racc_action_check = arr = ::Array.new(2875, nil)
+'440,440,440,440,440,440,293,440,56,293,52,440,293,440,440,440,52,139',
+'440,440,440,440,440,440,440,438,438,438,438,438,438,106,438,354,326',
+'103,438,65,438,438,438,151,326,438,438,438,438,438,438,438,88,29,440',
+'31,51,29,354,31,109,56,56,56,120,207,286,120,106,120,293,120,120,120',
+'52,328,212,324,151,438,324,212,51,440,440,440,328,440,440,440,440,440',
+'440,440,440,440,440,318,110,49,207,286,318,88,88,88,142,142,438,438',
+'438,31,438,438,438,438,438,438,438,438,438,438,436,436,436,436,436,436',
+'304,436,120,120,120,436,49,436,436,436,428,362,436,436,436,436,436,436',
+'436,98,116,428,362,304,316,98,227,340,222,316,309,222,340,340,98,304',
+'309,167,167,167,167,167,167,222,167,309,436,226,167,333,167,167,167',
+'167,98,167,167,167,167,167,167,167,394,4,297,309,339,297,334,4,225,339',
+'339,394,66,436,436,436,4,436,436,436,436,436,436,436,436,436,436,167',
+'167,167,167,167,167,167,167,167,167,167,167,167,167,167,167,167,167',
+'167,167,167,167,167,167,167,167,267,267,101,167,167,167,95,167,167,167',
+'167,167,167,167,167,167,167,429,429,429,429,429,429,364,429,68,373,94',
+'429,373,429,429,429,87,364,429,429,429,429,429,429,429,427,427,427,427',
+'427,427,187,427,71,83,217,427,83,427,427,427,217,187,427,427,427,427',
+'427,427,427,217,269,429,75,75,75,75,75,75,75,75,75,75,75,75,75,75,75',
+'75,75,133,53,221,426,53,133,133,427,418,418,291,429,429,429,426,429',
+'429,429,429,429,429,429,429,429,429,137,137,350,220,136,136,136,136',
+'214,214,351,427,427,427,220,427,427,427,427,427,427,427,427,427,427',
+'175,175,175,175,175,175,363,175,215,215,352,175,353,175,175,175,218',
+'363,175,175,175,175,175,175,175,76,76,76,76,76,76,76,76,76,76,76,76',
+'76,76,76,76,76,425,82,82,82,82,82,82,274,82,357,175,425,82,283,82,82',
+'82,82,73,82,82,82,82,82,82,82,72,201,347,347,347,347,209,201,348,348',
+'348,348,365,175,175,175,201,175,175,175,175,175,175,175,175,175,175',
+'82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82,82',
+'82,82,82,349,349,198,82,82,82,197,82,82,82,82,82,82,82,82,82,82,273',
+'273,273,273,273,273,371,273,135,135,189,273,374,273,273,273,346,346',
+'273,273,273,273,273,273,273,404,404,404,404,404,404,376,404,345,345',
+'79,404,186,404,404,404,79,184,404,404,404,404,404,404,404,79,380,273',
+'47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,344,344,343,343,342',
+'342,138,404,99,99,179,273,273,273,178,273,273,273,273,273,273,273,273',
+'273,273,131,131,131,131,131,131,131,131,131,131,131,404,404,404,177',
+'404,404,404,404,404,404,404,404,404,404,402,402,402,402,402,402,176',
+'402,341,341,395,402,396,402,402,402,134,134,402,402,402,402,402,402',
+'402,275,275,275,275,275,275,102,275,27,403,77,275,25,275,275,275,77',
+'23,275,275,275,275,275,275,275,77,55,402,152,384,191,174,55,191,152',
+'384,191,173,408,412,414,55,416,152,384,191,281,422,172,140,165,141,275',
+'163,149,3,402,402,402,437,402,402,402,402,402,402,402,402,402,402,147',
+'1,,,,,,,,,,275,275,275,,275,275,275,275,275,275,275,275,275,275,360',
+'360,360,360,360,360,,360,,,,360,,360,360,360,,,360,360,360,360,360,360',
+'360,249,249,249,249,249,249,,249,,,,249,,249,249,,,,249,249,249,249',
+'249,249,249,,,360,383,383,383,383,383,383,,383,,,,383,,383,383,,,,383',
+'383,383,383,383,383,383,,,,360,360,360,,360,360,360,360,360,360,360',
+'360,360,360,,,,,,,377,377,377,377,377,377,,377,,377,,377,,377,377,,',
+'249,377,377,377,377,377,377,377,,,,367,367,367,367,367,367,,367,,,,367',
+',367,367,,,383,367,367,367,367,367,367,367,366,366,366,366,366,366,',
+'366,,,,366,,366,366,,,,366,366,366,366,366,366,366,,,367,,,,,,,,,,,',
+',377,,393,393,393,393,393,393,,393,,,366,393,,393,393,,,,393,393,393',
+'393,393,393,393,,367,,,,,,,,356,356,356,356,356,356,,356,,,,356,,356',
+'356,356,356,366,356,356,356,356,356,356,356,330,330,330,330,330,330',
+',330,,,,330,,330,330,,,,330,330,330,330,330,330,330,322,322,322,322',
+'322,322,,322,,393,,322,,322,322,322,,,322,322,322,322,322,322,322,,',
+',356,,,310,310,310,310,310,310,,310,,,,310,356,310,310,,,,310,310,310',
+'310,310,310,310,298,298,298,298,298,298,,298,,298,,298,330,298,298,',
+',,298,298,298,298,298,298,298,,,,,,,,,,,,,322,,,,,282,282,282,282,282',
+'282,,282,,,,282,,282,282,,,,282,282,282,282,282,282,282,,310,,,,,,,',
+',,,,,,,,,,,,,,,,,298,282,282,282,282,282,282,282,282,282,282,282,282',
+'282,282,282,282,282,282,282,282,282,282,282,282,282,282,280,280,280',
+'280,280,280,,280,,,,280,,280,280,282,,,280,280,280,280,280,280,280,146',
+'146,146,146,146,146,,146,,,,146,,146,146,146,,,146,146,146,146,146,146',
+'146,278,278,278,278,278,278,,278,,,,278,,278,278,,,,278,278,278,278',
+'278,278,278,,397,397,397,397,397,397,,397,,,,397,,397,397,,,280,397',
+'397,397,397,397,397,397,,,146,,,405,405,405,405,405,405,,405,,,,405',
+'146,405,405,,,,405,405,405,405,405,405,405,271,271,271,271,271,271,',
+'271,,,,271,278,271,271,,,,271,271,271,271,271,271,271,,266,266,266,266',
+'266,266,,266,,,,266,397,266,266,,,,266,266,266,266,266,266,266,80,80',
+'80,80,80,80,,80,,,,80,,80,80,80,,405,80,80,80,80,80,80,80,406,406,406',
+'406,406,406,406,406,,,,406,,406,406,,,271,406,406,406,406,406,406,406',
+',265,265,265,265,265,265,,265,,,,265,,265,265,,,266,265,265,265,265',
+'265,265,265,,,80,,,85,85,85,85,85,85,,85,,85,,85,80,85,85,,,,85,85,85',
+'85,85,85,85,264,264,264,264,264,264,,264,,,,264,406,264,264,,,,264,264',
+'264,264,264,264,264,,263,263,263,263,263,263,,263,,,,263,265,263,263',
+',,,263,263,263,263,263,263,263,262,262,262,262,262,262,,262,,,,262,',
+'262,262,,,85,262,262,262,262,262,262,262,261,261,261,261,261,261,,261',
+',,,261,,261,261,,,264,261,261,261,261,261,261,261,,260,260,260,260,260',
+'260,,260,,,,260,,260,260,,,263,260,260,260,260,260,260,260,259,259,259',
+'259,259,259,,259,,,,259,,259,259,,,262,259,259,259,259,259,259,259,258',
+'258,258,258,258,258,,258,,,,258,,258,258,,,261,258,258,258,258,258,258',
+'258,,257,257,257,257,257,257,,257,,,,257,,257,257,,,260,257,257,257',
+'257,257,257,257,256,256,256,256,256,256,,256,,,,256,,256,256,,,259,256',
+'256,256,256,256,256,256,255,255,255,255,255,255,,255,,,,255,,255,255',
+',,258,255,255,255,255,255,255,255,,254,254,254,254,254,254,,254,,,,254',
+',254,254,,,257,254,254,254,254,254,254,254,253,253,253,253,253,253,',
+'253,,,,253,,253,253,,,256,253,253,253,253,253,253,253,252,252,252,252',
+'252,252,,252,,,,252,,252,252,,,255,252,252,252,252,252,252,252,,251',
+'251,251,251,251,251,,251,,,,251,,251,251,,,254,251,251,251,251,251,251',
+'251,250,250,250,250,250,250,,250,,,,250,,250,250,,,253,250,250,250,250',
+'250,250,250,389,389,389,389,389,389,,389,,,,389,,389,389,389,,252,389',
+'389,389,389,389,389,389,,248,248,248,248,248,248,,248,,,,248,,248,248',
+',,251,248,248,248,248,248,248,248,,,,,,,,,,,,,,,,,,250,,,,,,,,,,389',
+',,117,117,117,117,117,117,,117,,,,117,389,117,117,,,,117,117,117,117',
+'117,117,117,,236,236,236,236,236,236,,236,,,,236,248,236,236,,,,236',
+'236,236,236,236,236,236,,,,,,,117,117,117,117,117,117,117,117,117,117',
+'117,117,117,117,117,117,117,,,121,121,121,121,121,121,,121,,,,121,,121',
+'121,,,117,121,121,121,121,121,121,121,,122,122,122,122,122,122,,122',
+',,,122,,122,122,,,236,122,122,122,122,122,122,122,123,123,123,123,123',
+'123,,123,,,,123,,123,123,,,,123,123,123,123,123,123,123,124,124,124',
+'124,124,124,,124,,,,124,,124,124,,,121,124,124,124,124,124,124,124,',
+',,,,,,,,,,,233,233,233,233,233,233,122,233,,,,233,,233,233,,,,233,233',
+'233,233,233,233,233,223,223,223,223,223,223,123,223,,,,223,,223,223',
+',,,223,223,223,223,223,223,223,,,,,,,124,233,233,233,233,233,233,233',
+'233,233,233,233,233,233,233,233,233,233,,,231,231,231,231,231,231,,231',
+',,,231,,231,231,,,233,231,231,231,231,231,231,231,224,224,224,224,224',
+'224,224,224,,,,224,,224,224,,,223,224,224,224,224,224,224,224,,,,,,',
+',231,231,231,231,231,231,231,231,231,231,231,231,231,231,231,231,231',
+',,213,213,213,213,213,213,,213,,,,213,,213,213,,,231,213,213,213,213',
+'213,213,213,210,210,210,210,210,210,,210,,,,210,,210,210,,,224,210,210',
+'210,210,210,210,210,180,180,180,180,180,180,,180,,,,180,,180,180,,,',
+'180,180,180,180,180,180,180,,407,407,407,407,407,407,407,407,,,,407',
+',407,407,,,213,407,407,407,407,407,407,407,,180,,,,435,435,435,435,435',
+'435,,435,,,,435,210,435,435,435,435,,435,435,435,435,435,435,435,164',
+'164,164,164,164,164,,164,,,,164,180,164,164,,,,164,164,164,164,164,164',
+'164,,279,279,279,279,279,279,,279,,,,279,407,279,279,,,,279,279,279',
+'279,279,279,279,,,435,,,,,,,,,,,,,,41,435,,,,,,,,,,,,,,,,,,,,,,,,,164',
+',,2,,,,,,,,,,,,,,,,,,,,,,,279,41,41,41,41,41,41,41,41,41,41,41,41,41',
+'41,41,41,41,41,41,41,41,41,41,41,41,41,,,41,2,2,2,2,2,2,2,2,2,2,2,2',
+'2,2,2,2,2,2,2,2,2,2,2,2,2,2,,2,2,294,294,,294,,,294,,,,,,,,,294,,,,',
+',,,,,325,325,,325,,,,,,,,,,,,325,,,,,,,,294,294,294,294,294,294,294',
+'294,294,294,294,294,294,294,294,294,294,294,294,294,294,294,294,294',
+'294,325,325,325,325,325,325,325,325,325,325,325,325,325,325,325,325',
+'325,325,325,325,325,325,325,325,325,86,,,,,86,,,,,,,,,,,,,,,,,,,,378',
+',,,,,,,,,,,,,,,,,,,,,86,86,86,86,86,86,86,86,86,86,86,86,86,86,86,86',
+'86,86,86,86,86,86,86,86,86,378,378,378,378,378,378,378,378,378,378,378',
+'378,378,378,378,378,378,378,378,378,378,378,378,378,378,292,7,7,7,7',
+'7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,,,,,,96,,,,,,,,,,,,292,292',
+'292,292,292,292,292,292,292,292,292,292,292,292,292,292,292,292,292',
+'292,292,292,292,292,292,96,96,96,96,96,96,96,96,96,96,96,96,96,96,96',
+'96,96,96,96,96,96,96,96,96,96,202,,,,,,,,,,,,,,,,,,,,,,,,,299,,,,,,',
+',,,,,202,202,202,202,202,202,202,202,202,202,202,202,202,202,202,202',
+'202,202,202,202,202,202,202,202,202,299,299,299,299,299,299,299,299',
+'299,299,299,299,299,299,299,299,299,299,299,299,299,299,299,299,299',
+'199,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92,92',
+'92,92,92,,,,,,,,,,,,199,199,199,199,199,199,199,199,199,199,199,199',
+'199,199,199,199,199,199,199,199,199,199,199,199,199,8,8,8,8,8,8,8,8',
+'8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,196,196,196,196,196,196,196,196,196',
+'196,196,196,196,196,196,196,196,196,196,196,196,196,196,196,196,6,6',
+'6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,5,5,5,5,5,5,5,5,5,5,5',
+'5,5,5,5,5,5,5,5,5,5,5,5,5,5,93,93,93,93,93,93,93,93,93,93,93,93,93,93',
+'93,93,93,93,93,93,93,93,93,93,93,69,69,69,69,69,69,69,69,69,69,69,69',
+'69,69,69,69,69,69,69,69,69,69,69,69,69' ]
+        racc_action_check = arr = ::Array.new(3198, nil)
         idx = 0
         clist.each do |str|
@@ -572,427 +611,475 @@
 
 racc_action_pointer = [
-   nil,   150,   420,   404,   652,  2412,  2762,  2744,   nil,   nil,
-   nil,   nil,   346,   nil,   323,   nil,   nil,   nil,   nil,   nil,
-   nil,   nil,   337,   nil,    -5,   nil,    -7,   nil,   nil,   nil,
-   nil,   nil,   366,   nil,   nil,   nil,   nil,   nil,  1848,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,    18,   nil,
-    23,   162,   188,   nil,   534,    -8,   nil,   nil,   nil,   nil,
-   nil,   nil,   nil,   232,   227,   nil,   204,  2674,   nil,   233,
-   124,   nil,   387,  2814,   653,   nil,   651,  1303,   nil,   nil,
-   205,   nil,  1363,  2342,   124,    72,   nil,   nil,  2604,  2552,
-    22,   543,  2482,   nil,   533,    21,   nil,   537,   563,   nil,
-   nil,    88,   nil,   nil,   533,   474,   nil,   nil,   nil,   nil,
-   nil,   542,  1866,   nil,     2,   581,  1972,  1995,  2027,  2050,
-   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   275,   322,
-   414,   685,    45,   480,   461,   458,   456,   351,   nil,   nil,
-   nil,  2073,   485,   nil,   477,  1749,   470,   nil,   467,   nil,
-   445,   nil,   235,   nil,   nil,  2534,   411,   409,  2622,   nil,
-   532,  2692,   nil,   nil,   nil,   nil,    74,   nil,   nil,   nil,
-   436,   608,    51,   nil,   655,   435,   nil,   419,   412,   nil,
-   206,   138,   401,  1386,   393,   383,   nil,   nil,   nil,    51,
-   nil,   890,   nil,   nil,   161,   184,   356,   379,   482,   821,
-   922,  1464,  1487,  1570,  1639,  1694,  1717,  1926,  1949,  1593,
-    -2,    21,  1616,    -7,   nil,   506,   nil,     4,   745,   nil,
+   nil,   732,  2528,   716,   182,  3068,  3043,  2752,  2993,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
-   nil,   515,   517,  2177,   518,   519,   488,  2137,   491,   nil,
-   529,   503,   507,  2096,   509,   nil,   nil,  2394,   204,  2271,
-   nil,   nil,   217,  1843,  2464,   nil,   nil,   nil,   nil,   108,
-   nil,   nil,   nil,   nil,   536,   nil,   nil,   nil,   nil,   nil,
-   nil,  1671,   nil,   145,  2253,   184,   nil,  1533,   581,   nil,
-   nil,   586,   nil,   nil,   nil,   273,   224,    91,   105,   144,
-   225,   250,   269,   724,   681,   287,   579,   -20,    -5,    -4,
-    10,   nil,  1510,    72,  1432,   nil,   nil,   nil,   nil,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,  1409,  1326,    82,  1280,
-  1257,  1069,   133,   975,   153,   nil,   nil,   155,   nil,   nil,
-   216,   nil,    22,   222,   nil,   235,   945,  2324,   nil,   260,
-   nil,   nil,   234,   nil,   nil,   nil,   867,   106,   nil,   nil,
-   844,   nil,   nil,   nil,   253,   294,   310,   315,   283,   319,
-   nil,   727,   nil,   nil,   nil,   329,   nil,   nil,   nil,   334,
-   nil,   339,   nil,   nil,   nil,   nil,   nil,   nil,   633,   514,
-   333,   310,   296,   nil,   nil,   nil,   nil,   303,   nil,   362,
-   332,   nil,   216,   350,   115,   nil,   nil,   385,  1163,   nil ]
+   nil,   nil,   nil,   624,   nil,   619,   nil,   656,   nil,    38,
+   nil,    40,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,  2499,   nil,   nil,   nil,   nil,   nil,   510,   nil,    78,
+   nil,    37,     3,   322,   nil,   680,   -14,   nil,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,    20,   183,   nil,   249,  3118,
+   nil,   278,   429,   421,   nil,   252,   344,   664,   nil,   544,
+  1392,   nil,   419,   285,   nil,  1473,  2701,   266,    28,   nil,
+   nil,   nil,  2932,  3093,   214,   193,  2819,   nil,   138,   576,
+   nil,   200,   654,    22,   nil,   nil,    12,   nil,   nil,    15,
+     1,   nil,   nil,   nil,   nil,   nil,   137,  1959,   nil,   nil,
+    55,  2035,  2061,  2086,  2111,   nil,   nil,   nil,   nil,   nil,
+   nil,   568,   nil,   306,   629,   495,   326,   318,   571,   -20,
+   672,   673,    64,   nil,   nil,   nil,  1235,   724,   nil,   702,
+   nil,    22,   682,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,   nil,   nil,   672,  2431,   669,   nil,   161,   nil,   nil,
+   nil,   nil,   702,   691,   685,   376,   635,   612,   546,   542,
+  2350,   nil,   nil,   nil,   547,   nil,   545,   281,   nil,   507,
+   nil,   684,   nil,   nil,   nil,   nil,  3018,   451,   447,  2968,
+   nil,   440,  2881,   nil,   nil,   nil,   nil,    44,   nil,   410,
+  2325,   nil,    61,  2300,   343,   368,   nil,   286,   381,   nil,
+   348,   322,   147,  2173,  2249,   189,   160,   139,   nil,   nil,
+   nil,  2224,   nil,  2148,   nil,   nil,  1985,   nil,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,  1904,   779,
+  1853,  1828,  1802,  1777,  1752,  1726,  1701,  1676,  1650,  1625,
+  1600,  1574,  1549,  1524,  1498,  1443,  1367,   223,   nil,   300,
+   nil,  1341,   nil,   514,   385,   659,   nil,   nil,  1260,  2457,
+  1210,   619,  1132,   379,   nil,   nil,    45,   nil,   nil,   nil,
+   nil,   325,  2794,    -1,  2604,   nil,   nil,   183,  1090,  2906,
+   nil,   nil,   nil,   nil,   107,   nil,   nil,   nil,   nil,   149,
+  1065,   nil,   nil,   nil,   nil,   nil,   137,   nil,    82,   nil,
+   nil,   nil,  1034,   nil,    68,  2629,    23,   nil,    65,   nil,
+  1009,   nil,   nil,   167,   186,   nil,   nil,   nil,   nil,   170,
+   131,   621,   567,   559,   557,   520,   503,   417,   423,   464,
+   334,   326,   350,   351,    14,   nil,   984,   421,   nil,   nil,
+   754,   nil,   129,   376,   256,   451,   908,   883,   nil,   nil,
+   nil,   510,   nil,   260,   520,   nil,   539,   855,  2726,   nil,
+   556,   nil,   nil,   807,   683,   nil,   nil,   nil,   nil,  1878,
+   nil,   nil,   nil,   950,   180,   629,   631,  1286,   nil,   nil,
+   nil,   nil,   634,   653,   539,  1316,  1417,  2376,   687,   nil,
+   nil,   nil,   689,   nil,   693,   nil,   649,   nil,   318,   nil,
+   nil,   nil,   622,   nil,   nil,   412,   323,   281,   128,   256,
+   nil,   nil,   nil,   nil,   nil,  2406,   118,   666,    23,   nil,
+    -2,   nil,   nil,   nil,   nil,   nil,   nil ]
 
 racc_action_default = [
-  -176,  -243,    -1,  -243,  -243,   -70,   -71,   -72,   -80,   -81,
-   -82,   -83,   -84,   -85,   -86,   -87,   -88,   -89,   -90,   -91,
-   -92,   -93,   -96,   -99,  -243,  -116,  -243,  -129,  -134,  -135,
-  -177,  -178,  -243,  -180,  -181,  -184,  -185,  -186,  -243,  -232,
-  -233,  -234,  -235,  -236,  -237,  -238,  -239,   400,  -243,   -76,
-   -78,  -243,  -137,  -139,  -243,  -145,   -73,   -84,   -86,   -74,
-   -75,  -183,  -182,   -98,  -243,  -102,  -115,  -243,  -119,  -243,
-  -128,  -179,  -106,  -108,  -243,   -69,  -243,  -243,  -190,  -191,
-  -136,  -138,  -243,  -243,  -243,  -146,  -147,   -94,  -243,  -243,
-   -84,   -85,  -243,  -117,  -243,  -243,  -130,  -132,  -243,  -107,
-  -109,  -243,  -188,   -77,   -78,    -2,    -3,    -4,    -5,    -6,
-    -7,    -8,  -243,   -10,   -12,   -23,  -243,  -243,  -243,  -243,
-   -29,   -30,   -31,   -32,   -33,   -34,   -35,   -37,   -41,   -44,
-   -47,   -52,   -55,   -57,   -59,   -61,   -63,   -65,   -68,   -79,
-  -170,  -243,  -243,  -240,  -243,  -243,  -243,  -142,  -243,  -144,
-  -149,  -151,  -155,  -140,  -148,  -243,   -84,   -85,  -243,  -100,
-  -243,  -243,  -122,  -121,  -114,  -118,  -243,  -123,  -125,  -126,
-  -243,  -243,  -243,  -187,  -243,  -243,   -11,  -243,  -243,   -67,
-  -156,   -20,  -243,  -243,  -243,  -243,   -18,   -19,   -24,  -243,
-   -25,  -243,   -27,   -28,  -243,  -243,  -243,  -243,  -243,  -243,
-  -243,  -243,  -243,  -243,  -243,  -243,  -243,  -243,  -243,  -243,
-  -243,  -243,  -243,  -243,  -174,  -243,  -241,   -35,  -243,  -192,
-  -193,  -194,  -195,  -196,  -197,  -198,  -199,  -200,  -201,  -202,
-  -203,  -243,  -243,  -243,  -243,  -243,  -240,  -243,  -243,  -213,
-  -243,  -243,  -243,  -243,  -243,  -141,  -143,  -243,  -158,  -243,
-  -153,  -154,  -159,  -243,  -243,  -105,  -104,   -97,  -101,  -243,
-  -110,  -112,  -113,  -120,  -243,  -131,  -133,  -127,  -189,  -242,
-    -9,  -243,  -157,  -158,  -243,  -243,   -21,   -20,  -243,   -16,
-   -17,  -243,   -38,   -39,   -40,   -42,   -43,   -45,   -46,   -48,
-   -49,   -50,   -51,   -53,   -54,   -56,   -58,   -60,   -62,   -64,
-  -243,  -171,  -243,  -243,  -243,  -221,  -222,  -223,  -224,  -225,
-  -226,  -227,  -228,  -229,  -230,  -231,  -243,  -243,  -243,  -243,
-  -243,  -243,  -243,  -243,  -243,  -215,  -216,  -243,  -218,  -219,
-  -243,  -152,  -160,  -243,  -166,  -243,  -243,  -243,  -162,  -243,
-   -95,  -103,  -243,  -124,   -36,   -13,  -243,  -243,   -15,   -26,
-  -243,  -172,  -175,  -173,  -243,  -243,  -243,  -243,  -243,  -243,
-  -210,  -243,  -212,  -214,  -217,  -243,  -161,  -167,  -164,  -243,
-  -168,  -243,  -163,  -111,   -22,   -14,   -66,  -220,  -243,  -243,
-  -243,  -243,  -243,  -211,  -150,  -165,  -169,  -204,  -206,  -243,
-  -243,  -209,  -243,  -243,  -243,  -205,  -207,  -243,  -243,  -208 ]
+  -215,  -269,    -1,  -269,  -269,   -86,   -88,   -90,   -92,   -98,
+   -99,  -100,  -101,  -102,  -103,  -104,  -105,  -106,  -107,  -108,
+  -109,  -110,  -111,  -112,  -113,  -114,  -115,  -118,  -121,  -269,
+  -139,  -269,  -163,  -164,  -165,  -166,  -167,  -168,  -169,  -216,
+  -217,  -269,  -219,  -220,  -223,  -224,  -225,  -269,   447,  -269,
+   -94,   -96,  -269,  -171,  -173,  -269,  -180,   -87,  -112,  -114,
+   -89,   -91,   -93,  -222,  -221,  -120,  -269,  -124,  -138,  -269,
+  -142,  -269,  -155,  -158,  -218,  -130,  -132,  -269,   -85,  -269,
+  -269,  -229,  -269,  -170,  -172,  -269,  -269,  -269,  -181,  -182,
+  -184,  -116,  -269,  -269,  -112,  -113,  -269,  -140,  -269,  -269,
+  -159,  -161,  -269,  -269,  -129,  -131,  -269,  -227,   -95,   -96,
+    -2,    -3,    -4,    -5,    -6,    -7,    -8,  -269,   -10,   -12,
+   -25,  -269,  -269,  -269,  -269,   -31,   -32,   -33,   -34,   -35,
+   -36,   -37,   -39,   -43,   -46,   -49,   -54,   -57,   -59,   -61,
+   -63,   -65,   -67,   -69,   -97,  -209,  -269,  -269,  -265,  -269,
+   -82,  -269,  -269,  -230,  -231,  -232,  -233,  -234,  -235,  -236,
+  -237,  -238,  -239,  -265,  -269,  -269,  -243,  -269,  -245,  -247,
+  -248,  -249,  -269,  -269,  -269,  -269,  -269,  -269,  -269,  -269,
+  -269,  -268,   -37,   -84,  -269,  -176,  -269,  -269,  -179,  -186,
+  -188,  -192,  -193,  -174,  -183,  -185,  -269,  -112,  -113,  -269,
+  -122,  -269,  -269,  -145,  -144,  -137,  -141,  -269,  -146,  -148,
+  -269,  -151,  -269,  -269,  -269,  -269,  -226,  -269,  -269,   -11,
+  -269,  -269,  -195,  -269,  -269,  -269,  -269,  -269,   -19,   -20,
+   -26,  -269,   -27,  -269,   -29,   -30,  -269,   -71,   -72,   -73,
+   -74,   -75,   -76,   -77,   -78,   -79,   -80,   -81,  -269,  -269,
+  -269,  -269,  -269,  -269,  -269,  -269,  -269,  -269,  -269,  -269,
+  -269,  -269,  -269,  -269,  -269,  -269,  -269,  -269,  -213,  -269,
+  -266,  -269,  -250,  -269,  -269,  -269,  -244,  -246,  -269,  -269,
+  -269,  -269,  -269,  -269,  -261,  -262,  -269,  -263,  -175,  -177,
+  -178,  -269,  -269,  -197,  -269,  -190,  -191,  -198,  -269,  -269,
+  -128,  -127,  -119,  -123,  -269,  -133,  -135,  -136,  -143,  -269,
+  -269,  -149,  -153,  -160,  -162,  -152,  -269,  -156,  -269,  -228,
+  -267,    -9,  -269,  -196,  -197,  -269,  -269,   -14,  -269,   -23,
+  -269,   -17,   -18,  -269,  -269,   -70,   -40,   -41,   -42,   -44,
+   -45,   -47,   -48,   -50,   -51,   -52,   -53,   -55,   -56,   -58,
+   -60,   -62,   -64,   -66,  -269,  -210,  -269,  -269,   -83,  -240,
+  -269,  -242,  -269,  -269,  -269,  -269,  -269,  -269,  -260,  -264,
+  -194,  -269,  -189,  -199,  -269,  -205,  -269,  -269,  -269,  -201,
+  -269,  -117,  -125,  -269,  -269,  -147,  -150,  -154,  -157,  -269,
+   -38,   -13,   -15,  -269,  -269,   -28,  -269,  -269,  -211,  -214,
+  -212,  -241,  -269,  -269,  -269,  -269,  -269,  -269,  -269,  -200,
+  -206,  -203,  -269,  -207,  -269,  -202,  -269,  -134,  -269,   -24,
+   -16,   -68,  -251,  -253,  -254,  -269,  -269,  -269,  -269,  -269,
+  -187,  -204,  -208,  -126,   -21,  -269,  -269,  -269,  -269,  -256,
+  -269,  -258,   -22,  -252,  -255,  -257,  -259 ]
 
 racc_goto_table = [
-    50,     4,   177,   146,    56,    59,    60,   190,   192,   193,
-   148,    86,   139,   138,   260,    80,   167,   188,   138,   158,
-   275,   258,   178,    35,    31,   165,   332,    73,    12,    74,
-    14,     4,   287,   288,    91,   217,    95,   293,   294,   251,
-   304,   154,   219,     2,    85,   295,    92,   285,   286,   296,
-    72,   332,   297,    35,    71,   157,    91,   298,    12,    91,
-    14,    73,    73,    99,   100,   172,    94,   272,   161,   299,
-   102,   276,   104,   278,   103,    63,   214,   138,   155,   177,
-    64,   177,   152,   259,    72,    72,   254,   160,    94,    66,
-   168,    94,   266,    90,   165,   282,   283,   284,   166,   281,
-   265,    73,   300,   182,   331,   213,    30,   138,   248,   289,
-   290,   291,   292,   101,   156,    90,   347,   258,    90,    78,
-   145,     1,   157,   217,    72,   157,   nil,   nil,    91,   nil,
-   318,   nil,   nil,   327,   nil,   nil,   273,   nil,   nil,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   250,   nil,
-   nil,   nil,   nil,   nil,   160,   nil,   261,   160,   322,   nil,
-    94,   nil,   nil,   nil,   nil,   nil,   nil,   276,   nil,   nil,
-   268,   nil,   344,   138,   339,   nil,   nil,   nil,    73,   nil,
-   nil,   156,   nil,   nil,   156,   nil,   343,    90,   nil,   138,
-   nil,   nil,   nil,   nil,   354,   nil,   373,   nil,   nil,   nil,
-   nil,    72,   nil,   nil,   nil,   248,   355,   356,   nil,   358,
-   359,   217,    80,   217,   104,   nil,   nil,   nil,   360,   nil,
-   362,   157,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
-   273,   nil,   nil,   nil,   nil,   nil,   374,   352,   138,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,   152,   nil,   152,   nil,
-   nil,   217,   nil,   160,   nil,   nil,   nil,   369,   383,   nil,
-   168,   nil,   nil,   nil,   371,   nil,   nil,   nil,   217,   217,
-   389,   390,   138,   152,   nil,   387,   388,   nil,   nil,   nil,
-   156,   nil,   217,   nil,   397,   nil,   376,   nil,   217,   395,
-   nil,   nil,   nil,   nil,   nil,   399,   nil,   nil,   nil,   nil,
+    51,   144,   145,    81,   183,   182,   184,   281,   186,    23,
+   267,    95,   208,    83,   206,   305,   303,   313,   328,   169,
+    25,     4,   199,   230,    57,    60,    61,    62,    75,    89,
+    40,    99,   168,   221,   198,    95,   296,    77,    95,   220,
+   373,   182,   232,   234,   235,    65,    96,   207,    23,    76,
+   304,   366,   343,   344,   345,   346,    75,    75,    90,    25,
+     4,   194,   214,   215,    66,   104,   105,   323,   145,    74,
+   202,   373,   196,   107,    68,   109,    94,    76,    76,   347,
+   348,   339,   340,   183,   182,   274,   341,   342,    98,   108,
+   195,   236,   187,    88,   209,   372,   353,   352,    75,   197,
+    94,   152,   286,    94,   169,   359,    39,   361,   351,   106,
+   350,   201,    98,   349,     2,    98,   303,   277,   167,    76,
+   206,   313,   225,   313,   394,     1,   299,   nil,   nil,   183,
+   182,   311,   183,   182,   314,   406,   407,   nil,   198,   nil,
+   nil,   198,   nil,   nil,    95,   326,   329,   333,   109,   334,
+   336,   337,   338,   220,   nil,   220,   nil,   nil,   335,   nil,
+   nil,   nil,   nil,   nil,   293,   nil,   nil,   nil,   182,   182,
+   182,   182,   182,   182,   182,   182,   182,   182,   182,   182,
+   182,   182,   182,   182,   182,   182,   152,   295,   354,   nil,
+   nil,   nil,   401,   358,   nil,   324,   nil,   306,   417,   nil,
+   362,   363,   364,   197,   nil,   nil,   197,   nil,   nil,    94,
+   nil,   nil,    75,   319,    75,   201,   nil,   nil,   201,   367,
+   380,    98,   nil,   385,   390,   nil,   nil,   nil,   nil,   183,
+   182,   386,   nil,    76,   422,    76,   424,   nil,   nil,   nil,
+   nil,   198,   182,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,   nil,   329,   418,    83,   nil,   nil,   nil,   nil,   439,
+   nil,   441,   nil,   nil,   nil,   nil,   nil,   293,   443,   nil,
+   445,   nil,   446,   nil,   nil,   nil,   nil,   399,   145,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   324,   412,
+   414,   152,   183,   182,   416,   209,   197,   nil,   nil,   nil,
+   nil,   145,   nil,   nil,   nil,   419,   421,   182,   201,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   425,   426,   428,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,   152,   nil,   261 ]
-
-racc_goto_check = [
-    32,    27,     6,    25,    27,    27,    27,    10,    10,    10,
-    57,    55,    33,    24,    45,    56,    51,    12,    24,    39,
-     8,    42,    13,    26,    64,    49,    61,     9,    34,    44,
-    36,    27,    15,    15,    35,    10,    53,    17,    17,    60,
-    79,    55,    70,     2,     9,    18,    48,    14,    14,    19,
-    30,    61,    20,    26,    64,    35,    35,    21,    34,    35,
-    36,     9,     9,    44,    44,    53,    27,    60,    48,    22,
-    32,     6,    32,     6,    31,    38,    33,    24,    40,     6,
-    41,     6,    27,    43,    30,    30,    39,    27,    27,    47,
-    32,    27,    25,    34,    49,    12,    12,    12,    50,    13,
-    54,     9,     6,     9,    59,    62,    63,    24,    55,    16,
-    16,    16,    16,    67,    34,    34,     8,    42,    34,    68,
-    69,     1,    35,    10,    30,    35,   nil,   nil,    35,   nil,
-    70,   nil,   nil,     6,   nil,   nil,    55,   nil,   nil,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,    32,   nil,
-   nil,   nil,   nil,   nil,    27,   nil,    32,    27,    25,   nil,
-    27,   nil,   nil,   nil,   nil,   nil,   nil,     6,   nil,   nil,
-    32,   nil,    12,    24,    25,   nil,   nil,   nil,     9,   nil,
-   nil,    34,   nil,   nil,    34,   nil,    51,    34,   nil,    24,
-   nil,   nil,   nil,   nil,     6,   nil,    45,   nil,   nil,   nil,
-   nil,    30,   nil,   nil,   nil,    55,     6,     6,   nil,     6,
-     6,    10,    56,    10,    32,   nil,   nil,   nil,    70,   nil,
-    70,    35,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
-    55,   nil,   nil,   nil,   nil,   nil,     6,    33,    24,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,    27,   nil,    27,   nil,
-   nil,    10,   nil,    27,   nil,   nil,   nil,    25,    70,   nil,
-    32,   nil,   nil,   nil,    57,   nil,   nil,   nil,    10,    10,
-     6,     6,    24,    27,   nil,    70,    70,   nil,   nil,   nil,
-    34,   nil,    10,   nil,     6,   nil,    24,   nil,    10,    70,
-   nil,   nil,   nil,   nil,   nil,    70,   nil,   nil,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,   423,   399,   145,   nil,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   306 ]
+
+racc_goto_check = [
+    36,    37,    12,    72,    26,    13,    28,    73,    60,    38,
+    11,    39,    55,    59,    53,    49,    46,    57,     8,    29,
+    40,    30,    43,    15,    30,    30,    30,    30,    33,    58,
+    68,    56,    84,    10,    39,    39,    65,    48,    39,     6,
+    66,    13,    13,    13,    13,    42,    52,    54,    38,     9,
+    47,    75,    18,    18,    18,    18,    33,    33,     9,    40,
+    30,    58,    56,    56,    45,    48,    48,    65,    12,    68,
+    52,    66,    44,    36,    51,    36,    38,     9,     9,    19,
+    19,    16,    16,    26,    13,    28,    17,    17,    30,    35,
+     9,    27,    61,    62,    36,    64,    24,    23,    33,    38,
+    38,    30,     6,    38,    29,    73,    67,    73,    22,    71,
+    21,    30,    30,    20,     2,    30,    46,    84,    83,     9,
+    53,    57,     9,    57,     8,     1,    43,   nil,   nil,    26,
+    13,    28,    26,    13,    28,    75,    75,   nil,    39,   nil,
+   nil,    39,   nil,   nil,    39,     6,    12,    10,    36,    10,
+    15,    15,    15,     6,   nil,     6,   nil,   nil,    12,   nil,
+   nil,   nil,   nil,   nil,    58,   nil,   nil,   nil,    13,    13,
+    13,    13,    13,    13,    13,    13,    13,    13,    13,    13,
+    13,    13,    13,    13,    13,    13,    30,    36,     6,   nil,
+   nil,   nil,    73,    12,   nil,    58,   nil,    36,    49,   nil,
+     6,     6,     6,    38,   nil,   nil,    38,   nil,   nil,    38,
+   nil,   nil,    33,    36,    33,    30,   nil,   nil,    30,    29,
+    12,    30,   nil,    55,    15,   nil,   nil,   nil,   nil,    26,
+    13,    28,   nil,     9,    73,     9,    73,   nil,   nil,   nil,
+   nil,    39,    13,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,   nil,    12,    11,    59,   nil,   nil,   nil,   nil,    73,
+   nil,    73,   nil,   nil,   nil,   nil,   nil,    58,    73,   nil,
+    73,   nil,    73,   nil,   nil,   nil,   nil,    37,    12,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
-   nil,   nil,   nil,   nil,   nil,   nil,    27,   nil,    32 ]
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,    58,    12,
+    60,    30,    26,    13,    28,    36,    38,   nil,   nil,   nil,
+   nil,    12,   nil,   nil,   nil,    12,    26,    13,    30,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,     6,     6,     6,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,    72,    37,    12,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
+    36 ]
 
 racc_goto_pointer = [
-   nil,   121,    43,   nil,   nil,   nil,  -110,   nil,  -161,   -11,
-  -110,   nil,   -99,   -90,  -150,  -167,   -92,  -168,  -162,  -159,
-  -157,  -153,  -142,   nil,   -64,   -79,    21,    -1,   nil,   nil,
-    12,    -2,    -4,   -65,    26,   -33,    28,   nil,    53,   -69,
-    -9,    58,  -137,   -77,    -9,  -146,   nil,    65,   -21,   -67,
-     4,   -78,   nil,   -33,   -70,   -44,   -36,   -73,   nil,  -143,
-  -113,  -222,   -36,   104,    22,   nil,   nil,    39,    69,    41,
-  -103,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,  -177 ]
+   nil,   125,   114,   nil,   nil,   nil,   -78,   nil,  -206,     2,
+   -84,  -136,   -78,   -80,   nil,   -98,  -170,  -167,  -203,  -180,
+  -148,  -152,  -155,  -167,  -169,   nil,   -81,   -40,   -79,   -63,
+    19,   nil,   nil,   -19,   nil,    10,    -4,   -79,     7,   -58,
+    18,   nil,    18,   -70,   -19,    37,  -183,  -151,   -10,  -186,
+   nil,    45,   -23,   -82,   -51,   -86,   -40,  -195,   -27,   -39,
+   -78,     6,    37,   nil,  -197,  -155,  -253,   104,    28,   nil,
+   nil,    32,   -48,  -168,   nil,  -231,   nil,   nil,   nil,   nil,
+   nil,   nil,   nil,    36,   -50 ]
 
 racc_goto_default = [
-   nil,   nil,   nil,   114,   105,   111,   244,   115,   nil,     7,
-   126,   116,   127,   nil,   128,   129,   130,   131,   132,   133,
-   134,   135,   136,   137,   179,   140,   220,   218,    48,     5,
-     6,    49,    84,   nil,    57,    13,    58,    22,   nil,   nil,
-   nil,   nil,   159,   nil,   180,   nil,    24,   nil,   nil,    93,
-   nil,   nil,    26,   nil,    96,    51,    52,   335,   150,   151,
-   333,   252,   nil,   nil,   nil,    33,    34,   nil,   227,   nil,
-   nil,   221,   222,   223,   224,   225,   226,   228,   229,   nil ]
+   nil,   nil,   nil,   119,   110,   116,   151,   120,   nil,     7,
+   nil,   nil,   150,   131,   121,   132,   133,   134,   135,   136,
+   137,   138,   139,   140,   141,   142,   143,   nil,   nil,    44,
+   191,    49,     5,     6,     8,    50,    87,   268,    58,    24,
+    59,    27,   nil,   nil,   nil,   nil,   200,   nil,   222,   nil,
+    29,   nil,   nil,    97,   nil,   nil,   nil,   100,    52,    53,
+   376,   nil,   nil,   189,   190,   374,   297,   nil,   nil,    42,
+    43,   nil,   154,   170,   153,   155,   156,   157,   158,   159,
+   160,   161,   162,   nil,   nil ]
 
 racc_reduce_table = [
   0, 0, :racc_error,
-  1, 97, :_reduce_none,
-  1, 99, :_reduce_2,
-  1, 99, :_reduce_3,
-  1, 99, :_reduce_4,
-  1, 99, :_reduce_5,
-  1, 99, :_reduce_6,
-  1, 99, :_reduce_7,
-  1, 99, :_reduce_8,
-  3, 99, :_reduce_9,
-  1, 101, :_reduce_10,
-  2, 101, :_reduce_11,
-  1, 103, :_reduce_none,
-  4, 103, :_reduce_none,
-  5, 103, :_reduce_none,
-  4, 103, :_reduce_15,
-  3, 103, :_reduce_16,
-  3, 103, :_reduce_17,
-  2, 103, :_reduce_18,
-  2, 103, :_reduce_19,
-  0, 104, :_reduce_none,
+  1, 98, :_reduce_none,
+  1, 100, :_reduce_2,
+  1, 100, :_reduce_3,
+  1, 100, :_reduce_4,
+  1, 100, :_reduce_5,
+  1, 100, :_reduce_6,
+  1, 100, :_reduce_7,
+  1, 100, :_reduce_8,
+  3, 100, :_reduce_9,
+  1, 102, :_reduce_10,
+  2, 102, :_reduce_11,
   1, 104, :_reduce_none,
+  4, 104, :_reduce_13,
   3, 104, :_reduce_none,
-  1, 106, :_reduce_none,
-  2, 106, :_reduce_24,
-  2, 106, :_reduce_25,
-  4, 106, :_reduce_26,
-  2, 106, :_reduce_27,
-  2, 106, :_reduce_28,
-  1, 107, :_reduce_29,
-  1, 107, :_reduce_30,
-  1, 107, :_reduce_31,
-  1, 107, :_reduce_32,
-  1, 107, :_reduce_33,
-  1, 107, :_reduce_34,
-  1, 108, :_reduce_none,
-  4, 108, :_reduce_36,
+  4, 104, :_reduce_none,
+  5, 104, :_reduce_none,
+  3, 104, :_reduce_17,
+  3, 104, :_reduce_18,
+  2, 104, :_reduce_19,
+  2, 104, :_reduce_20,
+  6, 104, :_reduce_none,
+  7, 104, :_reduce_none,
+  1, 105, :_reduce_none,
+  3, 105, :_reduce_none,
   1, 110, :_reduce_none,
-  3, 110, :_reduce_38,
-  3, 110, :_reduce_39,
-  3, 110, :_reduce_40,
-  1, 111, :_reduce_none,
-  3, 111, :_reduce_42,
-  3, 111, :_reduce_43,
+  2, 110, :_reduce_26,
+  2, 110, :_reduce_27,
+  4, 110, :_reduce_28,
+  2, 110, :_reduce_29,
+  2, 110, :_reduce_30,
+  1, 111, :_reduce_31,
+  1, 111, :_reduce_32,
+  1, 111, :_reduce_33,
+  1, 111, :_reduce_34,
+  1, 111, :_reduce_35,
+  1, 111, :_reduce_36,
   1, 112, :_reduce_none,
-  3, 112, :_reduce_45,
-  3, 112, :_reduce_46,
+  4, 112, :_reduce_38,
   1, 113, :_reduce_none,
-  3, 113, :_reduce_48,
-  3, 113, :_reduce_49,
-  3, 113, :_reduce_50,
-  3, 113, :_reduce_51,
+  3, 113, :_reduce_40,
+  3, 113, :_reduce_41,
+  3, 113, :_reduce_42,
   1, 114, :_reduce_none,
-  3, 114, :_reduce_53,
-  3, 114, :_reduce_54,
+  3, 114, :_reduce_44,
+  3, 114, :_reduce_45,
   1, 115, :_reduce_none,
-  3, 115, :_reduce_56,
+  3, 115, :_reduce_47,
+  3, 115, :_reduce_48,
   1, 116, :_reduce_none,
-  3, 116, :_reduce_58,
+  3, 116, :_reduce_50,
+  3, 116, :_reduce_51,
+  3, 116, :_reduce_52,
+  3, 116, :_reduce_53,
   1, 117, :_reduce_none,
-  3, 117, :_reduce_60,
+  3, 117, :_reduce_55,
+  3, 117, :_reduce_56,
   1, 118, :_reduce_none,
-  3, 118, :_reduce_62,
+  3, 118, :_reduce_58,
   1, 119, :_reduce_none,
-  3, 119, :_reduce_64,
+  3, 119, :_reduce_60,
   1, 120, :_reduce_none,
-  5, 120, :_reduce_66,
-  1, 102, :_reduce_67,
-  1, 121, :_reduce_68,
-  3, 122, :_reduce_none,
-  1, 123, :_reduce_70,
+  3, 120, :_reduce_62,
+  1, 121, :_reduce_none,
+  3, 121, :_reduce_64,
+  1, 122, :_reduce_none,
+  3, 122, :_reduce_66,
   1, 123, :_reduce_none,
-  1, 123, :_reduce_72,
-  2, 123, :_reduce_73,
-  2, 123, :_reduce_74,
-  2, 123, :_reduce_75,
-  1, 124, :_reduce_76,
-  3, 124, :_reduce_77,
+  5, 123, :_reduce_68,
+  1, 109, :_reduce_none,
+  3, 109, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 124, :_reduce_none,
+  1, 103, :_reduce_82,
+  3, 103, :_reduce_83,
+  1, 125, :_reduce_84,
+  3, 126, :_reduce_none,
+  1, 127, :_reduce_86,
+  2, 127, :_reduce_87,
   1, 127, :_reduce_none,
-  3, 127, :_reduce_79,
-  1, 126, :_reduce_80,
-  1, 126, :_reduce_81,
-  1, 126, :_reduce_82,
-  1, 126, :_reduce_83,
-  1, 126, :_reduce_84,
-  1, 126, :_reduce_85,
-  1, 126, :_reduce_86,
-  1, 126, :_reduce_87,
-  1, 126, :_reduce_88,
-  1, 126, :_reduce_89,
-  1, 126, :_reduce_90,
-  1, 126, :_reduce_91,
-  1, 126, :_reduce_92,
-  1, 126, :_reduce_93,
-  0, 136, :_reduce_94,
-  6, 130, :_reduce_95,
-  0, 137, :_reduce_96,
-  5, 130, :_reduce_97,
-  2, 130, :_reduce_98,
-  1, 133, :_reduce_99,
-  1, 135, :_reduce_none,
-  2, 135, :_reduce_none,
-  1, 134, :_reduce_102,
-  3, 138, :_reduce_103,
-  2, 138, :_reduce_none,
-  2, 138, :_reduce_none,
+  2, 127, :_reduce_89,
+  1, 127, :_reduce_90,
+  2, 127, :_reduce_91,
+  1, 127, :_reduce_none,
+  2, 127, :_reduce_none,
+  1, 128, :_reduce_94,
+  3, 128, :_reduce_95,
+  1, 132, :_reduce_none,
+  3, 132, :_reduce_97,
+  1, 129, :_reduce_none,
+  1, 129, :_reduce_none,
+  1, 129, :_reduce_none,
+  1, 129, :_reduce_none,
+  1, 130, :_reduce_102,
+  1, 130, :_reduce_103,
+  1, 130, :_reduce_104,
+  1, 130, :_reduce_105,
+  1, 130, :_reduce_106,
+  1, 130, :_reduce_107,
+  1, 130, :_reduce_108,
+  1, 130, :_reduce_109,
+  1, 130, :_reduce_110,
+  1, 130, :_reduce_111,
+  1, 130, :_reduce_112,
+  1, 130, :_reduce_113,
+  1, 130, :_reduce_114,
+  1, 130, :_reduce_115,
+  0, 141, :_reduce_116,
+  6, 135, :_reduce_117,
+  0, 142, :_reduce_118,
+  5, 135, :_reduce_119,
+  2, 135, :_reduce_120,
+  1, 138, :_reduce_121,
   1, 140, :_reduce_none,
-  2, 140, :_reduce_107,
-  1, 140, :_reduce_108,
-  2, 140, :_reduce_109,
-  1, 139, :_reduce_110,
-  3, 139, :_reduce_111,
-  1, 141, :_reduce_none,
-  5, 131, :_reduce_none,
-  4, 131, :_reduce_none,
-  2, 131, :_reduce_none,
-  1, 142, :_reduce_116,
-  1, 144, :_reduce_none,
-  2, 144, :_reduce_none,
-  1, 143, :_reduce_none,
-  3, 145, :_reduce_none,
-  2, 145, :_reduce_none,
-  2, 145, :_reduce_none,
+  2, 140, :_reduce_none,
+  1, 139, :_reduce_124,
+  3, 143, :_reduce_125,
+  5, 143, :_reduce_126,
+  2, 143, :_reduce_none,
+  2, 143, :_reduce_none,
+  2, 145, :_reduce_129,
+  1, 145, :_reduce_none,
+  2, 145, :_reduce_131,
+  1, 145, :_reduce_132,
+  1, 144, :_reduce_133,
+  3, 144, :_reduce_134,
   1, 146, :_reduce_none,
-  3, 146, :_reduce_none,
-  1, 147, :_reduce_none,
-  4, 132, :_reduce_none,
-  5, 132, :_reduce_none,
-  2, 132, :_reduce_none,
-  1, 148, :_reduce_129,
+  5, 136, :_reduce_none,
+  4, 136, :_reduce_none,
+  2, 136, :_reduce_none,
+  1, 147, :_reduce_139,
   1, 149, :_reduce_none,
-  3, 149, :_reduce_none,
-  1, 150, :_reduce_none,
+  2, 149, :_reduce_none,
+  1, 148, :_reduce_none,
   3, 150, :_reduce_none,
-  1, 105, :_reduce_134,
-  1, 105, :_reduce_135,
-  2, 128, :_reduce_136,
-  1, 128, :_reduce_none,
-  2, 128, :_reduce_138,
-  1, 152, :_reduce_139,
-  3, 152, :_reduce_140,
-  4, 152, :_reduce_141,
-  3, 152, :_reduce_142,
-  4, 152, :_reduce_143,
-  3, 152, :_reduce_144,
-  1, 151, :_reduce_145,
-  2, 151, :_reduce_146,
-  2, 151, :_reduce_147,
-  3, 151, :_reduce_148,
+  2, 150, :_reduce_none,
+  2, 150, :_reduce_none,
+  1, 151, :_reduce_none,
+  3, 151, :_reduce_none,
+  1, 152, :_reduce_none,
+  2, 152, :_reduce_none,
+  3, 152, :_reduce_none,
+  4, 137, :_reduce_none,
+  5, 137, :_reduce_none,
+  5, 137, :_reduce_none,
+  6, 137, :_reduce_none,
+  2, 137, :_reduce_none,
+  5, 137, :_reduce_none,
+  6, 137, :_reduce_none,
+  2, 137, :_reduce_none,
   1, 153, :_reduce_none,
-  5, 153, :_reduce_none,
+  3, 153, :_reduce_none,
   1, 154, :_reduce_none,
   3, 154, :_reduce_none,
-  2, 155, :_reduce_none,
-  2, 155, :_reduce_none,
-  1, 155, :_reduce_none,
-  1, 109, :_reduce_none,
-  2, 109, :_reduce_none,
-  1, 156, :_reduce_none,
-  1, 156, :_reduce_none,
-  2, 156, :_reduce_none,
-  3, 157, :_reduce_none,
-  2, 157, :_reduce_none,
-  3, 157, :_reduce_none,
-  3, 157, :_reduce_none,
-  4, 157, :_reduce_none,
-  2, 157, :_reduce_166,
-  3, 157, :_reduce_none,
-  3, 157, :_reduce_168,
-  4, 157, :_reduce_none,
-  1, 129, :_reduce_170,
-  3, 129, :_reduce_171,
-  4, 129, :_reduce_172,
-  4, 129, :_reduce_173,
-  1, 158, :_reduce_174,
-  3, 158, :_reduce_175,
-  0, 98, :_reduce_none,
-  2, 98, :_reduce_none,
+  1, 106, :_reduce_163,
+  1, 106, :_reduce_none,
+  1, 106, :_reduce_165,
+  1, 131, :_reduce_none,
+  1, 131, :_reduce_none,
+  1, 131, :_reduce_none,
+  1, 131, :_reduce_none,
+  2, 133, :_reduce_170,
+  1, 133, :_reduce_none,
+  2, 133, :_reduce_172,
+  1, 156, :_reduce_173,
+  3, 156, :_reduce_174,
+  4, 156, :_reduce_175,
+  3, 156, :_reduce_176,
+  4, 156, :_reduce_177,
+  4, 156, :_reduce_none,
+  3, 156, :_reduce_179,
+  1, 155, :_reduce_180,
+  2, 155, :_reduce_181,
+  2, 155, :_reduce_182,
+  3, 155, :_reduce_183,
   1, 159, :_reduce_none,
   2, 159, :_reduce_none,
+  1, 157, :_reduce_none,
+  5, 157, :_reduce_none,
   1, 160, :_reduce_none,
-  1, 160, :_reduce_none,
-  2, 160, :_reduce_none,
-  2, 160, :_reduce_none,
-  1, 160, :_reduce_none,
-  1, 160, :_reduce_none,
-  1, 160, :_reduce_none,
-  4, 161, :_reduce_187,
-  1, 163, :_reduce_188,
-  3, 163, :_reduce_189,
-  3, 162, :_reduce_none,
-  0, 165, :_reduce_none,
+  3, 160, :_reduce_none,
+  2, 161, :_reduce_none,
+  2, 161, :_reduce_none,
+  1, 161, :_reduce_none,
+  1, 158, :_reduce_none,
+  3, 158, :_reduce_none,
+  1, 107, :_reduce_none,
+  2, 107, :_reduce_none,
+  1, 162, :_reduce_none,
+  1, 162, :_reduce_none,
+  2, 162, :_reduce_none,
+  3, 163, :_reduce_none,
+  2, 163, :_reduce_none,
+  3, 163, :_reduce_none,
+  3, 163, :_reduce_none,
+  4, 163, :_reduce_none,
+  2, 163, :_reduce_205,
+  3, 163, :_reduce_none,
+  3, 163, :_reduce_207,
+  4, 163, :_reduce_none,
+  1, 134, :_reduce_209,
+  3, 134, :_reduce_210,
+  4, 134, :_reduce_211,
+  4, 134, :_reduce_212,
+  1, 108, :_reduce_213,
+  3, 108, :_reduce_214,
+  0, 99, :_reduce_none,
+  2, 99, :_reduce_none,
+  1, 164, :_reduce_none,
+  2, 164, :_reduce_none,
+  1, 165, :_reduce_none,
+  1, 165, :_reduce_none,
   2, 165, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  1, 166, :_reduce_none,
-  5, 167, :_reduce_none,
-  7, 167, :_reduce_none,
-  5, 168, :_reduce_none,
-  7, 169, :_reduce_none,
-  9, 170, :_reduce_none,
-  5, 171, :_reduce_none,
-  3, 172, :_reduce_none,
-  4, 172, :_reduce_none,
-  3, 172, :_reduce_none,
-  3, 164, :_reduce_none,
-  3, 173, :_reduce_none,
-  2, 173, :_reduce_none,
-  2, 173, :_reduce_none,
-  3, 173, :_reduce_none,
-  2, 173, :_reduce_none,
-  2, 174, :_reduce_none,
-  4, 174, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 175, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 125, :_reduce_none,
-  1, 100, :_reduce_240,
-  2, 100, :_reduce_241,
-  3, 100, :_reduce_242 ]
-
-racc_reduce_n = 243
-
-racc_shift_n = 400
+  2, 165, :_reduce_none,
+  1, 165, :_reduce_none,
+  1, 165, :_reduce_none,
+  1, 165, :_reduce_none,
+  4, 166, :_reduce_226,
+  1, 168, :_reduce_227,
+  3, 168, :_reduce_228,
+  3, 167, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  1, 170, :_reduce_none,
+  3, 171, :_reduce_none,
+  4, 171, :_reduce_none,
+  3, 171, :_reduce_none,
+  2, 169, :_reduce_none,
+  3, 169, :_reduce_none,
+  1, 180, :_reduce_none,
+  2, 180, :_reduce_none,
+  1, 181, :_reduce_none,
+  1, 181, :_reduce_none,
+  1, 172, :_reduce_none,
+  2, 172, :_reduce_none,
+  5, 173, :_reduce_none,
+  7, 173, :_reduce_none,
+  5, 177, :_reduce_none,
+  5, 174, :_reduce_none,
+  7, 175, :_reduce_none,
+  6, 176, :_reduce_none,
+  7, 176, :_reduce_none,
+  6, 176, :_reduce_none,
+  7, 176, :_reduce_none,
+  3, 178, :_reduce_none,
+  2, 178, :_reduce_none,
+  2, 178, :_reduce_none,
+  2, 178, :_reduce_none,
+  3, 178, :_reduce_none,
+  1, 101, :_reduce_265,
+  2, 101, :_reduce_266,
+  3, 101, :_reduce_267,
+  1, 179, :_reduce_268 ]
+
+racc_reduce_n = 269
+
+racc_shift_n = 447
 
 racc_token_table = {
@@ -1014,85 +1101,86 @@
   "++" => 15,
   "--" => 16,
-  "," => 17,
-  :SIZEOF => 18,
-  "&" => 19,
-  "*" => 20,
-  "+" => 21,
-  "-" => 22,
-  "~" => 23,
-  "!" => 24,
-  "/" => 25,
-  "%" => 26,
-  "<<" => 27,
-  ">>" => 28,
-  "<" => 29,
-  ">" => 30,
-  "<=" => 31,
-  ">=" => 32,
-  "==" => 33,
-  "!=" => 34,
-  "^" => 35,
-  "|" => 36,
-  "&&" => 37,
-  "||" => 38,
-  "?" => 39,
-  ":" => 40,
-  ";" => 41,
-  "=" => 42,
-  :VOID => 43,
-  :FLOAT => 44,
-  :DOUBLE => 45,
-  :BOOL => 46,
-  :TYPE_NAME => 47,
-  :CHAR => 48,
-  :SHORT => 49,
-  :INT => 50,
-  :LONG => 51,
-  :SIGNED => 52,
-  :UNSIGNED => 53,
-  "{" => 54,
-  "}" => 55,
-  :STRUCT => 56,
-  :UNION => 57,
-  :ENUM => 58,
-  :CONST => 59,
-  :VOLATILE => 60,
-  :C_EXP => 61,
-  :EXTENSION => 62,
-  :TYPEDEF => 63,
-  :IF => 64,
-  :ELSE => 65,
-  :WHILE => 66,
-  :DO => 67,
-  :FOR => 68,
-  :SWITCH => 69,
-  :infunc_statment => 70,
-  :CASE => 71,
-  :DEFAULT => 72,
-  :GOTO => 73,
-  :CONTINUE => 74,
-  :BREAK => 75,
-  :RETURN => 76,
-  "+=" => 77,
-  "-=" => 78,
-  "*=" => 79,
-  "/=" => 80,
-  "%=" => 81,
-  "<<=" => 82,
-  ">>=" => 83,
-  "&=" => 84,
-  "|=" => 85,
-  "^=" => 86,
-  :__INLINE__ => 87,
-  :INLINE => 88,
-  :__INLINE => 89,
-  :CINLINE => 90,
-  :EXTERN => 91,
-  :STATIC => 92,
-  :AUTO => 93,
-  :REGISTER => 94,
-  "::" => 95 }
-
-racc_nt_base = 96
+  "{" => 17,
+  "}" => 18,
+  "," => 19,
+  :SIZEOF => 20,
+  "&" => 21,
+  "*" => 22,
+  "+" => 23,
+  "-" => 24,
+  "~" => 25,
+  "!" => 26,
+  "/" => 27,
+  "%" => 28,
+  "<<" => 29,
+  ">>" => 30,
+  "<" => 31,
+  ">" => 32,
+  "<=" => 33,
+  ">=" => 34,
+  "==" => 35,
+  "!=" => 36,
+  "^" => 37,
+  "|" => 38,
+  "&&" => 39,
+  "||" => 40,
+  "?" => 41,
+  ":" => 42,
+  "=" => 43,
+  "+=" => 44,
+  "-=" => 45,
+  "*=" => 46,
+  "/=" => 47,
+  "%=" => 48,
+  "<<=" => 49,
+  ">>=" => 50,
+  "&=" => 51,
+  "|=" => 52,
+  "^=" => 53,
+  ";" => 54,
+  :EXTERN => 55,
+  :STATIC => 56,
+  :AUTO => 57,
+  :REGISTER => 58,
+  :VOID => 59,
+  :CHAR => 60,
+  :SHORT => 61,
+  :INT => 62,
+  :LONG => 63,
+  :FLOAT => 64,
+  :DOUBLE => 65,
+  :SIGNED => 66,
+  :UNSIGNED => 67,
+  :BOOL => 68,
+  :TYPE_NAME => 69,
+  :STRUCT => 70,
+  :UNION => 71,
+  :ENUM => 72,
+  :CONST => 73,
+  :RESTRICT => 74,
+  :VOLATILE => 75,
+  :__INLINE__ => 76,
+  :INLINE => 77,
+  :__INLINE => 78,
+  :CINLINE => 79,
+  :C_EXP => 80,
+  :EXTENSION => 81,
+  :TYPEDEF => 82,
+  :CASE => 83,
+  :DEFAULT => 84,
+  :IF => 85,
+  :ELSE => 86,
+  :SWITCH => 87,
+  :WHILE => 88,
+  :DO => 89,
+  :FOR => 90,
+  :GOTO => 91,
+  :CONTINUE => 92,
+  :BREAK => 93,
+  :RETURN => 94,
+  "::" => 95,
+  :_ASM => 96 }
+
+racc_nt_base = 97
 
 racc_use_result_var = true
@@ -1132,4 +1220,6 @@
   "\"++\"",
   "\"--\"",
+  "\"{\"",
+  "\"}\"",
   "\",\"",
   "SIZEOF",
@@ -1156,40 +1246,5 @@
   "\"?\"",
   "\":\"",
-  "\";\"",
   "\"=\"",
-  "VOID",
-  "FLOAT",
-  "DOUBLE",
-  "BOOL",
-  "TYPE_NAME",
-  "CHAR",
-  "SHORT",
-  "INT",
-  "LONG",
-  "SIGNED",
-  "UNSIGNED",
-  "\"{\"",
-  "\"}\"",
-  "STRUCT",
-  "UNION",
-  "ENUM",
-  "CONST",
-  "VOLATILE",
-  "C_EXP",
-  "EXTENSION",
-  "TYPEDEF",
-  "IF",
-  "ELSE",
-  "WHILE",
-  "DO",
-  "FOR",
-  "SWITCH",
-  "infunc_statment",
-  "CASE",
-  "DEFAULT",
-  "GOTO",
-  "CONTINUE",
-  "BREAK",
-  "RETURN",
   "\"+=\"",
   "\"-=\"",
@@ -1202,13 +1257,47 @@
   "\"|=\"",
   "\"^=\"",
+  "\";\"",
+  "EXTERN",
+  "STATIC",
+  "AUTO",
+  "REGISTER",
+  "VOID",
+  "CHAR",
+  "SHORT",
+  "INT",
+  "LONG",
+  "FLOAT",
+  "DOUBLE",
+  "SIGNED",
+  "UNSIGNED",
+  "BOOL",
+  "TYPE_NAME",
+  "STRUCT",
+  "UNION",
+  "ENUM",
+  "CONST",
+  "RESTRICT",
+  "VOLATILE",
   "__INLINE__",
   "INLINE",
   "__INLINE",
   "CINLINE",
-  "EXTERN",
-  "STATIC",
-  "AUTO",
-  "REGISTER",
+  "C_EXP",
+  "EXTENSION",
+  "TYPEDEF",
+  "CASE",
+  "DEFAULT",
+  "IF",
+  "ELSE",
+  "SWITCH",
+  "WHILE",
+  "DO",
+  "FOR",
+  "GOTO",
+  "CONTINUE",
+  "BREAK",
+  "RETURN",
   "\"::\"",
+  "_ASM",
   "$start",
   "all",
@@ -1219,10 +1308,12 @@
   "expression",
   "postfix_expression",
-  "argument_list",
+  "argument_expression_list",
   "type_qualifier",
+  "type_name",
+  "initializer_list",
+  "assignment_expression",
   "unary_expression",
   "unary_operator",
   "cast_expression",
-  "type_name",
   "multiplicative_expression",
   "additive_expression",
@@ -1236,10 +1327,12 @@
   "logical_or_expression",
   "conditional_expression",
+  "assignment_operator",
   "constant_expression",
   "declaration",
   "declaration_specifiers",
   "init_declarator_list",
-  "storage_class",
+  "storage_class_specifier",
   "type_specifier",
+  "function_specifier",
   "init_declarator",
   "declarator",
@@ -1255,5 +1348,5 @@
   "struct_declaration",
   "struct_declarator_list",
-  "type_specifier_qualifier_list",
+  "specifier_qualifier_list",
   "struct_declarator",
   "union_term",
@@ -1263,5 +1356,4 @@
   "union_declarator_list",
   "union_declarator",
-  "enum_type",
   "enumerator_list",
   "enumerator",
@@ -1269,17 +1361,19 @@
   "direct_declarator",
   "parameter_type_list",
+  "identifier_list",
+  "type_qualifier_list",
   "parameter_list",
   "parameter_declaration",
   "abstract_declarator",
   "direct_abstract_declarator",
-  "initializer_list",
   "extension_statement",
-  "statement",
+  "cdl_statement",
   "typedef",
   "func_def",
   "declarator_list",
-  "compoundstatement",
-  "infunc_statement_list",
-  "infunc_statement",
+  "compound_statement",
+  "statement",
+  "labeled_statement",
+  "expression_statement",
   "ifstatement",
   "whilestatement",
@@ -1287,8 +1381,8 @@
   "forstatement",
   "switchstatement",
-  "labelstatement",
-  "gotostatement",
-  "expressionstatement",
-  "assignment_operator" ]
+  "jump_statement",
+  "asm_statement",
+  "block_item_list",
+  "block_item" ]
 
 Racc_debug_parser = false
@@ -1300,5 +1394,5 @@
 # reduce 1 omitted
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 52)
+module_eval(<<'.,.,', 'C_parser.y.rb', 57)
   def _reduce_2(val, _values, result)
      result = [ :IDENTIFIER, val[0] ] 
@@ -1307,5 +1401,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 60)
+module_eval(<<'.,.,', 'C_parser.y.rb', 65)
   def _reduce_3(val, _values, result)
      result = [ :INTEGER_CONSTANT, val[0] ] 
@@ -1314,5 +1408,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 62)
+module_eval(<<'.,.,', 'C_parser.y.rb', 67)
   def _reduce_4(val, _values, result)
      result = [ :FLOATING_CONSTANT, val[0] ] 
@@ -1321,5 +1415,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 64)
+module_eval(<<'.,.,', 'C_parser.y.rb', 69)
   def _reduce_5(val, _values, result)
      result = [ :OCTAL_CONSTANT, val[0] ] 
@@ -1328,5 +1422,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 66)
+module_eval(<<'.,.,', 'C_parser.y.rb', 71)
   def _reduce_6(val, _values, result)
      result = [ :HEX_CONSTANT, val[0] ] 
@@ -1335,5 +1429,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 68)
+module_eval(<<'.,.,', 'C_parser.y.rb', 73)
   def _reduce_7(val, _values, result)
      result = [ :CHARACTER_LITERAL, val[0] ] 
@@ -1342,5 +1436,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 70)
+module_eval(<<'.,.,', 'C_parser.y.rb', 75)
   def _reduce_8(val, _values, result)
      result = [ :STRING_LITERAL_LIST, val[0] ] 
@@ -1349,5 +1443,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 72)
+module_eval(<<'.,.,', 'C_parser.y.rb', 77)
   def _reduce_9(val, _values, result)
      result = [ :PARENTHESES, val[1].get_elements ] 
@@ -1356,5 +1450,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 76)
+module_eval(<<'.,.,', 'C_parser.y.rb', 81)
   def _reduce_10(val, _values, result)
      result = [val[0]] 
@@ -1363,5 +1457,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 78)
+module_eval(<<'.,.,', 'C_parser.y.rb', 83)
   def _reduce_11(val, _values, result)
      result << val[1] 
@@ -1372,17 +1466,19 @@
 # reduce 12 omitted
 
-# reduce 13 omitted
+module_eval(<<'.,.,', 'C_parser.y.rb', 89)
+  def _reduce_13(val, _values, result)
+     result = [ :OP_SUBSC, val[0], val[2] ] 
+    result
+  end
+.,.,
 
 # reduce 14 omitted
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 86)
-  def _reduce_15(val, _values, result)
-     result = [ :OP_SUBSC, val[0], val[2] ] 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 88)
-  def _reduce_16(val, _values, result)
+# reduce 15 omitted
+
+# reduce 16 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 94)
+  def _reduce_17(val, _values, result)
      result = [ :OP_DOT, val[0], val[2] ] 
     result
@@ -1390,6 +1486,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 90)
-  def _reduce_17(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 96)
+  def _reduce_18(val, _values, result)
      result = [ :OP_REF, val[0], val[2] ] 
     result
@@ -1397,12 +1493,5 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 91)
-  def _reduce_18(val, _values, result)
-     result = val[0] 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 92)
+module_eval(<<'.,.,', 'C_parser.y.rb', 97)
   def _reduce_19(val, _values, result)
      result = val[0] 
@@ -1411,5 +1500,10 @@
 .,.,
 
-# reduce 20 omitted
+module_eval(<<'.,.,', 'C_parser.y.rb', 98)
+  def _reduce_20(val, _values, result)
+     result = val[0] 
+    result
+  end
+.,.,
 
 # reduce 21 omitted
@@ -1419,6 +1513,10 @@
 # reduce 23 omitted
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 104)
-  def _reduce_24(val, _values, result)
+# reduce 24 omitted
+
+# reduce 25 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 111)
+  def _reduce_26(val, _values, result)
      result = [ val[0], val[1] ] 
     result
@@ -1426,6 +1524,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 106)
-  def _reduce_25(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 113)
+  def _reduce_27(val, _values, result)
      result = [ :OP_SIZEOF_EXPR, val[1] ] 
     result
@@ -1433,6 +1531,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 108)
-  def _reduce_26(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 115)
+  def _reduce_28(val, _values, result)
      result = [ :OP_SIZEOF_TYPE, val[1] ] 
     result
@@ -1440,6 +1538,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 109)
-  def _reduce_27(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 116)
+  def _reduce_29(val, _values, result)
      result = val[1] 
     result
@@ -1447,6 +1545,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 110)
-  def _reduce_28(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 117)
+  def _reduce_30(val, _values, result)
      result = val[1] 
     result
@@ -1454,6 +1552,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 113)
-  def _reduce_29(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 120)
+  def _reduce_31(val, _values, result)
      result = :OP_U_AMP 
     result
@@ -1461,6 +1559,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 114)
-  def _reduce_30(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 121)
+  def _reduce_32(val, _values, result)
      result = :OP_U_ASTER 
     result
@@ -1468,6 +1566,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 115)
-  def _reduce_31(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 122)
+  def _reduce_33(val, _values, result)
      result = :OP_U_PLUS 
     result
@@ -1475,6 +1573,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 116)
-  def _reduce_32(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 123)
+  def _reduce_34(val, _values, result)
      result = :OP_U_MINUS 
     result
@@ -1482,6 +1580,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 117)
-  def _reduce_33(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 124)
+  def _reduce_35(val, _values, result)
      result = :OP_U_TILDE 
     result
@@ -1489,6 +1587,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 118)
-  def _reduce_34(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 125)
+  def _reduce_36(val, _values, result)
      result = :OP_U_EXCLAM 
     result
@@ -1496,8 +1594,8 @@
 .,.,
 
-# reduce 35 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 123)
-  def _reduce_36(val, _values, result)
+# reduce 37 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 130)
+  def _reduce_38(val, _values, result)
       result = [ :CAST, val[1], val[3] ] 
     result
@@ -1505,8 +1603,8 @@
 .,.,
 
-# reduce 37 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 128)
-  def _reduce_38(val, _values, result)
+# reduce 39 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 135)
+  def _reduce_40(val, _values, result)
      result = [ :OP_MULT, val[0], val[2] ]  
     result
@@ -1514,6 +1612,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 130)
-  def _reduce_39(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 137)
+  def _reduce_41(val, _values, result)
      result = [ :OP_DIV, val[0], val[2] ]  
     result
@@ -1521,6 +1619,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 132)
-  def _reduce_40(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 139)
+  def _reduce_42(val, _values, result)
      result = [ :OP_REMAIN, val[0], val[2] ]  
     result
@@ -1528,8 +1626,8 @@
 .,.,
 
-# reduce 41 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 137)
-  def _reduce_42(val, _values, result)
+# reduce 43 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 144)
+  def _reduce_44(val, _values, result)
      result = [ :OP_ADD, val[0], val[2] ]  
     result
@@ -1537,6 +1635,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 139)
-  def _reduce_43(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 146)
+  def _reduce_45(val, _values, result)
      result = [ :OP_SUB, val[0], val[2] ]  
     result
@@ -1544,8 +1642,8 @@
 .,.,
 
-# reduce 44 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 144)
-  def _reduce_45(val, _values, result)
+# reduce 46 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 151)
+  def _reduce_47(val, _values, result)
      result = [ :OP_LSFT, val[0], val[2] ]  
     result
@@ -1553,6 +1651,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 146)
-  def _reduce_46(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 153)
+  def _reduce_48(val, _values, result)
      result = [ :OP_RSFT, val[0], val[2] ]  
     result
@@ -1560,8 +1658,8 @@
 .,.,
 
-# reduce 47 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 151)
-  def _reduce_48(val, _values, result)
+# reduce 49 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 158)
+  def _reduce_50(val, _values, result)
      result = [ :OP_LT, val[0], val[2] ]  
     result
@@ -1569,6 +1667,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 153)
-  def _reduce_49(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 160)
+  def _reduce_51(val, _values, result)
      result = [ :OP_GT, val[0], val[2] ]  
     result
@@ -1576,6 +1674,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 155)
-  def _reduce_50(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 162)
+  def _reduce_52(val, _values, result)
      result = [ :OP_LE, val[0], val[2] ]  
     result
@@ -1583,6 +1681,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 157)
-  def _reduce_51(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 164)
+  def _reduce_53(val, _values, result)
      result = [ :OP_GE, val[0], val[2] ]  
     result
@@ -1590,8 +1688,8 @@
 .,.,
 
-# reduce 52 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 162)
-  def _reduce_53(val, _values, result)
+# reduce 54 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 169)
+  def _reduce_55(val, _values, result)
      result = [ :OP_EQ, val[0], val[2] ]  
     result
@@ -1599,6 +1697,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 164)
-  def _reduce_54(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 171)
+  def _reduce_56(val, _values, result)
      result = [ :OP_NE, val[0], val[2] ]  
     result
@@ -1606,8 +1704,8 @@
 .,.,
 
-# reduce 55 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 169)
-  def _reduce_56(val, _values, result)
+# reduce 57 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 176)
+  def _reduce_58(val, _values, result)
      result = [ :OP_AND, val[0], val[2] ]  
     result
@@ -1615,8 +1713,8 @@
 .,.,
 
-# reduce 57 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 174)
-  def _reduce_58(val, _values, result)
+# reduce 59 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 181)
+  def _reduce_60(val, _values, result)
      result = [ :OP_EOR, val[0], val[2] ]  
     result
@@ -1624,8 +1722,8 @@
 .,.,
 
-# reduce 59 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 179)
-  def _reduce_60(val, _values, result)
+# reduce 61 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 186)
+  def _reduce_62(val, _values, result)
      result = [ :OP_OR, val[0], val[2] ]  
     result
@@ -1633,8 +1731,8 @@
 .,.,
 
-# reduce 61 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 184)
-  def _reduce_62(val, _values, result)
+# reduce 63 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 191)
+  def _reduce_64(val, _values, result)
      result = [ :OP_LAND, val[0], val[2] ]  
     result
@@ -1642,8 +1740,8 @@
 .,.,
 
-# reduce 63 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 189)
-  def _reduce_64(val, _values, result)
+# reduce 65 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 196)
+  def _reduce_66(val, _values, result)
      result = [ :OP_LOR, val[0], val[2] ]  
     result
@@ -1651,8 +1749,8 @@
 .,.,
 
-# reduce 65 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 194)
-  def _reduce_66(val, _values, result)
+# reduce 67 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 201)
+  def _reduce_68(val, _values, result)
      result = [ :OP_CEX, val[0], val[2].get_elements, val[4] ]  
     result
@@ -1660,6 +1758,32 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 201)
-  def _reduce_67(val, _values, result)
+# reduce 69 omitted
+
+# reduce 70 omitted
+
+# reduce 71 omitted
+
+# reduce 72 omitted
+
+# reduce 73 omitted
+
+# reduce 74 omitted
+
+# reduce 75 omitted
+
+# reduce 76 omitted
+
+# reduce 77 omitted
+
+# reduce 78 omitted
+
+# reduce 79 omitted
+
+# reduce 80 omitted
+
+# reduce 81 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 223)
+  def _reduce_82(val, _values, result)
     			result = Expression.new( val[0] )
 			# result.print
@@ -1669,6 +1793,14 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 208)
-  def _reduce_68(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 228)
+  def _reduce_83(val, _values, result)
+    			result = Expression.new( val[2] )    # ',' の後ろを採用
+		
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 234)
+  def _reduce_84(val, _values, result)
     			result = Expression.new( val[0] )
 			# result.print
@@ -1685,8 +1817,8 @@
 .,.,
 
-# reduce 69 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 237)
-  def _reduce_70(val, _values, result)
+# reduce 85 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 261)
+  def _reduce_86(val, _values, result)
     			result = CIntType.new( -3 )    # storage class は無視
 		
@@ -1695,8 +1827,24 @@
 .,.,
 
-# reduce 71 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 242)
-  def _reduce_72(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 265)
+  def _reduce_87(val, _values, result)
+    			result = val[1]                # storage class は無視
+		
+    result
+  end
+.,.,
+
+# reduce 88 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 270)
+  def _reduce_89(val, _values, result)
+    			result = val[1].merge val[0]
+		
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 274)
+  def _reduce_90(val, _values, result)
     			result = CIntType.new( -3 )
 			result.set_qualifier val[0]
@@ -1706,31 +1854,19 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 247)
-  def _reduce_73(val, _values, result)
-    			result = val[1]                # storage class は無視
-		
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 251)
-  def _reduce_74(val, _values, result)
-    			result = val[1].merge val[0]
-		
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 255)
-  def _reduce_75(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 279)
+  def _reduce_91(val, _values, result)
     			val[1].set_qualifier val[0]
-                        result = val[1]
-		
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 262)
-  def _reduce_76(val, _values, result)
+						result = val[1]
+		
+    result
+  end
+.,.,
+
+# reduce 92 omitted
+
+# reduce 93 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 287)
+  def _reduce_94(val, _values, result)
      result = [val[0]] 
     result
@@ -1738,6 +1874,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 264)
-  def _reduce_77(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 289)
+  def _reduce_95(val, _values, result)
      result << val[2] 
     result
@@ -1745,8 +1881,8 @@
 .,.,
 
-# reduce 78 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 269)
-  def _reduce_79(val, _values, result)
+# reduce 96 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 294)
+  def _reduce_97(val, _values, result)
      val[0].set_initializer( val[2] ) 
     result
@@ -1754,6 +1890,14 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 272)
-  def _reduce_80(val, _values, result)
+# reduce 98 omitted
+
+# reduce 99 omitted
+
+# reduce 100 omitted
+
+# reduce 101 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 304)
+  def _reduce_102(val, _values, result)
      set_no_type_name true; result = CVoidType.new 
     result
@@ -1761,6 +1905,34 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 273)
-  def _reduce_81(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 306)
+  def _reduce_103(val, _values, result)
+     set_no_type_name true; result = CIntType.new(-11 ) 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 308)
+  def _reduce_104(val, _values, result)
+     set_no_type_name true; result = CIntType.new( -2 ) 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 310)
+  def _reduce_105(val, _values, result)
+     set_no_type_name true; result = CIntType.new( -3 ) 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 312)
+  def _reduce_106(val, _values, result)
+     set_no_type_name true; result = CIntType.new( -4 ) 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 314)
+  def _reduce_107(val, _values, result)
      set_no_type_name true; result = CFloatType.new(-32) 
     result
@@ -1768,6 +1940,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 274)
-  def _reduce_82(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 316)
+  def _reduce_108(val, _values, result)
      set_no_type_name true; result = CFloatType.new(-64) 
     result
@@ -1775,69 +1947,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 275)
-  def _reduce_83(val, _values, result)
-     set_no_type_name true; result = CBoolType.new 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 276)
-  def _reduce_84(val, _values, result)
-     set_no_type_name true; result = val[0] 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 277)
-  def _reduce_85(val, _values, result)
-     set_no_type_name true; result = CVoidType.new 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 278)
-  def _reduce_86(val, _values, result)
-     set_no_type_name true; result = CVoidType.new 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 279)
-  def _reduce_87(val, _values, result)
-     set_no_type_name true; result = CDefinedType.new( val[0].val ) 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 281)
-  def _reduce_88(val, _values, result)
-     set_no_type_name true; result = CIntType.new(-11 ) 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 282)
-  def _reduce_89(val, _values, result)
-     set_no_type_name true; result = CIntType.new( -2 ) 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 283)
-  def _reduce_90(val, _values, result)
-     set_no_type_name true; result = CIntType.new( -3 ) 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 284)
-  def _reduce_91(val, _values, result)
-     set_no_type_name true; result = CIntType.new( -4 ) 
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 287)
-  def _reduce_92(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 319)
+  def _reduce_109(val, _values, result)
     			set_no_type_name true
 			result = CIntType.new( -3 )
@@ -1848,6 +1957,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 293)
-  def _reduce_93(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 325)
+  def _reduce_110(val, _values, result)
     			set_no_type_name true
 			result = CIntType.new( -3 )
@@ -1858,6 +1967,41 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 302)
-  def _reduce_94(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 330)
+  def _reduce_111(val, _values, result)
+     set_no_type_name true; result = CBoolType.new 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 332)
+  def _reduce_112(val, _values, result)
+     set_no_type_name true; result = val[0] 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 334)
+  def _reduce_113(val, _values, result)
+     set_no_type_name true; result = CVoidType.new 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 336)
+  def _reduce_114(val, _values, result)
+     set_no_type_name true; result = CVoidType.new 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 338)
+  def _reduce_115(val, _values, result)
+     set_no_type_name true; result = CDefinedType.new( val[0].val ) 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 344)
+  def _reduce_116(val, _values, result)
      StructType.set_define( true )  
     result
@@ -1865,6 +2009,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 305)
-  def _reduce_95(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 347)
+  def _reduce_117(val, _values, result)
     			StructType.end_of_parse
 			result = val[1]
@@ -1874,6 +2018,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 311)
-  def _reduce_96(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 353)
+  def _reduce_118(val, _values, result)
     			result = CStructType.new()
 			StructType.set_define( true )
@@ -1883,6 +2027,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 316)
-  def _reduce_97(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 358)
+  def _reduce_119(val, _values, result)
     			StructType.end_of_parse
 			result = val[1]
@@ -1892,6 +2036,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 322)
-  def _reduce_98(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 364)
+  def _reduce_120(val, _values, result)
     			StructType.set_define( false )
 			StructType.end_of_parse
@@ -1902,6 +2046,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 328)
-  def _reduce_99(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 370)
+  def _reduce_121(val, _values, result)
      set_no_type_name true 
     result
@@ -1909,10 +2053,10 @@
 .,.,
 
-# reduce 100 omitted
-
-# reduce 101 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 337)
-  def _reduce_102(val, _values, result)
+# reduce 122 omitted
+
+# reduce 123 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 379)
+  def _reduce_124(val, _values, result)
     			result = CStructType.new( val[0].val )
 			set_no_type_name true
@@ -1922,6 +2066,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 346)
-  def _reduce_103(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 388)
+  def _reduce_125(val, _values, result)
     			val[1].each { |i|	# i: Decl
 				i.set_type( val[0] )
@@ -1936,12 +2080,24 @@
 .,.,
 
-# reduce 104 omitted
-
-# reduce 105 omitted
-
-# reduce 106 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 365)
-  def _reduce_107(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 399)
+  def _reduce_126(val, _values, result)
+    			val[1].each { |i|	# i: Decl
+				i.set_type( val[0] )
+				i.set_kind( :MEMBER )
+				i.check
+				CStructType.new_member( i )
+			}
+			result = val[1]
+		
+    result
+  end
+.,.,
+
+# reduce 127 omitted
+
+# reduce 128 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 417)
+  def _reduce_129(val, _values, result)
     			result = val[1].merge val[0]
 		
@@ -1950,6 +2106,17 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 369)
-  def _reduce_108(val, _values, result)
+# reduce 130 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 422)
+  def _reduce_131(val, _values, result)
+    			val[1].set_qualifier val[0]
+						result = val[1]
+		
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 427)
+  def _reduce_132(val, _values, result)
     			result = CIntType.new( -3 )
 			result.set_qualifier val[0]
@@ -1959,15 +2126,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 374)
-  def _reduce_109(val, _values, result)
-    			val[1].set_qualifier val[0]
-                        result = val[1]
-		
-    result
-  end
-.,.,
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 380)
-  def _reduce_110(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 433)
+  def _reduce_133(val, _values, result)
      result = [ val[0] ] 
     result
@@ -1975,6 +2133,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 382)
-  def _reduce_111(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 435)
+  def _reduce_134(val, _values, result)
      result << val[2] 
     result
@@ -1982,14 +2140,14 @@
 .,.,
 
-# reduce 112 omitted
-
-# reduce 113 omitted
-
-# reduce 114 omitted
-
-# reduce 115 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 399)
-  def _reduce_116(val, _values, result)
+# reduce 135 omitted
+
+# reduce 136 omitted
+
+# reduce 137 omitted
+
+# reduce 138 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 452)
+  def _reduce_139(val, _values, result)
      set_no_type_name true 
     result
@@ -1997,45 +2155,52 @@
 .,.,
 
-# reduce 117 omitted
-
-# reduce 118 omitted
-
-# reduce 119 omitted
-
-# reduce 120 omitted
-
-# reduce 121 omitted
-
-# reduce 122 omitted
-
-# reduce 123 omitted
-
-# reduce 124 omitted
-
-# reduce 125 omitted
-
-# reduce 126 omitted
-
-# reduce 127 omitted
-
-# reduce 128 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 430)
-  def _reduce_129(val, _values, result)
-     result = CEnumType.new( -1 ) 
-    result
-  end
-.,.,
-
-# reduce 130 omitted
-
-# reduce 131 omitted
-
-# reduce 132 omitted
-
-# reduce 133 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 446)
-  def _reduce_134(val, _values, result)
+# reduce 140 omitted
+
+# reduce 141 omitted
+
+# reduce 142 omitted
+
+# reduce 143 omitted
+
+# reduce 144 omitted
+
+# reduce 145 omitted
+
+# reduce 146 omitted
+
+# reduce 147 omitted
+
+# reduce 148 omitted
+
+# reduce 149 omitted
+
+# reduce 150 omitted
+
+# reduce 151 omitted
+
+# reduce 152 omitted
+
+# reduce 153 omitted
+
+# reduce 154 omitted
+
+# reduce 155 omitted
+
+# reduce 156 omitted
+
+# reduce 157 omitted
+
+# reduce 158 omitted
+
+# reduce 159 omitted
+
+# reduce 160 omitted
+
+# reduce 161 omitted
+
+# reduce 162 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 495)
+  def _reduce_163(val, _values, result)
      result = :CONST 
     result
@@ -2043,6 +2208,8 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 447)
-  def _reduce_135(val, _values, result)
+# reduce 164 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 498)
+  def _reduce_165(val, _values, result)
      result = :VOLATILE 
     result
@@ -2050,6 +2217,14 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 452)
-  def _reduce_136(val, _values, result)
+# reduce 166 omitted
+
+# reduce 167 omitted
+
+# reduce 168 omitted
+
+# reduce 169 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 509)
+  def _reduce_170(val, _values, result)
     			val[1].set_type( val[0] )
 			result = val[1]
@@ -2059,8 +2234,8 @@
 .,.,
 
-# reduce 137 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 458)
-  def _reduce_138(val, _values, result)
+# reduce 171 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 515)
+  def _reduce_172(val, _values, result)
     			result = Decl.new( val[1].val )
 			result.set_type( val[0] )
@@ -2070,6 +2245,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 464)
-  def _reduce_139(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 521)
+  def _reduce_173(val, _values, result)
      result = Decl.new( val[0].val ) 
     result
@@ -2077,6 +2252,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 466)
-  def _reduce_140(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 523)
+  def _reduce_174(val, _values, result)
      result = val[1] 
     result
@@ -2084,6 +2259,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 469)
-  def _reduce_141(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 526)
+  def _reduce_175(val, _values, result)
     			val[0].set_type( CArrayType.new( val[2] ) )
 			result = val[0]
@@ -2093,6 +2268,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 474)
-  def _reduce_142(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 531)
+  def _reduce_176(val, _values, result)
     			val[0].set_type( CArrayType.new )
 			result = val[0]
@@ -2102,6 +2277,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 479)
-  def _reduce_143(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 536)
+  def _reduce_177(val, _values, result)
     		# 	Generator.warning( "W6001 need 'void' for no parameter"  )
 			val[0].set_type( CFuncType.new )
@@ -2112,6 +2287,8 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 487)
-  def _reduce_144(val, _values, result)
+# reduce 178 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 543)
+  def _reduce_179(val, _values, result)
     		# 	Generator.warning( "W6002 need 'void' for no parameter"  )
 			val[0].set_type( CFuncType.new )
@@ -2122,6 +2299,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 494)
-  def _reduce_145(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 550)
+  def _reduce_180(val, _values, result)
      result = CPtrType.new 
     result
@@ -2129,6 +2306,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 497)
-  def _reduce_146(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 553)
+  def _reduce_181(val, _values, result)
     			result = CPtrType.new
 			result.set_qualifier( val[1] )
@@ -2138,6 +2315,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 502)
-  def _reduce_147(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 558)
+  def _reduce_182(val, _values, result)
     			val[1].set_type(CPtrType.new)
 			result = val[1]
@@ -2147,6 +2324,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 507)
-  def _reduce_148(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 563)
+  def _reduce_183(val, _values, result)
     			ptrtype = CPtrType.new
 			ptrtype.set_qualifier( val[1] )
@@ -2158,40 +2335,48 @@
 .,.,
 
-# reduce 149 omitted
-
-# reduce 150 omitted
-
-# reduce 151 omitted
-
-# reduce 152 omitted
-
-# reduce 153 omitted
-
-# reduce 154 omitted
-
-# reduce 155 omitted
-
-# reduce 156 omitted
-
-# reduce 157 omitted
-
-# reduce 158 omitted
-
-# reduce 159 omitted
-
-# reduce 160 omitted
-
-# reduce 161 omitted
-
-# reduce 162 omitted
-
-# reduce 163 omitted
-
-# reduce 164 omitted
-
-# reduce 165 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 571)
-  def _reduce_166(val, _values, result)
+# reduce 184 omitted
+
+# reduce 185 omitted
+
+# reduce 186 omitted
+
+# reduce 187 omitted
+
+# reduce 188 omitted
+
+# reduce 189 omitted
+
+# reduce 190 omitted
+
+# reduce 191 omitted
+
+# reduce 192 omitted
+
+# reduce 193 omitted
+
+# reduce 194 omitted
+
+# reduce 195 omitted
+
+# reduce 196 omitted
+
+# reduce 197 omitted
+
+# reduce 198 omitted
+
+# reduce 199 omitted
+
+# reduce 200 omitted
+
+# reduce 201 omitted
+
+# reduce 202 omitted
+
+# reduce 203 omitted
+
+# reduce 204 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 630)
+  def _reduce_205(val, _values, result)
     			Generator.warning( "W6003 need 'void' for no parameter"  )
 		
@@ -2200,8 +2385,8 @@
 .,.,
 
-# reduce 167 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 576)
-  def _reduce_168(val, _values, result)
+# reduce 206 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 635)
+  def _reduce_207(val, _values, result)
     			Generator.warning( "W6004 need 'void' for no parameter"  )
 		
@@ -2210,8 +2395,8 @@
 .,.,
 
-# reduce 169 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 583)
-  def _reduce_170(val, _values, result)
+# reduce 208 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 642)
+  def _reduce_209(val, _values, result)
      result = val[0] 
     result
@@ -2219,6 +2404,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 585)
-  def _reduce_171(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 644)
+  def _reduce_210(val, _values, result)
      result = val[1] 
     result
@@ -2226,6 +2411,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 587)
-  def _reduce_172(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 646)
+  def _reduce_211(val, _values, result)
      result = val[1] 
     result
@@ -2233,6 +2418,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 589)
-  def _reduce_173(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 648)
+  def _reduce_212(val, _values, result)
      result = C_EXP.new( val[2] ) 
     result
@@ -2240,6 +2425,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 594)
-  def _reduce_174(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 653)
+  def _reduce_213(val, _values, result)
     			result = [ val[0] ]
 		
@@ -2248,6 +2433,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 598)
-  def _reduce_175(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 657)
+  def _reduce_214(val, _values, result)
     			val[0] << val[2]
 			result = val[0]
@@ -2257,28 +2442,28 @@
 .,.,
 
-# reduce 176 omitted
-
-# reduce 177 omitted
-
-# reduce 178 omitted
-
-# reduce 179 omitted
-
-# reduce 180 omitted
-
-# reduce 181 omitted
-
-# reduce 182 omitted
-
-# reduce 183 omitted
-
-# reduce 184 omitted
-
-# reduce 185 omitted
-
-# reduce 186 omitted
-
-module_eval(<<'.,.,', 'C_parser.y.rb', 626)
-  def _reduce_187(val, _values, result)
+# reduce 215 omitted
+
+# reduce 216 omitted
+
+# reduce 217 omitted
+
+# reduce 218 omitted
+
+# reduce 219 omitted
+
+# reduce 220 omitted
+
+# reduce 221 omitted
+
+# reduce 222 omitted
+
+# reduce 223 omitted
+
+# reduce 224 omitted
+
+# reduce 225 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 685)
+  def _reduce_226(val, _values, result)
     			val[2].each{ |i|
 			   i.set_kind( :TYPEDEF )
@@ -2291,6 +2476,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 635)
-  def _reduce_188(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 694)
+  def _reduce_227(val, _values, result)
      result = [ val[0] ] 
     result
@@ -2298,6 +2483,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 637)
-  def _reduce_189(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 696)
+  def _reduce_228(val, _values, result)
      result << val[2] 
     result
@@ -2305,82 +2490,4 @@
 .,.,
 
-# reduce 190 omitted
-
-# reduce 191 omitted
-
-# reduce 192 omitted
-
-# reduce 193 omitted
-
-# reduce 194 omitted
-
-# reduce 195 omitted
-
-# reduce 196 omitted
-
-# reduce 197 omitted
-
-# reduce 198 omitted
-
-# reduce 199 omitted
-
-# reduce 200 omitted
-
-# reduce 201 omitted
-
-# reduce 202 omitted
-
-# reduce 203 omitted
-
-# reduce 204 omitted
-
-# reduce 205 omitted
-
-# reduce 206 omitted
-
-# reduce 207 omitted
-
-# reduce 208 omitted
-
-# reduce 209 omitted
-
-# reduce 210 omitted
-
-# reduce 211 omitted
-
-# reduce 212 omitted
-
-# reduce 213 omitted
-
-# reduce 214 omitted
-
-# reduce 215 omitted
-
-# reduce 216 omitted
-
-# reduce 217 omitted
-
-# reduce 218 omitted
-
-# reduce 219 omitted
-
-# reduce 220 omitted
-
-# reduce 221 omitted
-
-# reduce 222 omitted
-
-# reduce 223 omitted
-
-# reduce 224 omitted
-
-# reduce 225 omitted
-
-# reduce 226 omitted
-
-# reduce 227 omitted
-
-# reduce 228 omitted
-
 # reduce 229 omitted
 
@@ -2405,6 +2512,56 @@
 # reduce 239 omitted
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 718)
-  def _reduce_240(val, _values, result)
+# reduce 240 omitted
+
+# reduce 241 omitted
+
+# reduce 242 omitted
+
+# reduce 243 omitted
+
+# reduce 244 omitted
+
+# reduce 245 omitted
+
+# reduce 246 omitted
+
+# reduce 247 omitted
+
+# reduce 248 omitted
+
+# reduce 249 omitted
+
+# reduce 250 omitted
+
+# reduce 251 omitted
+
+# reduce 252 omitted
+
+# reduce 253 omitted
+
+# reduce 254 omitted
+
+# reduce 255 omitted
+
+# reduce 256 omitted
+
+# reduce 257 omitted
+
+# reduce 258 omitted
+
+# reduce 259 omitted
+
+# reduce 260 omitted
+
+# reduce 261 omitted
+
+# reduce 262 omitted
+
+# reduce 263 omitted
+
+# reduce 264 omitted
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 761)
+  def _reduce_265(val, _values, result)
      result = NamespacePath.new( val[0].val, false ) 
     result
@@ -2412,6 +2569,6 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 719)
-  def _reduce_241(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 762)
+  def _reduce_266(val, _values, result)
      result = NamespacePath.new( val[1].val, true ) 
     result
@@ -2419,7 +2576,24 @@
 .,.,
 
-module_eval(<<'.,.,', 'C_parser.y.rb', 721)
-  def _reduce_242(val, _values, result)
+module_eval(<<'.,.,', 'C_parser.y.rb', 764)
+  def _reduce_267(val, _values, result)
      result = val[0].append!( val[2].val ) 
+    result
+  end
+.,.,
+
+module_eval(<<'.,.,', 'C_parser.y.rb', 768)
+  def _reduce_268(val, _values, result)
+    		while true
+			# ';' が表れるまで、トークンを読み飛ばす。
+			# gcc の構文拡張に対応すべきだが、単純な実装として、';' まで読み飛ばす。
+			# トークン単位で読み飛ばしているので、文字列やコメント内の ';' は対象にならない。
+			token = next_token
+			if token[1].val == ";"
+				break
+			end
+			# p "skip: #{token[1].val}" 
+		end
+		
     result
   end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/C_parser.y.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/C_parser.y.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/C_parser.y.rb	(revision 374)
@@ -4,7 +4,7 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2018 by TOPPERS Project
 #--
-#   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
+#   上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
 #   ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
 #   変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
@@ -48,7 +48,12 @@
 # argument_expression_list(関数引数), assignment_expression(代入)がない
 # 式の result は、すべて配列で第一要素が識別シンボル、第二要素以下が引数
+#
+# 2019/3/28 長島 下記のC99の構文に近づくよう変更
+#（読めないヘッダーファイルがあったため）
+# http://www.quut.com/c/ANSI-C-grammar-y-1999.html
+# 元々のコメントと合わなくなっています
 
 primary_expression
-        : namespace_identifier
+		: namespace_identifier
 		{ result = [ :IDENTIFIER, val[0] ] }     #1ok
 #        : IDENTIFIER	# mikan namespace への対応
@@ -58,53 +63,55 @@
 #        | FALSE
 #		{ result = [ :BOOL_CONSTANT, false ] }
-        | INTEGER_CONSTANT
+		| INTEGER_CONSTANT
 		{ result = [ :INTEGER_CONSTANT, val[0] ] }
-        | FLOATING_CONSTANT
+		| FLOATING_CONSTANT
 		{ result = [ :FLOATING_CONSTANT, val[0] ] }
-        | OCTAL_CONSTANT
+		| OCTAL_CONSTANT
 		{ result = [ :OCTAL_CONSTANT, val[0] ] }
-        | HEX_CONSTANT
+		| HEX_CONSTANT
 		{ result = [ :HEX_CONSTANT, val[0] ] }
-        | CHARACTER_LITERAL
+		| CHARACTER_LITERAL
 		{ result = [ :CHARACTER_LITERAL, val[0] ] }
-        | string_literal_list
+		| string_literal_list
 		{ result = [ :STRING_LITERAL_LIST, val[0] ] }
-        | '(' expression ')'
+		| '(' expression ')'
 		{ result = [ :PARENTHESES, val[1].get_elements ] }
 
 string_literal_list
-        : STRING_LITERAL
+		: STRING_LITERAL
 		{ result = [val[0]] }
-        | string_literal_list STRING_LITERAL
+		| string_literal_list STRING_LITERAL
 		{ result << val[1] }
 
 # 関数呼び出しと後置インクリメント、デクリメント演算子がない
 postfix_expression
-        : primary_expression
-        | primary_expression '(' argument_list ')'
-        | primary_expression type_qualifier '(' argument_list ')'    # intended __asm volatile ( "   MNEMONIC  OPERAND" );
-        | postfix_expression '[' expression ']'
+		: primary_expression
+		| postfix_expression '[' expression ']'
 		{ result = [ :OP_SUBSC, val[0], val[2] ] }
-        | postfix_expression '.' IDENTIFIER
+		| postfix_expression '(' ')'
+		| postfix_expression '(' argument_expression_list ')'
+		| postfix_expression type_qualifier '(' argument_expression_list ')'    # intended __asm volatile ( "   MNEMONIC  OPERAND" );
+		| postfix_expression '.' IDENTIFIER
 		{ result = [ :OP_DOT, val[0], val[2] ] }
-        | postfix_expression '->' IDENTIFIER
+		| postfix_expression '->' IDENTIFIER
 		{ result = [ :OP_REF, val[0], val[2] ] }
-        | postfix_expression '++'	{ result = val[0] }   # ++, -- は無視する
-        | postfix_expression '--'	{ result = val[0] }
-
-argument_list
-        :
-        | expression
-        | argument_list ',' expression
+		| postfix_expression '++'	{ result = val[0] }   # ++, -- は無視する
+		| postfix_expression '--'	{ result = val[0] }
+		| '(' type_name ')' '{' initializer_list '}'
+		| '(' type_name ')' '{' initializer_list ',' '}'
+
+argument_expression_list
+		: assignment_expression
+		| argument_expression_list ',' assignment_expression
 
 
 # 前置インクリメント、デクリメント演算子がない
 unary_expression
-        : postfix_expression
-        | unary_operator cast_expression
+		: postfix_expression
+		| unary_operator cast_expression
 		{ result = [ val[0], val[1] ] }
-        | SIZEOF unary_expression
+		| SIZEOF unary_expression
 		{ result = [ :OP_SIZEOF_EXPR, val[1] ] }
-        | SIZEOF '(' type_name ')'
+		| SIZEOF '(' type_name ')'
 		{ result = [ :OP_SIZEOF_TYPE, val[1] ] }
 		| '++' unary_expression			{ result = val[1] }   # ++, -- は無視する
@@ -112,98 +119,117 @@
 
 unary_operator
-        : '&'	{ result = :OP_U_AMP }
-        | '*'	{ result = :OP_U_ASTER }
-        | '+'	{ result = :OP_U_PLUS }
-        | '-'	{ result = :OP_U_MINUS }
-        | '~'	{ result = :OP_U_TILDE }
-        | '!'	{ result = :OP_U_EXCLAM }
+		: '&'	{ result = :OP_U_AMP }
+		| '*'	{ result = :OP_U_ASTER }
+		| '+'	{ result = :OP_U_PLUS }
+		| '-'	{ result = :OP_U_MINUS }
+		| '~'	{ result = :OP_U_TILDE }
+		| '!'	{ result = :OP_U_EXCLAM }
 
 cast_expression
-        : unary_expression
-        | '(' type_name ')' cast_expression
+		: unary_expression
+		| '(' type_name ')' cast_expression
 		{  result = [ :CAST, val[1], val[3] ] }
 
 multiplicative_expression
-        : cast_expression
-        | multiplicative_expression '*' cast_expression
+		: cast_expression
+		| multiplicative_expression '*' cast_expression
 		{ result = [ :OP_MULT, val[0], val[2] ]  }
-        | multiplicative_expression '/' cast_expression
+		| multiplicative_expression '/' cast_expression
 		{ result = [ :OP_DIV, val[0], val[2] ]  }
-        | multiplicative_expression '%' cast_expression
+		| multiplicative_expression '%' cast_expression
 		{ result = [ :OP_REMAIN, val[0], val[2] ]  }
 
 additive_expression
-        : multiplicative_expression
-        | additive_expression '+' multiplicative_expression
+		: multiplicative_expression
+		| additive_expression '+' multiplicative_expression
 		{ result = [ :OP_ADD, val[0], val[2] ]  }
-        | additive_expression '-' multiplicative_expression
+		| additive_expression '-' multiplicative_expression
 		{ result = [ :OP_SUB, val[0], val[2] ]  }
 
 shift_expression
-        : additive_expression
-        | shift_expression '<<' additive_expression
+		: additive_expression
+		| shift_expression '<<' additive_expression
 		{ result = [ :OP_LSFT, val[0], val[2] ]  }
-        | shift_expression '>>' additive_expression
+		| shift_expression '>>' additive_expression
 		{ result = [ :OP_RSFT, val[0], val[2] ]  }
 
 relational_expression
-        : shift_expression
-        | relational_expression '<' shift_expression
+		: shift_expression
+		| relational_expression '<' shift_expression
 		{ result = [ :OP_LT, val[0], val[2] ]  }
-        | relational_expression '>' shift_expression
+		| relational_expression '>' shift_expression
 		{ result = [ :OP_GT, val[0], val[2] ]  }
-        | relational_expression '<=' shift_expression
+		| relational_expression '<=' shift_expression
 		{ result = [ :OP_LE, val[0], val[2] ]  }
-        | relational_expression '>=' shift_expression
+		| relational_expression '>=' shift_expression
 		{ result = [ :OP_GE, val[0], val[2] ]  }
 
 equality_expression
-        : relational_expression
-        | equality_expression '==' relational_expression
+		: relational_expression
+		| equality_expression '==' relational_expression
 		{ result = [ :OP_EQ, val[0], val[2] ]  }
-        | equality_expression '!=' relational_expression
+		| equality_expression '!=' relational_expression
 		{ result = [ :OP_NE, val[0], val[2] ]  }
 
 and_expression
-        : equality_expression
-        | and_expression '&' equality_expression
+		: equality_expression
+		| and_expression '&' equality_expression
 		{ result = [ :OP_AND, val[0], val[2] ]  }
 
 exclusive_or_expression
-        : and_expression
-        | exclusive_or_expression '^' and_expression
+		: and_expression
+		| exclusive_or_expression '^' and_expression
 		{ result = [ :OP_EOR, val[0], val[2] ]  }
 
 inclusive_or_expression
-        : exclusive_or_expression
-        | inclusive_or_expression '|' exclusive_or_expression
+		: exclusive_or_expression
+		| inclusive_or_expression '|' exclusive_or_expression
 		{ result = [ :OP_OR, val[0], val[2] ]  }
 
 logical_and_expression
-        : inclusive_or_expression
-        | logical_and_expression '&&' inclusive_or_expression
+		: inclusive_or_expression
+		| logical_and_expression '&&' inclusive_or_expression
 		{ result = [ :OP_LAND, val[0], val[2] ]  }
 
 logical_or_expression
-        : logical_and_expression
-        | logical_or_expression '||' logical_and_expression
+		: logical_and_expression
+		| logical_or_expression '||' logical_and_expression
 		{ result = [ :OP_LOR, val[0], val[2] ]  }
 
 conditional_expression
-        : logical_or_expression
-        | logical_or_expression '?' expression ':' conditional_expression
+		: logical_or_expression
+		| logical_or_expression '?' expression ':' conditional_expression
 		{ result = [ :OP_CEX, val[0], val[2].get_elements, val[4] ]  }
 
-
-# コンマ演算子が使えない
+assignment_expression
+		: conditional_expression
+		| unary_expression assignment_operator assignment_expression
+
+assignment_operator
+		: '='
+		| '+='
+		| '-='
+		| '*='
+		| '/='
+		| '%='
+		| '<<='
+		| '>>='
+		| '&='
+		| '|='
+		| '^='
+
 expression
-        : conditional_expression
+		: assignment_expression
 		{
 			result = Expression.new( val[0] )
 			# result.print
 		}
+		| expression ',' assignment_expression
+		{
+			result = Expression.new( val[2] )    # ',' の後ろを採用
+		}
 
 constant_expression
-        : conditional_expression
+		: conditional_expression
 		{
 			result = Expression.new( val[0] )
@@ -218,6 +244,4 @@
 		}
 
-
-
 # Types
 ##########################  宣言  ##########################
@@ -227,62 +251,70 @@
 # K&Rとの違い: storage classが指定できない、型が省略できない
 declaration
-        : declaration_specifiers init_declarator_list ';'
-#        : type_specifier_qualifier_list init_declarator_list ';'
+		: declaration_specifiers init_declarator_list ';'
+#        : specifier_qualifier_list init_declarator_list ';'
 
 # declaration_specifiersは関数のパラメータで使われるが、
-# type_specifier_qualifier_listで十分かもしれない
+# specifier_qualifier_listで十分かもしれない
 
 declaration_specifiers
-        : storage_class
+		: storage_class_specifier
 		{
 			result = CIntType.new( -3 )    # storage class は無視
 		}
-        | type_specifier
-        | type_qualifier
+		| storage_class_specifier declaration_specifiers
+		{
+			result = val[1]                # storage class は無視
+		}
+		| type_specifier
+		| type_specifier declaration_specifiers
+		{
+			result = val[1].merge val[0]
+		}
+		| type_qualifier
 		{
 			result = CIntType.new( -3 )
 			result.set_qualifier val[0]
 		}
-        | storage_class declaration_specifiers
-		{
-			result = val[1]                # storage class は無視
-		}
-        | type_specifier declaration_specifiers
-		{
-			result = val[1].merge val[0]
-		}
-        | type_qualifier declaration_specifiers
+		| type_qualifier declaration_specifiers
 		{
 			val[1].set_qualifier val[0]
-                        result = val[1]
-		}
-
+						result = val[1]
+		}
+		| function_specifier
+		| function_specifier declaration_specifiers
 
 init_declarator_list
-        : init_declarator
+		: init_declarator
 		{ result = [val[0]] }
-        | init_declarator_list ',' init_declarator
+		| init_declarator_list ',' init_declarator
 		{ result << val[2] }
 
 init_declarator
-        : declarator
-        | declarator '=' initializer
+		: declarator
+		| declarator '=' initializer
 		{ val[0].set_initializer( val[2] ) }
 
+storage_class_specifier
+		: EXTERN
+		| STATIC
+		| AUTO
+		| REGISTER
+
 type_specifier
-        : VOID	{ set_no_type_name true; result = CVoidType.new }
-        | FLOAT	{ set_no_type_name true; result = CFloatType.new(-32) }
-        | DOUBLE	{ set_no_type_name true; result = CFloatType.new(-64) }
-        | BOOL	{ set_no_type_name true; result = CBoolType.new }
-        | struct_specifier	{ set_no_type_name true; result = val[0] } # set_no_type_name true は struct_tag でも呼ばれる
-        | union_specifier	{ set_no_type_name true; result = CVoidType.new }  # void が宣言されたとする
-        | enum_specifier	{ set_no_type_name true; result = CVoidType.new }  # void が宣言されたとする
-        | TYPE_NAME	{ set_no_type_name true; result = CDefinedType.new( val[0].val ) }
-
-        | CHAR	{ set_no_type_name true; result = CIntType.new(-11 ) }
-        | SHORT	{ set_no_type_name true; result = CIntType.new( -2 ) }
-        | INT		{ set_no_type_name true; result = CIntType.new( -3 ) }
-        | LONG	{ set_no_type_name true; result = CIntType.new( -4 ) }
-        | SIGNED
+		: VOID
+		{ set_no_type_name true; result = CVoidType.new }
+		| CHAR
+		{ set_no_type_name true; result = CIntType.new(-11 ) }
+		| SHORT
+		{ set_no_type_name true; result = CIntType.new( -2 ) }
+		| INT
+		{ set_no_type_name true; result = CIntType.new( -3 ) }
+		| LONG
+		{ set_no_type_name true; result = CIntType.new( -4 ) }
+		| FLOAT
+		{ set_no_type_name true; result = CFloatType.new(-32) }
+		| DOUBLE
+		{ set_no_type_name true; result = CFloatType.new(-64) }
+		| SIGNED
 		{
 			set_no_type_name true
@@ -290,5 +322,5 @@
 			result.set_sign :SIGNED
 		}
-        | UNSIGNED
+		| UNSIGNED
 		{
 			set_no_type_name true
@@ -296,11 +328,21 @@
 			result.set_sign :UNSIGNED
 		}
+		| BOOL
+		{ set_no_type_name true; result = CBoolType.new }
+		| struct_specifier
+		{ set_no_type_name true; result = val[0] } # set_no_type_name true は struct_tag でも呼ばれる
+		| union_specifier
+		{ set_no_type_name true; result = CVoidType.new }  # void が宣言されたとする
+		| enum_specifier
+		{ set_no_type_name true; result = CVoidType.new }  # void が宣言されたとする
+		| TYPE_NAME
+		{ set_no_type_name true; result = CDefinedType.new( val[0].val ) }
 
 # mikan K&Rのstruct_or_union_specifierに相当するが、unionは使えない, bit field にも対応しない
 struct_specifier		# mikan
 #        : STRUCT struct_tag '{'
-        : struct_term struct_tag '{'
+		: struct_term struct_tag '{'
 		{ StructType.set_define( true )  }
-	   struct_declaration_list '}'
+		struct_declaration_list '}'
 		{
 			StructType.end_of_parse
@@ -308,10 +350,10 @@
 		}
 #        | STRUCT
-        | struct_term
+		| struct_term
 		{
 			result = CStructType.new()
 			StructType.set_define( true )
 		}
-	   '{' struct_declaration_list '}'
+		'{' struct_declaration_list '}'
 		{
 			StructType.end_of_parse
@@ -319,5 +361,5 @@
 		}
 #        | STRUCT struct_tag   # mikan struct_tag は namespace 対応が必要
-        | struct_term struct_tag   # mikan struct_tag は namespace 対応が必要
+		| struct_term struct_tag   # mikan struct_tag は namespace 対応が必要
 		{
 			StructType.set_define( false )
@@ -327,12 +369,12 @@
 
 struct_term
-        : STRUCT { set_no_type_name true }
+		: STRUCT { set_no_type_name true }
 
 struct_declaration_list
-        : struct_declaration
-        | struct_declaration_list struct_declaration
+		: struct_declaration
+		| struct_declaration_list struct_declaration
 
 struct_tag:
-        IDENTIFIER
+		IDENTIFIER
 		{
 			result = CStructType.new( val[0].val )
@@ -342,6 +384,6 @@
 # ポインタ修飾子を追加
 struct_declaration
-        : declaration_specifiers struct_declarator_list ';'
-#        :                                type_specifier_qualifier_list struct_declarator_list ';'
+		: declaration_specifiers struct_declarator_list ';'
+#        :                                specifier_qualifier_list struct_declarator_list ';'
 		{
 			val[1].each { |i|	# i: Decl
@@ -353,6 +395,17 @@
 			result = val[1]
 		}
-        | union_specifier ';'                       # 無名
-        | struct_specifier ';'                       # 無名
+		# ビットフィールドを読み飛ばし
+		| declaration_specifiers struct_declarator_list ':' constant_expression ';'
+		{
+			val[1].each { |i|	# i: Decl
+				i.set_type( val[0] )
+				i.set_kind( :MEMBER )
+				i.check
+				CStructType.new_member( i )
+			}
+			result = val[1]
+		}
+		| union_specifier ';'                       # 無名
+		| struct_specifier ';'                       # 無名
 
 
@@ -360,32 +413,32 @@
 # K&Rのspecifier_qualifier_listと同じ
 # 名前がまぎらわしかったのでtype_を付けた
-type_specifier_qualifier_list
-        : type_specifier
-        | type_specifier type_specifier_qualifier_list
+specifier_qualifier_list
+		: type_specifier specifier_qualifier_list
 		{
 			result = val[1].merge val[0]
 		}
-        | type_qualifier
+		| type_specifier
+		| type_qualifier specifier_qualifier_list
+		{
+			val[1].set_qualifier val[0]
+						result = val[1]
+		}
+		| type_qualifier
 		{
 			result = CIntType.new( -3 )
 			result.set_qualifier val[0]
 		}
-        | type_qualifier type_specifier_qualifier_list
-		{
-			val[1].set_qualifier val[0]
-                        result = val[1]
-		}
 
 struct_declarator_list
-        : struct_declarator
+		: struct_declarator
 		{ result = [ val[0] ] }
-        | struct_declarator_list ',' struct_declarator
+		| struct_declarator_list ',' struct_declarator
 		{ result << val[2] }
 
 # ビットフィールドは使えない
 struct_declarator
-        : declarator
-
-
+		: declarator
+#		| ':' constant_expression
+#		| declarator ':' constant_expression
 
 union_specifier
@@ -393,14 +446,14 @@
 #        | UNION '{' union_declaration_list '}'
 #        | UNION union_tag   # mikan struct_tag は namespace 対応が必要
-        : union_term union_tag '{' union_declaration_list '}'
-        | union_term '{' union_declaration_list '}'
-        | union_term union_tag   # mikan struct_tag は namespace 対応が必要
+		: union_term union_tag '{' union_declaration_list '}'
+		| union_term '{' union_declaration_list '}'
+		| union_term union_tag   # mikan struct_tag は namespace 対応が必要
 
 union_term
-        : UNION { set_no_type_name true }
+		: UNION { set_no_type_name true }
 
 union_declaration_list
-        : union_declaration
-        | union_declaration_list union_declaration
+		: union_declaration
+		| union_declaration_list union_declaration
 
 union_tag:
@@ -408,52 +461,56 @@
 
 union_declaration
-        : declaration_specifiers union_declarator_list ';'
+		: declaration_specifiers union_declarator_list ';'
 		| union_specifier ';'                       # 無名
 		| struct_specifier ';'                      # 無名
 
 union_declarator_list
-        : union_declarator
-        | union_declarator_list ',' union_declarator
-
-# ビットフィールドは使えない
+		: union_declarator
+		| union_declarator_list ',' union_declarator
+
 union_declarator
-        : declarator
-
-
-
-# enumの種類を追加
-enum_specifier		# mikan
-        : enum_type            '{' enumerator_list '}'
-        | enum_type IDENTIFIER '{' enumerator_list '}'
-        | enum_type IDENTIFIER
-
-enum_type
-        : ENUM	{ result = CEnumType.new( -1 ) }
-#        | ENUM8	{ result = CEnumType.new( 8 ) }
-#        | ENUM16	{ result = CEnumType.new( 16 ) }
-#        | ENUM32	{ result = CEnumType.new( 32 ) }
-#        | ENUM64	{ result = CEnumType.new( 64 ) }
-#        | ENUM128	{ result = CEnumType.new( 128 ) }
+		: declarator
+		| ':' constant_expression
+		| declarator ':' constant_expression
+
+enum_specifier
+		: ENUM '{' enumerator_list '}'
+		| ENUM IDENTIFIER '{' enumerator_list '}'
+		| ENUM '{' enumerator_list ',' '}'
+		| ENUM IDENTIFIER '{' enumerator_list ',' '}'
+		| ENUM IDENTIFIER
+		| ENUM TYPE_NAME '{' enumerator_list '}'
+		| ENUM TYPE_NAME '{' enumerator_list ',' '}'
+		| ENUM TYPE_NAME
 
 enumerator_list
-        : enumerator
-        | enumerator_list ',' enumerator
+		: enumerator
+		| enumerator_list ',' enumerator
 
 enumerator
-        : IDENTIFIER
-        | IDENTIFIER '=' constant_expression
+		: IDENTIFIER
+		| IDENTIFIER '=' constant_expression
 
 type_qualifier
-        : CONST	{ result = :CONST }
-        | VOLATILE	{ result = :VOLATILE }
+		: CONST
+		{ result = :CONST }
+		| RESTRICT
+		| VOLATILE
+		{ result = :VOLATILE }
+
+function_specifier
+		: __INLINE__
+		| INLINE
+		| __INLINE
+		| CINLINE
 
 declarator
-        : pointer direct_declarator
+		: pointer direct_declarator
 		{
 			val[1].set_type( val[0] )
 			result = val[1]
 		}
-        | direct_declarator
-        | pointer TYPE_NAME     # 関数ポインタの typedef が二重定義の場合
+		| direct_declarator
+		| pointer TYPE_NAME     # 関数ポインタの typedef が二重定義の場合
 		{
 			result = Decl.new( val[1].val )
@@ -462,19 +519,19 @@
 
 direct_declarator		# mikan
-        : IDENTIFIER
+		: IDENTIFIER
 		{ result = Decl.new( val[0].val ) }
-        | '(' declarator ')'
+		| '(' declarator ')'
 		{ result = val[1] }
-        | direct_declarator '[' constant_expression ']'
+		| direct_declarator '[' constant_expression ']'
 		{
 			val[0].set_type( CArrayType.new( val[2] ) )
 			result = val[0]
 		}
-        | direct_declarator '[' ']'
+		| direct_declarator '[' ']'
 		{
 			val[0].set_type( CArrayType.new )
 			result = val[0]
 		}
-        | direct_declarator '(' parameter_type_list ')'
+		| direct_declarator '(' parameter_type_list ')'
 		{
 		# 	Generator.warning( "W6001 need 'void' for no parameter"  )
@@ -482,7 +539,6 @@
 			result = val[0]
 		}
-
-#        | direct_declarator '(' identifier_list ')'  # これは何のために必要？ 060211
-        | direct_declarator '(' ')'
+		| direct_declarator '(' identifier_list ')'  # これは何のために必要？ 060211
+		| direct_declarator '(' ')'
 		{
 		# 	Generator.warning( "W6002 need 'void' for no parameter"  )
@@ -492,17 +548,17 @@
 
 pointer
-        : '*'
+		: '*'
 		{ result = CPtrType.new }
-        | '*' type_qualifier
+		| '*' type_qualifier_list
 		{
 			result = CPtrType.new
 			result.set_qualifier( val[1] )
 		}
-        | '*' pointer
+		| '*' pointer
 		{
 			val[1].set_type(CPtrType.new)
 			result = val[1]
 		}
-        | '*' type_qualifier pointer
+		| '*' type_qualifier_list pointer
 		{
 			ptrtype = CPtrType.new
@@ -512,14 +568,17 @@
 		}
 
+type_qualifier_list
+		: type_qualifier
+		| type_qualifier_list type_qualifier
 
 parameter_type_list
-        : parameter_list
-        | parameter_list ',' '.' '.' '.'
+		: parameter_list
+		| parameter_list ',' '.' '.' '.'
 		# mikan 可変長パラメータ,  ... の間のスペースが許される（手抜き）
 
 parameter_list
-        : parameter_declaration
+		: parameter_declaration
 #		{ result = ParamList.new( val[0] ) }
-        | parameter_list ',' parameter_declaration
+		| parameter_list ',' parameter_declaration
 #		{
 #			val[0].add_param( val[2] )
@@ -530,5 +589,5 @@
 # パラメータ修飾子を追加
 parameter_declaration
-        : declaration_specifiers declarator
+		: declaration_specifiers declarator
 #		{
 #			decl = ParamDecl.new( val[1], val[0], [] )
@@ -545,55 +604,55 @@
 #			result = nil
 #		}
-        | declaration_specifiers abstract_declarator	# 仮引数なし
-        | declaration_specifiers						# 仮引数なし
-
-
-#identifier_list       # 060211  不用になった
-#        : IDENTIFIER
-#        | identifier_list ',' IDENTIFIER
+		| declaration_specifiers abstract_declarator	# 仮引数なし
+		| declaration_specifiers						# 仮引数なし
+
+
+identifier_list       # 060211  不用になった
+        : IDENTIFIER
+        | identifier_list ',' IDENTIFIER
 
 type_name
-        : type_specifier_qualifier_list
-        | type_specifier_qualifier_list abstract_declarator
+		: specifier_qualifier_list
+		| specifier_qualifier_list abstract_declarator
 
 abstract_declarator		# mikan
-        : pointer
-        | direct_abstract_declarator
-        | pointer direct_abstract_declarator
+		: pointer
+		| direct_abstract_declarator
+		| pointer direct_abstract_declarator
 
 direct_abstract_declarator
-        : '(' abstract_declarator ')'
-        | '[' ']'
-        | '[' constant_expression ']'
-        | direct_abstract_declarator '[' ']'
-        | direct_abstract_declarator '[' constant_expression ']'
-        | '(' ')'
+		: '(' abstract_declarator ')'
+		| '[' ']'
+		| '[' assignment_expression ']'
+		| direct_abstract_declarator '[' ']'
+		| direct_abstract_declarator '[' assignment_expression ']'
+		| '(' ')'
 		{
 			Generator.warning( "W6003 need 'void' for no parameter"  )
 		}
-        | '(' parameter_type_list ')'
-        | direct_abstract_declarator '(' ')'
+		| '(' parameter_type_list ')'
+		| direct_abstract_declarator '(' ')'
 		{
 			Generator.warning( "W6004 need 'void' for no parameter"  )
 		}
-        | direct_abstract_declarator '(' parameter_type_list ')'
+		| direct_abstract_declarator '(' parameter_type_list ')'
 
 # assignment_expressionをconstant_expressionに変更
 initializer			# mikan
-        : constant_expression
+		: assignment_expression
 		{ result = val[0] }
-        | '{' initializer_list '}'
+		| '{' initializer_list '}'
 		{ result = val[1] }
-        | '{' initializer_list ',' '}'
+		| '{' initializer_list ',' '}'
 		{ result = val[1] }
-	| C_EXP '(' STRING_LITERAL ')'
+		| C_EXP '(' STRING_LITERAL ')'
 		{ result = C_EXP.new( val[2] ) }
 
 initializer_list
-        : initializer
+		: initializer
 		{
 			result = [ val[0] ]
 		}
-        | initializer_list ',' initializer
+		| initializer_list ',' initializer
 		{
 			val[0] << val[2]
@@ -606,22 +665,22 @@
 #トップレベルの構文規則
 C_parser
-        :
-        | C_parser extension_statement
+		:
+		| C_parser extension_statement
 
 extension_statement
-        : statement
-        | EXTENSION statement
-
-statement
-        : typedef
-        | func_def
-        | enum_specifier ';'
-        | struct_specifier ';'
-        | declaration
-        | ';'
-        | error   # エラー回復ポイント
+		: cdl_statement
+		| EXTENSION cdl_statement
+
+cdl_statement
+		: typedef
+		| func_def
+		| enum_specifier ';'
+		| struct_specifier ';'
+		| declaration
+		| ';'
+		| error   # エラー回復ポイント
 
 typedef
-        : TYPEDEF type_specifier_qualifier_list declarator_list ';'
+        : TYPEDEF specifier_qualifier_list declarator_list ';'
 		{
 			val[2].each{ |i|
@@ -633,384 +692,389 @@
 
 declarator_list
-        : declarator
+		: declarator
 		{ result = [ val[0] ] }
-        | declarator_list ',' declarator
+		| declarator_list ',' declarator
 		{ result << val[2] }
 
 func_def
-        : declaration_specifiers declarator compoundstatement
-
-infunc_statement_list
-        :
-        | infunc_statement_list infunc_statement
-
-infunc_statement
-        : declaration
-        | ifstatement
-        | whilestatement
-        | dowhilestatement
-        | forstatement
-        | switchstatement
-        | labelstatement
-        | compoundstatement
-        | gotostatement
-        | expressionstatement
-        | ';'
+		: declaration_specifiers declarator compound_statement
+
+statement
+		: labeled_statement
+		| compound_statement
+		| expression_statement
+		| ifstatement
+		| whilestatement
+		| dowhilestatement
+		| forstatement
+		| switchstatement
+		| jump_statement
+		| asm_statement
+
+labeled_statement
+		: IDENTIFIER ':' statement
+		| CASE constant_expression ':' statement
+		| DEFAULT ':' statement
+
+compound_statement
+		: '{' '}'
+		| '{' block_item_list '}'
+
+block_item_list
+		: block_item
+		| block_item_list block_item
+
+block_item
+		: declaration
+		| statement
+
+expression_statement
+		: ';'
+		| expression ';'
 
 ifstatement
-        : IF '(' expression ')' infunc_statement
-        | IF '(' expression ')' infunc_statement ELSE infunc_statement
+		: IF '(' expression ')' statement
+		| IF '(' expression ')' statement ELSE statement
+
+switchstatement
+		: SWITCH '(' expression ')' compound_statement
 
 whilestatement
-        : WHILE '(' expression ')' infunc_statement
+		: WHILE '(' expression ')' statement
 
 dowhilestatement
-        : DO infunc_statement WHILE '(' expression ')' ';'
+		: DO statement WHILE '(' expression ')' ';'
 
 forstatement
-        : FOR '(' expression ';' expression ';' expression ')' infunc_statement
-
-switchstatement
-        : SWITCH '(' expression ')'  infunc_statment
-
-labelstatement
-        : IDENTIFIER ':' infunc_statement
-        | CASE constant_expression ':' infunc_statement
-        | DEFAULT ':' infunc_statement
-
-compoundstatement
-        : '{' infunc_statement_list '}'
-
-gotostatement
-        : GOTO IDENTIFIER ';'
-        | CONTINUE ';'
-        | BREAK ';'
-        | RETURN expression ';'
-        | RETURN ';'
-
-expressionstatement
-        : expression ';'
-        | unary_expression assignment_operator expression ';'
-
-assignment_operator
-        : '='
-        | '+='
-        | '-='
-        | '*='
-        | '/='
-        | '%='
-        | '<<='
-        | '>>='
-        | '&='
-        | '|='
-        | '^='
-
-storage_class
-        : __INLINE__
-        | INLINE
-        | __INLINE
-        | CINLINE
-        | EXTERN
-        | STATIC
-        | AUTO
-        | REGISTER
+		: FOR '(' expression_statement expression_statement ')' statement
+		| FOR '(' expression_statement expression_statement expression ')' statement
+		| FOR '(' declaration expression_statement ')' statement
+		| FOR '(' declaration expression_statement expression ')' statement
+
+jump_statement
+		: GOTO IDENTIFIER ';'
+		| CONTINUE ';'
+		| BREAK ';'
+		| RETURN ';'
+		| RETURN expression ';'
 
 namespace_identifier
-        : IDENTIFIER		{ result = NamespacePath.new( val[0].val, false ) }
-        | '::' IDENTIFIER	{ result = NamespacePath.new( val[1].val, true ) }
-        | namespace_identifier '::' IDENTIFIER
+		: IDENTIFIER		{ result = NamespacePath.new( val[0].val, false ) }
+		| '::' IDENTIFIER	{ result = NamespacePath.new( val[1].val, true ) }
+		| namespace_identifier '::' IDENTIFIER
 		{ result = val[0].append!( val[2].val ) }
 
+asm_statement
+		: _ASM {
+		while true
+			# ';' が表れるまで、トークンを読み飛ばす。
+			# gcc の構文拡張に対応すべきだが、単純な実装として、';' まで読み飛ばす。
+			# トークン単位で読み飛ばしているので、文字列やコメント内の ';' は対象にならない。
+			token = next_token
+			if token[1].val == ";"
+				break
+			end
+			# p "skip: #{token[1].val}" 
+		end
+		}
+
 end
 
 ---- inner
 
-  RESERVED = {
-    # keyword
-    'typedef' => :TYPEDEF,
-    'struct' => :STRUCT,
-    'union' => :UNION,
-    'sizeof' => :SIZEOF,
-    'throw' => :THROW,
-
-    # specifier
-    # types
-    'void'    => :VOID,
-    'char'    => :CHAR,
-    'short'   => :SHORT,
-
-    'volatile'=> :VOLATILE,
-    'const'   => :CONST,
-    'extern'   => :EXTERN,
-
-    'long'    => :LONG,
-    'float'   => :FLOAT,
-    'double'  => :DOUBLE,
-    'signed'  => :SIGNED,
-    'unsigned'=> :UNSIGNED,
-
-    'int'     => :INT,
-    'enum'    => :ENUM,
-
-    'if'      => :IF,
-    'else'    => :ELSE,
-    'while'   => :WHILE,
-    'do'      => :DO,
-    'for'     => :FOR,
-    'case'    => :CASE,
-    'default' => :DEFAULT,
-    'goto'    => :GOTO,
-    'continue' => :CONTINUE,
-    'break'   => :BREAK,
-    'return'  => :RETURN,
-    '__inline__'  => :__INLINE__,
-    'inline'  => :INLINE,
-    '__inline'  => :__INLINE,
-    'Inline'  => :CINLINE,        # inline starting with Capital letter
-    'static'  => :STATIC,
-    'register' => :REGISTER,
-    'auto'    => :AUTO,
-    '__extension__'    => :EXTENSION,
-
-  }
-
-  @@generator_nest = -1
-  @@generator_stack = []
-  @@current_locale = []
-
-  def finalize
-
-    # mikan Namespace.pop
-    Celltype.pop
-    Cell.pop
-    CompositeCelltype.pop
-    Region.pop
-
-  end
-
-  def set_plugin( plugin )
-    @plugin = plugin
-  end
-
-  def self.get_plugin
-    @@generator_stack[@@generator_nest].get_plugin
-  end
-
-  def get_plugin
-    @plugin
-  end
-
-  def parse(files)
-
-    # mikan Namespace.push
-    Celltype.push
-    Cell.push
-    CompositeCelltype.push
-    Region.push
-
-    @@generator_nest += 1
-    @@generator_stack[@@generator_nest] = self
-    @b_no_type_name = false
-
-   begin
-
-    @q = []
-    comment = false
-
-    # euc のコメントを utf8 として扱うと、コメントの終わりを誤る問題の対策
-    TECS_LANG::set_kcode_binary
-
-    # 800U, 0xffLL など (整数リテラルに共通の修飾子)
-    integer_qualifier = "([Uu][Ll][Ll]|[Uu][Ll]|[Uu]|[Ll][Ll]|[Ll])?"
-
-    files.each {|file|
-      lineno = 1
-     begin
-#2.0       IO.foreach(file) {|line|
-       TECSIO.foreach(file) {|line|
-        col = 1
-        line.rstrip!
-
-        until line.empty?
-
-          if comment
-            case line
-            # コメント終了
-            when /\A\*\//
-              comment = false
-            when /\A./
-              ;
-            end
-          else
-            case line
-            # 空白、プリプロセスディレクティブ
-            when /\A\s+/
-              ;
-            # 識別子
-            when /\A[a-zA-Z_]\w*/
-              word = $&
-              @q << [RESERVED[word] || :IDENTIFIER, Token.new(word.intern, file, lineno, col)]
-            # 16 進数定数
-            when /\A0x[0-9A-Fa-f]+#{integer_qualifier}/
-              @q << [:HEX_CONSTANT, Token.new($&, file, lineno, col)]
-            # 8 進数定数
-            when /\A0[0-7]+#{integer_qualifier}/
-              @q << [:OCTAL_CONSTANT, Token.new($&, file, lineno, col)]
-            # 浮動小数定数
-            when /\A[0-9]+\.([0-9]*)?([Ee][+-]?[0-9]+)?/
-              @q << [:FLOATING_CONSTANT, Token.new($&, file, lineno, col)]
-            # 整数定数
-            when /\A\d+#{integer_qualifier}/
-            # when /\A\d+/
-              @q << [:INTEGER_CONSTANT, Token.new($&.to_i, file, lineno, col)]
-            # 文字
-            when /\A'(?:[^'\\]|\\.)'/
-              @q << [:CHARACTER_LITERAL, Token.new($&, file, lineno, col)]
-            # 文字列
-#              "#include  #include #include \"../systask/logtask.cfg\"       最後の " 忘れ)で無限ループ
-#            when /\A"(?:[^"\\]+|\\.)*"/
-            when /\A"(?:[^"\\]|\\.)*"/   # これはうまく行くようだ
-              @q << [:STRING_LITERAL, Token.new($&, file, lineno, col)]
-            # 行コメント
-            when /\A\/\/.*$/
-              # 読み飛ばすだけ
-            # コメント開始
-            when /\A\/\*/
-              comment = true
-            when /\A>>=/, /\A<<=/, /\A>>/,  /\A<</
-              @q << [$&, Token.new($&, file, lineno, col)]
-            when /\A\+=/, /\A\-=/, /\A\*=/, /\A\/=/, /\A%=/, /\A&=/, /\A\|=/, /\A\^=/
-              @q << [$&, Token.new($&, file, lineno, col)]
-            when /\A::/, /\A==/, /\A!=/, /\A>=/, /\A<=/, /\A\->/, /\A\+\+/, /\A\-\-/
-              @q << [$&, Token.new($&, file, lineno, col)]
-            when /\A./
-              @q << [$&, Token.new($&, file, lineno, col)]
-            else
-              raise
-            end
-          end
-
-          line = $'
-          col += $&.length
-        end
-
-        lineno += 1
-      }
-
-     rescue => evar
-       Generator.error( "B1002 while open or reading \'$1\'" , file )
-       print_exception( evar )
-     end
-    }
-
-    # 終了の印
-    @q << nil
-
-    @yydebug = true
-    do_parse
-
-   ensure
-    @@generator_nest -= 1
-    TECS_LANG::reset_kcode
-   end
-
-  end
-
-
-  def next_token
-    token = @q.shift
-
-    if token then
-      @@current_locale[@@generator_nest] = token[1].locale
-
-      case token[1].val
-      when ";", ":", ",", "(", ")", "{", "}"
-        set_no_type_name false
-      when ".", "->"
-        set_no_type_name true
-      end
-
-      # TYPE_NAME トークンへ置き換え
-      if @b_no_type_name == false
-        if token[0] == :IDENTIFIER && Namespace.is_typename?( token[1].val ) then
-          token[0] = :TYPE_NAME
-          locale = @@current_locale[@@generator_nest]
+	RESERVED = {
+		# keyword
+		'typedef' => :TYPEDEF,
+		'struct' => :STRUCT,
+		'union' => :UNION,
+		'sizeof' => :SIZEOF,
+		'throw' => :THROW,
+
+		# specifier
+		# types
+		'void'    => :VOID,
+		'char'    => :CHAR,
+		'short'   => :SHORT,
+
+		'volatile'=> :VOLATILE,
+		'restrict'=> :RESTRICT,
+		'const'   => :CONST,
+		'extern'   => :EXTERN,
+
+		'long'    => :LONG,
+		'float'   => :FLOAT,
+		'double'  => :DOUBLE,
+		'signed'  => :SIGNED,
+		'unsigned'=> :UNSIGNED,
+
+		'int'     => :INT,
+		'enum'    => :ENUM,
+
+		'if'      => :IF,
+		'else'    => :ELSE,
+		'while'   => :WHILE,
+		'do'      => :DO,
+		'for'     => :FOR,
+		'switch'  => :SWITCH,
+		'case'    => :CASE,
+		'default' => :DEFAULT,
+		'goto'    => :GOTO,
+		'continue' => :CONTINUE,
+		'break'   => :BREAK,
+		'return'  => :RETURN,
+		'__inline__'  => :__INLINE__,
+		'inline'  => :INLINE,
+		'__inline'  => :__INLINE,
+		'Inline'  => :CINLINE,        # inline starting with Capital letter
+		'static'  => :STATIC,
+		'register' => :REGISTER,
+		'auto'    => :AUTO,
+		'__extension__'    => :EXTENSION,
+		'__asm__' => :_ASM,
+		'asm' =>     :_ASM
+
+	}
+
+	@@generator_nest = -1
+	@@generator_stack = []
+	@@current_locale = []
+
+	def finalize
+
+		# mikan Namespace.pop
+		Celltype.pop
+		Cell.pop
+		CompositeCelltype.pop
+		Region.pop
+
+	end
+
+	def set_plugin( plugin )
+		@plugin = plugin
+	end
+
+	def self.get_plugin
+		@@generator_stack[@@generator_nest].get_plugin
+	end
+
+	def get_plugin
+		@plugin
+	end
+
+	def parse(files)
+
+		# mikan Namespace.push
+		Celltype.push
+		Cell.push
+		CompositeCelltype.push
+		Region.push
+
+		@@generator_nest += 1
+		@@generator_stack[@@generator_nest] = self
+		@b_no_type_name = false
+
+	begin
+
+		@q = []
+		comment = false
+#		b_asm   = false
+
+		# euc のコメントを utf8 として扱うと、コメントの終わりを誤る問題の対策
+		TECS_LANG::set_kcode_binary
+
+		# 800U, 0xffLL など (整数リテラルに共通の修飾子)
+		integer_qualifier = "([Uu][Ll][Ll]|[Uu][Ll]|[Uu]|[Ll][Ll]|[Ll])?"
+
+		files.each {|file|
+			lineno = 1
+		begin
+#2.0		IO.foreach(file) {|line|
+			TECSIO.foreach(file) {|line|
+			col = 1
+			line.rstrip!
+
+			until line.empty?
+
+				if comment
+					case line
+					# コメント終了
+					when /\A\*\//
+						comment = false
+					when /\A./
+						;
+					end
+				else
+					case line
+					# 空白、プリプロセスディレクティブ
+					when /\A\s+/
+						;
+					# 識別子
+					when /\A[a-zA-Z_]\w*/
+						word = $&
+						@q << [RESERVED[word] || :IDENTIFIER, Token.new(word.intern, file, lineno, col)]
+					# 16 進数定数
+					when /\A0x[0-9A-Fa-f]+#{integer_qualifier}/
+						@q << [:HEX_CONSTANT, Token.new($&, file, lineno, col)]
+					# 8 進数定数
+					when /\A0[0-7]+#{integer_qualifier}/
+						@q << [:OCTAL_CONSTANT, Token.new($&, file, lineno, col)]
+					# 浮動小数定数
+					when /\A[0-9]+\.([0-9]*)?([Ee][+-]?[0-9]+)?/
+						@q << [:FLOATING_CONSTANT, Token.new($&, file, lineno, col)]
+					# 整数定数
+					when /\A\d+#{integer_qualifier}/
+					# when /\A\d+/
+						@q << [:INTEGER_CONSTANT, Token.new($&.to_i, file, lineno, col)]
+					# 文字
+					when /\A'(?:[^'\\]|\\.)'/
+						@q << [:CHARACTER_LITERAL, Token.new($&, file, lineno, col)]
+					# 文字列
+#					"#include  #include #include \"../systask/logtask.cfg\"       最後の " 忘れ)で無限ループ
+#					when /\A"(?:[^"\\]+|\\.)*"/
+					when /\A"(?:[^"\\]|\\.)*"/   # これはうまく行くようだ
+						@q << [:STRING_LITERAL, Token.new($&, file, lineno, col)]
+					# 行コメント
+					when /\A\/\/.*$/
+						# 読み飛ばすだけ
+					# コメント開始
+					when /\A\/\*/
+						comment = true
+					when /\A>>=/, /\A<<=/, /\A>>/,  /\A<</
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A\+=/, /\A\-=/, /\A\*=/, /\A\/=/, /\A%=/, /\A&=/, /\A\|=/, /\A\^=/
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A::/, /\A==/, /\A!=/, /\A>=/, /\A<=/, /\A\->/, /\A\+\+/, /\A\-\-/
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A\|\|/, /\A\&\&/
+						@q << [$&, Token.new($&, file, lineno, col)]
+					when /\A./
+						@q << [$&, Token.new($&, file, lineno, col)]
+					else
+						raise
+					end
+				end
+
+				line = $'
+				col += $&.length
+			end
+
+			lineno += 1
+		}
+
+		rescue => evar
+			Generator.error( "B1002 while open or reading \'$1\'" , file )
+			print_exception( evar )
+		end
+	}
+
+	# 終了の印
+	@q << nil
+
+	@yydebug = true
+	do_parse
+
+	ensure
+		@@generator_nest -= 1
+		TECS_LANG::reset_kcode
+	end
+
+	end
+
+
+	def next_token
+		token = @q.shift
+
+		if token then
+			@@current_locale[@@generator_nest] = token[1].locale
+
+			case token[1].val
+			when ";", ":", ",", "(", ")", "{", "}"
+			set_no_type_name false
+			when ".", "->"
+			set_no_type_name true
+			end
+
+			# TYPE_NAME トークンへ置き換え
+			if @b_no_type_name == false
+				if token[0] == :IDENTIFIER && Namespace.is_typename?( token[1].val ) then
+					token[0] = :TYPE_NAME
+					locale = @@current_locale[@@generator_nest]
 #print( "#{locale[0]}: line #{locale[1]} : #{token[0]} '#{token[1].val}: type_name'\n" )
-        end
-      end
-
-      if $debug then     # 070107 token 無効時ここを通さないようした (through 対応 -d の時に例外発生) 
-        locale = @@current_locale[@@generator_nest]
-        if token then
-          print( "#{locale[0]}: line #{locale[1]} : #{token[0]} '#{token[1].val}'\n" )
-        else
-          print( "#{locale[0]}: line #{locale[1]} : EOF\n" )
-        end
-      end
-    end
-
-    token
-  end
-
-  def on_error(t, v, vstack)
-    if v == "$" then
-     Generator.error( "B1003 Unexpected EOF"  )
-    else
-     Generator.error( "B1004 syntax error near \'$1\'" , v.val )
-    end
-
-  end
-
-  def self.current_locale
-    @@current_locale[ @@generator_nest ]
-  end
-
-  @@n_error = 0
-  @@n_warning = 0
-  @@n_info = 0
-
-  # このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でエラー発生は不適切）
-  def self.error( msg )
-    @@n_error += 1
-    locale = @@current_locale[ @@generator_nest ]
-
-    if locale then
-      Console.puts "error: #{locale[0]}: line #{locale[1]} #{msg}"
-    else
-      Console.puts "error: #{msg}"
-    end
-  end
-
-  # このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でウォーニング発生は不適切）
-  def self.warning( msg )
-    @@n_warning += 1
-    locale = @@current_locale[ @@generator_nest ]
-    Console.puts "warning: #{locale[0]}: line #{locale[1]} #{msg}"
-  end
-
-  # このメソッドは構文解析、意味解析からのみ呼出し可
-  def self.info( msg )
-    @@n_info += 1
-    locale = @@current_locale[ @@generator_nest ]
-    Console.puts "info: #{locale[0]}: line #{locale[1]} #{msg}"
-  end
-
-  def self.get_n_error
-    @@n_error
-  end
-
-  def self.get_n_warning
-    @@n_warning
-  end
-
-  def self.get_nest
-    @@generator_nest
-  end
-
-  def set_no_type_name b_no_type_name
-    locale = @@current_locale[ @@generator_nest ]
+				end
+			end
+
+			if $debug then     # 070107 token 無効時ここを通さないようした (through 対応 -d の時に例外発生) 
+				locale = @@current_locale[@@generator_nest]
+				if token then
+					print( "#{locale[0]}: line #{locale[1]} : #{token[0]} '#{token[1].val}'\n" )
+				else
+					print( "#{locale[0]}: line #{locale[1]} : EOF\n" )
+				end
+			end
+		end
+
+		token
+	end
+
+	def on_error(t, v, vstack)
+		if v == "$" then
+			Generator.error( "B1003 Unexpected EOF"  )
+		else
+			Generator.error( "B1004 syntax error near \'$1\'" , v.val )
+		end
+
+	end
+
+	def self.current_locale
+		@@current_locale[ @@generator_nest ]
+	end
+
+	@@n_error = 0
+	@@n_warning = 0
+	@@n_info = 0
+
+	# このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でエラー発生は不適切）
+	def self.error( msg )
+		@@n_error += 1
+		locale = @@current_locale[ @@generator_nest ]
+
+		if locale then
+			Console.puts "error: #{locale[0]}: line #{locale[1]} #{msg}"
+		else
+			Console.puts "error: #{msg}"
+		end
+	end
+
+	# このメソッドは構文解析、意味解析からのみ呼出し可（コード生成でウォーニング発生は不適切）
+	def self.warning( msg )
+		@@n_warning += 1
+		locale = @@current_locale[ @@generator_nest ]
+		Console.puts "warning: #{locale[0]}: line #{locale[1]} #{msg}"
+	end
+
+	# このメソッドは構文解析、意味解析からのみ呼出し可
+	def self.info( msg )
+		@@n_info += 1
+		locale = @@current_locale[ @@generator_nest ]
+		Console.puts "info: #{locale[0]}: line #{locale[1]} #{msg}"
+	end
+
+	def self.get_n_error
+		@@n_error
+	end
+
+	def self.get_n_warning
+		@@n_warning
+	end
+
+	def self.get_nest
+		@@generator_nest
+	end
+
+	def set_no_type_name b_no_type_name
+		locale = @@current_locale[ @@generator_nest ]
 #print "b_no_type_name=#{b_no_type_name} #{locale[0]}: line #{locale[1]}\n"
-    @b_no_type_name = b_no_type_name
-  end
+		@b_no_type_name = b_no_type_name
+	end
 
 ---- footer
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/bnf.tab.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/bnf.tab.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/bnf.tab.rb	(revision 374)
@@ -284,5 +284,5 @@
                   string += line
                   # この位置では error メソッドは使えない (token 読出し前)
-                  puts "error: #{file} line #{lineno}: string literal has newline without escape"
+                  puts "#{file}:#{lineno}:#{col}: error: string literal has newline without escape"
                   @@n_error += 1
                 end
@@ -325,8 +325,9 @@
                   b_in_string = true
                   # この位置では error メソッドは使えない (token 読出し前) # mikan cdl_error ではない
-                  puts "error: #{file} line #{lineno}: string literal has newline without escape"
+                  puts "#{file}:#{lineno}:#{col}: error: string literal has newline without escape"
                   @@n_error += 1
                 # 山括弧で囲まれた文字列
-                when /\A<[0-9A-Za-z_\. \/]+>/   # AB: angle bracke
+                # when /\A<[0-9A-Za-z_\. \/]+>/   # AB: angle bracke
+                when /\A<(?:[^>\\]|\\.)*>/   # これはうまく行くようだ
                   @q << [:AB_STRING_LITERAL, Token.new($&, file, lineno, col)]
                 # 行コメント
@@ -458,5 +459,5 @@
       end
       if locale then
-        Console.puts "error: #{locale[0]}: line #{locale[1]} #{msg}"
+        Console.puts "#{locale[0]}:#{locale[1]}:#{locale[2]}: error: #{msg}"
       else
         Console.puts "error: #{msg}"
@@ -491,5 +492,5 @@
       end
       if locale then
-        Console.puts "warning: #{locale[0]}: line #{locale[1]} #{msg}"
+        Console.puts "#{locale[0]}:#{locale[1]}:#{locale[2]}: warning: #{msg}"
       else
         Console.puts "warning: #{msg}"
@@ -524,5 +525,5 @@
       end
       if locale then
-        Console.puts "info: #{locale[0]}: line #{locale[1]} #{msg}"
+        Console.puts "#{locale[0]}:#{locale[1]}:#{locale[2]}: info: #{msg}"
       else
         Console.puts "info: #{msg}"
@@ -589,176 +590,176 @@
 
 clist = [
-'66,575,328,666,538,872,78,330,562,328,78,78,78,163,199,200,201,202,203',
-'204,205,207,846,208,678,700,897,135,647,212,213,214,215,216,217,218',
-'679,249,761,711,565,547,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24',
+'66,575,328,559,538,815,78,330,869,328,78,78,78,409,199,200,201,202,203',
+'204,205,207,846,208,678,135,897,135,647,212,213,214,215,216,217,218',
+'249,679,177,872,870,408,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24',
 '25,26,27,28,29,30,31,32,33,34,35,38,465,189,693,333,334,42,43,44,45',
-'46,47,48,49,896,180,644,256,559,177,815,163,135,189,135,135,135,135',
-'189,66,189,189,70,68,69,135,71,72,328,73,78,74,304,305,324,860,901,189',
-'255,162,325,136,327,189,75,75,75,76,77,77,77,135,88,189,189,189,189',
-'79,87,101,80,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28',
-'29,30,31,32,33,34,35,38,78,426,569,668,899,42,43,44,45,46,47,48,49,189',
-'178,189,136,66,136,136,136,136,256,135,446,89,100,78,78,136,328,70,68',
-'69,667,71,72,135,73,571,74,304,305,324,135,135,135,478,868,325,479,327',
-'867,399,75,136,76,89,77,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24',
-'25,26,27,28,29,30,31,32,33,34,35,38,450,48,49,400,839,42,43,44,45,46',
-'47,48,49,135,135,328,838,66,304,305,306,607,307,308,310,311,406,208',
-'78,136,136,70,68,69,401,71,72,797,73,150,74,78,149,136,654,304,305,324',
-'78,796,136,136,136,325,75,327,76,407,77,5,6,7,10,13,14,15,16,17,18,19',
-'20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,38,835,163,403,661,402',
-'42,43,44,45,46,47,48,49,163,648,826,403,88,697,136,136,432,78,87,681',
-'816,574,89,208,520,720,70,68,69,660,71,72,532,73,196,74,510,636,827',
-'199,200,201,202,203,204,205,207,208,208,75,682,76,135,77,212,213,214',
-'215,216,217,218,304,305,306,889,307,308,310,311,199,200,201,202,203',
-'204,205,207,817,208,635,747,518,135,637,212,213,214,215,216,217,218',
-'529,888,415,199,200,201,202,203,204,205,207,341,208,342,528,343,135',
-'234,212,213,214,215,216,217,218,199,200,201,202,203,204,205,207,414',
-'208,270,878,235,135,719,212,213,214,215,216,217,218,525,277,589,504',
-'691,314,180,136,582,590,721,581,199,200,201,202,203,204,205,207,879',
-'208,720,587,163,135,776,212,213,214,215,216,217,218,503,690,313,136',
-'199,200,201,202,203,204,205,207,264,208,523,698,282,135,770,212,213',
-'214,215,216,217,218,347,582,136,275,581,348,349,898,180,850,199,200',
-'201,202,203,204,205,207,163,208,699,283,91,135,136,212,213,214,215,216',
-'217,218,199,200,201,202,203,204,205,207,851,208,722,833,691,135,162',
-'212,213,214,215,216,217,218,630,163,88,887,136,902,478,886,87,479,347',
-'859,89,163,409,348,349,88,631,699,832,794,903,87,904,234,592,89,629',
-'170,136,199,200,201,202,203,204,205,207,858,208,564,408,90,135,235,212',
-'213,214,215,216,217,218,522,199,200,201,202,203,204,205,207,136,208',
-'521,150,906,135,149,212,213,214,215,216,217,218,199,200,201,202,203',
-'204,205,207,136,208,394,395,396,135,360,212,213,214,215,216,217,218',
-'199,200,201,202,203,204,205,207,361,208,394,395,396,135,362,212,213',
-'214,215,216,217,218,145,146,363,199,200,201,202,203,204,205,207,437',
-'208,287,288,454,135,136,212,213,214,215,216,217,218,234,354,355,356',
-'357,591,436,438,439,440,441,456,457,458,455,136,347,350,351,515,235',
-'348,349,199,200,201,202,203,204,205,207,907,208,352,353,514,135,136',
-'212,213,214,215,216,217,218,199,200,201,202,203,204,205,207,513,208',
-'358,359,512,135,136,212,213,214,215,216,217,218,364,365,511,199,200',
-'201,202,203,204,205,207,208,208,404,336,482,135,136,212,213,214,215',
-'216,217,218,199,200,201,202,203,204,205,207,481,208,517,518,474,135',
-'473,212,213,214,215,216,217,218,472,199,200,201,202,203,204,205,207',
-'470,208,350,351,463,135,136,212,213,214,215,216,217,218,350,351,234',
-'354,355,356,357,607,454,737,738,740,741,437,136,88,352,353,196,739,785',
-'87,235,608,234,89,610,743,742,456,457,458,455,436,438,439,440,441,611',
-'136,354,355,356,357,235,352,353,199,200,201,202,203,204,205,207,336',
-'208,352,353,612,135,136,212,213,214,215,216,217,218,614,199,200,201',
-'202,203,204,205,207,472,208,352,353,615,135,136,212,213,214,215,216',
-'217,218,199,200,201,202,203,204,205,207,616,208,358,359,617,135,618',
-'212,213,214,215,216,217,218,199,200,201,202,203,204,205,207,208,208',
-'594,336,908,135,621,212,213,214,215,216,217,218,620,288,163,199,200',
-'201,202,203,204,205,207,462,208,787,788,459,135,136,212,213,214,215',
-'216,217,218,625,199,200,201,202,203,204,205,207,448,208,789,790,445',
+'46,47,48,49,896,88,644,406,666,761,711,87,135,871,135,135,135,135,189',
+'66,189,189,70,68,69,135,71,72,328,73,78,74,304,305,324,860,901,189,407',
+'136,325,136,327,189,75,75,75,76,77,77,77,135,874,178,189,189,189,79',
+'875,101,80,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28',
+'29,30,31,32,33,34,35,38,78,364,365,256,899,42,43,44,45,46,47,48,49,189',
+'189,189,136,66,136,136,136,136,878,135,135,89,100,78,78,136,328,70,68',
+'69,399,71,72,135,73,877,74,304,305,324,135,446,135,478,868,325,479,327',
+'867,879,75,136,76,89,77,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24',
+'25,26,27,28,29,30,31,32,33,34,35,38,450,48,49,314,838,42,43,44,45,46',
+'47,48,49,135,135,839,135,66,304,305,306,135,307,308,310,311,691,838',
+'78,136,136,70,68,69,313,71,72,275,73,880,74,78,180,136,816,304,305,324',
+'78,881,136,136,136,325,75,327,76,690,77,5,6,7,10,13,14,15,16,17,18,19',
+'20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,38,835,426,403,282,697',
+'42,43,44,45,46,47,48,49,163,817,163,620,288,277,136,136,432,136,180',
+'504,78,150,136,654,149,720,70,68,69,283,71,72,403,73,402,74,520,636',
+'162,199,200,201,202,203,204,205,207,328,208,75,503,76,135,77,212,213',
+'214,215,216,217,218,304,305,306,859,307,308,310,311,199,200,201,202',
+'203,204,205,207,889,208,635,648,883,135,637,212,213,214,215,216,217',
+'218,884,858,681,199,200,201,202,203,204,205,207,341,208,342,888,343',
+'135,234,212,213,214,215,216,217,218,199,200,201,202,203,204,205,207',
+'682,208,885,668,235,135,661,212,213,214,215,216,217,218,88,789,790,691',
+'256,400,87,136,150,890,89,149,199,200,201,202,203,204,205,207,667,208',
+'891,660,163,135,776,212,213,214,215,216,217,218,794,255,401,136,199',
+'200,201,202,203,204,205,207,892,208,719,415,850,135,162,212,213,214',
+'215,216,217,218,887,898,136,902,886,582,721,903,581,833,199,200,201',
+'202,203,204,205,207,720,208,414,851,904,135,136,212,213,214,215,216',
+'217,218,199,200,201,202,203,204,205,207,832,208,722,698,826,135,906',
+'212,213,214,215,216,217,218,163,163,88,478,136,907,479,582,87,908,581',
+'607,89,163,3,163,88,910,827,699,699,81,87,352,353,234,89,797,170,770',
+'136,199,200,201,202,203,204,205,207,796,208,547,587,564,135,235,212',
+'213,214,215,216,217,218,90,199,200,201,202,203,204,205,207,136,208,394',
+'395,396,135,91,212,213,214,215,216,217,218,199,200,201,202,203,204,205',
+'207,136,208,394,395,396,135,92,212,213,214,215,216,217,218,199,200,201',
+'202,203,204,205,207,163,208,350,351,96,135,124,212,213,214,215,216,217',
+'218,594,336,125,199,200,201,202,203,204,205,207,126,208,130,510,132',
+'135,136,212,213,214,215,216,217,218,134,199,200,201,202,203,204,205',
+'207,140,208,352,353,142,135,136,212,213,214,215,216,217,218,199,200',
+'201,202,203,204,205,207,143,208,404,336,144,135,136,212,213,214,215',
+'216,217,218,199,200,201,202,203,204,205,207,147,208,358,359,155,135',
+'136,212,213,214,215,216,217,218,350,351,156,199,200,201,202,203,204',
+'205,207,159,208,350,351,160,135,136,212,213,214,215,216,217,218,164',
+'199,200,201,202,203,204,205,207,165,208,358,359,166,135,136,212,213',
+'214,215,216,217,218,199,200,201,202,203,204,205,207,167,208,630,437',
+'168,135,136,212,213,214,215,216,217,218,352,353,234,747,518,171,631',
+'287,288,436,438,439,440,441,136,347,629,172,347,173,348,349,235,348',
+'349,199,200,201,202,203,204,205,207,174,208,352,353,175,135,136,212',
+'213,214,215,216,217,218,176,199,200,201,202,203,204,205,207,180,208',
+'184,772,185,135,136,212,213,214,215,216,217,218,199,200,201,202,203',
+'204,205,207,454,208,145,146,186,135,136,212,213,214,215,216,217,218',
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-'30,31,32,33,34,35,38,78,638,,,,42,43,44,45,46,47,48,49,,,,,,,,,,,,,',
-',,,,,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30',
-'31,32,33,34,35,38,,658,,,,42,43,44,45,46,47,48,49,104,105,106,107,108',
-'109,110,111,112,113,114,,,,,,,,,,,,,,,,,,,,,,,,,,,,117,118,119,120,121',
-'122,123,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29',
-'30,31,32,33,34,35,38,,,,,,42,43,44,45,46,47,48,49,5,6,7,10,13,14,15',
-'16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,38,,,,,',
-'42,43,44,45,46,47,48,49,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24',
-'25,26,27,28,29,30,31,32,33,34,35,38,,,,,,42,43,44,45,46,47,48,49,5,6',
-'7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33',
-'34,35,38,,,,,,42,43,44,45,46,47,48,49,5,6,7,10,13,14,15,16,17,18,19',
-'20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,38,,,,,,42,43,44,45',
-'46,47,48,49,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28',
 '29,30,31,32,33,34,35,38,,,,,,42,43,44,45,46,47,48,49,5,6,7,10,13,14',
 '15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,38,,',
 ',,,42,43,44,45,46,47,48,49,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23',
-'24,25,26,27,28,29,30,31,32,33,34,35,38,,,,,,42,43,44,45,46,47' ]
-        racc_action_table = arr = ::Array.new(3623, nil)
+'24,25,26,27,28,29,30,31,32,33,34,35,38,,,,,,42,43,44,45,46,47,48,49',
+'5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32',
+'33,34,35,38,,,,,,42,43,44,45,46,47,48,49,5,6,7,10,13,14,15,16,17,18',
+'19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,38,,,,,,42,43,44',
+'45,46,47,48,49,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27',
+'28,29,30,31,32,33,34,35,38,,,,,,42,43,44,45,46,47,48,49,5,6,7,10,13',
+'14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,38',
+',,,,,42,43,44,45,46,47,48,49,5,6,7,10,13,14,15,16,17,18,19,20,21,22',
+'23,24,25,26,27,28,29,30,31,32,33,34,35,38,,,,,,42,43,44,45,46,47,48',
+'49,5,6,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31',
+'32,33,34,35,38,,,,,,42,43,44,45,46,47' ]
+        racc_action_table = arr = ::Array.new(3593, nil)
         idx = 0
         clist.each do |str|
@@ -770,192 +771,192 @@
 
 clist = [
-'2,469,843,576,422,856,192,194,450,192,329,2,613,434,630,630,630,630',
-'630,630,630,630,824,630,596,630,893,630,560,630,630,630,630,630,630',
-'630,597,154,703,642,454,434,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2',
-'2,2,2,2,2,2,2,2,329,422,613,194,194,2,2,2,2,2,2,2,2,893,414,560,157',
-'447,125,777,573,721,460,558,631,303,470,576,291,856,469,2,2,2,839,2',
-'2,563,2,291,2,192,192,192,843,895,824,157,573,192,630,192,596,329,2',
-'613,2,329,2,613,782,85,703,642,597,154,2,85,41,2,291,291,291,291,291',
+'2,469,843,447,422,777,192,194,852,192,329,2,613,269,515,515,515,515',
+'515,515,515,515,824,515,596,325,893,515,560,515,515,515,515,515,515',
+'515,154,597,125,856,853,269,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2',
+'2,2,2,2,2,2,2,2,329,422,613,194,194,2,2,2,2,2,2,2,2,893,85,560,267,576',
+'703,642,85,721,855,631,558,528,511,447,161,777,469,2,2,2,92,2,2,563',
+'2,161,2,192,192,192,843,895,824,267,325,192,515,192,596,329,2,613,2',
+'329,2,613,75,860,125,856,154,597,2,861,41,2,161,161,161,161,161,161',
+'161,161,161,161,161,161,161,161,161,161,161,161,161,161,161,161,161',
+'161,161,161,161,161,187,230,230,258,895,161,161,161,161,161,161,161',
+'161,576,703,642,721,185,631,558,528,511,866,691,303,89,41,315,185,92',
+'315,161,161,161,258,161,161,333,161,863,161,563,563,563,286,308,782',
+'340,851,563,340,563,851,866,161,75,161,340,161,185,185,185,185,185,185',
+'185,185,185,185,185,185,185,185,185,185,185,185,185,185,185,185,185',
+'185,185,185,185,185,315,89,89,190,869,185,185,185,185,185,185,185,185',
+'839,470,812,692,291,187,187,187,512,187,187,187,187,609,812,291,691',
+'303,185,185,185,190,185,185,171,185,872,185,778,171,333,778,315,315',
+'315,294,873,286,308,782,315,185,315,185,609,185,291,291,291,291,291',
 '291,291,291,291,291,291,291,291,291,291,291,291,291,291,291,291,291',
-'291,291,291,291,291,291,187,291,461,577,895,291,291,291,291,291,291',
-'291,291,447,125,777,721,185,558,631,303,470,258,286,308,89,41,315,185',
-'839,315,291,291,291,577,291,291,92,291,462,291,563,563,563,512,75,325',
-'340,851,563,340,563,851,258,291,782,291,340,291,185,185,185,185,185',
-'185,185,185,185,185,185,185,185,185,185,185,185,185,185,185,185,185',
-'185,185,185,185,185,185,315,89,89,262,812,185,185,185,185,185,185,185',
-'185,511,333,463,812,161,187,187,187,756,187,187,187,187,267,413,161',
-'286,308,185,185,185,262,185,185,756,185,148,185,561,148,92,561,315,315',
-'315,294,756,512,75,325,315,185,315,185,267,185,161,161,161,161,161,161',
-'161,161,161,161,161,161,161,161,161,161,161,161,161,161,161,161,161',
-'161,161,161,161,161,808,392,264,568,264,161,161,161,161,161,161,161',
-'161,375,561,784,625,127,625,511,333,294,778,127,599,778,465,127,412',
-'392,808,161,161,161,568,161,161,411,161,472,161,375,553,784,720,720',
-'720,720,720,720,720,720,410,720,161,599,161,720,161,720,720,720,720',
-'720,720,720,294,294,294,880,294,294,294,294,257,257,257,257,257,257',
-'257,257,778,257,553,684,684,257,553,257,257,257,257,257,257,257,409',
-'880,278,474,474,474,474,474,474,474,474,210,474,210,408,210,474,720',
-'474,474,474,474,474,474,474,403,403,403,403,403,403,403,403,278,403',
-'407,866,720,403,653,403,403,403,403,403,403,403,402,172,480,366,609',
-'190,172,720,580,483,653,580,479,479,479,479,479,479,479,479,866,479',
-'653,479,716,479,720,479,479,479,479,479,479,479,366,609,190,257,889',
-'889,889,889,889,889,889,889,401,889,396,626,176,889,716,889,889,889',
-'889,889,889,889,488,477,474,171,477,488,488,894,171,834,504,504,504',
-'504,504,504,504,504,102,504,626,176,9,504,403,504,504,504,504,504,504',
-'504,862,862,862,862,862,862,862,862,834,862,657,801,751,862,102,862',
-'862,862,862,862,862,862,549,115,253,879,479,897,476,879,253,476,221',
-'841,253,452,269,221,221,88,549,657,801,751,898,88,901,504,504,88,549',
-'115,889,859,859,859,859,859,859,859,859,841,859,452,269,8,859,504,859',
-'859,859,859,859,859,859,395,513,513,513,513,513,513,513,513,504,513',
-'394,86,904,513,86,513,513,513,513,513,513,513,848,848,848,848,848,848',
-'848,848,862,848,254,254,254,848,498,848,848,848,848,848,848,848,359',
-'359,359,359,359,359,359,359,499,359,520,520,520,359,500,359,359,359',
-'359,359,359,359,82,82,501,358,358,358,358,358,358,358,358,547,358,181',
-'181,564,358,859,358,358,358,358,358,358,358,848,496,496,496,496,502',
-'547,547,547,547,547,564,564,564,564,513,487,222,222,384,848,487,487',
-'806,806,806,806,806,806,806,806,905,806,223,223,383,806,848,806,806',
-'806,806,806,806,806,357,357,357,357,357,357,357,357,382,357,225,225',
-'381,357,359,357,357,357,357,357,357,357,230,230,380,797,797,797,797',
-'797,797,797,797,368,797,265,265,343,797,358,797,797,797,797,797,797',
-'797,796,796,796,796,796,796,796,796,342,796,389,389,338,796,337,796',
-'796,796,796,796,796,796,335,356,356,356,356,356,356,356,356,334,356',
-'489,489,327,356,806,356,356,356,356,356,356,356,490,490,797,495,495',
-'495,495,525,318,739,739,739,739,297,357,696,491,491,739,739,739,696',
-'797,526,796,696,528,739,739,318,318,318,318,297,297,297,297,297,529',
-'797,224,224,224,224,796,492,492,355,355,355,355,355,355,355,355,530',
-'355,493,493,531,355,796,355,355,355,355,355,355,355,533,354,354,354',
-'354,354,354,354,354,739,354,494,494,534,354,356,354,354,354,354,354',
-'354,354,353,353,353,353,353,353,353,353,535,353,497,497,536,353,537',
-'353,353,353,353,353,353,353,352,352,352,352,352,352,352,352,538,352',
-'505,505,906,352,543,352,352,352,352,352,352,352,539,539,544,748,748',
-'748,748,748,748,748,748,326,748,742,742,324,748,355,748,748,748,748',
-'748,748,748,548,729,729,729,729,729,729,729,729,309,729,743,743,307',
-'729,354,729,729,729,729,729,729,729,719,719,719,719,719,719,719,719',
-'306,719,285,719,557,719,353,719,719,719,719,719,719,719,430,602,748',
-'246,246,246,430,602,284,559,430,602,283,282,352,246,246,246,246,246',
-'246,281,748,280,565,351,351,351,351,351,351,351,351,276,351,274,570',
-'572,351,748,351,351,351,351,351,351,351,272,147,147,147,147,147,147',
-'147,147,271,147,266,256,578,147,729,147,147,147,147,147,147,147,350',
-'350,350,350,350,350,350,350,242,350,240,236,583,350,719,350,350,350',
-'350,350,350,350,149,149,149,149,149,149,149,149,235,149,586,149,588',
-'149,229,149,149,149,149,149,149,149,546,546,546,147,546,546,546,546',
-'228,349,349,349,349,349,349,349,349,351,349,227,598,226,349,147,349',
-'349,349,349,349,349,349,600,714,714,714,714,714,714,714,714,147,714',
-'206,604,605,714,606,714,714,714,714,714,714,714,348,348,348,348,348',
-'348,348,348,350,348,607,608,198,348,611,348,348,348,348,348,348,348',
-'710,710,710,710,710,710,710,710,149,710,195,616,619,710,189,710,710',
-'710,710,710,710,710,184,183,179,347,347,347,347,347,347,347,347,178',
-'347,632,634,636,347,349,347,347,347,347,347,347,347,827,827,827,827',
-'637,638,373,288,640,827,827,641,373,288,177,714,373,288,827,827,643',
-'644,646,706,706,706,706,706,706,706,706,648,706,651,175,174,706,348',
-'706,706,706,706,706,706,706,345,345,345,345,345,345,345,345,658,345',
-'662,663,664,345,710,345,345,345,345,345,345,345,665,666,827,36,36,36',
-'36,36,36,36,36,36,36,36,36,36,36,347,668,345,345,345,345,345,345,345',
-'345,345,345,345,345,345,345,345,345,345,345,345,345,345,345,345,345',
-'345,345,345,345,173,671,673,169,1,345,345,345,345,345,345,345,345,688',
-'689,706,260,260,260,260,260,260,260,515,515,515,515,515,515,515,515',
-'691,515,692,693,694,515,345,515,515,515,515,515,515,515,166,166,166',
-'166,166,166,166,166,695,166,168,697,699,166,700,166,166,166,166,166',
-'166,166,341,341,341,341,341,341,341,341,701,341,167,165,164,341,707',
-'341,341,341,341,341,341,341,682,682,682,682,682,682,682,682,160,682',
-'159,711,152,682,151,682,682,682,682,682,682,682,718,144,141,139,521',
-'521,521,521,521,521,521,521,725,521,727,138,730,521,515,521,521,521',
-'521,521,521,521,522,522,522,522,522,522,522,522,731,522,137,3,909,522',
-'166,522,522,522,522,522,522,522,523,523,523,523,523,523,523,523,746',
-'523,136,749,133,523,341,523,523,523,523,523,523,523,581,581,581,581',
-'581,581,581,581,755,581,131,581,760,581,682,581,581,581,581,581,581',
-'581,761,763,764,766,908,908,908,908,908,908,908,908,767,908,768,769',
-'770,908,521,908,908,908,908,908,908,908,783,783,783,783,771,146,518',
-'245,772,783,783,146,518,245,522,146,518,245,783,783,773,775,290,290',
-'290,290,290,290,290,290,776,290,129,128,780,290,523,290,290,290,290',
-'290,290,290,207,207,207,207,207,207,207,207,781,207,126,124,123,207',
-'581,207,207,207,207,207,207,207,510,510,510,783,170,170,170,170,170',
-'170,170,793,510,510,510,510,510,510,908,207,207,207,207,207,207,207',
+'291,291,291,291,291,291,808,291,625,176,625,291,291,291,291,291,291',
+'291,291,392,778,573,539,539,172,839,470,294,692,172,366,561,86,512,561',
+'86,808,291,291,291,176,291,291,264,291,264,291,392,553,573,720,720,720',
+'720,720,720,720,720,874,720,291,366,291,720,291,720,720,720,720,720',
+'720,720,294,294,294,841,294,294,294,294,902,902,902,902,902,902,902',
+'902,880,902,553,561,876,902,553,902,902,902,902,902,902,902,877,841',
+'599,889,889,889,889,889,889,889,889,210,889,210,880,210,889,720,889',
+'889,889,889,889,889,889,521,521,521,521,521,521,521,521,599,521,878',
+'577,720,521,568,521,521,521,521,521,521,521,430,743,743,751,157,262',
+'430,720,148,881,430,148,522,522,522,522,522,522,522,522,577,522,882',
+'568,102,522,720,522,522,522,522,522,522,522,751,157,262,902,523,523',
+'523,523,523,523,523,523,883,523,653,278,834,523,102,523,523,523,523',
+'523,523,523,879,894,889,897,879,580,653,898,580,801,234,234,234,234',
+'234,234,234,234,653,234,278,834,901,234,521,234,234,234,234,234,234',
+'234,166,166,166,166,166,166,166,166,801,166,657,626,784,166,904,166',
+'166,166,166,166,166,166,115,716,518,476,522,905,476,477,518,906,477',
+'756,518,434,1,452,127,909,784,657,626,3,127,494,494,234,127,756,115',
+'716,523,479,479,479,479,479,479,479,479,756,479,434,479,452,479,234',
+'479,479,479,479,479,479,479,8,358,358,358,358,358,358,358,358,234,358',
+'520,520,520,358,9,358,358,358,358,358,358,358,363,363,363,363,363,363',
+'363,363,166,363,254,254,254,363,16,363,363,363,363,363,363,363,360,360',
+'360,360,360,360,360,360,375,360,222,222,38,360,68,360,360,360,360,360',
+'360,360,505,505,69,361,361,361,361,361,361,361,361,70,361,72,375,73',
+'361,479,361,361,361,361,361,361,361,74,682,682,682,682,682,682,682,682',
+'76,682,223,223,77,682,358,682,682,682,682,682,682,682,862,862,862,862',
+'862,862,862,862,79,862,265,265,80,862,363,862,862,862,862,862,862,862',
+'362,362,362,362,362,362,362,362,84,362,225,225,94,362,360,362,362,362',
+'362,362,362,362,489,489,95,797,797,797,797,797,797,797,797,100,797,490',
+'490,101,797,361,797,797,797,797,797,797,797,104,811,811,811,811,811',
+'811,811,811,106,811,497,497,108,811,682,811,811,811,811,811,811,811',
+'838,838,838,838,838,838,838,838,110,838,549,297,114,838,862,838,838',
+'838,838,838,838,838,491,491,797,684,684,117,549,181,181,297,297,297',
+'297,297,362,487,549,118,221,119,487,487,797,221,221,796,796,796,796',
+'796,796,796,796,122,796,492,492,123,796,797,796,796,796,796,796,796',
+'796,124,835,835,835,835,835,835,835,835,126,835,128,835,129,835,811',
+'835,835,835,835,835,835,835,514,514,514,514,514,514,514,514,318,514',
+'82,82,131,514,838,514,514,514,514,514,514,514,488,133,796,389,389,488',
+'488,318,318,318,318,823,823,823,823,823,823,823,823,564,823,136,796',
+'137,823,138,823,823,823,823,823,823,823,495,495,495,495,742,742,796',
+'564,564,564,564,224,224,224,224,207,207,207,207,207,207,207,207,547',
+'207,510,510,510,207,835,207,207,207,207,207,207,207,510,510,510,510',
+'510,510,547,547,547,547,547,546,546,546,514,546,546,546,546,207,207',
 '207,207,207,207,207,207,207,207,207,207,207,207,207,207,207,207,207',
-'207,207,207,207,122,119,799,118,117,207,207,207,207,207,207,207,207',
-'114,810,290,110,108,814,815,816,817,821,211,211,211,211,211,211,211',
-'211,822,211,106,104,101,211,207,211,211,211,211,211,211,211,212,212',
-'212,212,212,212,212,212,828,212,833,100,95,212,836,212,212,212,212,212',
-'212,212,902,902,902,902,902,902,902,902,837,902,94,84,840,902,80,902',
-'902,902,902,902,902,902,591,591,591,591,591,591,591,591,79,591,845,846',
-'77,591,850,591,591,591,591,591,591,591,76,852,853,855,575,575,575,575',
-'575,575,575,575,74,575,73,860,861,575,211,575,575,575,575,575,575,575',
-'234,234,234,234,234,234,234,234,72,234,863,70,869,234,212,234,234,234',
-'234,234,234,234,584,584,584,584,584,584,584,584,872,584,873,584,874',
-'584,902,584,584,584,584,584,584,584,514,514,514,514,514,514,514,514',
-'876,514,877,878,69,514,591,514,514,514,514,514,514,514,68,881,882,234',
-'162,162,162,162,162,162,162,162,162,162,162,4,883,38,575,16,431,4,432',
-'234,428,4,365,365,365,365,365,365,365,365,437,365,442,443,426,365,234',
-'365,365,365,365,365,365,365,364,364,364,364,364,364,364,364,425,364',
-'446,419,416,364,584,364,364,364,364,364,364,364,363,363,363,363,363',
-'363,363,363,,363,,,,363,514,363,363,363,363,363,363,363,838,838,838',
-'838,838,838,838,838,,838,,,,838,,838,838,838,838,838,838,838,,,,,835',
-'835,835,835,835,835,835,835,,835,,835,,835,365,835,835,835,835,835,835',
-'835,362,362,362,362,362,362,362,362,,362,,,,362,364,362,362,362,362',
-'362,362,362,361,361,361,361,361,361,361,361,,361,,,,361,363,361,361',
-'361,361,361,361,361,823,823,823,823,823,823,823,823,,823,,,,823,838',
-'823,823,823,823,823,823,823,,,,,360,360,360,360,360,360,360,360,,360',
-',,,360,835,360,360,360,360,360,360,360,811,811,811,811,811,811,811,811',
-',811,,,,811,362,811,811,811,811,811,811,811,669,669,669,669,,424,,,',
-'669,669,424,,,361,424,,,669,669,,,,,,,,,,,,,,,,,823,54,54,54,54,54,54',
-'54,54,54,54,54,,,,478,478,,478,,,,,,,478,360,,,,,,,669,,,,,,54,54,54',
-'54,54,54,54,,,811,478,478,478,478,478,478,478,478,478,478,478,478,478',
-'478,478,478,478,478,478,478,478,478,478,478,478,478,478,478,150,,150',
-',,478,478,478,478,478,478,478,478,,,,,,,,,,,,,,,,,,,,,150,150,150,150',
+'207,207,207,207,207,207,207,207,207,823,496,496,496,496,207,207,207',
+'207,207,207,207,207,748,748,748,748,748,748,748,748,139,748,493,493',
+'141,748,144,748,748,748,748,748,748,748,151,152,207,859,859,859,859',
+'859,859,859,859,159,859,160,164,165,859,167,859,859,859,859,859,859',
+'859,575,575,575,575,575,575,575,575,168,575,169,173,174,575,175,575',
+'575,575,575,575,575,575,748,177,178,179,183,184,257,257,257,257,257',
+'257,257,257,189,257,195,198,206,257,748,257,257,257,257,257,257,257',
+'226,581,581,581,581,581,581,581,581,748,581,227,581,228,581,229,581',
+'581,581,581,581,581,581,729,729,729,729,729,729,729,729,235,729,236',
+'859,240,729,242,729,729,729,729,729,729,729,256,584,584,584,584,584',
+'584,584,584,266,584,575,584,271,584,272,584,584,584,584,584,584,584',
+'274,276,147,147,147,147,147,147,147,147,280,147,281,282,283,147,257',
+'147,147,147,147,147,147,147,284,591,591,591,591,591,591,591,591,285',
+'591,306,307,309,591,581,591,591,591,591,591,591,591,719,719,719,719',
+'719,719,719,719,324,719,326,719,327,719,729,719,719,719,719,719,719',
+'719,334,288,147,602,246,246,246,288,335,602,337,288,338,602,342,584',
+'246,246,246,246,246,246,147,343,368,714,714,714,714,714,714,714,714',
+'380,714,381,382,383,714,147,714,714,714,714,714,714,714,384,710,710',
+'710,710,710,710,710,710,394,710,395,396,401,710,591,710,710,710,710',
+'710,710,710,706,706,706,706,706,706,706,706,402,706,407,408,409,706',
+'719,706,706,706,706,706,706,706,504,504,504,504,504,504,504,504,410',
+'504,411,412,413,504,414,504,504,504,504,504,504,504,416,419,425,365',
+'365,365,365,365,365,365,365,426,365,428,431,432,365,714,365,365,365',
+'365,365,365,365,827,827,827,827,437,442,443,446,450,827,827,783,783',
+'783,783,710,454,460,827,827,783,783,504,504,461,4,696,462,373,783,783',
+'4,696,146,373,4,696,706,373,146,463,465,504,146,472,630,630,630,630',
+'630,630,630,630,480,630,483,630,498,630,504,630,630,630,630,630,630',
+'630,499,500,827,364,364,364,364,364,364,364,364,501,364,783,502,525',
+'364,365,364,364,364,364,364,364,364,908,908,908,908,908,908,908,908',
+'526,908,529,530,531,908,533,908,908,908,908,908,908,908,341,341,341',
+'341,341,341,341,341,534,341,535,536,537,341,538,341,341,341,341,341',
+'341,341,543,739,739,739,739,544,548,88,424,557,739,739,739,88,424,630',
+'559,88,424,739,739,565,570,572,578,583,347,347,347,347,347,347,347,347',
+'586,347,588,598,600,347,364,347,347,347,347,347,347,347,345,345,345',
+'345,345,345,345,345,604,345,605,606,607,345,908,345,345,345,345,345',
+'345,345,739,162,162,162,162,162,162,162,162,162,162,162,608,610,341',
+'611,616,619,632,345,345,345,345,345,345,345,345,345,345,345,345,345',
+'345,345,345,345,345,345,345,345,345,345,345,345,345,345,345,634,636',
+'637,638,640,345,345,345,345,345,345,345,345,641,643,347,260,260,260',
+'260,260,260,260,348,348,348,348,348,348,348,348,644,348,646,648,651',
+'348,345,348,348,348,348,348,348,348,349,349,349,349,349,349,349,349',
+'658,349,662,663,664,349,665,349,349,349,349,349,349,349,350,350,350',
+'350,350,350,350,350,666,350,668,671,673,350,688,350,350,350,350,350',
+'350,350,351,351,351,351,351,351,351,351,689,351,693,694,695,351,697',
+'351,351,351,351,351,351,351,699,700,701,707,352,352,352,352,352,352',
+'352,352,711,352,718,725,727,352,348,352,352,352,352,352,352,352,353',
+'353,353,353,353,353,353,353,730,353,731,746,749,353,349,353,353,353',
+'353,353,353,353,354,354,354,354,354,354,354,354,750,354,755,760,761',
+'354,350,354,354,354,354,354,354,354,355,355,355,355,355,355,355,355',
+'763,355,764,766,767,355,351,355,355,355,355,355,355,355,768,769,770',
+'771,356,356,356,356,356,356,356,356,772,356,773,775,776,356,352,356',
+'356,356,356,356,356,356,357,357,357,357,357,357,357,357,780,357,781',
+'793,799,357,353,357,357,357,357,357,357,357,359,359,359,359,359,359',
+'359,359,810,359,814,815,816,359,354,359,359,359,359,359,359,359,149',
+'149,149,149,149,149,149,149,817,149,821,149,822,149,355,149,149,149',
+'149,149,149,149,828,833,836,837,474,474,474,474,474,474,474,474,840',
+'474,845,846,850,474,356,474,474,474,474,474,474,474,290,290,290,290',
+'290,290,290,290,,290,,,,290,357,290,290,290,290,290,290,290,848,848',
+'848,848,848,848,848,848,,848,,,,848,359,848,848,848,848,848,848,848',
+'806,806,806,806,806,806,806,806,,806,,,,806,149,806,806,806,806,806',
+'806,806,245,,,,,,245,,,253,245,669,669,669,669,253,,,474,253,669,669',
+',,,848,,,,669,669,170,170,170,170,170,170,170,,,290,,,,,848,,,403,403',
+'403,403,403,403,403,403,,403,,,,403,848,403,403,403,403,403,403,403',
+'513,513,513,513,513,513,513,513,,513,669,,,513,806,513,513,513,513,513',
+'513,513,212,212,212,212,212,212,212,212,,212,,,,212,,212,212,212,212',
+'212,212,212,211,211,211,211,211,211,211,211,,211,,,,211,,211,211,211',
+'211,211,211,211,,,,464,464,464,464,464,464,464,464,464,464,464,,,,,403',
+',,,,,,54,54,54,54,54,54,54,54,54,54,54,,,,,513,464,464,464,464,464,464',
+'464,,,,478,478,,478,,,,,,,478,212,54,54,54,54,54,54,54,36,36,36,36,36',
+'36,36,36,36,36,36,36,36,36,211,478,478,478,478,478,478,478,478,478,478',
+'478,478,478,478,478,478,478,478,478,478,478,478,478,478,478,478,478',
+'478,582,,582,,,478,478,478,478,478,478,478,478,,,,,,,,,,,,,,,,,,,,,582',
+'582,582,582,582,582,582,582,582,582,582,582,582,582,582,582,582,582',
+'582,582,582,582,582,582,582,582,582,582,150,,150,,,582,582,582,582,582',
+'582,582,582,,,,,,,,,,,,,,,,,,,,,150,150,150,150,150,150,150,150,150',
 '150,150,150,150,150,150,150,150,150,150,150,150,150,150,150,150,150',
-'150,150,150,150,150,150,150,582,,582,,,150,150,150,150,150,150,150,150',
-',,,,,,,,,,,,,,,,,,,,582,582,582,582,582,582,582,582,582,582,582,582',
-'582,582,582,582,582,582,582,582,582,582,582,582,582,582,582,582,372',
-',,,,582,582,582,582,582,582,582,582,,,,,,,,,,,,,,,,,,,372,372,372,372',
+'150,150,372,,,,,150,150,150,150,150,150,150,150,,,,,,,,,,,,,,,,,,,372',
 '372,372,372,372,372,372,372,372,372,372,372,372,372,372,372,372,372',
-'372,372,372,372,372,372,372,459,,,,,372,372,372,372,372,372,372,372',
-'372,,,,,,,,,,,,,,,,,,459,459,459,459,459,459,459,459,459,459,459,459',
-'459,459,459,459,459,459,459,459,459,459,459,459,459,459,459,459,250',
-',,,,459,459,459,459,459,459,459,459,,,,,,,,,,,,,,,,,,,250,250,250,250',
+'372,372,372,372,372,372,372,372,372,372,293,,,,,372,372,372,372,372',
+'372,372,372,372,,,,,,,,,,,,,,,,,,293,293,293,293,293,293,293,293,293',
+'293,293,293,293,293,293,293,293,293,293,293,293,293,293,293,293,293',
+'293,293,444,293,,,,293,293,293,293,293,293,293,293,,,,,,,,,,,,,,,,,',
+',444,444,444,444,444,444,444,444,444,444,444,444,444,444,444,444,444',
+'444,444,444,444,444,444,444,444,444,444,444,445,,,,,444,444,444,444',
+'444,444,444,444,,,,,,,,,,,,,,,,,,,445,445,445,445,445,445,445,445,445',
+'445,445,445,445,445,445,445,445,445,445,445,445,445,445,445,445,445',
+'445,445,550,,,,,445,445,445,445,445,445,445,445,,,,,,,,,,,,,,,,,,,550',
+'550,550,550,550,550,550,550,550,550,550,550,550,550,550,550,550,550',
+'550,550,550,550,550,550,550,550,550,550,554,550,,,,550,550,550,550,550',
+'550,550,550,,,,,,,,,,,,,,,,,,,554,554,554,554,554,554,554,554,554,554',
+'554,554,554,554,554,554,554,554,554,554,554,554,554,554,554,554,554',
+'554,566,554,,,,554,554,554,554,554,554,554,554,,,,,,,,,,,,,,,,,,,566',
+'566,566,566,566,566,566,566,566,566,566,566,566,566,566,566,566,566',
+'566,566,566,566,566,566,566,566,566,566,71,566,,,,566,566,566,566,566',
+'566,566,566,,,,,,,,,,,,,,,,,,,71,71,71,71,71,71,71,71,71,71,71,71,71',
+'71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,386,,,,,71,71,71,71,71',
+'71,71,71,,,,,,,,,,,,,,,,,,,386,386,386,386,386,386,386,386,386,386,386',
+'386,386,386,386,386,386,386,386,386,386,386,386,386,386,386,386,386',
+'459,386,,,,386,386,386,386,386,386,386,386,,,,,,,,,,,,,,,,,,,459,459',
+'459,459,459,459,459,459,459,459,459,459,459,459,459,459,459,459,459',
+'459,459,459,459,459,459,459,459,459,251,,,,,459,459,459,459,459,459',
+'459,459,,,,,,,,,,,,,,,,,,,251,251,251,251,251,251,251,251,251,251,251',
+'251,251,251,251,251,251,251,251,251,251,251,251,251,251,251,251,251',
+'250,251,,,,251,251,251,251,251,251,251,251,,,,,,,,,,,,,,,,,,,250,250',
 '250,250,250,250,250,250,250,250,250,250,250,250,250,250,250,250,250',
-'250,250,250,250,250,250,250,293,,,,,250,250,250,250,250,250,250,250',
-',,,,,,,,,,,,,,,,,,293,293,293,293,293,293,293,293,293,293,293,293,293',
-'293,293,293,293,293,293,293,293,293,293,293,293,293,293,293,445,293',
-',,,293,293,293,293,293,293,293,293,,,,,,,,,,,,,,,,,,,445,445,445,445',
-'445,445,445,445,445,445,445,445,445,445,445,445,445,445,445,445,445',
-'445,445,445,445,445,445,445,251,,,,,445,445,445,445,445,445,445,445',
-',,,,,,,,,,,,,,,,,,251,251,251,251,251,251,251,251,251,251,251,251,251',
-'251,251,251,251,251,251,251,251,251,251,251,251,251,251,251,444,251',
-',,,251,251,251,251,251,251,251,251,,,,,,,,,,,,,,,,,,,444,444,444,444',
-'444,444,444,444,444,444,444,444,444,444,444,444,444,444,444,444,444',
-'444,444,444,444,444,444,444,156,,,,,444,444,444,444,444,444,444,444',
-',,,,,,,,,,,,,,,,,,156,156,156,156,156,156,156,156,156,156,156,156,156',
-'156,156,156,156,156,156,156,156,156,156,156,156,156,156,156,386,,,,',
-'156,156,156,156,156,156,156,156,,,,,,,,,,,,,,,,,,,386,386,386,386,386',
-'386,386,386,386,386,386,386,386,386,386,386,386,386,386,386,386,386',
-'386,386,386,386,386,386,71,386,,,,386,386,386,386,386,386,386,386,,',
-',,,,,,,,,,,,,,,,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71',
-'71,71,71,71,71,71,71,71,71,71,550,,,,,71,71,71,71,71,71,71,71,,,,,,',
-',,,,,,,,,,,,550,550,550,550,550,550,550,550,550,550,550,550,550,550',
-'550,550,550,550,550,550,550,550,550,550,550,550,550,550,554,550,,,,550',
-'550,550,550,550,550,550,550,,,,,,,,,,,,,,,,,,,554,554,554,554,554,554',
-'554,554,554,554,554,554,554,554,554,554,554,554,554,554,554,554,554',
-'554,554,554,554,554,566,554,,,,554,554,554,554,554,554,554,554,,,,,',
-',,,,,,,,,,,,,566,566,566,566,566,566,566,566,566,566,566,566,566,566',
-'566,566,566,566,566,566,566,566,566,566,566,566,566,566,,566,,,,566',
-'566,566,566,566,566,566,566,464,464,464,464,464,464,464,464,464,464',
-'464,,,,,,,,,,,,,,,,,,,,,,,,,,,,464,464,464,464,464,464,464,244,244,244',
+'250,250,250,250,250,250,250,250,250,156,,,,,250,250,250,250,250,250',
+'250,250,,,,,,,,,,,,,,,,,,,156,156,156,156,156,156,156,156,156,156,156',
+'156,156,156,156,156,156,156,156,156,156,156,156,156,156,156,156,156',
+',,,,,156,156,156,156,156,156,156,156,622,622,622,622,622,622,622,622',
+'622,622,622,622,622,622,622,622,622,622,622,622,622,622,622,622,622',
+'622,622,622,,,,,,622,622,622,622,622,622,622,622,40,40,40,40,40,40,40',
+'40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,,,,,',
+'40,40,40,40,40,40,40,40,705,705,705,705,705,705,705,705,705,705,705',
+'705,705,705,705,705,705,705,705,705,705,705,705,705,705,705,705,705',
+',,,,,705,705,705,705,705,705,705,705,244,244,244,244,244,244,244,244',
 '244,244,244,244,244,244,244,244,244,244,244,244,244,244,244,244,244',
-'244,244,244,244,244,244,244,244,,,,,,244,244,244,244,244,244,244,244',
-'40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40',
-'40,40,40,40,40,,,,,,40,40,40,40,40,40,40,40,289,289,289,289,289,289',
-'289,289,289,289,289,289,289,289,289,289,289,289,289,289,289,289,289',
-'289,289,289,289,289,,,,,,289,289,289,289,289,289,289,289,709,709,709',
+'244,244,244,,,,,,244,244,244,244,244,244,244,244,519,519,519,519,519',
+'519,519,519,519,519,519,519,519,519,519,519,519,519,519,519,519,519',
+'519,519,519,519,519,519,,,,,,519,519,519,519,519,519,519,519,709,709',
 '709,709,709,709,709,709,709,709,709,709,709,709,709,709,709,709,709',
-'709,709,709,709,709,709,709,709,,,,,,709,709,709,709,709,709,709,709',
-'519,519,519,519,519,519,519,519,519,519,519,519,519,519,519,519,519',
-'519,519,519,519,519,519,519,519,519,519,519,,,,,,519,519,519,519,519',
-'519,519,519,622,622,622,622,622,622,622,622,622,622,622,622,622,622',
-'622,622,622,622,622,622,622,622,622,622,622,622,622,622,,,,,,622,622',
-'622,622,622,622,622,622,705,705,705,705,705,705,705,705,705,705,705',
-'705,705,705,705,705,705,705,705,705,705,705,705,705,705,705,705,705',
-',,,,,705,705,705,705,705,705,705,705,239,239,239,239,239,239,239,239',
-'239,239,239,239,239,239,239,239,239,239,239,239,239,239,239,239,239',
-'239,239,239,,,,,,239,239,239,239,239,239' ]
-        racc_action_check = arr = ::Array.new(3623, nil)
+'709,709,709,709,709,709,709,709,709,,,,,,709,709,709,709,709,709,709',
+'709,289,289,289,289,289,289,289,289,289,289,289,289,289,289,289,289',
+'289,289,289,289,289,289,289,289,289,289,289,289,,,,,,289,289,289,289',
+'289,289,289,289,239,239,239,239,239,239,239,239,239,239,239,239,239',
+'239,239,239,239,239,239,239,239,239,239,239,239,239,239,239,,,,,,239',
+'239,239,239,239,239' ]
+        racc_action_check = arr = ::Array.new(3593, nil)
         idx = 0
         clist.each do |str|
@@ -967,95 +968,95 @@
 
 racc_action_pointer = [
-   nil,  1442,    -1,  1586,  1989,   nil,   nil,   nil,   602,   527,
-   nil,   nil,   nil,   nil,   nil,   nil,  1993,   nil,   nil,   nil,
+   nil,   613,    -1,   620,  1492,   nil,   nil,   nil,   612,   627,
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+   nil,   nil,   nil,  1954,   nil,   nil,   904,   812,   nil,  1930,
+   nil,   513,   nil,   nil,   nil,   nil,  2092,   nil,   330,   nil,
+  1947,   835,   240,   nil,  1975,  1976,  1864,  1970,   nil,   nil,
+   nil,  1884,  1974,   982,     8,   nil,   nil,  1474,  1982,   nil,
+   nil,   nil,   nil,  2014,   525,   927,  2015,  1987,   857,   253,
+  1996,   399,   nil,   -13,   nil,  1997,  2024,   nil,  2070,   nil,
+  2000,   205,    -5,    30,   nil,    52,    25,   nil,   nil,  1126,
+   117,    97,   765,   197,   nil,   nil,   180,   nil,   nil,   217,
+   nil,   nil,   279,   291,   379,   nil,   418,   367,   433,   534,
+   412,   454,   467,   460,   nil,   nil,   nil,   nil,   nil,   439,
+   nil,   nil,   nil,    11,   533,   100,   nil,   539,   512,   nil,
+   nil,   558,   414,   nil,   576,   594,   567,   nil,  1566,   606,
    nil ]
 
@@ -1200,5 +1201,5 @@
    665,   nil,   nil,   nil,   nil,   nil,   671,   596,   597,   588,
    nil,   nil,   553,   557,   673,   nil,   238,   nil,   763,   622,
-   853,   nil,   766,   nil,   nil,   nil,   530,   553,   nil,   nil,
+   853,   nil,   766,   nil,   610,   nil,   530,   553,   nil,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   664,   nil,
@@ -1216,5 +1217,5 @@
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   696,
    nil,   873,   nil,   792,   nil,   nil,   nil,   nil,   nil,   nil,
-   nil,   464,   nil,   nil,   339,   nil,   nil,   nil,   nil,   nil,
+   nil,   464,   nil,   nil,   339,   nil,   nil,   750,   610,   nil,
    nil,   769,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
    nil,   894,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
@@ -1280,5 +1281,5 @@
     23,   nil,   nil,   nil,   nil,   nil,    23,     4,     4,    23,
    nil,   nil,    45,    45,    55,   nil,    28,   nil,     6,    47,
-    84,   nil,     6,   nil,   nil,   nil,     5,    45,   nil,   nil,
+    84,   nil,     6,   nil,     4,   nil,     5,    45,   nil,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,    47,   nil,
@@ -1296,5 +1297,5 @@
    nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,    25,
    nil,     6,   nil,    32,   nil,   nil,   nil,   nil,   nil,   nil,
-   nil,    45,   nil,   nil,    22,   nil,   nil,   nil,   nil,   nil,
+   nil,    45,   nil,   nil,    22,   nil,   nil,     4,     4,   nil,
    nil,    47,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
    nil,     6,   nil,   nil,   nil,   nil,   nil,   nil,   nil,   nil,
@@ -2943,5 +2944,5 @@
   def _reduce_104(val, _values, result)
     			# tag が無い場合、内部名を与える
-			result = StructType.new( :"$TAG_#{@@no_struct_tag_num}" )
+			result = StructType.new( :"TAG__#{@@no_struct_tag_num}__" )
 			@@no_struct_tag_num += 1
 			StructType.set_define( true )
@@ -3749,5 +3750,5 @@
 module_eval(<<'.,.,', 'bnf.y.rb', 802)
   def _reduce_233(val, _values, result)
-    	result = [val[0].val]		
+    	result = [val[0]]		
     result
   end
@@ -3756,5 +3757,5 @@
 module_eval(<<'.,.,', 'bnf.y.rb', 804)
   def _reduce_234(val, _values, result)
-    	result << val[2].val		
+    	result << val[2]		
     result
   end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/bnf.y.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/bnf.y.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/bnf.y.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2016 by TOPPERS Project
+#   Copyright (C) 2008-2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -379,5 +379,5 @@
 		{
 			# tag が無い場合、内部名を与える
-			result = StructType.new( :"$TAG_#{@@no_struct_tag_num}" )
+			result = StructType.new( :"TAG__#{@@no_struct_tag_num}__" )
 			@@no_struct_tag_num += 1
 			StructType.set_define( true )
@@ -800,8 +800,8 @@
 
 region_name_list
-        : IDENTIFIER
-		{	result = [val[0].val]		}
-        | region_name_list ',' IDENTIFIER
-		{	result << val[2].val		}
+        : namespace_identifier
+		{	result = [val[0]]		}
+        | region_name_list ',' namespace_identifier
+		{	result << val[2]		}
 
 const_statement
@@ -1807,5 +1807,5 @@
                   string += line
                   # この位置では error メソッドは使えない (token 読出し前)
-                  puts "error: #{file} line #{lineno}: string literal has newline without escape"
+                  puts "#{file}:#{lineno}:#{col}: error: string literal has newline without escape"
                   @@n_error += 1
                 end
@@ -1848,8 +1848,9 @@
                   b_in_string = true
                   # この位置では error メソッドは使えない (token 読出し前) # mikan cdl_error ではない
-                  puts "error: #{file} line #{lineno}: string literal has newline without escape"
+                  puts "#{file}:#{lineno}:#{col}: error: string literal has newline without escape"
                   @@n_error += 1
                 # 山括弧で囲まれた文字列
-                when /\A<[0-9A-Za-z_\. \/]+>/   # AB: angle bracke
+                # when /\A<[0-9A-Za-z_\. \/]+>/   # AB: angle bracke
+                when /\A<(?:[^>\\]|\\.)*>/   # これはうまく行くようだ
                   @q << [:AB_STRING_LITERAL, Token.new($&, file, lineno, col)]
                 # 行コメント
@@ -1981,5 +1982,5 @@
       end
       if locale then
-        Console.puts "error: #{locale[0]}: line #{locale[1]} #{msg}"
+        Console.puts "#{locale[0]}:#{locale[1]}:#{locale[2]}: error: #{msg}"
       else
         Console.puts "error: #{msg}"
@@ -2014,5 +2015,5 @@
       end
       if locale then
-        Console.puts "warning: #{locale[0]}: line #{locale[1]} #{msg}"
+        Console.puts "#{locale[0]}:#{locale[1]}:#{locale[2]}: warning: #{msg}"
       else
         Console.puts "warning: #{msg}"
@@ -2047,5 +2048,5 @@
       end
       if locale then
-        Console.puts "info: #{locale[0]}: line #{locale[1]} #{msg}"
+        Console.puts "#{locale[0]}:#{locale[1]}:#{locale[2]}: info: #{msg}"
       else
         Console.puts "info: #{msg}"
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/componentobj.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/componentobj.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/componentobj.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2017 by TOPPERS Project
+#   Copyright (C) 2008-2019 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -149,5 +149,5 @@
     end
 
-    set_descriptor_list
+    # set_descriptor_list ##
 
     if @generate then
@@ -364,4 +364,14 @@
   end
 
+  @@set_descriptor_list = {}
+  def self.set_descriptor_list
+    Namespace.get_root.travers_all_signature{ |sig|
+      if @@set_descriptor_list[ sig ] == nil then
+        @@set_descriptor_list[ sig ] = true
+        sig.set_descriptor_list
+      end
+    }
+  end
+
   #== Signature# 引数で参照されている Descriptor 型のリストを作成する
   def set_descriptor_list
@@ -538,7 +548,9 @@
 # @ct_factory_list::    Factory[] :    celltype factory
 # @cell_list:: Cell[] : 定義のみ (V1.0.0.2 以降)
+# @ordered_cell_list:: Cell[] : ID 順に順序付けされたセルリスト、最適化以降有効 (リンク単位ごとに生成されなおす)
 # @singleton:: bool
 # @idx_is_id:: bool
 # @idx_is_id_act:: bool: actual value
+# @b_need_ptab:: bool: true if having cells in multi-domain
 # @active:: bool
 # @b_reuse:: bool :  reuse 指定されて import された(template 不要)
@@ -654,8 +666,11 @@
     if $idx_is_id then
       @idx_is_id = true
+      @idx_is_id_act = true
+      @b_need_ptab = true
     else
       @idx_is_id = false
-    end
-    @idx_is_id_act = @idx_is_id
+      @idx_is_id_act = false
+      @b_need_ptab = false
+    end
 
     Namespace.new_celltype( self )
@@ -700,5 +715,5 @@
     end
 
-    check_dynamic_join
+    # check_dynamic_join ##
 
     @@current_object = nil
@@ -886,4 +901,5 @@
         @idx_is_id = true
         @idx_is_id_act = true
+        @b_need_ptab = true
       when :ACTIVE
         @active = true
@@ -899,4 +915,5 @@
     if @singleton then
       @idx_is_id_act = false
+      @b_need_ptab = false
     end
   end
@@ -999,6 +1016,17 @@
   end
 
+  @@dynamic_join_checked_list = {}
+  def self.check_dynamic_join
+    Namespace.get_root.travers_all_celltype{ |ct|
+      if @@dynamic_join_checked_list[ ct ] == nil then
+        @@dynamic_join_checked_list[ ct ] = true
+        ct.check_dynamic_join
+      end
+    }
+  end
+
   #=== Celltype#dynamic の適合性チェック
   def check_dynamic_join
+    return if ! $verbose
     @port.each{ |port|
       signature = port.get_signature
@@ -1038,5 +1066,5 @@
               end
             end
-            cdl_warning( 'W9999 "$1" cannot handle Descriptor "$2" infromation for port "$3"', @name, param.get_name, port.get_name )
+            cdl_warning( 'W9999 "$1" cannot handle Descriptor "$2" information for port "$3"', @name, param.get_name, port.get_name )
           }
         end
@@ -1143,12 +1171,14 @@
   #     呼び口（ただし、最適化で不要となるものは除く）
   def has_INIB?
-#    print "name=#{@name} @n_attribute_ro=#{@n_attribute_ro}  @n_var_size_is=#{@n_var_size_is} @n_call_port=#{@n_call_port} @n_call_port_omitted_in_CB=#{@n_call_port_omitted_in_CB} @n_entry_port_array_ns=#{@n_entry_port_array_ns}\n"
-    return $rom &&
-      (@n_attribute_ro > 0 ||
-       @n_var_size_is > 0 ||
-       ( @n_call_port - @n_call_port_omitted_in_CB - (@n_call_port_dynamic-@n_call_port_array_dynamic) ) > 0 ||
-       $ram_initializer && @n_call_port_dynamic ||
-       @n_entry_port_array_ns > 0)
-#    return $rom && (@n_attribute_ro > 0 || ( @n_call_port - @n_call_port_omitted_in_CB ) > 0)
+
+    result = $rom &&
+             (@n_attribute_ro > 0 ||
+              @n_var_size_is > 0 ||
+              ( @n_call_port - @n_call_port_omitted_in_CB - (@n_call_port_dynamic-@n_call_port_array_dynamic) ) > 0 ||
+              $ram_initializer && @n_call_port_dynamic > 0 ||
+              @n_entry_port_array_ns > 0)
+    # print "name=#{@name} n_attribute_ro=#{@n_attribute_ro}  n_var_size_is=#{@n_var_size_is} n_call_port=#{@n_call_port} n_call_port_omitted_in_CB=#{@n_call_port_omitted_in_CB} n_call_port_dynamic=#{@n_call_port_dynamic} n_call_port_array_dynamic=#{@n_call_port_array_dynamic} n_entry_port_array_ns=#{@n_entry_port_array_ns} has_INIB?=#{result}\n"
+
+    return result
   end
 
@@ -1231,4 +1261,8 @@
   def idx_is_id_act?
     @idx_is_id_act
+  end
+
+  def multi_domain?
+    @b_need_ptab
   end
 
@@ -1353,4 +1387,5 @@
 #                                               逆require ポートに対して複数の結合がないかチェックする
 # @generate:: [ Symbol, String, Plugin ]  = [ PluginName, option, Plugin ] Plugin は生成後に追加される
+# @b_post_code_generated:: Bool: true if generated in tmp_plugin_post_code.cdl
 #
 # composite のためインスタンス変数
@@ -1375,5 +1410,7 @@
 # @id:: Integer : コード生成直前に設定  (プロトタイプ宣言の場合は -1 のまま放置)
 # @id_specified::Integer : 指定された id
-# @restrict_list::{ entry_name => { func_name, [ region_name, ... ] } }
+# @restrict_list::{ entry_name => { func_name, [ region_path_str, ... ] } }
+# @restrict_list2::{ entry_name => { func_name, [ domain_root_region, ... ] } }
+# @b_restrict_referenced::Bool: restrict_list が参照れた
 
 =begin
@@ -1459,4 +1496,7 @@
     @referenced_port_list = {}
     @restrict_list = {}
+    @restrict_list2 = {}
+    @b_restrict_referenced = false
+    @b_post_code_generated = false
 
     @cell_list = {}
@@ -1802,4 +1842,7 @@
       # f_def == true の場合 new_def で、呼出される
       set_specifier_list( Generator.get_statement_specifier )
+    end
+    if TECSGEN.post_coded?
+      @b_post_code_generated = true
     end
     set_f_def f_def
@@ -2133,4 +2176,18 @@
   end
 
+  #=== Cell# composite のセルか？
+  def is_of_composite?
+    if @celltype.kind_of? CompositeCelltype
+      return true
+    else
+      return false
+    end
+  end
+
+  #=== Cell# tmp_plugin_post_code.cdl で生成されたセルか？
+  def post_code_generated?
+    @b_post_code_generated
+  end
+
   # composite cell の port に対応する内部の cell の port の名前（リンク時に必要な名前）
   def get_real_global_name port_name
@@ -2220,4 +2277,6 @@
 
       # セルタイプ内で port_name の CompositeCelltypeJoin を探す（コード生成段階では必ず見つかる）
+      # print "get_real_cell: cell=#{@name} port=#{port_name}\n"
+      # pp @cell_list
       cj = @celltype.find_export( port_name )
 
@@ -2231,4 +2290,13 @@
   end
 
+  #=== Cell#get_real_celltype
+  #
+  def get_real_celltype( port_name )
+    if @celltype.instance_of?( CompositeCelltype ) then
+      return @celltype.get_real_celltype port_name
+    else
+      return @celltype
+    end
+  end
 
   #=== Cell# 受け口のport の参照カウントをアップする
@@ -2271,4 +2339,16 @@
       return "#{@global_name}_#{port_name}"
     end
+  end
+
+  #Cell#属性の初期値を得る
+  #attr_name::Symbol  必ず初期化されていないと Ruby 例外となる
+  def get_attr_initializer attr_name
+    val = @join_list.get_item( attr_name )
+    if val == nil then
+      val = (@celltype.find  attr_name).get_initializer
+    else
+      val = val.get_rhs
+    end
+    return val
   end
 
@@ -2521,6 +2601,12 @@
         else
           cell = j.get_rhs_cell2
-          next if cell == nil     # 右辺が見つからなかった．既にエラー
+          next if cell == nil || cell.get_celltype == nil     # 右辺が見つからなかった．既にエラー
           port = cell.get_celltype.find( j.get_rhs_port2 )
+          if port == nil then
+            dbgPrint "set_port_ref: #{@name}.#{j.get_name} = #{cell.get_name}.#{j.get_rhs_port2}\n"
+            # through プラグインで生成されたセルの受け口が見つからないケース (のハズ)
+            cdl_error( "entry '$1' not found in '$2' refered from $3.$4", j.get_rhs_port2, cell.get_name, @name, j.get_name )
+            next
+          end
           dbgPrint( "set_port_reference_count: #{@name}.#{j.get_name} => #{cell.get_name}.#{port.get_name}\n")
           cell.port_referenced port
@@ -2967,72 +3053,111 @@
   #=== Cell#restrict を追加
   def add_restrict( entry_name, func_name, region_name_list )
-    if @restrict_list[ entry_name ] then
-      if @restrict_list[ entry_name ][ func_name ] then
-        @restrict_list[ entry_name ][ func_name ].each{ |rn|
-          if region_name_list.include? rn then
-            # p func_name
-            name = func_name ? entry_name : entry_name+"."+func_name
-            cdl_warning( "W9999 $1 restrict region duplicate $2", name, rn )
+    if @restrict_list[ entry_name ] == nil then
+      @restrict_list[ entry_name ] = {}
+      @restrict_list2[ entry_name ] = {}
+    end
+    if @restrict_list[ entry_name ][ func_name ] == nil then
+      @restrict_list[ entry_name ][ func_name ] = []
+      @restrict_list2[ entry_name ][ func_name ] = []
+    end
+    region_name_list.each { |rp|
+      @restrict_list[ entry_name ][ func_name ] << rp
+      # p "Class: " + rp.to_s
+      obj = Namespace.find rp
+      if ( obj.kind_of? Region ) then
+        @restrict_list2[ entry_name ][ func_name ] << obj.get_domain_root
+      else
+        cdl_error( "S9999 $1 not found or not region", rp.to_s )
+      end
+    }
+  end
+
+  #=== Cell#check_restrict_list
+  def check_restrict_list
+    # p "check_restrict_list"
+    @restrict_list.each{ |entry_name, func_hash|
+      func_hash.each{ |func_name, region_list|
+        region_list.each{ |rp|
+          obj = Namespace.find rp
+          if ( obj.kind_of? Region ) then
+            if obj.get_domain_root != @region.get_domain_root then
+            else
+              cdl_info( "I9999 $1: restrict calling domain to $2, which is same domain as the cell locates", @name, rp.to_s )
+              # restrict を同じドメインを指定してもよいこととする (HRP3)
+              # KernelDoamin 内のセルに対し、KernelDomain に restrict している場合、
+              # 無所属経由で結合されているが、KernelDomain から呼出すことを想定した許可
+            end
+          else
+            cdl_error( "S9999 $1 not region", rp.to_s )
+          end
+        }
+      }
+    }
+  end
+
+  #=== Cell#callable?
+  def callable?( callee_cell, entry_name, func_name )
+    # p "callable? #{@name}"
+    res = callee_cell.callable_from?( entry_name, func_name, self )
+    dbgPrint "callable? #{callee_cell.get_namespace_path}.#{entry_name}.#{func_name} from #{@NamespacePath} is #{res}\n"
+    return res
+  end
+
+  #=== Cell#callable_from? (private)
+  def callable_from?( entry_name, func_name, caller_cell )
+    @b_restrict_referenced = true
+    if @restrict_list.length == 0 then
+      return true
+    end
+
+    dr = caller_cell.get_region.get_domain_root
+    if @restrict_list[entry_name] then
+      if @restrict_list[entry_name][func_name] then
+        @restrict_list2[entry_name][func_name].each{ |region|
+          if dr == region then
+            return true
+          end
+        }
+      elsif @restrict_list[entry_name][nil] then
+        @restrict_list2[entry_name][nil].each{ |region|
+          if dr == region then
+            return true
           end
         }
       else
-        @restrict_list[ entry_name ][ func_name ] = region_name_list
-      end
-    else
-      func_list = { }
-      func_list[ func_name ] = region_name_list
-      @restrict_list[ entry_name ] = func_list
-    end
-    # pp @restrict_list
-  end
-
-  #=== Cell#check_restrict_list
-  def check_restrict_list
-    @restrict_list.each{ |entry_name, func_hash|
-      func_hash.each{ |func_name, region_list|
-        region_list.each{ |rn|
-          obj = Namespace.find [ rn ]
-          if ( obj.kind_of? Region ) then
-            if obj.get_domain_root != @region.get_domain_root then
-            else
-              cdl_warning( "W9999 $1 in same domain", rn )
-            end
-          else
-            cdl_error( "S9999 $1 not region", region )
-          end
-        }
-      }
-    }
-  end
-
-  #=== Cell#callable?
-  def callable?( callee_cell, entry_name, func_name )
-    res = callee_cell.callable_from?( entry_name, func_name, self )
-    dbgPrint "callable? #{callee_cell.get_namespace_path}.#{entry_name}.#{func_name} from #{@NamespacePath} is #{res}\n"
-    return res
-  end
-
-  #=== Cell#callable_from? (private)
-  def callable_from?( entry_name, func_name, caller_cell )
-    if @restrict_list.length == 0 then
+        return false
+      end
+    else
+      return false
+    end
+  end
+
+  #=== Cell#get_callable_regions( entry_name, func_name )
+  # func_name=nil の場合、entry_name の可否をチェック数る
+  # nil が返る場合、制限されていないことを意味する
+  def get_restricted_regions( entry_name, func_name )
+    # p "get_restricted_regions #{@name}"
+    @b_restrict_referenced = true
+    if @restrict_list[entry_name] then
+      if @restrict_list[entry_name][func_name] then
+        return @restrict_list2[entry_name][func_name]
+      else
+        return @restrict_list2[entry_name][nil]
+      end
+    end
+    return nil
+  end
+
+  #=== Cell#has_ineffective_restrict_specifier
+  # restrict 指定子が指定されていて、参照されていない場合 true
+  # 参照は、HRPSVCPlugin のみ
+  def has_ineffective_restrict_specifier
+    if @restrict_list.length != 0 && @b_restrict_referenced == false then
       return true
-    end
-
-    if @restrict_list[entry_name] then
-      if @restrict_list[entry_name][nil] &&
-         @restrict_list[entry_name][nil].include?( caller_cell.get_region.get_domain_root.get_name )then
-        return true
-      end
-      if @restrict_list[entry_name][func_name] &&
-         @restrict_list[entry_name][func_name].include?( caller_cell.get_region.get_domain_root.get_name )then
-        return true
-      else
-        return false
-      end
-    else
-      return true
-    end
-  end
-  
+    else
+      return false
+    end
+  end
+
   def show_tree( indent )
     indent.times { print "  " }
@@ -3710,4 +3835,8 @@
   end
 
+  def get_global_name
+    @global_name
+  end
+
   def get_port_list
     @port_list
@@ -3724,4 +3853,16 @@
   def get_internal_allocator_list
     @internal_allocator_list
+  end
+
+  #== CompositeCelltype#get_real_celltype
+  # port_name に接続されている内部のセルタイプを得る
+  def get_real_celltype( port_name )
+    cj = find_export port_name
+    inner_celltype = cj.get_cell.get_celltype
+    if inner_celltype.instance_of? CompositeCelltype then
+      return inner_celltype.get_real_celltype
+    else
+      return inner_celltype
+    end
   end
 
@@ -3937,5 +4078,5 @@
     else
       # entry port optimize
-      if $unopt then
+      if $unopt || $unopt_entry then
         # 最適化なし
         @b_VMT_useless = false                     # VMT 不要 (true の時 VMT を介することなく呼出す)
@@ -4261,9 +4402,21 @@
 
   def is_VMT_useless?                     # VMT 関数テーブルを使用しない
-   @b_VMT_useless
+    if @port_type == :ENTRY && $unopt_entry == true then
+      # プラグインから $unopt_entry を設定するケースのため
+      # ここで読み出すときに、false を返す (reset_optimize での設定変更は速すぎる)
+      return false
+    else
+      return @b_VMT_useless
+    end
   end
 
   def is_skelton_useless?                 # スケルトン関数不要   (true の時、受け口関数を呼出す)
-    @b_skelton_useless
+    if @port_type == :ENTRY && $unopt_entry == true then
+      # プラグインから $unopt_entry を設定するケースのため
+      # ここで読み出すときに、false を返す (reset_optimize での設定変更は速すぎる)
+      return false
+    else
+      return @b_skelton_useless
+    end
   end
 
@@ -4802,7 +4955,7 @@
       if ! c.get_f_def then   # Namespace の @cell_list にはプロトタイプが含まれるケースあり
         if c.get_f_ref then
-          cdl_error( "S1093 $1 : undefined cell" , c.get_namespace_path.get_path_str )
+          c.cdl_error( "S1093 $1 : undefined cell" , c.get_namespace_path.get_path_str )
         elsif $verbose then
-          cdl_warning( "W1006 $1 : only prototype, unused and undefined cell" , c.get_namespace_path.get_path_str )
+          c.cdl_warning( "W1006 $1 : only prototype, unused and undefined cell" , c.get_namespace_path.get_path_str )
         end
       else
@@ -4811,5 +4964,8 @@
         # if c.get_f_ref == false && c.is_generate? && ct && ct.is_inactive? then
         if c.get_f_ref == false && ct && ct.is_inactive? then
-          cdl_warning( "W1007 $1 : non-active cell has no entry join and no factory" , c.get_namespace_path.get_path_str )
+          c.cdl_warning( "W1007 $1 : non-active cell has no entry join and no factory" , c.get_namespace_path.get_path_str )
+        end
+        if c.has_ineffective_restrict_specifier then
+          c.cdl_warning( "W9999: $1 has ineffective restrict specifier", c.get_namespace_path.get_path_str )
         end
       end
@@ -5006,4 +5162,16 @@
   end
 
+  #== Namespace (Region) に属するセルのリスト
+  def get_cell_list
+    @cell_list
+  end
+
+  #== Namespace (Region)# 子リージョンのリスト
+  #
+  # リージョンは Namespace クラスで namespace として記憶されている
+  def get_region_list
+    @namespace_list
+  end
+  
   def show_tree( indent )
     indent.times { print "  " }
@@ -5602,4 +5770,5 @@
           next_cell_nsp       = @through_generated_list[ i + 1 ].get_cell_namespace_path
           next_port_name      = @through_generated_list[ i + 1 ].get_through_entry_port_name
+          next_port_subscript = @through_generated_list[ i + 1 ].get_through_entry_port_subscript
         rescue Exception => evar
           cdl_error( "S1124 $1: plugin function failed: \'get_through_entry_port_name\'" , plugin_name )
@@ -5620,4 +5789,5 @@
         next_cell      = @cell
         next_port_name = @port_name
+        next_port_subscript = @rhs_subscript
 
         if next_cell == nil then
@@ -5631,5 +5801,5 @@
         # region から @cell_name.@port_name への through がないか探す
         # rp = @through_list[i][3].find_cell_port_through_plugin( @cell_name, @port_name ) #762
-        rp = @through_list[i][3].find_cell_port_through_plugin( @cell.get_global_name, @port_name )
+        rp = @through_list[i][3].find_cell_port_through_plugin( @cell.get_global_name, @port_name, @rhs_subscript )
            # @through_list[i] と @region_through_list[i-cp_len] は同じ
         # 共用しないようにするには、見つからなかったことにすればよい
@@ -5644,5 +5814,5 @@
         plClass = load_plugin( plugin_name, ThroughPlugin )
         if( plClass ) then
-          gen_through_cell_code_and_parse( plugin_name, i, next_cell, next_port_name, plClass )
+          gen_through_cell_code_and_parse( plugin_name, i, next_cell, next_port_name, next_port_subscript, plClass )
         end
       else
@@ -5657,5 +5827,5 @@
           # 生成したものを region(@through_list[i][3]) のリストに追加
           # @through_list[i][3].add_cell_port_through_plugin( @cell_name, @port_name, @through_generated_list[i] ) #762
-          @through_list[i][3].add_cell_port_through_plugin( @cell.get_global_name, @port_name, @through_generated_list[i] )
+          @through_list[i][3].add_cell_port_through_plugin( @cell.get_global_name, @port_name, @rhs_subscript, @through_generated_list[i] )
         end
       end
@@ -5691,5 +5861,5 @@
 
   #=== Join# through プラグインを呼び出して CDL 生成させるとともに、import する
-  def gen_through_cell_code_and_parse( plugin_name, i, next_cell, next_port_name, plClass )
+  def gen_through_cell_code_and_parse( plugin_name, i, next_cell, next_port_name, next_port_subscript, plClass )
 
     through = @through_list[ i ]
@@ -5718,5 +5888,7 @@
 
     begin
-      plugin_object = plClass.new( "#{generating_cell_name}".to_sym, plugin_arg.to_s, next_cell, "#{next_port_name}".to_sym, @definition.get_signature, @celltype, caller_cell )
+      plugin_object = plClass.new( generating_cell_name.to_sym, plugin_arg.to_s,
+                                   next_cell, next_port_name.to_sym, next_port_subscript,
+                                   @definition.get_signature, @celltype, caller_cell )
       plugin_object.set_locale @locale
     rescue Exception => evar
@@ -5913,5 +6085,12 @@
   end
 
-  def get_rhs_subscript
+  # 末尾数字1 : CDL で指定された、右辺のセルを返す
+  def get_rhs_cell1   # get_cell と同じ
+    @cell
+  end
+  def get_rhs_port1   # get_port_name 同じ
+    @port_name
+  end
+  def get_rhs_subscript1
     @rhs_subscript
   end
@@ -5923,7 +6102,5 @@
     # through 指定あり？
     if @through_list[0] then
-      # mikan through で生成したものが root namespace 限定
       # through で生成されたセルを探す
-#      cell = Namespace.find( [ "::", @through_generated_list[0].get_cell_name.to_sym ] )    #1
       cell = Namespace.find( @through_generated_list[0].get_cell_namespace_path )    #1
       # cell のプラグインで生成されたポート名のポートを探す (composite なら内部の繋がるポート)
@@ -5932,4 +6109,16 @@
       # ポートを返す(composite なら内部の繋がるポートを返す)
       return @cell.get_real_port( @port_name )
+    end
+  end
+
+  #=== Join# 右辺の配列添数を得る
+  #    右辺が through の場合は挿入されたセルの添数
+  #    右辺が composite の場合は、内部の繋がるセルのポートの添数 (composite では変わらない)
+  #    このメソッドは get_rhs_cell,  と対になっている
+  def get_rhs_subscript
+    if @through_list[0] then
+      return @through_generated_list[0].get_through_entry_port_subscript
+    else
+      return @rhs_subscript
     end
   end
@@ -6569,5 +6758,5 @@
 end
 
-#== Domain
+#== DomainType
 #
 # region の domain を記憶するクラス
@@ -6608,4 +6797,5 @@
       return if pluginClass == nil
       @plugin = pluginClass.new( @region, @name, @option )
+      @plugin.set_locale @locale
     end
   end
@@ -6625,5 +6815,5 @@
   end
 
-  #== Domain リージョンの Hash を得る
+  #== DomainType リージョンの Hash を得る
   # @@domain_regions の説明参照
   def self.get_domain_regions
@@ -6637,4 +6827,10 @@
   def get_option
     @option
+  end
+
+  #== DomainType#ドメイン種別を得る
+  #return::Symbol :kernel, :user, :OutOfDomain
+  def get_kind
+    @plugin.get_kind
   end
 
@@ -6698,4 +6894,5 @@
 
     if @@domain_name then
+      dbgPrint "Region=#{name} domain_type=#{@@domain_name} option=#{@@domain_option}\n"
       domain_option = CDLString.remove_dquote @@domain_option.to_s
       @domain_type = DomainType.new( self, @@domain_name, domain_option )
@@ -6946,4 +7143,10 @@
   end
 
+  #== Region# ルートリージョン
+  # ルートリージョンは、namespace のルートと同じインスタンス
+  def selfget_root
+    Namespace.get_root
+  end
+
   def next_in_through_count
     @in_through_count += 1
@@ -6979,10 +7182,16 @@
   #=== Region# through プラグインで、この region から cell_name.port_name へのプラグインオブジェクトを登録
   # mikan namesppace 対応 (cell_name)
-  def add_cell_port_through_plugin( cell_name, port_name, through_plugin_object )
-    @cell_port_throug_plugin_list[ "#{cell_name}.#{port_name}" ] = through_plugin_object
-  end
-
-  def find_cell_port_through_plugin( cell_name, port_name )
-    return @cell_port_throug_plugin_list[ "#{cell_name}.#{port_name}" ]
+  def add_cell_port_through_plugin( cell_name, port_name, subscript, through_plugin_object )
+    if subscript then
+      subscript = '[' + subscript.to_s + ']'
+    end
+    @cell_port_throug_plugin_list[ "#{cell_name}.#{port_name}#{subscript}" ] = through_plugin_object
+  end
+
+  def find_cell_port_through_plugin( cell_name, port_name, subscript )
+    if subscript then
+      subscript = '[' + subscript.to_s + ']'
+    end
+    return @cell_port_throug_plugin_list[ "#{cell_name}.#{port_name}#{subscript}" ]
   end
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/ctypes.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/ctypes.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/ctypes.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -122,5 +122,6 @@
       #   TECS には long double を表現する手段がない (double80_t を定義すればよいか?)
 #      cdl_warning( "C1003 $1 & $2 incompatible (\'long double\' is not supported.). Treated as $3." , self.class, another.class, self.class )
-      cdl_warning( "W9999 $1 & $2 incompatible (\'long double\' is not supported.). Treated as $3." , self.get_type_str, another.get_type_str, self.get_type_str )
+#      cdl_warning( "W9999 $1 & $2 incompatible (\'long double\' is not supported.). Treated as $3." , self.get_type_str, another.get_type_str, self.get_type_str )
+      self.to_long      
       return self
     else
@@ -185,4 +186,11 @@
   end
 
+  def to_long
+    if @bit_size != -64 then
+      cdl_warning( "W9999 long specified for $1" , get_type_str )
+    else
+      @bit_size = -128  # @bit_size = -128 : long double
+    end
+  end
 end
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/expression.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/expression.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/expression.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/generate.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/generate.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/generate.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2017 by TOPPERS Project
+#   Copyright (C) 2008-2019 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -122,4 +122,5 @@
 
 class Namespace
+  @@domain_gen_factory_list = nil
   def generate
 
@@ -135,4 +136,7 @@
           return
         end
+        if instance_of? Region then
+          @@domain_gen_factory_list = {}   # create hash
+        end
       end
 
@@ -141,4 +145,13 @@
       gen_global_header
 
+      if ( instance_of? Region ) && get_domain_type != nil then
+        # p "*******************  domain_type: #{get_domain_type.get_name}  ****************"
+        domain_type = get_domain_type
+        if @@domain_gen_factory_list[ domain_type ] == nil then
+          @@domain_gen_factory_list[ domain_type ] = self
+          domain_type.gen_factory
+        end
+      end
+      
       # signature のコードを生成
       @signature_list.each { |s|
@@ -455,5 +468,5 @@
       }
     end
-	f.print "	rm -f $(CELLTYPE_COBJS) $(TECSGEN_COBJS) $(PLUGIN_COBJS) $(OTHER_OBJS) $(TARGET) #{timestamp}\n"
+	  f.print "	rm -f $(CELLTYPE_COBJS) $(TECSGEN_COBJS) $(PLUGIN_COBJS) $(OTHER_OBJS) $(TARGET) #{timestamp}\n"
     if $generating_region == @@root_namespace then
       f.print "	rm -rf $(GEN_DIR)\n"
@@ -465,7 +478,6 @@
       f.print "tecs : $(PRE_TECSGEN_TARGET) $(TIMESTAMP) $(POST_TECSGEN_TARGET)\n\n"
       f.print "$(TIMESTAMP) : $(TECS_IMPORTS)\n"
-      f.print "	$(TECSGEN) #{TECSGEN.subst_tecspath( $arguments, true )}\n"
+      f.print "	$(TECSGEN) #{TECSGEN.subst_tecspath( $arguments, true )}\n\n"
       # f.print "	touch $(TIMESTAMP)\n\n"
-
     else
       f.print "tecs:\n"
@@ -473,4 +485,44 @@
     end
 
+    # tecsflow:, tcflow ターゲット
+    if $generating_region.get_n_cells != 0 || $generating_region == @@root_namespace then
+      f.print "#####  TECSFlow targets  #####\n"
+    end
+
+    if Region.get_link_roots.length > 1 && $generating_region == @@root_namespace then
+      tecsflow_target = "tecsflow_sub"
+      if $generating_region.get_n_cells > 0 then
+        f.print "tecsflow: tecs tecsflow_sub\n"
+      else
+        f.print "tecsflow:\n"
+      end
+      Region.get_link_roots.each {|region|
+        if region.get_n_cells > 0 then
+          f.print "\tcd #{region.get_global_name}; make tecsflow\n"
+        end
+      }
+      f.print "\n"
+    else
+      tecsflow_target = "tecsflow"
+    end
+
+    if $generating_region.get_n_cells != 0 then
+      f.print "#{tecsflow_target} : $(GEN_DIR)/tecsgen.rbdmp tcflow\n"
+      f.print "\ttecsflow -g $(GEN_DIR)\n\n"
+      f.print "tecsflow_u : $(GEN_DIR)/tecsgen.rbdmp tcflow\n"
+      f.print "\ttecsflow -g $(GEN_DIR) -U\n\n"
+      f.print "$(GEN_DIR)/tecsgen.rbdmp : tecs\n\n"
+      f.print "tcflow : tecs\n"
+      f.print "\tmake tcflow_exec\n\n"
+      f.print "tcflow_exec : $(GEN_DIR)/tcflow.rbdmp\n"
+      f.print "$(GEN_DIR)/tcflow.rbdmp : $(CELLTYPE_SRCS) $(PLUGIN_CELLTYPE_SRCS)\n"
+      f.print "\ttcflow -g $(GEN_DIR) -c '$(CC) -E -DTECSFLOW -DTECSGEN $(CFLAGS) -I ./' $^\n"
+    end
+
+    if $generating_region.get_n_cells != 0 || $generating_region == @@root_namespace then
+      f.print "#####  end TECSFlow targets  #####\n\n"
+    end
+
+    # generic %.o : %.c
     f.print "# generic target for objs\n"
     f.print "$(_TECS_OBJ_DIR)%.o : %.#{$c_suffix}\n"
@@ -492,4 +544,46 @@
     ### Makefile.tecsgen の生成
     f = AppFile.open( "#{$gen}/Makefile.tecsgen" )
+
+    f.print <<EOT
+# generated automatically by tecsgen.
+# This file is not intended to modify.
+#
+# Makefile variables below are defined.
+#  TECS_IMPORT_CDLS          .cdl files improted by import statement
+#  SIGNATURE_HEADERS         .h files of signature
+#  CELLTYPE_TECSGEN_HEADERS  .h files of celltype
+#  CELLTYPE_FACTORY_HEADERS  .h files of celltype's factory
+#  TECS_HEADERS              summary of .h files above
+#  TECS_INLINE_HEADERS       .h files of celltype inline header
+#  PLUGIN_INLINE_HEADERS     .h files of plugin generated inline header
+#
+#  TECS_COBJS                .o files of TECS
+#                            = $(TECSGEN_COBJS)+$(PLUGIN_COBJS)+$(CELLTYPE_COBJS)
+#                            = $(TECS_KERNEL_COBJS)+$(TECS_KERNEL_COBJS)+$(TECS_OUTOFDOMAIN_COBJS)
+#                            = $(TECSGEN_domain_COBJS)+$(PLUGIN_domain_COBJS)+$(CELLTYPE_domain_COBJS) for each domain
+#
+#  TECSGEN_COBJS             .o files of celltype_tecsgen.c
+#  CELLTYPE_COBJS            .o files of celltype.c (celltype code)
+#  PLUGIN_COBJS              .o files of plugin generated .c files
+#
+#  TECSGEN_SRCS              .c files of celltype_tecsgen.c
+#  CELLTYPE_SRCS             .c files of celltype.c (celltype code)
+#  PLUGIN_SRCS               .c files of plugin generated
+#  PLUGIN_CELLTYPE_SRCS      .c files of plugin generated celltype.c (celltype code)
+#  PLUGIN_TECSGEN_SRCS       .c files of plugin generated celltype_tecsgen.c
+#
+# Variables for domain
+#  TECS_DOMAINS             domain names
+#  TECS_KERNEL_COBJS        .o files of kernel domain (tecsgen, celltype, plugin)
+#  TECS_USER_COBJS          .o files of user domain (tecsgen, celltype, plugin)
+#  TECS_OUTOFDOMAIN_COBJS   .o files of OutOfDomain (tecsgen, celltype, plugin)
+#  TECSGEN_domain_COBJS     .o files of celltype_tecsgen.c files for each domain
+#  PLUGIN_domain_COBJS      .o files of plugin generated .c files for each domain
+#  CELLTYPE_domain_COBJS    .o files of celltype.c files for each domain
+#  TECSGEN_domain_SRCS      .c files of celltype_domain_tecsgen.c
+#  PLUGIN_domain_SRCS       .c files of plugin generated .c files for each domain
+#  CELLTYPE_domain_SRCS     .c files of celltype.c files for each domain
+
+EOT
 
     f.print( "TECS_IMPORT_CDLS =" )
@@ -546,4 +640,5 @@
     DomainType.get_domain_regions.each{ |dt, regions|
       # domain_type は一つのノードには、一つしかないので、このループは、必ず一回しか回らない
+        ###   mikan 複数のノードがあり、異なる domain_type が指定される可能性はある
       domain_regions = regions
       domain_type = dt
@@ -588,5 +683,38 @@
       f.print( "\n\n" )
 
-      f.print( "# TECS_COBJS: objects from sources which are automatically generated by tecsgen\n" )
+      f.print( "# TECS_KERNEL_COBJS: objects belong to kernel domain\n" )
+      f.print( "TECS_KERNEL_COBJS = \\\n" )
+      domain_regions.each{ |r|
+        if r.get_domain_type.get_kind == :kernel then
+          f.print( "	$(TECSGEN#{decideDomainNameProc.call r}_COBJS) \\\n" )
+          f.print( "	$(PLUGIN#{decideDomainNameProc.call r}_COBJS) \\\n" )
+          f.print( "	$(CELLTYPE#{decideDomainNameProc.call r}_COBJS) \\\n" )
+        end
+      }
+      f.print( "# TECS_KERNEL_COBJS terminator\n\n" )
+
+      f.print( "# TECS_USER_COBJS: objects belong to user domain\n" )
+      f.print( "TECS_USER_COBJS = \\\n" )
+      domain_regions.each{ |r|
+        if r.get_domain_type.get_kind == :user then
+          f.print( "	$(TECSGEN#{decideDomainNameProc.call r}_COBJS) \\\n" )
+          f.print( "	$(PLUGIN#{decideDomainNameProc.call r}_COBJS) \\\n" )
+          f.print( "	$(CELLTYPE#{decideDomainNameProc.call r}_COBJS) \\\n" )
+        end
+      }
+      f.print( "# TECS_USER_COBJS terminator\n\n" )
+
+      f.print( "# TECS_OUTOFDOMAIN_COBJS: objects belong to OutOfDomain\n" )
+      f.print( "TECS_OUTOFDOMAIN_COBJS = \\\n" )
+      domain_regions.each{ |r|
+        if r.get_domain_type.get_kind == :OutOfDomain then
+          f.print( "	$(TECSGEN#{decideDomainNameProc.call r}_COBJS) \\\n" )
+          f.print( "	$(PLUGIN#{decideDomainNameProc.call r}_COBJS) \\\n" )
+          f.print( "	$(CELLTYPE#{decideDomainNameProc.call r}_COBJS) \\\n" )
+        end
+      }
+      f.print( "# TECS_OUTOFDOMAIN_COBJS terminator\n\n" )
+      
+      f.print( "# TECSGEN_COBJS: objects from sources which are automatically generated by tecsgen\n" )
       f.print( "TECSGEN_COBJS = \\\n" )
       domain_regions.each{ |r|
@@ -622,5 +750,5 @@
 
     ###
-    f.print( "# TECS_COBJS: objects from sources which are automatically generated by tecsgen\n" )
+    f.print( "# TECSGEN_COBJS: objects from sources which are automatically generated by tecsgen\n" )
     domain_regions.each{ |r|
       nsp = decideDomainNameProc.call( r )
@@ -656,12 +784,32 @@
 
     f.print( "# PLUGIN_SRCS: sources automatically generated by plugin\n" )
+    f.print( "PLUGIN_CELLTYPE_SRCS = \\\n" )
     domain_regions.each{ |r|
       nsp = decideDomainNameProc.call( r )
-      f.print( "PLUGIN#{nsp}_SRCS = \\\n" )
-      gen_celltype_names_domain( f, "	$(GEN_DIR)/", "_tecsgen.#{$c_suffix} \\\n", domain_type, r, true )
-      gen_celltype_names_domain2( f, "	$(GEN_DIR)/", ".#{$c_suffix} \\\n", domain_type, r, true, false )
-      f.print( "# PLUGIN#{nsp}_SRCS terminator\n\n" )
-    }
-
+      f.print( "  $(PLUGIN#{nsp}_CELLTYPE_SRCS)\\\n" )
+    }
+    f.print( "# PLUGIN_CELLTYPE_SRCS terminator\n\n" )
+    f.print( "PLUGIN_TECSGEN_SRCS = \\\n" )
+    domain_regions.each{ |r|
+      nsp = decideDomainNameProc.call( r )
+      f.print( "  $(PLUGIN#{nsp}_TECSGEN_SRCS)\\\n" )
+    }
+    f.print( "# PLUGIN_TECSGEN_SRCS terminator\n\n" )
+    domain_regions.each{ |r|
+      nsp = decideDomainNameProc.call( r )
+      f.print( "PLUGIN#{nsp}_SRCS = $(PLUGIN#{nsp}_CELLTYPE_SRCS) $(PLUGIN#{nsp}_TECSGEN_SRCS)\n\n" )
+      f.print( "PLUGIN#{nsp}_CELLTYPE_SRCS = \\\n" )
+      gen_celltype_names_domain2( f, "", ".#{$c_suffix} \\\n", domain_type, r, true, false )
+      f.print( "# PLUGIN#{nsp}_CELLTYPE_SRCS terminator\n\n" )
+      nsp = decideDomainNameProc.call( r )
+      f.print( "PLUGIN#{nsp}_TECSGEN_SRCS = \\\n" )
+      gen_celltype_names_domain( f, "", "_tecsgen.#{$c_suffix} \\\n", domain_type, r, true )
+      f.print( "# PLUGIN#{nsp}_TECSGEN_SRCS terminator\n\n" )
+    }
+
+    f.print( "# CELLTYPE_SRCS: sources of celltype code written by user\n" )
+     f.print( "CELLTYPE_SRCS = \\\n" )
+     gen_celltype_names( f, "	", ".#{$c_suffix} \\\n", false, false )
+      f.print( "# CELLTYPE_SRCS terminator\n\n" )
     f.close
 
@@ -779,4 +927,23 @@
     @namespace_list.each{ |ns|
       ns.travers_all_signature_proc proc
+    }
+  end
+
+  #=== Namespace#すべてのセルタイプをたどる
+  def travers_all_celltype # ブロック引数 { |celltype|  }
+    proc = Proc.new    # このメソッドのブロック引数
+    @celltype_list.each{ |ct|
+      proc.call ct
+    }
+    @namespace_list.each{ |ns|
+      ns.travers_all_celltype_proc proc
+    }
+  end
+  def travers_all_celltype_proc proc
+    @celltype_list.each{ |ct|
+      proc.call ct
+    }
+    @namespace_list.each{ |ns|
+      ns.travers_all_celltype_proc proc
     }
   end
@@ -1023,5 +1190,9 @@
     gen_ph_get_cellcb f
     gen_ph_attr_access f          if @n_attribute_rw > 0 || @n_attribute_ro > 0 || @n_var > 0
-    gen_ph_cp_fun_macro f         if @n_call_port > 0
+    f.print "#ifndef TECSFLOW\n"
+    gen_ph_cp_fun_macro f, false  if @n_call_port > 0
+    f.print "#else  /* TECSFLOW */\n"
+    gen_ph_cp_fun_macro f, true   if @n_call_port > 0
+    f.print "#endif /* TECSFLOW */\n"
 #    gen_ph_abstract_ep_des_type f
 
@@ -1247,4 +1418,6 @@
   def gen_ph_info f
 
+    yn_multi_domain = "no"
+    yn_multi_domain = "yes" if multi_domain?
     yn_idx_is_id = "no"
     yn_idx_is_id = "yes"  if @idx_is_id
@@ -1255,4 +1428,8 @@
     yn_rom       = "no"
     yn_rom       = "yes"  if $rom
+    yn_has_CB    = "no"
+    yn_has_CB    = "yes"  if has_CB?
+    yn_has_INIB  = "no"
+    yn_has_INIB  = "yes"  if has_INIB?
     yn_cb_init   = "no"
     yn_cb_init   = "yes"  if need_CB_initializer?
@@ -1263,8 +1440,9 @@
  * celltype          :  #{@name}
  * global name       :  #{@global_name}
+ * multi-domain      :  #{yn_multi_domain}
  * idx_is_id(actual) :  #{yn_idx_is_id}(#{yn_idx_is_id_act})
  * singleton         :  #{yn_singleton}
- * has_CB            :  #{has_CB?}
- * has_INIB          :  #{has_INIB?}
+ * has_CB            :  #{yn_has_CB}
+ * has_INIB          :  #{yn_has_INIB}
  * rom               :  #{yn_rom}
  * CB initializer    :  #{yn_cb_init}
@@ -1595,5 +1773,5 @@
       f.print( "#define #{@global_name}_GET_CELLCB(idx) ((void *)0)\n" )
     elsif @idx_is_id_act then   # mikan 単一のセルの場合の最適化, idx_is_id でない場合
-      f.print( "#define #{@global_name}_GET_CELLCB(idx) (#{@global_name}_CB_tab[(idx) - #{@global_name}_ID_BASE])\n" )
+      f.print( "#define #{@global_name}_GET_CELLCB(idx) (#{@global_name}_CB_ptab[(idx) - #{@global_name}_ID_BASE])\n" )
     else
       f.print( "#define #{@global_name}_GET_CELLCB(idx) (idx)\n" )
@@ -1799,6 +1977,6 @@
   end
 
-  def gen_ph_cp_fun_macro f
-    if @n_call_port >0 then
+  def gen_ph_cp_fun_macro f, b_flow
+    if @n_call_port >0 && b_flow == false then
       f.printf( TECSMsg.get( :CPM_comment ) , "#_CPM_#" )
     end
@@ -1856,5 +2034,7 @@
 
         # 関数名の出力(標準：受け口ディスクリプタから VMT の関数名、最適化：受け口関数 or 受け口ディスクリプタ)
-        if ! p.is_VMT_useless? then
+        if b_flow then
+          f.print( "\t  (p_that)->#{p.get_name}#{subsc}.#{fun.get_name}__T( \\\n" )
+        elsif ! p.is_VMT_useless? then
           # 標準コード
           if @singleton then
@@ -1891,5 +2071,6 @@
 
         # 受け口情報の出力(標準：受け口ディスクリプタ、最適化：IDX など)
-        if ! p.is_skelton_useless? && ! p.is_cell_unique? then
+        if b_flow then
+        elsif ! p.is_skelton_useless? && ! p.is_cell_unique? then
           # 標準コード
           if @singleton then
@@ -1969,5 +2150,5 @@
         p_cellcb = "    #{@global_name}_CB *p_cellcb = p_that;\n"
         delim = ", "
-        cb = "p_that#{inib}->"
+        cb = "p_cellcb#{inib}->"
       end
 
@@ -2616,23 +2797,45 @@
         f.print "extern  #{@global_name}_INIB  #{@global_name}_SINGLE_CELL_INIB;\n"
       end
-
-#     @ordered_cell_list.each{ |c|
-#        f.print "extern  #{@global_name}_CB  #{@global_name}_#{c.get_name}_CB;\n"
-#      }
-
       f.print "\n"
-    elsif @idx_is_id_act then
-      f.print "extern #{@global_name}_CB  *#{@global_name}_CB_tab[];\n"
+    elsif @b_need_ptab then
+      f.printf( TECSMsg.get( :SCP_comment ),  "#_MCPP_#" )
+      if has_CB? then
+        f.print "extern #{@global_name}_CB  *const #{@global_name}_CB_ptab[];\n"
+        @ordered_cell_list.each{ |c|
+          if c.is_generate? then                           # 生成対象か？
+            name_array = get_name_array c
+            f.print "extern #{@global_name}_CB  #{name_array[4]};\n"
+          end
+        }
+      elsif has_INIB?
+        f.print "extern #{@global_name}_INIB  *const #{@global_name}_INIB_ptab[];\n"
+        @ordered_cell_list.each{ |c|
+          if c.is_generate? then                           # 生成対象か？
+            name_array = get_name_array c
+            f.print "extern #{@global_name}_INIB  #{name_array[11]};\n"
+          end
+        }
+      end
     else
-      f.print "extern #{@global_name}_CB  #{@global_name}_CB_tab[];\n"
+      f.printf( TECSMsg.get( :SCP_comment ),  "#_MCPB_#" )
+      if has_CB? then
+        f.print "extern #{@global_name}_CB  #{@global_name}_CB_tab[];\n"
+      elsif has_INIB?
+        f.print "extern #{@global_name}_INIB  #{@global_name}_INIB_tab[];\n"
+      end
     end
   end
 
   def gen_ph_INIB_as_CB f
-
+    # ここは、手抜きである。本来なら INIB を出力すべき
     if ! has_CB? && has_INIB? then
       f.printf( TECSMsg.get( :DCI_comment ),  "#_DCI_#" )
-      f.print "#define #{@global_name}_CB_tab           #{@global_name}_INIB_tab\n"
-      f.print "#define #{@global_name}_SINGLE_CELL_CB   #{@global_name}_SINGLE_CELL_INIB\n"
+      if @singleton then
+        f.print "#define #{@global_name}_SINGLE_CELL_CB   #{@global_name}_SINGLE_CELL_INIB\n"
+      elsif @b_need_ptab then
+        f.print "#define #{@global_name}_CB_ptab           #{@global_name}_INIB_ptab\n"
+      else
+        f.print "#define #{@global_name}_CB_tab           #{@global_name}_INIB_tab\n"
+      end
       f.print "#define #{@global_name}_CB               #{@global_name}_INIB\n"
       f.print "#define tag_#{@global_name}_CB           tag_#{@global_name}_INIB\n"
@@ -2658,13 +2861,15 @@
       f.printf( TECSMsg.get( :FEC_comment ), "#_FEC_#" )
 
-      if @idx_is_id_act then
+      if @b_need_ptab then
         amp = ''
+        tab = 'ptab'
       else
         amp = '&'
+        tab = 'tab'
       end
       f.print <<EOT
 #define FOREACH_CELL(i,p_cb)   \\
     for( (i) = 0; (i) < #{@global_name}_N_CELL; (i)++ ){ \\
-       #{necessity}(p_cb) = #{amp}#{@global_name}_CB_tab[i];
+       #{necessity}(p_cb) = #{amp}#{@global_name}_CB_#{tab}[i];
 
 #define END_FOREACH_CELL   }
@@ -2799,6 +3004,6 @@
         if @singleton then
           f.print "\t#{that}_inib = &#{@global_name}_SINGLE_CELL_INIB;\n\n"
-        elsif @idx_is_id_act
-          f.print "\t#{that}_inib = #{@global_name}_INIB_tab[(i)];\n\n"
+        elsif @b_need_ptab then
+          f.print "\t#{that}_inib = #{@global_name}_INIB_ptab[(i)];\n\n"
         else
           f.print "\t#{that}_inib = &#{@global_name}_INIB_tab[(i)];\n\n"
@@ -3397,5 +3602,5 @@
         fs.each{ |r, f| f.print "#{@global_name}_INIB #{@global_name}_SINGLE_CELL_INIB = \n" }
         indent = 0
-      elsif ! @idx_is_id_act then
+      elsif ! @b_need_ptab then
         fs.each{ |r, f| f.print "#{@global_name}_INIB #{@global_name}_INIB_tab[] = {\n" }
         indent = 1
@@ -3418,5 +3623,5 @@
 
         print_indent( f, indent )
-        if @idx_is_id_act then
+        if @b_need_ptab then
           f.print "const #{@global_name}_INIB #{name_array[5]} = "
         end
@@ -3428,5 +3633,5 @@
         unless @singleton then
           # 1 つの cell INIB の終わり
-          if @idx_is_id_act then
+          if @b_need_ptab then
             f.print( "};\n\n" )
           else
@@ -3435,5 +3640,5 @@
         end
       }
-      if ! @idx_is_id_act then
+      if ! @b_need_ptab then
         fs.each{ |r, f| f.print( "};\n\n" ) }
       end
@@ -3450,5 +3655,5 @@
           fs.each{ |r, f| f.print "struct tag_#{@global_name}_CB #{@global_name}_SINGLE_CELL_CB = \n" }
           indent = 0
-        elsif ! @idx_is_id_act then
+        elsif ! @b_need_ptab then
           fs.each{ |r, f| f.print "struct tag_#{@global_name}_CB #{@global_name}_CB_tab[] = {\n" }
           indent = 1
@@ -3471,5 +3676,5 @@
 
           print_indent( f, indent )
-          if @idx_is_id_act then
+          if @b_need_ptab then
             f.print "#{@global_name}_CB #{name_array[2]} = "
           end
@@ -3493,5 +3698,5 @@
           unless @singleton then
             # 1 つの cell CB の終わり
-            if @idx_is_id_act then
+            if @b_need_ptab then
               f.print( "};\n\n" )
             else
@@ -3500,5 +3705,5 @@
           end
         }
-        if ! @idx_is_id_act then
+        if ! @b_need_ptab then
           fs.each{ |r, f| f.print( "};\n\n" ) }
         end
@@ -3507,5 +3712,5 @@
           fs.each{ |r, f| f.print "struct tag_#{@global_name}_CB #{@global_name}_SINGLE_CELL_CB;\n" }
           indent = 0
-        elsif @idx_is_id_act then
+        elsif @b_need_ptab then
           @ordered_cell_list.each{ |c|
             next if ! c.is_generate?
@@ -3526,5 +3731,5 @@
   def gen_cell_cb_tab f
     indent = 0
-    if @idx_is_id_act then
+    if @b_need_ptab then
       if has_INIB? && ( $ram_initializer || ! has_CB? ) then
         f.print "/* ID to INIB table #_INTAB_# */\n"
@@ -3537,5 +3742,5 @@
         }
 
-        f.print "#{@global_name}_INIB *#{@global_name}_INIB_tab[] ={\n"
+        f.print "#{@global_name}_INIB *const #{@global_name}_INIB_ptab[] ={\n"
         @ordered_cell_list.each{ |c|
           if c.is_generate? then                           # 生成対象か？
@@ -3557,5 +3762,5 @@
         }
 
-        f.print "#{@global_name}_CB *#{@global_name}_CB_tab[] ={\n"
+        f.print "#{@global_name}_CB *const #{@global_name}_CB_ptab[] ={\n"
         @ordered_cell_list.each{ |c|
           if c.is_generate? then                           # 生成対象か？
@@ -3598,5 +3803,5 @@
       cell_ID = 0
     else
-      if ! @idx_is_id_act then
+      if ! @b_need_ptab then
         index = cell.get_id - cell.get_celltype.get_id_base
         cell_CB_name = "#{@global_name}_CB_tab[#{index}]"
@@ -3614,9 +3819,4 @@
       cell_ID = cell.get_id
     end
-    if @idx_is_id_act then
-      cell_IDX = cell_ID
-    else
-      cell_IDX = "&#{cell_CB_name}"
-    end
 
     if has_CB? then
@@ -3626,4 +3826,10 @@
     else
       cell_CBP = "NULL"    # CB も INIB もなければ NULL に置換
+    end
+
+    if @idx_is_id_act then
+      cell_IDX = cell_ID
+    else
+      cell_IDX = cell_CBP
     end
 
@@ -3825,6 +4031,6 @@
               c = j.get_rhs_cell                    # 呼び先セル
               ct = c.get_celltype                   # 呼び先セルタイプ
+              name_array = ct.get_name_array( c )   # 呼び先セルタイプで name_array を得る
               if ct.has_INIB? || ct.has_CB? then
-                name_array = ct.get_name_array( c )   # 呼び先セルタイプで name_array を得る
                 f.printf( "%-40s /* %s #_CCP2_# */\n", "#{name_array[7]},", p.get_name )
               else
@@ -4112,6 +4318,7 @@
       f = fs[ c.get_region.get_domain_root ]
 
-      ct = c.get_celltype
+      ct = c.get_celltype     # ct = self でも同じ
       jl = c.get_join_list
+      name_array = get_name_array( c )
 
       port = ct.get_port_list
@@ -4148,16 +4355,18 @@
               else
                 if has_CB? then
-                  if @singleton then
-                    f.print "    &#{@global_name}_SINGLE_CELL_CB,        /* CB */\n"
-                  else
-                    # f.print "    &#{@global_name}_#{c.get_name}_CB,\n"
-                    f.print "    &#{@global_name}_CB_tab[#{index}],      /* CB */\n"
-                  end
+                  # if @singleton then
+                  #   f.print "    &#{@global_name}_SINGLE_CELL_CB,        /* CB 1 */\n"
+                  # else
+                  #   # f.print "    &#{@global_name}_#{c.get_name}_CB,\n"
+                  #   f.print "    &#{@global_name}_CB_tab[#{index}],      /* CB 2 */\n"
+                  # end
+                  f.print "    #{name_array[8]},      /* CB 1 */\n"
                 elsif has_INIB? then
-                  if @singleton then
-                    f.print "    &#{@global_name}_SINGLE_CELL_INIB,      /* INIB */\n"
-                  else
-                    f.print "    &#{@global_name}_INIB_tab[#{index}],    /* INIB */\n"
-                  end
+                  # if @singleton then
+                  #   f.print "    &#{@global_name}_SINGLE_CELL_INIB,      /* INIB 1 */\n"
+                  # else
+                  #   f.print "    &#{@global_name}_INIB_tab[#{index}],    /* INIB 2 */\n"
+                  # end
+                  f.print "    &#{name_array[5]},      /* INIB 1 */\n"
                 else
                   f.print "    0,\n"
@@ -4183,16 +4392,18 @@
             else
               if has_CB? then
-                if @singleton then
-                  f.print "    &#{@global_name}_SINGLE_CELL_CB,       /* CB */\n"
-                else
-                  f.print "    &#{@global_name}_CB_tab[#{index}],     /* CB */\n"
-                  # f.print "    &#{@global_name}_#{c.get_name}_CB,\n"
-                end
+                # if @singleton then
+                #   f.print "    &#{@global_name}_SINGLE_CELL_CB,       /* CB 3 */\n"
+                # else
+                #   f.print "    &#{@global_name}_CB_tab[#{index}],     /* CB 4 */\n"
+                #   # f.print "    &#{@global_name}_#{c.get_name}_CB,\n"
+                # end
+                f.print "    #{name_array[8]},      /* CB 3 */\n"
               elsif has_INIB? then
-                if @singleton then
-                  f.print "    &#{@global_name}_SINGLE_CELL_INIB,     /* INIB */\n"
-                else
-                  f.print "    &#{@global_name}_INIB_tab[#{index}],   /* INIB */\n"
-                end
+                # if @singleton then
+                #   f.print "    &#{@global_name}_SINGLE_CELL_INIB,     /* INIB 3 */\n"
+                # else
+                #   # f.print "    &#{@global_name}_INIB_tab[#{index}],   /* INIB 4 */\n"
+                # end
+                f.print "    &#{name_array[5]},      /* INIB 3 */\n"
               else
                 f.print "    0,\n"
@@ -4555,4 +4766,5 @@
   def generate_inline_template_code
     return if @n_entry_port_inline == 0
+    return if @b_reuse && ! $generate_all_template
     if ! ( @plugin && @plugin.gen_ep_func? ) then
       return if @b_reuse && ! $generate_all_template
@@ -4932,13 +5144,13 @@
   #  str に以下の置換を行う
   #-   $ct$ ⇒ セルタイプ名(ct)
-  #-   $cell$ ⇒ セル名(cell)   cell が nil ならば3つの置換は行われない
+  #-   $cell$ ⇒ セル名(cell)   cell が nil ならば以下の置換は行われない
   #-   $cb$ ⇒ CB の C 言語名(cb)
   #-   $cbp$ ⇒ CB へのポインタ(cbp)
   #-   $cb_proto$ ⇒ CB の C 言語名プロトタイプ宣言用(cb_proto)
-  #-   $id$ ⇒ ct_cell
+  #-   $id$ ⇒ $ct$_$cell_global$    # ct_cell  before or same V1.5.2
   #-   $idx$ ⇒ idx
   #-   $ID$ ⇒ id (整数の番号)
   #-   $ct_global$ ⇒ セルタイプ名(ct)
-  #-   $cell_global$ ⇒ セル名(cell)   cell が nil ならば3つの置換は行われない
+  #-   $cell_global$ ⇒ セル名(cell)
   #-   $$   ⇒ $
   def subst_name( str, name_array )
@@ -4955,13 +5167,14 @@
 
     str = str.gsub( /(^|[^\$])\$ct\$/, "\\1#{ct}" )
+    str = str.gsub( /(^|[^\$])\$ct_global\$/, "\\1#{ct_global}" )
     if cell then
       str = str.gsub( /(^|[^\$])\$cell\$/, "\\1#{cell}" )
       str = str.gsub( /(^|[^\$])\$cb\$/, "\\1#{cb}" )
-      str = str.gsub( /(^|[^\$])\$id\$/, "\\1#{ct}_#{cell}" )
+      # str = str.gsub( /(^|[^\$])\$id\$/, "\\1#{ct}_#{cell}" )
+      str = str.gsub( /(^|[^\$])\$id\$/, "\\1#{ct}_#{cell_global}" )
       str = str.gsub( /(^|[^\$])\$cb_proto\$/, "\\1#{cb_proto}" )
       str = str.gsub( /(^|[^\$])\$ID\$/, "\\1#{id}" )
       str = str.gsub( /(^|[^\$])\$idx\$/, "\\1#{idx}" )
       str = str.gsub( /(^|[^\$])\$cbp\$/, "\\1#{cbp}" )
-      str = str.gsub( /(^|[^\$])\$ct_global\$/, "\\1#{ct_global}" )
       str = str.gsub( /(^|[^\$])\$cell_global\$/, "\\1#{cell_global}" )
     end
@@ -5083,2 +5296,9 @@
   end
 end
+
+class DomainType < Node
+  def gen_factory
+    # p "DomainType: gen_factory"
+    @plugin.gen_factory
+  end
+end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/location.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/location.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/location.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/messages.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/messages.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/messages.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/optimize.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/optimize.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/optimize.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -178,4 +178,5 @@
 
   def set_domain
+    domain_cells = {}
     @cell_list.each{ |c|
       if c.is_generate? then
@@ -191,4 +192,9 @@
           @domain_roots[ dn ] = [ dr ]
         end
+        if domain_cells[ dr ]  then
+          domain_cells[ dr ] << c
+        else
+          domain_cells[ dr ] = [ c ]
+        end
       end
     }
@@ -196,10 +202,21 @@
     @domain_roots.each{ |dn, drs|
       drs.uniq!
-      if ! $debug then
-        dbgPrint "domains celltype:#{@name} domain=#{dn} "
+      if $verbose && dn then
+        print "[domain] celltype=#{@name} domainType=#{dn} domainRootRegions={"
+        delim = ""
         drs.each{ |r|
-          dbgPrint " region=#{r.get_name}"
+          print delim, r.get_name
+          delim = ", "
         }
-        dbgPrint "\n"
+        print "}\n"
+        drs.each{ |r|
+          print "[domain] celltype=#{@name} domainRootRegion=#{r.get_name} domainType=#{dn} domainKind=#{r.get_domain_root.get_domain_type.get_kind} domainCells={"
+          delim = ""
+          domain_cells[r].each{ |c|
+            print delim, c.get_name
+            delim = ", "
+          }
+          print "}\n"
+        }
       end
     }
@@ -212,9 +229,12 @@
       # domain_type は一つのノードに一つしかないので、一つの要素を無条件で取り出す
       if regions.length > 1 then
-        cdl_info( "I9999 celltype:#{@name} has cells in multi domain.\n" )
-        if @idx_is_id == false then
-          cdl_info( "I9999 celltype:#{@name} forcely set idx_is_id\n" )
-        end
-        @idx_is_id_act = true
+        if $verbose then
+          cdl_info( "I9999 celltype '$1' has cells in multi-domain.\n", @name )
+        end
+        # if @idx_is_id == false then
+        #   cdl_info( "I9999 celltype '$1' forcely set idx_is_id\n", @name )
+        # end
+        @b_need_ptab = true
+        # @idx_is_id_act = true
       end
     }
@@ -228,4 +248,12 @@
     end
 
+    optimize_call
+    if $unopt_entry == false then
+      optimize_entry
+    end
+  end
+
+  #=== Celltype#呼び口最適化
+  def optimize_call
     @port.each{ |port|
       next if port.get_port_type != :CALL
@@ -361,5 +389,9 @@
       dbgPrint "#{port.get_name} : # of cells : #{port_cells.length}  # of ports : #{port_ports.length}\n"
     }
-
+  end
+
+  #=== Celltype#受け口最適化
+  # optimize_entry は、呼び口最適化の結果を使用している
+  def optimize_entry
     # 受け口最適化の設定
     @port.each{ |port|
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/plugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/plugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/plugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -160,5 +160,5 @@
       #  識別子取得
       if arg =~ /\A[a-zA-Z_]\w*/ then
-        ident = $~
+        ident = $~.to_s    # 
         arg = $'
       else
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/pluginModule.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/pluginModule.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/pluginModule.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/syntaxobj.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/syntaxobj.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/syntaxobj.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2016 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -685,4 +685,11 @@
   end
 
+  #=== Decl# print_flowinfo
+  def print_flowinfo file
+    if @kind == :VAR then
+      file.write "#{@identifier} "
+    end
+  end
+
   def show_tree( indent )
     indent.times { print "  " }
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tecsgen.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tecsgen.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tecsgen.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -250,4 +250,8 @@
     Cell.create_reverse_join
 
+    DescriptorType.check_signature
+    Signature.set_descriptor_list
+    Celltype.check_dynamic_join
+
     #0 set_definition_join は2回呼び出される（1回目）
     dbgPrint( "## Checking all join\n")
@@ -450,4 +454,68 @@
   end # finalize
 
+  def dump_tecsgen_rbdmp
+    dbgPrint "dump_tecsgen_rbdmp 0:\n"
+    #### unjoin_plugin 後に行う必要があるため、コード生成後にダンプを行う
+    #### Region link root ごとにオプティマイズしてダンプ ####
+    Namespace.get_root.unjoin_plugin
+    Namespace.get_root.find_plugin 0, []
+
+    Region.get_link_roots.each { |region|
+      dbgPrint "dump_tecsgen_rbdmp 1: Region.path_str: #{region.get_namespace_path.get_path_str}\n"
+
+      n_cells = region.get_n_cells
+
+      if $region_list.length > 0 then
+        if $region_list[ region.get_namespace_path.get_path_str ] == false then
+          $region_list[ region.get_namespace_path.get_path_str ] = true
+        else
+          next
+        end
+      end
+
+      dbgPrint "dump_tecsgen_rbdmp 2: Region.path_str: #{region.get_namespace_path.get_path_str}\n"
+      # セルが一つもなければ生成しない
+      # セルの生成がない場合
+      if region.get_n_cells == 0 then
+        # if $region_list.length > 0 then
+        #   Generator.warning( "W9999 $1: specified to generate but has no cell", region.get_name )
+        # end
+        if region != @root_namespace then
+          next
+        end
+      end
+
+      dbgPrint "dump_tecsgen_rbdmp 3: Region.path_str: #{region.get_namespace_path.get_path_str}\n"
+      $generating_region = region
+      if Region.get_link_roots.length > 1 then
+        if region.get_name == "::" then
+          $gen = $gen_base
+        else
+          $gen = $gen_base + "/" + region.get_global_name.to_s
+        end
+      else
+        $gen = $gen_base
+      end
+
+      dbgPrint "dump_tecsgen_rbdmp 4: Region.path_str: #{region.get_namespace_path.get_path_str}\n"
+      dbgPrint( "## Unset optimize variables\n")
+      @root_namespace.reset_optimize   # 最適化をリセットする
+
+      #  if Generator.get_n_error == 0 then
+      #   # エラーが発生していたら、ここへは来ない
+         dbgPrint( "## Set cell id\n")
+        @root_namespace.set_cell_id_and_domain      # セルの ID とドメイン情報を設定（linkunit 毎に0からつける）
+
+        # エラーが発生していたら、最適化は実施しない
+        if ! $unopt then
+          dbgPrint( "## Optimizing: Link Region=#{@root_namespace.get_name}\n")
+          @root_namespace.optimize
+        end
+      # end
+      dbgPrint "dump_tecsgen_rbdmp final: Region.path_str: #{region.get_namespace_path.get_path_str}\n"
+      File.write( "#{$gen}/tecsgen.rbdmp", Marshal.dump(Namespace.get_root) )
+    }
+  end
+  
   def self.post_coded?
     @@b_post_coded
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tecsinfo.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tecsinfo.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tecsinfo.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2017 by TOPPERS Project
+#   Copyright (C) 2017-2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -49,5 +49,7 @@
 #{indent0}region rTECSInfo {
 EOT
-    # mikan 全部生成するのではなく、region 下のセルのセルタイプと、そこから参照されるシグニチャ、セルタイプに限定して出力する．
+    Type.reset_print_info
+
+    # mikan 全部生成するのではなく、region 下のセルのセルタイプと、そこから参照されるシグニチャ、セルタイプに限定して出力すべき
     # しかし、意味解析後に出力するため、これは容易ではない．最適化とコード生成は、リンクルートごとに行われる．
     Namespace.print_info f, indent
@@ -149,4 +151,7 @@
                  "#{tag.get_ID_str}_#{decl.get_name}",
                  "(uint32_t)(intptr_t)&(((#{tag.get_type_str}#{tag.get_type_str_post}*)0)->#{decl.get_name})"
+        f.printf "#define PLACE_OF_%-30s  (%s)\n",
+                 "#{tag.get_ID_str}_#{decl.get_name}",
+                 "VARDECL_PLACE_STRUCT"
       }
     }
@@ -213,4 +218,5 @@
       name = @global_name
     end
+    # p "region:#{get_name}"
     f.print "\n#{indent}/*** #{get_namespace_path} region information cell ***/\n"
     f.print <<EOT
@@ -219,11 +225,20 @@
 EOT
     @cell_list.each{ |cell|
-      if cell.get_global_name != :rTECSInfo_TECSInfoSub then
+        # print "cell class="+cell.get_celltype.class.name+", " + cell.get_celltype.get_name.to_s + " 1\n"
+      if ! cell.exclude_info? then
+        # print "cell class="+cell.get_celltype.class.name+", " + cell.get_celltype.get_name.to_s + " 2\n"
         f.print "#{indent}    cCellInfo[] = #{cell.get_global_name}CellInfo.eCellInfo;\n"
       end
+    }
+    @namespace_list.each { |region|
+      if region.instance_of? Region then
+        f.print "#{indent}    cRegionInfo[] = #{region.get_global_name}RegionInfo.eRegionInfo;\n"
+       end
     }
     f.print "#{indent}};\n"
     @cell_list.each{ |cell|
-      cell.print_info f, indent
+      if ! cell.exclude_info? then
+        cell.print_info f, indent
+      end
     }
   end
@@ -256,4 +271,5 @@
     ct_list = {}
     @cell_list.each{ |cell|
+      next if cell.exclude_info_factory?
       ct_list[ cell.get_celltype ] = true
     }
@@ -264,9 +280,12 @@
     f.print "\n"
     @cell_list.each{ |cell|
+      next if cell.exclude_info_factory?
       name_array = cell.get_celltype.get_name_array cell
       if cell.get_celltype.has_CB?
         cb = "(void*)#{name_array[8]}"
+        cb_proto = "extern #{cell.get_celltype.get_global_name}_CB #{name_array[4]};\n"
       else
         cb = "0"
+        cb_proto = ""
       end
       if cell.get_celltype.has_INIB?
@@ -277,7 +296,7 @@
         inib_proto = ""
       end
-      if cell.get_global_name != :rTECSInfo_TECSInfoSub then
+      if ! cell.exclude_info_factory? then
         f.print <<EOT
-#define  #{cell.get_global_name}__CBP   #{cb}
+#{cb_proto}#define  #{cell.get_global_name}__CBP   #{cb}
 #{inib_proto}#define  #{cell.get_global_name}__INIBP #{inib}
 EOT
@@ -287,4 +306,31 @@
       if region.instance_of? Region then
         region.print_cell_define f
+      end
+    }
+  end
+
+  def print_entry_descriptor_define f
+    @cell_list.each{ |cell|
+      next if cell.exclude_info_factory?
+
+      signatures = {}
+      cell.get_celltype.get_port_list.each{ |port|
+        next if port.get_port_type != :ENTRY
+
+        if signatures[ port.get_signature ] == nil then
+          f.print "#include \"#{port.get_signature.get_global_name}_tecsgen.h\"\n"
+        end
+        if cell.get_celltype.get_global_name == :nTECSInfo_tRawEntryDescriptorInfo then
+          f.print "const struct tag_#{cell.get_celltype.get_global_name}_#{port.get_name}_DES "
+          f.print "#{cell.get_global_name}_#{port.get_name}_des;\n"
+        else
+          f.print "extern struct tag_#{port.get_signature.get_global_name}_VDES "
+          f.print "#{cell.get_global_name}_#{port.get_name}_des;\n"
+        end
+      }
+    }
+    @namespace_list.each { |region|
+      if region.instance_of? Region then
+        region.print_entry_descriptor_define f
       end
     }
@@ -342,8 +388,8 @@
     }
     @attribute.each{ |decl|
-      decl.print_info f, @global_name, indent
+      decl.print_info f, @global_name, indent, :DECLTYPE_ATTR
     }
     @var.each{ |decl|
-      decl.print_info f, @global_name, indent
+      decl.print_info f, @global_name, indent, :DECLTYPE_VAR
     }
   end
@@ -364,16 +410,21 @@
         if ! decl.is_omit? then
           offset = "(uint32_t)(intptr_t)&(((#{@global_name}_#{inib_cb}*)0)->#{decl.get_name})"
+          place = inib_cb
         else
           offset = "0xffffffff"
+          place = "NON"
         end
         f.printf "#define OFFSET_OF_%-30s  (%s)\n", "#{@global_name}_#{decl.get_name}", offset
+        f.printf "#define PLACE_OF_%-30s  VARDECL_PLACE_%s\n", "#{@global_name}_#{decl.get_name}", place
       }
       @var.each{ |decl|
-        if decl.get_size_is then
+        if decl.get_size_is && has_INIB? then
           inib_cb = "INIB"
         else
           inib_cb = "CB"
         end
-          f.printf "#define OFFSET_OF_%-30s  (%s)\n", "#{@global_name}_#{decl.get_name}", "(uint32_t)(intptr_t)&(((#{@global_name}_#{inib_cb}*)0)->#{decl.get_name})"
+        place = inib_cb
+        f.printf "#define OFFSET_OF_%-30s  (%s)\n", "#{@global_name}_#{decl.get_name}", "(uint32_t)(intptr_t)&(((#{@global_name}_#{inib_cb}*)0)->#{decl.get_name})"
+        f.printf "#define PLACE_OF_%-30s  VARDECL_PLACE_%s\n", "#{@global_name}_#{decl.get_name}", place
       }
     else
@@ -385,7 +436,9 @@
       @attribute.each{ |decl|
         f.printf "#define OFFSET_OF_%-30s  (%s)\n", "#{@global_name}_#{decl.get_name}", "0xffffffff"
+        f.printf "#define PLACE_OF_%-30s   VARDECL_PLACE_NON\n", "#{@global_name}_#{decl.get_name}"
       }
       @var.each{ |decl|
         f.printf "#define OFFSET_OF_%-30s  (%s)\n", "#{@global_name}_#{decl.get_name}", "0xffffffff"
+        f.printf "#define PLACE_OF_%-30s   VARDECL_PLACE_NON\n", "#{@global_name}_#{decl.get_name}"
       }
     end
@@ -404,9 +457,16 @@
     end
 
-    f.printf "\n#include \"#{@global_name}_tecsgen.h\"\n"
-    f.printf "#define %-50s (#{@idx_is_id_act})\n",     "#{@global_name}__IDX_is_ID_act"
-    f.printf "#define %-50s (#{size_CB})\n",            "#{@global_name}__sizeOfCB"
-    f.printf "#define %-50s (#{size_INIB})\n",          "#{@global_name}__sizeOfINIB"
-    f.printf "#define %-30s (%d)\n", "#{@global_name}__NCELLINLINKUNIT", @n_cell_gen
+    if @n_cell_gen > 0 then
+      f.printf "\n#include \"#{@global_name}_tecsgen.h\"\n"
+      f.printf "#define %-50s (#{@idx_is_id_act})\n",     "#{@global_name}__IDX_is_ID_act"
+      f.printf "#define %-50s (#{size_CB})\n",            "#{@global_name}__sizeOfCB"
+      f.printf "#define %-50s (#{size_INIB})\n",          "#{@global_name}__sizeOfINIB"
+      f.printf "#define %-30s (%d)\n", "#{@global_name}__NCELLINLINKUNIT", @n_cell_gen
+    else
+      f.printf "#define %-50s (false)\n",                 "#{@global_name}__IDX_is_ID_act"
+      f.printf "#define %-50s (0)\n",                     "#{@global_name}__sizeOfCB"
+      f.printf "#define %-50s (0)\n",                     "#{@global_name}__sizeOfINIB"
+      f.printf "#define %-30s (%d)\n", "#{@global_name}__NCELLINLINKUNIT", @n_cell_gen
+    end
   end
 
@@ -446,5 +506,5 @@
         end
       end
-      if ( port.is_VMT_useless? && port.is_cell_unique? ) || @n_cell_gen == 0 then
+      if ( port.is_VMT_useless? && port.is_cell_unique? ) || port.is_omit? || @n_cell_gen == 0 then
         offset = "0xffffffff"
       else
@@ -525,5 +585,5 @@
 class Cell
   def print_info f, indent
-    if @global_name == :rTECSInfo_TECSInfoSub then
+    if exclude_info? then
       return
     end
@@ -536,6 +596,67 @@
 #{indent}    inibp           = C_EXP( \"#{@global_name}__INIBP\" );
 #{indent}    cCelltypeInfo   = #{@celltype.get_global_name}CelltypeInfo.eCelltypeInfo;
-#{indent}};
-EOT
+EOT
+    @celltype.get_port_list.each{ |port|
+      next if port.get_port_type != :ENTRY
+
+      f.print <<EOT
+#{indent}    cRawEntryDescriptor[] = #{@global_name}_#{port.get_name}RawEntryDescriptorInfo.eRawEntryDescriptor;
+EOT
+    }
+    f.print "#{indent}};\n"
+
+    # RawEntryDescriptorInfo cells
+    @celltype.get_port_list.each{ |port|
+      next if port.get_port_type != :ENTRY
+
+      size = port.get_array_size
+      if size == nil then
+        size = 1
+      elsif size == "[]" then
+        size = @entry_array_max_subscript[ port ]
+      end
+      if ! port.is_omit? then
+        red = "C_EXP( \"&#{@global_name}_#{port.get_name}_des\" )"
+      else
+        red = "(void *)0"
+      end
+      # mikan 受け口配列
+      f.print <<EOT
+#{indent}cell nTECSInfo::tRawEntryDescriptorInfo #{@global_name}_#{port.get_name}RawEntryDescriptorInfo {
+#{indent}   size = #{size};
+#{indent}   rawEntryDescriptor = { #{red} };
+EOT
+#  #{indent}   cEntryInfo = #{@celltype.get_global_name}_#{port.get_name}EntryInfo.eEntryInfo;
+      f.print "#{indent}};\n"
+    }
+  end
+
+  def exclude_info?
+    # print "exclude_info?: name=" + get_name.to_s
+    if @celltype == nil ||
+       is_of_composite? ||
+       @celltype.get_global_name == :nTECSInfo_tTECSInfoSub ||
+       post_code_generated? ||
+       @b_defined == false then
+      # print ": true celltype_is_of_composite=#{is_of_composite?} celltype_name=#{@celltype.get_global_name} celltype.need_generate=#{@celltype.need_generate?}\n"
+      return true
+    else
+      # print ": false\n"
+      return false
+    end
+  end
+
+  def exclude_info_factory?
+    # print "exclude_info_factory?: name=" + get_name.to_s
+    if @celltype == nil ||
+       is_of_composite? ||
+       @celltype.get_global_name == :nTECSInfo_tTECSInfoSub ||
+       ! @celltype.need_generate? then
+      # print ": true celltype_is_of_composite=#{is_of_composite?} celltype_name=#{@celltype.get_global_name} celltype.need_generate=#{@celltype.need_generate?}\n"
+      return true
+    else
+      # print ": false\n"
+      return false
+    end
   end
 end
@@ -569,5 +690,5 @@
     f.print <<EOT
 #{indent}cell nTECSInfo::tFunctionInfo #{sig_name}_#{func_name}FunctionInfo {
-#{indent}    name            = "#{@owner.get_global_name}_#{@name}";
+#{indent}    name            = "#{get_name}";
 #{indent}    bOneway         = #{is_oneway?};
 EOT
@@ -625,5 +746,5 @@
 
 class Decl
-  def print_info f, parent_ID_str, indent
+  def print_info f, parent_ID_str, indent, decl_type
     if @size_is then
       size = "\"mikan\"";
@@ -635,6 +756,7 @@
 #{indent}    name            = "#{get_name}";
 #{indent}    sizeIsExpr      = #{size};
-#{indent}    declType        = DECLTYPE_STMEMBER;
+#{indent}    declType        = #{decl_type};
 #{indent}    offset          = C_EXP( "OFFSET_OF_#{parent_ID_str}_#{get_name}" );
+#{indent}    place           = C_EXP( "PLACE_OF_#{parent_ID_str}_#{get_name}" );
 #{indent}    cTypeInfo       = #{get_type.get_ID_str}TypeInfo.eTypeInfo;
 #{indent}};
@@ -646,4 +768,9 @@
 class Type
   @@typeinfo_printed = {}
+
+  def self.reset_print_info
+    @@typeinfo_printed = {}
+  end
+
   def print_info f, indent
     # Type の info は、最後にまとめて出力するので、ここでは記録するだけ
@@ -661,5 +788,5 @@
     elsif self.kind_of? StructType then
       get_members_decl.get_items.each{ |decl|
-        decl.get_type.print_info f, indent
+        decl.print_info f, get_ID_str, indent, :DECLTYPE_STMEMBER
       }
     end
@@ -673,8 +800,4 @@
 
   def print_info_post f, indent
-    bit_size = get_bit_size
-    if bit_size <= 0 then
-      bit_size = "C_EXP( \"sizeof(#{get_type_str}#{get_type_str_post})\" )"
-    end
     if self.class.superclass == Type then     # 親クラスが Type の場合 types.rb のクラス
       type_name = self.class.name
@@ -689,17 +812,17 @@
 #{indent}    name           = "#{get_type_str}#{get_type_str_post}";
 #{indent}    typeKind       = TECSTypeKind_#{type_name};
-#{indent}    size           = #{bit_size};
+#{indent}    size           = C_EXP( "sizeof(#{get_type_str}#{get_type_str_post})" );
 #{indent}    b_const        = #{is_const?};
 #{indent}    b_volatile     = #{is_volatile?};
 EOT
     if self.kind_of? PtrType then
-      f.print "#{indent}    cTypeInfo      = #{get_referto.get_ID_str}TypeInfo.eTypeInfo;\n"
+      f.print "#{indent}    cTypeInfo        = #{get_referto.get_ID_str}TypeInfo.eTypeInfo;\n"
     elsif self.kind_of? ArrayType then
-      f.print "#{indent}    cTypeInfo      = #{get_type.get_ID_str}TypeInfo.eTypeInfo;\n"
+      f.print "#{indent}    cTypeInfo        = #{get_type.get_ID_str}TypeInfo.eTypeInfo;\n"
     elsif self.kind_of? DefinedType then
-      f.print "#{indent}    cTypeInfo      = #{get_type.get_ID_str}TypeInfo.eTypeInfo;\n"
+      f.print "#{indent}    cTypeInfo        = #{get_type.get_ID_str}TypeInfo.eTypeInfo;\n"
     elsif self.kind_of? StructType then
       get_members_decl.get_items.each{ |decl|
-        f.print "#{indent}    cTypeInfo[]    = #{decl.get_type.get_ID_str}TypeInfo.eTypeInfo;\n"
+        f.print "#{indent}    cVarDeclInfo[] = #{get_ID_str}_#{decl.get_name}VarDeclInfo.eVarDeclInfo;\n"
       }
     elsif self.kind_of? DescriptorType then
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tool_info.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tool_info.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/tool_info.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/types.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/types.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/types.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #
-#   Copyright (C) 2008-2015 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--  
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -629,5 +629,5 @@
 
 class FloatType < Type
-#  @bit_size::         32, 64, (80), -32, -64
+#  @bit_size::         32, 64, (80), -32, -64, -128
 
   def initialize( bit_size )
@@ -684,4 +684,6 @@
     when -64
       str = "#{str}double"
+    when -128
+      str = "#{str}long double"
     end
     return str
@@ -1558,18 +1560,12 @@
 # 動的結合で渡すデスクリプタ型
 class DescriptorType < Type
-# @sinagure_nsp::NamespacePath
+  # @sinagure_nsp::NamespacePath
+
+  @@descriptors = {}
 
   def initialize( signature_nsp )
-    # p "Desc #{signature_nsp.to_s}"
-    obj = Namespace.find signature_nsp
-    if ! obj.kind_of? Signature then
-      cdl_error( "T9999 '$1': not signature or not found", signature_nsp.to_s )
-      @signature_nsp = signature_nsp
-    else
-      if obj.has_descriptor? then
-       # cdl_error( "T9999 '$1': has Descriptor in function parameter", signature_nsp.to_s )
-      end
-      @signature_nsp = obj.get_namespace_path
-    end
+    @signature_nsp = signature_nsp
+    # check_signature ##
+    @@descriptors[ self ] = false
   end
 
@@ -1595,4 +1591,26 @@
     else
       cdl_error2( locale, "T9999 Descriptor cannot be used for $1", kind)
+    end
+  end
+
+  def self.check_signature
+    @@descriptors.each{ |desc, val|
+      if val != true then
+        desc.check_signature
+        @@descriptors[ desc ] = true
+      end
+    }
+  end
+  
+  def check_signature
+    # p "Desc #{@signature_nsp.to_s}"
+    obj = Namespace.find @signature_nsp
+    if ! obj.kind_of? Signature then
+      cdl_error( "T9999 '$1': not signature or not found", @signature_nsp.to_s )
+    else
+      if obj.has_descriptor? then
+       # cdl_error( "T9999 '$1': has Descriptor in function parameter", @signature_nsp.to_s )
+      end
+      # @signature_nsp = obj.get_namespace_path
     end
   end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/unjoin_plugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/unjoin_plugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/core/unjoin_plugin.rb	(revision 374)
@@ -0,0 +1,234 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2019 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#++
+
+# Marshal.dump ã§ä¸é½åãªäºé 
+ã¸ã®å¯¾ç­
+# Proc ã¯ _dump_data ãå®ç¾©ããã¦ããªããããå®ç¾©ããï¼
+# plugin é¢ä¿ã¯ãtecsflow ã« Plugin ã¯ã©ã¹ãå­å¨ããªããããæ¶ãã¦ããï¼
+
+# Proc ã¯ãMarshal.dump ãããã¨ãã§ããªããã _dump_data ãå®ç¾©
+class Proc
+  def _dump_data
+    nil
+  end
+end
+
+class Object
+  @@visited = {}
+  @@n_visited = 0
+  @@n_found = 0
+  @@n_plugin_proxy = 0
+
+  # do nothing now. this function is used to find remained Proxy object.
+    def find_plugin level, object_list
+
+    # find_plugin_1 level, object_list
+    # print "find_plugin: n_visted=", @@n_visited, " (len=", @@visited.length, ")  found=", @@n_found, "  proxy=", @@n_plugin_proxy, "\n"
+  end
+
+  def find_plugin_1 level, object_list
+    if @@visited[ self ] then
+      return
+    end
+    @@visited[ self ] = true
+    @@n_visited += 1
+
+    if kind_of? Expression then
+      # print   # Expression ã§ã¯ print ãå¥ã«å®ç¾©ããã¦ãã
+      get_elements.each{|ele|
+        ele.find_plugin_1 level+1, object_list
+      }
+      return
+    end
+
+    if level > 100 then    # 100 is enough now, 50 is too small
+      print "reached max level: "
+      if respond_to? :get_name then
+        print "#{get_name}(#{self.class.name})\n"
+      else
+        print "(#{self.class.name})\n"
+      end
+      return
+    end
+
+    object_list.push self                 ##### ãããã return ä¸å¯
+
+    if (kind_of? Plugin) || (kind_of? HRPSVCPlugin) then
+      @@n_found += 1
+      print "Plugin found: #{self.class.name}\n"
+      object_list.each{ |obj|
+        if obj.respond_to? :get_name then
+          print "#{obj.get_name}(#{obj.class.name}), "
+        else
+          print "(#{obj.class.name}), "
+        end
+      }
+      print "\n"
+    elsif kind_of? Join::ThroughPluginProxy then
+      @@n_plugin_proxy += 1
+    end
+
+    level += 1
+    if kind_of? Array then
+      each{ |val|
+        val.find_plugin_1 level, object_list
+      }
+    elsif kind_of? Hash then
+      each{ |key, val|
+        key.find_plugin_1 level, object_list
+        val.find_plugin_1 level, object_list
+      }
+    else
+      instance_variables.each{|iv|
+        iv_val = instance_variable_get iv
+        iv_val.find_plugin_1 level, object_list
+      }
+    end
+    object_list.pop                       ##### ããã¾ã§ return ä¸å¯
+  end
+end
+
+class Namespace
+  def unjoin_plugin
+    @signature_list.each{ |sig| sig.unjoin_plugin }
+    @celltype_list.each{ |ct| ct.unjoin_plugin }
+    @cell_list.each{ |cell| cell.unjoin_plugin }
+    @namespace_list.each{ |ns| ns.unjoin_plugin}
+  end
+end
+
+class Region < Namespace
+  def unjoin_plugin
+    if @domain_type then
+      @domain_type.unjoin_plugin
+    end
+    @cell_port_throug_plugin_list.each{ |key, po|
+      proxy = Join::ThroughPluginProxy.new po.get_cell_namespace_path, po.get_through_entry_port_name, po.get_through_entry_port_subscript
+      @cell_port_throug_plugin_list[ key ] = proxy
+    }
+    super
+  end
+end
+
+class DomainType < Node
+  def unjoin_plugin
+    @plugin = nil
+  end
+end
+
+class Signature < NSBDNode
+  def unjoin_plugin
+    @generate = nil
+  end
+end
+
+class Celltype < NSBDNode
+  def unjoin_plugin
+    @generate = nil
+    @generate_list = []
+    @plugin = nil
+  end
+end
+
+class Cell < NSBDNode
+  def unjoin_plugin
+    @generate = nil
+    @plugin   = nil
+    @join_list.get_items.each{ |j| j.unjoin_plugin }
+  end
+end
+
+class Join < BDNode
+  class ThroughPluginProxy
+    def initialize namespace_path, entry_port_name, entry_port_subscript
+      @namespace_path = namespace_path
+      @entry_port_name = entry_port_name
+      @entry_port_subscript = entry_port_subscript
+    end 
+    def get_cell_namespace_path
+      @namespace_path
+    end
+    def get_through_entry_port_name
+      @entry_port_name
+    end
+    def get_through_entry_port_subscript
+      @entry_port_subscript
+    end
+  end 
+
+  def unjoin_plugin
+    # @thourhg_generated_list is refered in get_rhs_cell, get_rhs_port
+    @through_generated_list.map!{|po| # po: plugin object
+      ThroughPluginProxy.new po.get_cell_namespace_path, po.get_through_entry_port_name, po.get_through_entry_port_subscript
+    }
+    @region_through_generated_list.map!{|po| # po: plugin object
+      ThroughPluginProxy.new po.get_cell_namespace_path, po.get_through_entry_port_name, po.get_through_entry_port_subscript
+    }
+    if @array_member2 then
+      @array_member2.each{ |j| 
+        if j then
+          j.unjoin_plugin2
+        end
+      }
+    end
+  end
+  def unjoin_plugin2
+    @through_generated_list.map!{|po| # po: plugin object
+      ThroughPluginProxy.new po.get_cell_namespace_path, po.get_through_entry_port_name, po.get_through_entry_port_subscript
+    }
+    @region_through_generated_list.map!{|po| # po: plugin object
+      ThroughPluginProxy.new po.get_cell_namespace_path, po.get_through_entry_port_name, po.get_through_entry_port_subscript
+    }
+  end
+end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_console_en_US.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_console_en_US.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_console_en_US.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_console_ja_JP.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_console_ja_JP.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_console_ja_JP.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_file_en_US.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_file_en_US.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_file_en_US.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -76,5 +76,5 @@
 #  * このファイルを編集して使用することが意図されていますが
 #  * tecsgen の再実行により上書きされてしまうため、通常
-#  *   gen/%s_template.c => src/%s.c
+#  *   gen/%s_templ.c => src/%s.c
 #  * のように名前, フォルダを変更してから修正します
 #  */
@@ -83,5 +83,5 @@
  * This file was automatically generated by tecsgen.
  * Move and rename like below before editing,
- *   gen/%s_template.c => src/%s.c
+ *   gen/%s_templ.c => src/%s.c
  * to avoid to be overwritten by tecsgen.
  */
@@ -335,3 +335,8 @@
 @@comment[ :TEFB_comment ] = "\t/* Put statements here %s */\n"
 
+# @@comment[ :MCPP_comment ] = "/* セル CB プロトタイプ宣言 %s */\n"
+@@comment[ :MCPP_comment ] = "/* cell CB prototype declaration %s */\n"
+
+# @@comment[ :MCPB_comment ] = "/* セル CB プロトタイプ宣言 %s */\n"
+@@comment[ :MCPB_comment ] = "/* cell CB prototype declaration %s */\n"
 end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_file_ja_JP.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_file_ja_JP.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/messages/messages_file_ja_JP.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -65,5 +65,5 @@
  * このファイルを編集して使用することが意図されていますが
  * tecsgen の再実行により上書きされてしまうため、通常
- *   gen/%s_template.c => src/%s.c
+ *   gen/%s_templ.c => src/%s.c
  * のように名前, フォルダを変更してから修正します
  */
@@ -163,4 +163,6 @@
 @@comment[ :TEPF_comment ] = "/* 受け口関数 %s */\n"
 @@comment[ :TEFB_comment ] = "\t/* ここに処理本体を記述します %s */\n"
+@@comment[ :MCPP_comment ] = "/* CB プロトタイプ宣言 %s */\n"
+@@comment[ :MCPB_comment ] = "/* CB プロトタイプ宣言 %s */\n"
 
 end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1AlarmPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1AlarmPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1AlarmPlugin.rb	(revision 374)
@@ -35,5 +35,5 @@
 #   の責任を負わない．
 #  
-#   $Id
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1DelayTaskPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1DelayTaskPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1DelayTaskPlugin.rb	(revision 374)
@@ -35,5 +35,5 @@
 #   の責任を負わない．
 #  
-#   $Id
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1ISRPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1ISRPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1ISRPlugin.rb	(revision 374)
@@ -35,5 +35,5 @@
 #   の責任を負わない．
 #  
-#   $Id
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1KernelPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1KernelPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1KernelPlugin.rb	(revision 374)
@@ -35,5 +35,5 @@
 #   の責任を負わない．
 #  
-#   $Id
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1ResourcePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1ResourcePlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1ResourcePlugin.rb	(revision 374)
@@ -35,5 +35,5 @@
 #   の責任を負わない．
 #  
-#   $Id
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1TaskPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1TaskPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ATK1TaskPlugin.rb	(revision 374)
@@ -35,5 +35,5 @@
 #   の責任を負わない．
 #  
-#   $Id
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/DomainPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/DomainPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/DomainPlugin.rb	(revision 374)
@@ -46,4 +46,5 @@
   #option::String : domain 指定子の第二引数
   def initialize( region, domain_type_name, option )
+    super()
   end
 
@@ -77,3 +78,14 @@
     return false
   end
+
+  #== ドメイン種別を返す
+  #return::Symbol :kernel, :user, :OutOfDomain
+  def get_kind
+    :kernel
+  end
+
+  #== factory 生成
+  # DomainPlugin の factory は特定のファイルへの出力が想定されていない
+  def gen_factory
+  end
 end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2Cache.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2Cache.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2Cache.rb	(revision 374)
@@ -1,3 +1,4 @@
 # -*- coding: utf-8 -*-
 
+#   $Id$
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2CyclicHandlerPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2CyclicHandlerPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2CyclicHandlerPlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2012 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2DataqueuePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2DataqueuePlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2DataqueuePlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2012 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2EventflagPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2EventflagPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2EventflagPlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2012 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2FixedSizeMemoryPoolPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2FixedSizeMemoryPoolPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2FixedSizeMemoryPoolPlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2012 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2HandlerPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2HandlerPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2HandlerPlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -77,13 +77,13 @@
         elsif @plugin_arg_str == "ISR"
             file.print <<EOT
-#{tab}ATT_ISR({ #{val[:attribute]}, &#{cell_CB_name}, #{val[:interruptNumber]}, tISR_start, #{val[:priority]} });
+#{tab}ATT_ISR({ #{val[:attribute]}, #{cell_CBP}, #{val[:interruptNumber]}, tISR_start, #{val[:priority]} });
 EOT
         elsif @plugin_arg_str == "INIT_ROUTINE"
             file.print <<EOT
-#{tab}ATT_INI({ #{val[:attribute]}, &#{cell_CB_name}, tInitializeRoutine_start });
+#{tab}ATT_INI({ #{val[:attribute]}, #{cell_CBP}, tInitializeRoutine_start });
 EOT
         elsif @plugin_arg_str == "TERM_ROUTINE"
             file.print <<EOT
-#{tab}ATT_TER({ #{val[:attribute]}, &#{cell_CB_name}, tTerminateRoutine_start });
+#{tab}ATT_TER({ #{val[:attribute]}, #{cell_CBP}, tTerminateRoutine_start });
 EOT
         else
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2KernelObjectPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2KernelObjectPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2KernelObjectPlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2012 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -186,5 +186,5 @@
                 val = {}
                 @celltype.get_attribute_list.each{ |a|
-                    p a.get_name
+                    # p a.get_name
                     if a.get_type.kind_of?( ArrayType )
                         val[a.get_name] = []
@@ -218,5 +218,6 @@
                 if val[:id].nil? != true
                     puts val[:id]
-                    val[:id] = val[:id].gsub( /(^|[^\$])\$id\$/, "\\1#{@celltype.get_name.to_s}_#{cell.get_name.to_s}" )
+                    #val[:id] = val[:id].gsub( /(^|[^\$])\$id\$/, "\\1#{@celltype.get_name.to_s}_#{cell.get_name.to_s}" )
+                    val[:id] = @celltype.subst_name( val[:id], @celltype.get_name_array( cell ) )
                 end
                 # $cbp$の代わり
@@ -244,6 +245,6 @@
                         file2.puts "}\n"
                     else
-                        print "~~~~~ #{cell.get_region.get_name.to_s} is included in"
-                        p @@region_list
+                        dbgPrint "~~~~~ #{cell.get_region.get_name.to_s} is included in"
+                        # p @@region_list
                     end
                     file3 = AppFile.open( "#{$gen}/tecsgen_#{cell_domain_root.get_name.to_s}.cfg" )
@@ -260,6 +261,6 @@
                 if !val[:accessPattern].nil?
                     puts "===== begin check regions #{cell.get_name} ====="
-                    p val[:accessPattern]
-                    p val[:accessPattern].class
+                    # p val[:accessPattern]
+                    # p val[:accessPattern].class
 
                     #ep = [ :eTaskActivate, :eTaskControl, :eTaskManage, :eTaskRefer ]
@@ -273,8 +274,8 @@
                         if acptnx != "OMIT"
                             acv << acptnx
-                            p acv[i]
+                            # p acv[i]
                         elsif cell_domain_type.get_option.to_s == "trusted"
                             acv << "TACP_KERNEL"
-                            p acv[i]
+                            # p acv[i]
                         elsif cell_domain_type.get_option.to_s != "OutOfDomain"
                             acv << "TACP(#{cell_domain_root.get_name.to_s})"
@@ -286,5 +287,5 @@
                     }
 
-                    print "acv = "
+                    dbgPrint "acv = "
                     p acv
 
@@ -322,9 +323,9 @@
 
     def self.check_referenced_cells()
-        puts "===== begin check registered celltype ====="
+        dbgPrint "===== begin check registered celltype =====\n"
         self.get_celltype_list.each { |ct|
-            p ct.get_name.to_s
+            dbgPrint( ct.get_name.to_s + "\n" )
         }
-        puts "===== end check registered celltype ====="
+        dbgPrint "===== end check registered celltype =====\n"
 
 =begin
@@ -334,5 +335,5 @@
                 j = cell.get_join_list.get_item(p.get_name)
                 printf "===== check call port : "
-                p p.get_name.to_s
+                # p p.get_name.to_s
                 next if j.nil? # 未結合の場合
                 if @@celltype_list.include?(j.get_celltype)
@@ -341,7 +342,7 @@
                     j.get_cell.set_referenced_cell(cell, j.get_port_name)
                     printf "===== check joined rhs cell : "
-                    p j.get_cell.get_name.to_s
+                    # p j.get_cell.get_name.to_s
                     printf "===== check joined rhs port_name : "
-                    p j.get_port_name
+                    # p j.get_port_name
                 end
             }
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2ObjectPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2ObjectPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2ObjectPlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2Plugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2Plugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2Plugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2014 by TOPPERS Project
+#   Copyright (C) 2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -44,5 +44,17 @@
 
   def initialize( region, name, option )
+    super
     print "HRP2Plugin: initialize: region=#{region.get_name}, domainName=#{name}, option=#{option}\n"
+    @region = region
+    @name   = name
+
+    case option
+    when "trusted", "nontrusted", "OutOfDomain"
+      # OK
+      @option = option
+    else
+      cdl_error( "HRPPlugin: '$1' is unacceptable domain kind, specify 'trusted' or 'nontrusted'", option )
+      @option = "trusted"   # とりあえず trusted を設定しておく
+    end
   end
 
@@ -108,4 +120,17 @@
   end
 
+  #== ドメイン種別を返す
+  #return::Symbol :kernel, :user, :OutOfDomain
+  def get_kind
+    case @option
+    when "trusted"
+      return :kernel
+    when "nontrusted"
+      return :user
+    when "OutOfDomain"
+      return :OutOfDomain
+    end
+  end
+
   def joinable?(current_region, next_region, through_type )
     print "HRP2Plugin: joinable? from #{current_region.get_name} to #{next_region.get_name} (#{through_type})\n"
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2PostHook.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2PostHook.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2PostHook.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2012 by TOPPERS Project
+#   Copyright (C) 2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2PriorityDataqueuePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2PriorityDataqueuePlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2PriorityDataqueuePlugin.rb	(revision 374)
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2RPCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2RPCPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2RPCPlugin.rb	(revision 374)
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
@@ -70,5 +71,5 @@
   #=== RPCPlugin の initialize
   #  説明は ThroughPlugin (plugin.rb) を参照
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
     super
     @b_noClientSemaphore = false
@@ -234,5 +235,5 @@
     if cell.get_allocator_list.length > 0 then
 
-      dbgPrint "make allocator"
+      dbgPrint "make allocator\n"
       file.print "#{indent_str}[allocator("
 
@@ -269,8 +270,14 @@
     nest = @end_region.gen_region_str_pre file
     indent_str = "  " * nest
+    nest_str = "  " * nest
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     file.print <<EOT
 #{indent_str}cell #{@rpc_channel_celltype_name}Server #{@cell_name}Body {
-#{indent_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name};
+#{indent_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
 //#{indent_str}    #{@call_port_name} = #{@next_cell.get_name}.#{@next_cell_port_name};
 #{indent_str}  //cTDR         = #{@channelCellName}.eTDR;
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2SVCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2SVCPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2SVCPlugin.rb	(revision 374)
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
@@ -83,5 +84,5 @@
   @@generated_celltype_header = {}
 
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
     super
     @ct_name_body = "#{@ct_name}SVCBody_#{@next_cell.get_name}_#{@next_cell_port_name}".to_sym
@@ -217,4 +218,9 @@
     nest = @end_region.gen_region_str_pre file
     nest_str = "  " * nest
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     # サーバー側チャンネルの生成 
@@ -224,5 +230,5 @@
 #{nest_str}  //  Server Side Channel
 #{nest_str}  cell #{@ct_name_body} #{@cell_name_body}{
-#{nest_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name};
+#{nest_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
 #{nest_str}  };
 EOT
@@ -241,4 +247,9 @@
     nest = @start_region.gen_region_str_pre file
     nest_str = "  " * nest
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     # クライアント側チャンネルの生成
@@ -247,5 +258,5 @@
 #{nest_str}  //  Client Side Channel
 #{nest_str}  cell #{@ct_name} #{@cell_name}{
-#{nest_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name};
+#{nest_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
 #{nest_str}  };
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2SemaphorePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2SemaphorePlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2SemaphorePlugin.rb	(revision 374)
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2TaskPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2TaskPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRP2TaskPlugin.rb	(revision 374)
@@ -53,5 +53,6 @@
     # tab  : 
     def print_cfg_cre(file, cell, val, tab)
-        val[:id] = val[:id].gsub( /(^|[^\$])\$id\$/, "\\1#{@celltype.get_name.to_s}_#{cell.get_name.to_s}" )
+        #val[:id] = val[:id].gsub( /(^|[^\$])\$id\$/, "\\1#{@celltype.get_name.to_s}_#{cell.get_global_name.to_s}" )
+        #val[:id] = @celltype.subst_name( val[:id], @celltype.get_name_array( cell ) )
         # $cbp$の代わり
         index = cell.get_id - @celltype.get_id_base
@@ -59,7 +60,8 @@
         cell_CB_name = "#{index}"
         # CRE_XXX/DEF_XXXの生成
-        print "assign task plugin\n"
+        dbgPrint "assign task plugin\n"
         domainOption = cell.get_region.get_domain_root.get_domain_type.get_option
         # if cell.get_region.get_region_type == :DOMAIN
+# cell.show_tree 1
         if domainOption != "OutOfDomain"
             # 保護ドメインに属する場合
@@ -69,4 +71,5 @@
                     raise "system task cannot have user stack."
                 end
+p "CRE_TSK 0 user=#{val[:userStackSize]} system=#{val[:systemStackSize]}"
                 file.print <<EOT
 #{tab}CRE_TSK(#{val[:id]}, { #{val[:taskAttribute]}, #{cell_CB_name}, tTask_start_task, #{val[:priority]}, #{val[:systemStackSize]}, NULL });
@@ -77,4 +80,5 @@
                     raise "user task must have user stack."
                 end
+p "CRE_TSK 1"
                 if val[:systemStackSize] == "OMIT"
                     file.print <<EOT
@@ -82,4 +86,5 @@
 EOT
                 else
+p "CRE_TSK 2"
                     file.print <<EOT
 #{tab}CRE_TSK(#{val[:id]}, { #{val[:taskAttribute]}, #{cell_CB_name}, tTask_start_task, #{val[:priority]}, #{val[:userStackSize]}, NULL, #{val[:systemStackSize]}, NULL });
@@ -138,7 +143,7 @@
                     regions = ct.get_domain_roots
                     regions_hrp2 = regions[ :HRP2 ]
-                    print "HRP2 domain in #{ct.get_name}: "
+                    dbgPrint "HRP2 domain in #{ct.get_name}: "
                     regions_hrp2.each { |reg|
-                        print reg.get_name
+                        dbgPrint reg.get_name
                     }
                     puts ""
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPHandlerPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPHandlerPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPHandlerPlugin.rb	(revision 374)
@@ -0,0 +1,145 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#++
+
+require_tecsgen_lib "HRPKernelObjectPlugin.rb"
+
+
+#== celltype ãã©ã°ã¤ã³ã®å
+±éã®è¦ªã¯ã©ã¹
+class HRPHandlerPlugin < HRPKernelObjectPlugin
+
+    ##
+    # oyama: add to avoid Ruby exception in code generation phase.
+    def new_cell cell
+        domainOption = cell.get_region.get_domain_root.get_domain_type.get_option
+        if (domainOption == "OutOfDomain") || (domainOption != "kernel")
+          cdl_error( "HRP9999 HRP handler '$1' must belong to kernel domain", cell.get_name )
+        end
+    end
+
+    ##
+    #
+    # file : output file (ex.tecsgen.cfg)
+    # cell : 
+    # val  : 
+    # tab  : 
+    def print_cfg_cre(file, cell, val, tab)
+        if !val[:id].nil?
+            val[:id] = val[:id].gsub( /(^|[^\$])\$id\$/, "\\1#{@celltype.get_name.to_s}_#{cell.get_name.to_s}" )
+        end
+        # $cbp$ã®ä»£ãã
+        index = cell.get_id - @celltype.get_id_base
+        #cell_CB_name = "#{@celltype.get_global_name}_CB_tab[#{index}]"
+        name_array = cell.get_celltype.get_name_array cell
+        cell_CBP = name_array[8]
+        # CRE_XXXã®çæ
+        domainOption = cell.get_region.get_domain_root.get_domain_type.get_option
+        if (domainOption == "OutOfDomain") || (domainOption != "kernel")
+            # ç¡æå± or ã¦ã¼ã¶ãã¡ã¤ã³ã«å±ããå ´å
+                raise "#{@plugin_arg_str.to_s.downcase} handler #{val[:id]} must belong to kernel domain."
+        elsif @plugin_arg_str == "CONFIG_INT"
+            file.print <<EOT
+#{tab}CFG_INT( #{val[:interruptNumber]}, { #{val[:attribute]}, #{val[:interruptPriority]} });
+EOT
+        elsif @plugin_arg_str == "ISR"
+            file.print <<EOT
+#{tab}CRE_ISR(#{val[:id]}, { #{val[:attribute]}, #{cell_CBP}, #{val[:interruptNumber]}, tISR_start, #{val[:isrPriority]} });
+EOT
+        elsif @plugin_arg_str == "DEF_INH"
+            name_array = @celltype.get_name_array cell
+            start = @celltype.subst_name( "$id$_start", name_array )
+            file.print <<EOT
+#{tab}DEF_INH(#{val[:interruptHandlerNumber]}, { #{val[:attribute]}, #{start} });
+EOT
+        elsif @plugin_arg_str == "DEF_EXC"
+            name_array = @celltype.get_name_array cell
+            start = @celltype.subst_name( "$id$_start", name_array )
+            file.print <<EOT
+#{tab}DEF_EXC(#{val[:cpuExceptionHandlerNumber]}, { #{val[:attribute]}, #{start} });
+EOT
+        elsif @plugin_arg_str == "INIT_ROUTINE"
+            file.print <<EOT
+#{tab}ATT_INI({ #{val[:attribute]}, #{cell_CBP}, tInitializeRoutine_start });
+EOT
+        elsif @plugin_arg_str == "TERM_ROUTINE"
+            file.print <<EOT
+#{tab}ATT_TER({ #{val[:attribute]}, #{cell_CBP}, tTerminateRoutine_start });
+EOT
+        else
+            raise "#{@plugin_arg_str} is unknown option"
+        end
+    end
+
+    def print_cfg_sac(file, val, acv)
+        if @plugin_arg_str == "CONFIG_INT"
+            # nothing to do
+        elsif @plugin_arg_str == "ISR"
+            # kernel.cdl ã® tISR ã§ accessPattern1 ï½ accessPattern4 ãå®ç¾©ããã¦ããã¨ãã®åæ®ã
+            # accessPattern1 ãå®ç¾©ããã¦ããªãå ´åããããã¸ã¯æ¥ãªãï¼å¾©æ´»ããã¨ãã«åãã¦æ®ãã¦ããï¼
+            # file.puts "SAC_#{@plugin_arg_str}(#{val[:id]}, { #{acv[:accessPattern1]}, #{acv[:accessPattern2]}, #{acv[:accessPattern3]}, #{acv[:accessPattern4]} });"
+            puts "*** Unsupported *** SAC_#{@plugin_arg_str}(#{val[:id]}, { #{acv[:accessPattern1]}, #{acv[:accessPattern2]}, #{acv[:accessPattern3]}, #{acv[:accessPattern4]} });\n"
+        elsif @plugin_arg_str == "DEF_INH"
+            # nothing to do
+        elsif @plugin_arg_str == "DEF_EXC"
+            # nothing to do
+        elsif @plugin_arg_str == "INIT_ROUTINE"
+            # nothing to do
+        elsif @plugin_arg_str == "TERM_ROUTINE"
+            # nothing to do
+        else
+            raise "#{@plugin_arg_str} is unknown option"
+        end
+    end
+
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPKernelObjectManager.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPKernelObjectManager.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPKernelObjectManager.rb	(revision 374)
@@ -0,0 +1,86 @@
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2015-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#
+#   $Id$
+#  
+#++
+# This file has been generated by gen_kernel_celltype.py
+class HRPKernelObjectManager
+	@@kernel_objs = [\
+		:tKernel, \
+		:tTask, \
+		:tSemaphore, \
+		:tEventflag, \
+		:tDataqueue, \
+		:tPriorityDataqueue, \
+		:tMutex, \
+		:tFixedSizeMemoryPool, \
+		:tTimeEventHandler, \
+		:tCyclicNotifier, \
+		:tAlarmNotifier, \
+		:tInterruptRequest, \
+		:tISR, \
+		:tInterruptHandler, \
+		:tCpuExceptionHandler, \
+		:tInitializeRoutine, \
+		:tTerminateRoutine, \
+		:tMessageBuffer, \
+	]
+
+    def initialize()
+        # 
+        #  æ¬ã¯ã©ã¹ã¯ã¤ã³ã¹ã¿ã³ã¹ãæããªãä»®æ³çãªã¯ã©ã¹ã§ãã
+        #
+        raise "class #{self.class.name} shall not have instances"
+    end
+    def self.include_celltype?(str)
+        return @@kernel_objs.include?(str)
+    end
+end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPKernelObjectPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPKernelObjectPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPKernelObjectPlugin.rb	(revision 374)
@@ -0,0 +1,364 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#
+#  $Id$
+#++
+
+#== celltype ãã©ã°ã¤ã³ã®å
+±éã®è¦ªã¯ã©ã¹
+class HRPKernelObjectPlugin < CelltypePlugin
+    # @@obj_hash = {}
+
+    #@celltype:: Celltype
+    #@option:: String     :ãªãã·ã§ã³æå­å
+    def initialize( celltype, option )
+        super
+        #
+        #  ããããã®ã«ã¼ãã«ãªãã¸ã§ã¯ããè§£æå¯¾è±¡ã»ã«ã¿ã¤ãã«è¿½å 
+        #  ç®çï¼
+        #   - ã«ã¼ãã«ãªãã¸ã§ã¯ãã®ã»ã«ãã¡ã¢ãªä¿è­·å¯¾è±¡å¤ã¨ãã
+        #    - ã«ã¼ãã«ãªãã¸ã§ã¯ãæ¬ä½ã®ç®¡çã¯TECSã§ãªãOSã§å®æ½ãããã
+        #   - ã«ã¼ãã«ãªãã¸ã§ã¯ãã®ã»ã«ã¸ã®ã¢ã¯ã»ã¹ãç´æ¥é¢æ°å¼åºã
+        #   ãã¨ãã
+        #    - ã·ã¹ãã ãµã¼ãã¹å¼åºãã¯OSãæä¾ãããã
+        HRPKernelObjectPlugin.set_celltype(celltype)
+    end
+  
+    #=== HRPKernelObjectPlugin#print_cfg_cre
+    # åç¨®ã«ã¼ãã«ãªãã¸ã§ã¯ãã®CRE_*ã®åºå
+    # file:: FILE:     åºåå
+ãã¡ã¤ã«
+    # val :: string:   ã«ã¼ãã«ãªãã¸ã§ã¯ãã®å±æ§ã®è§£æçµæ
+    # tab :: string:   ã¤ã³ãã³ãç¨ã®tab
+    def print_cfg_cre(file, cell, val, tab)
+        raise "called virtual method print_cfg_cre in #{@celltype.get_name} plugin"
+    end
+  
+    #=== HRPKernelObjectPlugin#print_cfg_sac
+    # åç¨®ã«ã¼ãã«ãªãã¸ã§ã¯ãã®SAC_*ã®åºå
+    # file:: FILE:     åºåå
+ãã¡ã¤ã«
+    # val :: string:   ã«ã¼ãã«ãªãã¸ã§ã¯ãã®å±æ§ã®è§£æçµæ
+    # acv :: string:   ã¢ã¯ã»ã¹ãã¯ã¿
+    def print_cfg_sac(file, val, acv)
+        raise "called virtual method print_cfg_sac in #{@celltype.get_name} plugin"
+    end
+  
+    #
+    #  ã»ã«ã¿ã¤ããã©ã°ã¤ã³ã®æ¬ä½ã¡ã½ãã
+    #   - éçAPIã®çæ
+    #  file:: FILE:     åºåå
+ãã¡ã¤ã«
+    #
+    def gen_factory file
+        dbgPrint "===== begin #{@celltype.get_name.to_s} plugin =====\n"
+
+        #
+        # å¯¾è±¡ã¨ãªããã¹ã¦ã®ã»ã«ã«ã¤ãã¦ãåãå£ã«çµåããã¦ãã
+        # ã»ã«ã®æå±ãã¡ã¤ã³ãè§£æ
+        #  - çæãã¹ãcfgãã¡ã¤ã«åãåå¾ããããã«å¿
+è¦
+        #
+        if !HRPKernelObjectPlugin.isChecked()
+            HRPKernelObjectPlugin.check_referenced_cells()
+        else
+            dbgPrint "***** already checked\n"
+        end
+
+        # è¿½è¨ããããã« AppFile ãä½¿ãï¼æå­ã³ã¼ãå¤æãããªãï¼
+        file2 = AppFile.open( "#{$gen}/tecsgen.cfg" )
+        file2.print "\n/* Generated by #{self.class.name} */\n\n"
+
+        @celltype.get_cell_list.each { |cell|
+            if cell.is_generate?
+                dbgPrint "===== begin check my domain #{cell.get_name} =====\n"
+                #
+                #  ã«ã¼ãã«ãªãã¸ã§ã¯ãã®å±æ§ãï¼valã«ã³ãã¼
+                #
+                val = {}
+                @celltype.get_attribute_list.each{ |a|
+                    # p a.get_name
+                    if a.get_type.kind_of?( ArrayType )
+                        val[a.get_name] = []
+                        if j = cell.get_join_list.get_item(a.get_name)
+                            # ã»ã«çææã«åæåããå ´å
+                            j.get_rhs.each { |elem|
+                                val[a.get_name] << elem.to_s
+                            }
+                        elsif i = a.get_initializer
+                            # ã»ã«ã¿ã¤ãã®åæåå¤ãä½¿ãå ´å
+                            i.each { |elem|
+                                val[a.get_name] << elem.to_s
+                            }
+                        else
+                            raise "attribute is not initialized"
+                        end
+                    else
+                        if j = cell.get_join_list.get_item(a.get_name)
+                            # ã»ã«çææã«åæåããå ´å
+                            val[a.get_name] = j.get_rhs.to_s
+                        elsif i = a.get_initializer
+                            # ã»ã«ã¿ã¤ãã®åæåå¤ãä½¿ãå ´å
+                            val[a.get_name] = i.to_s
+                        else
+                            raise "attribute is not initialized"
+                        end
+                    end
+                }
+                # generate.rbãåèã«
+                # $id$ãç½®æ
+                if val[:id].nil? != true
+                    name_array = @celltype.get_name_array( cell )
+                    val[:id]   = @celltype.subst_name( val[:id], name_array )
+                end
+                # $cbp$ã®ä»£ãã
+                cell_domain_root = cell.get_region.get_domain_root
+                cell_domain_type = cell.get_region.get_domain_root.get_domain_type
+
+                # CRE_XXX/DEF_XXXã®çæ
+                if cell_domain_type.get_option.to_s != "OutOfDomain"
+                    # ä¿è­·ãã¡ã¤ã³ã«å±ããå ´å
+                    if !HRPKernelObjectPlugin.include_region(cell_domain_root.get_name.to_s)
+                        # ãã®ä¿è­·ãã¡ã¤ã³ã®.cfgãçæããã¦ããªãå ´å
+                        HRPKernelObjectPlugin.set_region_list(cell_domain_root.get_name.to_s)
+                        dbgPrint "~~~~~ #{cell_domain_root.get_name.to_s} is registered!\n"
+
+#                        # if cell.get_region.get_param == :KERNEL_DOMAIN
+#                        if cell_domain_type.get_option.to_s == "kernel"
+#                            file2.print "KERNEL_DOMAIN{\n"
+#                        else
+#                            file2.print "DOMAIN(#{cell_domain_root.get_name.to_s}){\n"
+#                        end
+#                        file2.puts "\tINCLUDE(\"#{$gen}/tecsgen_#{cell_domain_root.get_name.to_s}.cfg\");" 
+#                        file2.puts "}\n"
+                    else
+                        dbgPrint "~~~~~ #{cell.get_region.get_namespace_path} is included in"
+                        #p @@region_list
+                    end
+                    file3 = AppFile.open( "#{$gen}/tecsgen_#{cell_domain_root.get_global_name}.cfg" )
+                    print_cfg_cre(file3, cell, val,"")
+                    file3.close
+                else
+                    # ç¡æå±ã®å ´å
+                    dbgPrint "~~~~~ #{cell_domain_root.get_namespace_path} is OutOfDomain\n"
+                    # print "~~~~~ #{cell_domain_root.get_namespace_path} is OutOfDomain\n"
+                    # p cell_domain_root.get_name
+                    if cell_domain_root.get_name == "::" then
+                      print_cfg_cre(file2, cell, val, "")
+                    else
+#                      if !HRPKernelObjectPlugin.include_region(cell_domain_root.get_name.to_s)
+#                        # ãã®ä¿è­·ãã¡ã¤ã³ã®.cfgãçæããã¦ããªãå ´å
+#                        HRPKernelObjectPlugin.set_region_list(cell_domain_root.get_name.to_s)
+#                        file2.puts "INCLUDE(\"#{$gen}/tecsgen_#{cell_domain_root.get_name.to_s}.cfg\");\n"
+#                      end
+                      file3 = AppFile.open( "#{$gen}/tecsgen_#{cell_domain_root.get_name.to_s}.cfg" )
+                      print_cfg_cre(file3, cell, val,"")
+                      file3.close
+                    end
+
+                end
+
+                dbgPrint "===== end check my domain #{cell.get_name} =====\n"
+
+                #
+                # SAC_XXXã®çæ
+                #
+                if !val[:accessPattern1].nil?
+                    dbgPrint "===== begin check regions #{cell.get_name} =====\n"
+                    i = 0
+                    acv = { \
+                            :accessPattern1 => val[:accessPattern1], \
+                            :accessPattern2 => val[:accessPattern2], \
+                            :accessPattern3 => val[:accessPattern3], \
+                            :accessPattern4 => val[:accessPattern4] \
+                    }
+                    acv_tmp = []
+                    domain_roots = HRPPlugin.get_inter_domain_join_roots cell
+                    # çµåå
+ã»ã«ã®ãã¡ã¤ã³ãå ãã
+                    if cell_domain_type.get_kind != :OutOfDomain then
+                      domain_roots << cell_domain_root
+                    end
+                    domain_roots.each{ |dr|
+                      case dr.get_domain_type.get_kind
+                      when :user
+                        acv_tmp << "TACP(#{dr.get_name})"
+                      when :kernel
+                        acv_tmp << "TACP_KERNEL"
+                      when :OutOfDomain
+                        if cell_domain_type.get_kind == :OutOfDomain then
+                          # å¼ã³å
+ããå¼ã³å
+ã OutOfDomain ã®å ´å
+                          acv_tmp << "TACP_SHARED"
+                        end
+                      end
+                    }
+                    acv_tmp.uniq!
+                    if acv_tmp.length == 0 then
+                      # å¼ã³å
+ã»ã«ãç¡æå±ãã¤ãå¼ã³å
+ãç¡æå±ã®ã¿ãã¾ãã¯çµåç¡ãã®å ´å
+                      acv_tmp = [ "TACP_SHARED" ]
+                    end
+                    b_info = false
+                    b_warn = false
+                    acv.each { |key, acp|
+                        if !acp.nil?
+                            if acp != "OMIT"
+                            elsif cell_domain_type.get_kind != :OutOfDomain
+                              # p "UserDomainCell or KernelDomainCell"
+                              domain_roots = HRPPlugin.get_inter_domain_join_roots cell
+                              domain_roots.each{ |dr|
+                                # 
+                                case dr.get_domain_type.get_kind
+                                when :kernel
+                                when :user
+                                  if dr.get_namespace_path != cell.get_region.get_domain_root.get_namespace_path
+                                    # ä»ã®ã¦ã¼ã¶ã¼ãã¡ã¤ã³ããã®çµå
+                                    if( b_warn == false ) then
+                                      cdl_error( "HRP9999 '$1': kernel object joined from other user domain. kernel object joined from multi-user-domain must be placed out of domain", cell.get_name )
+                                      b_warn = true
+                                    end
+                                  end
+                                when :OutOfDomain
+                                  if( b_info == false ) then
+                                    # ç¡æå±ããã®çµå
+                                    # cdl_error( "HRP9999 kernel object joined from out of domain" )
+                                    if cell_domain_type.get_kind == :OutOfDomain
+                                      # ãã®æ
+å ±ã¯ãä¸è¦ã¨å¤æ­ãã (ç¡æå±ããç¡æå±ã¸çµåãããã¨ãã¢ã¯ã»ã¹è¨±å¯ãã¯ã¿ãè¨­å®ãããªã)
+                                      # cdl_info2( cell.get_locale, "HRP9999 '$1': kernel object joined from out of domain, access vector is not set", cell.get_name )
+                                      b_info = true
+                                    end
+                                  end
+                                else
+                                  raise "unknown domain kind"
+                                end
+                              }
+                              # acv[key] = "TACP(#{cell_domain_root.get_name.to_s})"
+                            else
+                              # p "OutOfDomainCell"
+                              # ç¡æå±ã®ã»ã«
+                              # çµåå
+ãã¡ã¤ã³ã«è¨±å¯ãã
+                              # çµåå
+ã«ç¡æå±ã®ã»ã«ãããã¨ãTACP_SHARED ãè¨­å®ããã. ãã­ã¼è§£æãã¦ãã¡ã¤ã³ãç¹å®ã§ããã®ããããã¹ãä»æ§
+                            end
+                            if acp == "OMIT"
+                              acv[key] = acv_tmp.join( '|' )
+                            end 
+                        end
+                    }
+                    #åç¨®SACã®çæ
+                    domainOption = cell_domain_type.get_option
+                    # p "domain_root ", cell.get_region.get_domain_root.get_name
+                    if domainOption != "OutOfDomain" || cell.get_region.get_domain_root.get_name != "::"
+                        # ä¿è­·ãã¡ã¤ã³ã«å±ããå ´å
+                        file3 = AppFile.open( "#{$gen}/tecsgen_#{cell.get_region.get_name.to_s}.cfg" )
+                        print_cfg_sac(file3, val, acv)
+                        file3.close
+                    else
+                        # ç¡æå±ã®å ´å
+                        print_cfg_sac(file2, val, acv)
+                    end
+
+                    dbgPrint "===== end check regions #{cell.get_name} =====\n"
+                end
+            end
+        }
+        dbgPrint "===== end #{@celltype.get_name.to_s} plugin =====\n"
+        file2.close
+    end
+
+    # ã«ã¼ãã«ãªãã¸ã§ã¯ãã»ã«ã¿ã¤ãã®ç®¡ç
+    # HRPKernelObjectPluginã¯ã©ã¹ã«å¯¾ãã¦ã¡ã½ããå¼åºããè¡ããã¨ãæ³å®
+    @@checked = false
+    @@celltype_list = []
+    @@region_list = []
+
+    def self.isChecked()
+        return @@checked
+    end
+
+    def self.check_referenced_cells()
+        dbgPrint "===== begin check registered celltype =====\n"
+        self.get_celltype_list.each { |ct|
+          dbgPrint( ct.get_name.to_s + "\n" )
+        }
+        dbgPrint "===== end check registered celltype =====\n"
+
+        @@checked = true
+    end
+
+    def self.set_celltype( celltype )
+        @@celltype_list << celltype
+    end
+
+    def self.get_celltype_list
+        return @@celltype_list
+    end
+
+    def self.set_region_list( region )
+        @@region_list << region
+    end
+
+    def self.include_region( region )
+        return @@region_list.include?(region)
+    end
+
+    def self.include_celltype?( celltype )
+        return @@celltype_list.include?(celltype)
+    end
+
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPObjectPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPObjectPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPObjectPlugin.rb	(revision 374)
@@ -0,0 +1,114 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#  $Id$
+#++
+
+require_tecsgen_lib "HRPKernelObjectPlugin.rb"
+
+
+class HRPObjectPlugin < HRPKernelObjectPlugin
+    @@api = {
+        "SEMAPHORE"=>["SEM", :id, :attribute, :initialCount, :maxCount],
+        "EVENTFLAG"=>["FLG", :id, :attribute, :flagPattern],
+        "DATAQUEUE"=>["DTQ", :id, :attribute, :dataCount, :dataqueueManagementBuffer],
+        "PRIORITY_DATAQUEUE"=>["PDQ", :id, :attribute, :dataCount, :maxDataPriority, :priorityDataqueueManagementBuffer],
+        "FIXED_SIZE_MEMORYPOOL"=>["MPF", :id, :attribute, :blockCount, :blockSize, :memoryPool, :memoryPoolManagementBuffer],
+        "KERNEL"=>["SYS"],
+        "MESSAGE_BUFFER"=>["MBF", :id, :attribute, :maxMessageSize, :bufferSize, :mbfmb],
+        "MUTEX"=>["MTX", :id, :attribute, :ceilingPriority]
+    }
+
+    #=== HRPObjectPlugin#print_cfg_cre
+    # CRE_XXXã®åºå
+    # file:: FILE:     åºåå
+ãã¡ã¤ã«
+    # val :: string:   ã«ã¼ãã«ãªãã¸ã§ã¯ãã®å±æ§ã®è§£æçµæ
+    # tab :: string:   ã¤ã³ãã³ãç¨ã®tab
+    def print_cfg_cre(file, cell, val, tab)
+        if @@api.has_key?(@plugin_arg_str) == false
+            raise "#{@plugin_arg_str} is unknown"
+        elsif @plugin_arg_str != "KERNEL"
+            arg_list = []
+            params = @@api[@plugin_arg_str]
+            if @plugin_arg_str == "MUTEX" && ((val[:attribute] =~ /\bTA_CEILING\b/)==nil)
+              slice_end = -2   # :ceilingPriority ãå¤ã
+            else
+              slice_end = -1
+            end
+            # p @plugin_arg_str, slice_end, val[:attribute], (val[:attribute] =~ /\bTA_CEILING\b/)
+            params.slice(2..slice_end).each { |attr|
+                arg_list << "#{val[attr]}"
+            }
+            file.print tab
+            file.puts "CRE_#{@@api[@plugin_arg_str].at(0)}(#{val[:id]}, { #{arg_list.join(", ")} });"
+        end
+    end
+    #=== HRPObjectPlugin#print_cfg_sac
+    # SAC_XXXã®åºå
+    # file:: FILE:     åºåå
+ãã¡ã¤ã«
+    # val :: string:   ã«ã¼ãã«ãªãã¸ã§ã¯ãã®å±æ§ã®è§£æçµæ
+    # acv :: string:   ã¢ã¯ã»ã¹ãã¯ã¿    
+    def print_cfg_sac(file, val, acv)
+        if @@api.has_key?(@plugin_arg_str) == false
+            raise "#{@plugin_arg_str} is unknown"
+        elsif @plugin_arg_str != "KERNEL"
+            file.puts "SAC_#{@@api[@plugin_arg_str].at(0)}(#{val[:id]}, { #{acv[:accessPattern1]}, #{acv[:accessPattern2]}, #{acv[:accessPattern3]}, #{acv[:accessPattern4]} });"
+        else
+            file.puts "SAC_#{@@api[@plugin_arg_str].at(0)}({ #{acv[:accessPattern1]}, #{acv[:accessPattern2]}, #{acv[:accessPattern3]}, #{acv[:accessPattern4]} });"
+        end
+    end
+
+end
+
+
+  
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPPlugin.rb	(revision 374)
@@ -0,0 +1,384 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2014-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#  $Id$
+#++
+
+
+require_tecsgen_lib "HRPKernelObjectManager.rb"
+#
+# åã¡ã½ããã®å½¹å²ãã¯ãDomainPlugin.rb ãåç
+§ã®ãã¨
+# HRPã«ã¼ãã«ç¨ãã¡ã¤ã³ãã©ã°ã¤ã³
+class HRPPlugin < DomainPlugin
+  
+  def initialize( region, name, option )
+    super
+    dbgPrint "HRPPlugin: initialize: region=#{region.get_name}, domainName=#{name}, option=#{option}\n"
+    @region = region
+    @name   = name
+    case option
+    when "kernel", "user", "OutOfDomain"
+      # OK
+      @option = option
+    else
+      cdl_error( "HRPPlugin: '$1' is unacceptable domain kind, specify 'kernel' or 'user'", option )
+      @option = "kernel"   # ã¨ãããã kernel ãè¨­å®ãã¦ãã
+    end
+  end
+
+  def add_through_plugin( join, current_region, next_region, through_type )
+    # join.get_owner:Cell  å·¦è¾ºã®ã»ã«
+    # join.get_definition:Port å¼ã³å£
+    # join.get_subscript:Integer or nil å¼ã³å£é
+åã®æ·»æ° (Join::@subscript ã®èª¬æåç
+§)
+    # join.get_cell:Cell å³è¾ºã®ã»ã«
+    # join.get_port_name:Symbol åãå£
+    # get_rhs_subscript:Integer or nil åãå£é
+åã®æ·»æ° (Join::@rhs_subscript ã®èª¬æåç
+§)
+    # return []
+    dbgPrint "MyDomainPlugin: add_through_plugin: #{current_region.get_name}=>#{next_region.get_name}, #{join.get_owner.get_name}.#{join.get_definition.get_name}=>#{join.get_cell.get_name}.#{join.get_port_name}, #{through_type}\n"
+
+    #puts "=====Join Check Start====="
+    #puts "caller: #{join.get_owner.get_name.to_s}, callee: #{join.get_cell.get_name.to_s}"
+    #puts "=====Join Check param====="
+    current_domain = current_region.get_domain_root.get_domain_type
+    next_domain = next_region.get_domain_root.get_domain_type
+    #puts current_domain.get_option.to_s
+    # if !next_domain.nil?
+    #     puts next_domain.get_option.to_s
+    # else
+    #     puts "next domain is nil!"
+    # end
+
+    HRPPlugin.add_inter_domain_join_set join
+    # p join.get_cell.get_name
+    # p join.get_cell.get_real_celltype(join.get_rhs_port1).get_name
+    # if HRPKernelObjectManager.include_celltype?(join.get_cell.get_celltype.get_global_name)   #oyama: get_name => get_global_name 
+    if HRPKernelObjectManager.include_celltype?(join.
+                                                 get_cell.
+                                                 get_real_celltype(join.get_rhs_port1).
+                                                 get_global_name)                #oyama: get_name => get_global_name 
+        # çµåå
+ãã«ã¼ãã«ãªãã¸ã§ã¯ãã»ã«
+        # @plugin_body = HRP2SVCPlugin.new(cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell)
+        # ä½ãããªãthrough
+        # puts "***** #{join.get_cell.get_celltype.get_name} is kernel object"
+        return []
+        # return [ :HRP2SVCPlugin, "channelCelltype=tMessagebufferChannel,noClientSemaphore=true" ]
+    # elsif @end_region.is_root?
+    # elsif next_region.get_option == OutOfDomain
+    # elsif next_domain.nil?
+    elsif next_domain.get_option.to_s == "OutOfDomain"
+    #     # çµåå
+ãç¡æå±
+    #     # ä½ãããªãthrough
+    #     # @plugin_body = HRP2SVCPlugin.new(cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell)
+        # puts "***** nil"
+        return []
+    #elsif @start_region.get_param != :KERNEL_DOMAIN && @end_region.get_param == :KERNEL_DOMAIN
+    elsif current_domain.get_option.to_s != "kernel" && next_domain.get_option.to_s == "kernel"
+        # ã¦ã¼ã¶ãã¡ã¤ã³ããã«ã¼ãã«ãã¡ã¤ã³ã¸ã®çµå
+        # @plugin_body = HRP2SVCPlugin.new(cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell)
+        # puts "***** svc"
+        return [ :HRPSVCPlugin, "" ]
+    elsif current_domain != next_domain
+        # å¥ã®ã¦ã¼ã¶ãã¡ã¤ã³ã¸ã®çµå
+        # @plugin_body = HRP2RPCPlugin.new(cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell)
+        # puts "***** rpc"
+        # return [ :HRPRPCPlugin, "channelCelltype=tMessagebufferChannel,noClientSemaphore=true" ]
+        # puts "HRPPlugin:RPC:PPAllocatorSize=256"
+        return [ :HRPRPCPlugin, "noClientSemaphore=false,PPAllocatorSize=256" ]
+    else
+        # ãã®ä»
+        # ä½ãããªãthrough
+        # @plugin_body = HRP2SVCPlugin.new(cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell)
+        dbgPrint "warning: at HRP Join Check"
+        return nil
+    end
+
+    # puts "=====Join Check End====="
+  end
+
+  def joinable?(current_region, next_region, through_type )
+    dbgPrint "MyDomainPlugin: joinable? from #{current_region.get_name} to #{next_region.get_name} (#{through_type})\n"
+    return true
+  end
+
+  #== ãã¡ã¤ã³ç¨®å¥ãè¿ã
+  #return::Symbol :kernel, :user, :OutOfDomain
+  def get_kind
+    return @option.to_sym
+  end
+  
+  def self.gen_post_code file
+  end
+
+  # ATT_MODãçææ¸ã¿ãã©ãã                   # 2017.8.27
+  @@generate_memory_module = false
+
+  @@include_extsvc_fncd = false  # 17.07.26 æ«å®
+  # 
+  #  ATT_MODã®çæ
+  #  gen_factoryå®è¡æã«ã¯ï¼ãã¹ã¦ã®ã»ã«ã¿ã¤ããã©ã°ã¤ã³ãçææ¸ã¿ã®ã¯ããªã®ã§ï¼
+  #  ã«ã¼ãã«APIã³ã¼ãã®ã¡ã¢ãªä¿è­·ãçç¥ã§ããï¼
+  #
+  def gen_factory
+    super
+
+    if @@include_extsvc_fncd == false
+      file = AppFile.open( "#{$gen}/tecsgen.cfg" )
+      file.print "/* HRPPlugin 001 */\n"
+      file.print "#include \"extsvc_fncode.h\"\n"   ## 2017.7.26
+      file.close
+      @@include_extsvc_fncd = true
+    end
+
+    if @@generate_memory_module == false
+
+      # INCLUDE ãåºå
+      #  ãã¹ã¦ã®ãã¡ã¤ã³ã«å¯¾ãã cfg ãå
+ã«çæãã¦ãã
+      #  ããããã¡ã¤ã³ã«å±ããã«ã¼ãã«ãªãã¸ã§ã¯ãããã¢ã¸ã¥ã¼ã«ããªãå ´åã§ããcfg ãåºåããã
+      regions = DomainType.get_domain_regions[ :HRP ]
+      file = AppFile.open( "#{$gen}/tecsgen.cfg" )
+      file.print "/* HRPPlugin 002 */\n"
+      regions.each{ |region|
+        if ! region.is_root? then
+          nsp = "#{region.get_global_name}"
+          file2 = AppFile.open( "#{$gen}/tecsgen_#{nsp}.cfg" )
+          file2.close
+          case region.get_domain_type.get_kind
+          when :kernel
+            pre = "KERNEL_DOMAIN{\n    "
+            post = "}\n"
+          when :user
+            pre = "DOMAIN(#{region.get_name}){\n    "
+            post = "}\n"
+          when :OutOfDomain
+            pre = ""
+            post = "\n"
+          end
+          file.puts "#{pre}INCLUDE(\"#{$gen}/tecsgen_#{nsp}.cfg\");\n#{post}"
+        end
+      }
+      file.print "/* HRPPlugin 002 end */\n\n"
+      file.close
+
+      check_celltype_list = []
+
+      # 
+      #  ATT_MODã®çæ
+      #
+      Cell.get_cell_list2.each { |cell|
+        # ãã¹ã¦ã®ã»ã«ãèµ°æ»ãã¦ã»ã«ã¿ã¤ãããã§ãã¯
+        ct = cell.get_celltype
+        if ct.class == Celltype && check_celltype_list.include?( ct ) == false
+          # ãã§ãã¯æ¸ã¿ã»ã«ã¿ã¤ãã«ç»é²
+          check_celltype_list << ct
+
+          # æªãã§ãã¯ã®ã»ã«ã¿ã¤ãã ã£ãå ´å
+          # puts "check for ATT_MOD : #{ct.classget_global_name}"
+          # puts "check for ATT_MOD : #{ct.get_global_name}"
+
+          # ã«ã¼ãã«APIã®ã³ã¼ãï¼ãã¼ã¿ã¯ã¡ã¢ãªä¿è­·ããªã # HRP3 oyama delete by Takada's request
+          # next if HRPKernelObjectManager.include_celltype?( ct.get_name )
+
+          # å¿
+è¦ã®ãªãã»ã«ã¿ã¤ãã®ã³ã¼ãï¼ãã¼ã¿ã¯ã¡ã¢ãªä¿è­·ããªã
+          next if ! ct.need_generate?
+
+          # HRPã®ãã¡ã¤ã³ãªã¼ã¸ã§ã³ãåå¾
+          regions = ct.get_domain_roots
+          regions_hrp = regions[ :HRP ]
+          dbgPrint "HRP domain in #{ct.get_name}: "
+          regions_hrp.each { |reg|
+            dbgPrint reg.get_name
+          }
+          # puts ""
+
+          # ã»ã«ç®¡çãã­ãã¯ã¨ã¹ã±ã«ãã³ã®ã¡ã¢ãªä¿è­·
+          # gen_celltype_names_domain ç¸å½ã®å¦ç
+          if regions_hrp.include?( Region.get_root ) == false && regions_hrp.length > 1
+            # ãã¡ã¤ã³ãè¤æ°ã§ï¼OutOfDomainã«ã»ã«ãå­å¨ããªãã»ã«ã¿ã¤ãã®å ´å
+            # å
+±æã®ã»ã«ç®¡çãã­ãã¯ã¨ã¹ã±ã«ãã³ã³ã¼ããç»é²ãã
+            file = AppFile.open( "#{$gen}/tecsgen.cfg" )
+            file.printf "%-60s/* HRPPlugin 003 */\n", "ATT_MOD(\"#{ct.get_global_name}_tecsgen.o\");"
+            file.close
+          end
+
+          regions_hrp.each { |reg|
+            if reg.is_root? 
+              nsp = ""
+            else
+              nsp = "_#{reg.get_global_name}"
+            end
+            file = AppFile.open( "#{$gen}/tecsgen#{nsp}.cfg" )
+            file.printf "%-50s/* HRPPlugin 004 */\n", "ATT_MOD(\"#{ct.get_global_name}#{nsp}_tecsgen.o\");"
+            file.close
+          }
+
+          # ã»ã«ã¿ã¤ãã³ã¼ãããªãå ´åã¯ã¹ã­ãã
+          next if ct.is_all_entry_inline? && ! ct.is_active?
+
+          # ã»ã«ã¿ã¤ãã³ã¼ãã®ã¡ã¢ãªä¿è­·
+          # gen_celltype_names_domain2 ç¸å½ã®å¦ç
+          if regions_hrp.include?( Region.get_root ) == true || regions_hrp.length > 1
+            # OutOfDomainã«ã»ã«ãå­å¨ããã»ã«ã¿ã¤ãã®å ´å
+            # ã¾ãã¯ï¼è¤æ°ã®ãã¡ã¤ã³ã«ã»ã«ãå­å¨ããã»ã«ã¿ã¤ãã®å ´å
+            # ã»ã«ã¿ã¤ãã³ã¼ããå
+±æããããã«ç»é²ãã
+            file = AppFile.open( "#{$gen}/tecsgen.cfg" )
+          else
+            # OutOfDomainã§ãªãåä¸ã®ãã¡ã¤ã³ã«ã»ã«ãå­å¨ããã»ã«ã¿ã¤ãã®å ´å
+            # ã»ã«ã¿ã¤ãã³ã¼ããå°æããããã«ç»é²ãã
+            file = AppFile.open( "#{$gen}/tecsgen_#{regions_hrp[0].get_global_name}.cfg" )
+          end
+
+          file.printf "%-50s/* HRPPlugin 005 */\n", "ATT_MOD(\"#{ct.get_global_name}.o\");"
+          file.close
+        else
+          # ä½ãããªã
+        end
+      }
+
+      @@generate_memory_module = true
+    else
+      # ä½ãããªã
+    end
+  end
+
+  #----- Inter Domain Join Set -----#
+  @@inter_domain_join_set = {}      #{entry_cell =>{domain_root=>count} }  Hash of inter domain join
+  def self.add_inter_domain_join_set join
+    rhs_cell = join.get_cell
+    dbgPrint "--------- add_inter_domain:#{join.get_owner.get_namespace_path} => #{join.get_cell.get_namespace_path}-----\n"
+    domain_root = join.get_owner.get_region.get_domain_root   # lhs cell's domain root
+    if @@inter_domain_join_set[ rhs_cell ] == nil then
+      @@inter_domain_join_set[ rhs_cell ] = []
+    end
+    # å·¦è¾ºã®ãã¡ã¤ã³ã«ã¼ããè¨é²
+    @@inter_domain_join_set[ rhs_cell ] << join
+  end
+  def self.get_inter_domain_join_set rhs_cell
+    if @@inter_domain_join_set[ rhs_cell ] then
+      @@inter_domain_join_set[ rhs_cell ].uniq!
+    else
+      @@inter_domain_join_set[ rhs_cell ] = []
+    end
+    return @@inter_domain_join_set[ rhs_cell ]
+  end
+  def self.get_inter_domain_join_roots rhs_cell
+    dbgPrint "--------- get_inter_domain #{rhs_cell.get_namespace_path} -----\n"
+    domain_roots = []
+    set = get_inter_domain_join_set rhs_cell
+    set.each{ |join|
+      dbgPrint "--------- get_inter_domain:#{join.get_owner.get_namespace_path} => #{join.get_cell.get_namespace_path}-----\n"
+      # if join.get_owner.get_region.get_domain_root.get_domain_type.get_option == "user" then
+        domain_roots << join.get_owner.get_region.get_domain_root
+      # end
+    }
+    return domain_roots.uniq
+  end
+
+  def self.get_sac_str cell
+    domain_roots = self.get_inter_domain_join_roots cell
+    delim = ""
+    acv = ""
+    cell_domain_root = cell.get_region.get_domain_root
+    if cell_domain_root.get_domain_type.get_kind != :OutOfDomain then
+      domain_roots << cell.get_region.get_domain_root  # çµåå
+ã®ãã¡ã¤ã³ãå«ãã
+    end
+    domain_roots.each{ |dr|
+      case dr.get_domain_type.get_kind
+      when :kernel
+        acv += "#{delim}TACP_KERNEL"
+        delim = "|"
+      when :user
+        acv += "#{delim}TACP(#{dr.get_name})"
+        delim = "|"
+        if cell_domain_root.get_domain_type.get_kind != :OutOfDomain &&
+           dr.get_namespace_path != cell_domain_root.get_namespace_path then
+          cdl_error( "HRP9999 '$1': kernel object joined from other user domain. kernel object joined from multi-user-domain must be placed out of domain", cell.get_name )
+        end
+      when :OutOfDomain
+        if cell_domain_root.get_domain_type.get_kind == :OutOfDomain then
+          acv += "#{delim}TACP_SHARED"
+          delim = "|"
+        end
+      else
+        raise "unkown domain kind"
+      end
+    }
+    if acv == "" then
+      # å¼ã³å
+ã»ã«ãç¡æå±ãã¤ãå¼ã³å
+ãç¡æå±ã®ã¿ãã¾ãã¯çµåç¡ãã®å ´å
+      acv = "TACP_SHARED"
+    end
+    sac_str = "{"
+    delim = ""
+    [:accessPattern1, :accessPattern2, :accessPattern3, :accessPattern4].each{ |acp|
+      init = (cell.get_attr_initializer acp).to_s
+      if init != "OMIT"
+        sac_str += delim + init
+      else
+        sac_str += delim + acv
+      end
+      delim = ", "
+    }
+    return sac_str + '}'
+  end
+end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPRPCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPRPCPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPRPCPlugin.rb	(revision 374)
@@ -0,0 +1,441 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#  $Id$
+#++
+
+require_tecsgen_lib "lib/GenOpaqueMarshaler.rb"
+require_tecsgen_lib "lib/GenParamCopy.rb"
+
+#= HRPRPCPlugin ãã©ã°ã¤ã³
+# ã¹ã«ã¼ãã©ã°ã¤ã³ (through)
+# ã»OpaqueMarshalerPlugin ãä½¿ç¨ãã¦ãã¼ã·ã£ã©ã»ã«ã¿ã¤ããçæãã
+# ã»ãã¼ã·ã£ã©ãTDRããã£ã³ãã«ãã¡ãã»ã¼ã¸ãããã¡ãçæãã
+#
+class HRPRPCPlugin < ThroughPlugin
+
+  include GenOpaqueMarshaler
+  include GenParamCopy
+
+  # RPCPlugin å°ç¨ã®ãªãã·ã§ã³
+  HRPRPCPluginArgProc = RPCPluginArgProc.dup  # è¤è£½ãä½ã£ã¦å
+ãå¤æ´ããªãããã«ãã
+  HRPRPCPluginArgProc[ "noClientSemaphore"  ] = Proc.new { |obj,rhs| obj.set_noClientSemaphore rhs }
+  HRPRPCPluginArgProc[ "semaphoreCelltype"  ] = Proc.new { |obj,rhs| obj.set_semaphoreCelltype rhs }
+  @@isFirstInstance = true
+
+  #=== RPCPlugin ã® initialize
+  #  èª¬æã¯ ThroughPlugin (plugin.rb) ãåç
+§
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
+    super
+    @b_noClientSemaphore = false
+    @semaphoreCelltype = "tSemaphore"
+    initialize_opaque_marshaler
+
+    # ãªãã·ã§ã³ï¼GenOpaqueMarshaler åç
+§
+    @plugin_arg_check_proc_tab = HRPRPCPluginArgProc
+    parse_plugin_arg
+
+    @rpc_channel_celltype_name = "tRPCPlugin_#{@TDRCelltype}_#{@channelCelltype}_#{@signature.get_name}"
+    @rpc_channel_celltype_file_name = "#{$gen}/#{@rpc_channel_celltype_name}.cdl"
+
+    if @signature.get_context == "non-task" then
+        cdl_error( "HRP9999 RPC cannot be applied to non-task context signature '$1'", @signature.get_name )
+    elsif @signature.get_context == "any" then
+        cdl_info( "HRP9999 RPC is applied to any context signature '$1'", @signature.get_name )
+    end
+
+    if @signature.need_PPAllocator?(true) then
+      if @PPAllocatorSize == nil then
+        cdl_error( "HRP9999 PPAllocatorSize must be speicified for pointer argments" )
+        # @PPAllocatorSize = 0   # ä»®ã« 0 ã¨ãã¦ãã (cdl ã®æ§æã¨ã©ã¼ãé¿ãããã)
+      end
+    elsif @PPAllocatorSize then
+      cdl_warning( "HRP9999 PPAllocatorSize speicified in spite of PPAllocator unnecessary" )
+      @PPAllocatorSize = nil
+    end
+
+#    @signature.each_param{ |func_decl, param_decl|
+#      if func_decl.get_type.is_oneway? then
+#        if ( param_decl.get_size || param_decl.get_count ) && param_decl.get_string then
+#          cdl_error( "array of string not supported for oneway function in Transparent RPC" )  # mikan æå­åã®é
+å
+#        elsif param_decl.get_string == -1 then
+#          cdl_error( "length unspecified string is not permited for oneway function in Transparent RPC" )  # mikan é·ãæªæå®æå­å
+#        end
+#      end
+#    }
+
+    # 
+    #  tecsgen/tecs/rpcã«includeãã¹ãéã
+    #  #include "tecs_rpc.h" ãå®ç¾ããããã«å¿
+è¦
+    #    å¤§å±±:åé¤ Makefile.tecsgen ã« vpath, INCLUDES ãå
+¥ããã®ã¯ããããªãèã
+    #             TECSGEN.add_search_path ã§ Makefile_templ ã«å
+¥ããã®ããã
+    # if @@isFirstInstance
+    #     f = AppFile.open( "#{$gen}/Makefile.tecsgen" )
+    #     f.puts "INCLUDES := $(INCLUDES) -I $(TECSPATH) -I $(TECSPATH)/rpc"
+    #     f.puts "vpath %.c $(TECSPATH) $(TECSPATH)/rpc"
+    #     f.close()
+    #     @@isFirstInstance = false
+    # end
+  end
+
+  #=== plugin ã®å®£è¨ã³ã¼ã (celltype ã®å®ç¾©) çæ
+  def gen_plugin_decl_code( file )
+
+    ct_name = "#{@ct_name}_#{@channelCelltype}"
+
+    # ãã®ã»ã«ã¿ã¤ãï¼åãã·ã°ããã£ï¼ã¯æ¢ã«çæããã¦ãããï¼
+    if @@generated_celltype[ ct_name ] == nil then
+      @@generated_celltype[ ct_name ] = [ self ]
+    else
+      @@generated_celltype[ ct_name ] << self
+      return
+    end
+
+    f = CFile.open( @rpc_channel_celltype_file_name, "w" )
+    # åãå
+å®¹ãäºåº¦æ¸ãå¯è½æ§ãã (AppFile ã¯ä¸å¯)
+
+    f.print <<EOT
+import( <rpc.cdl> );
+import( <tMessageBufferCEP.cdl> );
+generate( OpaqueMarshalerPlugin, #{@signature.get_namespace_path}, "" );
+
+composite tOpaqueMarshaler_#{@signature.get_global_name}_through {
+  entry #{@signature.get_namespace_path} eThroughEntry;
+  call sTDR       cTDR;
+  [optional]
+    call sSemaphore cLockChannel;
+  [optional]
+    call sRPCErrorHandler cErrorHandler;
+
+  cell tOpaqueMarshaler_#{@signature.get_global_name} Marshaler{
+    cTDR          => composite.cTDR;
+    cLockChannel  => composite.cLockChannel;
+    cErrorHandler => composite.cErrorHandler;
+  };
+  composite.eThroughEntry => Marshaler.eClientEntry;
+};
+
+EOT
+
+    f.close
+  end
+
+  #===  through cell ã³ã¼ããçæ
+  #
+  #
+  def gen_through_cell_code( file )
+
+    gen_plugin_decl_code( file )
+    file.print <<EOT
+import( <#{@rpc_channel_celltype_file_name}> );
+EOT
+
+    case @start_region.get_domain_root.get_domain_type.get_kind
+    when :kernel
+      tacp_str = "\"TACP_KERNEL"
+    when :user
+      tacp_str = "\"TACP(#{@start_region.get_domain_root.get_name})"
+    when :OutOfDomain
+      tacp_str = "\"TACP_SHARED"
+    end
+    # p "end_region=#{@end_region.get_name} kind=#{@end_region.get_domain_root.get_domain_type.get_kind}"
+    case @end_region.get_domain_root.get_domain_type.get_kind
+    when :kernel
+      tacp_str += "|TACP_KERNEL\""
+    when :user
+      tacp_str += "|TACP(#{@end_region.get_domain_root.get_name})\""
+    when :OutOfDomain
+      tacp_str += "|TACP_SHARED\""
+    end
+    nest_str = ""
+    file.print <<EOT
+#{nest_str}  //  MessageBuffer client=>server
+#{nest_str}  cell tMessageBuffer #{@clientChannelCell}Body0{
+#{nest_str}      maxMessageSize = 64;      /* This value must be same as MessageBufferCEP's buffer size */
+#{nest_str}      bufferSize     = 128;
+#{nest_str}      accessPattern1 = C_EXP( #{tacp_str} );
+#{nest_str}      accessPattern2 = C_EXP( #{tacp_str} );
+#{nest_str}      accessPattern3 = C_EXP( #{tacp_str} );
+#{nest_str}      accessPattern4 = C_EXP( #{tacp_str} );
+#{nest_str}  };
+EOT
+    file.print <<EOT
+
+#{nest_str}  //  MessageBuffer server=>client
+#{nest_str}  cell tMessageBuffer #{@clientChannelCell}Body1{
+#{nest_str}      maxMessageSize = 64;      /* This value must be same as MessageBufferCEP's buffer size */
+#{nest_str}      bufferSize     = 128;
+#{nest_str}      accessPattern1 = C_EXP( #{tacp_str} );
+#{nest_str}      accessPattern2 = C_EXP( #{tacp_str} );
+#{nest_str}      accessPattern3 = C_EXP( #{tacp_str} );
+#{nest_str}      accessPattern4 = C_EXP( #{tacp_str} );
+#{nest_str}  };
+EOT
+
+    ##### ã¯ã©ã¤ã¢ã³ãå´ã®ã»ã«ã®çæ #####
+    nest = @start_region.gen_region_str_pre file
+    nest_str = "  " * nest
+
+    # ã»ããã©ã®çæ
+    if @b_noClientSemaphore == false then
+      file.print <<EOT
+#{nest_str}  //  Semaphore for Multi-task use ("specify noClientSemaphore" option to delete this)
+#{nest_str}  cell #{@semaphoreCelltype} #{@serverChannelCell}_Semaphore{
+#{nest_str}    initialCount = 1;
+#{nest_str}  };
+EOT
+    end
+
+    # ã¯ã©ã¤ã¢ã³ãå´ãã£ã³ãã« (tMessageBufferCEP)ã®çæ
+    # ãã£ã³ãã«ã¯å¿
+ããªã¼ã¸ã§ã³ä¸ã«ããã®ã§ã '::' ã§ã¤ãªã (ã§ãªããã°ãã«ã¼ããªã¼ã¸ã§ã³ã«ãªãããã§ãã¯ãå¿
+è¦ï¼
+
+    file.print <<EOT
+#{nest_str}  //  Client Side Channel
+#{nest_str}  cell tMessageBufferCEP #{@clientChannelCell}_CEP{
+#{nest_str}      cMessageBuffer0 = #{@clientChannelCell}Body0.eMessageBuffer;
+#{nest_str}      cMessageBuffer1 = #{@clientChannelCell}Body1.eMessageBuffer;
+#{nest_str}  };
+
+#{nest_str}  //  Client Side TDR
+#{nest_str}  cell tTDR #{@clientChannelCell}_TDR{
+#{nest_str}    cChannel = #{@clientChannelCell}_CEP.eChannel;
+#{nest_str}  };
+
+#{nest_str}  //  Marshaler
+EOT
+
+    # ã»ããã©ã®çµåæ
+    if @b_noClientSemaphore == false then
+      semaphore = "#{nest_str}    cLockChannel = #{@serverChannelCell}_Semaphore.eSemaphore;\n"
+    else
+      semaphore = ""
+    end
+
+    ### ã¯ã©ã¤ã¢ã³ãå´ãã£ã³ãã« (ãã¼ã·ã£ã©+TDR)ã®çæ ###
+    cell = @next_cell
+    # ã¢ã­ã±ã¼ã¿ã®æå®ããããï¼
+    if cell.get_allocator_list.length > 0 then
+
+      file.print nest_str
+      file.print "[allocator("
+
+      delim = ""
+      cell.get_allocator_list.each do |type, eport, subsc, func, buf, alloc|
+
+        alloc_str = alloc.to_s
+        subst = @substituteAllocator[alloc_str.to_sym]
+        if subst then
+          alloc_str = subst[2]+"."+subst[3]
+        end
+
+        file.print delim
+        delim = ",\n"        # æçµè¡ã«ã¯åºããªã
+
+        if subsc then        # é
+åæ·»æ°
+          subsc_str = '[#{subsc}]'
+        else
+          subsc_str = ""
+        end
+
+        eport = "eThroughEntry" #RPCã®åãå£åã«å¤æ´
+        file.print nest_str
+        file.print  "#{eport}#{subsc_str}.#{func}.#{buf} = #{alloc_str}"
+      end
+
+      file.puts ")]"
+    end
+
+    if @clientErrorHandler then
+      clientErrorHandler_str = "#{nest_str}    cErrorHandler = #{@clientErrorHandler};\n"
+    else
+      clientErrorHandler_str = ""
+    end
+
+    file.print <<EOT
+#{nest_str}  cell tOpaqueMarshaler_#{@signature.get_global_name}_through #{@cell_name} {
+#{nest_str}    cTDR = #{@clientChannelCell}_TDR.eTDR;
+#{clientErrorHandler_str}#{semaphore}#{nest_str}  };
+EOT
+    ### END: ã¯ã©ã¤ã¢ã³ãå´ãã£ã³ãã« (ãã¼ã·ã£ã©+TDR)ã®çæ ###
+    @start_region.gen_region_str_post file
+    file.print "\n\n"
+
+    ##### ãµã¼ãã¼å´ã®ã»ã«ã®çæ #####
+    nest = @end_region.gen_region_str_pre file
+    nest_str = "  " * nest
+
+    if @serverErrorHandler then
+      serverErrorHandler_str = "#{nest_str}    cErrorHandler = #{@serverErrorHandler};\n"
+    else
+      serverErrorHandler_str = ""
+    end
+
+    if @b_genOpener then
+      opener = "#{nest_str}    cOpener       = #{@serverChannelCell}.eOpener;\n"
+    else
+      opener = ""
+    end
+
+    # ãµã¼ãã¼å´ãã£ã³ãã« (tMessageBufferCEP)
+    if @PPAllocatorSize then
+      alloc_cell =<<EOT
+
+#{nest_str}  cell tPPAllocator #{@serverChannelCell}_PPAllocator {
+#{nest_str}    heapSize = #{@PPAllocatorSize};
+#{nest_str}  };
+EOT
+      alloc_call_port_join = "#{nest_str}    cPPAllocator = #{@serverChannelCell}_PPAllocator.ePPAllocator;\n"
+    else
+      alloc_cell = ""
+      alloc_call_port_join = ""
+    end
+
+    file.print <<EOT
+#{nest_str}  //  Server Side Channel
+#{nest_str}  cell tMessageBufferCEP #{@serverChannelCell}_CEP{
+#{nest_str}      cMessageBuffer0 = #{@clientChannelCell}Body1.eMessageBuffer;
+#{nest_str}      cMessageBuffer1 = #{@clientChannelCell}Body0.eMessageBuffer;
+#{nest_str}  };
+EOT
+
+    # ãµã¼ãã¼å´TDR
+    file.print <<EOT
+
+#{nest_str}  //  Server Side TDR
+#{nest_str}  cell tTDR #{@serverChannelCell}_TDR{
+#{nest_str}    cChannel = #{@serverChannelCell}_CEP.eChannel;
+#{nest_str}  };
+EOT
+
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
+
+    # ãµã¼ãã¼å´ãã£ã³ãã« (ã¢ã³ãã¼ã·ã£ã©)
+    file.print <<EOT
+#{alloc_cell}
+#{nest_str}  //  Unmarshaler
+#{nest_str}  cell tOpaqueUnmarshaler_#{@signature.get_global_name} #{@serverChannelCell}_Unmarshaler {
+#{nest_str}    cTDR        = #{@serverChannelCell}_TDR.eTDR;
+#{nest_str}    cServerCall = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
+#{alloc_call_port_join}#{serverErrorHandler_str}#{nest_str}  };
+EOT
+
+    # ãµã¼ãã¼å´ã¿ã¹ã¯ã¡ã¤ã³
+    file.print <<EOT
+
+#{nest_str}  //  Unmarshaler Task Main
+#{nest_str}  cell #{@taskMainCelltype} #{@serverChannelCell}_TaskMain {
+#{nest_str}    cMain         = #{@serverChannelCell}_Unmarshaler.eService;
+#{opener}#{nest_str}  };
+EOT
+
+    # ãµã¼ãã¼å´ã¿ã¹ã¯
+    file.print <<EOT
+
+#{nest_str}  //  Unmarshaler Task
+#{nest_str}  cell #{@taskCelltype} #{@serverChannelCell}_Task {
+#{nest_str}    cTaskBody = #{@serverChannelCell}_TaskMain.eMain;
+#{nest_str}    priority  = #{@taskPriority};
+#{nest_str}    stackSize = #{@stackSize};
+#{nest_str}    attribute = C_EXP( "TA_ACT" );  /* mikan : marshaler task starts at beginning */
+#{nest_str}  };
+EOT
+    @end_region.gen_region_str_post file
+  end
+
+
+  #=== ãã©ã°ã¤ã³å¼æ° noClientSemaphore ã®ãã§ãã¯
+  def set_noClientSemaphore rhs
+    rhs = rhs.to_sym
+    if rhs == :true then
+      @b_noClientSemaphore = true
+    elsif rhs == :false then
+      @b_noClientSemaphore = false
+    else
+      cdl_error( "RPCPlugin: specify true or false for noClientSemaphore" )
+    end
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° semaphoreCelltype ã®ãã§ãã¯
+  def set_semaphoreCelltype rhs
+    @semaphoreCelltype = rhs.to_sym
+    nsp = NamespacePath.analyze( @semaphoreCelltype.to_s )
+    obj = Namespace.find( nsp )
+    if ! obj.instance_of?( Celltype ) && ! obj.instance_of?( CompositeCelltype ) then
+      cdl_error( "RPCPlugin: semaphoreCelltype '#{rhs}' not celltype or not defined" )
+    end
+  end
+
+  #=== NamespacePath ãå¾ã
+  # çæããã»ã«ã® namespace path ãçæãã
+  def get_cell_namespace_path
+#    nsp = @region.get_namespace.get_namespace_path
+    nsp = @start_region.get_namespace_path
+    return nsp.append( @cell_name )
+  end
+
+end
+
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPSVCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPSVCPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPSVCPlugin.rb	(revision 374)
@@ -0,0 +1,910 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#  $Id$
+#++
+
+# mikan through plugin: namespace ãèæ
+®ããã¦ããªã
+# ãããå©ç¨ããå ´åãä»¥ä¸ã®ããã« toppers_jsp.cdl sChannel.cdl ãæå®ããå¿
+è¦ããã
+# tecsgen toppers_jsp.cdl sChannel.cdl your_description.cdl
+
+# ä»¥ä¸ãä»®å®ï¼å¶éäºé 
+ï¼
+#  å¼ã³å
+ãå¼ã³å
+ã®ã¨ã³ãã£ã¢ã³ãchar, short, int_t, long_t, intptr_t ã®ãµã¤ãºãåã
+#  æç¬¦å·ãç¡ç¬¦å·ã§ãµã¤ãºãåã
+
+class SVCManage
+    #
+    #  @@id: TECSã®ãã©ã°ã¤ã³ã§çæããæ¡å¼µãµã¼ãã¹ã³ã¼ã«ã«å²ãå½ã¦ãid
+    #        å®éã®æ¡å¼µãµã¼ãã¹ã³ã¼ã«IDã¯ï¼TFN_TECSGEN_ORIGINã§ä¸é§ã
+    #        å±¥ãããå¤ã¨ãªã
+    #        TFN_TECSGEN_ORIGINã¯ï¼hrp3/include/extsvc_fncode.h ã§å®ç¾©
+    #        ããã
+    #  @@func_ids: æ¡å¼µãµã¼ãã¹ã³ã¼ã«ã®é¢æ°åã¨æ¡å¼µãµã¼ãã¹ã³ã¼ã«IDã
+    #  ãããå¯¾å¿ã¥ããããã·ã¥
+    #
+    @@id = 0
+    @@func_ids = {}
+    def initialize()
+        # 
+      #  æ¬ã¯ã©ã¹ã¯ã¤ã³ã¹ã¿ã³ã¹ãæããªãä»®æ³çãªã¯ã©ã¹ã§ãã
+        #
+        raise "class #{self.class.name} shall not have instances"
+    end
+    def self.get_func_id func_name
+        return @@func_ids[ func_name ]
+    end
+    def self.set_func_id func_name
+        @@func_ids[ func_name ] = self.assign_id
+        # puts @@func_ids[ func_name ]
+    end
+    def self.get_id
+        return @@id
+    end
+    def self.set_id id
+        @@id = id
+    end
+    def self.assign_id
+        assignedId = @@id
+        @@id += 1
+        return assignedId
+    end
+end
+
+#
+#  æ¡å¼µãµã¼ãã¹ã³ã¼ã«ãç¨ãããã¡ã¤ã³ééä¿¡ã®
+#  throughãã©ã°ã¤ã³
+#  HRPãã¡ã¤ã³ãã©ã°ã¤ã³ã«ãã£ã¦æ¿å
+¥ããã
+#  åææ¡ä»¶: å¼åºãå
+ãã«ã¼ãã«ãªãã¸ã§ã¯ããã©ããã®å¤å®ã¯HRPãã¡ã¤ã³ãã©ã°ã¤ã³
+#  ãããããã§å®æ½ãããããï¼ããã§ã¯å¤å®ããªããã¨ã¨ãã
+#
+class HRPSVCPlugin < ThroughPlugin
+
+  NUM_SVC_ARG_MAX = 5              # HRP3 ã®æ¡å¼µãµã¼ãã¹ã³ã¼ã«ã§æ±ããã¨ã®ã§ããå¼æ°ã®æå¤§åæ°
+
+  @@generated_celltype ={}    # ã»ã«ã¿ã¤ãã®éè¤æé¤ç¨
+  @@generated_cell = {}       # ã»ã«ã®éè¤æé¤ç¨
+
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
+    super
+
+    # åãå£é
+åã®å ´åãé
+åæ·»æ°ãã¨ã«å¥ã®ã»ã«ã¿ã¤ãã¨ãã
+    # ã»ã«ã¿ã¤ããã·ã³ã°ã«ãã³åãããããã
+    # ãããªãã¨ãã»ã«ãè­å¥ããå¼æ°ãæ¸¡ãå¿
+è¦ããããNUM_SVC_ARG_MAX(5) ã¤ããæ¸¡ããªãå¼æ°ã®ä¸ã¤ãæ¶è²»ãããã¨ã«ãªãããã
+    if @next_cell_port_subscript then
+      subscript = "__" + @next_cell_port_subscript.to_s
+    else
+      subscript = ""
+    end
+    @ct_name_body = "#{@ct_name}SVCBody_#{@next_cell.get_name}_#{@next_cell_port_name}#{subscript}".to_sym
+    @ct_name = "#{@ct_name}SVCCaller_#{@next_cell.get_name}_#{@next_cell_port_name}#{subscript}".to_sym
+    @cell_name_body = "#{@cell_name}SVCBody".to_sym
+    @cell_name = "#{@cell_name}SVCCaller".to_sym
+    # puts "%%%% "
+    # p @next_cell.get_name
+    # p @caller_cell.get_name
+    @b_printed_include_stdint = false
+    check_signature signature
+  end
+
+  #=== NamespacePath ãå¾ã
+  # çæããã»ã«ã® namespace path ãçæãã
+  def get_cell_namespace_path
+#    nsp = @region.get_namespace.get_namespace_path
+    nsp = @start_region.get_namespace_path
+    return nsp.append( @cell_name )
+  end
+
+  def gen_plugin_decl_code( file )
+
+    # ãã®ã»ã«ã¿ã¤ãï¼åãã·ã°ããã£ï¼ã¯æ¢ã«çæããã¦ãããï¼
+    if @@generated_celltype[ @ct_name_body ] == nil then
+        @@generated_celltype[ @ct_name_body ] = [ self ]
+        file2 = CFile.open( "#{$gen}/#{@ct_name_body}.cdl", "w" )
+        file2.print <<EOT
+import_C( "t_stdlib.h" );
+
+/* HRPSVC0001 */
+[active,singleton]
+celltype #{@ct_name_body} {
+    call #{@signature.get_name} #{@call_port_name};
+    FACTORY {
+		write("$ct$_tecsgen.h", "#include \\"kernel_cfg.h\\"");
+    };
+};
+EOT
+        file2.close
+    else
+      @@generated_celltype[ @ct_name_body ] << self
+    end
+    file.print "import( \"#{$gen}/#{@ct_name_body}.cdl\" );\n"
+
+    # ãã®ã»ã«ã¿ã¤ãï¼åãã·ã°ããã£ï¼ã¯æ¢ã«çæããã¦ãããï¼
+    if @@generated_celltype[ @ct_name ] == nil then
+        @@generated_celltype[ @ct_name ] = [ self ]
+        file2 = CFile.open( "#{$gen}/#{@ct_name}.cdl", "w" )
+        file2.print <<EOT
+/* HRPSVC0002 */
+celltype #{@ct_name} {
+    entry #{@signature.get_name} #{@entry_port_name};
+    FACTORY {
+		write("$ct$_tecsgen.h", "#include \\"extsvc_fncode.h\\"");
+    };
+};
+EOT
+        file2.close
+    else
+      @@generated_celltype[ @ct_name ] << self
+    end
+    file.print "import( \"#{$gen}/#{@ct_name}.cdl\" );\n"
+
+=begin
+    # TODO: send. receive å¯¾å¿
+    send_receive = []
+    if @signature != nil then
+      @signature.each_param{ |fd,param|
+        dir =param.get_direction
+        case dir
+        when :SEND, :RECEIVE
+          send_receive << [ dir, fd, param ]
+        end
+      }
+    end
+=end
+
+=begin
+composite #{@ct_name} {
+    entry #{@signature.get_name} #{@entry_port_name};
+    call #{@signature.get_name} #{@call_port_name};
+
+    cell #{@ct_name}Client #{@cell_name}Client{
+    };
+
+    [active]
+    cell #{@ct_name}Server #{@cell_name}Server{
+        #{@call_port_name} => composite.#{@call_port_name};
+    };
+
+    composite.#{@entry_port_name} => #{@cell_name}.#{@entry_port_name};
+};
+=end
+
+  end
+
+  #===  through cell ã³ã¼ããçæ
+  #
+  #
+  def gen_through_cell_code( file )
+
+    # gen_plugin_decl_code( file )  this is called from super.
+
+    # ã»ã«ãæ¢ã
+    # path =["::",@next_cell.get_name]  # mikan namespace
+    # cell = Namespace.find( path )
+    # cell = Namespace.find( @next_cell.get_namespace_path )
+
+    ##### ã¯ã©ã¤ã¢ã³ãå´ã®ã»ã«ã®çæ #####
+    # file.print "[domain(HRP, \"kernel\")]"
+    nest = @start_region.gen_region_str_pre file
+    nest_str = "  " * nest
+
+    # ã¯ã©ã¤ã¢ã³ãå´ãã£ã³ãã«ã®çæ
+    # æ¡å¼µãµã¼ãã¹ã³ã¼ã«å¼åºã
+    file.print <<EOT
+/* HRPSVC0003 */
+#{nest_str}  //  Client Side Channel
+#{nest_str}  cell #{@ct_name} #{@cell_name}{
+#{nest_str}  };
+
+EOT
+
+    @start_region.gen_region_str_post file
+    file.print "\n\n"
+
+    ##### ãµã¼ãã¼å´ã®ã»ã«ã®çæ #####
+    # print "######  #{@cell_name_body} ... #{@ct_name_body} #{@@generated_cell[ @ct_name_body ].class}  #####\n"
+
+    if @@generated_cell[ @ct_name_body ] then
+      file.print "/* cell #{@ct_name_body} #{@@generated_cell[ @ct_name_body ]}: already generated. */\n"
+    else
+      @@generated_cell[ @ct_name_body ] = @cell_name_body
+      nest = @end_region.gen_region_str_pre file
+      nest_str = "  " * nest
+      if @next_cell_port_subscript then
+        subscript = '[' + @next_cell_port_subscript.to_s + ']'
+      else
+        subscript = ""
+      end
+
+      # ãµã¼ãã¼å´ãã£ã³ãã«ã®çæ 
+      # æ¡å¼µãµã¼ãã¹ã³ã¼ã«æ¬ä½
+      file.print <<EOT
+
+/* HRPSVC0004 */
+#{nest_str}  //  Server Side Channel
+#{nest_str}  cell #{@ct_name_body} #{@cell_name_body}{
+#{nest_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
+#{nest_str}  };
+EOT
+
+      @end_region.gen_region_str_post file
+
+      file2 = AppFile.open( "#{$gen}/tecsgen.cfg" )
+      file2.print "\n/* Generated by HRPSVCPlugin */\n\n"
+      file2.print <<EOT
+/* HRPSVC0005 */
+#include "#{@ct_name_body}_factory.h"
+EOT
+      file2.close
+
+      # callee_cell ã®get_restricted_regions ãå¼ã³åºãã¦ãã
+      # restrict ãåç
+§ãããå°ãã¤ãããã
+      @callee_cell.get_restricted_regions( :dummy_entry_name, :dummy_func_name )
+    end
+  end
+
+  #===  åãå£é¢æ°ã®æ¬ä½(Cè¨èª)ãçæãã
+  #     éå¸¸ã§ããã°ãã¸ã§ãã¬ã¼ã¿ã¯åãå£é¢æ°ã®ãã³ãã¬ã¼ããçæãã
+  #     ãã©ã°ã¤ã³ã®å ´åãå¤æ´ããå¿
+è¦ã®ãªãã»ã«ã¿ã¤ãã³ã¼ããçæãã
+  #file::           FILE        åºåå
+ãã¡ã¤ã«
+  #b_singleton::    bool        true if singleton
+  #ct_name::        Symbol
+  #global_ct_name:: string
+  #sig_name::       string
+  #ep_name::        string
+  #func_name::      string
+  #func_global_name:: string
+  #func_type::      class derived from Type
+  def gen_ep_func_body( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+        # puts "generate ep_func for #{ct_name}"
+
+        #
+        #  æ¡å¼µãµã¼ãã¹ã³ã¼ã«å¼åºãå´ã®é¢æ°çæ
+        #
+        #  å®æå½¢ã®ã¤ã¡ã¼ã¸
+        #  
+        # ER_UINT
+        # eThroughEntry_write(CELLIDX idx, const char* buffer, uint_t length)
+        # {
+        #   ER_UINT  retval;
+        #   tHRPSVCPlugin_<Sig>SVCCaller_<Cell>_<Entry>_CB    *p_cellcb;
+        #   if( VALID_IDX( idx ) ){
+        #       p_cellcb = tHRPSVCPlugin_<Sig>SVCBody_<Cell>_<Entry>_GET_CELLCB(idx);
+        #   }else{
+        #       /* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿° */
+        #   }
+        # 
+        #   retval = (ER_UINT)cal_svc( TFN_TECSGEN_ORIGIN + svcid, 
+        #                              (intptr_t)par1, (intptr_t)par2, 0, 0, 0 );
+        #
+        #   return retval;
+        # }
+
+        if ! func_type.get_type.kind_of?( VoidType ) then
+            file.print( "  #{func_type.get_type_str}  retval;\n" )
+        end
+
+        # p "celltype_name, sig_name, func_name, func_global_name"
+        # p "#{ct_name}, #{sig_name}, #{func_name}, #{func_global_name}"
+
+        delim = ""
+        if ! func_type.get_type.kind_of?( VoidType ) then
+            file.print( "  retval = (#{func_type.get_type_str})" )
+        else
+            file.print( "  " )
+        end
+
+        #file.print( "#{@call_port_name}_#{func_name}(" )
+        SVCManage.set_func_id( "#{@ct_name_body}_#{func_name}" )
+        svcid = SVCManage.get_func_id( "#{@ct_name_body}_#{func_name}" )
+        #file.print( "cal_svc( #{@ct_name_body}_#{func_name}" )
+        file.print( "cal_svc( TFN_TECSGEN_ORIGIN + #{svcid.to_s}" )
+
+        #    if ( ! b_singleton ) then
+        #      file.print( " tecs_this" )
+        #      delim = ","
+        #    end
+
+        i = 0
+        passed_param = {}
+        params.each{ |param|
+            delim = ","
+            file.printf( "#{delim} (intptr_t)#{param.get_name}" )
+            passed_param[i] = param.get_name
+            i += 1
+        }
+
+        while(i < NUM_SVC_ARG_MAX) do
+            delim = ","
+            file.printf( "#{delim} 0" )
+            passed_param[i] = "par#{i+1}"
+            i += 1
+        end
+
+        file.print( " );\n\n" )
+
+        if ! func_type.get_type.kind_of?( VoidType ) then
+            file.print( "  return retval;\n" )
+        end
+
+        #
+        #  æ¡å¼µãµã¼ãã¹ã³ã¼ã«æ¬ä½å´ã®é¢æ°çæ
+        #
+        #  å®æå½¢ã®ã¤ã¡ã¼ã¸
+        #  
+        # ER_UINT
+        # eThroughEntry_write(CELLIDX idx, const char* buffer, uint_t length)
+        # {
+        #   ER_UINT  retval;
+        #   tHRPSVCPlugin_<Sig>SVCBody_<Cell>_<Entry>_CB    *p_cellcb;
+        #   if( VALID_IDX( idx ) ){
+        #       p_cellcb = tHRPSVCPlugin_<Sig>SVCBody_<Cell>_<Entry>_GET_CELLCB(idx);
+        #   }else{
+        #       /* ã¨ã©ã¼å¦çã³ã¼ããããã«è¨è¿° */
+        #   }
+        # 
+        #   retval = (ER_UINT)cal_svc( TFN_TECSGEN_ORIGIN + svcid, 
+        #                              (intptr_t)par1, (intptr_t)par2, 0, 0, 0 );
+        #
+        #   return retval;
+        # }
+            file2 = AppFile.open( "#{$gen}/#{@ct_name_body}.c" )
+            if @b_printed_include_stdint == false then
+              file2.print <<EOT
+#ifndef SIZE_MAX
+#define  SIZE_MAX   (~0UL)
+#endif
+
+EOT
+              @b_printed_include_stdint = true
+            end
+
+            if func_type.get_type.kind_of?( VoidType ) then
+                retval_assign = ""
+            else
+                retval_assign = "retval = (ER_UINT)"
+            end
+
+            file2.print <<EOT
+/* HRPSVC0006 */
+ER_UINT
+#{@ct_name_body}_#{func_name}(intptr_t #{passed_param[0]}, intptr_t #{passed_param[1]}, intptr_t #{passed_param[2]}, intptr_t #{passed_param[3]}, intptr_t #{passed_param[4]}, ID cdmid)
+{
+    ER_UINT retval = E_OK;
+
+EOT
+
+            # 
+            #  ã¨ã©ã¼ãã§ãã¯å¦çã®çæ
+            #
+
+            # 
+            #  å¼åºãå
+ãã¡ã¤ã³ã®ãã§ãã¯
+            #   * private method: gen_caller_check_codeåç
+§
+            #
+            generated_check_code = gen_caller_check_code(func_name)
+            check_code = generated_check_code["check_code"]
+            user_cannot_callable = generated_check_code["user_cannot_callable"]
+
+            # 
+            #  ãã©ã¡ã¼ã¿ã«ãã¤ã³ã¿ãå­å¨ããå ´åï¼å¼åºãå
+ã¿ã¹ã¯ã«å¯¾ãã
+            #  ã¢ã¯ã»ã¹æ¨©ã®ãã§ãã¯å¦çãåºåãã
+            #  â» cdmidãã«ã¼ãã«ãã¡ã¤ã³(æ¡å¼µãµã¼ãã¹ã³ã¼ã«å¼åºãä¸­ã®ã¦ã¼ã¶
+            #    ãã¡ã¤ã³ãå«ã)ã§ããã°prb_memã®å¦çãã¹ã­ãããï¼åæ®µã®
+            #    æ¡å¼µãµã¼ãã¹ã³ã¼ã«ã®ã¿prb_memãå¼åºãå
+ã¿ã¹ã¯ã«çºè¡ãã
+            #
+            num = 0
+            params.each{ |param|
+                if param.get_declarator.get_ptr_level > 0 then
+                    align_check_str = "!ALIGN_TYPE(#{passed_param[num]}, #{param.get_type.get_referto.get_type_str}) || "
+                  
+                    if param.get_type.get_referto.kind_of?(IntType) then
+                        case param.get_type.get_referto.get_bit_size
+                        when -11, -1, 8   # char, char_t, int8_t (ç¡ç¬¦å·å«ã)
+                        #
+                        #  charãã¼ã¿ã®å ´åï¼ALIGN_TYPEã¯å¿
+ãTRUE
+                        #  ã¨ãªãã®ã§ï¼ã¨ã©ã¼ãã§ãã¯ãçç¥
+                        #  charåã®@bit_sizeã¯-11
+                        #  tecsgen/tecslib/core/types.rbãåç
+§
+                        #
+                          align_check_str = ""
+                        end
+                    end
+                    if param.get_direction == :IN then
+                        #
+                        #  å
+¥å([in])ã®ãã¤ã³ã¿ãã©ã¡ã¼ã¿ã¯ï¼å¼åºãå
+ã¿ã¹ã¯ã«
+                        #  TPM_READ(èª­åºãå¯è½)ã®ã¢ã¯ã»ã¹æ¨©ãå¿
+è¦
+                        #
+                        # äºéãã¤ã³ã¿ãä¸å¯ã®ãããsize_is ã¨ string ãåæã«è¨­å®ããããã¨ã¯ãªã
+                        prb_func = "prb_mem"
+                        if param.get_size then
+                          size_str = param.get_size.to_s
+                        elsif param.get_string == -1 then
+                          size_str = "SIZE_MAX"
+                          prb_func = "prb_str"
+                        elsif param.get_string then
+                          size_str = param.get_string.to_s
+                          prb_func = "prb_str"
+                        else
+                          size_str = "1"
+                        end
+                        check_code.concat <<EOT
+        /* HRPSVC0007 */
+        if (#{align_check_str}#{prb_func}((void *)#{passed_param[num]}, sizeof(#{param.get_type.get_referto.get_type_str}) * (#{size_str}), TSK_SELF, TPM_READ) != E_OK) {
+            return E_MACV;
+        }
+EOT
+
+                    elsif param.get_direction == :OUT || param.get_direction == :INOUT then
+                        #
+                        #  åºå([out])ã®ãã¤ã³ã¿ãã©ã¡ã¼ã¿ã¯ï¼å¼åºãå
+ã¿ã¹ã¯ã«
+                        #  TPM_WRITE(æ¸è¾¼ã¿å¯è½)ã®ã¢ã¯ã»ã¹æ¨©ãå¿
+è¦
+                        #
+                        prb_func = "prb_mem"
+                        if param.get_size then
+                          size_str = param.get_size.to_s
+                        elsif param.get_string then          # å¼æ°ãªãã® string ã¯ãªã
+                          size_str = param.get_string.to_s
+                          # prb_func = "prb_str"             # out, inout ã®å ´åãå¿
+ãé åãç¢ºä¿ãã. prb_mem ãç¨ãã
+                        else
+                          size_str = "1"
+                        end
+                        check_code.concat <<EOT
+        /* HRPSVC0008 */
+        if (#{align_check_str}#{prb_func}((void *)#{passed_param[num]}, sizeof(#{param.get_type.get_referto.get_type_str}) * (#{size_str}), TSK_SELF, TPM_WRITE) != E_OK) {
+            return E_MACV;
+        }
+EOT
+
+                    end
+                end
+                num += 1
+            }
+
+            # 
+            #  å¼åºãå
+ãã«ã¼ãã«ãã¡ã¤ã³ã®ã¿è¨±å¯ããã¦ããå ´åï¼
+            #  ãã¹ã¦ã®ã¦ã¼ã¶ãã¡ã¤ã³ããã®å¼åºãã«å¯¾ãï¼E_OACVãè¿ã
+            #
+            if user_cannot_callable
+                check_code = "\t\treturn E_OACV;"
+            end
+
+            if check_code != ""
+                # 
+                #  å¼åºãå
+ãã«ã¼ãã«ãã¡ã¤ã³ã®å ´åï¼ã¢ã¯ã»ã¹æ¨©ã®ãã§ãã¯
+                #  å¦çãã¹ã­ããããã
+                #
+                file2.print <<eot
+    if (cdmid != TDOM_KERNEL) {
+#{check_code}
+    }
+eot
+            end
+
+            # 
+            #  æ¡å¼µãµã¼ãã¹ã³ã¼ã«æ¬ä½(æ¬æ¥ã®åãå£é¢æ°)ãå¼ã³åºã
+            #
+            file2.print"    #{retval_assign}#{@call_port_name}_#{func_name}("
+
+            delim = ""
+            num = 0
+            params.each{ |param|
+                file2.print "#{delim}"
+                delim = ", "
+                file2.print "(#{param.get_type.get_type_str})"
+                file2.print passed_param[num]
+                file2.print param.get_type.get_type_str_post
+                num += 1
+            }
+
+            file2.print ");\n"
+
+            file2.print "\n    return retval;\n"
+            file2.print "}\n\n"
+
+            file2.close
+
+            # 
+            #  æ¡å¼µãµã¼ãã¹ã³ã¼ã«ã®ç»é²
+            #
+            file2 = AppFile.open( "#{$gen}/tecsgen.cfg" )
+            file2.print "\n/* Generated by HRPSVCPlugin */\n\n"
+            file2.print <<EOT
+/* HRPSVC0009 */
+KERNEL_DOMAIN{
+    DEF_SVC( TFN_TECSGEN_ORIGIN + #{svcid.to_s}, { TA_NULL, #{@ct_name_body}_#{func_name}, SSZ_#{func_global_name} } );
+}
+EOT
+            file2.close
+
+            # 
+            #  æ¡å¼µãµã¼ãã¹ã³ã¼ã«ç»é²ã«å¿
+è¦ãªæ
+å ±ããããã«åºå
+            #   - æ¡å¼µãµã¼ãã¹ã³ã¼ã«å¼åºãæã®ãã§ãã¯ã§ä½¿ç¨ããã¹ã¿ãã¯ãµã¤ãºãåºå
+            #   - æ¡å¼µãµã¼ãã¹ã³ã¼ã«ã¨ãã¦ç»é²ããé¢æ°åã®externå®£è¨ãåºå
+            #
+            file2 = AppFile.open( "#{$gen}/#{@ct_name_body}_factory.h" )
+            file2.print "\n/* Generated by HRPSVCPlugin */\n\n"
+            file2.print <<EOT
+/* HRPSVC0010 */
+#ifndef SSZ_#{func_global_name}
+#define SSZ_#{func_global_name}	DefaultExtsvcStackSize
+#endif /* SSZ_#{func_global_name} */
+
+/* HRPSVC0011 */
+extern ER_UINT #{@ct_name_body}_#{func_name}(intptr_t par1, intptr_t par2, intptr_t par3, intptr_t par4, intptr_t par5, ID cdmid);
+EOT
+            file2.close
+  end
+
+  def get_callee_cell
+      return @callee_cell
+  end
+
+  def get_caller_cell
+      return @caller_cell
+  end
+
+  def get_callee_ep_name
+      return @join.get_port_name
+  end
+
+  private
+  # 
+  #  æ¡å¼µãµã¼ãã¹ã³ã¼ã«æ¬ä½ã«ãããï¼å¼åºãå
+ãã§ãã¯ã®ã³ã¼ãã
+  #  åºåãã
+  #  gen_ep_func_body ããã®ã¿å¼ã³åºããã
+  #  å¼æ°: å¯¾è±¡ã®é¢æ°å
+  #  è¿ãå¤: ä¸è¨ã®ããã·ã¥
+  #    {"check_code"=>åºåããã¨ã©ã¼ãã§ãã¯ã³ã¼ã, 
+  #     "user_cannot_callable"=>ã¦ã¼ã¶ãã¡ã¤ã³ãå¼åºãä¸å¯è½ãã©ããã®ãã©ã°}
+  #
+  def gen_caller_check_code(func_name)  
+    dbgPrint "gen_caller_check_code(func_name): #{@callee_cell.get_name}\n"
+      # 
+      #  ã¨ã©ã¼ãã§ãã¯å¦ç
+      #
+      check_code = ""
+      user_cannot_callable = false
+      all_domain_callable = false
+      caller_unrestricted = false
+
+      # 
+      #  å¼åºãå
+ãã¡ã¤ã³ã®ãã§ãã¯å¦ç
+      #  callable_domains: æ¡å¼µãµã¼ãã¹ã³ã¼ã«ãå¼åºãå¯è½ãªãã¡ã¤ã³ã®ãªã¹ã
+      #    - ç¡æå±ã®ã»ã«ããçµåããã¦ããå ´åï¼ãã¹ã¦ã®ã»ã«ã«å¯¾ãã¦ï¼
+      #    ãcallable?ããã§ãã¯ãï¼å¼åºãå¯è½ãªãã¹ã¦ã®ãã¡ã¤ã³ãè¿ã
+      #    - ç¡æå±ä»¥å¤ã®ã»ã«ããçµåããã¦ããå ´åï¼ãã®ã»ã«ã«å¯¾ãã¦
+      #      callable?ããã§ãã¯ãï¼å¼åºãå¯è½ã§ããã°ï¼ãã®ãã¡ã¤ã³ãè¿ã
+      #
+      callable_domains = []
+      @@generated_celltype[ @ct_name_body ].each { |svcplugin|
+          if svcplugin.get_caller_cell.get_region.get_domain_root.get_domain_type.get_option == "OutOfDomain"
+              # ç¡æå±ãã¤ active ãªå ´åããrestrict ã«å¾ã
+              # if svcplugin.get_caller_cell.get_celltype.is_active?
+              #    #
+              #    #  ç¡æå±ãã¤activeãªã»ã«ã¯ãTECSããå­å¨ãèªè­ããã¦ããªãã®ã
+              #    #  å«ãä»»æã®ãã¡ã¤ã³ããå¼ã³åºãããå¯è½æ§ãå­å¨ãã
+              #    #
+              #    caller_unrestricted = true
+              # else
+              #     # 
+              #     #  ç¡æå±ããæ¥ç¶ããã¦ããå ´åã¯ï¼ãã¹ã¦ã®ã»ã«ã®
+              #     #  restrictããã§ãã¯
+              #     #
+              #     Cell.get_cell_list2.each { |cell|
+              #         if cell.callable?(svcplugin.get_callee_cell, svcplugin.get_callee_ep_name, func_name)
+              #             callable_domains << cell.get_region.get_domain_root
+              #         end
+              #     }
+              #     print "callable_domains: "
+              #     callable_domains.each{ |dm| print dm.get_name, " " }
+              #     print "\n"
+              # end
+
+              # restrict æå®ãããå ´åã«ã¯ãããã«å¾ãããããªããã°ããã§ãã¯ããªã
+              callable_domains = @callee_cell.get_restricted_regions( get_callee_ep_name, func_name )
+              if callable_domains == nil then
+                caller_unrestricted = true
+              end
+              #  print "restrict_list: "
+              #  delim = ""
+              #  callable_domains.each{ |domain|
+              #    print delim, domain
+              #    delim = ", "
+              #  }
+              #  print "\n"
+
+          elsif svcplugin.get_caller_cell.callable?( svcplugin.get_callee_cell, svcplugin.get_callee_ep_name, func_name )
+              # 
+              #  ç¹å®ã®ãã¡ã¤ã³ããæ¥ç¶ããã¦ããå ´åã¯ï¼å¼åºãå
+ã»ã«ã®
+              #  restrictããã§ãã¯
+              #
+              callable_domains << svcplugin.get_caller_cell.get_region.get_domain_root
+          else
+              # 
+              #  ç¡æå±ããçµåããã¦ãããï¼ç¹å®ã®å¼åºãå
+ãã¡ã¤ã³ã«ã¢ã¯ã»ã¹æ¨©
+              #  ããªãå ´åï¼callable_domainsã¯ç©ºã¨ãªã
+              #
+              # pp "#{svcplugin.get_caller_cell.get_name} cannot call #{svcplugin.get_callee_cell.get_name}_#{svcplugin.get_callee_ep_name}_#{func_name}"
+          end
+      }
+
+      if caller_unrestricted
+          # pp "caller_unrestricted: #{@ct_name_body}"
+          return {"check_code"=>"", "user_cannot_callable"=>false}
+      end
+
+      # 
+      #  éè¤ãåé¤
+      #
+      callable_domains.uniq!
+      # 
+      #  ç¡æå±ã«å¯¾ãããã¡ã¤ã³ãã§ãã¯ã¯å®æ½ããªã
+      #  ã«ã¼ãã«ãã¡ã¤ã³ã«å¯¾ãããã¡ã¤ã³ãã§ãã¯ã¯å®æ½ããªã
+      #
+      callable_domains = callable_domains.select { |domain|
+          ((domain.get_domain_type.get_option != "OutOfDomain") && \
+           (domain.get_domain_type.get_option != "kernel"))
+      }
+      # pp "callable_domains"
+      # pp callable_domains.map{|domain| domain.get_name }
+      # 
+      #  ãã¹ã¦ã®ã¦ã¼ã¶ãã¡ã¤ã³ããå¼åºãå¯è½ãªå ´åï¼ãã¡ã¤ã³ãã§ãã¯ã¯
+      #  å®æ½ããªã
+      #
+      all_domain_regions = DomainType.get_domain_regions[:HRP].select { |reg|
+          ((reg.get_domain_type.get_option != "OutOfDomain") && \
+           (reg.get_domain_type.get_option != "kernel"))
+
+      }
+      # pp "all domains"
+      # pp all_domain_regions.map {|reg| reg.get_name}
+      if all_domain_regions.all? {|reg| callable_domains.include?(reg)}
+          all_domain_callable = true
+      end
+
+      # 
+      #  å¼åºãå
+ãã¡ã¤ã³ã®ãã§ãã¯å¦çæ¬ä½ã®çæ
+      #
+      if callable_domains.length == 0
+        dbgPrint "callable_domain.length = 0\n"
+          # 
+          #  ã¦ã¼ã¶ãã¡ã¤ã³ããå¼åºãä¸å¯è½ãªå ´åã¯
+          #  åå¥ã®ã¨ã©ã¼ãã§ãã¯ã¯ããï¼åç­ç¡ç¨ã§E_OACVãè¿ã
+          #
+          user_cannot_callable = true
+      elsif callable_domains.length == 1
+        dbgPrint "callable_domain.length = 1\n"
+          # 
+          #  å¼åºãå¯è½ãªã¦ã¼ã¶ãã¡ã¤ã³ãåä¸ã®å ´åã¯
+          #  cdmid != <domainå> ã®å½¢å¼ã§ãã§ãã¯ãã
+          #
+          check_code += "\t/* HRPSVC0012.1 */\n"
+          check_code += "\tif (cdmid != #{callable_domains[0].get_name}) {\n"
+      elsif callable_domains.length > 1 && !all_domain_callable
+        dbgPrint "callable_domain.length > 1 && not all_domains \n"
+          # 
+          #  å¼åºãå¯è½ãªã¦ã¼ã¶ãã¡ã¤ã³ãè¤æ°ã®å ´åã¯
+          #  TACP(cdmid) & (TACP(<domainå>) | ...) != 0U
+          #  ã®å½¢å¼ã§ãã§ãã¯ãã
+          #
+          check_code += "\t/* HRPSVC0012.2 */\n"
+          check_code += "\tif((TACP(cdmid) & ("
+          check_code += (callable_domains.map { |domain| "TACP(#{domain.get_name})"}).join("|")
+          check_code += ")) != 0U) {\n"
+      else
+        dbgPrint "callable_all_domains\n"
+      end
+      if check_code != ""
+          # 
+          #  å¼åºãå¯è½ãªã¦ã¼ã¶ãã¡ã¤ã³ã®ãã§ãã¯ãããå ´åã¯
+          #  ã¨ã©ã¼ã³ã¼ããè¿ãããã®ã³ã¼ããåºåãã
+          #
+          check_code += <<EOS
+            /* HRPSVC0013 */
+            return E_OACV;
+        }
+EOS
+      end
+
+      return {"check_code"=>check_code, "user_cannot_callable"=>user_cannot_callable}
+  end
+
+  #---------------------------------------------------------#
+  #=== ã·ã°ããã£ã®ãã§ãã¯
+  def check_signature signature
+    signature.get_function_head_array.each{ |fh|
+      type = fh.get_return_type
+      check_return_type signature, fh, type
+      if fh.get_paramlist.get_items.length > NUM_SVC_ARG_MAX then
+        cdl_error( "HSV0005 $1.$2: # of parameter more than #{NUM_SVC_ARG_MAX}", signature.get_name, fh.get_name )
+      end
+      fh.get_paramlist.get_items.each{ |param|
+        check_param signature, fh, param
+      }
+    }
+  end
+  #=== æ»ãå¤ã®åã®ãã§ãã¯
+  # ER, ER_UINT ã¯æ¨å¥¨ãããå
+  # æ´æ°ããã¼ã«ãvoid ã¯å¯è½ãä»ã¯ä¸å¯
+  def check_return_type signature, fh, type
+    ot = type.get_original_type
+    if( type.get_type_str == "ER" || type.get_type_str == "ER_UINT" ) then
+      # OK!
+    elsif ot.kind_of?( IntType ) || ot.kind_of?( VoidType ) || ot.kind_of?( BoolType ) then
+      cdl_warning( "HSW0001 $1.$2: $3 return type cannot get access violation error", signature.get_name, fh.get_name, type.get_type_str.downcase )
+      check_intptr "#{signature.get_name}.#{fh.get_name} return type", type
+    else
+      cdl_error( "HSV0001 $1.$2 return type $3 cannot be used", signature.get_name, fh.get_name, type.get_type_str.to_s+type.get_type_str_post.to_s )
+    end
+  end
+  #=== å¼æ°ã®åã®ãã§ãã¯
+  def check_param signature, fh, param
+    type = param.get_type
+    ot = type.get_original_type
+    dir = param.get_direction
+    case dir
+    when :IN
+      if ot.kind_of?( IntType ) || ot.kind_of?( BoolType ) then
+        # OK!
+        check_intptr "#{signature.get_name}.#{fh.get_name}.#{param.get_name}", type
+      elsif ot.kind_of? PtrType then
+        check_ptr signature, fh, param, dir
+      else
+        cdl_error( "HSV0002 $1.$2.$3 $4 param type cannot be used", signature.get_name, fh.get_name, param.get_name, type.get_type_str.to_s+type.get_type_str_post.to_s )
+      end
+    when :OUT, :INOUT
+      if ot.kind_of? PtrType then
+        check_ptr signature, fh, param, dir
+      else
+        # error
+      end
+    when :SEND, :RECEIVE
+      cdl_error( "HSV0008 $1.$2.$3 param direction '$4' cannot be used", signature.get_name, fh.get_name, param.get_name, param.get_direction.to_s.downcase )
+    end
+  end
+  def check_ptr signature, fh, param, dir
+    type = param.get_type.get_referto
+    ot = type.get_original_type
+    if ot.kind_of?( IntType ) || ot.kind_of?( BoolType ) || ot.kind_of?( FloatType ) then
+      # OK!
+      check_intptr "#{signature.get_name}.#{fh.get_name}.#{param.get_name}", type
+    elsif ot.kind_of? PtrType then
+      cdl_error( "HSV0003 $1.$2.$3 multi-pointer type cannot be used", signature.get_name, fh.get_name, param.get_name, type.get_type_str.to_s+type.get_type_str_post.to_s )
+    elsif  ot.kind_of? StructType then
+      check_struct signature, fh, param
+    else
+      cdl_error( "HSV0004 $1.$2.$3 $4 type cannot be used", signature.get_name, fh.get_name, param.get_name, type.get_type_str.to_s+type.get_type_str_post.to_s )
+    end
+    if ( dir == :OUT || dir == :INOUT) && param.get_string == -1 then
+      cdl_error( "HSV0009 $1.$2.$3 string argment is necessary for out/inout parameter", signature.get_name, fh.get_name, param.get_name )
+    end
+  end
+  def check_struct signature, fh, param
+    type = param.get_type.get_referto
+    ot = type.get_original_type
+    ot.get_members_decl.get_items.each{ |decl|
+      type = decl.get_type
+      ot = type.get_original_type
+      if ot.kind_of?( IntType ) || ot.kind_of?( BoolType ) || ot.kind_of?( FloatType ) then
+        # OK!
+        check_intptr "#{signature.get_name}.#{fh.get_name}.#{param.get_name}.#{decl.get_name} member", type
+      else
+        dbgPrint "struct member #{decl.get_name} #{type} #{decl.get_type} #{decl.get_type.get_original_type}\n"
+        if( decl.get_type.get_original_type.kind_of? ArrayType ) then
+          dbgPrint "member array type #{decl.get_type.get_original_type.get_type} #{decl.get_type.get_original_type.get_type.get_original_type}\n"
+          check_struct_member_array signature, fh, param, decl
+        else
+          cdl_error( "HSV0006 $1.$2.$3 $4 type cannot be used as struct member", signature.get_name, fh.get_name, param.get_name, type.get_type_str.to_s+type.get_type_str_post.to_s )
+        end
+      end
+    }
+  end
+  def check_struct_member_array signature, fh, param, member_decl
+    # p "check_struct_member_array: #{member_decl.get_type.get_type_str}"
+    type = member_decl.get_type.get_type
+    ot = type.get_original_type
+    if ot.kind_of?( IntType ) || ot.kind_of?( BoolType ) || ot.kind_of?( FloatType ) then
+      # OK!
+      check_intptr "#{signature.get_name}.#{fh.get_name}.#{param.get_name}.#{member_decl.get_name} member", type
+    else
+      cdl_error( "HSV0007 $1.$2.$3 $4 type cannot be used as struct member", signature.get_name, fh.get_name, param.get_name, type.get_type_str.to_s+type.get_type_str_post )
+    end
+  end
+  def check_intptr msg, type
+    dbgPrint "check_intptr IN\n"
+    t = type
+    while( t.kind_of? DefinedType )
+      dbgPrint "check_intptr #{msg} #{t.get_type_str} #{t.get_original_type.get_type_str}\n"
+      tstr = t.get_type_str
+      tstr.sub!( /const /, "" )
+      tstr.sub!( /volatile /, "" )
+      if tstr == "intptr_t" || tstr == "uintptr_t" then
+        cdl_info( "HSI0001 $1 type '$2' not checked by plugin", msg, type.get_type_str )
+      end
+      t = t.get_type
+    end
+  end
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPTaskPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPTaskPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/HRPTaskPlugin.rb	(revision 374)
@@ -0,0 +1,127 @@
+# coding: utf-8
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#  $Id$
+#++
+
+require_tecsgen_lib "HRPKernelObjectPlugin.rb"
+require_tecsgen_lib "HRPKernelObjectManager.rb"
+#== celltype ãã©ã°ã¤ã³ã®å
+±éã®è¦ªã¯ã©ã¹
+class HRPTaskPlugin < HRPKernelObjectPlugin
+    ##
+    # oyama: add to avoid Ruby exception in code generation phase.
+    def new_cell cell
+      region = cell.get_region
+      dbgPrint "HRPTaskCelltypePlugin new_cell=#{cell.get_name} region=#{region.get_name}\n"
+      domainOption = cell.get_region.get_domain_root.get_domain_type.get_option
+      if domainOption == "OutOfDomain"
+        cdl_error( "HRP9999 HRP task '$1' must belong to a domain", cell.get_name )
+      end
+    end
+
+    # # ATT_MODãçææ¸ã¿ãã©ãã                   # 2017.8.27
+    # @@generate_memory_module = false
+
+    #
+    #  CRE_TSKã®åºå
+    #  file:: FILE:     åºåå
+ãã¡ã¤ã«
+    #  cell :: Cell ã¿ã¹ã¯ã»ã«ã¤ã³ã¹ã¿ã³ã¹
+    #  val :: Hash {attr => string}:   ã«ã¼ãã«ãªãã¸ã§ã¯ãã®å±æ§ã®è§£æçµæ
+    #  tab :: string: ã¿ã
+    #
+    def print_cfg_cre(file, cell, val, tab)
+        val[:id] = val[:id].gsub( /(^|[^\$])\$id\$/, "\\1#{@celltype.get_name.to_s}_#{cell.get_name.to_s}" )
+        # $cbp$ã®ä»£ãã
+        cell_IDX = @celltype.get_name_array(cell)[7]
+        # CRE_TSKã®çæ
+        dbgPrint "assign task plugin\n"
+        domainOption = cell.get_region.get_domain_root.get_domain_type.get_option
+        # if cell.get_region.get_region_type == :DOMAIN
+        if domainOption != "OutOfDomain"
+            if val[:systemStackSize] == "0"
+                # 
+                #  ã·ã¹ãã ã¹ã¿ãã¯ã®å®ç¾©ãçç¥
+                #
+                file.print <<EOT
+CRE_TSK(#{val[:id]}, { #{val[:attribute]}, #{cell_IDX}, tTask_start, #{val[:priority]}, #{val[:stackSize]}, NULL });
+EOT
+            else
+                # 
+                #  ã·ã¹ãã ã¹ã¿ãã¯ã®å®ç¾©ãè¿½å 
+                #
+                file.print <<EOT
+CRE_TSK(#{val[:id]}, { #{val[:attribute]}, #{cell_IDX}, tTask_start, #{val[:priority]}, #{val[:stackSize]}, NULL, #{val[:systemStackSize]}, NULL });
+EOT
+            end
+        else
+            #
+            #  ç¡æå±ã®ã¿ã¹ã¯ã¯å­å¨ãã¦ã¯ãªããªãããï¼ã¨ã©ã¼ã¨ãã
+            #
+            raise "task #{val[:id]} must belong to a domain."
+        end
+    end
+
+    #
+    #  SAC_TSKã®åºå
+    #  file:: FILE:     åºåå
+ãã¡ã¤ã«
+    #  val :: Hash {attr => string}:   ã«ã¼ãã«ãªãã¸ã§ã¯ãã®å±æ§ã®è§£æçµæ
+    #  acv :: Hash {accessPatternx => string}:   ã¢ã¯ã»ã¹è¨±å¯ãã¯ã¿
+    #
+    def print_cfg_sac(file, val, acv)
+       # pp "SAC_TSK"
+       # pp val
+       file.puts "SAC_TSK(#{val[:id]}, { #{acv[:accessPattern1]}, #{acv[:accessPattern2]}, #{acv[:accessPattern3]}, #{acv[:accessPattern4]} });"
+    end
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCellPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCellPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCellPlugin.rb	(revision 374)
@@ -0,0 +1,284 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2017 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#++
+
+#== celltype ãã©ã°ã¤ã³ã®å
+±éã®è¦ªã¯ã©ã¹
+class MrubyBridgeCellPlugin < CellPlugin
+
+  # ãã©ã°ã¤ã³å¼æ°å => Proc
+  MrubyBridgePluginArgProc = { 
+      "ignoreUnsigned" => Proc.new { |obj,rhs| obj.set_ignoreUnsigned rhs },
+      "exclude_port" => Proc.new { |obj,rhs| obj.set_exclude_port rhs },
+      "exclude_port_func" => Proc.new { |obj,rhs| obj.set_exclude_port_func rhs },
+      "auto_exclude" => Proc.new { |obj,rhs| obj.set_auto_exclude rhs },
+  }
+  @@b_gen_post_code_by_dependent = false  # true if gen_post_code is called by MrubyBridgeCelltypePlugin
+  @@cell_list = {}      # gen_cdl_file'ed list to avoid duplicate generation
+  @@signature_list = {}
+
+  require_tecsgen_lib( "MrubyBridgeSignaturePlugin.rb" )
+
+  #@exclude_port::[ String(port_name) ] : 
+  #@exclude_port_func::{ [ String(port_name) ] => [ String(func_name) ] } : 
+  #@port_list::{ String(port_name) => String(include/exclude=func_name) }  : all included port and opt_string
+
+  #=== CellPlugin# initialize
+  #cell::     Cell        ã»ã«ï¼ã¤ã³ã¹ã¿ã³ã¹ï¼
+  # ãã®ã¡ã½ããã¯ãã»ã«ã®æ§æè§£æãçµãã£ãã¨ããã§å¼ã³åºããã
+  # ãã®æ®µéã§ã¯æå³è§£æãçµãã£ã¦ããªã
+  def initialize( cell, option )
+    dbgPrint "  #{self.class.name}: initialzie=#{cell.get_name} option=#{option}\n"
+    super
+    @cell = cell
+
+    # option
+    @b_ignoreUnsigned = false
+    @exclude_port = []
+    @exclude_port_func = {}
+    @b_auto_exclude = true     # auto_exclude = true by default 
+    MrubyBridgeSignaturePlugin.set_gen_post_code_by_dependent
+
+    @plugin_arg_str = CDLString.remove_dquote option
+    # @plugin_arg_str = option.gsub( /\A"(.*)/, '\1' )    # åå¾ã® "" ãåãé¤ã
+    # @plugin_arg_str.sub!( /(.*)"\z/, '\1' )
+    @plugin_arg_list = {}
+    dbgPrint "#{self.class.name}: initialzie: #{cell.get_name}\n"
+    @plugin_arg_check_proc_tab = MrubyBridgePluginArgProc
+    parse_plugin_arg
+
+    @port_list = {}         # set @port_list before return
+    ct = @cell.get_celltype
+    return if ct == nil     # error case
+
+    port_list = ct.get_port_list
+    if @exclude_port.length > 0 then
+      # ãã®å®è£
+ã§ã¯ãå­å¨ããªã port ãæå®ããã¦ããã§ãã¯ã§ããªã
+      # print "MRBBridgeCellPlugin: exclude list\n"
+      port_list.each{ |port|
+        if ! @exclude_port.include?( port.get_name.to_s ) then
+          # print "MRBBridgeCellPlugin: #{port.get_name} included\n"
+          @port_list[ port ] = ""
+        else
+          # print "MRBBridgeCellPlugin: #{port.get_name} excluded\n"
+        end
+      }
+    else
+      port_list.each{ |port|
+        @port_list[ port ] = ""
+      }
+    end
+
+    if @exclude_port_func.length > 0 then
+      @port_list.each{ |port, opt_str|
+        delim = ""
+        if @exclude_port_func.include?( port.get_name.to_s ) then
+          @exclude_port_func[ port.get_name.to_s ].each{ |func_name|
+            opt_str += delim + "exclude=" + func_name
+            delim = ","
+          }
+        end
+        @port_list[ port ] = opt_str
+      }
+    end
+  end
+
+  def gen_cdl_file file
+    dbgPrint "#{self.class.name}: gen_cdl_file: #{@cell.get_name}\n"
+
+    file.print <<EOT
+/* MrubyBridgeCellPlugin: generate for cell=#{@cell.get_name} */
+EOT
+
+    if @@cell_list[ @cell ] then
+      file.print <<EOT
+
+/*
+ * generate for #{@cell.get_name} duplicate and ignored.
+ * This might comes from generate for celltype.
+ */
+EOT
+      cdl_info( "MrubyBridgeCellPlugin: generate duplicate for cell '$1'", @cell.get_name )
+      return
+    end
+    @@cell_list[ @cell ] = @cell
+                
+    @port_list.each{ |port, opt_str|
+      next if port.get_signature == nil
+
+      case port.get_signature.get_context
+      when "task", "any"
+      else
+        next
+      end
+
+      if port.get_port_type == :ENTRY then
+        print "  MrubyBridgeCellPlugin: [cell.port] #{@cell.get_name}.#{port.get_name} => [mruby instance] TECS::T#{port.get_signature.get_name}.new( '#{@cell.get_name}#{port.get_name}Bridge' ) \n"
+        if @@signature_list[ port.get_signature ] == nil then
+          opt_str = "ignoreUnsigned=#{@b_ignoreUnsigned}, auto_exclude=#{@b_auto_exclude}, " + opt_str
+          # p "opt_str=#{opt_str}"
+
+          file.print <<EOT
+
+/* cell.port=#{@cell.get_name}.#{port.get_name} */
+generate( MrubyBridgePlugin, #{port.get_signature.get_namespace_path}, "#{opt_str}" );
+EOT
+          @@signature_list[ port.get_signature ] = true
+        end
+
+        # mikan option
+        nest = @cell.get_region.gen_region_str_pre file
+        nest_str = "  " * nest
+
+        file.print <<EOT
+#{nest_str}/* BridgeCell */
+#{nest_str}cell nMruby::t#{port.get_signature.get_name} #{@cell.get_name}#{port.get_name}Bridge {
+#{nest_str}    cTECS = #{@cell.get_namespace_path}.#{port.get_name};
+#{nest_str}};
+EOT
+        @cell.get_region.gen_region_str_post file
+      end
+    }
+  end
+
+  #=== å¾ãã® CDL ã³ã¼ããçæ
+  #ãã©ã°ã¤ã³ã®å¾ãã® CDL ã³ã¼ããçæ
+  #file:: File: 
+  def self.gen_post_code( file )
+    dbgPrint "#{self.name}: gen_post_code\n"
+    if ! @@b_gen_post_code_by_dependent then
+      gen_post_code_body file
+    end
+  end
+
+  def self.set_gen_post_code_by_dependent # by MrubyBridgeCelltypePlugin
+    dbgPrint "#{self.name}: set_gen_post_code_by_dependent\n"
+    @@b_gen_post_code_by_dependent = true
+    MrubyBridgeSignaturePlugin.set_gen_post_code_by_dependent
+  end
+
+  def self.gen_post_code_body file
+    # è¤æ°ã®ãã©ã°ã¤ã³ã® post_code ãä¸ã¤ã®ãã¡ã¤ã«ã«å«ã¾ãããããä»¥ä¸ã®ãããªè¦åºããã¤ãããã¨
+    # file.print "/* '#{self.class.name}' post code */\n"
+    dbgPrint "#{self.name}: gen_post_code_body\n"
+    MrubyBridgeSignaturePlugin.gen_post_code_body file
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° ignoreUnsigned
+  def set_ignoreUnsigned rhs
+    if rhs == "true" || rhs == nil then
+      @b_ignoreUnsigned = true
+    end
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° exclude_port
+  def set_exclude_port rhs
+    ports = rhs.split ','
+    ct = @cell.get_celltype
+    return if ct == nil    # error case
+    ports.each{ |rhs_port|
+      obj = ct.find( rhs_port.to_sym )
+      if( ( ! obj.instance_of? Port ) || obj.get_port_type != :ENTRY ) then
+        cdl_error( "MRB9999 exclude_port '$1' not found or not entry in celltype '$2'", rhs_port, ct.get_name )
+      else
+        # print "MRBBridgeCellPlugin: exclude #{rhs_port}\n"
+        @exclude_port << rhs_port
+      end
+    }
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° exclude_port_func
+  def set_exclude_port_func rhs
+    port_funcs = rhs.split ','
+    ct = @cell.get_celltype
+    return if ct == nil    # error case
+    port_funcs.each{ |rhs_port_func|
+      port_func = rhs_port_func.split '.'
+      if port_func.length != 2 then
+        cdl_error( "MRB9999 exclude_port_func: '$1' not in 'port.func' form", rhs_port_func )
+      end
+      obj = ct.find( port_func[0].to_sym )
+      if( ( ! obj.instance_of? Port ) || obj.get_port_type != :ENTRY ) then
+        cdl_error( "MRB9999 exclude_port_func: port '$1' not found in celltype '$2'", rhs_port, ct.get_name )
+      else
+        signature = obj.get_signature
+        next if signature == nil     # error case
+        if signature.get_function_head port_func[1].to_sym
+          # print "MRBBridgeCellPlugin: #{port_func[0]}.#{port_func[1]} exclude\n"
+          if @exclude_port_func[ port_func[0] ] then
+            @exclude_port_func[ port_func[0] ] <<  port_func[1]
+          else
+            @exclude_port_func[ port_func[0] ] = [ port_func[1] ]
+          end
+        else
+          cdl_error( "MRB9999 exclude_port_func: func '$1' not found in port '$2' celltype $3",
+                     port_func[1], port_func[0], ct.get_name )
+        end
+      end
+    }
+  end
+  #=== ãã©ã°ã¤ã³å¼æ° auto_exclude
+  def set_auto_exclude rhs
+    # print "MrubyBridgeCellPlugin: auto_exclude=#{rhs}\n"
+    if rhs == "false" then
+      @b_auto_exclude = false
+    elsif rhs == "true" then
+      @b_auto_exclude = true     # auto_exclude = true by default 
+    else
+      cdl_warning( "MRB9999 auto_exclude: unknown rhs value ignored. specify true or false" )
+    end
+  end
+
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCelltypePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCelltypePlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCelltypePlugin.rb	(revision 374)
@@ -0,0 +1,311 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2017 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#++
+
+require_tecsgen_lib 'tecslib/plugin/lib/MrubyBridgeCelltypePluginModule.rb'
+
+#== MrubyBridgeCompositePlugin
+class MrubyBridgeCelltypePlugin < CompositePlugin
+  dbgPrint "MrubyBridgeCelltypePlugin loaded\n"
+  include MrubyBridgeCelltypePluginModule
+
+  def self.gen_post_code( file )
+    MrubyBridgeCelltypePluginModule.gen_post_code file
+  end
+end
+
+
+#
+##== celltype ãã©ã°ã¤ã³ã®å
+±éã®è¦ªã¯ã©ã¹
+#class MrubyBridgeCelltypePlugin < CelltypePlugin
+#
+#  # ãã©ã°ã¤ã³å¼æ°å => Proc
+#  MrubyBridgePluginArgProc = { 
+#      "ignoreUnsigned" => Proc.new { |obj,rhs| obj.set_ignoreUnsigned rhs },
+#      "include_inner_cell" => Proc.new { |obj,rhs| obj.set_include_inner_cell rhs },
+#      "exclude_cell" => Proc.new { |obj,rhs| obj.set_exclude_cell rhs },
+#      "exclude_port" => Proc.new { |obj,rhs| obj.set_exclude_port rhs },
+#      "exclude_port_func" => Proc.new { |obj,rhs| obj.set_exclude_port_func rhs },
+#      "auto_exclude" => Proc.new { |obj,rhs| obj.set_auto_exclude rhs },
+#  }
+#
+#  require_tecsgen_lib( "MrubyBridgeCellPlugin.rb" )
+#  @@plugin_list = []
+#  @@count = 1
+#
+#  #celltype::     Celltype        ã»ã«ã¿ã¤ãï¼ã¤ã³ã¹ã¿ã³ã¹ï¼
+#  def initialize( celltype, option )
+#    dbgPrint "#{self.class.name}: initialzie: #{celltype.get_name}\n"
+#
+#    super
+#    @celltype = celltype
+#    @cell_list = []
+#    @include_inner_cell = false
+#    @exclude_cells = []
+#    @exclude_port = []
+#    @exclude_port_func = {}
+#    @b_ignoreUnsigned = false
+#    @b_auto_exclude = true     # auto_exclude = true by default 
+#    @@plugin_list << self
+#
+#    @plugin_arg_check_proc_tab = MrubyBridgePluginArgProc
+#    @plugin_arg_str = CDLString.remove_dquote option
+#    parse_plugin_arg
+#
+#    MrubyBridgeCellPlugin.set_gen_post_code_by_dependent
+#  end
+#
+#  #=== æ°ããã»ã«
+#  #cell::        Cell            ã»ã«
+#  #
+#  # celltype ãã©ã°ã¤ã³ãæå®ãããã»ã«ã¿ã¤ãã®ã»ã«ãçæããã
+#  # ã»ã«ã¿ã¤ããã©ã°ã¤ã³ã«å¯¾ããæ°ããã»ã«ã®å ±å
+#  # generate æã«ããå¼ã³åºãããå ´åãããã¾ã§ã«å®ç¾©ããã cell ã«ã¤ãã¦ã¯ãinitialize ã®ã¿ã¤ãã³ã°ã§å¼ã³åºããã
+#  def new_cell( cell )
+#    dbgPrint "MrubyBridgeCelltypePlugin: new_cell: #{cell.get_name}\n"
+#
+#    return if @cell_list.include? cell   # ãã®è¡ã¯ãæ¬æ¥ä¸è¦ã®ã¯ã
+#    if TECSGEN.post_coded?               # post_code ä»¥éã®ã»ã«ã¯å¯¾è±¡ããå¤ã
+#      cdl_info( "I9999 MrubyBridgeCelltypePlugin: $1 is excluded because cell generated after post_coded", cell.get_name )
+#      return
+#    end
+#
+#    # include_inner_cell option
+#    if cell.is_cloned? && @include_inner_cell == false then
+#    #   p "#{cell.get_name} excluded"
+#      cdl_info( "I9999 MrubyBridgeCelltypePlugin: inner cell $1 is excluded", cell.get_name )
+#      return
+#    # else
+#    #   p "#{cell.get_name} included"
+#    end
+#
+#    # exclude_cell option
+#    if @exclude_cells.include?( cell.get_name ) then
+#      return
+#    end
+#
+#    opt_str = "ignoreUnsigned=#{@b_ignoreUnsigned}, auto_exclude=#{@b_auto_exclude}"
+#    @exclude_port.each{ |port|
+#      opt_str += ",exclude_port=#{port}"
+#    }
+#    @exclude_port_func.each{ |port, funcs|
+#      funcs.each{ |func|
+#        opt_str += ",exclude_port_func=#{port}.#{func}"
+#      }
+#    }
+#
+#    # p "MrubyBridgeCelltypePlugin: opt_str=#{opt_str}"
+#
+#    # mikan option, region
+#    fn2 = "#{$gen}/tmp_MrubyBridgeCelltypePlugin_#{@celltype.get_name}_#{@@count}.cdl"
+#    f2 = File.open( fn2, "w" )
+#    f2.print <<EOT
+#/* MrubyBridgeCelltypePlugin: celltype=#{@celltype.get_name} */
+#generate( MrubyBridgeCellPlugin, #{cell.get_namespace_path}, "#{opt_str}" );
+#EOT
+#    f2.close
+#    Import.new "#{fn2}"
+#    @@count += 1
+#  end
+#
+#### æå³è§£ææ®µéã§å¼ã³åºãããã¡ã½ãã ###
+#  #===  CDL ãã¡ã¤ã«ã®çæ
+#  #      typedef, signature, celltype, cell ã®ã³ã¼ããçæ
+#  #      éè¤ãã¦çæãã¦ã¯ãªããªã
+#  #      ãã§ã«çæããã¦ããå ´åã¯åºåããªããã¨ã
+#  #      ãããã¯ååã® import ã«ãããéè¤ãé¿ãããã¨ã
+#  #file::        FILE       çæãããã¡ã¤ã«
+#  def gen_cdl_file file
+##   ãã®æ®µéã§å¼ã³ã ãã¨ generate æãå¼ã³åºãããåã®ã»ã«ã®ã¿ã®åºåã¨ãªã
+#    
+##    dbgPrint "MrubyBridgeCelltypePlugin: gen_cdl_file: #{@celltype.get_name}\n"
+##    file.print <<EOT
+##/* MrubyBridgeCelltypePlugin: celltype=#{@celltype.get_name}
+## *
+## *    cell's generate before celltype's generate
+## */
+##
+##EOT
+##    @celltype.get_cell_list.each { |cell|
+##      @cell_list << cell
+##      # mikan option, region
+##      dbgPrint "MrubyBridgeCelltypePlugin: cell=#{cell.get_name}\n"
+##      file.print <<EOT
+##generate( MrubyBridgeCellPlugin, #{cell.get_namespace_path}, "" );
+##EOT
+##    }
+#
+#  end
+#
+#  #=== tCelltype_factory.h ã«æ¿å
+¥ããã³ã¼ããçæãã
+#  # file ä»¥å¤ã®ä»ã®ãã¡ã¤ã«ã«ãã¡ã¯ããªã³ã¼ããçæãã¦ããã
+#  # ã»ã«ã¿ã¤ããã©ã°ã¤ã³ãæå®ãããã»ã«ã¿ã¤ãã®ã¿å¼ã³åºããã
+#  def gen_factory file
+#  end
+#
+#  def get_celltype
+#    @celltype
+#  end
+#
+#  #=== å¾ãã® CDL ã³ã¼ããçæ
+#  #ãã©ã°ã¤ã³ã®å¾ãã® CDL ã³ã¼ããçæ
+#  #file:: File: 
+#  def self.gen_post_code( file )
+#    dbgPrint "#{self.name}: gen_post_code_body\n"
+#    print "#{self.name}: gen_post_code_body\n"
+##    ãã®æ®µéã§çæããã¨ãåããã¹ãã³ã¼ãã§åºåããã mruby ã®åæåã³ã¼ãã«åæ ãããªã
+#    
+##    # MrubyBridgeCelltypePlugin ã®çæãã generate æã¯ã
+##    fn2 = "#{$gen}/tmp_MrubyBridgeCelltypePlugin_post.cdl"
+##    f2 = File.open( fn2, "w" )
+##    # è¤æ°ã®ãã©ã°ã¤ã³ã® post_code ãä¸ã¤ã®ãã¡ã¤ã«ã«å«ã¾ãããããä»¥ä¸ã®ãããªè¦åºããã¤ãããã¨
+##    dbgPrint "MrubyBridgeCelltypePlugin: gen_post_code\n"
+##    f2.print "/* '#{self.name}' post code */\n"
+##    @@plugin_list.each{ |plugin|
+##      plugin.get_celltype.get_cell_list.each{ |cell|
+##        # mikan option, region
+##        f2.print <<EOT
+##generate( MrubyBridgeCellPlugin, #{cell.get_namespace_path}, "" );
+##EOT
+##      }
+##    }
+##    f2.close
+##    p Import
+##    Import.new "#{fn2}"
+#
+#    MrubyBridgeCellPlugin.gen_post_code_body file
+#  end
+#
+#  #=== ãã©ã°ã¤ã³å¼æ° 
+#
+#  #=== ãã©ã°ã¤ã³å¼æ° ignoreUnsigned
+#  def set_ignoreUnsigned rhs
+#    if rhs == "true" || rhs == nil then
+#      @b_ignoreUnsigned = true
+#    end
+#  end
+#
+#  def set_include_inner_cell rhs
+#    if rhs == "true" || rhs == nil then
+#      @include_inner_cell = true
+#    end
+#  end
+#
+#  def set_exclude_cell rhs
+#    cells = rhs.split ','
+#    cells.each{ |rhs_cell|
+#      rhs_cell.gsub!( /\s/, "" )
+#      @exclude_cells << rhs_cell.to_sym
+#    }
+#  end
+#  def set_exclude_port rhs
+#    ports = rhs.split ','
+#    ct = @cell.get_celltype
+#    return if ct == nil    # error case
+#    ports.each{ |rhs_port|
+#      obj = ct.find( rhs_port.to_sym )
+#      if( ( ! obj.instance_of? Port ) || obj.get_port_type != :ENTRY ) then
+#        cdl_error( "MRB9999 exclude_port '$1' not found or not entry in celltype '$2'", rhs_port, ct.get_name )
+#      else
+#        # print "MRBBridgeCellPlugin: exclude #{rhs_port}\n"
+#        @exclude_port << rhs_port
+#      end
+#    }
+#  end
+#
+#  #=== ãã©ã°ã¤ã³å¼æ° exclude_port_func
+#  def set_exclude_port_func rhs
+#    port_funcs = rhs.split ','
+#    ct = @celltype
+#    return if ct == nil    # error case
+#    port_funcs.each{ |rhs_port_func|
+#      port_func = rhs_port_func.split( '.' )
+#      if port_func.length != 2 then
+#        cdl_error( "MRB9999 exclude_port_func: '$1' not in 'port.func' form", rhs_port_func )
+#      end
+#      obj = ct.find( port_func[0].to_sym )
+#      if( ( ! obj.instance_of? Port ) || obj.get_port_type != :ENTRY ) then
+#        cdl_error( "MRB9999 exclude_port_func: port '$1' not found in celltype '$2'", rhs_port_func, ct.get_name )
+#      else
+#        signature = obj.get_signature
+#        next if signature == nil     # error case
+#        if signature.get_function_head port_func[1].to_sym
+#          # print "MRBBridgeCellPlugin: #{port_func[0]}.#{port_func[1]} exclude\n"
+#          if @exclude_port_func[ port_func[0] ] then
+#            @exclude_port_func[ port_func[0] ] <<  port_func[1]
+#          else
+#            @exclude_port_func[ port_func[0] ] = [ port_func[1] ]
+#          end
+#        else
+#          cdl_error( "MRB9999 include_port_func: func '$1' not found in port '$2' celltype $3",
+#                     port_func[1], port_func[0], ct.get_name )
+#        end
+#      end
+#    }
+#  end
+#
+#  #=== ãã©ã°ã¤ã³å¼æ° auto_exclude
+#  def set_auto_exclude rhs
+#    # print "MrubyBridgeCellPlugin: auto_exclude=#{rhs}\n"
+#    if rhs == "false" then
+#      @b_auto_exclude = false
+#    elsif rhs == "true" then
+#      @b_auto_exclude = true     # auto_exclude = true by default 
+#    else
+#      cdl_warning( "MRB9999 auto_exclude: unknown rhs value ignored. specify true or false" )
+#    end
+#  end
+#end
+#
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCompositePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCompositePlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeCompositePlugin.rb	(revision 374)
@@ -0,0 +1,66 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2017 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#++
+
+require_tecsgen_lib 'tecslib/plugin/lib/MrubyBridgeCelltypePluginModule.rb'
+
+#== MrubyBridgeCompositePlugin
+class MrubyBridgeCompositePlugin < CompositePlugin
+  dbgPrint "MrubyBridgeCompositePlugin loaded\n"
+  include MrubyBridgeCelltypePluginModule
+
+  def self.gen_post_code( file )
+    MrubyBridgeCelltypePluginModule.gen_post_code file
+  end
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgePlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgePlugin.rb	(revision 374)
@@ -3,5 +3,5 @@
 #  mruby => TECS bridge
 #  
-#   Copyright (C) 2008-2015 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeSignaturePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeSignaturePlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MrubyBridgeSignaturePlugin.rb	(revision 374)
@@ -0,0 +1,1336 @@
+# -*- coding: utf-8 -*-
+#
+#  mruby => TECS bridge
+#  
+#   Copyright (C) 2008-2017 by TOPPERS Project
+#
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#
+
+# Todo:
+# çæãããã®
+#  gen_cdl_file
+#    ããªãã¸åæåã»ã«ã¿ã¤ã (ã·ã°ããã£ãã¨)
+#       @@init_celltypes ã«è¨é²
+#    ããªãã¸ã»ã«ã¿ã¤ã (ã·ã°ããã£ãã¨)
+#       @@celltypes ã«è¨é²
+#    æ§é ä½ã»ã«ã¿ã¤ã
+#       @@struct_list ã«è¨é²
+#  new_cell
+#    TECS åæåã»ã«(ãã­ãã¿ã¤ãå®£è¨)
+#       @@VM_init_cells ã«è¨é²
+#       @@VM_struct_list ã«è¨é²
+#       @@VM_ptr_list ã«è¨é²
+#  gen_post_code
+#    æ§é ä½åæåã»ã«
+#    ãã¤ã³ã¿åæåã»ã«
+#    TECS åæåã»ã«
+#
+#   ep_func ã®ä½æ
+#     signature, ãã¤ã³ã¿ãæ§é ä½ â¦ åæååãå£ï¼mruby VM ã¸ã®ç»é²
+#     ãã¤ã³ã¿
+#   preamble ã®ä½æ
+#     ãã¤ã³ã¿ãæ§é ä½ â¦ ã¢ã¯ã»ã¹ç¨ã³ã¼ãã®çæ
+#     signature â¦ ããªãã¸é¢æ°ã®ãã­ãã¿ã¤ãå®£è¨
+#   postamble ã®ä½æ
+#     signature â¦ ããªãã¸é¢æ°ã®å®ç¾©
+
+class MrubyBridgeSignaturePlugin < SignaturePlugin
+
+  # ãã©ã°ã¤ã³å¼æ°å => Proc
+  MrubyBridgePluginArgProc = { 
+      "ignoreUnsigned" => Proc.new { |obj,rhs| obj.set_ignoreUnsigned rhs },
+      "include" => Proc.new { |obj,rhs| obj.set_include rhs },
+      "exclude" => Proc.new { |obj,rhs| obj.set_exclude rhs },
+      "auto_exclude" => Proc.new { |obj,rhs| obj.set_auto_exclude rhs },
+  }
+
+  @@b_no_banner = false         #
+  @@b_gen_post_code_by_dependent = false  # true if gen_post_code is called by MrubyBridgeCellPlugin
+  @@celltypes = { }             # {celltype_name => [ BridgePlugin ã®ã¤ã³ã¹ã¿ã³ã¹ã®é
+å }
+  @@init_celltypes = { }        # {celltype_name => [ BridgePlugin ã®ã¤ã³ã¹ã¿ã³ã¹ã®é
+å }
+  @@struct_list = { }           # {struct_name=>StructType}
+  @@ptr_list = { }              # {ptr_celltype_name=> @@TYPE_MAP ã®å¯¾å¿ãããã®}
+  @@VM_list = { }               # VM_name => true
+  @@VM_celltypes = {  }             # VM_name => { @celltype_name => ã»ã«ã®é
+å }
+  @@VM_struct_list = { }           # {name=>StructType}
+  @@VM_ptr_list = { }              # { VM_name => {name=> @@TYPE_MAP ã®å¯¾å¿ãããã®} }
+  @@TYPE_MAP = {           # type_str   class             GET_SET
+    :char_t            => [:char_t,    "Char",     :Char,  :INT   ],
+    :uchar_t           => [:uchar_t,   "UChar",    :Char,  :INT   ],
+    :schar_t           => [:schar_t,   "SChar",    :Char,  :INT   ],
+
+    :bool_t            => [:bool_t,    "Bool",     :Bool,  :BOOL  ],
+    :int8_t            => [:int8_t,    "Int8",     :Int,   :INT   ],
+    :int16_t           => [:int16_t,   "Int16",    :Int,   :INT   ],
+    :int32_t           => [:int32_t,   "Int32",    :Int,   :INT   ],
+    :int64_t           => [:int64_t,   "Int64",    :Int,   :INT   ],
+    :uint8_t           => [:uint8_t,   "UInt8",    :Int,   :INT   ],
+    :uint16_t          => [:uint16_t,  "UInt16",   :Int,   :INT   ],
+    :uint32_t          => [:uint32_t,  "UInt32",   :Int,   :INT   ],
+    :uint64_t          => [:uint64_t,  "UInt64",   :Int,   :INT   ],
+
+    :int               => [:int,       "Int",      :Int,  :INT   ], 
+    :char              => [:char,      "Char",     :Char, :INT   ],    # char ã¯ char_t ã¨ãã¦æ±ã
+    :short             => [:short,     "Short",    :Int,  :INT   ],
+    :long              => [:long,      "Long",     :Int,  :INT   ],
+
+    :"unsigned char"   => [:uchar_t,   "UChar",         :Char, :INT   ],
+    :"unsigned int"    => [:"unsigned int",   "UInt",   :Int,  :INT   ],
+    :"unsigned short"  => [:"unsigned short", "UShort", :Int,  :INT   ],
+    :"unsigned long"   => [:"unsigned long",  "ULong",  :Int,  :INT   ],
+    :"signed char"     => [:schar_t,   "SChar",    :Char,  :INT   ],
+    :"signed int"      => [:int,       "Int",      :Int,   :INT   ],
+    :"signed short"    => [:short,     "Short",    :Int,   :INT   ],
+    :"signed long"     => [:long,      "Long",     :Int,   :INT   ],
+
+    :float32_t         => [:float32_t, "Float32",  :Float, :FLOAT ],
+    :double64_t        => [:double64_t,"Double64", :Float, :FLOAT ],
+
+    :float             => [:float,     "Float32",  :Float, :FLOAT ],
+    :double            => [:double,    "Double64", :Float, :FLOAT ]
+  }
+
+  # included  or excluded functions
+
+  ### ã­ã¼ããããæç¹ã§å®è¡ããã ###
+
+  # -I ã« $(TECSPATH)/mruby ãè¿½å 
+  # TECSGEN::Makefile.add_obj "$(MRUBY_MAIN_OBJ)"
+  TECSGEN::Makefile.add_ldflag "-lmruby -L$(MRUBYPATH)/lib -lm"
+  TECSGEN::Makefile.add_search_path "$(MRUBYPATH)/include"
+  TECSGEN::Makefile.add_var "MRUBYPATH",      "..",  "CHANGE this to suitable path"
+  # TECSGEN::Makefile.add_var "MRUBY_MAIN_OBJ", "$(_TECS_OBJ_DIR)tecs_mruby.o", "CHANGE this if your have your main"
+
+  #=== ãã©ã°ã¤ã³ã¤ã³ã¹ã¿ã³ã¹ã®åæå
+  # æ»ãå¤ãå¼æ°ã®åãä½¿ç¨å¯è½ãªãã®ããã§ãã¯ãã
+  #
+  def initialize( signature, option )
+    super
+
+    if ! @@b_no_banner
+      STDERR << "MrubyBridgePlugin: version 1.3.0 (Suitable for mruby ver 1.3.0 & ver 1.2.0). \n"
+      @@b_no_banner = true
+    end
+
+    @b_ignoreUnsigned = false
+    @includes = []
+    @excludes = []
+    @struct_list = { }
+    @ptr_list = { }
+    @auto_exclude_list = {}
+    @b_auto_exclude = true     # auto_exclude = true by default 
+
+    @plugin_arg_check_proc_tab = MrubyBridgePluginArgProc
+    parse_plugin_arg
+
+    @celltype_name = :"t#{@signature.get_global_name}"
+    @init_celltype_name = :"#{@celltype_name}_Initializer"
+        # this variable is sometimes not used. rhs coded directry.
+    @class_name = :"T#{@signature.get_global_name}"
+
+    @func_head_array = []
+    fh_array = []
+    if @includes.length > 0 && @excludes.length > 0 then
+      cdl_error( "MRB1011 both include && exclude are specified" )
+    end
+
+    if signature.get_function_head_array == nil then
+      return   # ä»¥åã«ææ³ã¨ã©ã¼çºç
+    end
+
+    signature.get_function_head_array.each{ |func_head|
+      if @includes.length > 0 then
+        if @includes.index func_head.get_name then
+          dbgPrint "MrubyBridgePlugin: #{func_head.get_name} INCLUDED\n"
+          fh_array << func_head
+        else
+          dbgPrint "MrubyBridgePlugin: #{func_head.get_name} NOT included\n"
+        end
+      elsif @excludes.length > 0 then
+        if @excludes.index( func_head.get_name ) == nil then
+          dbgPrint "MrubyBridgePlugin: #{func_head.get_name} NOT excluded\n"
+          fh_array << func_head
+        else
+          dbgPrint "MrubyBridgePlugin: #{func_head.get_name} EXCLUDED\n"
+        end
+      else
+        fh_array << func_head
+      end
+    }
+
+    check_name_and_return_type fh_array
+    check_parameter_type fh_array
+
+    fh_array.each{ |fh|
+      if @auto_exclude_list[ fh.get_name ] == nil then
+        @func_head_array << fh
+      else
+        dbgPrint "MrubyBridgePlugin: auto_exclude #{fh.get_name}\n"
+      end
+    }
+
+    if @func_head_array.length == 0 then
+      cdl_error( "MRB1012 '$1' no function remained by exclude", @signature.get_name )
+    end
+  end
+
+  #=== check function name & return type
+  def check_name_and_return_type func_head_array
+    b_init = false; b_init_cell = false
+    func_head_array.each{ |func_head|
+      if( func_head.get_name == :initialize )then
+        cdl_warning( "MRW2001 initialize: internally defined. change to initialize_cell in ruby" )
+        b_init = true
+      elsif( func_head.get_name == :initialize_cell )then
+        b_init_cell = true
+      end
+      rtype = func_head.get_return_type.get_original_type
+      case rtype
+      when BoolType, IntType, FloatType, VoidType
+      else
+        if @b_auto_exclude then
+          cdl_info( "MRI0001 cannot return type $1, $2 automatcally excluded", rtype.get_type_str, func_head.get_name )
+          @auto_exclude_list[ func_head.get_name ] = func_head
+        else
+          cdl_error( "MRB1001 cannot return type $1", rtype.get_type_str )
+        end
+      end
+    }
+    if( b_init && b_init_cell )then
+      cdl_warning( "MRB1002 initialize: internally defined. change to initialize_cell in ruby" )
+    end
+  end
+
+  #=== check paramter type
+  def check_parameter_type func_head_array
+    # check type of parameters
+    func_head_array.each{ |fh|
+      fh.get_paramlist.get_items.each{ |param_decl|
+        case param_decl.get_direction
+        when :SEND, :RECEIVE
+          if @b_auto_exclude then
+            cdl_info( "MRI0002 $1: $2 parameter cannot be used in mruby Bridge, $3 automatcally excluded",
+                      param_decl.get_name, param_decl.get_direction.to_s.downcase, fh.get_name )
+            @auto_exclude_list[ fh.get_name ] = fh
+          else
+            cdl_error( "MRB1003 $1: $2 parameter cannot be used in mruby Bridge",  param_decl.get_name, param_decl.get_direction.to_s.downcase )
+          end
+        end
+        type = param_decl.get_type
+        type_org = type.get_original_type
+        type_str = type.get_type_str + type.get_type_str_post
+
+        b_ng = false
+        case type_org
+        when IntType
+          case  type_org.get_bit_size
+          when 8, 16, 32, 64
+          when -1, -2, -3, -4, -11
+          else
+            b_ng = true
+          end
+        when BoolType
+        when FloatType
+        when PtrType
+          ttype_org = type_org.get_type       # ãã¤ã³ã¿ã®æãã¦ããå
+ã®å
+          ttype = ttype_org.get_original_type # ä¸è¨ã® typedef ããã¦ããå ´åãå
+ã®å
+          register_ptr_type ttype_org, fh
+
+          if( type_org.get_string.to_s == "-1" ) then
+            case param_decl.get_direction
+            when :OUT, :INOUT
+              if @b_auto_exclude then
+                cdl_info( "MRB9999 string specifier without length cannot be used for out & inout parameter, $1 automatcally excluded", 
+                        fh.get_name )
+                @auto_exclude_list[ fh.get_name ] = fh
+              else
+                cdl_error( "MRB9999 string specifier without length cannot be used for out & inout parameter")
+              end
+            end
+          end
+
+          case ttype
+          when IntType
+            bit_size = ttype.get_bit_size
+            # if  bit_size < 0 && bit_size != -1 then
+            #   b_ng = true
+            # end
+          when FloatType
+          when BoolType
+          when StructType
+            if( type_org.get_size || type_org.get_string || type_org.get_count ) then
+              if @b_auto_exclude then
+                cdl_info( "MRI9999 $1: size_is, count_is, string cannot be specified for struct pointer, $2 automatcally excluded",
+                          param_decl.get_name, fh.get_name )
+                @auto_exclude_list[ fh.get_name ] = fh
+              else
+                cdl_error( "MRB1004 $1: size_is, count_is, string cannot be specified for struct pointer", param_decl.get_name )
+              end
+            end
+            check_struct_member ttype_org, fh
+          else
+            b_ng = true
+          end
+        when StructType
+          check_struct_member type_org, fh
+        else  # ArrayType, FuncType, EnumType, VoidType
+          b_ng = true
+        end
+        if b_ng then
+          if @b_auto_exclude then
+            cdl_info( "MRI9999 $1: type $2 cannot be used in mruby Bridge, $3 automatcally excluded",
+                      param_decl.get_name, type_str, fh.get_name )
+            @auto_exclude_list[ fh.get_name ] = fh
+          else
+            cdl_error( "MRB1005 $1: type $2 cannot be used in mruby Bridge", param_decl.get_name, type_str )
+          end
+        end
+      }
+    }
+  end
+
+  #=== æ§é ä½ã®ã¡ã³ãã¼ã®åã®ãã§ãã¯
+  def check_struct_member struct_type, fh
+    #p "tag name:#{struct_type.get_name}"
+    # sttype = Namespace.find_tag( struct_type.get_name )
+    sttype = struct_type.get_original_type
+    if sttype.get_name == nil then
+      if @b_auto_exclude then
+        cdl_info( "MRI9999 tagless-struct cannot be handled, $1 automatcally excluded", fh.get_name )
+        @auto_exclude_list[ fh.get_name ] = fh
+        return  # ç»é²ããªãããã«æã¡åã
+      else
+        cdl_error( "MRB10007 tagless-struct cannot be handled")
+      end
+    end
+    sttype.get_members_decl.get_items.each { |d|
+      t = d.get_type.get_original_type
+      case t
+      when IntType, FloatType, BoolType
+      else
+        if @b_auto_exclude then
+          cdl_info( "MRI9999 $1: type $2 not allowed for struct member, $3 automatcally excluded",
+                    d.get_name, d.get_type.get_type_str + d.get_type.get_type_str_post, fh.get_name )
+          @auto_exclude_list[ fh.get_name ] = fh
+          return  # ç»é²ããªãããã«æã¡åã
+        else
+          cdl_error( "MRB1006 $1: type $2 not allowed for struct member", d.get_name, d.get_type.get_type_str + d.get_type.get_type_str_post )
+        end
+      end
+    }
+    st_name = :"t{}"
+    if @struct_list[ sttype.get_name ] == nil then
+      # print_msg "  MrubyBridgePlugin: [struct]   #{struct_type.get_type_str} => class TECS::Struct#{sttype.get_name}\n"
+      print "  MrubyBridgePlugin: [struct]   #{struct_type.get_type_str} => class TECS::Struct#{sttype.get_name}\n"
+      @struct_list[ sttype.get_name ] = sttype
+    end
+  end
+
+  def register_ptr_type ttype, fh
+    t_org = ttype.get_original_type
+    tment = get_type_map_ent t_org
+    if tment == nil then
+      return
+      # cdl_error( "MRB1008 unknown pointer type '$1'", ttype.get_type_str )
+    end
+    ptr_celltype_name = :"t#{tment[1]}Pointer"
+    if @@ptr_list[ ptr_celltype_name ] == nil then
+      # print_msg "  MrubyBridgePlugin: [pointer]  #{ttype.get_type_str}* => class TECS::#{tment[1]}Pointer\n"
+      print "  MrubyBridgePlugin: [pointer]  #{ttype.get_type_str}* => class TECS::#{tment[1]}Pointer\n"
+      @@ptr_list[ ptr_celltype_name ] = tment
+    end
+    if @ptr_list[ ptr_celltype_name ] == nil then
+      @ptr_list[ ptr_celltype_name ] = tment
+    end
+  end
+
+  def get_type_map_ent ttype
+    # structure type is registerd in check_struct_member
+    if ttype.kind_of? StructType
+      return
+    end
+    tstr = ttype.get_type_str.sub( /const /, "" )    # const ã¯ç¡è¦
+    tstr = tstr.sub( /volatile /, "" )               # volatile ãç¡è¦
+    if @b_ignoreUnsigned then
+      tstr = tstr.sub( /unsigned /, "" )             # volatile ãç¡è¦
+      tstr = tstr.sub( /uint/, "int" )               # volatile ãç¡è¦
+      tstr = tstr.sub( /[cs]char/, "char" )          # volatile ãç¡è¦
+    end
+    return @@TYPE_MAP[ tstr.to_sym ]
+  end
+
+  #===  CDL ãã¡ã¤ã«ã®çæ
+  #      typedef, signature, celltype, cell ã³ã¼ããçæ
+  #file::        FILE       çæãããã¡ã¤ã«
+  def gen_cdl_file(file)
+
+    # ããªãã¸ã»ã«ã¿ã¤ãã®çæ
+    if @@celltypes[ @celltype_name ] == nil then
+      @@celltypes[ @celltype_name ] = [ self ]
+      @@init_celltypes[ @init_celltype_name ] = true
+      print_msg <<EOT
+  MrubyBridgePlugin: [signature] #{@signature.get_namespace_path} => [celltype] nMruby::#{@celltype_name} => [class] TECS::#{@class_name}
+EOT
+
+      file.print <<EOT
+/*
+ * MrubyBridgeSignaturePlugin:
+ *     signature=#{@signature.get_namespace_path}
+ *
+ *   => celltype=nMruby::#{@celltype_name}
+ *      (bridge cell's celltype; generated in this file)
+ *      cell nMruby::#{@celltype_name} BridgeCellName { cTECS = CellName.eEntry; };
+ *        where eEntry's signature must be #{@signature.get_namespace_path}.
+ *      => class=TECS::#{@class_name}
+ *         (mruby's class; accessible from your script)
+ *          bridge = TECS::#{@class_name}.new("BridgeCellName")
+ */
+import( <mruby.cdl> );
+
+/****  Ruby => TECS Bridge Celltype (MBP500) ****/
+namespace nMruby{
+    // bridge celltype
+    [idx_is_id,active]   // not actually active, to avoid warning W1002, W1007
+    celltype #{@celltype_name} {
+        call #{@signature.get_namespace_path.to_s} cTECS;
+        attr {
+            [omit]
+            char_t *VMname = "VM";
+            [omit]
+            char_t *bridgeName = C_EXP( "$cell$" );
+        };
+    };
+    // bridge initializer celltype
+    celltype #{@init_celltype_name} {
+        entry sInitializeTECSBridge eInitialize;
+    };
+};
+EOT
+
+      # æ§é ä½ã»ã«ã¿ã¤ãã®çæ
+      @struct_list.each{ |name, sttype|
+        if @@struct_list[ name ] == nil then
+          file.print <<EOT
+namespace nMruby{
+    [singleton]
+    celltype #{name} {
+        entry sInitializeTECSBridge eInitialize;
+    };
+};
+EOT
+          @@struct_list[ name ] = sttype
+        end
+      }
+
+    else
+      cdl_info( "MRBW001 MrubyBridgePlugin: signature '$1' duplicate. ignored current one", @signature.get_namespace_path )
+      @@celltypes[ @celltype_name ] << self
+    end
+  end
+
+  #=== gen_cdl_file ã§å®ç¾©ããã»ã«ã¿ã¤ãã« æ°ããã»ã«ãå®ç¾©ããã
+  # cell ã®ã»ã«ã¿ã¤ãã®ååã¯ @celltype_name
+  def new_cell cell
+    if cell.get_celltype.get_name != @celltype_name then
+      return
+    end
+
+    join = cell.get_join_list.get_item :VMname
+    if join then
+      vm_name = CDLString.remove_dquote(join.get_rhs.to_s).to_sym
+    else
+      vm_name = :"VM"
+    end
+
+    if @@VM_list[ vm_name ] == nil then
+      @@VM_list[ vm_name ] = true
+
+      initializer_celltype_cdl = "#{$gen}/#{cell.get_name}Initializer.cdl"
+      file = CFile.open( initializer_celltype_cdl, "w" )
+
+      # TECS åæåã»ã«(ãã­ãã¿ã¤ãå®£è¨)
+      print_msg "  MrubyBridgePlugin: join your VM's cInitialize to #{vm_name}_TECSInitializer.eInitialize\n"
+
+      file.print <<EOT
+
+  // prototype of TECSInitializer (MBP510)
+  cell nMruby::tTECSInitializer #{vm_name}_TECSInitializer;
+EOT
+      file.close
+
+      Generator.parse( initializer_celltype_cdl, self )
+    end
+
+    if @@VM_celltypes[ vm_name ] then
+      vma = @@VM_celltypes[ vm_name ]
+
+      if vma[ @celltype_name ] then
+        vma[ @celltype_name ] << cell
+      else
+        vma[ @celltype_name ] = [cell]
+        @@VM_celltypes[ vm_name ] = vma
+      end
+    else
+      vma = { }
+      vma[ @celltype_name ] = [cell]
+      @@VM_celltypes[ vm_name ] = vma
+    end
+
+    @struct_list.each{ |stname, sttype|
+      if @@VM_struct_list[ vm_name ] then
+        @@VM_struct_list[ vm_name ][ sttype.get_name ] = sttype
+      else
+        @@VM_struct_list[ vm_name ] = { sttype.get_name => sttype }
+      end
+    }
+    @ptr_list.each{ |ptr_celltype_name, tment|
+      if @@VM_ptr_list[ vm_name ] then
+        @@VM_ptr_list[ vm_name ][ ptr_celltype_name ] = tment
+      else
+        @@VM_ptr_list[ vm_name ] = { ptr_celltype_name => tment }
+      end
+    }
+
+  end
+
+  #=== ãã©ã°ã¤ã³ã CDL ã® POST ã³ã¼ããçæ
+  # tmp_plugin_post_code.cdl ã¸ã®åºå
+  def self.gen_post_code file
+    dbgPrint "#{self.name}: gen_post_code\n"
+    if ! @@b_gen_post_code_by_dependent then
+      gen_post_code_body file
+    end
+  end
+
+  def self.set_gen_post_code_by_dependent # by MrubyBriddeCellPlugin
+    dbgPrint "#{self.name}: set_gen_post_code_by_dependent\n"
+    @@b_gen_post_code_by_dependent = true
+  end
+
+  def self.gen_post_code_body file
+    dbgPrint "#{self.name}: gen_post_code_body\n"
+
+#     file.print <<EOT
+# namespace nMruby {
+# EOT
+# 
+#     @@ptr_list.each{ |name,tment|
+#       file.print <<EOT
+# 
+#     // MBP600
+#     [singleton]
+#     celltype #{name} {
+#         entry  sInitializeTECSBridge eInitialize;
+#     };
+# EOT
+#     }
+# 
+#     file.print <<EOT
+# };
+# EOT
+
+# gen_post_code ã§çæãã celltype ã¯ gen_ep_func ãå¼ã³åºãããªã #847
+#    @@struct_list.each{ |name,sttype|
+#      file.print <<EOT
+#
+#    [singleton]
+#    celltype #{name} {
+#        entry  sInitializeTECSBridge eInitialize;
+#    };
+#EOT
+#    }
+
+    file.print "\n  // MrubyBridgeSignaturePlugin: MBP601\n"
+    @@VM_celltypes.each{ |vm_name, instance_list|
+      instance_list.each { |celltype_name, array|
+        cell = array[0]
+	if cell.get_celltype then
+	  ct_name = cell.get_celltype.get_name
+        file.print <<EOT
+  cell nMruby::#{ct_name}_Initializer #{vm_name}_#{ct_name}_Initializer{ };
+EOT
+        end
+      }
+    }
+
+    file.print "  // MBP602\n"
+    @@ptr_list.each{ |name,tment|
+      file.print <<EOT
+  cell nMruby::#{name} C#{name} { };
+EOT
+    }
+
+    file.print "  // MBP603\n"
+    @@struct_list.each{ |name,sttype|
+      file.print <<EOT
+  cell nMruby::#{name} C#{name} { };
+EOT
+    }
+
+    if @@VM_celltypes == nil
+      raise "MrubyBridgeSignaturePlugin: are0"
+    end
+    @@VM_celltypes.each{ |vm_name, instance_list|
+      file.print "  /* === VM name is '#{vm_name}' === (MBP610) */\n"
+      init_cell_name = "#{vm_name}_TECSInitializer"
+
+      file.print "  cell nMruby::tTECSInitializer #{init_cell_name} {\n"
+
+      instance_list.each { |celltype_name, array|
+#        array.each{ |cell|
+#          ct_name = cell.get_celltype.get_name
+          ct_name = celltype_name
+          file.print "    cInitialize[] = #{vm_name}_#{ct_name}_Initializer.eInitialize;\n"
+#        }
+      }
+      if @@VM_ptr_list[vm_name] then
+        @@VM_ptr_list[vm_name].each{ |name, tment|
+          file.print "    cInitialize[] = C#{name}.eInitialize;\n"
+        }
+      end
+      if @@VM_struct_list[vm_name] then
+        @@VM_struct_list[vm_name].each{ |name, sttype|
+          file.print "    cInitialize[] = C#{name}.eInitialize;\n"
+        }
+      end
+      file.print "  };"
+    }
+    
+  end
+
+  ####### ä»¥ä¸ã³ã¼ãçææ®µé ######
+
+  #===  åãå£é¢æ°ã®æ¬ä½ã³ã¼ããçæï¼é ­é¨ã¨æ«å°¾ã¯å¥éåºåï¼
+  #ct_name:: Symbol    (ãã©ã°ã¤ã³ã§çæããã) ã»ã«ã¿ã¤ãå ï¼Symbol ã¨ãã¦éããã¦ãã
+  def gen_ep_func_body( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    if @@celltypes[ ct_name ] then
+      gen_ep_func_body_bridge( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    elsif @@init_celltypes[ ct_name ] then
+      gen_ep_func_body_bridge_init( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    elsif @@ptr_list[ ct_name ] then
+      gen_ep_func_body_ptr( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    elsif @@struct_list[ ct_name ] then
+      gen_ep_func_body_struct( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    else
+      raise "MrubyBridgeSignaturePlugin: Unknown #{ct_name}"
+    end
+  end
+
+  def gen_ep_func_body_bridge( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    raise "MrubyBridgeSignaturePlugin: unexpected "
+  end
+
+  def gen_ep_func_body_bridge_init( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    file.print <<EOT
+    // CELLCB *p_cellcb = GET_CELLCB( idx );  /* no error check */     /* MBP700 */
+    struct RClass	*rc;
+
+    rc = mrb_define_class_under( mrb, TECS, \"#{@class_name}\", mrb->object_class );
+    mrb_define_method( mrb, rc, "initialize", MrubyBridge_#{@celltype_name}_initialize, MRB_ARGS_REQ(1) );
+    MRB_SET_INSTANCE_TT(rc, MRB_TT_DATA);
+EOT
+
+    @func_head_array.each{ |f|
+      if ! f.is_function? then
+        next
+      end
+      if f.get_name != :initialize then
+        func_name = f.get_name
+      else
+        func_name = :initialize_cell
+      end
+
+      ret_type = f.get_return_type
+      n_param = 0
+      f.get_paramlist.get_items.each{ |param|
+        case param.get_direction
+        when :IN, :INOUT, :OUT
+          n_param += 1
+        when :SEND, :RECEIVE
+          raise "MrubyBridgeSignaturePlugin: send, receive"
+        end
+      }
+      if n_param > 0 then
+        p_str = "MRB_ARGS_REQ( #{n_param} )"
+      else
+        p_str = "MRB_ARGS_NONE()"
+      end
+      file.print <<EOT
+	mrb_define_method( mrb, rc, "#{func_name}", MrubyBridge_#{@celltype_name}_#{func_name}, #{p_str} );
+EOT
+    }
+  end
+
+  def gen_ep_func_body_ptr( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    
+    t = @@ptr_list[ct_name]
+    type = t[1]
+    file.print <<EOT
+	struct RClass *a;                                /* MBP710 */
+
+    a = mrb_define_class_under(mrb, TECS, "#{type}Pointer", mrb->object_class);
+    MRB_SET_INSTANCE_TT(a, MRB_TT_DATA);
+
+    mrb_define_method(mrb, a, "initialize",      #{type}Pointer_initialize,   MRB_ARGS_REQ(1));
+    mrb_define_method(mrb, a, "[]",              #{type}Pointer_aget,         MRB_ARGS_REQ(1));
+    mrb_define_method(mrb, a, "value",           #{type}Pointer_get_val,      MRB_ARGS_NONE());
+    mrb_define_method(mrb, a, "[]=",             #{type}Pointer_aset,         MRB_ARGS_REQ(2));
+    mrb_define_method(mrb, a, "value=",          #{type}Pointer_set_val,      MRB_ARGS_REQ(1));
+    mrb_define_method(mrb, a, "size",            #{type}Pointer_size,         MRB_ARGS_NONE());
+    mrb_define_method(mrb, a, "length",          #{type}Pointer_size,         MRB_ARGS_NONE());
+EOT
+
+    if t[2] == :Char then
+      file.print <<EOT
+	mrb_define_method(mrb, a, "to_s",            CharPointer_to_s, MRB_ARGS_NONE());
+	mrb_define_method(mrb, a, "from_s",          CharPointer_from_s, MRB_ARGS_REQ(1));
+EOT
+    end
+  end
+
+  def gen_ep_func_body_struct( file, b_singleton, ct_name, global_ct_name, sig_name, ep_name, func_name, func_global_name, func_type, params )
+    tag = ct_name
+    structType = @@struct_list[ tag ]
+    file.print  <<EOT
+	struct RClass *a;                                /* MBP720 */
+
+	a = mrb_define_class_under(mrb, TECS, "Struct#{tag}", mrb->object_class);
+	MRB_SET_INSTANCE_TT(a, MRB_TT_DATA);
+
+	mrb_define_method(mrb, a, "initialize", Struct_#{tag}_initialize, MRB_ARGS_NONE());
+EOT
+
+      structType.get_members_decl.get_items.each{ |d|
+        file.print "  STRUCT_INIT_MEMBER( #{tag}, #{d.get_name} )\n"
+      }
+  end
+
+  #===  åãå£é¢æ°ã® preamble (Cè¨èª)ãçæãã
+  #     å¿
+è¦ãªã preamble é¨ã«åºåãã
+  #file::           FILE        åºåå
+ãã¡ã¤ã«
+  #b_singleton::    bool        true if singleton
+  #ct_name::        Symbol
+  #global_ct_name:: string
+  def gen_preamble( file, b_singleton, ct_name, global_ct_name )
+    if @@celltypes[ ct_name ] then
+      gen_preamble_mruby( file, b_singleton, ct_name, global_ct_name )
+      gen_preamble_instance( file, b_singleton, ct_name, global_ct_name )
+      gen_preamble_instance_initialize( file, b_singleton, ct_name, global_ct_name )
+      gen_preamble_bridge_func( file, b_singleton, ct_name, global_ct_name )
+    elsif @@init_celltypes[ ct_name ] then
+      gen_preamble_mruby( file, b_singleton, ct_name, global_ct_name )
+      gen_preamble_instance_proto( file, b_singleton, ct_name, global_ct_name )
+    elsif @@ptr_list[ ct_name ] then
+      gen_preamble_ptr( file, b_singleton, ct_name, global_ct_name )
+    elsif @@struct_list[ ct_name ] then
+      gen_preamble_struct( file, b_singleton, ct_name, global_ct_name )
+    else
+      raise "MrubyBridgeSignaturePlugin: MrubyBridgeSignaturePlugin: Unknown #{ct_name}"
+    end
+  end
+
+  def gen_preamble_mruby( file, b_singleton, ct_name, global_ct_name )
+    file.print <<EOT
+/* MBP: MrubyBridgePlugin: MBP000 */
+#include "mruby.h"
+#include "mruby/class.h"
+#include "mruby/data.h"
+#include "mruby/string.h"
+#include "TECSPointer.h"
+#include "TECSStruct.h"
+
+#if defined(_WIN32) || defined(__WIN32__) || defined(__CYGWIN__)
+#define DLLEXPORT __declspec(dllexport)
+#else
+#define DLLEXPORT
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+EOT
+  end
+
+  def gen_preamble_instance( file, b_singleton, ct_name, global_ct_name )
+    # ã#1005  MrubyBridgePlugin-test ã®ãã«ãã«å¤±æãã«ã¦è¿½å 
+    # ã#1004 idx_is_id ã true ã®å ´å(domain ã®å ´åã¯æªæå®ã§ã true) ã® CBP ã®ãã­ãã¿ã¤ãå®£è¨ãã«ã¦ä¸è¦ã«ãªãè¦è¾¼ã¿
+    nsp = NamespacePath.new( :nMruby, true )
+    nsp.append! ct_name
+    ct = Namespace.find nsp
+    if ct.idx_is_id_act? then
+      if ct.has_CB? then
+        inib_cb = "CB"
+      elsif ct.has_INIB? then
+        inib_cb = "INIB"
+      else
+        inib_cb = nil
+      end
+      if inib_cb then
+        ct.get_cell_list.each{ |cell|
+          if cell.is_generate? then
+            name_array = ct.get_name_array( cell )
+            file.print "extern #{ct.get_global_name}_CB  #{cell.get_global_name}_#{inib_cb};\n"
+          end
+        }
+      end
+    end
+
+    file.print <<EOT
+
+/* RData MBP001 */
+static void 
+#{@celltype_name}_free( mrb_state *mrb, void *p )
+{
+	if( p )
+		(void)mrb_free( mrb, p );
+}
+
+/* RData MBP002 */
+struct mrb_data_type data_type_#{@celltype_name} =
+{
+	"#{@celltype_name}",
+	#{@celltype_name}_free
+};
+
+/* RData MBP003 */
+struct tecs_#{@celltype_name} {
+    CELLCB  *cbp;
+};
+
+/* name_to_cbp MBP010 */
+const struct name_to_cbp_#{@celltype_name} {
+    char   *name;    /* Cell Name */
+    CELLCB *cbp;
+} Name_to_cbp_#{@celltype_name}[] = {
+EOT
+
+    nsp = NamespacePath.new( :nMruby, true )
+    nsp.append! ct_name
+    ct = Namespace.find nsp
+
+    ct.get_cell_list.each{ |cell|
+      if cell.is_generate? then
+        join_list = cell.get_join_list
+        join = join_list.get_item( :bridgeName )
+        if join == nil then
+          name = "\"#{cell.get_name}\""
+        else
+          rhs = join.get_rhs
+          attr_list = cell.get_celltype.get_attribute_list
+          name = rhs.eval_const join_list, attr_list
+        end
+
+        name_array = ct.get_name_array( cell )
+        file.print "\t{ #{name}, #{name_array[8]} },\n"
+      end
+    }
+
+    file.print <<EOT
+\t{ 0, 0 },
+};
+
+EOT
+
+  end
+
+  def gen_preamble_ptr( file, b_singleton, ct_name, global_ct_name )
+    tment = @@ptr_list[ ct_name ]
+    file.print <<EOT
+
+GET_SET_#{tment[3]}( #{tment[1]}, #{tment[0]} )
+POINTER_CLASS( #{tment[1]}, #{tment[0]} )
+EOT
+  end
+
+  def gen_preamble_struct( file, b_singleton, ct_name, global_ct_name )
+    tag = ct_name
+    structType = @@struct_list[ tag ]
+    file.print <<EOT
+/* struct #{tag} */
+STRUCT_CLASS( #{tag} )
+EOT
+
+    structType.get_members_decl.get_items.each{ |d|
+      type = d.get_type.get_original_type
+      case type
+      when IntType, CIntType
+        bit_size = type.get_bit_size
+        case bit_size
+        when -11, -1
+          tType = "Char"
+          ttype = "char"
+        when -2
+          tType = "Short"
+          ttype = "short"
+        when -3
+          tType = "Int"
+          ttype = "int"
+        when -4
+          tType = "Long"
+          ttype = "long"
+        when -5
+          tType = "IntPtr"
+          ttype = "intptr"
+        when 8, 16, 32, 64
+          tType = "Int#{bit_size}"
+          ttype = "int#{bit_size}"
+        else
+            raise "MrubyBridgeSignaturePlugin: MrubyBridgeSignaturePlugin: cannot handle bit_size #{bit_size}"
+        end
+        file.print "MEMBER_GET_SET_INT( #{tag}, #{d.get_name}, #{tType}, #{ttype} )\n"
+      when FloatType, CFloatType
+        file.print "MEMBER_GET_SET_FLOAT( #{tag}, #{d.get_name} )\n"
+      else
+        raise "MrubyBridgeSignaturePlugin: MrubyBridgeSignaturePlugin: cannot handle type"
+      end
+    }
+
+  end
+
+  def gen_preamble_instance_proto( file, b_singleton, ct_name, global_ct_name )
+    file.print <<EOT
+//  Prototype MBP400
+mrb_value  MrubyBridge_#{@celltype_name}_initialize( mrb_state *mrb, mrb_value self);
+EOT
+
+    @func_head_array.each{ |f|
+      if ! f.is_function? then
+        next
+      end
+      if f.get_name != :initialize then
+        func_name = f.get_name
+      else
+        func_name = :initialize_cell
+      end
+
+      ret_type  = f.get_return_type
+      ret_type0 = f.get_return_type.get_original_type
+      b_void    = ret_type0.is_void?
+      plist     = f.get_paramlist.get_items
+
+      file.print <<EOT
+mrb_value  MrubyBridge_#{@celltype_name}_#{func_name}( mrb_state *mrb, mrb_value self );
+EOT
+    }
+  end
+
+  def gen_preamble_instance_initialize( file, b_singleton, ct_name, global_ct_name )
+    file.print <<EOT
+
+/* MBP100 */
+mrb_value
+MrubyBridge_#{@celltype_name}_initialize( mrb_state *mrb, mrb_value self)
+{
+	mrb_value	name;
+	struct tecs_#{@celltype_name} *tecs_cb;
+	const struct name_to_cbp_#{@celltype_name} *ntc;
+
+	/* set DATA_TYPE earlier to avoid SEGV */
+	DATA_TYPE( self ) = &data_type_#{@celltype_name};
+
+	mrb_get_args(mrb, "o", &name );
+	if( mrb_type( name ) != MRB_TT_STRING ){
+		mrb_raise(mrb, E_NAME_ERROR, "cell name not string");
+	}
+	for( ntc = &Name_to_cbp_#{@celltype_name}[0]; ntc->name != NULL; ntc++ ){
+		if( strcmp( ntc->name, RSTRING_PTR( name ) ) == 0 )
+			break;
+	}
+	if( ntc->name == 0 ){
+		mrb_raise(mrb, E_ARGUMENT_ERROR, "cell not found");
+	}
+	tecs_cb = (struct tecs_#{@celltype_name} *)mrb_malloc(mrb, sizeof(struct tecs_#{@celltype_name}) );
+	tecs_cb->cbp = ntc->cbp;
+	DATA_PTR( self ) = (void *)tecs_cb;
+
+	return self;
+}
+EOT
+  end
+
+  def gen_preamble_bridge_func( file, b_singleton, ct_name, global_ct_name )
+
+    @func_head_array.each{ |f|
+      if ! f.is_function? then
+        next
+      end
+      if f.get_name != :initialize then
+        func_name = f.get_name
+      else
+        func_name = :initialize_cell
+      end
+
+      ret_type  = f.get_return_type
+      ret_type0 = f.get_return_type.get_original_type
+      b_void    = ret_type0.is_void?
+      plist     = f.get_paramlist.get_items
+
+      file.print <<EOT
+
+/* bridge function (MBP101) */
+mrb_value
+MrubyBridge_#{ct_name}_#{func_name}( mrb_state *mrb, mrb_value self )
+{
+	/* cellcbp (MBP105) */
+	CELLCB	*p_cellcb = ((struct tecs_#{@celltype_name} *)DATA_PTR(self))->cbp;
+EOT
+      
+      file.print "	/* variables for return & parameter (MBP110) */\n"
+      if ! b_void then
+        file.print "	", ret_type.get_type_str, "\tret_val", ret_type.get_type_str_post, ";\n"
+      end
+      arg_str = ""
+      n_param  = 0
+      n_scalar = 0
+      n_ptr    = 0
+      n_struct = 0
+      plist.each{ |param|
+        case param.get_direction
+        when :IN, :INOUT, :OUT
+          type = param.get_type.get_original_type
+          case type
+          when IntType
+            file.print "	mrb_int	mrb_", param.get_name, ";\n"
+            file.print "	#{param.get_type.get_type_str}	#{param.get_name}#{param.get_type.get_type_str_post};\n"
+            arg_str += "i"
+            n_param += 1
+            n_scalar += 1
+          when FloatType
+            file.print "	mrb_float	mrb_", param.get_name, ";\n"
+            file.print "	#{param.get_type.get_type_str}	#{param.get_name}#{param.get_type.get_type_str_post};\n"
+            arg_str += "f"
+            n_param += 1
+            n_scalar += 1
+          when BoolType
+            file.print "	mrb_value	mrb_", param.get_name, ";\n"
+            file.print "	#{param.get_type.get_type_str}	#{param.get_name}#{param.get_type.get_type_str_post};\n"
+            arg_str += "o"
+            n_param += 1
+            n_scalar += 1
+          when PtrType
+            file.print "	mrb_value	mrb_", param.get_name, ";\n"
+            file.print "	#{param.get_type.get_type_str}	#{param.get_name}#{param.get_type.get_type_str_post};\n"
+            arg_str += "o"
+            n_param += 1
+            n_ptr += 1
+          when StructType
+            file.print "	mrb_value	mrb_", param.get_name, ";\n"
+            file.print "	#{param.get_type.get_type_str}	*#{param.get_name}#{param.get_type.get_type_str_post};\n"
+            arg_str += "o"
+            n_param += 1
+            n_struct += 1
+          else
+            raise "MrubyBridgeSignaturePlugin: Unknown type"
+          end
+        end
+      }
+
+      if n_param > 0 then
+        file.print "	/* retrieve arguments (MBP111) */\n"
+        file.print "	mrb_get_args(mrb, \"#{arg_str}\""
+        plist.each{ |param|
+          case param.get_direction
+          when :IN, :INOUT, :OUT
+            type = param.get_type.get_original_type
+            case type
+            when IntType
+              file.print ", &mrb_", param.get_name
+            when FloatType
+              file.print ", &mrb_", param.get_name
+            when BoolType
+              file.print ", &mrb_", param.get_name
+            when PtrType
+              file.print ", &mrb_", param.get_name
+            when StructType
+              file.print ", &mrb_", param.get_name
+            else
+              raise "MrubyBridgeSignaturePlugin: Unknown type"
+            end
+          end
+        }
+        file.print " );\n"
+
+        if n_scalar > 0 || n_struct > 0 then
+          file.print "	/* convert mrb to C (MBP112) */\n"
+        end
+        plist.each{ |param|
+          case param.get_direction
+          when :IN, :INOUT, :OUT
+            type = param.get_type.get_original_type
+            case type
+            when IntType
+              ttype = type.get_original_type
+              tment = get_type_map_ent ttype
+              file.print "	VALCHECK_#{tment[1]}( mrb, mrb_#{param.get_name} );\n"
+              file.print "	#{param.get_name} = (#{param.get_type.get_type_str})mrb_#{param.get_name};\n"
+            when FloatType
+              file.print "	#{param.get_name} = (#{param.get_type.get_type_str})mrb_#{param.get_name};\n"
+            when BoolType
+              file.print "	#{param.get_name} = mrb_test( mrb_#{param.get_name} );\n"
+            when PtrType
+              ttype = type.get_type.get_original_type
+              case ttype
+              when StructType
+                file.print "	CHECK_STRUCT( #{ttype.get_name}, mrb_#{param.get_name} );\n"
+                file.print "	#{param.get_name} = (struct #{ttype.get_name}*)DATA_PTR(mrb_#{param.get_name});\n"
+              when IntType
+              when FloatType
+              when BoolType
+              else
+                raise "MrubyBridgeSignaturePlugin: cannot handle type"
+              end
+            when StructType
+              file.print "	CHECK_STRUCT( #{type.get_name}, mrb_#{param.get_name} );\n"
+              file.print "	#{param.get_name} = (struct #{type.get_name}*)DATA_PTR(mrb_#{param.get_name});\n"
+            else
+              raise( "MrubyBridgeSignaturePlugin: canot treat class" )
+            end
+          end
+        }
+
+        if n_ptr > 0 then
+          file.print "	/* convert mrb to C for pointer types (MBP113) */\n"
+        end
+        plist.each{ |param|
+          case param.get_direction
+          when :IN, :INOUT, :OUT
+            type = param.get_type.get_original_type
+            case type
+            when IntType
+            when FloatType
+            when BoolType
+            when PtrType
+              case type.get_type.get_original_type
+              when StructType
+              when IntType
+                ptrMrb2C file, type, param
+              when FloatType
+                ptrMrb2C file, type, param
+              when BoolType
+                ptrMrb2C file, type, param
+              else
+                raise "MrubyBridgeSignaturePlugin: cannot handle type"
+              end
+            when StructType
+            else
+              raise( "MrubyBridgeSignaturePlugin: canot treat class" )
+            end
+          end
+        }
+
+      end
+
+      file.print "	/* calling target (MBP120) */\n"
+      if ! b_void then
+        file.print "	ret_val = "
+      else
+        file.print "	"
+      end
+      delim = ""
+      file.print "cTECS_", f.get_name, "( "
+      plist.each{ |param|
+        if param.get_type.get_original_type.kind_of? StructType then
+          aster = "*"
+        else
+          aster = ""
+        end
+        file.print delim, aster, param.get_name
+        delim = ", "
+      }
+      file.print " );\n"
+      
+      file.print "	/* return (MBP130) */\n"
+      case ret_type0
+      when BoolType
+        file.print "	return ret_val ? mrb_true_value() : mrb_false_value();\n"
+      when IntType
+        file.print "	return mrb_fixnum_value( ret_val );\n"
+      when FloatType
+        file.print "	return mrb_float_value( mrb, ret_val );\n"
+      when VoidType
+        file.print "	return  mrb_nil_value();\n"
+      else
+        raise "MrubyBridgeSignaturePlugin: unknown type"
+      end
+
+      file.print "}\n"
+    }
+  end
+
+  def ptrMrb2C file, type, param
+    ttype = type.get_type.get_original_type
+    tment = get_type_map_ent ttype
+    tstr = tment[1]
+=begin
+    case ttype
+    when IntType
+      bit_size = ttype.get_bit_size
+      case bit_size
+      when -1, -11
+        tstr = "Char"
+      when 8, 16, 32, 64
+        tstr = "Int#{bit_size}"
+      when -2
+        tstr = "Short"
+      when -3
+        tstr = "Int"
+      when -4
+        tstr = "Long"
+      when -5
+        tstr = "IntPtr"
+      else
+        raise "MrubyBridgeSignaturePlugin: not handle type"
+      end
+    when FloatType
+      if ttype.get_bit_size == 32 then
+        tstr = "Float32"
+      else
+        tstr = "Double64"
+      end
+    when BoolType
+      tstr = "Bool"
+    when StructType
+      raise "MrubyBridgeSignaturePlugin: not handle type 2 #{ttype}"
+    else
+      raise "MrubyBridgeSignaturePlugin: not handle type 2 #{ttype}"
+    end
+=end
+    if( param.get_size ) then
+      sz_str = param.get_size.to_s
+    elsif param.get_string then      # mikan ã¨ãããã size_is ã¨ string ã®åææå® (äºéãã¤ã³ã¿) ã¯ãªã
+      sz_str = param.get_string.to_s
+    else
+      sz_str = "1"
+    end
+    # unsigned åã®å ´åã«ã¯ cast ãå¿
+è¦
+    if ttype.get_original_type.get_type_str != param.get_type.get_type.get_type_str then
+      cast_str = "(#{param.get_type.get_type_str})"
+    else
+      cast_str = ""
+    end
+
+    modify = ""
+    case param.get_direction
+    when :OUT, :INOUT
+      case tstr
+      when "Char", "SChar", "UChar"
+        modify = "Mod"
+      end
+    end
+    if param.is_nullable? then
+      nullable = "Nullable"
+    else
+      nullable = ""
+    end
+
+    # file.print "	CHECK_POINTER( #{tstr}, mrb_#{param.get_name}, #{sz_str} );\n"
+    # file.print "	#{param.get_name} = #{cast_str}((struct #{tstr}PointerBody*)(DATA_PTR(mrb_#{param.get_name})))->buf;\n"
+    file.print "	#{param.get_name} = CheckAndGet#{tstr}Pointer#{modify}#{nullable}( mrb, mrb_#{param.get_name}, #{sz_str} );\n"
+  end
+
+  def get_celltype_name
+    @celltype_name
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° ignoreUnsigned
+  def set_ignoreUnsigned rhs
+    if rhs == "true" || rhs == nil then
+      @b_ignoreUnsigned = true
+    end
+  end
+  #=== ãã©ã°ã¤ã³å¼æ° include
+  def set_include rhs
+    funcs = rhs.split ','
+    funcs.each{ |rhs_func|
+      found = false
+      rhs_func.gsub!( /\s/, "" )
+      @signature.get_function_head_array.each{ |a|
+        if rhs_func.to_sym == a.get_name then
+          found = true
+        end
+      }
+      if found == false then
+        cdl_error( "MRB1009 include function '$1' not found in signagture '$2'", rhs, @signature.get_name )
+      else
+        @includes << rhs_func.to_sym
+      end
+    }
+  end
+  #=== ãã©ã°ã¤ã³å¼æ° exclude
+  def set_exclude rhs
+    funcs = rhs.split ','
+    funcs.each{ |rhs_func|
+      rhs_func.gsub!( /\s/, "" )
+      func_head = @signature.get_function_head rhs_func.to_sym
+      if func_head == false then
+        cdl_error( "MRB1010 exclude function '$1' not found in signagture '$2", rhs, @signature.get_name )
+      else
+        @excludes << rhs_func.to_sym
+      end
+    }
+  end
+  #=== ãã©ã°ã¤ã³å¼æ° auto_exclude
+  def set_auto_exclude rhs
+    if rhs == "false" then
+      @b_auto_exclude = false
+    elsif rhs == "true" then
+      @b_auto_exclude = true     # auto_exclude = true by default 
+    else
+      cdl_warning( "MRB9999 auto_exclude: unknown rhs value ignored. specify true or false" )
+    end
+  end
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MultiPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MultiPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/MultiPlugin.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2017 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/NotifierPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/NotifierPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/NotifierPlugin.rb	(revision 374)
@@ -1,3 +1,6 @@
 # -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
 #
 #  Copyright (C) 2015 by Ushio Laboratory
@@ -5,5 +8,38 @@
 #  Copyright (C) 2015-2016 by Embedded and Real-Time Systems Laboratory
 #              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2015-2018 by TOPPERS Project
 #
+#--
+#   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
+#   ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#   変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#   (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#       権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#       スコード中に含まれていること．
+#   (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#       用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#       者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#       の無保証規定を掲載すること．
+#   (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#       用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#       と．
+#     (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#         作権表示，この利用条件および下記の無保証規定を掲載すること．
+#     (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#         報告すること．
+#   (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#       害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#       また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#       由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#       免責すること．
+#  
+#   本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#   よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#   に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#   アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#   の責任を負わない．
+#  
+#  $Id$
+#++
 
 NotifierPluginArgProc = {
@@ -128,6 +164,7 @@
 			# @param [Cell, Symbol] cell セル．セルについて一般化する場合は `:generic`
 			# @param [Integer, Symbol, nil] subscript 添字．添字について一般化する場合は `:generic`
+			# @param [Celltype] 呼び先のセルタイプ、cell==:generic の場合のみ有効
 			# @private
-			def generate_inner(context, fn_name, cell, subscript)
+			def generate_inner(context, fn_name, cell, subscript, callee_ct=nil)
 				source_file = context.source_file
 				header_file = context.header_file
@@ -141,5 +178,6 @@
 				unless ct.is_singleton?
 					if cell == :generic
-						params << "(CELLIDX)extinf"
+						params << "(#{callee_ct.get_global_name}_IDX)extinf"
+						# params << "(CELLIDX)extinf"
 					else
 						# セルのCELLIDXを得る
@@ -233,5 +271,5 @@
 
 						generate_inner context, fn_name,
-							:generic, subscript
+							:generic, subscript, ct
 
 						props.each { |prop|
@@ -445,5 +483,5 @@
 	    # join:: Join : 結合 (declarationがPortであるもの)
 		def validate_join(handler, cell, join)
-        	return !generate_attr_map(handler, cell).nil?
+        return !generate_attr_map(handler, cell).nil?
 		end
 
@@ -872,9 +910,9 @@
     	parse_plugin_arg
     	unless @factory
-    		cdl_error("ASP1003 celltype $1: option factory is not specified",
+    		cdl_error("NTF1003 celltype $1: option factory is not specified",
     			celltype.get_name)
     	end
     	unless @output_file
-    		cdl_error("ASP1003 celltype $1: option output_file is not specified",
+    		cdl_error("NTF1003 celltype $1: option output_file is not specified",
     			celltype.get_name)
     	end
@@ -883,5 +921,5 @@
     def set_factory(template_string)
     	unless @factory.nil?
-    		cdl_error("ASP1003 celltype $1: option factory was specified more than once",
+    		cdl_error("NTF1003 celltype $1: option factory was specified more than once",
     			celltype.get_name)
     	end
@@ -891,5 +929,5 @@
     def set_factory_output_file(output_file)
     	unless @output_file.nil?
-    		cdl_error("ASP1003 celltype $1: option output_file was specified more than once",
+    		cdl_error("NTF1003 celltype $1: option output_file was specified more than once",
     			celltype.get_name)
     	end
@@ -898,5 +936,5 @@
 
     def gen_factory file
-        puts "===== begin #{@celltype.get_name.to_s} plugin ====="
+        # puts "===== begin #{@celltype.get_name.to_s} plugin ====="
 
         kernelCfg = AppFile.open( "#{$gen}/#{@output_file}" )
@@ -922,5 +960,5 @@
 			subst_attr = @celltype.find(name)
 			unless subst_attr
-	    		cdl_error( "ASP1007 celltype $1: additional_param: attribute $2 does not exist.",
+	    		cdl_error( "NTF1007 celltype $1: additional_param: attribute $2 does not exist.",
 	    			@celltype.get_name, name)
 			end
@@ -935,8 +973,9 @@
 
         kernelCfg.close
-        puts "===== end #{@celltype.get_name.to_s} plugin ====="
+        # puts "===== end #{@celltype.get_name.to_s} plugin ====="
     end
 
     def gen_factory_for_cell(kernelCfg, cell)
+      # print "########## gen_factory_for_cell cell=#{cell.get_name}\n"
     	handler_flags = []
     	handler_args = []
@@ -959,12 +998,28 @@
 			when 'false' then ignoreErrors = false
 			else
-				cdl_warning( "ASP1005 cell $1: unrecognized value '$2' specified for ignoreErrors",
+				cdl_warning2( cell.get_locale, "NTF1005 cell $1: unrecognized value '$2' specified for ignoreErrors",
 					cell.get_name, ignoreErrors )
 				ignoreErrors = false
 		end
 
+    # ドメイン指定用文字列
+    pre_text  = ""
+    post_text = "\n"
+    indent    = ""
+ 
     	[EVENT_HANDLER, ERROR_HANDLER].each { |handler|
     		# 呼び口の結合を取得
     		call_join = cell.get_join_list.get_item(handler.call_port_name.to_sym)
+        domain_root = cell.get_region.get_domain_root
+        if cell.get_region.get_domain_root.get_domain_type then
+          # print "cell=#{cell.get_name} domain_root=#{domain_root.get_name} domain_type=#{domain_root.get_domain_type.get_name} domain_option=#{domain_root.get_domain_type.get_option}\n"
+        else
+          # print "cell=#{cell.get_name} domain_root=#{cell.get_region.get_domain_root.get_name}\n"
+        end
+        if call_join
+          # print "validate_join: hanlder=#{handler.class.name} cell=#{cell.get_name} join=#{call_join.get_name} rhs_cell=#{call_join.get_cell}\n"
+        else
+          # print "validate_join: hanlder=#{handler.class.name} cell=#{cell.get_name}\n"
+        end
 
 	    	# ハンドラタイプを判別する
@@ -974,10 +1029,59 @@
 
 	    	if matches.length == 0
-	    		cdl_error( "ASP1001 cell $1: no matching handler type found for $2", cell.get_name, handler.call_port_name )
+	    		cdl_error2( cell.get_locale, "NTF1001 cell $1: no matching handler type found for $2", cell.get_name, handler.call_port_name )
 	    		next
-	    	end
+        end
 
 			# 最初に見つかった有効なハンドラタイプを使用
 	    	ht = matches[0]
+
+      # ドメインプラグインが指定されている場合、所属ドメインのチェック
+      domain_root = cell.get_region.get_domain_root
+      if domain_root.get_domain_type then
+        if domain_root.get_domain_type.get_name == :HRP then
+          option = domain_root.get_domain_type.get_option
+          matches.each{ |match|
+            # p "match:#{match}"
+            case match
+            when ActivateTaskHandlerType,       WakeUpTaskHandlerType,
+                 SetVariableHandlerType,        SetVariableToErrorCodeHandlerType,
+ 		             IncrementVariableHandlerType,  SignalSemaphoreHandlerType, 
+		             SetEventflagHandlerType,       SendToDataqueueHandlerType,
+		             SendErrorCodeToDataqueueHandlerType
+              if option == "OutOfDomain" then
+                cdl_error2( cell.get_locale, "NTF9999: NotifierPlugin: $1 cannot be placed out of domain", cell.get_name )
+              elsif call_join.get_cell.get_region.get_domain_root == nil ||
+                    call_join.get_cell.get_region.get_domain_root != domain_root then
+                cdl_error2( cell.get_locale, "NTF9999: NotifierPlugin: $1 and $2 must be placed in same domain", cell.get_name, call_join.get_cell.get_name )
+              end
+              dbgPrint "#{self.class.name}: match pattern 1.\n"
+            when UserHandlerType
+              if option != "kernel" then
+                cdl_error2( cell.get_locale, "NTF9999: NotifierPlugin: $1 can be placed in kernel domain only, because notify target is handler", cell.get_name )
+              elsif call_join.get_cell.get_region.get_domain_root == nil ||
+                    call_join.get_cell.get_region.get_domain_root != domain_root then
+                cdl_error2( cell.get_locale, "NTF9999: NotifierPlugin: $1 and $2 must be placed in same domain", cell.get_name, call_join.get_cell.get_name )
+              end
+              dbgPrint "#{self.class.name}: match pattern 2.\n"
+		        when NullHandlerType.new  # エラー通知を指定していない
+              dbgPrint "#{self.class.name}: match pattern 3.\n"
+            end
+          }
+
+          # if cell.get_region.get_param == :KERNEL_DOMAIN
+          if option == "kernel"
+            pre_text  = "KERNEL_DOMAIN{\n"
+            post_text = "}\n"
+            indent    =  "\t"
+          elsif option != "OutOfDomain" then
+            pre_text  = "DOMAIN(#{domain_root.get_name.to_s}){\n"
+            post_text = "}\n"
+            indent    =  "\t"
+          end
+        else
+          cdl_error( "NTF9999: NotifierPlugin: unknown domain type $1", domain_root.get_domain_type.get_name )
+        end
+
+      end
 
 			# 通知ハンドラで「エラーが発生するはずがない」のに「エラーハンドラが指定されている」
@@ -986,9 +1090,9 @@
 			#  なため、検出は行わない。)
     		if handler == ERROR_HANDLER && !ht.is_a?(NullHandlerType) && !event_handler_might_fail
-	    		cdl_error( "ASP1004 cell $1: handler type $2 which never raises an error was inferred for the normal notification handler, but an error notification handler was specified.",
+	    		cdl_error2( cell.get_locale, "NTF1004 cell $1: handler type $2 which never raises an error was inferred for the normal notification handler, but an error notification handler was specified.",
 	    			cell.get_name, handler_flag)
     		end
     		if handler == ERROR_HANDLER && ht.is_a?(NullHandlerType) && event_handler_might_fail && !ignoreErrors
-	    		cdl_warning( "ASP1006 cell $1: handler type $2 which might raise an error was inferred for the normal notificaton handler, but an error notification handler was not specified.",
+	    		cdl_warning2( cell.get_locale, "NTF1006 cell $1: handler type $2 which might raise an error was inferred for the normal notificaton handler, but an error notification handler was not specified.",
 	    			cell.get_name, handler_flag)
     		end
@@ -1057,11 +1161,33 @@
 			# $id$等の置換
 			cell.get_celltype.subst_name(subst, name_array)
-    	}
-
-    	# 出力
-    	kernelCfg.puts text
-
-    end
-    private :gen_factory_for_cell
+      }
+
+     # 出力 (CRE_xxx)
+     kernelCfg.print pre_text
+     kernelCfg.print indent, text, "\n"
+     gen_sac kernelCfg, cell, indent
+     kernelCfg.print post_text
+   end
+
+   def gen_sac file, cell, indent
+     domain_root = cell.get_region.get_domain_root
+     if domain_root.get_domain_type then
+       id = (cell.get_attr_initializer :id).to_s
+                 name_array = cell.get_celltype.get_name_array(cell)
+       case cell.get_celltype.get_name
+       when :tCyclicNotifier
+         obj_type = "CYC"
+       when :tAlarmNotifier
+         obj_type = "ALM"
+       else
+         raise "NotifierPlugin: unknown celltype #{cell.get_celltype.get_name}"
+       end
+       id = cell.get_celltype.subst_name(id, name_array)
+       # p obj_type
+       # p HRPPlugin.get_sac_str cell
+       file.print indent, "SAC_#{obj_type}( #{id}, #{HRPPlugin.get_sac_str cell} );\n"
+     end
+   end
+   private :gen_factory_for_cell
 
 end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/OpaqueRPCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/OpaqueRPCPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/OpaqueRPCPlugin.rb	(revision 374)
@@ -56,5 +56,5 @@
   #=== RPCPlugin の initialize
   #  説明は ThroughPlugin (plugin.rb) を参照
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
     super
     @b_noClientSemaphore = false
@@ -254,4 +254,9 @@
     nest = @end_region.gen_region_str_pre file
     nest_str = "  " * nest
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     if @serverErrorHandler then
@@ -282,5 +287,5 @@
 #{nest_str}  cell #{@rpc_server_channel_celltype_name} #{@serverChannelCell}_Unmarshaler {
 #{nest_str}    cChannel = #{@serverChannelCell}.eC1;
-#{nest_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name};
+#{nest_str}    #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
 #{serverErrorHandler_str}#{nest_str}  };
 EOT
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RPCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RPCPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RPCPlugin.rb	(revision 374)
@@ -65,5 +65,5 @@
   #=== RPCPlugin の initialize
   #  説明は ThroughPlugin (plugin.rb) を参照
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
     super
     @b_noClientSemaphore = false
@@ -197,4 +197,9 @@
     nest = @region.gen_region_str_pre file
     indent_str = "  " * nest
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     file.print <<EOT
@@ -233,5 +238,5 @@
     file.print <<EOT
 #{indent_str}cell #{@rpc_channel_celltype_name} #{@cell_name} {
-#{indent_str}  #{@call_port_name} = #{@next_cell.get_name}.#{@next_cell_port_name};
+#{indent_str}  #{@call_port_name} = #{@next_cell.get_name}.#{@next_cell_port_name}#{subscript};
 #{indent_str}  cTDR         = #{@channelCellName}.eTDR;
 #{indent_str}  cEventflag   = #{@channelCellName}.eEventflag;
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RepeatCellPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RepeatCellPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RepeatCellPlugin.rb	(revision 374)
@@ -0,0 +1,185 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#
+#  Copyright (C) 2015-2018 by TOPPERS Project
+#
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#  $Id$
+#++
+
+#== cell ã count åç¹°ãè¿ãã»ã«ãã©ã°ã¤ã³
+# ä¸å®å
+¨ç¹ï¼
+#    æå®å­ã«å¯¾å¿ãã¦ããªã
+#       cell ã®æå®å­ (allocator, id)
+#       çµåã®æå®å­ (through)
+class RepeatCellPlugin < CellPlugin
+
+  @@plugin_list = []
+  RepeatCellPluginArgProc = {
+    "count" => Proc.new { |obj,rhs| obj.set_count rhs }
+  }
+
+  def initialize( cell, option )
+    super
+    @@plugin_list << self
+    print "RepeatCellPlugin: #{@cell.get_name}\n"
+    # cell.show_tree 0
+    # @cell.get_join_list.get_items.each{ |j|
+    #  print "Join: #{j.get_name} = #{j.get_rhs.to_s}\n"
+    # }
+    @count = 0
+    @plugin_arg_check_proc_tab = RepeatCellPluginArgProc
+    parse_plugin_arg
+  end
+
+  def gen_cdl_file( file )
+    if $verbose then
+      print "#{self.class}: repeat #{@cell.get_name} #(num} times\n"
+    end
+
+    nest = @cell.get_region.gen_region_str_pre file
+    indent_str = "  " * nest
+    @cell.get_name.to_s =~ /.*[^0-9]([0-9]+)\z/
+    if $1 then
+      tail_zero = $1
+      bname = @cell.get_name.to_s.gsub( /[0-9]+\z/, "" )
+    else
+      cdl_error( "#{self.class}: #{@cell.get_name}'s name ends without '0-9'")
+      return
+    end
+    base_count = tail_zero.to_i
+
+    count = 1
+    num = @count
+    file.print "/*  #{num} times repeat of '#{@cell.get_name}' */\n"
+    while count < num
+
+      # ã»ã«åã®ã«ã¦ã³ã
+      count_str = (count + base_count).to_s
+      if tail_zero.length > count_str.length then
+        leading_zero = "0" * ( tail_zero.length - count_str.length )
+      else
+        leading_zero = ""
+      end
+      cname = bname + leading_zero + count_str
+
+      #   "cell tCelltype Cell {" 
+      file.print "#{indent_str}cell #{@cell.get_celltype.get_name} #{cname}{\n"
+
+      # Join ã® CDL æå­åçæ
+      @cell.get_join_list.get_items.each{ |j|
+
+        # Join ã®å³è¾ºã®è§£æ
+        res = j.get_rhs.analyze_cell_join_expression
+        if res then
+          nsp, subscript, port_name = res[0], res[1], res[2]
+        else
+          nsp = j.get_rhs.analyze_single_identifier
+          if nsp then
+            subscript, port_name = nil, nil
+          else
+            file.print "#{indent_str}  #{j.get_name} = #{j.get_rhs.to_s};\n"
+            next
+          end
+        end
+
+        # å³è¾ºã®ã»ã«å (æ«å°¾ã®æ°å­ãã«ã¦ã³ãã¢ãã)
+        nsp.get_name.to_s =~ /(.*[^0-9])([0-9]+)\z/
+        if $2 then
+          rhs_tail_num = $2
+          rhs_name_count = count + rhs_tail_num.to_i
+          if rhs_tail_num.length > rhs_name_count.to_s.length then
+            leading_zero = "0" * ( rhs_tail_num.length - rhs_name_count.to_s.length )
+          else
+            leading_zero = ""
+          end
+          rhs_cname = $1 + leading_zero + rhs_name_count.to_s
+          nsp = nsp.change_name_clone rhs_cname
+        end
+
+        # Join æå­åã®åºå
+        if port_name then
+          # å³è¾ºã¯ ã»ã«ã®çµå
+          if subscript then
+            file.print "#{indent_str}  #{j.get_name} = #{nsp.get_path_str}.#{port_name}[#{(count+subscript).to_s}];\n"
+          else
+            file.print "#{indent_str}  #{j.get_name} = #{nsp.get_path_str}.#{port_name};\n"
+          end
+        else
+          # å³è¾ºã¯åä¸ã®è­å¥å­
+          file.print "#{indent_str}  #{j.get_name} = #{nsp.get_path_str};\n"
+        end
+      }
+
+      file.print "#{indent_str}};\n\n"
+      count += 1
+    end
+
+    @cell.get_region.gen_region_str_post file
+  end
+
+  #=== count ãªãã·ã§ã³ã®è§£æ
+  def set_count rhs
+    if rhs =~ /\A\d+\z/
+      @count = rhs.to_i
+    else
+      nsp = NamespacePath.new( rhs.to_sym, true )
+      expr = Expression.create_single_identifier( nsp, nil )
+      res = expr.eval_const( nil )
+      if res == nil then
+        cdl_error( "count value ($1): not single identifier or integer number", rhs.to_s )
+        @count = 0
+      else
+        @count = res
+      end
+    end
+  end
+
+end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RepeatJoinPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RepeatJoinPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/RepeatJoinPlugin.rb	(revision 374)
@@ -0,0 +1,147 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#
+#  Copyright (C) 2015-2018 by TOPPERS Project
+#
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#  $Id$
+#++
+
+class RepeatJoinPlugin < CellPlugin
+
+  RepeatJoinPluginArgProc = {
+    "count" => Proc.new { |obj,rhs| obj.set_count rhs }
+  }
+
+  def initialize( cell, option )
+    super
+    print "RepeatJoinPlugin: #{@cell.get_name}\n"
+    # cell.show_tree 0
+    @plugin_arg_check_proc_tab = RepeatJoinPluginArgProc
+    parse_plugin_arg
+
+    @cell.get_join_list.get_items.each{ |j|
+      # print "Join: #{j.get_name} = #{j.get_rhs.to_s}\n"
+
+      # Join ã®å³è¾ºãè§£æ
+      ret = j.get_rhs.analyze_cell_join_expression
+      if ret == nil then
+        next
+      end
+      rhs_nsp = ret[0]; rhs_subscript = ret[1]; rhs_port_name = ret[2]
+
+      # å¼ã³å£é
+åã§ãæ·»æ°ã 0 ã®å ´åã«ã®ã¿ã«ã¦ã³ãã¢ããããã
+      if j.get_subscript == 0 then
+        rhs_name = rhs_nsp.get_name.to_s
+        if rhs_name =~ /(.*[^0-9])([0-9]+)\z/ then
+          b_rhs_name_count = true
+          rhs_name = $1
+          n_digits = $2.length
+          rhs_count_base = $2.to_i
+        else
+          b_rhs_name_count = false
+          rhs_count_base = 0
+        end
+
+        if rhs_subscript && rhs_subscript == 0 then
+          b_rhs_subscript_count = true
+        else
+          b_rhs_subscript_count = false
+        end
+
+        count = 1
+        while count < @count
+          count_str = (count+rhs_count_base).to_s
+
+          if b_rhs_subscript_count then
+            rhs_subscript = count
+          end
+
+          if b_rhs_name_count then
+            if n_digits - count_str.length > 0 then
+              leading_zero = "0" * ( n_digits - count_str.length )
+            else
+              leading_zero = ""
+            end
+
+            rhs_name_real = rhs_name + leading_zero + count_str
+          else
+            rhs_name_real = rhs_name
+          end
+          rhs_nsp2 = rhs_nsp.change_name_clone rhs_name_real.to_sym
+
+          rhs = Expression.create_cell_join_expression( rhs_nsp2, rhs_subscript, rhs_port_name )
+          j2 = Join.new( j.get_name, count, rhs )
+          cell.new_join j2
+
+          count += 1
+        end
+      end
+    }
+  end
+
+  #=== count ãªãã·ã§ã³ã®è§£æ
+  def set_count rhs
+    if rhs =~ /\A\d+\z/
+      @count = rhs.to_i
+    else
+      nsp = NamespacePath.new( rhs.to_sym, true )
+      expr = Expression.create_single_identifier( nsp, nil )
+      res = expr.eval_const( nil )
+      if res == nil then
+        cdl_error( "count value ($1): not single identifier or integer number", rhs.to_s )
+        @count = 0
+      else
+        @count = res
+      end
+    end
+  end
+
+end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/SharedOpaqueRPCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/SharedOpaqueRPCPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/SharedOpaqueRPCPlugin.rb	(revision 374)
@@ -68,5 +68,5 @@
   #=== RPCPlugin の initialize
   #  説明は ThroughPlugin (plugin.rb) を参照
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
     super
     initialize_opaque_marshaler
@@ -221,4 +221,10 @@
     nest = @start_region.gen_region_str_pre file
     indent_str = "  " * nest
+    nest_str = "  " * nest
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     # セルを探す
@@ -303,5 +309,5 @@
 #{indent_str}cell #{@unmarshaler_celltype_name} #{@cell_name}_Server {
 #{indent_str}  cTDR         = #{@shared_channel_cell}_Server.eTDR;
-#{indent_str}  cServerCall  = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name};
+#{indent_str}  cServerCall  = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
 #{ppallocator_join}#{indent_str}};
 EOT
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/SharedRPCPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/SharedRPCPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/SharedRPCPlugin.rb	(revision 374)
@@ -62,5 +62,5 @@
   #=== RPCPlugin の initialize
   #  説明は ThroughPlugin (plugin.rb) を参照
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
 
     # mikan プラグインオプション指定の不一致のチェック task_priority, 
@@ -236,4 +236,9 @@
     nest = @region.gen_region_str_pre file
     indent_str = "  " * nest
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     # セルを探す
@@ -291,5 +296,5 @@
     file.print <<EOT
 #{indent_str}cell #{@rpc_channel_celltype_name} #{@cell_name} {
-#{indent_str}  #{@call_port_name} = #{@next_cell.get_name}.#{@next_cell_port_name};
+#{indent_str}  #{@call_port_name} = #{@next_cell.get_name}.#{@next_cell_port_name}#{subscript};
 #{indent_str}  cTDR         = #{@shared_channel_cell}.eTDR;
 #{indent_str}  cEventflag   = #{@shared_channel_cell}.eEventflag;
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/TECSInfoPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/TECSInfoPlugin.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/TECSInfoPlugin.rb	(revision 374)
@@ -0,0 +1,299 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+# 
+#   Copyright (C) 2017-2018 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#++
+
+#== CelltypePlugin for tTECSInfo
+class TECSInfoPlugin < CelltypePlugin
+
+  @@cell_list = []
+  #@celltype::Celltype
+  #@plugin_arg_str::String
+  #@plugin_arg_list::{argNameString=>argOptionString}
+  #@cell_list::[Cell]
+
+  #celltype::     Celltype        ã»ã«ã¿ã¤ãï¼ã¤ã³ã¹ã¿ã³ã¹ï¼
+  def initialize( celltype, option )
+    super
+    if $unopt_entry == false then
+      cdl_info( "TIF0001 forcely set --unoptimize-entry by TECSInfoPlugin (by importing TECSInfo.cdl)" )
+      $unopt_entry = true
+    end
+  end
+
+  #=== æ°ããã»ã«
+  #cell::        Cell            ã»ã«
+  #
+  # celltype ãã©ã°ã¤ã³ãæå®ãããã»ã«ã¿ã¤ãã®ã»ã«ãçæããã
+  # ã»ã«ã¿ã¤ããã©ã°ã¤ã³ã«å¯¾ããæ°ããã»ã«ã®å ±å
+  def new_cell( cell )
+    @@cell_list << cell
+
+    # AppFile ã¯ãéã­æ¸ããããªã®ã§ãããã
+    # p "import: cell nTECSInfo::tTECSInfoSub #{cell.get_namespace_path.to_s} under #{cell.get_region.get_name}"
+    # cell.show_tree 0
+    # TECSInfoSub ã»ã«ã®ãã­ãã¿ã¤ãå®£è¨
+    fn = "#{$gen}/tmp_#{cell.get_region.get_global_name}_TECSInfoSub.cdl"
+    File.open( fn, "w" ){ |f|
+      f.print "/* prototype declaration of TECSInfoSub */\n"
+      nest = cell.get_region.gen_region_str_pre f
+      indent = "    " * nest
+      f.print <<EOT
+#{indent}[in_through()]
+#{indent}region rTECSInfo {
+#{indent}    cell nTECSInfo::tTECSInfoSub TECSInfoSub;
+#{indent}}; /* rTECSInfo} */
+EOT
+      cell.get_region.gen_region_str_post f
+    }
+    Import.new fn
+
+    # ã»ã«ã« cTECSInfo ã®çµåããããï¼
+    if cell.get_join_list.get_item( :cTECSInfo ) == nil then
+      # cTECSInfo = rTECSInfo::TECSInfosub.eTECSInfo; ã®è¿½å 
+      nsp = NamespacePath.new( :rTECSInfo, false )
+      nsp.append! :TECSInfoSub
+      rhs = Expression.create_cell_join_expression nsp, nil, :eTECSInfo
+      join = Join.new :cTECSInfo, nil, rhs
+      cell.new_join join
+    end
+  end
+
+  #=== tCelltype_factory.h ã«æ¿å
+¥ããã³ã¼ããçæãã
+  # file ä»¥å¤ã®ä»ã®ãã¡ã¤ã«ã«ãã¡ã¯ããªã³ã¼ããçæãã¦ããã
+  # ã»ã«ã¿ã¤ããã©ã°ã¤ã³ãæå®ãããã»ã«ã¿ã¤ãã®ã¿å¼ã³åºããã
+  def gen_factory file
+    File.open( "#{$gen}/include_all_signature_header.h", "w" ){ |f|
+      f.print <<EOT
+#ifndef include_all_signature_header_h
+#define include_all_signature_header_h
+
+EOT
+      Namespace.get_root.travers_all_signature{ |sig|
+        f.print "#include \"#{sig.get_global_name}_tecsgen.h\"\n"
+      }
+      f.print <<EOT
+
+#endif /* include_all_signature_header_h */
+EOT
+    }
+
+    undefs2 = [ :INITIALIZE_CB, :FOREACH_CELL, :END_FOREACH_CELL ]
+    f = AppFile.open( "#{$gen}/nTECSInfo_tVarDeclInfo_factory.h" )
+    Namespace.get_root.print_struct_define f
+
+    undefs = [ :VALID_IDX, :GET_CELLCB, :CELLCB, :CELLIDX,
+               :tVarDeclInfo_IDX, :ATTR_name, :ATTR_sizeIsExpr,
+               :ATTR_declType, :ATTR_offset ]
+
+    f.print <<EOT
+
+/***** Offset of attr & var of celltype  *****/
+#define TOPPERS_CB_TYPE_ONLY
+
+/* In case a celltype has 'inline' entry,
+ * some macros are temporally defined
+ * even if TOPPERS_CB_TYPE_ONLY is defined.
+ * To avoid redefinition warning, undef these macros.
+ */
+#{ str=""; undefs.each{|u| str += "#undef #{u}\n" }; str }
+EOT
+    if $ram_initializer then
+      undefs2.each{|u|
+        f.print "#undef #{u}\n"
+      }
+    end
+    Namespace.get_root.print_celltype_define_offset f
+    f.print <<EOT
+
+/* redefine macros */
+#define tVarDeclInfo_IDX  nTECSInfo_tVarDeclInfo_IDX
+
+EOT
+    if $ram_initializer then
+      f.print <<EOT
+#define FOREACH_CELL(i,p_cb)   { (void)(i);
+#define END_FOREACH_CELL   }
+#define INITIALIZE_CB(p_that)   (void)(p_that);
+#define SET_CB_INIB_POINTER(i,p_that)
+EOT
+    end
+    f.close
+
+    undefs = [ :N_CP_cEntryInfo, :NCP_cEntryInfo, :N_CP_cCallInfo, :NCP_cCallInfo,
+               :N_CP_cAttrInfo, :NCP_cAttrInfo, :N_CP_cVarInfo, :NCP_cVarInfo,
+               :VALID_IDX, :GET_CELLCB, :CELLCB, :CELLIDX, :ATTR_name, :ATTR_b_singleton,
+               :ATTR_b_IDX_is_ID_act, :ATTR_sizeOfCB, :ATTR_sizeOfINIB, :ATTR_n_cellInLinUnit,
+               :ATTR_n_cellInSystem, :cEntryInfo_getName, :cEntryInfo_getNameLength,
+               :cEntryInfo_getSignatureInfo, :cEntryInfo_getArraySize, :cEntryInfo_isInline,
+               :cCallInfo_getName, :cCallInfo_getNameLength, :cCallInfo_getSignatureInfo,
+               :cCallInfo_getArraySize, :cCallInfo_getSpecifierInfo, :cCallInfo_getInternalInfo,
+               :cCallInfo_getLocationInfo, :cCallInfo_getOptimizeInfo, :cAttrInfo_getName,
+               :cAttrInfo_getOffset, :cAttrInfo_getTypeInfo, :cAttrInfo_getSizeIsExpr,
+               :cAttrInfo_getSizeIs, :cVarInfo_getName, :cVarInfo_getOffset, :cVarInfo_getTypeInfo,
+               :cVarInfo_getSizeIsExpr, :cVarInfo_getSizeIs, :cEntryInfo_refer_to_descriptor,
+               :cEntryInfo_ref_desc, :cCallInfo_refer_to_descriptor, :cCallInfo_ref_desc,
+               :cAttrInfo_refer_to_descriptor, :cAttrInfo_ref_desc, :cVarInfo_refer_to_descriptor,
+               :cVarInfo_ref_desc, :is_cEntryInfo_joined, :is_cCallInfo_joined,
+               :is_cAttrInfo_joined, :is_cVarInfo_joined, :eCelltypeInfo_getName,
+               :eCelltypeInfo_getNameLength, :eCelltypeInfo_getNAttr, :eCelltypeInfo_getAttrInfo,
+               :eCelltypeInfo_getNVar, :eCelltypeInfo_getVarInfo, :eCelltypeInfo_getNCall,
+               :eCelltypeInfo_getCallInfo, :eCelltypeInfo_getNEntry, :eCelltypeInfo_getEntryInfo,
+               :eCelltypeInfo_isSingleton, :eCelltypeInfo_isIDX_is_ID, :eCelltypeInfo_hasCB,
+               :eCelltypeInfo_hasINIB, :FOREACH_CELL, :END_FOREACH_CELL ]
+
+    f = AppFile.open( "#{$gen}/nTECSInfo_tCelltypeInfo_factory.h" )
+    undefs.each{ |u|
+      f.print "#undef #{u}\n"
+    }
+    f.print "#define TOPPERS_CB_TYPE_ONLY\n"
+    Namespace.get_root.print_celltype_define f
+    # FOREACH_CELL ãåºããªãã
+    ct = Namespace.find [ "::", :nTECSInfo, :tCelltypeInfo ]
+    ct.gen_ph_foreach_cell f
+    ct.gen_ph_cb_initialize_macro f
+    f.print "\n"
+    f.close
+   
+    undefs = [ :VALID_IDX, :GET_CELLCB, :CELLCB, :CELLIDX,
+               :tCallInfo_IDX, :ATTR_name, :ATTR_offset, :ATTR_b_inCB,
+               :ATTR_b_optional, :ATTR_b_omit, :ATTR_b_dynamic,
+               :ATTR_b_ref_desc, :ATTR_b_allocator_port,
+               :ATTR_b_require_port, :ATTR_b_VMT_useless,
+               :ATTR_b_skelton_useless, :ATTR_b_cell_unique,
+               :cSignatureInfo_getName, :cSignatureInfo_getNameLength,
+               :cSignatureInfo_getNFunction,
+               :cSignatureInfo_getFunctionInfo,
+               :cSignatureInfo_refer_to_descriptor,
+               :cSignatureInfo_ref_desc, :eCallInfo_getName,
+               :eCallInfo_getNameLength, :eCallInfo_getSignatureInfo,
+               :eCallInfo_getArraySize, :eCallInfo_isOptional,
+               :eCallInfo_isDynamic, :eCallInfo_isRefDesc,
+               :eCallInfo_isOmit ]
+
+    f = AppFile.open( "#{$gen}/nTECSInfo_tCallInfo_factory.h" )
+    f.print <<EOT
+
+/***** Offset of attr & var of celltype  *****/
+#define TOPPERS_CB_TYPE_ONLY
+
+/* In case a celltype has 'inline' entry,
+ * some macros are temporally defined
+ * even if TOPPERS_CB_TYPE_ONLY is defined.
+ * To avoid redefinition warning, undef these macros.
+ */
+#{ str=""; undefs.each{|u| str += "#undef #{u}\n" }; str }
+EOT
+    if $ram_initializer then
+      undefs2.each{|u|
+        f.print "#undef #{u}\n"
+      }
+    end
+
+    Namespace.get_root.print_call_define f
+    f.print <<EOT
+
+/* redefine macros */
+#define tCallInfo_IDX  nTECSInfo_tCallInfo_IDX
+
+EOT
+    if $ram_initializer then
+      f.print <<EOT
+#define FOREACH_CELL(i,p_cb)   { (void)(i);
+#define END_FOREACH_CELL   }
+#define INITIALIZE_CB(p_that)   (void)(p_that);
+#define SET_CB_INIB_POINTER(i,p_that)
+
+EOT
+    end
+    f.close
+
+    f = AppFile.open( "#{$gen}/nTECSInfo_tEntryInfo_factory.h" )
+    Namespace.get_root.print_entry_define f
+    f.close
+
+    undefs = [ :GET_CELLCB, :CELLCB, :CELLIDX, :ATTR_name, :INITIALIZE_CB, :FOREACH_CELL ]
+    f = AppFile.open( "#{$gen}/nTECSInfo_tCellInfo_factory.h" )
+    undefs.each{ |u|
+      f.print "#undef #{u}\n"
+    }
+    Region.get_root.print_cell_define f
+    # FOREACH_CELL ãåºããªãã
+    ct = Namespace.find [ "::", :nTECSInfo, :tCellInfo ]
+    ct.gen_ph_foreach_cell f
+    ct.gen_ph_cb_initialize_macro f
+    f.close
+
+    f = AppFile.open( "#{$gen}/nTECSInfo_tRawEntryDescriptorInfo_factory.h" )
+    Region.get_root.print_entry_descriptor_define f
+    f.close
+  end
+
+  #=== å¾ãã® CDL ã³ã¼ããçæ
+  #ãã©ã°ã¤ã³ã®å¾ãã® CDL ã³ã¼ããçæ
+  #file:: File:
+  def self.gen_post_code( file )
+    if Generator.get_n_error > 0 then
+      Generator.info( "I9999 TECSInfoPlugin does not generate TECSInfo code because of early error" )
+      return
+    end
+    # è¤æ°ã®ãã©ã°ã¤ã³ã® post_code ãä¸ã¤ã®ãã¡ã¤ã«ã«å«ã¾ãããããä»¥ä¸ã®ãããªè¦åºããã¤ãããã¨
+    file.print <<EOT
+/*------------ #{self.name} post code ------------*/
+EOT
+    @@cell_list.each{|cell|
+      root = cell.get_region # .get_link_root
+      TECSInfo.print_info file, root
+    }
+  end
+end
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ThroughPlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ThroughPlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/ThroughPlugin.rb	(revision 374)
@@ -47,4 +47,5 @@
 #@next_cell:: Cell                    呼び口を結合するセル
 #@next_cell_port_name:: Symbol       呼び口を結合する受口の名前
+#@next_cell_port_subscript::Nil|Integer   呼び口を結合する受口の配列添数．受け口配列でない場合 nil
 #@signature::      Signature          シグニチャ
 #@celltype::       Celltype           呼び先のセルのセルタイプ. through が連接する場合、最終的な呼び先のセルのセルタイプ
@@ -74,8 +75,9 @@
   #next_cell::      Cell               呼び口を接続するセル
   #next_cell_port_name:: Symbol        呼び口を接続する受口の名前
+  #next_cell_port_subscript:: Nil|Integer  呼び口を接続する受口配列添数
   #signature::      Signature          シグニチャ
   #celltype::       Celltype           セルタイプ (呼び先のセルのセルタイプ)
   #caller_cell::    Cell               呼び元のセル．@caller_cell の項を参照
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
     super()
     @cell_name = cell_name                      # 生成すべきセル名（受け口側のセル名）
@@ -83,4 +85,5 @@
     @next_cell = next_cell                      # 呼び先のセル
     @next_cell_port_name = next_cell_port_name
+    @next_cell_port_subscript = next_cell_port_subscript
     @signature = signature
     @entry_port_name = :"eThroughEntry"
@@ -136,4 +139,9 @@
   def get_through_entry_port_name
     @entry_port_name
+  end
+
+  #===  生成されたセルの受け口配列添数を得る
+  def get_through_entry_port_subscript
+    @entry_port_subscript
   end
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/TracePlugin.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/TracePlugin.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/TracePlugin.rb	(revision 374)
@@ -44,5 +44,5 @@
   #=== TracePlugin の initialize
   #  説明は ThroughPlugin (plugin.rb) を参照
-  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, signature, celltype, caller_cell )
+  def initialize( cell_name, plugin_arg, next_cell, next_cell_port_name, next_cell_port_subscript, signature, celltype, caller_cell )
 
     @maxArrayDisplay = 16
@@ -141,4 +141,9 @@
       nest = @region.gen_region_str_pre file
       indent_str =  "  " * nest
+      if @next_cell_port_subscript then
+        subscript = '[' + @next_cell_port_subscript.to_s + ']'
+      else
+        subscript = ""
+      end
 
       if @probeName then
@@ -155,5 +160,5 @@
       file.print <<EOT
 #{indent_str}cell #{@ct_name} #{@cell_name} {
-#{indent_str}  #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name};
+#{indent_str}  #{@call_port_name} = #{@next_cell.get_namespace_path.get_path_str}.#{@next_cell_port_name}#{subscript};
 #{probeName_str}#{caller_cell_str}#{indent_str}};
 EOT
@@ -210,8 +215,13 @@
     }
     file.print( " );\n" )
+    if @next_cell_port_subscript then
+      subscript = '[' + @next_cell_port_subscript.to_s + ']'
+    else
+      subscript = ""
+    end
 
     file.print <<EOT
 \tgetMicroTime( &utime );
-\tsyslog( LOG_INFO, \"Leave: %sTime=%d: #{@next_cell.get_name}.#{@next_cell_port_name}.#{func_name}\", ATTR_probeName_str, utime );
+\tsyslog( LOG_INFO, \"Leave: %sTime=%d: #{@next_cell.get_name}.#{@next_cell_port_name}#{subscript}.#{func_name}\", ATTR_probeName_str, utime );
 EOT
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenHRP2Marshaler.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenHRP2Marshaler.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenHRP2Marshaler.rb	(revision 374)
@@ -35,4 +35,5 @@
 #   の責任を負わない．
 #  
+#   $Id$
 #++
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenOpaqueMarshaler.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenOpaqueMarshaler.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenOpaqueMarshaler.rb	(revision 374)
@@ -4,5 +4,5 @@
 #      Generator for TOPPERS Embedded Component System
 #  
-#   Copyright (C) 2008-2014 by TOPPERS Project
+#   Copyright (C) 2008-2018 by TOPPERS Project
 #--
 #   上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
@@ -464,6 +464,8 @@
 	/* Channel Lock */
 	SET_RPC_STATE( state_, RPCSTATE_CLIENT_GET_SEM );
-	if( is_cLockChannel_joined() )
-		cLockChannel_wait();
+	if( is_cLockChannel_joined() ){
+		if( (ercd_=cLockChannel_wait()) != E_OK )
+			goto error_reset;
+	}
 EOT
 
@@ -554,6 +556,14 @@
 	/* Channel Unlock */
 	SET_RPC_STATE( state_, RPCSTATE_CLIENT_RELEASE_SEM );
-	if( is_cLockChannel_joined() )
-		cLockChannel_signal();
+	if( is_cLockChannel_joined() ){
+		if( (ercd_=cLockChannel_signal()) != E_OK )
+			goto error_reset;
+	}
+EOT
+
+    file.print <<EOT
+	/* state_ is not used in normal case */
+  /* below is to avoid 'set but not used' warnning */
+	(void)state_;
 EOT
 
@@ -630,5 +640,5 @@
         file.print <<EOT
 	}else{
-		return;
+		return E_ID;
 	}
 EOT
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenTransparentMarshaler.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenTransparentMarshaler.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/GenTransparentMarshaler.rb	(revision 374)
@@ -388,5 +388,5 @@
     };
 #{ppallocator_dealloc_str}
-    return;
+    return E_OK;
 
 error_reset:
@@ -394,4 +394,5 @@
         (void)cTDR_reset();
 #{ppallocator_dealloc_str}
+    return E_OK;
 EOT
 
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/MrubyBridgeCelltypePluginModule.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/MrubyBridgeCelltypePluginModule.rb	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/plugin/lib/MrubyBridgeCelltypePluginModule.rb	(revision 374)
@@ -0,0 +1,301 @@
+# -*- coding: utf-8 -*-
+#
+#  TECS Generator
+#      Generator for TOPPERS Embedded Component System
+#  
+#   Copyright (C) 2008-2011 by TOPPERS Project
+#--
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+#  
+#   $Id$
+#++
+
+#== celltype ãã©ã°ã¤ã³ã®å
+±éã®è¦ªã¯ã©ã¹
+module MrubyBridgeCelltypePluginModule
+
+  # ãã©ã°ã¤ã³å¼æ°å => Proc
+  MrubyBridgePluginArgProc = { 
+      "ignoreUnsigned" => Proc.new { |obj,rhs| obj.set_ignoreUnsigned rhs },
+      "include_inner_cell" => Proc.new { |obj,rhs| obj.set_include_inner_cell rhs },
+      "exclude_cell" => Proc.new { |obj,rhs| obj.set_exclude_cell rhs },
+      "exclude_port" => Proc.new { |obj,rhs| obj.set_exclude_port rhs },
+      "exclude_port_func" => Proc.new { |obj,rhs| obj.set_exclude_port_func rhs },
+      "auto_exclude" => Proc.new { |obj,rhs| obj.set_auto_exclude rhs },
+  }
+
+  require_tecsgen_lib( "MrubyBridgeCellPlugin.rb" )
+  @@plugin_list = []
+  @@count = 1
+
+  #celltype::     Celltype        ã»ã«ã¿ã¤ãï¼ã¤ã³ã¹ã¿ã³ã¹ï¼
+  def initialize( celltype, option )
+    dbgPrint "#{self.class.name}: initialzie: #{celltype.get_name}\n"
+
+    super
+    @celltype = celltype
+    @cell_list = []
+    @include_inner_cell = false
+    @exclude_cells = []
+    @exclude_port = []
+    @exclude_port_func = {}
+    @b_ignoreUnsigned = false
+    @b_auto_exclude = true     # auto_exclude = true by default 
+    @@plugin_list << self
+
+    @plugin_arg_check_proc_tab = MrubyBridgePluginArgProc
+    @plugin_arg_str = CDLString.remove_dquote option
+    parse_plugin_arg
+
+    MrubyBridgeCellPlugin.set_gen_post_code_by_dependent
+  end
+
+  #=== æ°ããã»ã«
+  #cell::        Cell            ã»ã«
+  #
+  # celltype ãã©ã°ã¤ã³ãæå®ãããã»ã«ã¿ã¤ãã®ã»ã«ãçæããã
+  # ã»ã«ã¿ã¤ããã©ã°ã¤ã³ã«å¯¾ããæ°ããã»ã«ã®å ±å
+  # generate æã«ããå¼ã³åºãããå ´åãããã¾ã§ã«å®ç¾©ããã cell ã«ã¤ãã¦ã¯ãinitialize ã®ã¿ã¤ãã³ã°ã§å¼ã³åºããã
+  def new_cell( cell )
+    dbgPrint "MrubyBridgeCelltypePluginModule: new_cell: #{cell.get_name}\n"
+
+    return if @cell_list.include? cell   # ãã®è¡ã¯ãæ¬æ¥ä¸è¦ã®ã¯ã
+    if TECSGEN.post_coded?               # post_code ä»¥éã®ã»ã«ã¯å¯¾è±¡ããå¤ã
+      cdl_info( "I9999 MrubyBridgeCelltypePlugin: $1 is excluded because cell generated after post_coded", cell.get_name )
+      return
+    end
+
+    # include_inner_cell option
+    if cell.is_cloned? && @include_inner_cell == false then
+    #   p "#{cell.get_name} excluded"
+      cdl_info( "I9999 MrubyBridgeCelltypePlugin: inner cell $1 is excluded", cell.get_name )
+      return
+    # else
+    #   p "#{cell.get_name} included"
+    end
+
+    # exclude_cell option
+    if @exclude_cells.include?( cell.get_name ) then
+      return
+    end
+
+    opt_str = "ignoreUnsigned=#{@b_ignoreUnsigned}, auto_exclude=#{@b_auto_exclude}"
+    @exclude_port.each{ |port|
+      opt_str += ",exclude_port=#{port}"
+    }
+    @exclude_port_func.each{ |port, funcs|
+      funcs.each{ |func|
+        opt_str += ",exclude_port_func=#{port}.#{func}"
+      }
+    }
+
+    # p "MrubyBridgeCelltypePlugin: opt_str=#{opt_str}"
+
+    fn2 = "#{$gen}/tmp_MrubyBridgeCelltypePluginModule_#{@celltype.get_name}_#{@@count}.cdl"
+    f2 = File.open( fn2, "w" )
+    f2.print <<EOT
+/* MrubyBridgeCelltypePluginModule: celltype=#{@celltype.get_name} */
+generate( MrubyBridgeCellPlugin, #{cell.get_namespace_path}, "#{opt_str}" );
+EOT
+    f2.close
+    dbgPrint "MrubyBridgeCelltypePluginModule new_cell: Import #{fn2}\n"
+    Import.new "#{fn2}"
+    @@count += 1
+  end
+
+### æå³è§£ææ®µéã§å¼ã³åºãããã¡ã½ãã ###
+  #===  CDL ãã¡ã¤ã«ã®çæ
+  #      typedef, signature, celltype, cell ã®ã³ã¼ããçæ
+  #      éè¤ãã¦çæãã¦ã¯ãªããªã
+  #      ãã§ã«çæããã¦ããå ´åã¯åºåããªããã¨ã
+  #      ãããã¯ååã® import ã«ãããéè¤ãé¿ãããã¨ã
+  #file::        FILE       çæãããã¡ã¤ã«
+  def gen_cdl_file file
+#   ãã®æ®µéã§å¼ã³ã ãã¨ generate æãå¼ã³åºãããåã®ã»ã«ã®ã¿ã®åºåã¨ãªã
+    
+#    dbgPrint "MrubyBridgeCelltypePlugin: gen_cdl_file: #{@celltype.get_name}\n"
+#    file.print <<EOT
+#/* MrubyBridgeCelltypePlugin: celltype=#{@celltype.get_name}
+# *
+# *    cell's generate before celltype's generate
+# */
+#
+#EOT
+#    @celltype.get_cell_list.each { |cell|
+#      @cell_list << cell
+#      # mikan option, region
+#      dbgPrint "MrubyBridgeCelltypePlugin: cell=#{cell.get_name}\n"
+#      file.print <<EOT
+#generate( MrubyBridgeCellPlugin, #{cell.get_namespace_path}, "" );
+#EOT
+#    }
+
+  end
+
+  #=== tCelltype_factory.h ã«æ¿å
+¥ããã³ã¼ããçæãã
+  # file ä»¥å¤ã®ä»ã®ãã¡ã¤ã«ã«ãã¡ã¯ããªã³ã¼ããçæãã¦ããã
+  # ã»ã«ã¿ã¤ããã©ã°ã¤ã³ãæå®ãããã»ã«ã¿ã¤ãã®ã¿å¼ã³åºããã
+  def gen_factory file
+  end
+
+  def get_celltype
+    @celltype
+  end
+
+  @@b_gen_post_code_called = false
+  #=== å¾ãã® CDL ã³ã¼ããçæ
+  #ãã©ã°ã¤ã³ã®å¾ãã® CDL ã³ã¼ããçæ
+  #file:: File: 
+  def self.gen_post_code( file )
+    dbgPrint "#{self.name}: gen_post_code_body\n"
+
+    if @@b_gen_post_code_called == false then
+      @@b_gen_post_code_called = true
+      MrubyBridgeCellPlugin.gen_post_code_body file
+    end
+
+#    ãã®æ®µéã§çæããã¨ãåããã¹ãã³ã¼ãã§åºåããã mruby ã®åæåã³ã¼ãã«åæ ãããªã
+    
+#    # MrubyBridgeCelltypePlugin ã®çæãã generate æã¯ã
+#    fn2 = "#{$gen}/tmp_MrubyBridgeCelltypePlugin_post.cdl"
+#    f2 = File.open( fn2, "w" )
+#    # è¤æ°ã®ãã©ã°ã¤ã³ã® post_code ãä¸ã¤ã®ãã¡ã¤ã«ã«å«ã¾ãããããä»¥ä¸ã®ãããªè¦åºããã¤ãããã¨
+#    dbgPrint "MrubyBridgeCelltypePlugin: gen_post_code\n"
+#    f2.print "/* '#{self.name}' post code */\n"
+#    @@plugin_list.each{ |plugin|
+#      plugin.get_celltype.get_cell_list.each{ |cell|
+#        # mikan option, region
+#        f2.print <<EOT
+#generate( MrubyBridgeCellPlugin, #{cell.get_namespace_path}, "" );
+#EOT
+#      }
+#    }
+#    f2.close
+#    p Import
+#    Import.new "#{fn2}"
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° 
+
+  #=== ãã©ã°ã¤ã³å¼æ° ignoreUnsigned
+  def set_ignoreUnsigned rhs
+    if rhs == "true" || rhs == nil then
+      @b_ignoreUnsigned = true
+    end
+  end
+
+  def set_include_inner_cell rhs
+    if rhs == "true" || rhs == nil then
+      @include_inner_cell = true
+    end
+  end
+
+  def set_exclude_cell rhs
+    cells = rhs.split ','
+    cells.each{ |rhs_cell|
+      rhs_cell.gsub!( /\s/, "" )
+      @exclude_cells << rhs_cell.to_sym
+    }
+  end
+  def set_exclude_port rhs
+    ports = rhs.split ','
+    ct = @cell.get_celltype
+    return if ct == nil    # error case
+    ports.each{ |rhs_port|
+      obj = ct.find( rhs_port.to_sym )
+      if( ( ! obj.instance_of? Port ) || obj.get_port_type != :ENTRY ) then
+        cdl_error( "MRB9999 exclude_port '$1' not found or not entry in celltype '$2'", rhs_port, ct.get_name )
+      else
+        # print "MRBBridgeCellPlugin: exclude #{rhs_port}\n"
+        @exclude_port << rhs_port
+      end
+    }
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° exclude_port_func
+  def set_exclude_port_func rhs
+    port_funcs = rhs.split ','
+    ct = @celltype
+    return if ct == nil    # error case
+    port_funcs.each{ |rhs_port_func|
+      port_func = rhs_port_func.split( '.' )
+      if port_func.length != 2 then
+        cdl_error( "MRB9999 exclude_port_func: '$1' not in 'port.func' form", rhs_port_func )
+      end
+      obj = ct.find( port_func[0].to_sym )
+      if( ( ! obj.instance_of? Port ) || obj.get_port_type != :ENTRY ) then
+        cdl_error( "MRB9999 exclude_port_func: port '$1' not found in celltype '$2'", rhs_port_func, ct.get_name )
+      else
+        signature = obj.get_signature
+        next if signature == nil     # error case
+        if signature.get_function_head port_func[1].to_sym
+          # print "MRBBridgeCellPlugin: #{port_func[0]}.#{port_func[1]} exclude\n"
+          if @exclude_port_func[ port_func[0] ] then
+            @exclude_port_func[ port_func[0] ] <<  port_func[1]
+          else
+            @exclude_port_func[ port_func[0] ] = [ port_func[1] ]
+          end
+        else
+          cdl_error( "MRB9999 include_port_func: func '$1' not found in port '$2' celltype $3",
+                     port_func[1], port_func[0], ct.get_name )
+        end
+      end
+    }
+  end
+
+  #=== ãã©ã°ã¤ã³å¼æ° auto_exclude
+  def set_auto_exclude rhs
+    # print "MrubyBridgeCellPlugin: auto_exclude=#{rhs}\n"
+    if rhs == "false" then
+      @b_auto_exclude = false
+    elsif rhs == "true" then
+      @b_auto_exclude = true     # auto_exclude = true by default 
+    else
+      cdl_warning( "MRB9999 auto_exclude: unknown rhs value ignored. specify true or false" )
+    end
+  end
+end
+
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/version.rb
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/version.rb	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tecsgen/tecslib/version.rb	(revision 374)
@@ -1,2 +1,2 @@
 $package = "tecsgen"
-$version = "1.5.0"
+$version = "1.6.4"
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/Makefile.tinet
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/Makefile.tinet	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/Makefile.tinet	(revision 374)
@@ -42,4 +42,4 @@
 INCLUDES	:= $(INCLUDES) -I$(TINET_ROOT)/netdev/$(NET_DEV)
 TINET_DIRS	:= $(TINET_DIRS):$(TINET_ROOT)/netdev/$(NET_DEV)
-TINET_COBJS	:= $(TINET_COBJS) nap_main.o panu_main.o if_btusb.o
+TINET_COBJS	:= $(TINET_COBJS) bt_main.o if_btusb.o
 TINET_KERNEL_CFG := $(TINET_KERNEL_CFG) $(TINET_ROOT)/netdev/$(NET_DEV)/if_btusb.cfg
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/bt_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/bt_main.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/bt_main.c	(revision 374)
@@ -0,0 +1,689 @@
+/*
+ * Copyright (C) 2014 BlueKitchen GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ * 4. Any redistribution, use, or modification is done solely for
+ *    personal benefit and not for any commercial purpose or for
+ *    monetary gain.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
+ * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Please inquire about commercial licensing options at
+ * contact@bluekitchen-gmbh.com
+ *
+ */
+
+#include "btstack-config.h"
+
+#include <stdint.h>
+
+#include <btstack/hci_cmds.h>
+#include <btstack/run_loop.h>
+#include <btstack/sdp_util.h>
+
+#include <kernel.h>
+#include "kernel_cfg.h"
+#include "target_syssvc.h"
+
+#include "debug.h"
+#include "hci.h"
+#include "btstack_memory.h"
+#include "hci_dump.h"
+#include "l2cap.h"
+#include "sdp_parser.h"
+#include "sdp_client.h"
+#include "sdp_query_util.h"
+#include "sdp.h"
+#include "pan.h"
+#include "bt_main.h"
+#include "usb_hbth.h"
+
+//#define PACKET_DUMP
+
+// エラー返却用定数(-1:0xffff固定)
+#define FAILED_RFCOMM_ID_NOT_SET	0xffff
+
+#define RFCOMM_SERVER_CHANNEL 1
+static uint16_t  rfcomm_channel_id = FAILED_RFCOMM_ID_NOT_SET;
+
+static int record_id = -1;
+static uint16_t bnep_l2cap_psm = 0;
+static uint32_t bnep_remote_uuid = 0;
+static uint16_t bnep_version = 0;
+static uint16_t bnep_cid = 0;
+static bool_t bnep_do_connect = false;
+
+static uint16_t sdp_bnep_l2cap_psm = 0;
+static uint16_t sdp_bnep_version = 0;
+static uint32_t sdp_bnep_remote_uuid = 0;
+
+uint8_t   attribute_value[1000];
+const unsigned int attribute_value_buffer_size = sizeof(attribute_value);
+
+extern bd_addr_t remote_addr;
+
+uint8_t   spp_service_buffer[120];
+uint8_t   bnep_service_buffer[256];
+
+char bt_localname[] = TARGET_NAME"0000";
+
+volatile int bt_bnep_mode = 0;
+
+enum bt_state_t {
+	BT_STATE_DORMANT,
+	BT_STATE_POWER_ON,
+	BT_STATE_BNEP_QUERY,
+	BT_STATE_BNEP_WAIT,
+	BT_STATE_BNEP_QUERY_WAIT,
+	BT_STATE_CONNECTING,
+	BT_STATE_CONNECTED,
+};
+
+enum bt_state_t bt_state = BT_STATE_DORMANT;
+int bt_timer;
+
+// outgoing network packet
+const uint8_t * network_buffer;
+uint16_t network_buffer_len;
+uint16_t network_buffer_cid;
+
+/*************** PANU client routines *********************/
+
+char * get_string_from_data_element(uint8_t * element) {
+	de_size_t de_size = de_get_size_type(element);
+	int pos = de_get_header_size(element);
+	int len = 0;
+	switch (de_size) {
+	case DE_SIZE_VAR_8:
+		len = element[1];
+		break;
+	case DE_SIZE_VAR_16:
+		len = big_endian_read_16(element, 1);
+		break;
+	default:
+		break;
+	}
+	char * str = (char*)malloc(len + 1);
+	memcpy(str, &element[pos], len);
+	str[len] = '\0';
+	return str;
+}
+
+/* @section SDP parser callback
+*
+* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
+* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
+*/
+static void handle_sdp_client_record_complete(void)
+{
+	log_info("SDP BNEP Record complete");
+
+	// accept first entry or if we foudn a NAP and only have a PANU yet
+	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BLUETOOTH_SERVICE_CLASS_NAP && bnep_remote_uuid == BLUETOOTH_SERVICE_CLASS_PANU)) {
+		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
+		bnep_remote_uuid = sdp_bnep_remote_uuid;
+		bnep_version = sdp_bnep_version;
+	}
+}
+
+/* SDP parser callback */
+static void handle_sdp_client_query_result(sdp_query_event_t *event)
+{
+	sdp_query_attribute_value_event_t *value_event;
+	sdp_query_complete_event_t        *complete_event;
+	des_iterator_t des_list_it;
+	des_iterator_t prot_it;
+	char *str;
+
+	switch (event->type) {
+	case SDP_EVENT_QUERY_ATTRIBUTE_VALUE:
+		value_event = (sdp_query_attribute_value_event_t*)event;
+
+		// Handle new SDP record
+		if (value_event->record_id != record_id) {
+			handle_sdp_client_record_complete();
+			// next record started
+			record_id = value_event->record_id;
+			log_info("SDP Record: Nr: %d", record_id);
+		}
+
+		if (value_event->attribute_length <= attribute_value_buffer_size) {
+			attribute_value[value_event->data_offset] = value_event->data;
+
+			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
+				//printf("SDP Attribute Data:");
+				//printf_hexdump(attribute_value, value_event->attribute_length);
+
+				switch (value_event->attribute_id) {
+				case BLUETOOTH_ATTRIBUTE_SERVICE_CLASS_ID_LIST:
+					if (de_get_element_type(attribute_value) != DE_DES) break;
+					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
+						uint8_t * element = des_iterator_get_element(&des_list_it);
+						if (de_get_element_type(element) != DE_UUID) continue;
+						uint32_t uuid = de_get_uuid32(element);
+						switch (uuid) {
+						case BLUETOOTH_SERVICE_CLASS_PANU:
+						case BLUETOOTH_SERVICE_CLASS_NAP:
+						case BLUETOOTH_SERVICE_CLASS_GN:
+							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
+							sdp_bnep_remote_uuid = uuid;
+							break;
+						default:
+							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
+							break;
+						}
+					}
+					break;
+					// 0x0100 "Service Name"
+				case 0x0100:
+					// 0x0101 "Service Description"
+				case 0x0101:
+					str = get_string_from_data_element(attribute_value);
+					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
+					free(str);
+					break;
+				case BLUETOOTH_ATTRIBUTE_PROTOCOL_DESCRIPTOR_LIST: {
+					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
+
+					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
+						uint8_t       *des_element;
+						uint8_t       *element;
+						uint32_t       uuid;
+
+						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
+
+						des_element = des_iterator_get_element(&des_list_it);
+						des_iterator_init(&prot_it, des_element);
+						element = des_iterator_get_element(&prot_it);
+
+						if (de_get_element_type(element) != DE_UUID) continue;
+
+						uuid = de_get_uuid32(element);
+						switch (uuid) {
+						case BLUETOOTH_PROTOCOL_L2CAP:
+							if (!des_iterator_has_more(&prot_it)) continue;
+							des_iterator_next(&prot_it);
+							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
+							break;
+						case BLUETOOTH_PROTOCOL_BNEP:
+							if (!des_iterator_has_more(&prot_it)) continue;
+							des_iterator_next(&prot_it);
+							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
+							break;
+						default:
+							log_info("uuid 0x%04x", uuid);
+							break;
+						}
+					}
+					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
+					break;
+				}
+				default:
+					break;
+				}
+			}
+		}
+		else {
+			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
+		}
+		break;
+
+	case SDP_EVENT_QUERY_COMPLETE:
+		handle_sdp_client_record_complete();
+		complete_event = (sdp_query_complete_event_t*)event;
+		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
+		if (bnep_l2cap_psm) {
+			bnep_do_connect = complete_event->status == 0;
+		}
+		else {
+			bnep_do_connect = false;
+			log_error("No BNEP service found");
+		}
+		if (!bnep_do_connect) {
+			// 20秒後 BNEP Query 開始
+			bt_state = BT_STATE_BNEP_QUERY_WAIT;
+			bt_timer = 20 * 1000;
+		}
+		break;
+	}
+}
+
+static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
+{
+	uint8_t   event;
+	bd_addr_t event_addr;
+	uint8_t   rfcomm_channel_nr;
+	uint16_t  uuid_source;
+	uint16_t  uuid_dest;
+	uint16_t  mtu;
+
+	switch (packet_type) {
+	case HCI_EVENT_PACKET:
+		event = packet[0];
+		switch (event) {
+		case BTSTACK_EVENT_STATE:
+			/* BT Stack activated, get started */
+			if (packet[2] == HCI_STATE_WORKING) {
+				hci_send_cmd(&hci_write_local_name, bt_localname);
+				if (bt_bnep_mode == 0) {
+					// 即時 BNEP Query 開始
+					bt_state = BT_STATE_BNEP_QUERY_WAIT;
+					bt_timer = 0;
+				}
+				else {
+					bt_state = BT_STATE_BNEP_WAIT;
+					bt_timer = -1;
+				}
+			}
+			break;
+
+		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
+			if ((packet[2] == 0) && bnep_do_connect) {
+				bnep_do_connect = false;
+				/* Create BNEP connection */
+				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
+			}
+			break;
+
+		case HCI_EVENT_COMMAND_COMPLETE:
+			if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_read_bd_addr)) {
+				reverse_bd_addr(&packet[6], event_addr);
+				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
+
+				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
+				gap_set_local_name(bt_localname);
+				break;
+			}
+			if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_write_local_name)) {
+				gap_discoverable_control(1);
+				break;
+			}
+			break;
+
+		case HCI_EVENT_LINK_KEY_REQUEST:
+			// deny link key request
+			log_info("Link key request");
+			reverse_bd_addr(&packet[2], event_addr);
+			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
+			break;
+
+		case HCI_EVENT_PIN_CODE_REQUEST:
+			// inform about pin code request
+			log_info("Pin code request - using '0000'");
+			reverse_bd_addr(&packet[2], event_addr);
+			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
+			break;
+
+		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
+			// inform about user confirmation request
+			log_info("HCI User Confirmation Request with numeric value '%06u'", little_endian_read_32(packet, 8));
+			log_info("HCI User Confirmation Auto accept");
+			break;
+
+		case RFCOMM_EVENT_INCOMING_CONNECTION:
+			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
+			reverse_bd_addr(&packet[2], event_addr);
+			rfcomm_channel_nr = packet[8];
+			rfcomm_channel_id = little_endian_read_16(packet, 9);
+			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
+			rfcomm_accept_connection_internal(rfcomm_channel_id);
+			break;
+
+		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
+			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
+			if (packet[2]) {
+				log_info("RFCOMM channel open failed, status %u", packet[2]);
+			}
+			else {
+				rfcomm_channel_id = little_endian_read_16(packet, 12);
+				mtu = little_endian_read_16(packet, 14);
+				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
+			}
+			break;
+
+		case RFCOMM_EVENT_CHANNEL_CLOSED:
+			log_info("RFCOMM channel closed");
+			rfcomm_channel_id = 0;
+			break;
+
+		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
+			if (packet[2]) {
+				log_info("BNEP channel open failed, status %02x", packet[2]);
+
+				// 30秒後 BNEP Query 開始
+				bt_state = BT_STATE_BNEP_QUERY_WAIT;
+				bt_timer = 30 * 1000;
+			}
+			else {
+				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
+				bnep_cid = little_endian_read_16(packet, 3);
+				uuid_source = little_endian_read_16(packet, 5);
+				uuid_dest = little_endian_read_16(packet, 7);
+				mtu = little_endian_read_16(packet, 9);
+				//reverse_bd_addr(&packet[11], remote_addr); 
+				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
+				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
+				/* Setup network interface */
+				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), (uint8_t *)remote_addr);
+				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
+
+				bt_state = BT_STATE_CONNECTED;
+				bt_timer = -1;
+			}
+			break;
+
+		case BNEP_EVENT_CHANNEL_TIMEOUT:
+			log_info("BNEP channel timeout! Channel will be closed");
+			break;
+
+		case BNEP_EVENT_CHANNEL_CLOSED:
+			bnep_cid = little_endian_read_16(packet, 2);
+			bt_channel_closed(bnep_cid);
+
+			// 30秒後 BNEP Query 開始
+			bt_state = BT_STATE_BNEP_QUERY_WAIT;
+			bt_timer = 30 * 1000;
+			break;
+
+		case BNEP_EVENT_READY_TO_SEND:
+			bnep_cid = little_endian_read_16(packet, 2);
+			bt_send_packet(bnep_cid);
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case RFCOMM_DATA_PACKET:
+		// loopback
+		if (rfcomm_channel_id) {
+			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
+			if (err) {
+				log_error("rfcomm_send_internal -> error %d", err);
+			}
+		}
+		break;
+
+	case BNEP_DATA_PACKET:
+		bt_recv_packet(channel, packet, size);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*
+ * @section Network packet handler
+ *
+ * @text A pointer to the network packet is stored and a BNEP_EVENT_CAN_SEND_NOW requested
+ */
+
+ /* LISTING_START(networkPacketHandler): Network Packet Handler */
+static void network_send_packet_callback(uint16_t bnep_cid, const uint8_t * packet, uint16_t size) {
+	if ((bnep_cid == 0) || (network_buffer_len > 0)) {
+#ifdef PACKET_DUMP
+		int len = size;
+		printf("DROP %04x %d ", bnep_cid, size);
+		if (len > 128)
+			len = 128;
+		printf_hexdump(packet, len);
+#endif
+		if (network_buffer_len > 0) {
+			network_buffer_len = 0;
+			btstack_network_packet_sent(network_buffer_cid);
+		}
+	}
+
+	network_buffer_cid = bnep_cid;
+	network_buffer = packet;
+	network_buffer_len = size;
+}
+
+void bt_init(void)
+{
+	const hci_transport_t *transport;
+	bt_control_t       * control;
+	hci_uart_config_t  * config;
+	remote_device_db_t * remote_db;
+	service_record_item_t *spp_service_record_item;
+	service_record_item_t *bnep_service_record_item;
+
+	btstack_network_init(&network_send_packet_callback);
+
+	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
+
+	// start with BTstack init - especially configure HCI Transport
+	btstack_memory_init();
+	run_loop_init(RUN_LOOP_EMBEDDED);
+
+	/* Initialize HCI */
+	transport = hci_transport_usb_instance();
+	control = NULL;
+	config = NULL;
+	remote_db = (remote_device_db_t *)&remote_device_db_memory;
+	hci_init(transport, config, control, remote_db);
+	hci_set_class_of_device(0x820300/*0x820810*/);
+
+	/* Initialize L2CAP */
+	l2cap_init();
+	l2cap_register_packet_handler(packet_handler);
+
+	/* Initialise SDP, create record for SPP and register with SDP */
+	sdp_init();
+
+	/* Initialize RFCOMM */
+	rfcomm_init();
+	rfcomm_register_packet_handler(packet_handler);
+	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
+
+	/* Initialise BNEP */
+	bnep_init();
+	bnep_register_packet_handler(packet_handler);
+	if (bt_bnep_mode == 0) {
+		bnep_register_service(NULL, BLUETOOTH_SERVICE_CLASS_PANU, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
+	}
+	else {
+		bnep_register_service(NULL, BLUETOOTH_SERVICE_CLASS_NAP, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
+	}
+
+	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
+	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
+
+	// サービス定義
+	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
+	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
+
+	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
+	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
+	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
+	sdp_register_service_internal(NULL, spp_service_record_item);
+
+	if (bt_bnep_mode == 0) {
+		pan_create_panu_service((uint8_t*)&bnep_service_record_item->service_record, "RX PANU", "RX PANU", BNEP_SECURITY_NONE);
+		de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
+		log_info("PANU SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
+	}
+	else {
+		pan_create_nap_service((uint8_t*)&bnep_service_record_item->service_record, "RX NAP", "RX NAP", BNEP_SECURITY_NONE,
+			PAN_NET_ACCESS_TYPE_100MB_ETHERNET, 0x0001312D0/*10Mb/sec*/, NULL, NULL);
+		de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
+		log_info("NAP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
+	}
+	sdp_register_service_internal(NULL, bnep_service_record_item);
+
+	// Secure Simple Pairing configuration -> just works
+	hci_ssp_set_enable(1);
+	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
+	hci_ssp_set_auto_accept(1);
+
+	/* Turn on the device */
+	hci_power_control(HCI_POWER_ON);
+
+	/* Initialise SDP */
+	sdp_parser_init();
+	sdp_parser_register_callback(handle_sdp_client_query_result);
+
+	bt_state = BT_STATE_POWER_ON;
+	bt_timer = -1;
+}
+
+void bt_process(void)
+{
+	if (bt_state != BT_STATE_DORMANT) {
+		run_loop_execute();
+		bt_send_packet(0xffff);
+	}
+
+	if (bt_timer != 0)
+		return;
+
+	switch (bt_state) {
+	case BT_STATE_BNEP_QUERY_WAIT:
+		/* Send a general query for BNEP Protocol ID */
+		log_info("Start SDP BNEP query.");
+		sdp_general_query_for_uuid(remote_addr, BLUETOOTH_PROTOCOL_BNEP);
+
+		bt_state = BT_STATE_BNEP_QUERY;
+		bt_timer = -1;
+		break;
+	default:
+		bt_timer = -1;
+		break;
+	}
+}
+
+int bt_can_send_packet(void)
+{
+	return network_buffer_len == 0;
+}
+
+void bt_send_packet(uint16_t bnep_cid)
+{
+	if (network_buffer_len > 0) {
+		if (network_buffer_cid == 0) {
+			network_buffer_len = 0;
+			btstack_network_packet_sent(network_buffer_cid);
+			return;
+		}
+		/* Check for parked network packets and send it out now */
+		if (bnep_can_send_packet_now(network_buffer_cid)) {
+			uint16_t len = network_buffer_len;
+#ifdef PACKET_DUMP
+			printf("ETH %u => ", len);
+			if (len > 128)
+				len = 128;
+			printf_hexdump(network_buffer, len);
+#endif
+			// この関数はbnep_sendから再帰呼び出しされるので、
+			// bnep_sendを呼び出すより前に送信パケットなし状態にします。
+			network_buffer_len = 0;
+			bnep_send(network_buffer_cid, (uint8_t*)network_buffer, len);
+			btstack_network_packet_sent(network_buffer_cid);
+		}
+	}
+}
+
+void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size)
+{
+#ifdef PACKET_DUMP
+	int len = size;
+	printf("ETH %d <= ", size);
+	if (len > 128)
+		len = 128;
+	printf_hexdump(packet, len);
+#endif
+	btstack_network_process_packet(bnep_cid, packet, size);
+}
+
+void bt_channel_closed(uint16_t bnep_cid)
+{
+	log_info("BNEP channel closed");
+	btstack_network_down(bnep_cid);
+	if ((network_buffer_len > 0) && (network_buffer_cid == bnep_cid)) {
+		network_buffer_len = 0;
+		btstack_network_packet_sent(network_buffer_cid);
+	}
+}
+
+void bt_terminate(void)
+{
+	hci_close();
+
+	bt_state = BT_STATE_DORMANT;
+	bt_timer = -1;
+}
+
+void bt_task_on_start(struct task_if_t *task, ID tskid)
+{
+}
+
+void bt_task_on_end(struct task_if_t *task)
+{
+}
+
+int bt_task_get_timer(struct task_if_t *task)
+{
+	return bt_timer;
+}
+
+void bt_task_progress(struct task_if_t *task, int elapse)
+{
+	if (bt_timer == -1)
+		return;
+
+	bt_timer -= elapse;
+	if (bt_timer < 0)
+		bt_timer = 0;
+}
+
+void bt_task_process(struct task_if_t *task, enum task_event_t event)
+{
+	extern void hal_tick_handler();
+
+	switch (event & ~TASK_EVENT_TICK) {
+	case TASK_EVENT_START:
+		bt_init();
+		break;
+	case TASK_EVENT_TERMINATE:
+		bt_terminate();
+		break;
+	case TASK_EVENT_WAKEUP:
+	case TASK_EVENT_TIMEOUT:
+		if (event & TASK_EVENT_TICK)
+			hal_tick_handler();
+		bt_process();
+		break;
+	}
+}
+
+struct task_if_t bt_task = {
+	bt_task_on_start,
+	bt_task_on_end,
+	bt_task_get_timer,
+	bt_task_progress,
+	bt_task_process,
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/bt_main.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/bt_main.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/bt_main.h	(revision 374)
@@ -0,0 +1,34 @@
+/*
+ * bt_main.h
+ *
+ */
+#ifndef __BT_MAIN_
+#define __BT_MAIN_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+// エラー返却用定数(-1:0xffff固定)
+#define FAILED_RFCOMM_ID_NOT_SET	0xffff
+
+#define RFCOMM_SERVER_CHANNEL 1
+
+void bt_init(void);
+int bt_can_send_packet(void);
+void bt_send_packet(uint16_t bnep_cid);
+void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
+void bt_channel_closed(uint16_t bnep_cid);
+void bt_terminate(void);
+
+void btstack_network_init(void (*send_packet_callback)(uint16_t bnep_cid, const uint8_t * packet, uint16_t size));
+void btstack_network_up(uint16_t bnep_cid, bd_addr_t local_addr, bd_addr_t remote_addr);
+const char * btstack_network_get_name(uint16_t bnep_cid);
+int btstack_network_down(uint16_t bnep_cid);
+void btstack_network_process_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
+void btstack_network_packet_sent(uint16_t bnep_cid);
+
+#if defined __cplusplus
+}
+#endif
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/if_btusb.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/if_btusb.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/if_btusb.c	(revision 374)
@@ -79,5 +79,5 @@
 #include "kernel/kernel_impl.h"
 #include "btstack/utils.h"
-#include "panu_main.h"
+#include "bt_main.h"
 #include "usb_hbth.h"
 //#include "hal_cpu.h"
@@ -691,19 +691,4 @@
 }
 
-static int usb_acl_out_active = 0;
-static int usb_command_active = 0;
-
-static int usb_can_send_packet_now(uint8_t packet_type)
-{
-	switch (packet_type) {
-	case HCI_COMMAND_DATA_PACKET:
-		return !usb_command_active;
-	case HCI_ACL_DATA_PACKET:
-		return !usb_acl_out_active;
-	default:
-		return 0;
-	}
-}
-
 // single instance
 static const hci_transport_t hci_transport_usb =
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/nap_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/nap_main.c	(revision 373)
+++ 	(revision )
@@ -1,447 +1,0 @@
-/*
- * Copyright (C) 2014 BlueKitchen GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- * 4. Any redistribution, use, or modification is done solely for
- *    personal benefit and not for any commercial purpose or for
- *    monetary gain.
- *
- * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
- * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Please inquire about commercial licensing options at
- * contact@bluekitchen-gmbh.com
- *
- */
-
-#include "btstack-config.h"
-
-#include <stdint.h>
-
-#include <btstack/hci_cmds.h>
-#include <btstack/run_loop.h>
-#include <btstack/sdp_util.h>
-
-#include <kernel.h>
-#include "kernel_cfg.h"
-#include "target_syssvc.h"
-
-#include "debug.h"
-#include "hci.h"
-#include "btstack_memory.h"
-#include "hci_dump.h"
-#include "l2cap.h"
-#include "sdp_parser.h"
-#include "sdp_client.h"
-#include "sdp_query_util.h"
-#include "sdp.h"
-#include "pan.h"
-#include "panu_main.h"
-
-extern uint16_t  rfcomm_channel_id;
-
-static int record_id = -1;
-static uint16_t bnep_l2cap_psm = 0;
-static uint32_t bnep_remote_uuid = 0;
-static uint16_t bnep_version = 0;
-static uint16_t bnep_cid = 0;
-static bool_t bnep_do_connect = false;
-
-static uint16_t sdp_bnep_l2cap_psm = 0;
-static uint16_t sdp_bnep_version = 0;
-static uint32_t sdp_bnep_remote_uuid = 0;
-
-extern uint8_t   attribute_value[];
-extern const unsigned int attribute_value_buffer_size;
-
-static bd_addr_t remote_addr;
-
-extern uint8_t   spp_service_buffer[120];
-extern uint8_t   bnep_service_buffer[256];
-
-extern char bt_localname[sizeof(TARGET_NAME"0000")];
-
-/*************** NAP server routines *********************/
-
-char * get_string_from_data_element(uint8_t * element);
-
-/* @section SDP parser callback
-*
-* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
-* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
-*/
-static void handle_sdp_client_record_complete(void)
-{
-	log_info("SDP BNEP Record complete");
-
-	// accept first entry or if we foudn a PANU and only have a NAP yet
-	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BNEP_UUID_PANU && bnep_remote_uuid == BNEP_UUID_NAP)) {
-		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
-		bnep_remote_uuid = sdp_bnep_remote_uuid;
-		bnep_version = sdp_bnep_version;
-	}
-}
-
-/* SDP parser callback */
-static void handle_sdp_client_query_result(sdp_query_event_t *event)
-{
-	sdp_query_attribute_value_event_t *value_event;
-	sdp_query_complete_event_t        *complete_event;
-	des_iterator_t des_list_it;
-	des_iterator_t prot_it;
-	char *str;
-
-	switch (event->type) {
-	case SDP_QUERY_ATTRIBUTE_VALUE:
-		value_event = (sdp_query_attribute_value_event_t*)event;
-
-		// Handle new SDP record
-		if (value_event->record_id != record_id) {
-			handle_sdp_client_record_complete();
-			// next record started
-			record_id = value_event->record_id;
-			log_info("SDP Record: Nr: %d", record_id);
-		}
-
-		if (value_event->attribute_length <= attribute_value_buffer_size) {
-			attribute_value[value_event->data_offset] = value_event->data;
-
-			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
-				//printf("SDP Attribute Data:");
-				//printf_hexdump(attribute_value, value_event->attribute_length);
-
-				switch (value_event->attribute_id) {
-				case SDP_ServiceClassIDList:
-					if (de_get_element_type(attribute_value) != DE_DES) break;
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t * element = des_iterator_get_element(&des_list_it);
-						if (de_get_element_type(element) != DE_UUID) continue;
-						uint32_t uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case BNEP_UUID_PANU:
-						case BNEP_UUID_NAP:
-						case BNEP_UUID_GN:
-							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
-							sdp_bnep_remote_uuid = uuid;
-							break;
-						default:
-							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
-							break;
-						}
-					}
-					break;
-					// 0x0100 "Service Name"
-				case 0x0100:
-					// 0x0101 "Service Description"
-				case 0x0101:
-					str = get_string_from_data_element(attribute_value);
-					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
-					free(str);
-					break;
-				case SDP_ProtocolDescriptorList: {
-					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
-
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t       *des_element;
-						uint8_t       *element;
-						uint32_t       uuid;
-
-						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
-
-						des_element = des_iterator_get_element(&des_list_it);
-						des_iterator_init(&prot_it, des_element);
-						element = des_iterator_get_element(&prot_it);
-
-						if (de_get_element_type(element) != DE_UUID) continue;
-
-						uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case SDP_L2CAPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
-							break;
-						case SDP_BNEPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
-							break;
-						default:
-							log_info("uuid 0x%04x", uuid);
-							break;
-						}
-					}
-					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
-					break;
-				}
-				default:
-					break;
-				}
-			}
-		}
-		else {
-			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
-		}
-		break;
-
-	case SDP_QUERY_COMPLETE:
-		handle_sdp_client_record_complete();
-		complete_event = (sdp_query_complete_event_t*)event;
-		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
-		if (bnep_l2cap_psm) {
-			bnep_do_connect = complete_event->status == 0;
-		}
-		else {
-			log_error("No BNEP service found");
-		}
-		break;
-	}
-}
-
-static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
-{
-	uint8_t   event;
-	bd_addr_t event_addr;
-	uint8_t   rfcomm_channel_nr;
-	uint16_t  uuid_source;
-	uint16_t  uuid_dest;
-	uint16_t  mtu;
-
-	switch (packet_type) {
-	case HCI_EVENT_PACKET:
-		event = packet[0];
-		switch (event) {
-		case BTSTACK_EVENT_STATE:
-			/* BT Stack activated, get started */
-			if (packet[2] == HCI_STATE_WORKING) {
-				hci_send_cmd(&hci_write_local_name, bt_localname);
-			}
-			break;
-
-		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
-			if ((packet[2] == 0) && bnep_do_connect) {
-				bnep_do_connect = false;
-				/* Create BNEP connection */
-				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
-			}
-			break;
-
-		case HCI_EVENT_COMMAND_COMPLETE:
-			if (COMMAND_COMPLETE_EVENT(packet, hci_read_bd_addr)) {
-				bt_flip_addr(event_addr, &packet[6]);
-				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
-
-				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
-				gap_set_local_name(bt_localname);
-				break;
-			}
-			if (COMMAND_COMPLETE_EVENT(packet, hci_write_local_name)) {
-				hci_discoverable_control(1);
-				break;
-			}
-			break;
-
-		case HCI_EVENT_LINK_KEY_REQUEST:
-			// deny link key request
-			log_info("Link key request");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
-			break;
-
-		case HCI_EVENT_PIN_CODE_REQUEST:
-			// inform about pin code request
-			log_info("Pin code request - using '0000'");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
-			break;
-
-		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
-			// inform about user confirmation request
-			log_info("HCI User Confirmation Request with numeric value '%06u'", READ_BT_32(packet, 8));
-			log_info("HCI User Confirmation Auto accept");
-			break;
-
-		case RFCOMM_EVENT_INCOMING_CONNECTION:
-			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
-			bt_flip_addr(event_addr, &packet[2]);
-			rfcomm_channel_nr = packet[8];
-			rfcomm_channel_id = READ_BT_16(packet, 9);
-			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
-			rfcomm_accept_connection_internal(rfcomm_channel_id);
-			break;
-
-		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
-			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
-			if (packet[2]) {
-				log_info("RFCOMM channel open failed, status %u", packet[2]);
-			}
-			else {
-				rfcomm_channel_id = READ_BT_16(packet, 12);
-				mtu = READ_BT_16(packet, 14);
-				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
-			}
-			break;
-
-		case RFCOMM_EVENT_CHANNEL_CLOSED:
-			log_info("RFCOMM channel closed");
-			rfcomm_channel_id = 0;
-			break;
-
-		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
-			if (packet[2]) {
-				log_info("BNEP channel open failed, status %02x", packet[2]);
-			}
-			else {
-				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
-				bnep_cid = READ_BT_16(packet, 3);
-				uuid_source = READ_BT_16(packet, 5);
-				uuid_dest = READ_BT_16(packet, 7);
-				mtu = READ_BT_16(packet, 9);
-				//bt_flip_addr(remote_addr, &packet[11]); 
-				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
-				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
-				/* Setup network interface */
-				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), remote_addr);
-				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
-			}
-			break;
-
-		case BNEP_EVENT_CHANNEL_TIMEOUT:
-			log_info("BNEP channel timeout! Channel will be closed");
-			break;
-
-		case BNEP_EVENT_CHANNEL_CLOSED:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_channel_closed(bnep_cid);
-			break;
-
-		case BNEP_EVENT_READY_TO_SEND:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_send_packet(bnep_cid);
-			break;
-
-		default:
-			break;
-		}
-		break;
-
-	case RFCOMM_DATA_PACKET:
-		// loopback
-		if (rfcomm_channel_id) {
-			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
-			if (err) {
-				log_error("rfcomm_send_internal -> error %d", err);
-			}
-		}
-		break;
-
-	case BNEP_DATA_PACKET:
-		bt_recv_packet(channel, packet, size);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void nap_init(void)
-{
-	const hci_transport_t *transport;
-	bt_control_t       * control;
-	hci_uart_config_t  * config;
-	remote_device_db_t * remote_db;
-	service_record_item_t *spp_service_record_item;
-	service_record_item_t *bnep_service_record_item;
-
-	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
-
-	log_info("bt初期化...");
-
-	// start with BTstack init - especially configure HCI Transport
-	btstack_memory_init();
-	run_loop_init(RUN_LOOP_EMBEDDED);
-
-	/* Initialize HCI */
-	log_info("HCI初期化...");
-	transport = hci_transport_usb_instance();
-	control = NULL;
-	config = NULL;
-	remote_db = (remote_device_db_t *)&remote_device_db_memory;
-	hci_init(transport, config, control, remote_db);
-	hci_set_class_of_device(0x820300/*0x820810*/);
-
-	/* Initialize L2CAP */
-	log_info("L2CAP初期化...");
-	l2cap_init();
-	l2cap_register_packet_handler(packet_handler);
-
-	/* Initialise SDP, create record for SPP and register with SDP */
-	log_info("SDP初期化...");
-	sdp_init();
-
-	/* Initialize RFCOMM */
-	log_info("RFCOMM初期化...");
-	rfcomm_init();
-	rfcomm_register_packet_handler(packet_handler);
-	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
-
-	/* Initialise BNEP */
-	log_info("BNEP初期化...");
-	bnep_init();
-	bnep_register_packet_handler(packet_handler);
-	bnep_register_service(NULL, BNEP_UUID_NAP, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
-
-	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
-	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
-
-	// サービス定義
-	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
-	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
-
-	log_info("SPPサービス登録...");
-	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
-	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
-	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, spp_service_record_item);
-
-	log_info("BNEPサービス登録...");
-	pan_create_nap_service((uint8_t*)&bnep_service_record_item->service_record, "RX NAP", "RX NAP", BNEP_SECURITY_NONE,
-		PAN_NET_ACCESS_TYPE_100MB_ETHERNET, 0x0001312D0/*10Mb/sec*/, NULL, NULL);
-	de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
-	log_info("NAP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, bnep_service_record_item);
-
-	// Secure Simple Pairing configuration -> just works
-	hci_ssp_set_enable(1);
-	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
-	hci_ssp_set_auto_accept(1);
-
-	/* Turn on the device */
-	log_info("HCI電源ON...");
-	hci_power_control(HCI_POWER_ON);
-
-	/* Initialise SDP */
-	sdp_parser_init();
-	sdp_parser_register_callback(handle_sdp_client_query_result);
-}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/panu_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/panu_main.c	(revision 373)
+++ 	(revision )
@@ -1,595 +1,0 @@
-/*
- * Copyright (C) 2014 BlueKitchen GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- * 4. Any redistribution, use, or modification is done solely for
- *    personal benefit and not for any commercial purpose or for
- *    monetary gain.
- *
- * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
- * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Please inquire about commercial licensing options at
- * contact@bluekitchen-gmbh.com
- *
- */
-
-#include "btstack-config.h"
-
-#include <stdint.h>
-
-#include <btstack/hci_cmds.h>
-#include <btstack/run_loop.h>
-#include <btstack/sdp_util.h>
-
-#include <kernel.h>
-#include "kernel_cfg.h"
-#include "target_syssvc.h"
-
-#include "debug.h"
-#include "hci.h"
-#include "btstack_memory.h"
-#include "hci_dump.h"
-#include "l2cap.h"
-#include "sdp_parser.h"
-#include "sdp_client.h"
-#include "sdp_query_util.h"
-#include "sdp.h"
-#include "pan.h"
-#include "panu_main.h"
-
-//#define PACKET_DUMP
-
-// エラー返却用定数(-1:0xffff固定)
-#define FAILED_RFCOMM_ID_NOT_SET	0xffff
-
-#define RFCOMM_SERVER_CHANNEL 1
-/*static*/ uint16_t  rfcomm_channel_id = FAILED_RFCOMM_ID_NOT_SET;
-
-static int record_id = -1;
-static uint16_t bnep_l2cap_psm = 0;
-static uint32_t bnep_remote_uuid = 0;
-static uint16_t bnep_version = 0;
-static uint16_t bnep_cid = 0;
-static bool_t bnep_do_connect = false;
-
-static uint16_t sdp_bnep_l2cap_psm = 0;
-static uint16_t sdp_bnep_version = 0;
-static uint32_t sdp_bnep_remote_uuid = 0;
-
-uint8_t   attribute_value[1000];
-const unsigned int attribute_value_buffer_size = sizeof(attribute_value);
-
-extern bd_addr_t remote_addr;
-
-uint8_t   spp_service_buffer[120];
-uint8_t   bnep_service_buffer[256];
-
-char bt_localname[] = TARGET_NAME"0000";
-
-volatile int bt_bnep_mode = 0;
-bool_t bt_enabled = false;
-
-// outgoing network packet
-const uint8_t * network_buffer;
-uint16_t network_buffer_len;
-uint16_t network_buffer_cid;
-
-/*************** PANU client routines *********************/
-
-char * get_string_from_data_element(uint8_t * element) {
-	de_size_t de_size = de_get_size_type(element);
-	int pos = de_get_header_size(element);
-	int len = 0;
-	switch (de_size) {
-	case DE_SIZE_VAR_8:
-		len = element[1];
-		break;
-	case DE_SIZE_VAR_16:
-		len = READ_NET_16(element, 1);
-		break;
-	default:
-		break;
-	}
-	char * str = (char*)malloc(len + 1);
-	memcpy(str, &element[pos], len);
-	str[len] = '\0';
-	return str;
-}
-
-/* @section SDP parser callback
-*
-* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
-* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
-*/
-static void handle_sdp_client_record_complete(void)
-{
-	log_info("SDP BNEP Record complete");
-
-	// accept first entry or if we foudn a NAP and only have a PANU yet
-	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BNEP_UUID_NAP && bnep_remote_uuid == BNEP_UUID_PANU)) {
-		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
-		bnep_remote_uuid = sdp_bnep_remote_uuid;
-		bnep_version = sdp_bnep_version;
-	}
-}
-
-/* SDP parser callback */
-static void handle_sdp_client_query_result(sdp_query_event_t *event)
-{
-	sdp_query_attribute_value_event_t *value_event;
-	sdp_query_complete_event_t        *complete_event;
-	des_iterator_t des_list_it;
-	des_iterator_t prot_it;
-	char *str;
-
-	switch (event->type) {
-	case SDP_QUERY_ATTRIBUTE_VALUE:
-		value_event = (sdp_query_attribute_value_event_t*)event;
-
-		// Handle new SDP record
-		if (value_event->record_id != record_id) {
-			handle_sdp_client_record_complete();
-			// next record started
-			record_id = value_event->record_id;
-			log_info("SDP Record: Nr: %d", record_id);
-		}
-
-		if (value_event->attribute_length <= attribute_value_buffer_size) {
-			attribute_value[value_event->data_offset] = value_event->data;
-
-			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
-				//printf("SDP Attribute Data:");
-				//printf_hexdump(attribute_value, value_event->attribute_length);
-
-				switch (value_event->attribute_id) {
-				case SDP_ServiceClassIDList:
-					if (de_get_element_type(attribute_value) != DE_DES) break;
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t * element = des_iterator_get_element(&des_list_it);
-						if (de_get_element_type(element) != DE_UUID) continue;
-						uint32_t uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case BNEP_UUID_PANU:
-						case BNEP_UUID_NAP:
-						case BNEP_UUID_GN:
-							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
-							sdp_bnep_remote_uuid = uuid;
-							break;
-						default:
-							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
-							break;
-						}
-					}
-					break;
-					// 0x0100 "Service Name"
-				case 0x0100:
-					// 0x0101 "Service Description"
-				case 0x0101:
-					str = get_string_from_data_element(attribute_value);
-					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
-					free(str);
-					break;
-				case SDP_ProtocolDescriptorList: {
-					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
-
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t       *des_element;
-						uint8_t       *element;
-						uint32_t       uuid;
-
-						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
-
-						des_element = des_iterator_get_element(&des_list_it);
-						des_iterator_init(&prot_it, des_element);
-						element = des_iterator_get_element(&prot_it);
-
-						if (de_get_element_type(element) != DE_UUID) continue;
-
-						uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case SDP_L2CAPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
-							break;
-						case SDP_BNEPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
-							break;
-						default:
-							log_info("uuid 0x%04x", uuid);
-							break;
-						}
-					}
-					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
-					break;
-				}
-				default:
-					break;
-				}
-			}
-		}
-		else {
-			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
-		}
-		break;
-
-	case SDP_QUERY_COMPLETE:
-		handle_sdp_client_record_complete();
-		complete_event = (sdp_query_complete_event_t*)event;
-		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
-		if (bnep_l2cap_psm) {
-			bnep_do_connect = complete_event->status == 0;
-		}
-		else {
-			log_error("No BNEP service found");
-		}
-		break;
-	}
-}
-
-static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
-{
-	uint8_t   event;
-	bd_addr_t event_addr;
-	uint8_t   rfcomm_channel_nr;
-	uint16_t  uuid_source;
-	uint16_t  uuid_dest;
-	uint16_t  mtu;
-
-	switch (packet_type) {
-	case HCI_EVENT_PACKET:
-		event = packet[0];
-		switch (event) {
-		case BTSTACK_EVENT_STATE:
-			/* BT Stack activated, get started */
-			if (packet[2] == HCI_STATE_WORKING) {
-				hci_send_cmd(&hci_write_local_name, bt_localname);
-				/* Send a general query for BNEP Protocol ID */
-				log_info("Start SDP BNEP query.");
-				sdp_general_query_for_uuid(remote_addr, SDP_BNEPProtocol);
-			}
-			break;
-
-		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
-			if ((packet[2] == 0) && bnep_do_connect) {
-				bnep_do_connect = false;
-				/* Create BNEP connection */
-				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
-			}
-			break;
-
-		case HCI_EVENT_COMMAND_COMPLETE:
-			if (COMMAND_COMPLETE_EVENT(packet, hci_read_bd_addr)) {
-				bt_flip_addr(event_addr, &packet[6]);
-				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
-
-				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
-				gap_set_local_name(bt_localname);
-				break;
-			}
-			if (COMMAND_COMPLETE_EVENT(packet, hci_write_local_name)) {
-				hci_discoverable_control(1);
-				break;
-			}
-			break;
-
-		case HCI_EVENT_LINK_KEY_REQUEST:
-			// deny link key request
-			log_info("Link key request");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
-			break;
-
-		case HCI_EVENT_PIN_CODE_REQUEST:
-			// inform about pin code request
-			log_info("Pin code request - using '0000'");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
-			break;
-
-		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
-			// inform about user confirmation request
-			log_info("HCI User Confirmation Request with numeric value '%06u'", READ_BT_32(packet, 8));
-			log_info("HCI User Confirmation Auto accept");
-			break;
-
-		case RFCOMM_EVENT_INCOMING_CONNECTION:
-			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
-			bt_flip_addr(event_addr, &packet[2]);
-			rfcomm_channel_nr = packet[8];
-			rfcomm_channel_id = READ_BT_16(packet, 9);
-			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
-			rfcomm_accept_connection_internal(rfcomm_channel_id);
-			break;
-
-		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
-			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
-			if (packet[2]) {
-				log_info("RFCOMM channel open failed, status %u", packet[2]);
-			}
-			else {
-				rfcomm_channel_id = READ_BT_16(packet, 12);
-				mtu = READ_BT_16(packet, 14);
-				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
-			}
-			break;
-
-		case RFCOMM_EVENT_CHANNEL_CLOSED:
-			log_info("RFCOMM channel closed");
-			rfcomm_channel_id = 0;
-			break;
-
-		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
-			if (packet[2]) {
-				log_info("BNEP channel open failed, status %02x", packet[2]);
-			}
-			else {
-				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
-				bnep_cid = READ_BT_16(packet, 3);
-				uuid_source = READ_BT_16(packet, 5);
-				uuid_dest = READ_BT_16(packet, 7);
-				mtu = READ_BT_16(packet, 9);
-				//bt_flip_addr(remote_addr, &packet[11]); 
-				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
-				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
-				/* Setup network interface */
-				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), (uint8_t *)remote_addr);
-				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
-			}
-			break;
-
-		case BNEP_EVENT_CHANNEL_TIMEOUT:
-			log_info("BNEP channel timeout! Channel will be closed");
-			break;
-
-		case BNEP_EVENT_CHANNEL_CLOSED:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_channel_closed(bnep_cid);
-			break;
-
-		case BNEP_EVENT_READY_TO_SEND:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_send_packet(bnep_cid);
-			break;
-
-		default:
-			break;
-		}
-		break;
-
-	case RFCOMM_DATA_PACKET:
-		// loopback
-		if (rfcomm_channel_id) {
-			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
-			if (err) {
-				log_error("rfcomm_send_internal -> error %d", err);
-			}
-		}
-		break;
-
-	case BNEP_DATA_PACKET:
-		bt_recv_packet(channel, packet, size);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/*
- * @section Network packet handler
- *
- * @text A pointer to the network packet is stored and a BNEP_EVENT_CAN_SEND_NOW requested
- */
-
- /* LISTING_START(networkPacketHandler): Network Packet Handler */
-static void network_send_packet_callback(uint16_t bnep_cid, const uint8_t * packet, uint16_t size) {
-	if ((bnep_cid == 0) || (network_buffer_len > 0)) {
-#ifdef PACKET_DUMP
-		int len = size;
-		printf("DROP %04x %d ", bnep_cid, size);
-		if (len > 128)
-			len = 128;
-		printf_hexdump(packet, len);
-#endif
-		if (network_buffer_len > 0) {
-			network_buffer_len = 0;
-			btstack_network_packet_sent(network_buffer_cid);
-		}
-	}
-
-	network_buffer_cid = bnep_cid;
-	network_buffer = packet;
-	network_buffer_len = size;
-}
-
-void panu_init(void)
-{
-	const hci_transport_t *transport;
-	bt_control_t       * control;
-	hci_uart_config_t  * config;
-	remote_device_db_t * remote_db;
-	service_record_item_t *spp_service_record_item;
-	service_record_item_t *bnep_service_record_item;
-
-	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
-
-	log_info("bt初期化...");
-
-	// start with BTstack init - especially configure HCI Transport
-	btstack_memory_init();
-	run_loop_init(RUN_LOOP_EMBEDDED);
-
-	/* Initialize HCI */
-	log_info("HCI初期化...");
-	transport = hci_transport_usb_instance();
-	control = NULL;
-	config = NULL;
-	remote_db = (remote_device_db_t *)&remote_device_db_memory;
-	hci_init(transport, config, control, remote_db);
-	hci_set_class_of_device(0x820300/*0x820810*/);
-
-	/* Initialize L2CAP */
-	log_info("L2CAP初期化...");
-	l2cap_init();
-	l2cap_register_packet_handler(packet_handler);
-
-	/* Initialise SDP, create record for SPP and register with SDP */
-	log_info("SDP初期化...");
-	sdp_init();
-
-	/* Initialize RFCOMM */
-	log_info("RFCOMM初期化...");
-	rfcomm_init();
-	rfcomm_register_packet_handler(packet_handler);
-	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
-
-	/* Initialise BNEP */
-	log_info("BNEP初期化...");
-	bnep_init();
-	bnep_register_packet_handler(packet_handler);
-	bnep_register_service(NULL, BNEP_UUID_PANU, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
-
-	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
-	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
-
-	// サービス定義
-	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
-	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
-
-	log_info("SPPサービス登録...");
-	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
-	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
-	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, spp_service_record_item);
-
-	log_info("BNEPサービス登録...");
-	pan_create_panu_service((uint8_t*)&bnep_service_record_item->service_record, "RX PANU", "RX PANU", BNEP_SECURITY_NONE);
-	de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
-	log_info("PANU SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, bnep_service_record_item);
-
-	// Secure Simple Pairing configuration -> just works
-	hci_ssp_set_enable(1);
-	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
-	hci_ssp_set_auto_accept(1);
-
-	/* Turn on the device */
-	log_info("HCI電源ON...");
-	hci_power_control(HCI_POWER_ON);
-
-	/* Initialise SDP */
-	sdp_parser_init();
-	sdp_parser_register_callback(handle_sdp_client_query_result);
-}
-
-void nap_init(void);
-
-void bt_init(void)
-{
-	btstack_network_init(&network_send_packet_callback);
-
-	if (bt_bnep_mode == 0) {
-		panu_init();
-	}
-	else {
-		nap_init();
-	}
-
-	bt_enabled = true;
-}
-
-void bt_task(void)
-{
-	extern void hal_tick_handler();
-
-	if (bt_enabled) {
-		hal_tick_handler();
-		run_loop_execute();
-		bt_send_packet(0xffff);
-	}
-}
-
-int bt_can_send_packet(void)
-{
-	return network_buffer_len == 0;
-}
-
-void bt_send_packet(uint16_t bnep_cid)
-{
-	if (network_buffer_len > 0) {
-		if (network_buffer_cid == 0) {
-			network_buffer_len = 0;
-			btstack_network_packet_sent(network_buffer_cid);
-			return;
-		}
-		/* Check for parked network packets and send it out now */
-		if (bnep_can_send_packet_now(network_buffer_cid)) {
-			uint16_t len = network_buffer_len;
-#ifdef PACKET_DUMP
-			printf("ETH %u => ", len);
-			if (len > 128)
-				len = 128;
-			printf_hexdump(network_buffer, len);
-#endif
-			// この関数はbnep_sendから再帰呼び出しされるので、
-			// bnep_sendを呼び出すより前に送信パケットなし状態にします。
-			network_buffer_len = 0;
-			bnep_send(network_buffer_cid, (uint8_t*)network_buffer, len);
-			btstack_network_packet_sent(network_buffer_cid);
-		}
-	}
-}
-
-void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size)
-{
-#ifdef PACKET_DUMP
-	int len = size;
-	printf("ETH %d <= ", size);
-	if (len > 128)
-		len = 128;
-	printf_hexdump(packet, len);
-#endif
-	btstack_network_process_packet(bnep_cid, packet, size);
-}
-
-void bt_channel_closed(uint16_t bnep_cid)
-{
-	log_info("BNEP channel closed");
-	btstack_network_down(bnep_cid);
-	if ((network_buffer_len > 0) && (network_buffer_cid == bnep_cid)) {
-		network_buffer_len = 0;
-		btstack_network_packet_sent(network_buffer_cid);
-	}
-}
-
-void bt_terminate(void)
-{
-	hci_close();
-
-	bt_enabled = false;
-}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/panu_main.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_btusb/panu_main.h	(revision 373)
+++ 	(revision )
@@ -1,35 +1,0 @@
-/*
- * panu_main.h
- *
- */
-#ifndef __BT_MAIN_
-#define __BT_MAIN_
-
-#if defined __cplusplus
-extern "C" {
-#endif
-
-// エラー返却用定数(-1:0xffff固定)
-#define FAILED_RFCOMM_ID_NOT_SET	0xffff
-
-#define RFCOMM_SERVER_CHANNEL 1
-
-void bt_init(void);
-void bt_task(void);
-int bt_can_send_packet(void);
-void bt_send_packet(uint16_t bnep_cid);
-void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
-void bt_channel_closed(uint16_t bnep_cid);
-void bt_terminate(void);
-
-void btstack_network_init(void (*send_packet_callback)(uint16_t bnep_cid, const uint8_t * packet, uint16_t size));
-void btstack_network_up(uint16_t bnep_cid, bd_addr_t local_addr, bd_addr_t remote_addr);
-const char * btstack_network_get_name(uint16_t bnep_cid);
-int btstack_network_down(uint16_t bnep_cid);
-void btstack_network_process_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
-void btstack_network_packet_sent(uint16_t bnep_cid);
-
-#if defined __cplusplus
-}
-#endif
-#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/Makefile.tinet
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/Makefile.tinet	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/Makefile.tinet	(revision 374)
@@ -37,4 +37,4 @@
 INCLUDES	:= $(INCLUDES) -I$(TINET_ROOT)/netdev/$(NET_DEV)
 TINET_DIRS	:= $(TINET_DIRS):$(TINET_ROOT)/netdev/$(NET_DEV)
-TINET_COBJS	:= $(TINET_COBJS) if_mbed.o if_btusb.o panu_main.o nap_main.o
+TINET_COBJS	:= $(TINET_COBJS) if_mbed.o if_btusb.o bt_main.o
 TINET_KERNEL_CFG := $(TINET_KERNEL_CFG) $(TINET_ROOT)/netdev/$(NET_DEV)/if_mbed.cfg
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/bt_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/bt_main.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/bt_main.c	(revision 374)
@@ -0,0 +1,689 @@
+/*
+ * Copyright (C) 2014 BlueKitchen GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ * 4. Any redistribution, use, or modification is done solely for
+ *    personal benefit and not for any commercial purpose or for
+ *    monetary gain.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
+ * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Please inquire about commercial licensing options at
+ * contact@bluekitchen-gmbh.com
+ *
+ */
+
+#include "btstack-config.h"
+
+#include <stdint.h>
+
+#include <btstack/hci_cmds.h>
+#include <btstack/run_loop.h>
+#include <btstack/sdp_util.h>
+
+#include <kernel.h>
+#include "kernel_cfg.h"
+#include "target_syssvc.h"
+
+#include "debug.h"
+#include "hci.h"
+#include "btstack_memory.h"
+#include "hci_dump.h"
+#include "l2cap.h"
+#include "sdp_parser.h"
+#include "sdp_client.h"
+#include "sdp_query_util.h"
+#include "sdp.h"
+#include "pan.h"
+#include "bt_main.h"
+#include "usb_hbth.h"
+
+//#define PACKET_DUMP
+
+// エラー返却用定数(-1:0xffff固定)
+#define FAILED_RFCOMM_ID_NOT_SET	0xffff
+
+#define RFCOMM_SERVER_CHANNEL 1
+static uint16_t  rfcomm_channel_id = FAILED_RFCOMM_ID_NOT_SET;
+
+static int record_id = -1;
+static uint16_t bnep_l2cap_psm = 0;
+static uint32_t bnep_remote_uuid = 0;
+static uint16_t bnep_version = 0;
+static uint16_t bnep_cid = 0;
+static bool_t bnep_do_connect = false;
+
+static uint16_t sdp_bnep_l2cap_psm = 0;
+static uint16_t sdp_bnep_version = 0;
+static uint32_t sdp_bnep_remote_uuid = 0;
+
+uint8_t   attribute_value[1000];
+const unsigned int attribute_value_buffer_size = sizeof(attribute_value);
+
+extern bd_addr_t remote_addr;
+
+uint8_t   spp_service_buffer[120];
+uint8_t   bnep_service_buffer[256];
+
+char bt_localname[] = TARGET_NAME"0000";
+
+volatile int bt_bnep_mode = 0;
+
+enum bt_state_t {
+	BT_STATE_DORMANT,
+	BT_STATE_POWER_ON,
+	BT_STATE_BNEP_QUERY,
+	BT_STATE_BNEP_WAIT,
+	BT_STATE_BNEP_QUERY_WAIT,
+	BT_STATE_CONNECTING,
+	BT_STATE_CONNECTED,
+};
+
+enum bt_state_t bt_state = BT_STATE_DORMANT;
+int bt_timer;
+
+// outgoing network packet
+const uint8_t * network_buffer;
+uint16_t network_buffer_len;
+uint16_t network_buffer_cid;
+
+/*************** PANU client routines *********************/
+
+char * get_string_from_data_element(uint8_t * element) {
+	de_size_t de_size = de_get_size_type(element);
+	int pos = de_get_header_size(element);
+	int len = 0;
+	switch (de_size) {
+	case DE_SIZE_VAR_8:
+		len = element[1];
+		break;
+	case DE_SIZE_VAR_16:
+		len = big_endian_read_16(element, 1);
+		break;
+	default:
+		break;
+	}
+	char * str = (char*)malloc(len + 1);
+	memcpy(str, &element[pos], len);
+	str[len] = '\0';
+	return str;
+}
+
+/* @section SDP parser callback
+*
+* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
+* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
+*/
+static void handle_sdp_client_record_complete(void)
+{
+	log_info("SDP BNEP Record complete");
+
+	// accept first entry or if we foudn a NAP and only have a PANU yet
+	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BLUETOOTH_SERVICE_CLASS_NAP && bnep_remote_uuid == BLUETOOTH_SERVICE_CLASS_PANU)) {
+		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
+		bnep_remote_uuid = sdp_bnep_remote_uuid;
+		bnep_version = sdp_bnep_version;
+	}
+}
+
+/* SDP parser callback */
+static void handle_sdp_client_query_result(sdp_query_event_t *event)
+{
+	sdp_query_attribute_value_event_t *value_event;
+	sdp_query_complete_event_t        *complete_event;
+	des_iterator_t des_list_it;
+	des_iterator_t prot_it;
+	char *str;
+
+	switch (event->type) {
+	case SDP_EVENT_QUERY_ATTRIBUTE_VALUE:
+		value_event = (sdp_query_attribute_value_event_t*)event;
+
+		// Handle new SDP record
+		if (value_event->record_id != record_id) {
+			handle_sdp_client_record_complete();
+			// next record started
+			record_id = value_event->record_id;
+			log_info("SDP Record: Nr: %d", record_id);
+		}
+
+		if (value_event->attribute_length <= attribute_value_buffer_size) {
+			attribute_value[value_event->data_offset] = value_event->data;
+
+			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
+				//printf("SDP Attribute Data:");
+				//printf_hexdump(attribute_value, value_event->attribute_length);
+
+				switch (value_event->attribute_id) {
+				case BLUETOOTH_ATTRIBUTE_SERVICE_CLASS_ID_LIST:
+					if (de_get_element_type(attribute_value) != DE_DES) break;
+					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
+						uint8_t * element = des_iterator_get_element(&des_list_it);
+						if (de_get_element_type(element) != DE_UUID) continue;
+						uint32_t uuid = de_get_uuid32(element);
+						switch (uuid) {
+						case BLUETOOTH_SERVICE_CLASS_PANU:
+						case BLUETOOTH_SERVICE_CLASS_NAP:
+						case BLUETOOTH_SERVICE_CLASS_GN:
+							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
+							sdp_bnep_remote_uuid = uuid;
+							break;
+						default:
+							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
+							break;
+						}
+					}
+					break;
+					// 0x0100 "Service Name"
+				case 0x0100:
+					// 0x0101 "Service Description"
+				case 0x0101:
+					str = get_string_from_data_element(attribute_value);
+					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
+					free(str);
+					break;
+				case BLUETOOTH_ATTRIBUTE_PROTOCOL_DESCRIPTOR_LIST: {
+					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
+
+					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
+						uint8_t       *des_element;
+						uint8_t       *element;
+						uint32_t       uuid;
+
+						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
+
+						des_element = des_iterator_get_element(&des_list_it);
+						des_iterator_init(&prot_it, des_element);
+						element = des_iterator_get_element(&prot_it);
+
+						if (de_get_element_type(element) != DE_UUID) continue;
+
+						uuid = de_get_uuid32(element);
+						switch (uuid) {
+						case BLUETOOTH_PROTOCOL_L2CAP:
+							if (!des_iterator_has_more(&prot_it)) continue;
+							des_iterator_next(&prot_it);
+							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
+							break;
+						case BLUETOOTH_PROTOCOL_BNEP:
+							if (!des_iterator_has_more(&prot_it)) continue;
+							des_iterator_next(&prot_it);
+							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
+							break;
+						default:
+							log_info("uuid 0x%04x", uuid);
+							break;
+						}
+					}
+					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
+					break;
+				}
+				default:
+					break;
+				}
+			}
+		}
+		else {
+			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
+		}
+		break;
+
+	case SDP_EVENT_QUERY_COMPLETE:
+		handle_sdp_client_record_complete();
+		complete_event = (sdp_query_complete_event_t*)event;
+		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
+		if (bnep_l2cap_psm) {
+			bnep_do_connect = complete_event->status == 0;
+		}
+		else {
+			bnep_do_connect = false;
+			log_error("No BNEP service found");
+		}
+		if (!bnep_do_connect) {
+			// 20秒後 BNEP Query 開始
+			bt_state = BT_STATE_BNEP_QUERY_WAIT;
+			bt_timer = 20 * 1000;
+		}
+		break;
+	}
+}
+
+static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
+{
+	uint8_t   event;
+	bd_addr_t event_addr;
+	uint8_t   rfcomm_channel_nr;
+	uint16_t  uuid_source;
+	uint16_t  uuid_dest;
+	uint16_t  mtu;
+
+	switch (packet_type) {
+	case HCI_EVENT_PACKET:
+		event = packet[0];
+		switch (event) {
+		case BTSTACK_EVENT_STATE:
+			/* BT Stack activated, get started */
+			if (packet[2] == HCI_STATE_WORKING) {
+				hci_send_cmd(&hci_write_local_name, bt_localname);
+				if (bt_bnep_mode == 0) {
+					// 即時 BNEP Query 開始
+					bt_state = BT_STATE_BNEP_QUERY_WAIT;
+					bt_timer = 0;
+				}
+				else {
+					bt_state = BT_STATE_BNEP_WAIT;
+					bt_timer = -1;
+				}
+			}
+			break;
+
+		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
+			if ((packet[2] == 0) && bnep_do_connect) {
+				bnep_do_connect = false;
+				/* Create BNEP connection */
+				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
+			}
+			break;
+
+		case HCI_EVENT_COMMAND_COMPLETE:
+			if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_read_bd_addr)) {
+				reverse_bd_addr(&packet[6], event_addr);
+				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
+
+				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
+				gap_set_local_name(bt_localname);
+				break;
+			}
+			if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_write_local_name)) {
+				gap_discoverable_control(1);
+				break;
+			}
+			break;
+
+		case HCI_EVENT_LINK_KEY_REQUEST:
+			// deny link key request
+			log_info("Link key request");
+			reverse_bd_addr(&packet[2], event_addr);
+			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
+			break;
+
+		case HCI_EVENT_PIN_CODE_REQUEST:
+			// inform about pin code request
+			log_info("Pin code request - using '0000'");
+			reverse_bd_addr(&packet[2], event_addr);
+			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
+			break;
+
+		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
+			// inform about user confirmation request
+			log_info("HCI User Confirmation Request with numeric value '%06u'", little_endian_read_32(packet, 8));
+			log_info("HCI User Confirmation Auto accept");
+			break;
+
+		case RFCOMM_EVENT_INCOMING_CONNECTION:
+			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
+			reverse_bd_addr(&packet[2], event_addr);
+			rfcomm_channel_nr = packet[8];
+			rfcomm_channel_id = little_endian_read_16(packet, 9);
+			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
+			rfcomm_accept_connection_internal(rfcomm_channel_id);
+			break;
+
+		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
+			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
+			if (packet[2]) {
+				log_info("RFCOMM channel open failed, status %u", packet[2]);
+			}
+			else {
+				rfcomm_channel_id = little_endian_read_16(packet, 12);
+				mtu = little_endian_read_16(packet, 14);
+				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
+			}
+			break;
+
+		case RFCOMM_EVENT_CHANNEL_CLOSED:
+			log_info("RFCOMM channel closed");
+			rfcomm_channel_id = 0;
+			break;
+
+		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
+			if (packet[2]) {
+				log_info("BNEP channel open failed, status %02x", packet[2]);
+
+				// 30秒後 BNEP Query 開始
+				bt_state = BT_STATE_BNEP_QUERY_WAIT;
+				bt_timer = 30 * 1000;
+			}
+			else {
+				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
+				bnep_cid = little_endian_read_16(packet, 3);
+				uuid_source = little_endian_read_16(packet, 5);
+				uuid_dest = little_endian_read_16(packet, 7);
+				mtu = little_endian_read_16(packet, 9);
+				//reverse_bd_addr(&packet[11], remote_addr); 
+				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
+				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
+				/* Setup network interface */
+				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), (uint8_t *)remote_addr);
+				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
+
+				bt_state = BT_STATE_CONNECTED;
+				bt_timer = -1;
+			}
+			break;
+
+		case BNEP_EVENT_CHANNEL_TIMEOUT:
+			log_info("BNEP channel timeout! Channel will be closed");
+			break;
+
+		case BNEP_EVENT_CHANNEL_CLOSED:
+			bnep_cid = little_endian_read_16(packet, 2);
+			bt_channel_closed(bnep_cid);
+
+			// 30秒後 BNEP Query 開始
+			bt_state = BT_STATE_BNEP_QUERY_WAIT;
+			bt_timer = 30 * 1000;
+			break;
+
+		case BNEP_EVENT_READY_TO_SEND:
+			bnep_cid = little_endian_read_16(packet, 2);
+			bt_send_packet(bnep_cid);
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case RFCOMM_DATA_PACKET:
+		// loopback
+		if (rfcomm_channel_id) {
+			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
+			if (err) {
+				log_error("rfcomm_send_internal -> error %d", err);
+			}
+		}
+		break;
+
+	case BNEP_DATA_PACKET:
+		bt_recv_packet(channel, packet, size);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*
+ * @section Network packet handler
+ *
+ * @text A pointer to the network packet is stored and a BNEP_EVENT_CAN_SEND_NOW requested
+ */
+
+ /* LISTING_START(networkPacketHandler): Network Packet Handler */
+static void network_send_packet_callback(uint16_t bnep_cid, const uint8_t * packet, uint16_t size) {
+	if ((bnep_cid == 0) || (network_buffer_len > 0)) {
+#ifdef PACKET_DUMP
+		int len = size;
+		printf("DROP %04x %d ", bnep_cid, size);
+		if (len > 128)
+			len = 128;
+		printf_hexdump(packet, len);
+#endif
+		if (network_buffer_len > 0) {
+			network_buffer_len = 0;
+			btstack_network_packet_sent(network_buffer_cid);
+		}
+	}
+
+	network_buffer_cid = bnep_cid;
+	network_buffer = packet;
+	network_buffer_len = size;
+}
+
+void bt_init(void)
+{
+	const hci_transport_t *transport;
+	bt_control_t       * control;
+	hci_uart_config_t  * config;
+	remote_device_db_t * remote_db;
+	service_record_item_t *spp_service_record_item;
+	service_record_item_t *bnep_service_record_item;
+
+	btstack_network_init(&network_send_packet_callback);
+
+	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
+
+	// start with BTstack init - especially configure HCI Transport
+	btstack_memory_init();
+	run_loop_init(RUN_LOOP_EMBEDDED);
+
+	/* Initialize HCI */
+	transport = hci_transport_usb_instance();
+	control = NULL;
+	config = NULL;
+	remote_db = (remote_device_db_t *)&remote_device_db_memory;
+	hci_init(transport, config, control, remote_db);
+	hci_set_class_of_device(0x820300/*0x820810*/);
+
+	/* Initialize L2CAP */
+	l2cap_init();
+	l2cap_register_packet_handler(packet_handler);
+
+	/* Initialise SDP, create record for SPP and register with SDP */
+	sdp_init();
+
+	/* Initialize RFCOMM */
+	rfcomm_init();
+	rfcomm_register_packet_handler(packet_handler);
+	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
+
+	/* Initialise BNEP */
+	bnep_init();
+	bnep_register_packet_handler(packet_handler);
+	if (bt_bnep_mode == 0) {
+		bnep_register_service(NULL, BLUETOOTH_SERVICE_CLASS_PANU, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
+	}
+	else {
+		bnep_register_service(NULL, BLUETOOTH_SERVICE_CLASS_NAP, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
+	}
+
+	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
+	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
+
+	// サービス定義
+	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
+	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
+
+	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
+	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
+	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
+	sdp_register_service_internal(NULL, spp_service_record_item);
+
+	if (bt_bnep_mode == 0) {
+		pan_create_panu_service((uint8_t*)&bnep_service_record_item->service_record, "RX PANU", "RX PANU", BNEP_SECURITY_NONE);
+		de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
+		log_info("PANU SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
+	}
+	else {
+		pan_create_nap_service((uint8_t*)&bnep_service_record_item->service_record, "RX NAP", "RX NAP", BNEP_SECURITY_NONE,
+			PAN_NET_ACCESS_TYPE_100MB_ETHERNET, 0x0001312D0/*10Mb/sec*/, NULL, NULL);
+		de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
+		log_info("NAP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
+	}
+	sdp_register_service_internal(NULL, bnep_service_record_item);
+
+	// Secure Simple Pairing configuration -> just works
+	hci_ssp_set_enable(1);
+	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
+	hci_ssp_set_auto_accept(1);
+
+	/* Turn on the device */
+	hci_power_control(HCI_POWER_ON);
+
+	/* Initialise SDP */
+	sdp_parser_init();
+	sdp_parser_register_callback(handle_sdp_client_query_result);
+
+	bt_state = BT_STATE_POWER_ON;
+	bt_timer = -1;
+}
+
+void bt_process(void)
+{
+	if (bt_state != BT_STATE_DORMANT) {
+		run_loop_execute();
+		bt_send_packet(0xffff);
+	}
+
+	if (bt_timer != 0)
+		return;
+
+	switch (bt_state) {
+	case BT_STATE_BNEP_QUERY_WAIT:
+		/* Send a general query for BNEP Protocol ID */
+		log_info("Start SDP BNEP query.");
+		sdp_general_query_for_uuid(remote_addr, BLUETOOTH_PROTOCOL_BNEP);
+
+		bt_state = BT_STATE_BNEP_QUERY;
+		bt_timer = -1;
+		break;
+	default:
+		bt_timer = -1;
+		break;
+	}
+}
+
+int bt_can_send_packet(void)
+{
+	return network_buffer_len == 0;
+}
+
+void bt_send_packet(uint16_t bnep_cid)
+{
+	if (network_buffer_len > 0) {
+		if (network_buffer_cid == 0) {
+			network_buffer_len = 0;
+			btstack_network_packet_sent(network_buffer_cid);
+			return;
+		}
+		/* Check for parked network packets and send it out now */
+		if (bnep_can_send_packet_now(network_buffer_cid)) {
+			uint16_t len = network_buffer_len;
+#ifdef PACKET_DUMP
+			printf("ETH %u => ", len);
+			if (len > 128)
+				len = 128;
+			printf_hexdump(network_buffer, len);
+#endif
+			// この関数はbnep_sendから再帰呼び出しされるので、
+			// bnep_sendを呼び出すより前に送信パケットなし状態にします。
+			network_buffer_len = 0;
+			bnep_send(network_buffer_cid, (uint8_t*)network_buffer, len);
+			btstack_network_packet_sent(network_buffer_cid);
+		}
+	}
+}
+
+void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size)
+{
+#ifdef PACKET_DUMP
+	int len = size;
+	printf("ETH %d <= ", size);
+	if (len > 128)
+		len = 128;
+	printf_hexdump(packet, len);
+#endif
+	btstack_network_process_packet(bnep_cid, packet, size);
+}
+
+void bt_channel_closed(uint16_t bnep_cid)
+{
+	log_info("BNEP channel closed");
+	btstack_network_down(bnep_cid);
+	if ((network_buffer_len > 0) && (network_buffer_cid == bnep_cid)) {
+		network_buffer_len = 0;
+		btstack_network_packet_sent(network_buffer_cid);
+	}
+}
+
+void bt_terminate(void)
+{
+	hci_close();
+
+	bt_state = BT_STATE_DORMANT;
+	bt_timer = -1;
+}
+
+void bt_task_on_start(struct task_if_t *task, ID tskid)
+{
+}
+
+void bt_task_on_end(struct task_if_t *task)
+{
+}
+
+int bt_task_get_timer(struct task_if_t *task)
+{
+	return bt_timer;
+}
+
+void bt_task_progress(struct task_if_t *task, int elapse)
+{
+	if (bt_timer == -1)
+		return;
+
+	bt_timer -= elapse;
+	if (bt_timer < 0)
+		bt_timer = 0;
+}
+
+void bt_task_process(struct task_if_t *task, enum task_event_t event)
+{
+	extern void hal_tick_handler();
+
+	switch (event & ~TASK_EVENT_TICK) {
+	case TASK_EVENT_START:
+		bt_init();
+		break;
+	case TASK_EVENT_TERMINATE:
+		bt_terminate();
+		break;
+	case TASK_EVENT_WAKEUP:
+	case TASK_EVENT_TIMEOUT:
+		if (event & TASK_EVENT_TICK)
+			hal_tick_handler();
+		bt_process();
+		break;
+	}
+}
+
+struct task_if_t bt_task = {
+	bt_task_on_start,
+	bt_task_on_end,
+	bt_task_get_timer,
+	bt_task_progress,
+	bt_task_process,
+};
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/bt_main.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/bt_main.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/bt_main.h	(revision 374)
@@ -0,0 +1,34 @@
+/*
+ * bt_main.h
+ *
+ */
+#ifndef __BT_MAIN_
+#define __BT_MAIN_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+// エラー返却用定数(-1:0xffff固定)
+#define FAILED_RFCOMM_ID_NOT_SET	0xffff
+
+#define RFCOMM_SERVER_CHANNEL 1
+
+void bt_init(void);
+int bt_can_send_packet(void);
+void bt_send_packet(uint16_t bnep_cid);
+void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
+void bt_channel_closed(uint16_t bnep_cid);
+void bt_terminate(void);
+
+void btstack_network_init(void (*send_packet_callback)(uint16_t bnep_cid, const uint8_t * packet, uint16_t size));
+void btstack_network_up(uint16_t bnep_cid, bd_addr_t local_addr, bd_addr_t remote_addr);
+const char * btstack_network_get_name(uint16_t bnep_cid);
+int btstack_network_down(uint16_t bnep_cid);
+void btstack_network_process_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
+void btstack_network_packet_sent(uint16_t bnep_cid);
+
+#if defined __cplusplus
+}
+#endif
+#endif
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/if_btusb.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/if_btusb.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/if_btusb.c	(revision 374)
@@ -77,5 +77,5 @@
 #include "kernel/kernel_impl.h"
 #include "btstack/utils.h"
-#include "panu_main.h"
+#include "bt_main.h"
 #include "usb_hbth.h"
 //#include "hal_cpu.h"
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/nap_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/nap_main.c	(revision 373)
+++ 	(revision )
@@ -1,447 +1,0 @@
-/*
- * Copyright (C) 2014 BlueKitchen GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- * 4. Any redistribution, use, or modification is done solely for
- *    personal benefit and not for any commercial purpose or for
- *    monetary gain.
- *
- * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
- * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Please inquire about commercial licensing options at
- * contact@bluekitchen-gmbh.com
- *
- */
-
-#include "btstack-config.h"
-
-#include <stdint.h>
-
-#include <btstack/hci_cmds.h>
-#include <btstack/run_loop.h>
-#include <btstack/sdp_util.h>
-
-#include <kernel.h>
-#include "kernel_cfg.h"
-#include "target_syssvc.h"
-
-#include "debug.h"
-#include "hci.h"
-#include "btstack_memory.h"
-#include "hci_dump.h"
-#include "l2cap.h"
-#include "sdp_parser.h"
-#include "sdp_client.h"
-#include "sdp_query_util.h"
-#include "sdp.h"
-#include "pan.h"
-#include "panu_main.h"
-
-extern uint16_t  rfcomm_channel_id;
-
-static int record_id = -1;
-static uint16_t bnep_l2cap_psm = 0;
-static uint32_t bnep_remote_uuid = 0;
-static uint16_t bnep_version = 0;
-static uint16_t bnep_cid = 0;
-static bool_t bnep_do_connect = false;
-
-static uint16_t sdp_bnep_l2cap_psm = 0;
-static uint16_t sdp_bnep_version = 0;
-static uint32_t sdp_bnep_remote_uuid = 0;
-
-extern uint8_t   attribute_value[];
-extern const unsigned int attribute_value_buffer_size;
-
-static bd_addr_t remote_addr;
-
-extern uint8_t   spp_service_buffer[120];
-extern uint8_t   bnep_service_buffer[256];
-
-extern char bt_localname[sizeof(TARGET_NAME"0000")];
-
-/*************** NAP server routines *********************/
-
-char * get_string_from_data_element(uint8_t * element);
-
-/* @section SDP parser callback
-*
-* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
-* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
-*/
-static void handle_sdp_client_record_complete(void)
-{
-	log_info("SDP BNEP Record complete");
-
-	// accept first entry or if we foudn a PANU and only have a NAP yet
-	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BNEP_UUID_PANU && bnep_remote_uuid == BNEP_UUID_NAP)) {
-		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
-		bnep_remote_uuid = sdp_bnep_remote_uuid;
-		bnep_version = sdp_bnep_version;
-	}
-}
-
-/* SDP parser callback */
-static void handle_sdp_client_query_result(sdp_query_event_t *event)
-{
-	sdp_query_attribute_value_event_t *value_event;
-	sdp_query_complete_event_t        *complete_event;
-	des_iterator_t des_list_it;
-	des_iterator_t prot_it;
-	char *str;
-
-	switch (event->type) {
-	case SDP_QUERY_ATTRIBUTE_VALUE:
-		value_event = (sdp_query_attribute_value_event_t*)event;
-
-		// Handle new SDP record
-		if (value_event->record_id != record_id) {
-			handle_sdp_client_record_complete();
-			// next record started
-			record_id = value_event->record_id;
-			log_info("SDP Record: Nr: %d", record_id);
-		}
-
-		if (value_event->attribute_length <= attribute_value_buffer_size) {
-			attribute_value[value_event->data_offset] = value_event->data;
-
-			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
-				//printf("SDP Attribute Data:");
-				//printf_hexdump(attribute_value, value_event->attribute_length);
-
-				switch (value_event->attribute_id) {
-				case SDP_ServiceClassIDList:
-					if (de_get_element_type(attribute_value) != DE_DES) break;
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t * element = des_iterator_get_element(&des_list_it);
-						if (de_get_element_type(element) != DE_UUID) continue;
-						uint32_t uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case BNEP_UUID_PANU:
-						case BNEP_UUID_NAP:
-						case BNEP_UUID_GN:
-							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
-							sdp_bnep_remote_uuid = uuid;
-							break;
-						default:
-							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
-							break;
-						}
-					}
-					break;
-					// 0x0100 "Service Name"
-				case 0x0100:
-					// 0x0101 "Service Description"
-				case 0x0101:
-					str = get_string_from_data_element(attribute_value);
-					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
-					free(str);
-					break;
-				case SDP_ProtocolDescriptorList: {
-					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
-
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t       *des_element;
-						uint8_t       *element;
-						uint32_t       uuid;
-
-						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
-
-						des_element = des_iterator_get_element(&des_list_it);
-						des_iterator_init(&prot_it, des_element);
-						element = des_iterator_get_element(&prot_it);
-
-						if (de_get_element_type(element) != DE_UUID) continue;
-
-						uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case SDP_L2CAPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
-							break;
-						case SDP_BNEPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
-							break;
-						default:
-							log_info("uuid 0x%04x", uuid);
-							break;
-						}
-					}
-					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
-					break;
-				}
-				default:
-					break;
-				}
-			}
-		}
-		else {
-			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
-		}
-		break;
-
-	case SDP_QUERY_COMPLETE:
-		handle_sdp_client_record_complete();
-		complete_event = (sdp_query_complete_event_t*)event;
-		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
-		if (bnep_l2cap_psm) {
-			bnep_do_connect = complete_event->status == 0;
-		}
-		else {
-			log_error("No BNEP service found");
-		}
-		break;
-	}
-}
-
-static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
-{
-	uint8_t   event;
-	bd_addr_t event_addr;
-	uint8_t   rfcomm_channel_nr;
-	uint16_t  uuid_source;
-	uint16_t  uuid_dest;
-	uint16_t  mtu;
-
-	switch (packet_type) {
-	case HCI_EVENT_PACKET:
-		event = packet[0];
-		switch (event) {
-		case BTSTACK_EVENT_STATE:
-			/* BT Stack activated, get started */
-			if (packet[2] == HCI_STATE_WORKING) {
-				hci_send_cmd(&hci_write_local_name, bt_localname);
-			}
-			break;
-
-		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
-			if ((packet[2] == 0) && bnep_do_connect) {
-				bnep_do_connect = false;
-				/* Create BNEP connection */
-				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
-			}
-			break;
-
-		case HCI_EVENT_COMMAND_COMPLETE:
-			if (COMMAND_COMPLETE_EVENT(packet, hci_read_bd_addr)) {
-				bt_flip_addr(event_addr, &packet[6]);
-				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
-
-				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
-				gap_set_local_name(bt_localname);
-				break;
-			}
-			if (COMMAND_COMPLETE_EVENT(packet, hci_write_local_name)) {
-				hci_discoverable_control(1);
-				break;
-			}
-			break;
-
-		case HCI_EVENT_LINK_KEY_REQUEST:
-			// deny link key request
-			log_info("Link key request");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
-			break;
-
-		case HCI_EVENT_PIN_CODE_REQUEST:
-			// inform about pin code request
-			log_info("Pin code request - using '0000'");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
-			break;
-
-		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
-			// inform about user confirmation request
-			log_info("HCI User Confirmation Request with numeric value '%06u'", READ_BT_32(packet, 8));
-			log_info("HCI User Confirmation Auto accept");
-			break;
-
-		case RFCOMM_EVENT_INCOMING_CONNECTION:
-			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
-			bt_flip_addr(event_addr, &packet[2]);
-			rfcomm_channel_nr = packet[8];
-			rfcomm_channel_id = READ_BT_16(packet, 9);
-			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
-			rfcomm_accept_connection_internal(rfcomm_channel_id);
-			break;
-
-		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
-			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
-			if (packet[2]) {
-				log_info("RFCOMM channel open failed, status %u", packet[2]);
-			}
-			else {
-				rfcomm_channel_id = READ_BT_16(packet, 12);
-				mtu = READ_BT_16(packet, 14);
-				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
-			}
-			break;
-
-		case RFCOMM_EVENT_CHANNEL_CLOSED:
-			log_info("RFCOMM channel closed");
-			rfcomm_channel_id = 0;
-			break;
-
-		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
-			if (packet[2]) {
-				log_info("BNEP channel open failed, status %02x", packet[2]);
-			}
-			else {
-				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
-				bnep_cid = READ_BT_16(packet, 3);
-				uuid_source = READ_BT_16(packet, 5);
-				uuid_dest = READ_BT_16(packet, 7);
-				mtu = READ_BT_16(packet, 9);
-				//bt_flip_addr(remote_addr, &packet[11]); 
-				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
-				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
-				/* Setup network interface */
-				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), remote_addr);
-				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
-			}
-			break;
-
-		case BNEP_EVENT_CHANNEL_TIMEOUT:
-			log_info("BNEP channel timeout! Channel will be closed");
-			break;
-
-		case BNEP_EVENT_CHANNEL_CLOSED:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_channel_closed(bnep_cid);
-			break;
-
-		case BNEP_EVENT_READY_TO_SEND:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_send_packet(bnep_cid);
-			break;
-
-		default:
-			break;
-		}
-		break;
-
-	case RFCOMM_DATA_PACKET:
-		// loopback
-		if (rfcomm_channel_id) {
-			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
-			if (err) {
-				log_error("rfcomm_send_internal -> error %d", err);
-			}
-		}
-		break;
-
-	case BNEP_DATA_PACKET:
-		bt_recv_packet(channel, packet, size);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void nap_init(void)
-{
-	const hci_transport_t *transport;
-	bt_control_t       * control;
-	hci_uart_config_t  * config;
-	remote_device_db_t * remote_db;
-	service_record_item_t *spp_service_record_item;
-	service_record_item_t *bnep_service_record_item;
-
-	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
-
-	log_info("bt初期化...");
-
-	// start with BTstack init - especially configure HCI Transport
-	btstack_memory_init();
-	run_loop_init(RUN_LOOP_EMBEDDED);
-
-	/* Initialize HCI */
-	log_info("HCI初期化...");
-	transport = hci_transport_usb_instance();
-	control = NULL;
-	config = NULL;
-	remote_db = (remote_device_db_t *)&remote_device_db_memory;
-	hci_init(transport, config, control, remote_db);
-	hci_set_class_of_device(0x820300/*0x820810*/);
-
-	/* Initialize L2CAP */
-	log_info("L2CAP初期化...");
-	l2cap_init();
-	l2cap_register_packet_handler(packet_handler);
-
-	/* Initialise SDP, create record for SPP and register with SDP */
-	log_info("SDP初期化...");
-	sdp_init();
-
-	/* Initialize RFCOMM */
-	log_info("RFCOMM初期化...");
-	rfcomm_init();
-	rfcomm_register_packet_handler(packet_handler);
-	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
-
-	/* Initialise BNEP */
-	log_info("BNEP初期化...");
-	bnep_init();
-	bnep_register_packet_handler(packet_handler);
-	bnep_register_service(NULL, BNEP_UUID_NAP, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
-
-	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
-	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
-
-	// サービス定義
-	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
-	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
-
-	log_info("SPPサービス登録...");
-	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
-	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
-	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, spp_service_record_item);
-
-	log_info("BNEPサービス登録...");
-	pan_create_nap_service((uint8_t*)&bnep_service_record_item->service_record, "RX NAP", "RX NAP", BNEP_SECURITY_NONE,
-		PAN_NET_ACCESS_TYPE_100MB_ETHERNET, 0x0001312D0/*10Mb/sec*/, NULL, NULL);
-	de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
-	log_info("NAP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, bnep_service_record_item);
-
-	// Secure Simple Pairing configuration -> just works
-	hci_ssp_set_enable(1);
-	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
-	hci_ssp_set_auto_accept(1);
-
-	/* Turn on the device */
-	log_info("HCI電源ON...");
-	hci_power_control(HCI_POWER_ON);
-
-	/* Initialise SDP */
-	sdp_parser_init();
-	sdp_parser_register_callback(handle_sdp_client_query_result);
-}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/panu_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/panu_main.c	(revision 373)
+++ 	(revision )
@@ -1,595 +1,0 @@
-/*
- * Copyright (C) 2014 BlueKitchen GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- * 4. Any redistribution, use, or modification is done solely for
- *    personal benefit and not for any commercial purpose or for
- *    monetary gain.
- *
- * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
- * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Please inquire about commercial licensing options at
- * contact@bluekitchen-gmbh.com
- *
- */
-
-#include "btstack-config.h"
-
-#include <stdint.h>
-
-#include <btstack/hci_cmds.h>
-#include <btstack/run_loop.h>
-#include <btstack/sdp_util.h>
-
-#include <kernel.h>
-#include "kernel_cfg.h"
-#include "target_syssvc.h"
-
-#include "debug.h"
-#include "hci.h"
-#include "btstack_memory.h"
-#include "hci_dump.h"
-#include "l2cap.h"
-#include "sdp_parser.h"
-#include "sdp_client.h"
-#include "sdp_query_util.h"
-#include "sdp.h"
-#include "pan.h"
-#include "panu_main.h"
-
-//#define PACKET_DUMP
-
-// エラー返却用定数(-1:0xffff固定)
-#define FAILED_RFCOMM_ID_NOT_SET	0xffff
-
-#define RFCOMM_SERVER_CHANNEL 1
-/*static*/ uint16_t  rfcomm_channel_id = FAILED_RFCOMM_ID_NOT_SET;
-
-static int record_id = -1;
-static uint16_t bnep_l2cap_psm = 0;
-static uint32_t bnep_remote_uuid = 0;
-static uint16_t bnep_version = 0;
-static uint16_t bnep_cid = 0;
-static bool_t bnep_do_connect = false;
-
-static uint16_t sdp_bnep_l2cap_psm = 0;
-static uint16_t sdp_bnep_version = 0;
-static uint32_t sdp_bnep_remote_uuid = 0;
-
-uint8_t   attribute_value[1000];
-const unsigned int attribute_value_buffer_size = sizeof(attribute_value);
-
-extern bd_addr_t remote_addr;
-
-uint8_t   spp_service_buffer[120];
-uint8_t   bnep_service_buffer[256];
-
-char bt_localname[] = TARGET_NAME"0000";
-
-volatile int bt_bnep_mode = 0;
-bool_t bt_enabled = false;
-
-// outgoing network packet
-const uint8_t * network_buffer;
-uint16_t network_buffer_len;
-uint16_t network_buffer_cid;
-
-/*************** PANU client routines *********************/
-
-char * get_string_from_data_element(uint8_t * element) {
-	de_size_t de_size = de_get_size_type(element);
-	int pos = de_get_header_size(element);
-	int len = 0;
-	switch (de_size) {
-	case DE_SIZE_VAR_8:
-		len = element[1];
-		break;
-	case DE_SIZE_VAR_16:
-		len = READ_NET_16(element, 1);
-		break;
-	default:
-		break;
-	}
-	char * str = (char*)malloc(len + 1);
-	memcpy(str, &element[pos], len);
-	str[len] = '\0';
-	return str;
-}
-
-/* @section SDP parser callback
-*
-* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
-* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
-*/
-static void handle_sdp_client_record_complete(void)
-{
-	log_info("SDP BNEP Record complete");
-
-	// accept first entry or if we foudn a NAP and only have a PANU yet
-	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BNEP_UUID_NAP && bnep_remote_uuid == BNEP_UUID_PANU)) {
-		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
-		bnep_remote_uuid = sdp_bnep_remote_uuid;
-		bnep_version = sdp_bnep_version;
-	}
-}
-
-/* SDP parser callback */
-static void handle_sdp_client_query_result(sdp_query_event_t *event)
-{
-	sdp_query_attribute_value_event_t *value_event;
-	sdp_query_complete_event_t        *complete_event;
-	des_iterator_t des_list_it;
-	des_iterator_t prot_it;
-	char *str;
-
-	switch (event->type) {
-	case SDP_QUERY_ATTRIBUTE_VALUE:
-		value_event = (sdp_query_attribute_value_event_t*)event;
-
-		// Handle new SDP record
-		if (value_event->record_id != record_id) {
-			handle_sdp_client_record_complete();
-			// next record started
-			record_id = value_event->record_id;
-			log_info("SDP Record: Nr: %d", record_id);
-		}
-
-		if (value_event->attribute_length <= attribute_value_buffer_size) {
-			attribute_value[value_event->data_offset] = value_event->data;
-
-			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
-				//printf("SDP Attribute Data:");
-				//printf_hexdump(attribute_value, value_event->attribute_length);
-
-				switch (value_event->attribute_id) {
-				case SDP_ServiceClassIDList:
-					if (de_get_element_type(attribute_value) != DE_DES) break;
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t * element = des_iterator_get_element(&des_list_it);
-						if (de_get_element_type(element) != DE_UUID) continue;
-						uint32_t uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case BNEP_UUID_PANU:
-						case BNEP_UUID_NAP:
-						case BNEP_UUID_GN:
-							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
-							sdp_bnep_remote_uuid = uuid;
-							break;
-						default:
-							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
-							break;
-						}
-					}
-					break;
-					// 0x0100 "Service Name"
-				case 0x0100:
-					// 0x0101 "Service Description"
-				case 0x0101:
-					str = get_string_from_data_element(attribute_value);
-					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
-					free(str);
-					break;
-				case SDP_ProtocolDescriptorList: {
-					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
-
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t       *des_element;
-						uint8_t       *element;
-						uint32_t       uuid;
-
-						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
-
-						des_element = des_iterator_get_element(&des_list_it);
-						des_iterator_init(&prot_it, des_element);
-						element = des_iterator_get_element(&prot_it);
-
-						if (de_get_element_type(element) != DE_UUID) continue;
-
-						uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case SDP_L2CAPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
-							break;
-						case SDP_BNEPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
-							break;
-						default:
-							log_info("uuid 0x%04x", uuid);
-							break;
-						}
-					}
-					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
-					break;
-				}
-				default:
-					break;
-				}
-			}
-		}
-		else {
-			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
-		}
-		break;
-
-	case SDP_QUERY_COMPLETE:
-		handle_sdp_client_record_complete();
-		complete_event = (sdp_query_complete_event_t*)event;
-		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
-		if (bnep_l2cap_psm) {
-			bnep_do_connect = complete_event->status == 0;
-		}
-		else {
-			log_error("No BNEP service found");
-		}
-		break;
-	}
-}
-
-static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
-{
-	uint8_t   event;
-	bd_addr_t event_addr;
-	uint8_t   rfcomm_channel_nr;
-	uint16_t  uuid_source;
-	uint16_t  uuid_dest;
-	uint16_t  mtu;
-
-	switch (packet_type) {
-	case HCI_EVENT_PACKET:
-		event = packet[0];
-		switch (event) {
-		case BTSTACK_EVENT_STATE:
-			/* BT Stack activated, get started */
-			if (packet[2] == HCI_STATE_WORKING) {
-				hci_send_cmd(&hci_write_local_name, bt_localname);
-				/* Send a general query for BNEP Protocol ID */
-				log_info("Start SDP BNEP query.");
-				sdp_general_query_for_uuid(remote_addr, SDP_BNEPProtocol);
-			}
-			break;
-
-		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
-			if ((packet[2] == 0) && bnep_do_connect) {
-				bnep_do_connect = false;
-				/* Create BNEP connection */
-				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
-			}
-			break;
-
-		case HCI_EVENT_COMMAND_COMPLETE:
-			if (COMMAND_COMPLETE_EVENT(packet, hci_read_bd_addr)) {
-				bt_flip_addr(event_addr, &packet[6]);
-				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
-
-				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
-				gap_set_local_name(bt_localname);
-				break;
-			}
-			if (COMMAND_COMPLETE_EVENT(packet, hci_write_local_name)) {
-				hci_discoverable_control(1);
-				break;
-			}
-			break;
-
-		case HCI_EVENT_LINK_KEY_REQUEST:
-			// deny link key request
-			log_info("Link key request");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
-			break;
-
-		case HCI_EVENT_PIN_CODE_REQUEST:
-			// inform about pin code request
-			log_info("Pin code request - using '0000'");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
-			break;
-
-		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
-			// inform about user confirmation request
-			log_info("HCI User Confirmation Request with numeric value '%06u'", READ_BT_32(packet, 8));
-			log_info("HCI User Confirmation Auto accept");
-			break;
-
-		case RFCOMM_EVENT_INCOMING_CONNECTION:
-			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
-			bt_flip_addr(event_addr, &packet[2]);
-			rfcomm_channel_nr = packet[8];
-			rfcomm_channel_id = READ_BT_16(packet, 9);
-			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
-			rfcomm_accept_connection_internal(rfcomm_channel_id);
-			break;
-
-		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
-			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
-			if (packet[2]) {
-				log_info("RFCOMM channel open failed, status %u", packet[2]);
-			}
-			else {
-				rfcomm_channel_id = READ_BT_16(packet, 12);
-				mtu = READ_BT_16(packet, 14);
-				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
-			}
-			break;
-
-		case RFCOMM_EVENT_CHANNEL_CLOSED:
-			log_info("RFCOMM channel closed");
-			rfcomm_channel_id = 0;
-			break;
-
-		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
-			if (packet[2]) {
-				log_info("BNEP channel open failed, status %02x", packet[2]);
-			}
-			else {
-				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
-				bnep_cid = READ_BT_16(packet, 3);
-				uuid_source = READ_BT_16(packet, 5);
-				uuid_dest = READ_BT_16(packet, 7);
-				mtu = READ_BT_16(packet, 9);
-				//bt_flip_addr(remote_addr, &packet[11]); 
-				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
-				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
-				/* Setup network interface */
-				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), (uint8_t *)remote_addr);
-				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
-			}
-			break;
-
-		case BNEP_EVENT_CHANNEL_TIMEOUT:
-			log_info("BNEP channel timeout! Channel will be closed");
-			break;
-
-		case BNEP_EVENT_CHANNEL_CLOSED:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_channel_closed(bnep_cid);
-			break;
-
-		case BNEP_EVENT_READY_TO_SEND:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_send_packet(bnep_cid);
-			break;
-
-		default:
-			break;
-		}
-		break;
-
-	case RFCOMM_DATA_PACKET:
-		// loopback
-		if (rfcomm_channel_id) {
-			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
-			if (err) {
-				log_error("rfcomm_send_internal -> error %d", err);
-			}
-		}
-		break;
-
-	case BNEP_DATA_PACKET:
-		bt_recv_packet(channel, packet, size);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/*
- * @section Network packet handler
- *
- * @text A pointer to the network packet is stored and a BNEP_EVENT_CAN_SEND_NOW requested
- */
-
- /* LISTING_START(networkPacketHandler): Network Packet Handler */
-static void network_send_packet_callback(uint16_t bnep_cid, const uint8_t * packet, uint16_t size) {
-	if ((bnep_cid == 0) || (network_buffer_len > 0)) {
-#ifdef PACKET_DUMP
-		int len = size;
-		printf("DROP %04x %d ", bnep_cid, size);
-		if (len > 128)
-			len = 128;
-		printf_hexdump(packet, len);
-#endif
-		if (network_buffer_len > 0) {
-			network_buffer_len = 0;
-			btstack_network_packet_sent(network_buffer_cid);
-		}
-	}
-
-	network_buffer_cid = bnep_cid;
-	network_buffer = packet;
-	network_buffer_len = size;
-}
-
-void panu_init(void)
-{
-	const hci_transport_t *transport;
-	bt_control_t       * control;
-	hci_uart_config_t  * config;
-	remote_device_db_t * remote_db;
-	service_record_item_t *spp_service_record_item;
-	service_record_item_t *bnep_service_record_item;
-
-	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
-
-	log_info("bt初期化...");
-
-	// start with BTstack init - especially configure HCI Transport
-	btstack_memory_init();
-	run_loop_init(RUN_LOOP_EMBEDDED);
-
-	/* Initialize HCI */
-	log_info("HCI初期化...");
-	transport = hci_transport_usb_instance();
-	control = NULL;
-	config = NULL;
-	remote_db = (remote_device_db_t *)&remote_device_db_memory;
-	hci_init(transport, config, control, remote_db);
-	hci_set_class_of_device(0x820300/*0x820810*/);
-
-	/* Initialize L2CAP */
-	log_info("L2CAP初期化...");
-	l2cap_init();
-	l2cap_register_packet_handler(packet_handler);
-
-	/* Initialise SDP, create record for SPP and register with SDP */
-	log_info("SDP初期化...");
-	sdp_init();
-
-	/* Initialize RFCOMM */
-	log_info("RFCOMM初期化...");
-	rfcomm_init();
-	rfcomm_register_packet_handler(packet_handler);
-	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
-
-	/* Initialise BNEP */
-	log_info("BNEP初期化...");
-	bnep_init();
-	bnep_register_packet_handler(packet_handler);
-	bnep_register_service(NULL, BNEP_UUID_PANU, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
-
-	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
-	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
-
-	// サービス定義
-	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
-	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
-
-	log_info("SPPサービス登録...");
-	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
-	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
-	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, spp_service_record_item);
-
-	log_info("BNEPサービス登録...");
-	pan_create_panu_service((uint8_t*)&bnep_service_record_item->service_record, "RX PANU", "RX PANU", BNEP_SECURITY_NONE);
-	de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
-	log_info("PANU SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, bnep_service_record_item);
-
-	// Secure Simple Pairing configuration -> just works
-	hci_ssp_set_enable(1);
-	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
-	hci_ssp_set_auto_accept(1);
-
-	/* Turn on the device */
-	log_info("HCI電源ON...");
-	hci_power_control(HCI_POWER_ON);
-
-	/* Initialise SDP */
-	sdp_parser_init();
-	sdp_parser_register_callback(handle_sdp_client_query_result);
-}
-
-void nap_init(void);
-
-void bt_init(void)
-{
-	btstack_network_init(&network_send_packet_callback);
-
-	if (bt_bnep_mode == 0) {
-		panu_init();
-	}
-	else {
-		nap_init();
-	}
-
-	bt_enabled = true;
-}
-
-void bt_task(void)
-{
-	extern void hal_tick_handler();
-
-	if (bt_enabled) {
-		hal_tick_handler();
-		run_loop_execute();
-		bt_send_packet(0xffff);
-	}
-}
-
-int bt_can_send_packet(void)
-{
-	return network_buffer_len == 0;
-}
-
-void bt_send_packet(uint16_t bnep_cid)
-{
-	if (network_buffer_len > 0) {
-		if (network_buffer_cid == 0) {
-			network_buffer_len = 0;
-			btstack_network_packet_sent(network_buffer_cid);
-			return;
-		}
-		/* Check for parked network packets and send it out now */
-		if (bnep_can_send_packet_now(network_buffer_cid)) {
-			uint16_t len = network_buffer_len;
-#ifdef PACKET_DUMP
-			printf("ETH %u => ", len);
-			if (len > 128)
-				len = 128;
-			printf_hexdump(network_buffer, len);
-#endif
-			// この関数はbnep_sendから再帰呼び出しされるので、
-			// bnep_sendを呼び出すより前に送信パケットなし状態にします。
-			network_buffer_len = 0;
-			bnep_send(network_buffer_cid, (uint8_t*)network_buffer, len);
-			btstack_network_packet_sent(network_buffer_cid);
-		}
-	}
-}
-
-void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size)
-{
-#ifdef PACKET_DUMP
-	int len = size;
-	printf("ETH %d <= ", size);
-	if (len > 128)
-		len = 128;
-	printf_hexdump(packet, len);
-#endif
-	btstack_network_process_packet(bnep_cid, packet, size);
-}
-
-void bt_channel_closed(uint16_t bnep_cid)
-{
-	log_info("BNEP channel closed");
-	btstack_network_down(bnep_cid);
-	if ((network_buffer_len > 0) && (network_buffer_cid == bnep_cid)) {
-		network_buffer_len = 0;
-		btstack_network_packet_sent(network_buffer_cid);
-	}
-}
-
-void bt_terminate(void)
-{
-	hci_close();
-
-	bt_enabled = false;
-}
Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/panu_main.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/tinet/netdev/if_enbt/panu_main.h	(revision 373)
+++ 	(revision )
@@ -1,35 +1,0 @@
-/*
- * panu_main.h
- *
- */
-#ifndef __BT_MAIN_
-#define __BT_MAIN_
-
-#if defined __cplusplus
-extern "C" {
-#endif
-
-// エラー返却用定数(-1:0xffff固定)
-#define FAILED_RFCOMM_ID_NOT_SET	0xffff
-
-#define RFCOMM_SERVER_CHANNEL 1
-
-void bt_init(void);
-void bt_task(void);
-int bt_can_send_packet(void);
-void bt_send_packet(uint16_t bnep_cid);
-void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
-void bt_channel_closed(uint16_t bnep_cid);
-void bt_terminate(void);
-
-void btstack_network_init(void (*send_packet_callback)(uint16_t bnep_cid, const uint8_t * packet, uint16_t size));
-void btstack_network_up(uint16_t bnep_cid, bd_addr_t local_addr, bd_addr_t remote_addr);
-const char * btstack_network_get_name(uint16_t bnep_cid);
-int btstack_network_down(uint16_t bnep_cid);
-void btstack_network_process_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
-void btstack_network_packet_sent(uint16_t bnep_cid);
-
-#if defined __cplusplus
-}
-#endif
-#endif
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/Debug/Makefile
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/Debug/Makefile	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/bnep_bridge/Debug/Makefile	(revision 374)
@@ -163,5 +163,5 @@
 #  共通コンパイルオプションの定義
 #
-COPTS := -g -std=gnu99 $(COPTS)
+COPTS := -g -std=gnu99 -ffunction-sections -fdata-sections $(COPTS)
 ifndef OMIT_WARNING_ALL
 	COPTS := -Wall $(COPTS)
@@ -199,9 +199,9 @@
 ifdef USE_CXX
 	APPL_CXXOBJS := main.o
-	APPL_COBJS := $(APPL_COBJS) if_btusb.o if_mbed.o nap_main.o panu_main.o
-else
-	APPL_COBJS := $(APPL_COBJS) main.o if_btusb.o if_mbed.o nap_main.o panu_main.o
-endif
-APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o
+	APPL_COBJS := $(APPL_COBJS) if_btusb.o if_mbed.o bt_main.o
+else
+	APPL_COBJS := $(APPL_COBJS) main.o if_btusb.o if_mbed.o bt_main.o
+endif
+APPL_COBJS := $(APPL_COBJS) log_output.o vasyslog.o t_perror.o strerror.o mbed_stub.o
 APPL_BINOBJS := rom_fs.o
 APPL_CFLAGS := $(APPL_CFLAGS) -nostdinc
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/bt_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/bt_main.c	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/bt_main.c	(revision 374)
@@ -0,0 +1,689 @@
+/*
+ * Copyright (C) 2014 BlueKitchen GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ * 4. Any redistribution, use, or modification is done solely for
+ *    personal benefit and not for any commercial purpose or for
+ *    monetary gain.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
+ * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Please inquire about commercial licensing options at
+ * contact@bluekitchen-gmbh.com
+ *
+ */
+
+#include "btstack-config.h"
+
+#include <stdint.h>
+
+#include <btstack/hci_cmds.h>
+#include <btstack/run_loop.h>
+#include <btstack/sdp_util.h>
+
+#include <kernel.h>
+#include "kernel_cfg.h"
+#include "target_syssvc.h"
+
+#include "debug.h"
+#include "hci.h"
+#include "btstack_memory.h"
+#include "hci_dump.h"
+#include "l2cap.h"
+#include "sdp_parser.h"
+#include "sdp_client.h"
+#include "sdp_query_util.h"
+#include "sdp.h"
+#include "pan.h"
+#include "bt_main.h"
+#include "usb_hbth.h"
+
+//#define PACKET_DUMP
+
+// エラー返却用定数(-1:0xffff固定)
+#define FAILED_RFCOMM_ID_NOT_SET	0xffff
+
+#define RFCOMM_SERVER_CHANNEL 1
+static uint16_t  rfcomm_channel_id = FAILED_RFCOMM_ID_NOT_SET;
+
+static int record_id = -1;
+static uint16_t bnep_l2cap_psm = 0;
+static uint32_t bnep_remote_uuid = 0;
+static uint16_t bnep_version = 0;
+static uint16_t bnep_cid = 0;
+static bool_t bnep_do_connect = false;
+
+static uint16_t sdp_bnep_l2cap_psm = 0;
+static uint16_t sdp_bnep_version = 0;
+static uint32_t sdp_bnep_remote_uuid = 0;
+
+uint8_t   attribute_value[1000];
+const unsigned int attribute_value_buffer_size = sizeof(attribute_value);
+
+extern bd_addr_t remote_addr;
+
+uint8_t   spp_service_buffer[120];
+uint8_t   bnep_service_buffer[256];
+
+char bt_localname[] = TARGET_NAME"0000";
+
+volatile int bt_bnep_mode = 0;
+
+enum bt_state_t {
+	BT_STATE_DORMANT,
+	BT_STATE_POWER_ON,
+	BT_STATE_BNEP_QUERY,
+	BT_STATE_BNEP_WAIT,
+	BT_STATE_BNEP_QUERY_WAIT,
+	BT_STATE_CONNECTING,
+	BT_STATE_CONNECTED,
+};
+
+enum bt_state_t bt_state = BT_STATE_DORMANT;
+int bt_timer;
+
+// outgoing network packet
+const uint8_t * network_buffer;
+uint16_t network_buffer_len;
+uint16_t network_buffer_cid;
+
+/*************** PANU client routines *********************/
+
+char * get_string_from_data_element(uint8_t * element) {
+	de_size_t de_size = de_get_size_type(element);
+	int pos = de_get_header_size(element);
+	int len = 0;
+	switch (de_size) {
+	case DE_SIZE_VAR_8:
+		len = element[1];
+		break;
+	case DE_SIZE_VAR_16:
+		len = big_endian_read_16(element, 1);
+		break;
+	default:
+		break;
+	}
+	char * str = (char*)malloc(len + 1);
+	memcpy(str, &element[pos], len);
+	str[len] = '\0';
+	return str;
+}
+
+/* @section SDP parser callback
+*
+* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
+* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
+*/
+static void handle_sdp_client_record_complete(void)
+{
+	log_info("SDP BNEP Record complete");
+
+	// accept first entry or if we foudn a NAP and only have a PANU yet
+	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BLUETOOTH_SERVICE_CLASS_NAP && bnep_remote_uuid == BLUETOOTH_SERVICE_CLASS_PANU)) {
+		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
+		bnep_remote_uuid = sdp_bnep_remote_uuid;
+		bnep_version = sdp_bnep_version;
+	}
+}
+
+/* SDP parser callback */
+static void handle_sdp_client_query_result(sdp_query_event_t *event)
+{
+	sdp_query_attribute_value_event_t *value_event;
+	sdp_query_complete_event_t        *complete_event;
+	des_iterator_t des_list_it;
+	des_iterator_t prot_it;
+	char *str;
+
+	switch (event->type) {
+	case SDP_EVENT_QUERY_ATTRIBUTE_VALUE:
+		value_event = (sdp_query_attribute_value_event_t*)event;
+
+		// Handle new SDP record
+		if (value_event->record_id != record_id) {
+			handle_sdp_client_record_complete();
+			// next record started
+			record_id = value_event->record_id;
+			log_info("SDP Record: Nr: %d", record_id);
+		}
+
+		if (value_event->attribute_length <= attribute_value_buffer_size) {
+			attribute_value[value_event->data_offset] = value_event->data;
+
+			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
+				//printf("SDP Attribute Data:");
+				//printf_hexdump(attribute_value, value_event->attribute_length);
+
+				switch (value_event->attribute_id) {
+				case BLUETOOTH_ATTRIBUTE_SERVICE_CLASS_ID_LIST:
+					if (de_get_element_type(attribute_value) != DE_DES) break;
+					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
+						uint8_t * element = des_iterator_get_element(&des_list_it);
+						if (de_get_element_type(element) != DE_UUID) continue;
+						uint32_t uuid = de_get_uuid32(element);
+						switch (uuid) {
+						case BLUETOOTH_SERVICE_CLASS_PANU:
+						case BLUETOOTH_SERVICE_CLASS_NAP:
+						case BLUETOOTH_SERVICE_CLASS_GN:
+							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
+							sdp_bnep_remote_uuid = uuid;
+							break;
+						default:
+							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
+							break;
+						}
+					}
+					break;
+					// 0x0100 "Service Name"
+				case 0x0100:
+					// 0x0101 "Service Description"
+				case 0x0101:
+					str = get_string_from_data_element(attribute_value);
+					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
+					free(str);
+					break;
+				case BLUETOOTH_ATTRIBUTE_PROTOCOL_DESCRIPTOR_LIST: {
+					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
+
+					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
+						uint8_t       *des_element;
+						uint8_t       *element;
+						uint32_t       uuid;
+
+						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
+
+						des_element = des_iterator_get_element(&des_list_it);
+						des_iterator_init(&prot_it, des_element);
+						element = des_iterator_get_element(&prot_it);
+
+						if (de_get_element_type(element) != DE_UUID) continue;
+
+						uuid = de_get_uuid32(element);
+						switch (uuid) {
+						case BLUETOOTH_PROTOCOL_L2CAP:
+							if (!des_iterator_has_more(&prot_it)) continue;
+							des_iterator_next(&prot_it);
+							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
+							break;
+						case BLUETOOTH_PROTOCOL_BNEP:
+							if (!des_iterator_has_more(&prot_it)) continue;
+							des_iterator_next(&prot_it);
+							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
+							break;
+						default:
+							log_info("uuid 0x%04x", uuid);
+							break;
+						}
+					}
+					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
+					break;
+				}
+				default:
+					break;
+				}
+			}
+		}
+		else {
+			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
+		}
+		break;
+
+	case SDP_EVENT_QUERY_COMPLETE:
+		handle_sdp_client_record_complete();
+		complete_event = (sdp_query_complete_event_t*)event;
+		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
+		if (bnep_l2cap_psm) {
+			bnep_do_connect = complete_event->status == 0;
+		}
+		else {
+			bnep_do_connect = false;
+			log_error("No BNEP service found");
+		}
+		if (!bnep_do_connect) {
+			// 20秒後 BNEP Query 開始
+			bt_state = BT_STATE_BNEP_QUERY_WAIT;
+			bt_timer = 20 * 1000;
+		}
+		break;
+	}
+}
+
+static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
+{
+	uint8_t   event;
+	bd_addr_t event_addr;
+	uint8_t   rfcomm_channel_nr;
+	uint16_t  uuid_source;
+	uint16_t  uuid_dest;
+	uint16_t  mtu;
+
+	switch (packet_type) {
+	case HCI_EVENT_PACKET:
+		event = packet[0];
+		switch (event) {
+		case BTSTACK_EVENT_STATE:
+			/* BT Stack activated, get started */
+			if (packet[2] == HCI_STATE_WORKING) {
+				hci_send_cmd(&hci_write_local_name, bt_localname);
+				if (bt_bnep_mode == 0) {
+					// 即時 BNEP Query 開始
+					bt_state = BT_STATE_BNEP_QUERY_WAIT;
+					bt_timer = 0;
+				}
+				else {
+					bt_state = BT_STATE_BNEP_WAIT;
+					bt_timer = -1;
+				}
+			}
+			break;
+
+		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
+			if ((packet[2] == 0) && bnep_do_connect) {
+				bnep_do_connect = false;
+				/* Create BNEP connection */
+				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
+			}
+			break;
+
+		case HCI_EVENT_COMMAND_COMPLETE:
+			if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_read_bd_addr)) {
+				reverse_bd_addr(&packet[6], event_addr);
+				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
+
+				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
+				gap_set_local_name(bt_localname);
+				break;
+			}
+			if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_write_local_name)) {
+				gap_discoverable_control(1);
+				break;
+			}
+			break;
+
+		case HCI_EVENT_LINK_KEY_REQUEST:
+			// deny link key request
+			log_info("Link key request");
+			reverse_bd_addr(&packet[2], event_addr);
+			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
+			break;
+
+		case HCI_EVENT_PIN_CODE_REQUEST:
+			// inform about pin code request
+			log_info("Pin code request - using '0000'");
+			reverse_bd_addr(&packet[2], event_addr);
+			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
+			break;
+
+		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
+			// inform about user confirmation request
+			log_info("HCI User Confirmation Request with numeric value '%06u'", little_endian_read_32(packet, 8));
+			log_info("HCI User Confirmation Auto accept");
+			break;
+
+		case RFCOMM_EVENT_INCOMING_CONNECTION:
+			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
+			reverse_bd_addr(&packet[2], event_addr);
+			rfcomm_channel_nr = packet[8];
+			rfcomm_channel_id = little_endian_read_16(packet, 9);
+			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
+			rfcomm_accept_connection_internal(rfcomm_channel_id);
+			break;
+
+		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
+			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
+			if (packet[2]) {
+				log_info("RFCOMM channel open failed, status %u", packet[2]);
+			}
+			else {
+				rfcomm_channel_id = little_endian_read_16(packet, 12);
+				mtu = little_endian_read_16(packet, 14);
+				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
+			}
+			break;
+
+		case RFCOMM_EVENT_CHANNEL_CLOSED:
+			log_info("RFCOMM channel closed");
+			rfcomm_channel_id = 0;
+			break;
+
+		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
+			if (packet[2]) {
+				log_info("BNEP channel open failed, status %02x", packet[2]);
+
+				// 30秒後 BNEP Query 開始
+				bt_state = BT_STATE_BNEP_QUERY_WAIT;
+				bt_timer = 30 * 1000;
+			}
+			else {
+				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
+				bnep_cid = little_endian_read_16(packet, 3);
+				uuid_source = little_endian_read_16(packet, 5);
+				uuid_dest = little_endian_read_16(packet, 7);
+				mtu = little_endian_read_16(packet, 9);
+				//reverse_bd_addr(&packet[11], remote_addr); 
+				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
+				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
+				/* Setup network interface */
+				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), (uint8_t *)remote_addr);
+				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
+
+				bt_state = BT_STATE_CONNECTED;
+				bt_timer = -1;
+			}
+			break;
+
+		case BNEP_EVENT_CHANNEL_TIMEOUT:
+			log_info("BNEP channel timeout! Channel will be closed");
+			break;
+
+		case BNEP_EVENT_CHANNEL_CLOSED:
+			bnep_cid = little_endian_read_16(packet, 2);
+			bt_channel_closed(bnep_cid);
+
+			// 30秒後 BNEP Query 開始
+			bt_state = BT_STATE_BNEP_QUERY_WAIT;
+			bt_timer = 30 * 1000;
+			break;
+
+		case BNEP_EVENT_READY_TO_SEND:
+			bnep_cid = little_endian_read_16(packet, 2);
+			bt_send_packet(bnep_cid);
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case RFCOMM_DATA_PACKET:
+		// loopback
+		if (rfcomm_channel_id) {
+			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
+			if (err) {
+				log_error("rfcomm_send_internal -> error %d", err);
+			}
+		}
+		break;
+
+	case BNEP_DATA_PACKET:
+		bt_recv_packet(channel, packet, size);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*
+ * @section Network packet handler
+ *
+ * @text A pointer to the network packet is stored and a BNEP_EVENT_CAN_SEND_NOW requested
+ */
+
+ /* LISTING_START(networkPacketHandler): Network Packet Handler */
+static void network_send_packet_callback(uint16_t bnep_cid, const uint8_t * packet, uint16_t size) {
+	if ((bnep_cid == 0) || (network_buffer_len > 0)) {
+#ifdef PACKET_DUMP
+		int len = size;
+		printf("DROP %04x %d ", bnep_cid, size);
+		if (len > 128)
+			len = 128;
+		printf_hexdump(packet, len);
+#endif
+		if (network_buffer_len > 0) {
+			network_buffer_len = 0;
+			btstack_network_packet_sent(network_buffer_cid);
+		}
+	}
+
+	network_buffer_cid = bnep_cid;
+	network_buffer = packet;
+	network_buffer_len = size;
+}
+
+void bt_init(void)
+{
+	const hci_transport_t *transport;
+	bt_control_t       * control;
+	hci_uart_config_t  * config;
+	remote_device_db_t * remote_db;
+	service_record_item_t *spp_service_record_item;
+	service_record_item_t *bnep_service_record_item;
+
+	btstack_network_init(&network_send_packet_callback);
+
+	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
+
+	// start with BTstack init - especially configure HCI Transport
+	btstack_memory_init();
+	run_loop_init(RUN_LOOP_EMBEDDED);
+
+	/* Initialize HCI */
+	transport = hci_transport_usb_instance();
+	control = NULL;
+	config = NULL;
+	remote_db = (remote_device_db_t *)&remote_device_db_memory;
+	hci_init(transport, config, control, remote_db);
+	hci_set_class_of_device(0x820300/*0x820810*/);
+
+	/* Initialize L2CAP */
+	l2cap_init();
+	l2cap_register_packet_handler(packet_handler);
+
+	/* Initialise SDP, create record for SPP and register with SDP */
+	sdp_init();
+
+	/* Initialize RFCOMM */
+	rfcomm_init();
+	rfcomm_register_packet_handler(packet_handler);
+	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
+
+	/* Initialise BNEP */
+	bnep_init();
+	bnep_register_packet_handler(packet_handler);
+	if (bt_bnep_mode == 0) {
+		bnep_register_service(NULL, BLUETOOTH_SERVICE_CLASS_PANU, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
+	}
+	else {
+		bnep_register_service(NULL, BLUETOOTH_SERVICE_CLASS_NAP, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
+	}
+
+	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
+	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
+
+	// サービス定義
+	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
+	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
+
+	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
+	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
+	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
+	sdp_register_service_internal(NULL, spp_service_record_item);
+
+	if (bt_bnep_mode == 0) {
+		pan_create_panu_service((uint8_t*)&bnep_service_record_item->service_record, "RX PANU", "RX PANU", BNEP_SECURITY_NONE);
+		de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
+		log_info("PANU SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
+	}
+	else {
+		pan_create_nap_service((uint8_t*)&bnep_service_record_item->service_record, "RX NAP", "RX NAP", BNEP_SECURITY_NONE,
+			PAN_NET_ACCESS_TYPE_100MB_ETHERNET, 0x0001312D0/*10Mb/sec*/, NULL, NULL);
+		de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
+		log_info("NAP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
+	}
+	sdp_register_service_internal(NULL, bnep_service_record_item);
+
+	// Secure Simple Pairing configuration -> just works
+	hci_ssp_set_enable(1);
+	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
+	hci_ssp_set_auto_accept(1);
+
+	/* Turn on the device */
+	hci_power_control(HCI_POWER_ON);
+
+	/* Initialise SDP */
+	sdp_parser_init();
+	sdp_parser_register_callback(handle_sdp_client_query_result);
+
+	bt_state = BT_STATE_POWER_ON;
+	bt_timer = -1;
+}
+
+void bt_process(void)
+{
+	if (bt_state != BT_STATE_DORMANT) {
+		run_loop_execute();
+		bt_send_packet(0xffff);
+	}
+
+	if (bt_timer != 0)
+		return;
+
+	switch (bt_state) {
+	case BT_STATE_BNEP_QUERY_WAIT:
+		/* Send a general query for BNEP Protocol ID */
+		log_info("Start SDP BNEP query.");
+		sdp_general_query_for_uuid(remote_addr, BLUETOOTH_PROTOCOL_BNEP);
+
+		bt_state = BT_STATE_BNEP_QUERY;
+		bt_timer = -1;
+		break;
+	default:
+		bt_timer = -1;
+		break;
+	}
+}
+
+int bt_can_send_packet(void)
+{
+	return network_buffer_len == 0;
+}
+
+void bt_send_packet(uint16_t bnep_cid)
+{
+	if (network_buffer_len > 0) {
+		if (network_buffer_cid == 0) {
+			network_buffer_len = 0;
+			btstack_network_packet_sent(network_buffer_cid);
+			return;
+		}
+		/* Check for parked network packets and send it out now */
+		if (bnep_can_send_packet_now(network_buffer_cid)) {
+			uint16_t len = network_buffer_len;
+#ifdef PACKET_DUMP
+			printf("ETH %u => ", len);
+			if (len > 128)
+				len = 128;
+			printf_hexdump(network_buffer, len);
+#endif
+			// この関数はbnep_sendから再帰呼び出しされるので、
+			// bnep_sendを呼び出すより前に送信パケットなし状態にします。
+			network_buffer_len = 0;
+			bnep_send(network_buffer_cid, (uint8_t*)network_buffer, len);
+			btstack_network_packet_sent(network_buffer_cid);
+		}
+	}
+}
+
+void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size)
+{
+#ifdef PACKET_DUMP
+	int len = size;
+	printf("ETH %d <= ", size);
+	if (len > 128)
+		len = 128;
+	printf_hexdump(packet, len);
+#endif
+	btstack_network_process_packet(bnep_cid, packet, size);
+}
+
+void bt_channel_closed(uint16_t bnep_cid)
+{
+	log_info("BNEP channel closed");
+	btstack_network_down(bnep_cid);
+	if ((network_buffer_len > 0) && (network_buffer_cid == bnep_cid)) {
+		network_buffer_len = 0;
+		btstack_network_packet_sent(network_buffer_cid);
+	}
+}
+
+void bt_terminate(void)
+{
+	hci_close();
+
+	bt_state = BT_STATE_DORMANT;
+	bt_timer = -1;
+}
+
+void bt_task_on_start(struct task_if_t *task, ID tskid)
+{
+}
+
+void bt_task_on_end(struct task_if_t *task)
+{
+}
+
+int bt_task_get_timer(struct task_if_t *task)
+{
+	return bt_timer;
+}
+
+void bt_task_progress(struct task_if_t *task, int elapse)
+{
+	if (bt_timer == -1)
+		return;
+
+	bt_timer -= elapse;
+	if (bt_timer < 0)
+		bt_timer = 0;
+}
+
+void bt_task_process(struct task_if_t *task, enum task_event_t event)
+{
+	extern void hal_tick_handler();
+
+	switch (event & ~TASK_EVENT_TICK) {
+	case TASK_EVENT_START:
+		bt_init();
+		break;
+	case TASK_EVENT_TERMINATE:
+		bt_terminate();
+		break;
+	case TASK_EVENT_WAKEUP:
+	case TASK_EVENT_TIMEOUT:
+		if (event & TASK_EVENT_TICK)
+			hal_tick_handler();
+		bt_process();
+		break;
+	}
+}
+
+struct task_if_t bt_task = {
+	bt_task_on_start,
+	bt_task_on_end,
+	bt_task_get_timer,
+	bt_task_progress,
+	bt_task_process,
+};
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/bt_main.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/bt_main.h	(revision 374)
+++ asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/bt_main.h	(revision 374)
@@ -0,0 +1,34 @@
+/*
+ * bt_main.h
+ *
+ */
+#ifndef __BT_MAIN_
+#define __BT_MAIN_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+// エラー返却用定数(-1:0xffff固定)
+#define FAILED_RFCOMM_ID_NOT_SET	0xffff
+
+#define RFCOMM_SERVER_CHANNEL 1
+
+void bt_init(void);
+int bt_can_send_packet(void);
+void bt_send_packet(uint16_t bnep_cid);
+void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
+void bt_channel_closed(uint16_t bnep_cid);
+void bt_terminate(void);
+
+void btstack_network_init(void (*send_packet_callback)(uint16_t bnep_cid, const uint8_t * packet, uint16_t size));
+void btstack_network_up(uint16_t bnep_cid, bd_addr_t local_addr, bd_addr_t remote_addr);
+const char * btstack_network_get_name(uint16_t bnep_cid);
+int btstack_network_down(uint16_t bnep_cid);
+void btstack_network_process_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
+void btstack_network_packet_sent(uint16_t bnep_cid);
+
+#if defined __cplusplus
+}
+#endif
+#endif
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/if_btusb.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/if_btusb.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/if_btusb.c	(revision 374)
@@ -77,5 +77,5 @@
 #include "kernel/kernel_impl.h"
 #include "btstack/utils.h"
-#include "panu_main.h"
+#include "bt_main.h"
 #include "usb_hbth.h"
 //#include "hal_cpu.h"
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/main.c	(revision 374)
@@ -56,5 +56,5 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "usrcmd.h"
 #include "util/ntopt.h"
@@ -186,17 +186,12 @@
 {
 	FILINFO fno;
-#if _USE_LFN
-	char lfn[_MAX_LFN + 1];
+#if FF_USE_LFN
+	char lfn[FF_MAX_LFN + 1];
 	fno.lfname = lfn;
-	fno.lfsize = _MAX_LFN + 1;
+	fno.lfsize = FF_MAX_LFN + 1;
 #endif
 	ER ret;
 
-#ifdef TOPPERS_OMIT_TECS
-	serial_opn_por(SIO_PORTID);
-#endif
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
-
-	ntshell_task_init(uart_read, uart_write, &main_obj);
+	ntshell_task_init(SIO_PORTID);
 
 	main_obj.timer = TMO_FEVR;
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/main.cfg	(revision 374)
@@ -43,4 +43,5 @@
 
 INCLUDE("tecsgen.cfg");
+INCLUDE("mbed_stub.cfg");
 INCLUDE("ffarch.cfg");
 INCLUDE("usb_hbth.cfg");
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/nap_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/nap_main.c	(revision 373)
+++ 	(revision )
@@ -1,447 +1,0 @@
-/*
- * Copyright (C) 2014 BlueKitchen GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- * 4. Any redistribution, use, or modification is done solely for
- *    personal benefit and not for any commercial purpose or for
- *    monetary gain.
- *
- * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
- * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Please inquire about commercial licensing options at
- * contact@bluekitchen-gmbh.com
- *
- */
-
-#include "btstack-config.h"
-
-#include <stdint.h>
-
-#include <btstack/hci_cmds.h>
-#include <btstack/run_loop.h>
-#include <btstack/sdp_util.h>
-
-#include <kernel.h>
-#include "kernel_cfg.h"
-#include "target_syssvc.h"
-
-#include "debug.h"
-#include "hci.h"
-#include "btstack_memory.h"
-#include "hci_dump.h"
-#include "l2cap.h"
-#include "sdp_parser.h"
-#include "sdp_client.h"
-#include "sdp_query_util.h"
-#include "sdp.h"
-#include "pan.h"
-#include "panu_main.h"
-
-extern uint16_t  rfcomm_channel_id;
-
-static int record_id = -1;
-static uint16_t bnep_l2cap_psm = 0;
-static uint32_t bnep_remote_uuid = 0;
-static uint16_t bnep_version = 0;
-static uint16_t bnep_cid = 0;
-static bool_t bnep_do_connect = false;
-
-static uint16_t sdp_bnep_l2cap_psm = 0;
-static uint16_t sdp_bnep_version = 0;
-static uint32_t sdp_bnep_remote_uuid = 0;
-
-extern uint8_t   attribute_value[];
-extern const unsigned int attribute_value_buffer_size;
-
-static bd_addr_t remote_addr;
-
-extern uint8_t   spp_service_buffer[120];
-extern uint8_t   bnep_service_buffer[256];
-
-extern char bt_localname[sizeof(TARGET_NAME"0000")];
-
-/*************** NAP server routines *********************/
-
-char * get_string_from_data_element(uint8_t * element);
-
-/* @section SDP parser callback
-*
-* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
-* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
-*/
-static void handle_sdp_client_record_complete(void)
-{
-	log_info("SDP BNEP Record complete");
-
-	// accept first entry or if we foudn a PANU and only have a NAP yet
-	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BNEP_UUID_PANU && bnep_remote_uuid == BNEP_UUID_NAP)) {
-		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
-		bnep_remote_uuid = sdp_bnep_remote_uuid;
-		bnep_version = sdp_bnep_version;
-	}
-}
-
-/* SDP parser callback */
-static void handle_sdp_client_query_result(sdp_query_event_t *event)
-{
-	sdp_query_attribute_value_event_t *value_event;
-	sdp_query_complete_event_t        *complete_event;
-	des_iterator_t des_list_it;
-	des_iterator_t prot_it;
-	char *str;
-
-	switch (event->type) {
-	case SDP_QUERY_ATTRIBUTE_VALUE:
-		value_event = (sdp_query_attribute_value_event_t*)event;
-
-		// Handle new SDP record
-		if (value_event->record_id != record_id) {
-			handle_sdp_client_record_complete();
-			// next record started
-			record_id = value_event->record_id;
-			log_info("SDP Record: Nr: %d", record_id);
-		}
-
-		if (value_event->attribute_length <= attribute_value_buffer_size) {
-			attribute_value[value_event->data_offset] = value_event->data;
-
-			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
-				//printf("SDP Attribute Data:");
-				//printf_hexdump(attribute_value, value_event->attribute_length);
-
-				switch (value_event->attribute_id) {
-				case SDP_ServiceClassIDList:
-					if (de_get_element_type(attribute_value) != DE_DES) break;
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t * element = des_iterator_get_element(&des_list_it);
-						if (de_get_element_type(element) != DE_UUID) continue;
-						uint32_t uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case BNEP_UUID_PANU:
-						case BNEP_UUID_NAP:
-						case BNEP_UUID_GN:
-							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
-							sdp_bnep_remote_uuid = uuid;
-							break;
-						default:
-							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
-							break;
-						}
-					}
-					break;
-					// 0x0100 "Service Name"
-				case 0x0100:
-					// 0x0101 "Service Description"
-				case 0x0101:
-					str = get_string_from_data_element(attribute_value);
-					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
-					free(str);
-					break;
-				case SDP_ProtocolDescriptorList: {
-					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
-
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t       *des_element;
-						uint8_t       *element;
-						uint32_t       uuid;
-
-						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
-
-						des_element = des_iterator_get_element(&des_list_it);
-						des_iterator_init(&prot_it, des_element);
-						element = des_iterator_get_element(&prot_it);
-
-						if (de_get_element_type(element) != DE_UUID) continue;
-
-						uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case SDP_L2CAPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
-							break;
-						case SDP_BNEPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
-							break;
-						default:
-							log_info("uuid 0x%04x", uuid);
-							break;
-						}
-					}
-					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
-					break;
-				}
-				default:
-					break;
-				}
-			}
-		}
-		else {
-			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
-		}
-		break;
-
-	case SDP_QUERY_COMPLETE:
-		handle_sdp_client_record_complete();
-		complete_event = (sdp_query_complete_event_t*)event;
-		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
-		if (bnep_l2cap_psm) {
-			bnep_do_connect = complete_event->status == 0;
-		}
-		else {
-			log_error("No BNEP service found");
-		}
-		break;
-	}
-}
-
-static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
-{
-	uint8_t   event;
-	bd_addr_t event_addr;
-	uint8_t   rfcomm_channel_nr;
-	uint16_t  uuid_source;
-	uint16_t  uuid_dest;
-	uint16_t  mtu;
-
-	switch (packet_type) {
-	case HCI_EVENT_PACKET:
-		event = packet[0];
-		switch (event) {
-		case BTSTACK_EVENT_STATE:
-			/* BT Stack activated, get started */
-			if (packet[2] == HCI_STATE_WORKING) {
-				hci_send_cmd(&hci_write_local_name, bt_localname);
-			}
-			break;
-
-		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
-			if ((packet[2] == 0) && bnep_do_connect) {
-				bnep_do_connect = false;
-				/* Create BNEP connection */
-				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
-			}
-			break;
-
-		case HCI_EVENT_COMMAND_COMPLETE:
-			if (COMMAND_COMPLETE_EVENT(packet, hci_read_bd_addr)) {
-				bt_flip_addr(event_addr, &packet[6]);
-				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
-
-				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
-				gap_set_local_name(bt_localname);
-				break;
-			}
-			if (COMMAND_COMPLETE_EVENT(packet, hci_write_local_name)) {
-				hci_discoverable_control(1);
-				break;
-			}
-			break;
-
-		case HCI_EVENT_LINK_KEY_REQUEST:
-			// deny link key request
-			log_info("Link key request");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
-			break;
-
-		case HCI_EVENT_PIN_CODE_REQUEST:
-			// inform about pin code request
-			log_info("Pin code request - using '0000'");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
-			break;
-
-		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
-			// inform about user confirmation request
-			log_info("HCI User Confirmation Request with numeric value '%06u'", READ_BT_32(packet, 8));
-			log_info("HCI User Confirmation Auto accept");
-			break;
-
-		case RFCOMM_EVENT_INCOMING_CONNECTION:
-			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
-			bt_flip_addr(event_addr, &packet[2]);
-			rfcomm_channel_nr = packet[8];
-			rfcomm_channel_id = READ_BT_16(packet, 9);
-			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
-			rfcomm_accept_connection_internal(rfcomm_channel_id);
-			break;
-
-		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
-			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
-			if (packet[2]) {
-				log_info("RFCOMM channel open failed, status %u", packet[2]);
-			}
-			else {
-				rfcomm_channel_id = READ_BT_16(packet, 12);
-				mtu = READ_BT_16(packet, 14);
-				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
-			}
-			break;
-
-		case RFCOMM_EVENT_CHANNEL_CLOSED:
-			log_info("RFCOMM channel closed");
-			rfcomm_channel_id = 0;
-			break;
-
-		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
-			if (packet[2]) {
-				log_info("BNEP channel open failed, status %02x", packet[2]);
-			}
-			else {
-				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
-				bnep_cid = READ_BT_16(packet, 3);
-				uuid_source = READ_BT_16(packet, 5);
-				uuid_dest = READ_BT_16(packet, 7);
-				mtu = READ_BT_16(packet, 9);
-				//bt_flip_addr(remote_addr, &packet[11]); 
-				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
-				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
-				/* Setup network interface */
-				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), remote_addr);
-				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
-			}
-			break;
-
-		case BNEP_EVENT_CHANNEL_TIMEOUT:
-			log_info("BNEP channel timeout! Channel will be closed");
-			break;
-
-		case BNEP_EVENT_CHANNEL_CLOSED:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_channel_closed(bnep_cid);
-			break;
-
-		case BNEP_EVENT_READY_TO_SEND:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_send_packet(bnep_cid);
-			break;
-
-		default:
-			break;
-		}
-		break;
-
-	case RFCOMM_DATA_PACKET:
-		// loopback
-		if (rfcomm_channel_id) {
-			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
-			if (err) {
-				log_error("rfcomm_send_internal -> error %d", err);
-			}
-		}
-		break;
-
-	case BNEP_DATA_PACKET:
-		bt_recv_packet(channel, packet, size);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void nap_init(void)
-{
-	const hci_transport_t *transport;
-	bt_control_t       * control;
-	hci_uart_config_t  * config;
-	remote_device_db_t * remote_db;
-	service_record_item_t *spp_service_record_item;
-	service_record_item_t *bnep_service_record_item;
-
-	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
-
-	log_info("bt初期化...");
-
-	// start with BTstack init - especially configure HCI Transport
-	btstack_memory_init();
-	run_loop_init(RUN_LOOP_EMBEDDED);
-
-	/* Initialize HCI */
-	log_info("HCI初期化...");
-	transport = hci_transport_usb_instance();
-	control = NULL;
-	config = NULL;
-	remote_db = (remote_device_db_t *)&remote_device_db_memory;
-	hci_init(transport, config, control, remote_db);
-	hci_set_class_of_device(0x820300/*0x820810*/);
-
-	/* Initialize L2CAP */
-	log_info("L2CAP初期化...");
-	l2cap_init();
-	l2cap_register_packet_handler(packet_handler);
-
-	/* Initialise SDP, create record for SPP and register with SDP */
-	log_info("SDP初期化...");
-	sdp_init();
-
-	/* Initialize RFCOMM */
-	log_info("RFCOMM初期化...");
-	rfcomm_init();
-	rfcomm_register_packet_handler(packet_handler);
-	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
-
-	/* Initialise BNEP */
-	log_info("BNEP初期化...");
-	bnep_init();
-	bnep_register_packet_handler(packet_handler);
-	bnep_register_service(NULL, BNEP_UUID_NAP, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
-
-	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
-	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
-
-	// サービス定義
-	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
-	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
-
-	log_info("SPPサービス登録...");
-	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
-	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
-	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, spp_service_record_item);
-
-	log_info("BNEPサービス登録...");
-	pan_create_nap_service((uint8_t*)&bnep_service_record_item->service_record, "RX NAP", "RX NAP", BNEP_SECURITY_NONE,
-		PAN_NET_ACCESS_TYPE_100MB_ETHERNET, 0x0001312D0/*10Mb/sec*/, NULL, NULL);
-	de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
-	log_info("NAP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, bnep_service_record_item);
-
-	// Secure Simple Pairing configuration -> just works
-	hci_ssp_set_enable(1);
-	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
-	hci_ssp_set_auto_accept(1);
-
-	/* Turn on the device */
-	log_info("HCI電源ON...");
-	hci_power_control(HCI_POWER_ON);
-
-	/* Initialise SDP */
-	sdp_parser_init();
-	sdp_parser_register_callback(handle_sdp_client_query_result);
-}
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/panu_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/panu_main.c	(revision 373)
+++ 	(revision )
@@ -1,595 +1,0 @@
-/*
- * Copyright (C) 2014 BlueKitchen GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- * 4. Any redistribution, use, or modification is done solely for
- *    personal benefit and not for any commercial purpose or for
- *    monetary gain.
- *
- * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
- * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
- * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Please inquire about commercial licensing options at
- * contact@bluekitchen-gmbh.com
- *
- */
-
-#include "btstack-config.h"
-
-#include <stdint.h>
-
-#include <btstack/hci_cmds.h>
-#include <btstack/run_loop.h>
-#include <btstack/sdp_util.h>
-
-#include <kernel.h>
-#include "kernel_cfg.h"
-#include "target_syssvc.h"
-
-#include "debug.h"
-#include "hci.h"
-#include "btstack_memory.h"
-#include "hci_dump.h"
-#include "l2cap.h"
-#include "sdp_parser.h"
-#include "sdp_client.h"
-#include "sdp_query_util.h"
-#include "sdp.h"
-#include "pan.h"
-#include "panu_main.h"
-
-//#define PACKET_DUMP
-
-// エラー返却用定数(-1:0xffff固定)
-#define FAILED_RFCOMM_ID_NOT_SET	0xffff
-
-#define RFCOMM_SERVER_CHANNEL 1
-/*static*/ uint16_t  rfcomm_channel_id = FAILED_RFCOMM_ID_NOT_SET;
-
-static int record_id = -1;
-static uint16_t bnep_l2cap_psm = 0;
-static uint32_t bnep_remote_uuid = 0;
-static uint16_t bnep_version = 0;
-static uint16_t bnep_cid = 0;
-static bool_t bnep_do_connect = false;
-
-static uint16_t sdp_bnep_l2cap_psm = 0;
-static uint16_t sdp_bnep_version = 0;
-static uint32_t sdp_bnep_remote_uuid = 0;
-
-uint8_t   attribute_value[1000];
-const unsigned int attribute_value_buffer_size = sizeof(attribute_value);
-
-extern bd_addr_t remote_addr;
-
-uint8_t   spp_service_buffer[120];
-uint8_t   bnep_service_buffer[256];
-
-char bt_localname[] = TARGET_NAME"0000";
-
-volatile int bt_bnep_mode = 0;
-bool_t bt_enabled = false;
-
-// outgoing network packet
-const uint8_t * network_buffer;
-uint16_t network_buffer_len;
-uint16_t network_buffer_cid;
-
-/*************** PANU client routines *********************/
-
-char * get_string_from_data_element(uint8_t * element) {
-	de_size_t de_size = de_get_size_type(element);
-	int pos = de_get_header_size(element);
-	int len = 0;
-	switch (de_size) {
-	case DE_SIZE_VAR_8:
-		len = element[1];
-		break;
-	case DE_SIZE_VAR_16:
-		len = READ_NET_16(element, 1);
-		break;
-	default:
-		break;
-	}
-	char * str = (char*)malloc(len + 1);
-	memcpy(str, &element[pos], len);
-	str[len] = '\0';
-	return str;
-}
-
-/* @section SDP parser callback
-*
-* @text The SDP parsers retrieves the BNEP PAN UUID as explained in
-* Section [on SDP BNEP Query example](#sec:sdpbnepqueryExample}.
-*/
-static void handle_sdp_client_record_complete(void)
-{
-	log_info("SDP BNEP Record complete");
-
-	// accept first entry or if we foudn a NAP and only have a PANU yet
-	if ((bnep_remote_uuid == 0) || (sdp_bnep_remote_uuid == BNEP_UUID_NAP && bnep_remote_uuid == BNEP_UUID_PANU)) {
-		bnep_l2cap_psm = sdp_bnep_l2cap_psm;
-		bnep_remote_uuid = sdp_bnep_remote_uuid;
-		bnep_version = sdp_bnep_version;
-	}
-}
-
-/* SDP parser callback */
-static void handle_sdp_client_query_result(sdp_query_event_t *event)
-{
-	sdp_query_attribute_value_event_t *value_event;
-	sdp_query_complete_event_t        *complete_event;
-	des_iterator_t des_list_it;
-	des_iterator_t prot_it;
-	char *str;
-
-	switch (event->type) {
-	case SDP_QUERY_ATTRIBUTE_VALUE:
-		value_event = (sdp_query_attribute_value_event_t*)event;
-
-		// Handle new SDP record
-		if (value_event->record_id != record_id) {
-			handle_sdp_client_record_complete();
-			// next record started
-			record_id = value_event->record_id;
-			log_info("SDP Record: Nr: %d", record_id);
-		}
-
-		if (value_event->attribute_length <= attribute_value_buffer_size) {
-			attribute_value[value_event->data_offset] = value_event->data;
-
-			if ((uint16_t)(value_event->data_offset + 1) == value_event->attribute_length) {
-				//printf("SDP Attribute Data:");
-				//printf_hexdump(attribute_value, value_event->attribute_length);
-
-				switch (value_event->attribute_id) {
-				case SDP_ServiceClassIDList:
-					if (de_get_element_type(attribute_value) != DE_DES) break;
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t * element = des_iterator_get_element(&des_list_it);
-						if (de_get_element_type(element) != DE_UUID) continue;
-						uint32_t uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case BNEP_UUID_PANU:
-						case BNEP_UUID_NAP:
-						case BNEP_UUID_GN:
-							log_info("SDP Attribute 0x%04x: BNEP PAN protocol UUID: %04x", value_event->attribute_id, uuid);
-							sdp_bnep_remote_uuid = uuid;
-							break;
-						default:
-							log_info("SDP Attribute 0x%04x: UUID: %04x", value_event->attribute_id, uuid);
-							break;
-						}
-					}
-					break;
-					// 0x0100 "Service Name"
-				case 0x0100:
-					// 0x0101 "Service Description"
-				case 0x0101:
-					str = get_string_from_data_element(attribute_value);
-					log_info("SDP Attribute: 0x%04x: %s", value_event->attribute_id, str);
-					free(str);
-					break;
-				case SDP_ProtocolDescriptorList: {
-					log_info("SDP Attribute: 0x%04x", value_event->attribute_id);
-
-					for (des_iterator_init(&des_list_it, attribute_value); des_iterator_has_more(&des_list_it); des_iterator_next(&des_list_it)) {
-						uint8_t       *des_element;
-						uint8_t       *element;
-						uint32_t       uuid;
-
-						if (des_iterator_get_type(&des_list_it) != DE_DES) continue;
-
-						des_element = des_iterator_get_element(&des_list_it);
-						des_iterator_init(&prot_it, des_element);
-						element = des_iterator_get_element(&prot_it);
-
-						if (de_get_element_type(element) != DE_UUID) continue;
-
-						uuid = de_get_uuid32(element);
-						switch (uuid) {
-						case SDP_L2CAPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_l2cap_psm);
-							break;
-						case SDP_BNEPProtocol:
-							if (!des_iterator_has_more(&prot_it)) continue;
-							des_iterator_next(&prot_it);
-							de_element_get_uint16(des_iterator_get_element(&prot_it), &sdp_bnep_version);
-							break;
-						default:
-							log_info("uuid 0x%04x", uuid);
-							break;
-						}
-					}
-					log_info("Summary: uuid 0x%04x, l2cap_psm 0x%04x, bnep_version 0x%04x", sdp_bnep_remote_uuid, sdp_bnep_l2cap_psm, sdp_bnep_version);
-					break;
-				}
-				default:
-					break;
-				}
-			}
-		}
-		else {
-			log_error("SDP attribute value buffer size exceeded: available %d, required %d", attribute_value_buffer_size, value_event->attribute_length);
-		}
-		break;
-
-	case SDP_QUERY_COMPLETE:
-		handle_sdp_client_record_complete();
-		complete_event = (sdp_query_complete_event_t*)event;
-		log_error("General query done with status %d, bnep psm %04x.", complete_event->status, bnep_l2cap_psm);
-		if (bnep_l2cap_psm) {
-			bnep_do_connect = complete_event->status == 0;
-		}
-		else {
-			log_error("No BNEP service found");
-		}
-		break;
-	}
-}
-
-static void packet_handler(void * connection, uint8_t packet_type, uint16_t channel, uint8_t *packet, uint16_t size)
-{
-	uint8_t   event;
-	bd_addr_t event_addr;
-	uint8_t   rfcomm_channel_nr;
-	uint16_t  uuid_source;
-	uint16_t  uuid_dest;
-	uint16_t  mtu;
-
-	switch (packet_type) {
-	case HCI_EVENT_PACKET:
-		event = packet[0];
-		switch (event) {
-		case BTSTACK_EVENT_STATE:
-			/* BT Stack activated, get started */
-			if (packet[2] == HCI_STATE_WORKING) {
-				hci_send_cmd(&hci_write_local_name, bt_localname);
-				/* Send a general query for BNEP Protocol ID */
-				log_info("Start SDP BNEP query.");
-				sdp_general_query_for_uuid(remote_addr, SDP_BNEPProtocol);
-			}
-			break;
-
-		case BTSTACK_EVENT_NR_CONNECTIONS_CHANGED:
-			if ((packet[2] == 0) && bnep_do_connect) {
-				bnep_do_connect = false;
-				/* Create BNEP connection */
-				bnep_connect(NULL, &remote_addr, bnep_l2cap_psm, bnep_remote_uuid);
-			}
-			break;
-
-		case HCI_EVENT_COMMAND_COMPLETE:
-			if (COMMAND_COMPLETE_EVENT(packet, hci_read_bd_addr)) {
-				bt_flip_addr(event_addr, &packet[6]);
-				log_info("BD-ADDR: %s", bd_addr_to_str(event_addr));
-
-				snprintf(bt_localname, sizeof(bt_localname), TARGET_NAME"%04x", ((event_addr[4] << 8) | event_addr[5]));
-				gap_set_local_name(bt_localname);
-				break;
-			}
-			if (COMMAND_COMPLETE_EVENT(packet, hci_write_local_name)) {
-				hci_discoverable_control(1);
-				break;
-			}
-			break;
-
-		case HCI_EVENT_LINK_KEY_REQUEST:
-			// deny link key request
-			log_info("Link key request");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_link_key_request_negative_reply, &event_addr);
-			break;
-
-		case HCI_EVENT_PIN_CODE_REQUEST:
-			// inform about pin code request
-			log_info("Pin code request - using '0000'");
-			bt_flip_addr(event_addr, &packet[2]);
-			hci_send_cmd(&hci_pin_code_request_reply, &event_addr, 4, "0000");
-			break;
-
-		case HCI_EVENT_USER_CONFIRMATION_REQUEST:
-			// inform about user confirmation request
-			log_info("HCI User Confirmation Request with numeric value '%06u'", READ_BT_32(packet, 8));
-			log_info("HCI User Confirmation Auto accept");
-			break;
-
-		case RFCOMM_EVENT_INCOMING_CONNECTION:
-			// data: event (8), len(8), address(48), channel (8), rfcomm_cid (16)
-			bt_flip_addr(event_addr, &packet[2]);
-			rfcomm_channel_nr = packet[8];
-			rfcomm_channel_id = READ_BT_16(packet, 9);
-			log_info("RFCOMM channel %u requested for %s", rfcomm_channel_nr, bd_addr_to_str(event_addr));
-			rfcomm_accept_connection_internal(rfcomm_channel_id);
-			break;
-
-		case RFCOMM_EVENT_OPEN_CHANNEL_COMPLETE:
-			// data: event(8), len(8), status (8), address (48), server channel(8), rfcomm_cid(16), max frame size(16)
-			if (packet[2]) {
-				log_info("RFCOMM channel open failed, status %u", packet[2]);
-			}
-			else {
-				rfcomm_channel_id = READ_BT_16(packet, 12);
-				mtu = READ_BT_16(packet, 14);
-				log_info("RFCOMM channel open succeeded. New RFCOMM Channel ID %u, max frame size %u", rfcomm_channel_id, mtu);
-			}
-			break;
-
-		case RFCOMM_EVENT_CHANNEL_CLOSED:
-			log_info("RFCOMM channel closed");
-			rfcomm_channel_id = 0;
-			break;
-
-		case BNEP_EVENT_OPEN_CHANNEL_COMPLETE:
-			if (packet[2]) {
-				log_info("BNEP channel open failed, status %02x", packet[2]);
-			}
-			else {
-				// data: event(8), len(8), status (8), bnep source uuid (16), bnep destination uuid (16), remote_address (48)
-				bnep_cid = READ_BT_16(packet, 3);
-				uuid_source = READ_BT_16(packet, 5);
-				uuid_dest = READ_BT_16(packet, 7);
-				mtu = READ_BT_16(packet, 9);
-				//bt_flip_addr(remote_addr, &packet[11]); 
-				memcpy(&remote_addr, &packet[11], sizeof(bd_addr_t));
-				log_info("BNEP connection open succeeded to %s source UUID 0x%04x dest UUID: 0x%04x, max frame size %u", bd_addr_to_str(event_addr), uuid_source, uuid_dest, mtu);
-				/* Setup network interface */
-				btstack_network_up(bnep_cid, (uint8_t *)hci_local_bd_addr(), (uint8_t *)remote_addr);
-				log_info("Network Interface %s activated", btstack_network_get_name(bnep_cid));
-			}
-			break;
-
-		case BNEP_EVENT_CHANNEL_TIMEOUT:
-			log_info("BNEP channel timeout! Channel will be closed");
-			break;
-
-		case BNEP_EVENT_CHANNEL_CLOSED:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_channel_closed(bnep_cid);
-			break;
-
-		case BNEP_EVENT_READY_TO_SEND:
-			bnep_cid = READ_BT_16(packet, 2);
-			bt_send_packet(bnep_cid);
-			break;
-
-		default:
-			break;
-		}
-		break;
-
-	case RFCOMM_DATA_PACKET:
-		// loopback
-		if (rfcomm_channel_id) {
-			int err = rfcomm_send_internal(rfcomm_channel_id, packet, size);
-			if (err) {
-				log_error("rfcomm_send_internal -> error %d", err);
-			}
-		}
-		break;
-
-	case BNEP_DATA_PACKET:
-		bt_recv_packet(channel, packet, size);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/*
- * @section Network packet handler
- *
- * @text A pointer to the network packet is stored and a BNEP_EVENT_CAN_SEND_NOW requested
- */
-
- /* LISTING_START(networkPacketHandler): Network Packet Handler */
-static void network_send_packet_callback(uint16_t bnep_cid, const uint8_t * packet, uint16_t size) {
-	if ((bnep_cid == 0) || (network_buffer_len > 0)) {
-#ifdef PACKET_DUMP
-		int len = size;
-		printf("DROP %04x %d ", bnep_cid, size);
-		if (len > 128)
-			len = 128;
-		printf_hexdump(packet, len);
-#endif
-		if (network_buffer_len > 0) {
-			network_buffer_len = 0;
-			btstack_network_packet_sent(network_buffer_cid);
-		}
-	}
-
-	network_buffer_cid = bnep_cid;
-	network_buffer = packet;
-	network_buffer_len = size;
-}
-
-void panu_init(void)
-{
-	const hci_transport_t *transport;
-	bt_control_t       * control;
-	hci_uart_config_t  * config;
-	remote_device_db_t * remote_db;
-	service_record_item_t *spp_service_record_item;
-	service_record_item_t *bnep_service_record_item;
-
-	//hci_dump_open("", HCI_DUMP_PACKETLOGGER);
-
-	log_info("bt初期化...");
-
-	// start with BTstack init - especially configure HCI Transport
-	btstack_memory_init();
-	run_loop_init(RUN_LOOP_EMBEDDED);
-
-	/* Initialize HCI */
-	log_info("HCI初期化...");
-	transport = hci_transport_usb_instance();
-	control = NULL;
-	config = NULL;
-	remote_db = (remote_device_db_t *)&remote_device_db_memory;
-	hci_init(transport, config, control, remote_db);
-	hci_set_class_of_device(0x820300/*0x820810*/);
-
-	/* Initialize L2CAP */
-	log_info("L2CAP初期化...");
-	l2cap_init();
-	l2cap_register_packet_handler(packet_handler);
-
-	/* Initialise SDP, create record for SPP and register with SDP */
-	log_info("SDP初期化...");
-	sdp_init();
-
-	/* Initialize RFCOMM */
-	log_info("RFCOMM初期化...");
-	rfcomm_init();
-	rfcomm_register_packet_handler(packet_handler);
-	rfcomm_register_service_internal(NULL, RFCOMM_SERVER_CHANNEL, 0xffff);  // reserved channel, mtu=100
-
-	/* Initialise BNEP */
-	log_info("BNEP初期化...");
-	bnep_init();
-	bnep_register_packet_handler(packet_handler);
-	bnep_register_service(NULL, BNEP_UUID_PANU, BNEP_MTU_MIN);  /* Minimum L2CAP MTU for bnep is 1691 bytes */
-
-	memset(spp_service_buffer, 0, sizeof(spp_service_buffer));
-	memset(bnep_service_buffer, 0, sizeof(bnep_service_buffer));
-
-	// サービス定義
-	spp_service_record_item = (service_record_item_t *)spp_service_buffer;
-	bnep_service_record_item = (service_record_item_t *)bnep_service_buffer;
-
-	log_info("SPPサービス登録...");
-	sdp_create_spp_service((uint8_t*)&spp_service_record_item->service_record, 1, "RX SPP");
-	de_dump_data_element((uint8_t*)spp_service_record_item->service_record);
-	log_info("SSP SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)spp_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, spp_service_record_item);
-
-	log_info("BNEPサービス登録...");
-	pan_create_panu_service((uint8_t*)&bnep_service_record_item->service_record, "RX PANU", "RX PANU", BNEP_SECURITY_NONE);
-	de_dump_data_element((uint8_t*)bnep_service_record_item->service_record);
-	log_info("PANU SDP service buffer size: %u", (uint16_t)(sizeof(service_record_item_t) + de_get_len((uint8_t*)bnep_service_record_item->service_record)));
-	sdp_register_service_internal(NULL, bnep_service_record_item);
-
-	// Secure Simple Pairing configuration -> just works
-	hci_ssp_set_enable(1);
-	hci_ssp_set_io_capability(SSP_IO_CAPABILITY_NO_INPUT_NO_OUTPUT);
-	hci_ssp_set_auto_accept(1);
-
-	/* Turn on the device */
-	log_info("HCI電源ON...");
-	hci_power_control(HCI_POWER_ON);
-
-	/* Initialise SDP */
-	sdp_parser_init();
-	sdp_parser_register_callback(handle_sdp_client_query_result);
-}
-
-void nap_init(void);
-
-void bt_init(void)
-{
-	btstack_network_init(&network_send_packet_callback);
-
-	if (bt_bnep_mode == 0) {
-		panu_init();
-	}
-	else {
-		nap_init();
-	}
-
-	bt_enabled = true;
-}
-
-void bt_task(void)
-{
-	extern void hal_tick_handler();
-
-	if (bt_enabled) {
-		hal_tick_handler();
-		run_loop_execute();
-		bt_send_packet(0xffff);
-	}
-}
-
-int bt_can_send_packet(void)
-{
-	return network_buffer_len == 0;
-}
-
-void bt_send_packet(uint16_t bnep_cid)
-{
-	if (network_buffer_len > 0) {
-		if (network_buffer_cid == 0) {
-			network_buffer_len = 0;
-			btstack_network_packet_sent(network_buffer_cid);
-			return;
-		}
-		/* Check for parked network packets and send it out now */
-		if (bnep_can_send_packet_now(network_buffer_cid)) {
-			uint16_t len = network_buffer_len;
-#ifdef PACKET_DUMP
-			printf("ETH %u => ", len);
-			if (len > 128)
-				len = 128;
-			printf_hexdump(network_buffer, len);
-#endif
-			// この関数はbnep_sendから再帰呼び出しされるので、
-			// bnep_sendを呼び出すより前に送信パケットなし状態にします。
-			network_buffer_len = 0;
-			bnep_send(network_buffer_cid, (uint8_t*)network_buffer, len);
-			btstack_network_packet_sent(network_buffer_cid);
-		}
-	}
-}
-
-void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size)
-{
-#ifdef PACKET_DUMP
-	int len = size;
-	printf("ETH %d <= ", size);
-	if (len > 128)
-		len = 128;
-	printf_hexdump(packet, len);
-#endif
-	btstack_network_process_packet(bnep_cid, packet, size);
-}
-
-void bt_channel_closed(uint16_t bnep_cid)
-{
-	log_info("BNEP channel closed");
-	btstack_network_down(bnep_cid);
-	if ((network_buffer_len > 0) && (network_buffer_cid == bnep_cid)) {
-		network_buffer_len = 0;
-		btstack_network_packet_sent(network_buffer_cid);
-	}
-}
-
-void bt_terminate(void)
-{
-	hci_close();
-
-	bt_enabled = false;
-}
Index: asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/panu_main.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/bnep_bridge/src/panu_main.h	(revision 373)
+++ 	(revision )
@@ -1,35 +1,0 @@
-/*
- * panu_main.h
- *
- */
-#ifndef __BT_MAIN_
-#define __BT_MAIN_
-
-#if defined __cplusplus
-extern "C" {
-#endif
-
-// エラー返却用定数(-1:0xffff固定)
-#define FAILED_RFCOMM_ID_NOT_SET	0xffff
-
-#define RFCOMM_SERVER_CHANNEL 1
-
-void bt_init(void);
-void bt_task(void);
-int bt_can_send_packet(void);
-void bt_send_packet(uint16_t bnep_cid);
-void bt_recv_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
-void bt_channel_closed(uint16_t bnep_cid);
-void bt_terminate(void);
-
-void btstack_network_init(void (*send_packet_callback)(uint16_t bnep_cid, const uint8_t * packet, uint16_t size));
-void btstack_network_up(uint16_t bnep_cid, bd_addr_t local_addr, bd_addr_t remote_addr);
-const char * btstack_network_get_name(uint16_t bnep_cid);
-int btstack_network_down(uint16_t bnep_cid);
-void btstack_network_process_packet(uint16_t bnep_cid, const uint8_t * packet, uint16_t size);
-void btstack_network_packet_sent(uint16_t bnep_cid);
-
-#if defined __cplusplus
-}
-#endif
-#endif
Index: asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/hci_cmds.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/hci_cmds.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/hci_cmds.h	(revision 374)
@@ -404,5 +404,5 @@
  * @param status
  */
-#define SDP_QUERY_COMPLETE                                 0x91
+#define SDP_EVENT_QUERY_COMPLETE                           0x91
 
 // data: event(8), len(8), rfcomm channel(8), name(var)
@@ -422,5 +422,5 @@
  * @param attribute_value
  */
-#define SDP_QUERY_ATTRIBUTE_VALUE                          0x93
+#define SDP_EVENT_QUERY_ATTRIBUTE_VALUE                          0x93
 
 // not provided by daemon, only used for internal testing
Index: asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/sdp_util.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/sdp_util.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/sdp_util.h	(revision 374)
@@ -68,8 +68,8 @@
 // UNIVERSAL ATTRIBUTE DEFINITIONS
 #define SDP_ServiceRecordHandle     0x0000
-#define SDP_ServiceClassIDList      0x0001
+#define BLUETOOTH_ATTRIBUTE_SERVICE_CLASS_ID_LIST      0x0001
 #define SDP_ServiceRecordState      0x0002
 #define SDP_ServiceID               0x0003
-#define SDP_ProtocolDescriptorList  0x0004
+#define BLUETOOTH_ATTRIBUTE_PROTOCOL_DESCRIPTOR_LIST  0x0004
 #define SDP_BrowseGroupList		    0x0005
 #define SDP_LanguageBaseAttributeIDList 0x0006
@@ -93,6 +93,6 @@
 #define SDP_RFCOMMProtocol    0x0003
 #define SDP_OBEXProtocol      0x0008
-#define SDP_L2CAPProtocol     0x0100
-#define SDP_BNEPProtocol      0x000f
+#define BLUETOOTH_PROTOCOL_L2CAP     0x0100
+#define BLUETOOTH_PROTOCOL_BNEP      0x000f
 
 // OFFSETS FOR LOCALIZED ATTRIBUTES - SDP_LanguageBaseAttributeIDList
Index: asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/utils.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/utils.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/include/btstack/utils.h	(revision 374)
@@ -90,11 +90,11 @@
 
 // helper for BT little endian format
-#define READ_BT_16( buffer, pos) ( ((uint16_t) buffer[pos]) | (((uint16_t)buffer[pos+1]) << 8))
-#define READ_BT_24( buffer, pos) ( ((uint32_t) buffer[pos]) | (((uint32_t)buffer[pos+1]) << 8) | (((uint32_t)buffer[pos+2]) << 16))
-#define READ_BT_32( buffer, pos) ( ((uint32_t) buffer[pos]) | (((uint32_t)buffer[pos+1]) << 8) | (((uint32_t)buffer[pos+2]) << 16) | (((uint32_t) buffer[pos+3])) << 24)
+#define little_endian_read_16( buffer, pos) ( ((uint16_t) buffer[pos]) | (((uint16_t)buffer[pos+1]) << 8))
+#define little_endian_read_24( buffer, pos) ( ((uint32_t) buffer[pos]) | (((uint32_t)buffer[pos+1]) << 8) | (((uint32_t)buffer[pos+2]) << 16))
+#define little_endian_read_32( buffer, pos) ( ((uint32_t) buffer[pos]) | (((uint32_t)buffer[pos+1]) << 8) | (((uint32_t)buffer[pos+2]) << 16) | (((uint32_t) buffer[pos+3])) << 24)
 
 // helper for SDP big endian format
-#define READ_NET_16( buffer, pos) ( ((uint16_t) buffer[pos+1]) | (((uint16_t)buffer[pos  ]) << 8))
-#define READ_NET_32( buffer, pos) ( ((uint32_t) buffer[pos+3]) | (((uint32_t)buffer[pos+2]) << 8) | (((uint32_t)buffer[pos+1]) << 16) | (((uint32_t) buffer[pos])) << 24)
+#define big_endian_read_16( buffer, pos) ( ((uint16_t) buffer[pos+1]) | (((uint16_t)buffer[pos  ]) << 8))
+#define big_endian_read_32( buffer, pos) ( ((uint32_t) buffer[pos+3]) | (((uint32_t)buffer[pos+2]) << 8) | (((uint32_t)buffer[pos+1]) << 16) | (((uint32_t) buffer[pos])) << 24)
 
 // HCI CMD OGF/OCF
@@ -103,6 +103,6 @@
 
 // check if command complete event for given command
-#define COMMAND_COMPLETE_EVENT(event,cmd) ( event[0] == HCI_EVENT_COMMAND_COMPLETE && READ_BT_16(event,3) == cmd.opcode)
-#define COMMAND_STATUS_EVENT(event,cmd) ( event[0] == HCI_EVENT_COMMAND_STATUS && READ_BT_16(event,4) == cmd.opcode)
+#define HCI_EVENT_IS_COMMAND_COMPLETE(event,cmd) ( event[0] == HCI_EVENT_COMMAND_COMPLETE && little_endian_read_16(event,3) == cmd.opcode)
+#define COMMAND_STATUS_EVENT(event,cmd) ( event[0] == HCI_EVENT_COMMAND_STATUS && little_endian_read_16(event,4) == cmd.opcode)
 
 // Code+Len=2, Pkts+Opcode=3; total=5
@@ -110,15 +110,15 @@
 
 // ACL Packet
-#define READ_ACL_CONNECTION_HANDLE( buffer ) ( READ_BT_16(buffer,0) & 0x0fff)
+#define READ_ACL_CONNECTION_HANDLE( buffer ) ( little_endian_read_16(buffer,0) & 0x0fff)
 #define READ_ACL_FLAGS( buffer )      ( buffer[1] >> 4 )
-#define READ_ACL_LENGTH( buffer )     (READ_BT_16(buffer, 2))
+#define READ_ACL_LENGTH( buffer )     (little_endian_read_16(buffer, 2))
 
 // L2CAP Packet
-#define READ_L2CAP_LENGTH(buffer)     ( READ_BT_16(buffer, 4))
-#define READ_L2CAP_CHANNEL_ID(buffer) ( READ_BT_16(buffer, 6))
+#define READ_L2CAP_LENGTH(buffer)     ( little_endian_read_16(buffer, 4))
+#define READ_L2CAP_CHANNEL_ID(buffer) ( little_endian_read_16(buffer, 6))
 
-void bt_store_16(uint8_t *buffer, uint16_t pos, uint16_t value);
-void bt_store_32(uint8_t *buffer, uint16_t pos, uint32_t value);
-void bt_flip_addr(bd_addr_t dest, bd_addr_t src);
+void little_endian_store_16(uint8_t *buffer, uint16_t pos, uint16_t value);
+void little_endian_store_32(uint8_t *buffer, uint16_t pos, uint32_t value);
+void reverse_bd_addr(bd_addr_t src, bd_addr_t dest);
 
 void net_store_16(uint8_t *buffer, uint16_t pos, uint16_t value);
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/bnep.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/bnep.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/bnep.c	(revision 374)
@@ -84,8 +84,8 @@
     event[1] = sizeof(event) - 2;
     event[2] = status;
-    bt_store_16(event, 3, channel->l2cap_cid);
-    bt_store_16(event, 5, channel->uuid_source);
-    bt_store_16(event, 7, channel->uuid_dest);
-    bt_store_16(event, 9, channel->max_frame_size);
+    little_endian_store_16(event, 3, channel->l2cap_cid);
+    little_endian_store_16(event, 5, channel->uuid_source);
+    little_endian_store_16(event, 7, channel->uuid_dest);
+    little_endian_store_16(event, 9, channel->max_frame_size);
     BD_ADDR_COPY(&event[11], channel->remote_addr);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -101,7 +101,7 @@
     event[0] = BNEP_EVENT_CHANNEL_TIMEOUT;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->l2cap_cid);
-    bt_store_16(event, 4, channel->uuid_source);
-    bt_store_16(event, 6, channel->uuid_dest);
+    little_endian_store_16(event, 2, channel->l2cap_cid);
+    little_endian_store_16(event, 4, channel->uuid_source);
+    little_endian_store_16(event, 6, channel->uuid_dest);
     BD_ADDR_COPY(&event[8], channel->remote_addr);
     event[14] = channel->state;
@@ -118,7 +118,7 @@
     event[0] = BNEP_EVENT_CHANNEL_CLOSED;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->l2cap_cid);
-    bt_store_16(event, 4, channel->uuid_source);
-    bt_store_16(event, 6, channel->uuid_dest);
+    little_endian_store_16(event, 2, channel->l2cap_cid);
+    little_endian_store_16(event, 4, channel->uuid_source);
+    little_endian_store_16(event, 6, channel->uuid_dest);
     BD_ADDR_COPY(&event[8], channel->remote_addr);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -133,5 +133,5 @@
     event[0] = BNEP_EVENT_READY_TO_SEND;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->l2cap_cid);
+    little_endian_store_16(event, 2, channel->l2cap_cid);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
 	(*app_packet_handler)(channel->connection, HCI_EVENT_PACKET, 0, (uint8_t *) event, sizeof(event));
@@ -464,5 +464,5 @@
     BD_ADDR_COPY(addr_source, &packet[pos]);
     pos += sizeof(bd_addr_t);
-    network_protocol_type = READ_NET_16(packet, pos);
+    network_protocol_type = big_endian_read_16(packet, pos);
     pos += sizeof(uint16_t);
 
@@ -475,5 +475,5 @@
         }
         /* The "real" network protocol type is 4 bytes ahead in a VLAN packet */
-		network_protocol_type = READ_NET_16(packet, pos + 2);
+		network_protocol_type = big_endian_read_16(packet, pos + 2);
 	}
 
@@ -808,16 +808,16 @@
     /* Check source and destination UUIDs for valid combinations */
     if (response_code == BNEP_RESP_SETUP_SUCCESS) {
-        channel->uuid_dest = READ_NET_16(packet, 2 + uuid_offset);
-        channel->uuid_source = READ_NET_16(packet, 2 + uuid_offset + uuid_size);
-
-        if ((channel->uuid_dest != BNEP_UUID_PANU) &&
-            (channel->uuid_dest != BNEP_UUID_NAP) &&
-            (channel->uuid_dest != BNEP_UUID_GN)) {
+        channel->uuid_dest = big_endian_read_16(packet, 2 + uuid_offset);
+        channel->uuid_source = big_endian_read_16(packet, 2 + uuid_offset + uuid_size);
+
+        if ((channel->uuid_dest != BLUETOOTH_SERVICE_CLASS_PANU) &&
+            (channel->uuid_dest != BLUETOOTH_SERVICE_CLASS_NAP) &&
+            (channel->uuid_dest != BLUETOOTH_SERVICE_CLASS_GN)) {
             log_error("BNEP_CONNECTION_REQUEST: Invalid destination service UUID: %04x", channel->uuid_dest);
             channel->uuid_dest = 0;
         }
-        if ((channel->uuid_source != BNEP_UUID_PANU) &&
-            (channel->uuid_source != BNEP_UUID_NAP) &&
-            (channel->uuid_source != BNEP_UUID_GN)) {
+        if ((channel->uuid_source != BLUETOOTH_SERVICE_CLASS_PANU) &&
+            (channel->uuid_source != BLUETOOTH_SERVICE_CLASS_NAP) &&
+            (channel->uuid_source != BLUETOOTH_SERVICE_CLASS_GN)) {
             log_error("BNEP_CONNECTION_REQUEST: Invalid source service UUID: %04x", channel->uuid_source);
             channel->uuid_source = 0;
@@ -829,5 +829,5 @@
             response_code = BNEP_RESP_SETUP_INVALID_DEST_UUID;
         } else
-        if ((channel->uuid_source != BNEP_UUID_PANU) && (channel->uuid_dest != BNEP_UUID_PANU)) {
+        if ((channel->uuid_source != BLUETOOTH_SERVICE_CLASS_PANU) && (channel->uuid_dest != BLUETOOTH_SERVICE_CLASS_PANU)) {
             response_code = BNEP_RESP_SETUP_INVALID_SOURCE_UUID;
         }
@@ -857,5 +857,5 @@
     }
 
-    response_code = READ_NET_16(packet, 1);
+    response_code = big_endian_read_16(packet, 1);
 
     if (response_code == BNEP_RESP_SETUP_SUCCESS) {
@@ -882,5 +882,5 @@
     }
 
-    list_length = READ_NET_16(packet, 1);
+    list_length = big_endian_read_16(packet, 1);
     /* Sanity check packet size again with known package size */
     if (size < 3 + list_length) {
@@ -903,6 +903,6 @@
         /* There is still enough space, copy the filters to our filter list */
         for (i = 0; i < list_length / (2 * 2); i ++) {
-            channel->net_filter[channel->net_filter_count].range_start = READ_NET_16(packet, 1 + 2 + i * 4);
-            channel->net_filter[channel->net_filter_count].range_end = READ_NET_16(packet, 1 + 2 + i * 4 + 2);
+            channel->net_filter[channel->net_filter_count].range_start = big_endian_read_16(packet, 1 + 2 + i * 4);
+            channel->net_filter[channel->net_filter_count].range_end = big_endian_read_16(packet, 1 + 2 + i * 4 + 2);
             if (channel->net_filter[channel->net_filter_count].range_start > channel->net_filter[channel->net_filter_count].range_end) {
                 /* Invalid filter range, ignore this filter rule */
@@ -945,5 +945,5 @@
     }
 
-    response_code = READ_NET_16(packet, 1);
+    response_code = big_endian_read_16(packet, 1);
 
     if (response_code == BNEP_RESP_FILTER_SUCCESS) {
@@ -966,5 +966,5 @@
     }
 
-    list_length = READ_NET_16(packet, 1);
+    list_length = big_endian_read_16(packet, 1);
     /* Sanity check packet size again with known package size */
     if (size < 3 + list_length) {
@@ -1032,5 +1032,5 @@
     }
 
-    response_code = READ_NET_16(packet, 1);
+    response_code = big_endian_read_16(packet, 1);
 
     if (response_code == BNEP_RESP_FILTER_SUCCESS) {
@@ -1169,8 +1169,8 @@
         case L2CAP_EVENT_INCOMING_CONNECTION:
             /* L2CAP event data: event(8), len(8), address(48), handle (16),  psm (16), source cid(16) dest cid(16) */
-            bt_flip_addr(event_addr, &packet[2]);
-            con_handle = READ_BT_16(packet,  8);
-            psm        = READ_BT_16(packet, 10);
-            l2cap_cid  = READ_BT_16(packet, 12);
+            reverse_bd_addr(&packet[2], event_addr);
+            con_handle = little_endian_read_16(packet,  8);
+            psm        = little_endian_read_16(packet, 10);
+            l2cap_cid  = little_endian_read_16(packet, 12);
 
             if (psm != PSM_BNEP) break;
@@ -1211,5 +1211,5 @@
         case L2CAP_EVENT_CHANNEL_OPENED:
             /* Check if the l2cap channel has been opened for PSM_BNEP */
-            if (READ_BT_16(packet, 11) != PSM_BNEP) {
+            if (little_endian_read_16(packet, 11) != PSM_BNEP) {
                 break;
             }
@@ -1219,7 +1219,7 @@
 
             /* Get the bnep channel fpr remote address */
-            con_handle = READ_BT_16(packet, 9);
-            l2cap_cid  = READ_BT_16(packet, 13);
-            bt_flip_addr(event_addr, &packet[3]);
+            con_handle = little_endian_read_16(packet, 9);
+            l2cap_cid  = little_endian_read_16(packet, 13);
+            reverse_bd_addr(&packet[3], event_addr);
             channel = bnep_channel_for_addr(&event_addr);
             if (!channel) {
@@ -1252,10 +1252,10 @@
                     channel->state = BNEP_CHANNEL_STATE_WAIT_FOR_CONNECTION_RESPONSE;
                     bnep_channel_state_add(channel, BNEP_CHANNEL_STATE_VAR_SND_CONNECTION_REQUEST);
-                    channel->max_frame_size = bnep_max_frame_size_for_l2cap_mtu(READ_BT_16(packet, 17));
+                    channel->max_frame_size = bnep_max_frame_size_for_l2cap_mtu(little_endian_read_16(packet, 17));
                     bnep_run();
                     break;
                 case BNEP_CHANNEL_STATE_WAIT_FOR_CONNECTION_REQUEST:
                     /* New information: channel mtu */
-                    channel->max_frame_size = bnep_max_frame_size_for_l2cap_mtu(READ_BT_16(packet, 17));
+                    channel->max_frame_size = bnep_max_frame_size_for_l2cap_mtu(little_endian_read_16(packet, 17));
                     break;
                 default:
@@ -1272,5 +1272,5 @@
         case L2CAP_EVENT_CHANNEL_CLOSED:
             // data: event (8), len(8), channel (16)
-            l2cap_cid   = READ_BT_16(packet, 2);
+            l2cap_cid   = little_endian_read_16(packet, 2);
             channel = bnep_channel_for_l2cap_cid(l2cap_cid);
             log_info("L2CAP_EVENT_CHANNEL_CLOSED cid 0x%0x, channel %p", l2cap_cid, channel);
@@ -1331,5 +1331,5 @@
             BD_ADDR_COPY(addr_source, &packet[pos]);
             pos += sizeof(bd_addr_t);
-            network_protocol_type = READ_NET_16(packet, pos);
+            network_protocol_type = big_endian_read_16(packet, pos);
             pos += 2;
             break;
@@ -1337,5 +1337,5 @@
             BD_ADDR_COPY(addr_dest, channel->local_addr);
             BD_ADDR_COPY(addr_source, channel->remote_addr);
-            network_protocol_type = READ_NET_16(packet, pos);
+            network_protocol_type = big_endian_read_16(packet, pos);
             pos += 2;
             break;
@@ -1344,5 +1344,5 @@
             BD_ADDR_COPY(addr_source, &packet[pos]);
             pos += sizeof(bd_addr_t);
-            network_protocol_type = READ_NET_16(packet, pos);
+            network_protocol_type = big_endian_read_16(packet, pos);
             pos += 2;
             break;
@@ -1351,5 +1351,5 @@
             pos += sizeof(bd_addr_t);
             BD_ADDR_COPY(addr_source, channel->remote_addr);
-            network_protocol_type = READ_NET_16(packet, pos);
+            network_protocol_type = big_endian_read_16(packet, pos);
             pos += 2;
             break;
@@ -1563,5 +1563,5 @@
     }
 
-    channel->uuid_source = BNEP_UUID_PANU;
+    channel->uuid_source = BLUETOOTH_SERVICE_CLASS_PANU;
     channel->uuid_dest   = uuid_dest;
 
@@ -1597,7 +1597,7 @@
 
     /* Only alow one the three service types: PANU, NAP, GN */
-    if ((service_uuid != BNEP_UUID_PANU) &&
-        (service_uuid != BNEP_UUID_NAP) &&
-        (service_uuid != BNEP_UUID_GN)) {
+    if ((service_uuid != BLUETOOTH_SERVICE_CLASS_PANU) &&
+        (service_uuid != BLUETOOTH_SERVICE_CLASS_NAP) &&
+        (service_uuid != BLUETOOTH_SERVICE_CLASS_GN)) {
         log_info("BNEP_REGISTER_SERVICE: Invalid service UUID: %04x", service_uuid);
         return BNEP_CHANNEL_NOT_CONNECTED;
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/bnep.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/bnep.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/bnep.h	(revision 374)
@@ -72,7 +72,7 @@
 
 /* BNEP UUIDs */
-#define BNEP_UUID_PANU                                  0x1115
-#define BNEP_UUID_NAP                                   0x1116
-#define BNEP_UUID_GN                                    0x1117
+#define BLUETOOTH_SERVICE_CLASS_PANU                                  0x1115
+#define BLUETOOTH_SERVICE_CLASS_NAP                                   0x1116
+#define BLUETOOTH_SERVICE_CLASS_GN                                    0x1117
     
 /* BNEP packet types */    
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/hci.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/hci.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/hci.c	(revision 374)
@@ -233,5 +233,5 @@
     bd_addr_t addr;
     hci_connection_t * conn;
-    bt_flip_addr(addr, *(bd_addr_t *) bd_addr);
+    reverse_bd_addr(*(bd_addr_t *) bd_addr, addr);
     conn = hci_connection_for_bd_addr_and_type(&addr, BD_ADDR_TYPE_CLASSIC);
     if (conn) {
@@ -469,11 +469,11 @@
         // copy handle_and_flags if not first fragment and update packet boundary flags to be 01 (continuing fragmnent)
         if (acl_header_pos > 0){
-            uint16_t handle_and_flags = READ_BT_16(hci_stack->hci_packet_buffer, 0);
+            uint16_t handle_and_flags = little_endian_read_16(hci_stack->hci_packet_buffer, 0);
             handle_and_flags = (handle_and_flags & 0xcfff) | (1 << 12);
-            bt_store_16(hci_stack->hci_packet_buffer, acl_header_pos, handle_and_flags);
+            little_endian_store_16(hci_stack->hci_packet_buffer, acl_header_pos, handle_and_flags);
         }
 
         // update header len
-        bt_store_16(hci_stack->hci_packet_buffer, acl_header_pos + 2, current_acl_data_packet_length);
+        little_endian_store_16(hci_stack->hci_packet_buffer, acl_header_pos + 2, current_acl_data_packet_length);
 
         // count packet
@@ -640,5 +640,5 @@
                 conn->acl_recombination_pos    = acl_length + 4;
                 conn->acl_recombination_length = l2cap_length;
-                bt_store_16(conn->acl_recombination_buffer, HCI_INCOMING_PRE_BUFFER_SIZE + 2, l2cap_length +4);
+                little_endian_store_16(conn->acl_recombination_buffer, HCI_INCOMING_PRE_BUFFER_SIZE + 2, l2cap_length +4);
             }
             break;
@@ -793,5 +793,5 @@
     // odd: waiting for event
     if (packet[0] == HCI_EVENT_COMMAND_COMPLETE){
-        uint16_t opcode = READ_BT_16(packet,3);
+        uint16_t opcode = little_endian_read_16(packet,3);
         if (opcode == hci_stack->last_cmd_opcode){
             command_completed = 1;
@@ -803,5 +803,5 @@
     if (packet[0] == HCI_EVENT_COMMAND_STATUS){
         uint8_t  status = packet[2];
-        uint16_t opcode = READ_BT_16(packet,4);
+        uint16_t opcode = little_endian_read_16(packet,4);
         if (opcode == hci_stack->last_cmd_opcode){
             if (status){
@@ -843,5 +843,5 @@
         case 1: // SEND BAUD CHANGE
             hci_stack->control->baudrate_cmd(hci_stack->config, ((hci_uart_config_t *)hci_stack->config)->baudrate_main, hci_stack->hci_packet_buffer);
-            hci_stack->last_cmd_opcode = READ_BT_16(hci_stack->hci_packet_buffer, 0);
+            hci_stack->last_cmd_opcode = little_endian_read_16(hci_stack->hci_packet_buffer, 0);
             hci_dump_packet(HCI_COMMAND_DATA_PACKET, 0, hci_stack->hci_packet_buffer, 3 + hci_stack->hci_packet_buffer[2]);
             hci_send_cmd_packet(hci_stack->hci_packet_buffer, 3 + hci_stack->hci_packet_buffer[2]);
@@ -860,5 +860,5 @@
                 if (valid_cmd){
                     int size = 3 + hci_stack->hci_packet_buffer[2];
-                    hci_stack->last_cmd_opcode = READ_BT_16(hci_stack->hci_packet_buffer, 0);
+                    hci_stack->last_cmd_opcode = little_endian_read_16(hci_stack->hci_packet_buffer, 0);
                     hci_dump_packet(HCI_COMMAND_DATA_PACKET, 0, hci_stack->hci_packet_buffer, size);
                     hci_stack->hci_transport->send_packet(HCI_COMMAND_DATA_PACKET, hci_stack->hci_packet_buffer, size);
@@ -992,9 +992,9 @@
             hci_stack->num_cmd_packets = packet[2];
 
-            if (COMMAND_COMPLETE_EVENT(packet, hci_read_buffer_size)){
+            if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_read_buffer_size)){
                 // from offset 5
                 // status
                 // "The HC_ACL_Data_Packet_Length return parameter will be used to determine the size of the L2CAP segments contained in ACL Data Packets"
-                hci_stack->acl_data_packet_length = READ_BT_16(packet, 6);
+                hci_stack->acl_data_packet_length = little_endian_read_16(packet, 6);
                 // ignore: SCO data packet len (8)
                 hci_stack->acl_packets_total_num  = packet[9];
@@ -1010,6 +1010,6 @@
             }
 #ifdef HAVE_BLE
-            if (COMMAND_COMPLETE_EVENT(packet, hci_le_read_buffer_size)){
-                hci_stack->le_data_packets_length = READ_BT_16(packet, 6);
+            if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_le_read_buffer_size)){
+                hci_stack->le_data_packets_length = little_endian_read_16(packet, 6);
                 hci_stack->le_acl_packets_total_num  = packet[8];
                     // determine usable ACL payload size
@@ -1021,14 +1021,14 @@
 #endif
             // Dump local address
-            if (COMMAND_COMPLETE_EVENT(packet, hci_read_bd_addr)) {
-                bt_flip_addr(hci_stack->local_bd_addr, &packet[OFFSET_OF_DATA_IN_COMMAND_COMPLETE + 1]);
+            if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_read_bd_addr)) {
+                reverse_bd_addr(&packet[OFFSET_OF_DATA_IN_COMMAND_COMPLETE + 1], hci_stack->local_bd_addr);
                 log_info("Local Address, Status: 0x%02x: Addr: %s",
                     packet[OFFSET_OF_DATA_IN_COMMAND_COMPLETE], bd_addr_to_str(hci_stack->local_bd_addr));
             }
-            if (COMMAND_COMPLETE_EVENT(packet, hci_write_scan_enable)){
+            if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_write_scan_enable)){
                 hci_emit_discoverable_enabled(hci_stack->discoverable);
             }
             // Note: HCI init checks
-            if (COMMAND_COMPLETE_EVENT(packet, hci_read_local_supported_features)){
+            if (HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_read_local_supported_features)){
                 memcpy(hci_stack->local_supported_features, &packet[OFFSET_OF_DATA_IN_COMMAND_COMPLETE+1], 8);
                 log_info("Local Supported Features: 0x%02x%02x%02x%02x%02x%02x%02x%02x",
@@ -1057,7 +1057,7 @@
             for (i=0; i<packet[2];i++){
                 uint16_t num_packets;
-                handle = READ_BT_16(packet, offset);
+                handle = little_endian_read_16(packet, offset);
                 offset += 2;
-                num_packets = READ_BT_16(packet, offset);
+                num_packets = little_endian_read_16(packet, offset);
                 offset += 2;
 
@@ -1079,5 +1079,5 @@
         }
         case HCI_EVENT_CONNECTION_REQUEST:
-            bt_flip_addr(addr, &packet[2]);
+            reverse_bd_addr(&packet[2], addr);
             // TODO: eval COD 8-10
             link_type = packet[11];
@@ -1106,5 +1106,5 @@
         case HCI_EVENT_CONNECTION_COMPLETE:
             // Connection management
-            bt_flip_addr(addr, &packet[5]);
+            reverse_bd_addr(&packet[5], addr);
             log_info("Connection_complete (status=%u) %s", packet[2], bd_addr_to_str(addr));
             addr_type = BD_ADDR_TYPE_CLASSIC;
@@ -1113,5 +1113,5 @@
                 if (!packet[2]){
                     conn->state = OPEN;
-                    conn->con_handle = READ_BT_16(packet, 3);
+                    conn->con_handle = little_endian_read_16(packet, 3);
                     conn->bonding_flags |= BONDING_REQUEST_REMOTE_FEATURES;
 
@@ -1148,5 +1148,5 @@
 
         case HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE:
-            handle = READ_BT_16(packet, 3);
+            handle = little_endian_read_16(packet, 3);
             conn = hci_connection_for_handle(handle);
             if (!conn) break;
@@ -1176,5 +1176,5 @@
         case HCI_EVENT_LINK_KEY_NOTIFICATION: {
             link_key_type_t link_key_type;
-            bt_flip_addr(addr, &packet[2]);
+            reverse_bd_addr(&packet[2], addr);
             conn = hci_connection_for_bd_addr_and_type(&addr, BD_ADDR_TYPE_CLASSIC);
             if (!conn) break;
@@ -1201,5 +1201,5 @@
             // PIN CODE REQUEST means the link key request didn't succee -> delete stored link key
             if (!hci_stack->remote_device_db) break;
-            bt_flip_addr(addr, &packet[2]);
+            reverse_bd_addr(&packet[2], addr);
             hci_stack->remote_device_db->delete_link_key(&addr);
             break;
@@ -1223,5 +1223,5 @@
 
         case HCI_EVENT_ENCRYPTION_CHANGE:
-            handle = READ_BT_16(packet, 3);
+            handle = little_endian_read_16(packet, 3);
             conn = hci_connection_for_handle(handle);
             if (!conn) break;
@@ -1237,5 +1237,5 @@
 
         case HCI_EVENT_AUTHENTICATION_COMPLETE_EVENT:
-            handle = READ_BT_16(packet, 3);
+            handle = little_endian_read_16(packet, 3);
             conn = hci_connection_for_handle(handle);
             if (!conn) break;
@@ -1262,5 +1262,5 @@
             if (!hci_stack->remote_device_db) break;
             if (packet[2]) break; // status not ok
-            bt_flip_addr(addr, &packet[3]);
+            reverse_bd_addr(&packet[3], addr);
             // fix for invalid remote names - terminate on 0xff
             for (i=0; i<248;i++){
@@ -1283,5 +1283,5 @@
             int offset = 3;
             for (i=0; i<packet[2];i++){
-                bt_flip_addr(addr, &packet[offset]);
+                reverse_bd_addr(&packet[offset], addr);
                 offset += 14; // 6 + 1 + 1 + 1 + 3 + 2;
                 if (hci_stack->remote_device_db->get_name(&addr, &device_name)){
@@ -1308,5 +1308,5 @@
         case HCI_EVENT_ROLE_CHANGE:
             if (packet[2]) break;   // status != 0
-            handle = READ_BT_16(packet, 3);
+            handle = little_endian_read_16(packet, 3);
             conn = hci_connection_for_handle(handle);
             if (!conn) break;       // no conn
@@ -1331,5 +1331,5 @@
                 case HCI_SUBEVENT_LE_CONNECTION_COMPLETE:
                     // Connection management
-                    bt_flip_addr(addr, &packet[8]);
+                    reverse_bd_addr(&packet[8], addr);
                     addr_type = (bd_addr_type_t)packet[7];
                     log_info("LE Connection_complete (status=%u) type %u, %s", packet[3], addr_type, bd_addr_to_str(addr));
@@ -1357,5 +1357,5 @@
 
                     conn->state = OPEN;
-                    conn->con_handle = READ_BT_16(packet, 4);
+                    conn->con_handle = little_endian_read_16(packet, 4);
 
                     // TODO: store - role, peer address type, conn_interval, conn_latency, supervision timeout, master clock
@@ -1370,5 +1370,5 @@
                     break;
 
-            // log_info("LE buffer size: %u, count %u", READ_BT_16(packet,6), packet[8]);
+            // log_info("LE buffer size: %u, count %u", little_endian_read_16(packet,6), packet[8]);
 
                 default:
@@ -1389,5 +1389,5 @@
     if (hci_stack->state == HCI_STATE_FALLING_ASLEEP
         && hci_stack->substate == 1
-        && COMMAND_COMPLETE_EVENT(packet, hci_write_scan_enable)){
+        && HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_write_scan_enable)){
         hci_stack->substate++;
     }
@@ -1400,5 +1400,5 @@
         if (!packet[2]){
             hci_connection_t * conn;
-            handle = READ_BT_16(packet, 3);
+            handle = little_endian_read_16(packet, 3);
             conn = hci_connection_for_handle(handle);
             if (conn) {
@@ -1793,5 +1793,5 @@
 }
 
-void hci_discoverable_control(uint8_t enable){
+void gap_discoverable_control(uint8_t enable){
     if (enable) enable = 1; // normalize argument
 
@@ -2140,5 +2140,5 @@
     // create_connection?
     if (IS_COMMAND(packet, hci_create_connection)){
-        bt_flip_addr(addr, &packet[3]);
+        reverse_bd_addr(&packet[3], addr);
         log_info("Create_connection to %s", bd_addr_to_str(addr));
 
@@ -2179,5 +2179,5 @@
     if (IS_COMMAND(packet, hci_delete_stored_link_key)){
         if (hci_stack->remote_device_db){
-            bt_flip_addr(addr, &packet[3]);
+            reverse_bd_addr(&packet[3], addr);
             hci_stack->remote_device_db->delete_link_key(&addr);
         }
@@ -2186,5 +2186,5 @@
     if (IS_COMMAND(packet, hci_pin_code_request_negative_reply)
     ||  IS_COMMAND(packet, hci_pin_code_request_reply)){
-        bt_flip_addr(addr, &packet[3]);
+        reverse_bd_addr(&packet[3], addr);
         conn = hci_connection_for_bd_addr_and_type(&addr, BD_ADDR_TYPE_CLASSIC);
         if (conn){
@@ -2197,5 +2197,5 @@
     ||  IS_COMMAND(packet, hci_user_passkey_request_negative_reply)
     ||  IS_COMMAND(packet, hci_user_passkey_request_reply)) {
-        bt_flip_addr(addr, &packet[3]);
+        reverse_bd_addr(&packet[3], addr);
         conn = hci_connection_for_bd_addr_and_type(&addr, BD_ADDR_TYPE_CLASSIC);
         if (conn){
@@ -2209,5 +2209,5 @@
     }
     if (IS_COMMAND(packet, hci_le_set_random_address)){
-        bt_flip_addr(hci_stack->adv_address, &packet[3]);
+        reverse_bd_addr(&packet[3], hci_stack->adv_address);
     }
 #endif
@@ -2303,6 +2303,6 @@
     event[1] = sizeof(event) - 2;
     event[2] = status;
-    bt_store_16(event, 3, conn->con_handle);
-    bt_flip_addr(&event[5], conn->address);
+    little_endian_store_16(event, 3, conn->con_handle);
+    reverse_bd_addr(conn->address, &event[5]);
     event[11] = 1; // ACL connection
     event[12] = 0; // encryption disabled
@@ -2317,11 +2317,11 @@
     event[2] = HCI_SUBEVENT_LE_CONNECTION_COMPLETE;
     event[3] = status;
-    bt_store_16(event, 4, conn_handle);
+    little_endian_store_16(event, 4, conn_handle);
     event[6] = 0; // TODO: role
     event[7] = address_type;
-    bt_flip_addr(&event[8], *address);
-    bt_store_16(event, 14, 0); // interval
-    bt_store_16(event, 16, 0); // latency
-    bt_store_16(event, 18, 0); // supervision timeout
+    reverse_bd_addr(*address, &event[8]);
+    little_endian_store_16(event, 14, 0); // interval
+    little_endian_store_16(event, 16, 0); // latency
+    little_endian_store_16(event, 18, 0); // supervision timeout
     event[20] = 0; // master clock accuracy
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -2334,5 +2334,5 @@
     event[1] = sizeof(event) - 2;
     event[2] = 0; // status = OK
-    bt_store_16(event, 3, handle);
+    little_endian_store_16(event, 3, handle);
     event[5] = reason;
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -2346,5 +2346,5 @@
     event[0] = L2CAP_EVENT_TIMEOUT_CHECK;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, conn->con_handle);
+    little_endian_store_16(event, 2, conn->con_handle);
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
     hci_stack->packet_handler(HCI_EVENT_PACKET, event, sizeof(event));
@@ -2378,5 +2378,5 @@
     event[2] = BTSTACK_MAJOR;
     event[3] = BTSTACK_MINOR;
-    bt_store_16(event, 4, BTSTACK_REVISION);
+    little_endian_store_16(event, 4, BTSTACK_REVISION);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
     hci_stack->packet_handler(HCI_EVENT_PACKET, event, sizeof(event));
@@ -2399,5 +2399,5 @@
     event[1] = sizeof(event) - 2 - 1;
     event[2] = 0;   // just to be compatible with HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE
-    bt_flip_addr(&event[3], *addr);
+    reverse_bd_addr(*addr, &event[3]);
     memcpy(&event[9], name, 248);
 
@@ -2426,5 +2426,5 @@
     event[pos++] = GAP_SECURITY_LEVEL;
     event[pos++] = sizeof(event) - 2;
-    bt_store_16(event, 2, con_handle);
+    little_endian_store_16(event, 2, con_handle);
     pos += 2;
     event[pos++] = level;
@@ -2441,5 +2441,5 @@
     event[pos++] = sizeof(event) - 2;
     event[pos++] = status;
-    bt_flip_addr( * (bd_addr_t *) &event[pos], address);
+    reverse_bd_addr(address,  * (bd_addr_t *) &event[pos]);
     pos += 6;
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/hci.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/hci.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/hci.h	(revision 374)
@@ -234,5 +234,5 @@
 
 //
-#define IS_COMMAND(packet, command) (READ_BT_16(packet,0) == command.opcode)
+#define IS_COMMAND(packet, command) (little_endian_read_16(packet,0) == command.opcode)
 
 // data: event(8)
@@ -595,5 +595,5 @@
 
 // Allows to control if device is discoverable. OFF by default.
-void hci_discoverable_control(uint8_t enable);
+void gap_discoverable_control(uint8_t enable);
 
 // Creates and sends HCI command packets based on a template and
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/hci_dump.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/hci_dump.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/hci_dump.c	(revision 374)
@@ -194,9 +194,9 @@
 
         case HCI_DUMP_BLUEZ:
-            bt_store_16( (uint8_t *) &header_bluez.len, 0, 1 + len);
+            little_endian_store_16( (uint8_t *) &header_bluez.len, 0, 1 + len);
             header_bluez.in  = in;
             header_bluez.pad = 0;
-            bt_store_32( (uint8_t *) &header_bluez.ts_sec,  0, curr_time.tv_sec);
-            bt_store_32( (uint8_t *) &header_bluez.ts_usec, 0, curr_time.tv_usec);
+            little_endian_store_32( (uint8_t *) &header_bluez.ts_sec,  0, curr_time.tv_sec);
+            little_endian_store_32( (uint8_t *) &header_bluez.ts_usec, 0, curr_time.tv_usec);
             header_bluez.packet_type = packet_type;
             write (dump_file, &header_bluez, sizeof(hcidump_hdr) );
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/l2cap.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/l2cap.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/l2cap.c	(revision 374)
@@ -135,12 +135,12 @@
     event[1] = sizeof(event) - 2;
     event[2] = status;
-    bt_flip_addr(&event[3], channel->address);
-    bt_store_16(event,  9, channel->handle);
-    bt_store_16(event, 11, channel->psm);
-    bt_store_16(event, 13, channel->local_cid);
-    bt_store_16(event, 15, channel->remote_cid);
-    bt_store_16(event, 17, channel->local_mtu);
-    bt_store_16(event, 19, channel->remote_mtu);
-    bt_store_16(event, 21, channel->flush_timeout);
+    reverse_bd_addr(channel->address, &event[3]);
+    little_endian_store_16(event,  9, channel->handle);
+    little_endian_store_16(event, 11, channel->psm);
+    little_endian_store_16(event, 13, channel->local_cid);
+    little_endian_store_16(event, 15, channel->remote_cid);
+    little_endian_store_16(event, 17, channel->local_mtu);
+    little_endian_store_16(event, 19, channel->remote_mtu);
+    little_endian_store_16(event, 21, channel->flush_timeout);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
     l2cap_dispatch(channel, HCI_EVENT_PACKET, event, sizeof(event));
@@ -152,5 +152,5 @@
     event[0] = L2CAP_EVENT_CHANNEL_CLOSED;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->local_cid);
+    little_endian_store_16(event, 2, channel->local_cid);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
     l2cap_dispatch(channel, HCI_EVENT_PACKET, event, sizeof(event));
@@ -163,9 +163,9 @@
     event[0] = L2CAP_EVENT_INCOMING_CONNECTION;
     event[1] = sizeof(event) - 2;
-    bt_flip_addr(&event[2], channel->address);
-    bt_store_16(event,  8, channel->handle);
-    bt_store_16(event, 10, channel->psm);
-    bt_store_16(event, 12, channel->local_cid);
-    bt_store_16(event, 14, channel->remote_cid);
+    reverse_bd_addr(channel->address, &event[2]);
+    little_endian_store_16(event,  8, channel->handle);
+    little_endian_store_16(event, 10, channel->psm);
+    little_endian_store_16(event, 12, channel->local_cid);
+    little_endian_store_16(event, 14, channel->remote_cid);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
     l2cap_dispatch(channel, HCI_EVENT_PACKET, event, sizeof(event));
@@ -176,6 +176,6 @@
     event[0] = L2CAP_EVENT_CONNECTION_PARAMETER_UPDATE_RESPONSE;
     event[1] = 4;
-    bt_store_16(event, 2, handle);
-    bt_store_16(event, 4, result);
+    little_endian_store_16(event, 2, handle);
+    little_endian_store_16(event, 4, result);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
     (*packet_handler)(NULL, HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -188,5 +188,5 @@
     event[1] = sizeof(event) - 2;
     event[2] = status;
-    bt_store_16(event, 3, psm);
+    little_endian_store_16(event, 3, psm);
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
     (*packet_handler)(connection, HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -201,5 +201,5 @@
     event[0] = L2CAP_EVENT_CREDITS;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->local_cid);
+    little_endian_store_16(event, 2, channel->local_cid);
     event[4] = credits;
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -412,11 +412,11 @@
 
     // 0 - Connection handle : PB=pb : BC=00
-    bt_store_16(acl_buffer, 0, channel->handle | (pb << 12) | (0 << 14));
+    little_endian_store_16(acl_buffer, 0, channel->handle | (pb << 12) | (0 << 14));
     // 2 - ACL length
-    bt_store_16(acl_buffer, 2,  len + 4);
+    little_endian_store_16(acl_buffer, 2,  len + 4);
     // 4 - L2CAP packet length
-    bt_store_16(acl_buffer, 4,  len + 0);
+    little_endian_store_16(acl_buffer, 4,  len + 0);
     // 6 - L2CAP channel DEST
-    bt_store_16(acl_buffer, 6, channel->remote_cid);
+    little_endian_store_16(acl_buffer, 6, channel->remote_cid);
     // send
     err = hci_send_acl_packet_buffer(len+8);
@@ -449,11 +449,11 @@
 
     // 0 - Connection handle : PB=pb : BC=00
-    bt_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
+    little_endian_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
     // 2 - ACL length
-    bt_store_16(acl_buffer, 2,  len + 4);
+    little_endian_store_16(acl_buffer, 2,  len + 4);
     // 4 - L2CAP packet length
-    bt_store_16(acl_buffer, 4,  len + 0);
+    little_endian_store_16(acl_buffer, 4,  len + 0);
     // 6 - L2CAP channel DEST
-    bt_store_16(acl_buffer, 6, cid);
+    little_endian_store_16(acl_buffer, 6, cid);
     // send
     err = hci_send_acl_packet_buffer(len+8);
@@ -665,5 +665,5 @@
                         config_options[0] = 1; // MTU
                         config_options[1] = 2; // len param
-                        bt_store_16( (uint8_t*)&config_options, 2, channel->remote_mtu);
+                        little_endian_store_16( (uint8_t*)&config_options, 2, channel->remote_mtu);
                         l2cap_send_signaling_packet(channel->handle, CONFIGURE_RESPONSE, channel->remote_sig_id, channel->remote_cid, flags, 0, 4, &config_options);
                         channelStateVarClearFlag(channel,L2CAP_CHANNEL_STATE_VAR_SEND_CONF_RSP_MTU);
@@ -679,5 +679,5 @@
                     config_options[0] = 1; // MTU
                     config_options[1] = 2; // len param
-                    bt_store_16( (uint8_t*)&config_options, 2, channel->local_mtu);
+                    little_endian_store_16( (uint8_t*)&config_options, 2, channel->local_mtu);
                     l2cap_send_signaling_packet(channel->handle, CONFIGURE_REQUEST, channel->local_sig_id, channel->remote_cid, 0, 4, &config_options);
                     l2cap_start_rtx(channel);
@@ -893,7 +893,7 @@
         // handle connection complete events
         case HCI_EVENT_CONNECTION_COMPLETE:
-            bt_flip_addr(address, &packet[5]);
+            reverse_bd_addr(&packet[5], address);
             if (packet[2] == 0){
-                handle = READ_BT_16(packet, 3);
+                handle = little_endian_read_16(packet, 3);
                 l2cap_handle_connection_success_for_addr(address, handle);
             } else {
@@ -904,7 +904,7 @@
         // handle successful create connection cancel command
         case HCI_EVENT_COMMAND_COMPLETE:
-            if ( COMMAND_COMPLETE_EVENT(packet, hci_create_connection_cancel) ) {
+            if ( HCI_EVENT_IS_COMMAND_COMPLETE(packet, hci_create_connection_cancel) ) {
                 if (packet[5] == 0){
-                    bt_flip_addr(address, &packet[6]);
+                    reverse_bd_addr(&packet[6], address);
                     // CONNECTION TERMINATED BY LOCAL HOST (0X16)
                     l2cap_handle_connection_failed_for_addr(address, 0x16);
@@ -921,5 +921,5 @@
         case HCI_EVENT_DISCONNECTION_COMPLETE:
             // send l2cap disconnect events for all channels on this handle and free them
-            handle = READ_BT_16(packet, 3);
+            handle = little_endian_read_16(packet, 3);
             linked_list_iterator_init(&it, &l2cap_channels);
             while (linked_list_iterator_has_next(&it)){
@@ -940,5 +940,5 @@
         // HCI Connection Timeouts
         case L2CAP_EVENT_TIMEOUT_CHECK:
-            handle = READ_BT_16(packet, 2);
+            handle = little_endian_read_16(packet, 2);
             if (hci_authentication_active_for_handle(handle)) break;
             hci_con_used = 0;
@@ -971,5 +971,5 @@
 
         case HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE:
-            handle = READ_BT_16(packet, 3);
+            handle = little_endian_read_16(packet, 3);
             linked_list_iterator_init(&it, &l2cap_channels);
             while (linked_list_iterator_has_next(&it)){
@@ -982,5 +982,5 @@
 
         case GAP_SECURITY_LEVEL:
-            handle = READ_BT_16(packet, 2);
+            handle = little_endian_read_16(packet, 2);
             log_info("l2cap - security level update");
             linked_list_iterator_init(&it, &l2cap_channels);
@@ -1163,5 +1163,5 @@
     channel->remote_sig_id = command[L2CAP_SIGNALING_COMMAND_SIGID_OFFSET];
 
-    flags = READ_BT_16(command, 6);
+    flags = little_endian_read_16(command, 6);
     if (flags & 1) {
         channelStateVarSetFlag(channel, L2CAP_CHANNEL_STATE_VAR_SEND_CONF_RSP_CONT);
@@ -1169,5 +1169,5 @@
 
     // accept the other's configuration options
-    end_pos = 4 + READ_BT_16(command, L2CAP_SIGNALING_COMMAND_LENGTH_OFFSET);
+    end_pos = 4 + little_endian_read_16(command, L2CAP_SIGNALING_COMMAND_LENGTH_OFFSET);
     pos     = 8;
     while (pos < end_pos){
@@ -1180,5 +1180,5 @@
         // MTU { type(8): 1, len(8):2, MTU(16) }
         if (option_type == 1 && length == 2){
-            channel->remote_mtu = READ_BT_16(command, pos);
+            channel->remote_mtu = little_endian_read_16(command, pos);
             // log_info("l2cap cid 0x%02x, remote mtu %u", channel->local_cid, channel->remote_mtu);
             channelStateVarSetFlag(channel, L2CAP_CHANNEL_STATE_VAR_SEND_CONF_RSP_MTU);
@@ -1186,5 +1186,5 @@
         // Flush timeout { type(8):2, len(8): 2, Flush Timeout(16)}
         if (option_type == 2 && length == 2){
-            channel->flush_timeout = READ_BT_16(command, pos);
+            channel->flush_timeout = little_endian_read_16(command, pos);
         }
         // check for unknown options
@@ -1237,9 +1237,9 @@
                 case CONNECTION_RESPONSE:
                     l2cap_stop_rtx(channel);
-                    result = READ_BT_16 (command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET+4);
+                    result = little_endian_read_16 (command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET+4);
                     switch (result) {
                         case 0:
                             // successful connection
-                            channel->remote_cid = READ_BT_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
+                            channel->remote_cid = little_endian_read_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
                             channel->state = L2CAP_STATE_CONFIG;
                             channelStateVarSetFlag(channel, L2CAP_CHANNEL_STATE_VAR_SEND_CONF_REQ);
@@ -1274,5 +1274,5 @@
 
         case L2CAP_STATE_CONFIG:
-            result = READ_BT_16 (command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET+4);
+            result = little_endian_read_16 (command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET+4);
             switch (code) {
                 case CONFIGURE_REQUEST:
@@ -1353,6 +1353,6 @@
 
         case CONNECTION_REQUEST: {
-            uint16_t psm =        READ_BT_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
-            uint16_t source_cid = READ_BT_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET+2);
+            uint16_t psm =        little_endian_read_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
+            uint16_t source_cid = little_endian_read_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET+2);
             l2cap_handle_connection_request(handle, sig_id, psm, source_cid);
             return;
@@ -1364,5 +1364,5 @@
 
         case INFORMATION_REQUEST: {
-            uint16_t infoType = READ_BT_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
+            uint16_t infoType = little_endian_read_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
             l2cap_register_signaling_response(handle, code, sig_id, infoType);
             return;
@@ -1375,5 +1375,5 @@
     
     // Get potential destination CID
-    dest_cid = READ_BT_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
+    dest_cid = little_endian_read_16(command, L2CAP_SIGNALING_COMMAND_DATA_OFFSET);
 
     // Find channel for this sig_id and connection handle
@@ -1415,5 +1415,5 @@
 
                 // increment command_offset
-                command_offset += L2CAP_SIGNALING_COMMAND_DATA_OFFSET + READ_BT_16(packet, command_offset + L2CAP_SIGNALING_COMMAND_LENGTH_OFFSET);
+                command_offset += L2CAP_SIGNALING_COMMAND_DATA_OFFSET + little_endian_read_16(packet, command_offset + L2CAP_SIGNALING_COMMAND_LENGTH_OFFSET);
             }
             break;
@@ -1435,5 +1435,5 @@
             switch (packet[8]){
                 case CONNECTION_PARAMETER_UPDATE_RESPONSE: {
-                    uint16_t result = READ_BT_16(packet, 12);
+                    uint16_t result = little_endian_read_16(packet, 12);
                     l2cap_emit_connection_parameter_update_response(handle, result);
                     break;
@@ -1450,8 +1450,8 @@
                         int update_parameter = 1;
                         le_connection_parameter_range_t existing_range = gap_le_get_connection_parameter_range();
-                        uint16_t le_conn_interval_min = READ_BT_16(packet,12);
-                        uint16_t le_conn_interval_max = READ_BT_16(packet,14);
-                        uint16_t le_conn_latency = READ_BT_16(packet,16);
-                        uint16_t le_supervision_timeout = READ_BT_16(packet,18);
+                        uint16_t le_conn_interval_min = little_endian_read_16(packet,12);
+                        uint16_t le_conn_interval_max = little_endian_read_16(packet,14);
+                        uint16_t le_conn_latency = little_endian_read_16(packet,16);
+                        uint16_t le_supervision_timeout = little_endian_read_16(packet,18);
 
                         if (le_conn_interval_min < existing_range.le_conn_interval_min) update_parameter = 0;
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/l2cap_signaling.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/l2cap_signaling.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/l2cap_signaling.c	(revision 374)
@@ -91,7 +91,7 @@
 
     // 0 - Connection handle : PB=pb : BC=00
-    bt_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
+    little_endian_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
     // 6 - L2CAP channel = 1
-    bt_store_16(acl_buffer, 6, cid);
+    little_endian_store_16(acl_buffer, 6, cid);
     // 8 - Code
     acl_buffer[8] = cmd;
@@ -134,9 +134,9 @@
 
     // 2 - ACL length
-    bt_store_16(acl_buffer, 2,  pos - 4);
+    little_endian_store_16(acl_buffer, 2,  pos - 4);
     // 4 - L2CAP packet length
-    bt_store_16(acl_buffer, 4,  pos - 6 - 2);
+    little_endian_store_16(acl_buffer, 4,  pos - 6 - 2);
     // 10 - L2CAP signaling parameter length
-    bt_store_16(acl_buffer, 10, pos - 12);
+    little_endian_store_16(acl_buffer, 10, pos - 12);
 
     return pos;
@@ -158,7 +158,7 @@
 
     // 0 - Connection handle : PB=pb : BC=00
-    bt_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
+    little_endian_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
     // 6 - L2CAP LE Signaling channel = 5
-    bt_store_16(acl_buffer, 6, 5);
+    little_endian_store_16(acl_buffer, 6, 5);
     // 8 - Code
     acl_buffer[8] = CONNECTION_PARAMETER_UPDATE_REQUEST;
@@ -166,18 +166,18 @@
     acl_buffer[9] = 1;
     uint16_t pos = 12;
-    bt_store_16(acl_buffer, pos, interval_min);
-    pos += 2;
-    bt_store_16(acl_buffer, pos, interval_max);
-    pos += 2;
-    bt_store_16(acl_buffer, pos, slave_latency);
-    pos += 2;
-    bt_store_16(acl_buffer, pos, timeout_multiplier);
+    little_endian_store_16(acl_buffer, pos, interval_min);
+    pos += 2;
+    little_endian_store_16(acl_buffer, pos, interval_max);
+    pos += 2;
+    little_endian_store_16(acl_buffer, pos, slave_latency);
+    pos += 2;
+    little_endian_store_16(acl_buffer, pos, timeout_multiplier);
     pos += 2;
     // 2 - ACL length
-    bt_store_16(acl_buffer, 2,  pos - 4);
+    little_endian_store_16(acl_buffer, 2,  pos - 4);
     // 4 - L2CAP packet length
-    bt_store_16(acl_buffer, 4,  pos - 6 - 2);
+    little_endian_store_16(acl_buffer, 4,  pos - 6 - 2);
     // 10 - L2CAP signaling parameter length
-    bt_store_16(acl_buffer, 10, pos - 12);
+    little_endian_store_16(acl_buffer, 10, pos - 12);
     return pos;
 }
@@ -188,7 +188,7 @@
 
     // 0 - Connection handle : PB=pb : BC=00
-    bt_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
+    little_endian_store_16(acl_buffer, 0, handle | (pb << 12) | (0 << 14));
     // 6 - L2CAP LE Signaling channel = 5
-    bt_store_16(acl_buffer, 6, 5);
+    little_endian_store_16(acl_buffer, 6, 5);
     // 8 - Code
     acl_buffer[8] = CONNECTION_PARAMETER_UPDATE_REQUEST;
@@ -196,12 +196,12 @@
     acl_buffer[9] = 1;
     uint16_t pos = 12;
-    bt_store_16(acl_buffer, pos, response);
+    little_endian_store_16(acl_buffer, pos, response);
     pos += 2;
     // 2 - ACL length
-    bt_store_16(acl_buffer, 2,  pos - 4);
+    little_endian_store_16(acl_buffer, 2,  pos - 4);
     // 4 - L2CAP packet length
-    bt_store_16(acl_buffer, 4,  pos - 6 - 2);
+    little_endian_store_16(acl_buffer, 4,  pos - 6 - 2);
     // 10 - L2CAP signaling parameter length
-    bt_store_16(acl_buffer, 10, pos - 12);
+    little_endian_store_16(acl_buffer, 10, pos - 12);
     return pos;
 }
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/pan.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/pan.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/pan.c	(revision 374)
@@ -80,5 +80,5 @@
 
 	// 0x0001 "Service Class ID List"
-	de_add_number(service,  DE_UINT, DE_SIZE_16, SDP_ServiceClassIDList);
+	de_add_number(service,  DE_UINT, DE_SIZE_16, BLUETOOTH_ATTRIBUTE_SERVICE_CLASS_ID_LIST);
 	attribute = de_push_sequence(service);
 	{
@@ -89,5 +89,5 @@
 
 	// 0x0004 "Protocol Descriptor List"
-	de_add_number(service,  DE_UINT, DE_SIZE_16, SDP_ProtocolDescriptorList);
+	de_add_number(service,  DE_UINT, DE_SIZE_16, BLUETOOTH_ATTRIBUTE_PROTOCOL_DESCRIPTOR_LIST);
 	attribute = de_push_sequence(service);
 	{
@@ -95,5 +95,5 @@
 		{
 			de_add_number(l2cpProtocol,  DE_UUID, DE_SIZE_16, 0x0100);
-			de_add_number(l2cpProtocol,  DE_UINT, DE_SIZE_16, SDP_BNEPProtocol);  // l2cap psm
+			de_add_number(l2cpProtocol,  DE_UINT, DE_SIZE_16, BLUETOOTH_PROTOCOL_BNEP);  // l2cap psm
 		}
 		de_pop_sequence(attribute, l2cpProtocol);
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/rfcomm.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/rfcomm.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/rfcomm.c	(revision 374)
@@ -136,7 +136,7 @@
     event[0] = RFCOMM_EVENT_INCOMING_CONNECTION;
     event[1] = sizeof(event) - 2;
-    bt_flip_addr(&event[2], channel->multiplexer->remote_addr);
+    reverse_bd_addr(channel->multiplexer->remote_addr, &event[2]);
     event[8] = channel->dlci >> 1;
-    bt_store_16(event, 9, channel->rfcomm_cid);
+    little_endian_store_16(event, 9, channel->rfcomm_cid);
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
 	(*app_packet_handler)(channel->connection, HCI_EVENT_PACKET, 0, (uint8_t *) event, sizeof(event));
@@ -157,9 +157,9 @@
     event[pos++] = sizeof(event) - 2;
     event[pos++] = status;
-    bt_flip_addr(&event[pos], channel->multiplexer->remote_addr); pos += 6;
-    bt_store_16(event,  pos, channel->multiplexer->con_handle);   pos += 2;
+    reverse_bd_addr(channel->multiplexer->remote_addr, &event[pos]); pos += 6;
+    little_endian_store_16(event,  pos, channel->multiplexer->con_handle);   pos += 2;
 	event[pos++] = channel->dlci >> 1;
-	bt_store_16(event, pos, channel->rfcomm_cid); pos += 2;       // channel ID
-	bt_store_16(event, pos, channel->max_frame_size); pos += 2;   // max frame size
+	little_endian_store_16(event, pos, channel->rfcomm_cid); pos += 2;       // channel ID
+	little_endian_store_16(event, pos, channel->max_frame_size); pos += 2;   // max frame size
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
 	(*app_packet_handler)(channel->connection, HCI_EVENT_PACKET, 0, (uint8_t *) event, pos);
@@ -175,9 +175,9 @@
     event[pos++] = sizeof(event) - 2;
     event[pos++] = BTSTACK_MEMORY_ALLOC_FAILED;
-    bt_flip_addr(&event[pos], *addr); pos += 6;
-    bt_store_16(event,  pos, 0);   pos += 2;
+    reverse_bd_addr(*addr, &event[pos]); pos += 6;
+    little_endian_store_16(event,  pos, 0);   pos += 2;
 	event[pos++] = server_channel;
-	bt_store_16(event, pos, 0); pos += 2;   // channel ID
-	bt_store_16(event, pos, 0); pos += 2;   // max frame size
+	little_endian_store_16(event, pos, 0); pos += 2;   // channel ID
+	little_endian_store_16(event, pos, 0); pos += 2;   // max frame size
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
 	(*app_packet_handler)(connection, HCI_EVENT_PACKET, 0, (uint8_t *) event, pos);
@@ -204,5 +204,5 @@
     event[0] = RFCOMM_EVENT_CHANNEL_CLOSED;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->rfcomm_cid);
+    little_endian_store_16(event, 2, channel->rfcomm_cid);
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
 	(*app_packet_handler)(channel->connection, HCI_EVENT_PACKET, 0, (uint8_t *) event, sizeof(event));
@@ -214,5 +214,5 @@
     event[0] = RFCOMM_EVENT_CREDITS;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->rfcomm_cid);
+    little_endian_store_16(event, 2, channel->rfcomm_cid);
     event[4] = credits;
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -237,5 +237,5 @@
     event[0] = RFCOMM_EVENT_REMOTE_LINE_STATUS;
     event[1] = sizeof(event) - 2;
-    bt_store_16(event, 2, channel->rfcomm_cid);
+    little_endian_store_16(event, 2, channel->rfcomm_cid);
     event[4] = line_status;
     hci_dump_packet( HCI_EVENT_PACKET, 0, event, sizeof(event));
@@ -905,8 +905,8 @@
         case L2CAP_EVENT_INCOMING_CONNECTION:
             // data: event(8), len(8), address(48), handle (16),  psm (16), source cid(16) dest cid(16)
-            bt_flip_addr(event_addr, &packet[2]);
-            con_handle = READ_BT_16(packet,  8);
-            psm        = READ_BT_16(packet, 10);
-            l2cap_cid  = READ_BT_16(packet, 12);
+            reverse_bd_addr(&packet[2], event_addr);
+            con_handle = little_endian_read_16(packet,  8);
+            psm        = little_endian_read_16(packet, 10);
+            l2cap_cid  = little_endian_read_16(packet, 12);
 
             if (psm != PSM_RFCOMM) break;
@@ -939,5 +939,5 @@
         case L2CAP_EVENT_CHANNEL_OPENED:
 
-            if (READ_BT_16(packet, 11) != PSM_RFCOMM) break;
+            if (little_endian_read_16(packet, 11) != PSM_RFCOMM) break;
 
             status = packet[2];
@@ -945,7 +945,7 @@
 
             // get multiplexer for remote addr
-            con_handle = READ_BT_16(packet, 9);
-            l2cap_cid = READ_BT_16(packet, 13);
-            bt_flip_addr(event_addr, &packet[3]);
+            con_handle = little_endian_read_16(packet, 9);
+            l2cap_cid = little_endian_read_16(packet, 13);
+            reverse_bd_addr(&packet[3], event_addr);
             multiplexer = rfcomm_multiplexer_for_addr(&event_addr);
             if (!multiplexer) {
@@ -990,5 +990,5 @@
 
                 // set max frame size based on l2cap MTU
-                multiplexer->max_frame_size = rfcomm_max_frame_size_for_l2cap_mtu(READ_BT_16(packet, 17));
+                multiplexer->max_frame_size = rfcomm_max_frame_size_for_l2cap_mtu(little_endian_read_16(packet, 17));
             }
             return 1;
@@ -998,5 +998,5 @@
         case L2CAP_EVENT_CREDITS:
             // data: event(8), len(8), local_cid(16), credits(8)
-            l2cap_cid = READ_BT_16(packet, 2);
+            l2cap_cid = little_endian_read_16(packet, 2);
             multiplexer = rfcomm_multiplexer_for_l2cap_cid(l2cap_cid);
             if (!multiplexer) break;
@@ -1019,5 +1019,5 @@
         case L2CAP_EVENT_CHANNEL_CLOSED:
             // data: event (8), len(8), channel (16)
-            l2cap_cid = READ_BT_16(packet, 2);
+            l2cap_cid = little_endian_read_16(packet, 2);
             multiplexer = rfcomm_multiplexer_for_l2cap_cid(l2cap_cid);
             log_info("L2CAP_EVENT_CHANNEL_CLOSED cid 0x%0x, mult %p", l2cap_cid, multiplexer);
@@ -1478,5 +1478,5 @@
                     event_pn.super.type = CH_EVT_RCVD_PN;
                     event_pn.priority = packet[payload_offset+4];
-                    event_pn.max_frame_size = READ_BT_16(packet, payload_offset+6);
+                    event_pn.max_frame_size = little_endian_read_16(packet, payload_offset+6);
                     event_pn.credits_outgoing = packet[payload_offset+9];
                     log_info("Received UIH Parameter Negotiation Command for #%u, credits %u",
@@ -1489,5 +1489,5 @@
                     event_pn.super.type = CH_EVT_RCVD_PN_RSP;
                     event_pn.priority = packet[payload_offset+4];
-                    event_pn.max_frame_size = READ_BT_16(packet, payload_offset+6);
+                    event_pn.max_frame_size = little_endian_read_16(packet, payload_offset+6);
                     event_pn.credits_outgoing = packet[payload_offset+9];
                     log_info("Received UIH Parameter Negotiation Response max frame %u, credits %u",
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/sdp.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/sdp.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/sdp.c	(revision 374)
@@ -90,5 +90,5 @@
     if (de_get_element_type(serviceRecordHandleAttribute) != DE_UINT) return 0;
     if (de_get_size_type(serviceRecordHandleAttribute) != DE_SIZE_32) return 0;
-    return READ_NET_32(serviceRecordHandleAttribute, 1);
+    return big_endian_read_32(serviceRecordHandleAttribute, 1);
 }
 
@@ -100,5 +100,5 @@
     event[1] = sizeof(event) - 2;
     event[2] = status;
-    bt_store_32(event, 3, handle);
+    little_endian_store_32(event, 3, handle);
     hci_dump_packet(HCI_EVENT_PACKET, 0, event, sizeof(event));
     (*app_packet_handler)(connection, HCI_EVENT_PACKET, 0, (uint8_t *) event, sizeof(event));
@@ -275,9 +275,9 @@
 
     // get request details
-    uint16_t  transaction_id = READ_NET_16(packet, 1);
-    // not used yet - uint16_t  param_len = READ_NET_16(packet, 3);
+    uint16_t  transaction_id = big_endian_read_16(packet, 1);
+    // not used yet - uint16_t  param_len = big_endian_read_16(packet, 3);
     uint8_t * serviceSearchPattern = &packet[5];
     uint16_t  serviceSearchPatternLen = de_get_len(serviceSearchPattern);
-    uint16_t  maximumServiceRecordCount = READ_NET_16(packet, 5 + serviceSearchPatternLen);
+    uint16_t  maximumServiceRecordCount = big_endian_read_16(packet, 5 + serviceSearchPatternLen);
     uint8_t * continuationState = &packet[5+serviceSearchPatternLen+2];
 
@@ -297,5 +297,5 @@
     continuation_index = 0;
     if (continuationState[0] == 2){
-        continuation_index = READ_NET_16(continuationState, 1);
+        continuation_index = big_endian_read_16(continuationState, 1);
     }
 
@@ -359,8 +359,8 @@
 
     // get request details
-    uint16_t  transaction_id = READ_NET_16(packet, 1);
-    // not used yet - uint16_t  param_len = READ_NET_16(packet, 3);
-    uint32_t  serviceRecordHandle = READ_NET_32(packet, 5);
-    uint16_t  maximumAttributeByteCount = READ_NET_16(packet, 9);
+    uint16_t  transaction_id = big_endian_read_16(packet, 1);
+    // not used yet - uint16_t  param_len = big_endian_read_16(packet, 3);
+    uint32_t  serviceRecordHandle = big_endian_read_32(packet, 5);
+    uint16_t  maximumAttributeByteCount = big_endian_read_16(packet, 9);
     uint8_t * attributeIDList = &packet[11];
     uint16_t  attributeIDListLen = de_get_len(attributeIDList);
@@ -383,5 +383,5 @@
     continuation_offset = 0;
     if (continuationState[0] == 2){
-        continuation_offset = READ_NET_16(continuationState, 1);
+        continuation_offset = big_endian_read_16(continuationState, 1);
     }
 
@@ -452,9 +452,9 @@
 
     // get request details
-    uint16_t  transaction_id = READ_NET_16(packet, 1);
-    // not used yet - uint16_t  param_len = READ_NET_16(packet, 3);
+    uint16_t  transaction_id = big_endian_read_16(packet, 1);
+    // not used yet - uint16_t  param_len = big_endian_read_16(packet, 3);
     uint8_t * serviceSearchPattern = &packet[5];
     uint16_t  serviceSearchPatternLen = de_get_len(serviceSearchPattern);
-    uint16_t  maximumAttributeByteCount = READ_NET_16(packet, 5 + serviceSearchPatternLen);
+    uint16_t  maximumAttributeByteCount = big_endian_read_16(packet, 5 + serviceSearchPatternLen);
     uint8_t * attributeIDList = &packet[5+serviceSearchPatternLen+2];
     uint16_t  attributeIDListLen = de_get_len(attributeIDList);
@@ -481,6 +481,6 @@
     continuation_offset = 0;
     if (continuationState[0] == 4){
-        continuation_service_index = READ_NET_16(continuationState, 1);
-        continuation_offset = READ_NET_16(continuationState, 3);
+        continuation_service_index = big_endian_read_16(continuationState, 1);
+        continuation_offset = big_endian_read_16(continuationState, 3);
     }
 
@@ -593,6 +593,6 @@
         case L2CAP_DATA_PACKET:
             pdu_id = (SDP_PDU_ID_t) packet[0];
-            transaction_id = READ_NET_16(packet, 1);
-            // param_len = READ_NET_16(packet, 3);
+            transaction_id = big_endian_read_16(packet, 1);
+            // param_len = big_endian_read_16(packet, 3);
             remote_mtu = l2cap_get_remote_mtu_for_local_cid(channel);
             // account for our buffer
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_client.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_client.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_client.c	(revision 374)
@@ -151,9 +151,9 @@
 static void parse_service_search_attribute_response(uint8_t* packet){
     uint16_t offset = 3;
-    uint16_t parameterLength = READ_NET_16(packet,offset);
+    uint16_t parameterLength = big_endian_read_16(packet,offset);
     uint16_t attributeListByteCount;
     offset+=2;
     // AttributeListByteCount <= mtu
-    attributeListByteCount = READ_NET_16(packet,offset);
+    attributeListByteCount = big_endian_read_16(packet,offset);
     offset+=2;
 
@@ -185,5 +185,5 @@
     // uint16_t handle;
     if (packet_type == L2CAP_DATA_PACKET){
-        uint16_t responseTransactionID = READ_NET_16(packet,1);
+        uint16_t responseTransactionID = big_endian_read_16(packet,1);
         if ( responseTransactionID != transactionID){
             log_error("Missmatching transaction ID, expected %u, found %u.", transactionID, responseTransactionID);
@@ -247,6 +247,6 @@
             }
             sdp_cid = channel;
-            mtu = READ_BT_16(packet, 17);
-            // handle = READ_BT_16(packet, 9);
+            mtu = little_endian_read_16(packet, 17);
+            // handle = little_endian_read_16(packet, 9);
             log_info("SDP Client Connected, cid %x, mtu %u.", sdp_cid, mtu);
 
@@ -261,6 +261,6 @@
         case L2CAP_EVENT_CHANNEL_CLOSED: {
             uint8_t status;
-            if (sdp_cid != READ_BT_16(packet, 2)) {
-                // log_info("Received L2CAP_EVENT_CHANNEL_CLOSED for cid %x, current cid %x\n",  READ_BT_16(packet, 2),sdp_cid);
+            if (sdp_cid != little_endian_read_16(packet, 2)) {
+                // log_info("Received L2CAP_EVENT_CHANNEL_CLOSED for cid %x, current cid %x\n",  little_endian_read_16(packet, 2),sdp_cid);
                 break;
             }
@@ -402,13 +402,13 @@
 static void parse_service_search_response(uint8_t* packet){
     uint16_t offset = 3;
-    uint16_t parameterLength = READ_NET_16(packet,offset);
+    uint16_t parameterLength = big_endian_read_16(packet,offset);
     uint16_t totalServiceRecordCount;
     uint16_t currentServiceRecordCount;
     offset+=2;
 
-    totalServiceRecordCount = READ_NET_16(packet,offset);
-    offset+=2;
-
-    currentServiceRecordCount = READ_NET_16(packet,offset);
+    totalServiceRecordCount = big_endian_read_16(packet,offset);
+    offset+=2;
+
+    currentServiceRecordCount = big_endian_read_16(packet,offset);
     offset+=2;
     if (currentServiceRecordCount > totalServiceRecordCount){
@@ -436,10 +436,10 @@
 static void parse_service_attribute_response(uint8_t* packet){
     uint16_t offset = 3;
-    uint16_t parameterLength = READ_NET_16(packet,offset);
+    uint16_t parameterLength = big_endian_read_16(packet,offset);
 	uint16_t attributeListByteCount;
     offset+=2;
 
     // AttributeListByteCount <= mtu
-    attributeListByteCount = READ_NET_16(packet,offset);
+    attributeListByteCount = big_endian_read_16(packet,offset);
     offset+=2;
 
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_parser.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_parser.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_parser.c	(revision 374)
@@ -166,5 +166,5 @@
             {
             sdp_query_attribute_value_event_t attribute_value_event = {
-                SDP_QUERY_ATTRIBUTE_VALUE,
+                SDP_EVENT_QUERY_ATTRIBUTE_VALUE,
                 record_counter,
                 attribute_id,
@@ -186,5 +186,5 @@
             {
             sdp_query_attribute_value_event_t attribute_value_event = {
-                SDP_QUERY_ATTRIBUTE_VALUE,
+                SDP_EVENT_QUERY_ATTRIBUTE_VALUE,
                 record_counter,
                 attribute_id,
@@ -258,5 +258,5 @@
     int i;
     for (i=0;i<record_handle_count;i++){
-        record_handle = READ_NET_32(data, i*4);
+        record_handle = big_endian_read_32(data, i*4);
         record_counter++;
 		{
@@ -275,5 +275,5 @@
 void sdp_parser_handle_done(uint8_t status){
     sdp_query_complete_event_t complete_event = {
-        SDP_QUERY_COMPLETE,
+        SDP_EVENT_QUERY_COMPLETE,
         status
     };
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_query_rfcomm.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_query_rfcomm.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_query_rfcomm.c	(revision 374)
@@ -248,5 +248,5 @@
     sdp_query_attribute_value_event_t * ve;
     switch (event->type){
-        case SDP_QUERY_ATTRIBUTE_VALUE:
+        case SDP_EVENT_QUERY_ATTRIBUTE_VALUE:
             ve = (sdp_query_attribute_value_event_t*) event;
            // log_info("handle_sdp_parser_event [ AID, ALen, DOff, Data] : [%x, %u, %u] BYTE %02x",
@@ -254,5 +254,5 @@
 
             switch (ve->attribute_id){
-                case SDP_ProtocolDescriptorList:
+                case BLUETOOTH_ATTRIBUTE_PROTOCOL_DESCRIPTOR_LIST:
                     // find rfcomm channel
                     handleProtocolDescriptorListData(ve->attribute_length, ve->data_offset, ve->data);
@@ -267,5 +267,5 @@
             }
             break;
-        case SDP_QUERY_COMPLETE:
+        case SDP_EVENT_QUERY_COMPLETE:
             (*sdp_app_callback)(event, sdp_app_context);
             break;
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_util.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_util.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/sdp_util.c	(revision 374)
@@ -98,8 +98,8 @@
             break;
         case DE_SIZE_VAR_16:
-            result = READ_NET_16(header,1);
+            result = big_endian_read_16(header,1);
             break;
         case DE_SIZE_VAR_32:
-            result = READ_NET_32(header,1);
+            result = big_endian_read_32(header,1);
             break;
         default:
@@ -122,5 +122,5 @@
 int de_element_get_uint16(uint8_t * element, uint16_t * value){
     if (de_get_size_type(element) != DE_SIZE_16) return 0;
-    *value = READ_NET_16(element, de_get_header_size(element));
+    *value = big_endian_read_16(element, de_get_header_size(element));
     return 1;
 }
@@ -134,8 +134,8 @@
     switch (uuidSize){
         case DE_SIZE_16:
-            shortUUID = READ_NET_16(element, 1);
+            shortUUID = big_endian_read_16(element, 1);
             break;
         case DE_SIZE_32:
-            shortUUID = READ_NET_32(element, 1);
+            shortUUID = big_endian_read_32(element, 1);
             break;
         case DE_SIZE_128:
@@ -157,5 +157,5 @@
     hasBlueoothBaseUuid = sdp_has_blueooth_base_uuid(uuid128);
     if (!hasBlueoothBaseUuid) return 0;
-    return READ_NET_32(uuid128, 0);
+    return big_endian_read_32(uuid128, 0);
 }
 
@@ -199,5 +199,5 @@
 void de_pop_sequence(uint8_t * parent, uint8_t * child){
     int child_len = de_get_len(child);
-    int data_size_parent = READ_NET_16(parent,1);
+    int data_size_parent = big_endian_read_16(parent,1);
     net_store_16(parent, 1, data_size_parent + child_len);
 }
@@ -205,5 +205,5 @@
 /* adds a single number value and 16+32 bit UUID to the sequence */
 void de_add_number(uint8_t *seq, de_type_t type, de_size_t size, uint32_t value){
-    int data_size   = READ_NET_16(seq,1);
+    int data_size   = big_endian_read_16(seq,1);
     int element_size = 1;   // e.g. for DE_TYPE_NIL
     de_store_descriptor(seq+3+data_size, type, size);
@@ -231,5 +231,5 @@
 /* add a single block of data, e.g. as DE_STRING, DE_URL */
 void de_add_data( uint8_t *seq, de_type_t type, uint16_t size, uint8_t *data){
-    int data_size   = READ_NET_16(seq,1);
+    int data_size   = big_endian_read_16(seq,1);
     if (size > 0xff) {
         // use 16-bit lengh information (3 byte header)
@@ -247,5 +247,5 @@
 
 void de_add_uuid128(uint8_t * seq, uint8_t * uuid){
-    int data_size   = READ_NET_16(seq,1);
+    int data_size   = big_endian_read_16(seq,1);
     de_store_descriptor(seq+3+data_size, DE_UUID, DE_SIZE_128);
     memcpy( seq + 4 + data_size, uuid, 16);
@@ -326,5 +326,5 @@
         uint8_t done;
         if (idType != DE_UINT || idSize != DE_SIZE_16) break; // wrong type
-        attribute_id = READ_NET_16(element, pos + 1);
+        attribute_id = big_endian_read_16(element, pos + 1);
         pos += 3;
         if (pos >= end_pos) break; // array out of bounds
@@ -349,5 +349,5 @@
     switch (size) {
         case DE_SIZE_16:
-            if (READ_NET_16(element, 1) == context->attributeID) {
+            if (big_endian_read_16(element, 1) == context->attributeID) {
                 context->result = 1;
                 return 1;
@@ -355,6 +355,6 @@
             break;
         case DE_SIZE_32:
-            if (READ_NET_16(element, 1) <= context->attributeID
-            &&  context->attributeID <= READ_NET_16(element, 3)) {
+            if (big_endian_read_16(element, 1) <= context->attributeID
+            &&  context->attributeID <= big_endian_read_16(element, 3)) {
                 context->result = 1;
                 return 1;
@@ -388,5 +388,5 @@
     if (sdp_attribute_list_constains_id(context->attributeIDList, attributeID)) {
         // DES_HEADER(3) + DES_DATA + (UINT16(3) + attribute)
-        uint16_t data_size = READ_NET_16(context->buffer, 1);
+        uint16_t data_size = big_endian_read_16(context->buffer, 1);
         int attribute_len = de_get_len(attributeValue);
         if (3 + data_size + (3 + attribute_len) <= context->maxBytes) {
@@ -662,5 +662,5 @@
                 break;
             case DE_SIZE_VAR_16:
-                len = READ_NET_16(element, 1);
+                len = big_endian_read_16(element, 1);
                 break;
             default:
@@ -678,8 +678,8 @@
                 break;
             case DE_SIZE_16:
-				value = READ_NET_16(element,pos);
+				value = big_endian_read_16(element,pos);
                 break;
             case DE_SIZE_32:
-				value = READ_NET_32(element,pos);
+				value = big_endian_read_32(element,pos);
                 break;
             default:
@@ -712,5 +712,5 @@
 
 	// 0x0001 "Service Class ID List"
-	de_add_number(service,  DE_UINT, DE_SIZE_16, SDP_ServiceClassIDList);
+	de_add_number(service,  DE_UINT, DE_SIZE_16, BLUETOOTH_ATTRIBUTE_SERVICE_CLASS_ID_LIST);
 	attribute = de_push_sequence(service);
 	{
@@ -720,5 +720,5 @@
 
 	// 0x0004 "Protocol Descriptor List"
-	de_add_number(service,  DE_UINT, DE_SIZE_16, SDP_ProtocolDescriptorList);
+	de_add_number(service,  DE_UINT, DE_SIZE_16, BLUETOOTH_ATTRIBUTE_PROTOCOL_DESCRIPTOR_LIST);
 	attribute = de_push_sequence(service);
 	{
Index: asp3_tinet_ecnl_arm/trunk/btstack/src/utils.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/btstack/src/utils.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/btstack/src/utils.c	(revision 374)
@@ -49,10 +49,10 @@
 #include "debug.h"
 
-void bt_store_16(uint8_t *buffer, uint16_t pos, uint16_t value){
+void little_endian_store_16(uint8_t *buffer, uint16_t pos, uint16_t value){
     buffer[pos++] = value;
     buffer[pos++] = value >> 8;
 }
 
-void bt_store_32(uint8_t *buffer, uint16_t pos, uint32_t value){
+void little_endian_store_32(uint8_t *buffer, uint16_t pos, uint32_t value){
     buffer[pos++] = value;
     buffer[pos++] = value >> 8;
@@ -73,5 +73,5 @@
 }
 
-void bt_flip_addr(bd_addr_t dest, bd_addr_t src){
+void reverse_bd_addr(bd_addr_t src, bd_addr_t dest){
     dest[0] = src[5];
     dest[1] = src[4];
Index: asp3_tinet_ecnl_arm/trunk/musl-1.1.18/.cproject
===================================================================
--- asp3_tinet_ecnl_arm/trunk/musl-1.1.18/.cproject	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/musl-1.1.18/.cproject	(revision 374)
@@ -17,5 +17,4 @@
 					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
 					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
 					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
 					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
@@ -122,5 +121,5 @@
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="arch"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="crt"/>
-						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="src"/>
+						<entry excluding="malloc" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="src"/>
 					</sourceEntries>
 				</configuration>
@@ -144,5 +143,4 @@
 					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
 					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
 					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
 					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
@@ -232,5 +230,5 @@
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="arch"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="crt"/>
-						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="src"/>
+						<entry excluding="malloc" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="src"/>
 					</sourceEntries>
 				</configuration>
@@ -261,3 +259,4 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
 </cproject>
Index: asp3_tinet_ecnl_arm/trunk/musl-1.1.18/crt/crt1.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/musl-1.1.18/crt/crt1.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/musl-1.1.18/crt/crt1.c	(revision 374)
@@ -1,5 +1,5 @@
 #include <features.h>
 
-#define START "_start"
+#define START "musl_start"
 
 #include "crt_arch.h"
@@ -11,5 +11,5 @@
 	void (*)(), void(*)(), void(*)());
 
-void _start_c(long *p)
+void musl_start_c(long *p)
 {
 	int argc = p[0];
Index: asp3_tinet_ecnl_arm/trunk/musl-1.1.18/src/stdio/__stdio_write.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/musl-1.1.18/src/stdio/__stdio_write.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/musl-1.1.18/src/stdio/__stdio_write.c	(revision 374)
@@ -32,3 +32,4 @@
 		iov[0].iov_len -= cnt;
 	}
+	return -1;
 }
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ccsbcs.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ccsbcs.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ccsbcs.c	(revision 374)
@@ -25,5 +25,5 @@
 
 
-#if _CODE_PAGE == 437
+#if FF_CODE_PAGE == 437
 #define _TBLDEF 1
 static
@@ -39,5 +39,5 @@
 };
 
-#elif _CODE_PAGE == 720
+#elif FF_CODE_PAGE == 720
 #define _TBLDEF 1
 static
@@ -53,5 +53,5 @@
 };
 
-#elif _CODE_PAGE == 737
+#elif FF_CODE_PAGE == 737
 #define _TBLDEF 1
 static
@@ -67,5 +67,5 @@
 };
 
-#elif _CODE_PAGE == 771
+#elif FF_CODE_PAGE == 771
 #define _TBLDEF 1
 static
@@ -81,5 +81,5 @@
 };
 
-#elif _CODE_PAGE == 775
+#elif FF_CODE_PAGE == 775
 #define _TBLDEF 1
 static
@@ -95,5 +95,5 @@
 };
 
-#elif _CODE_PAGE == 850
+#elif FF_CODE_PAGE == 850
 #define _TBLDEF 1
 static
@@ -109,5 +109,5 @@
 };
 
-#elif _CODE_PAGE == 852
+#elif FF_CODE_PAGE == 852
 #define _TBLDEF 1
 static
@@ -123,5 +123,5 @@
 };
 
-#elif _CODE_PAGE == 855
+#elif FF_CODE_PAGE == 855
 #define _TBLDEF 1
 static
@@ -137,5 +137,5 @@
 };
 
-#elif _CODE_PAGE == 857
+#elif FF_CODE_PAGE == 857
 #define _TBLDEF 1
 static
@@ -151,5 +151,5 @@
 };
 
-#elif _CODE_PAGE == 860
+#elif FF_CODE_PAGE == 860
 #define _TBLDEF 1
 static
@@ -165,5 +165,5 @@
 };
 
-#elif _CODE_PAGE == 861
+#elif FF_CODE_PAGE == 861
 #define _TBLDEF 1
 static
@@ -179,5 +179,5 @@
 };
 
-#elif _CODE_PAGE == 862
+#elif FF_CODE_PAGE == 862
 #define _TBLDEF 1
 static
@@ -193,5 +193,5 @@
 };
 
-#elif _CODE_PAGE == 863
+#elif FF_CODE_PAGE == 863
 #define _TBLDEF 1
 static
@@ -207,5 +207,5 @@
 };
 
-#elif _CODE_PAGE == 864
+#elif FF_CODE_PAGE == 864
 #define _TBLDEF 1
 static
@@ -221,5 +221,5 @@
 };
 
-#elif _CODE_PAGE == 865
+#elif FF_CODE_PAGE == 865
 #define _TBLDEF 1
 static
@@ -235,5 +235,5 @@
 };
 
-#elif _CODE_PAGE == 866
+#elif FF_CODE_PAGE == 866
 #define _TBLDEF 1
 static
@@ -249,5 +249,5 @@
 };
 
-#elif _CODE_PAGE == 869
+#elif FF_CODE_PAGE == 869
 #define _TBLDEF 1
 static
@@ -266,5 +266,5 @@
 
 
-#if _CODE_PAGE != 65001 && (!_TBLDEF || !_USE_LFN)
+#if FF_CODE_PAGE != 65001 && (!_TBLDEF || !FF_USE_LFN)
 #error This file is not needed at current configuration. Remove from the project.
 #endif
@@ -272,5 +272,5 @@
 
 
-#if _CODE_PAGE != 65001
+#if FF_CODE_PAGE != 65001
 WCHAR ff_convert (	/* Converted character, Returns zero on error */
 	WCHAR	chr,	/* Character code to be converted */
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/diskio.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/diskio.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/diskio.c	(revision 374)
@@ -34,5 +34,5 @@
 int get_status(volatile RD_STAT *stat) {
 	stat->sz_sector = SS_RAMDISK;
-	if(stat->sz_sector < _MIN_SS || stat->sz_sector > _MAX_SS) return 0;
+	if(stat->sz_sector < FF_MIN_SS || stat->sz_sector > FF_MAX_SS) return 0;
 	stat->n_sectors = SZ_RAMDISK * 1024 / SS_RAMDISK;
 	stat->status = 0;
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/diskio.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/diskio.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/diskio.h	(revision 374)
@@ -60,9 +60,9 @@
 
 /* Generic command (Used by FatFs) */
-#define CTRL_SYNC			0	/* Complete pending write process (needed at _FS_READONLY == 0) */
-#define GET_SECTOR_COUNT	1	/* Get media size (needed at _USE_MKFS == 1) */
-#define GET_SECTOR_SIZE		2	/* Get sector size (needed at _MAX_SS != _MIN_SS) */
-#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at _USE_MKFS == 1) */
-#define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
+#define CTRL_SYNC			0	/* Complete pending write process (needed at FF_FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at FF_USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at FF_USE_MKFS == 1) */
+#define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
 
 /* Generic command (Not used by FatFs) */
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ff.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ff.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ff.c	(revision 374)
@@ -20,5 +20,5 @@
 #include "ff.h"			/* Declarations of FatFs API */
 #include "diskio.h"		/* Declarations of disk I/O functions */
-#include "util/ntstdio.h"
+#include <stdio.h>
 
 /*--------------------------------------------------------------------------
@@ -34,6 +34,6 @@
 
 /* Reentrancy related */
-#if _FS_REENTRANT
-#if _USE_LFN == 1
+#if FF_FS_REENTRANT
+#if FF_USE_LFN == 1
 #error Static LFN work area cannot be used at thread-safe configuration
 #endif
@@ -49,9 +49,9 @@
 
 /* Definitions of sector size */
-#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096)
+#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096)
 #error Wrong sector size configuration
 #endif
-#if _MAX_SS == _MIN_SS
-#define	SS(fs)	((UINT)_MAX_SS)	/* Fixed sector size */
+#if FF_MAX_SS == FF_MIN_SS
+#define	SS(fs)	((UINT)FF_MAX_SS)	/* Fixed sector size */
 #else
 #define	SS(fs)	((fs)->ssize)	/* Variable sector size */
@@ -60,9 +60,9 @@
 
 /* Timestamp feature */
-#if _FS_NORTC == 1
-#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31
-#error Invalid _FS_NORTC settings
-#endif
-#define GET_FATTIME()	((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16)
+#if FF_FS_NORTC == 1
+#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31
+#error Invalid FF_FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16)
 #else
 #define GET_FATTIME()	get_fattime()
@@ -71,7 +71,7 @@
 
 /* File access control feature */
-#if _FS_LOCK
-#if _FS_READONLY
-#error _FS_LOCK must be 0 at read-only configuration
+#if FF_FS_LOCK != 0
+#if FF_FS_READONLY
+#error FF_FS_LOCK must be 0 at read-only configuration
 #endif
 typedef struct {
@@ -87,5 +87,5 @@
 /* DBCS code ranges and SBCS upper conversion tables */
 
-#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#if FF_CODE_PAGE == 932	/* Japanese Shift-JIS */
 #define _DF1S	0x81	/* DBC 1st byte range 1 start */
 #define _DF1E	0x9F	/* DBC 1st byte range 1 end */
@@ -97,5 +97,5 @@
 #define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
 
-#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#elif FF_CODE_PAGE == 936	/* Simplified Chinese GBK */
 #define _DF1S	0x81
 #define _DF1E	0xFE
@@ -105,5 +105,5 @@
 #define _DS2E	0xFE
 
-#elif _CODE_PAGE == 949	/* Korean */
+#elif FF_CODE_PAGE == 949	/* Korean */
 #define _DF1S	0x81
 #define _DF1E	0xFE
@@ -115,5 +115,5 @@
 #define _DS3E	0xFE
 
-#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#elif FF_CODE_PAGE == 950	/* Traditional Chinese Big5 */
 #define _DF1S	0x81
 #define _DF1E	0xFE
@@ -123,5 +123,5 @@
 #define _DS2E	0xFE
 
-#elif _CODE_PAGE == 437	/* U.S. */
+#elif FF_CODE_PAGE == 437	/* U.S. */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
@@ -134,5 +134,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 720	/* Arabic */
+#elif FF_CODE_PAGE == 720	/* Arabic */
 #define _DF1S	0
 #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
@@ -145,5 +145,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 737	/* Greek */
+#elif FF_CODE_PAGE == 737	/* Greek */
 #define _DF1S	0
 #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
@@ -156,5 +156,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 771	/* KBL */
+#elif FF_CODE_PAGE == 771	/* KBL */
 #define _DF1S	0
 #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
@@ -167,5 +167,5 @@
 				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
 
-#elif _CODE_PAGE == 775	/* Baltic */
+#elif FF_CODE_PAGE == 775	/* Baltic */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
@@ -178,5 +178,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 850	/* Latin 1 */
+#elif FF_CODE_PAGE == 850	/* Latin 1 */
 #define _DF1S	0
 #define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
@@ -189,5 +189,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 852	/* Latin 2 */
+#elif FF_CODE_PAGE == 852	/* Latin 2 */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
@@ -200,5 +200,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
 
-#elif _CODE_PAGE == 855	/* Cyrillic */
+#elif FF_CODE_PAGE == 855	/* Cyrillic */
 #define _DF1S	0
 #define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
@@ -211,5 +211,5 @@
 				0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 857	/* Turkish */
+#elif FF_CODE_PAGE == 857	/* Turkish */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
@@ -222,5 +222,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 860	/* Portuguese */
+#elif FF_CODE_PAGE == 860	/* Portuguese */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
@@ -233,5 +233,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 861	/* Icelandic */
+#elif FF_CODE_PAGE == 861	/* Icelandic */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
@@ -244,5 +244,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 862	/* Hebrew */
+#elif FF_CODE_PAGE == 862	/* Hebrew */
 #define _DF1S	0
 #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
@@ -255,5 +255,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 863	/* Canadian-French */
+#elif FF_CODE_PAGE == 863	/* Canadian-French */
 #define _DF1S	0
 #define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
@@ -266,5 +266,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 864	/* Arabic */
+#elif FF_CODE_PAGE == 864	/* Arabic */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
@@ -277,5 +277,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 865	/* Nordic */
+#elif FF_CODE_PAGE == 865	/* Nordic */
 #define _DF1S	0
 #define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
@@ -288,5 +288,5 @@
 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 866	/* Russian */
+#elif FF_CODE_PAGE == 866	/* Russian */
 #define _DF1S	0
 #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
@@ -299,5 +299,5 @@
 				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
 
-#elif _CODE_PAGE == 869	/* Greek 2 */
+#elif FF_CODE_PAGE == 869	/* Greek 2 */
 #define _DF1S	0
 #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
@@ -310,12 +310,12 @@
 				0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
 
-#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
-#if _USE_LFN
+#elif FF_CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#if FF_USE_LFN
 #error Cannot use LFN feature without valid code page.
 #endif
 #define _DF1S	0
 
-#elif _CODE_PAGE == 65001 /* UTF-8 */
-#if _LFN_UNICODE
+#elif FF_CODE_PAGE == 65001 /* UTF-8 */
+#if FF_LFN_UNICODE
 #error Cannot use LFN_UNICODE feature without valid code page.
 #endif
@@ -532,41 +532,41 @@
 */
 
-#if _VOLUMES < 1 || _VOLUMES > 9
-#error Wrong _VOLUMES setting
-#endif
-static FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
+#if FF_VOLUMES < 1 || FF_VOLUMES > 9
+#error Wrong FF_VOLUMES setting
+#endif
+static FATFS *FatFs[FF_VOLUMES];	/* Pointer to the file system objects (logical drives) */
 static WORD Fsid;				/* File system mount ID */
 
-#if _FS_RPATH && _VOLUMES >= 2
+#if FF_FS_RPATH && FF_VOLUMES >= 2
 static BYTE CurrVol;			/* Current drive */
 #endif
 
-#if _FS_LOCK
-static FILESEM Files[_FS_LOCK];	/* Open object lock semaphores */
-#endif
-
-#if _USE_LFN == 0			/* Non LFN feature */
+#if FF_FS_LOCK != 0
+static FILESEM Files[FF_FS_LOCK];	/* Open object lock semaphores */
+#endif
+
+#if FF_USE_LFN == 0			/* Non LFN feature */
 #define	DEFINE_NAMEBUF		BYTE sfn[12]
 #define INIT_BUF(dobj)		(dobj).fn = sfn
 #define	FREE_BUF()
 #else
-#if _MAX_LFN < 12 || _MAX_LFN > 255
-#error Wrong _MAX_LFN setting
-#endif
-#if _USE_LFN == 1			/* LFN feature with static working buffer */
-static WCHAR LfnBuf[_MAX_LFN + 1];
+#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255
+#error Wrong FF_MAX_LFN setting
+#endif
+#if FF_USE_LFN == 1			/* LFN feature with static working buffer */
+static WCHAR LfnBuf[FF_MAX_LFN + 1];
 #define	DEFINE_NAMEBUF		BYTE sfn[12]
 #define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
 #define	FREE_BUF()
-#elif _USE_LFN == 2 		/* LFN feature with dynamic working buffer on the stack */
-#define	DEFINE_NAMEBUF		BYTE sfn[12]; WCHAR lbuf[_MAX_LFN + 1]
+#elif FF_USE_LFN == 2 		/* LFN feature with dynamic working buffer on the stack */
+#define	DEFINE_NAMEBUF		BYTE sfn[12]; WCHAR lbuf[FF_MAX_LFN + 1]
 #define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = lbuf; }
 #define	FREE_BUF()
-#elif _USE_LFN == 3 		/* LFN feature with dynamic working buffer on the heap */
+#elif FF_USE_LFN == 3 		/* LFN feature with dynamic working buffer on the heap */
 #define	DEFINE_NAMEBUF		BYTE sfn[12]; WCHAR *lfn
-#define INIT_BUF(dobj)		{ lfn = ff_memalloc((_MAX_LFN + 1) * 2); if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define INIT_BUF(dobj)		{ lfn = ff_memalloc((FF_MAX_LFN + 1) * 2); if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); (dobj).lfn = lfn; (dobj).fn = sfn; }
 #define	FREE_BUF()			ff_memfree(lfn)
 #else
-#error Wrong _USE_LFN setting
+#error Wrong FF_USE_LFN setting
 #endif
 #endif
@@ -598,5 +598,5 @@
 	const BYTE *s = (const BYTE*)src;
 
-#if _WORD_ACCESS == 1
+#if FF_WORD_ACCESS == 1
 	while (cnt >= sizeof (int)) {
 		*(int*)d = *(int*)s;
@@ -641,5 +641,5 @@
 /* Request/Release grant to access the volume                            */
 /*-----------------------------------------------------------------------*/
-#if _FS_REENTRANT
+#if FF_FS_REENTRANT
 static
 int lock_fs (
@@ -673,9 +673,9 @@
 /* File lock control functions                                           */
 /*-----------------------------------------------------------------------*/
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 
 static
 FRESULT chk_lock (	/* Check if the file can be accessed */
-	DIR* dp,		/* Directory object pointing the file to be checked */
+	FATFS_DIR* dp,		/* Directory object pointing the file to be checked */
 	int acc			/* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
 )
@@ -684,5 +684,5 @@
 
 	/* Search file semaphore table */
-	for (i = be = 0; i < _FS_LOCK; i++) {
+	for (i = be = 0; i < FF_FS_LOCK; i++) {
 		if (Files[i].fs) {	/* Existing entry */
 			if (Files[i].fs == dp->fs &&	 	/* Check if the object matched with an open object */
@@ -693,5 +693,5 @@
 		}
 	}
-	if (i == _FS_LOCK)	/* The object is not opened */
+	if (i == FF_FS_LOCK)	/* The object is not opened */
 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new object? */
 
@@ -706,6 +706,6 @@
 	UINT i;
 
-	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
-	return (i == _FS_LOCK) ? 0 : 1;
+	for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;
+	return (i == FF_FS_LOCK) ? 0 : 1;
 }
 
@@ -713,5 +713,5 @@
 static
 UINT inc_lock (	/* Increment object open counter and returns its index (0:Internal error) */
-	DIR* dp,	/* Directory object pointing the file to register or increment */
+	FATFS_DIR* dp,	/* Directory object pointing the file to register or increment */
 	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
 )
@@ -720,5 +720,5 @@
 
 
-	for (i = 0; i < _FS_LOCK; i++) {	/* Find the object */
+	for (i = 0; i < FF_FS_LOCK; i++) {	/* Find the object */
 		if (Files[i].fs == dp->fs &&
 			Files[i].clu == dp->sclust &&
@@ -726,7 +726,7 @@
 	}
 
-	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
-		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
-		if (i == _FS_LOCK) return 0;	/* No free entry to register (int err) */
+	if (i == FF_FS_LOCK) {				/* Not opened. Register it as new. */
+		for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;
+		if (i == FF_FS_LOCK) return 0;	/* No free entry to register (int err) */
 		Files[i].fs = dp->fs;
 		Files[i].clu = dp->sclust;
@@ -752,5 +752,5 @@
 
 
-	if (--i < _FS_LOCK) {	/* Shift index number origin from 0 */
+	if (--i < FF_FS_LOCK) {	/* Shift index number origin from 0 */
 		n = Files[i].ctr;
 		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
@@ -773,5 +773,5 @@
 	UINT i;
 
-	for (i = 0; i < _FS_LOCK; i++) {
+	for (i = 0; i < FF_FS_LOCK; i++) {
 		if (Files[i].fs == fs) Files[i].fs = 0;
 	}
@@ -785,5 +785,5 @@
 /* Move/Flush disk access window in the file system object               */
 /*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 FRESULT sync_window (	/* FR_OK:succeeded, !=0:error */
@@ -825,5 +825,5 @@
 
 	if (sector != fs->winsect) {	/* Window offset changed? */
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 		res = sync_window(fs);		/* Write-back changes */
 #endif
@@ -845,5 +845,5 @@
 /* Synchronize file system and strage device                             */
 /*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 FRESULT sync_fs (	/* FR_OK:succeeded, !=0:error */
@@ -959,5 +959,5 @@
 /* Hidden API for hacks and disk tools */
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
 	FATFS* fs,		/* File system object */
@@ -1014,5 +1014,5 @@
 	return res;
 }
-#endif /* !_FS_READONLY */
+#endif /* !FF_FS_READONLY */
 
 
@@ -1022,5 +1022,5 @@
 /* FAT handling - Remove a cluster chain                                 */
 /*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
@@ -1031,5 +1031,5 @@
 	FRESULT res;
 	DWORD nxt;
-#if _USE_TRIM
+#if FF_USE_TRIM
 	DWORD scl = clst, ecl = clst, rt[2];
 #endif
@@ -1051,5 +1051,5 @@
 				fs->fsi_flag |= 1;
 			}
-#if _USE_TRIM
+#if FF_USE_TRIM
 			if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
 				ecl = nxt;
@@ -1075,5 +1075,5 @@
 /* FAT handling - Stretch or Create a cluster chain                      */
 /*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
@@ -1128,5 +1128,5 @@
 	return ncl;		/* Return new cluster number or error code */
 }
-#endif /* !_FS_READONLY */
+#endif /* !FF_FS_READONLY */
 
 
@@ -1137,5 +1137,5 @@
 /*-----------------------------------------------------------------------*/
 
-#if _USE_FASTSEEK
+#if FF_USE_FASTSEEK
 static
 DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
@@ -1157,5 +1157,5 @@
 	return cl + *tbl;	/* Return the cluster number */
 }
-#endif	/* _USE_FASTSEEK */
+#endif	/* FF_USE_FASTSEEK */
 
 
@@ -1168,5 +1168,5 @@
 static
 FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
-	DIR* dp,		/* Pointer to directory object */
+	FATFS_DIR* dp,		/* Pointer to directory object */
 	UINT idx		/* Index of directory table */
 )
@@ -1216,5 +1216,5 @@
 static
 FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
-	DIR* dp,		/* Pointer to the directory object */
+	FATFS_DIR* dp,		/* Pointer to the directory object */
 	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
 )
@@ -1222,5 +1222,5 @@
 	DWORD clst;
 	UINT i;
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 	UINT c;
 #endif
@@ -1244,5 +1244,5 @@
 				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
 				if (clst >= dp->fs->n_fatent) {					/* If it reached end of dynamic table, */
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 					if (!stretch) return FR_NO_FILE;			/* If do not stretch, report EOT */
 					clst = create_chain(dp->fs, dp->clust);		/* Stretch cluster chain */
@@ -1284,8 +1284,8 @@
 /*-----------------------------------------------------------------------*/
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
-	DIR* dp,		/* Pointer to the directory object */
+	FATFS_DIR* dp,		/* Pointer to the directory object */
 	UINT nent		/* Number of contiguous entries to allocate (1-21) */
 )
@@ -1337,5 +1337,5 @@
 
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 void st_clust (
@@ -1355,5 +1355,5 @@
 /* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry   */
 /*-----------------------------------------------------------------------*/
-#if _USE_LFN
+#if FF_USE_LFN
 static
 const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN characters in the directory entry */
@@ -1377,5 +1377,5 @@
 		uc = LD_WORD(dir + LfnOfs[s]);		/* Pick an LFN character */
 		if (wc) {
-			if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++]))	/* Compare it */
+			if (i >= FF_MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++]))	/* Compare it */
 				return 0;					/* Not matched */
 			wc = uc;
@@ -1410,5 +1410,5 @@
 		uc = LD_WORD(dir + LfnOfs[s]);		/* Pick an LFN character */
 		if (wc) {
-			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
+			if (i >= FF_MAX_LFN) return 0;	/* Buffer overflow? */
 			lfnbuf[i++] = wc = uc;			/* Store it */
 		} else {
@@ -1418,5 +1418,5 @@
 
 	if (dir[LDIR_Ord] & LLEF) {				/* Put terminator if it is the last LFN part */
-		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
+		if (i >= FF_MAX_LFN) return 0;		/* Buffer overflow? */
 		lfnbuf[i] = 0;
 	}
@@ -1426,5 +1426,5 @@
 
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 void fit_lfn (
@@ -1464,5 +1464,5 @@
 /* Create numbered name                                                  */
 /*-----------------------------------------------------------------------*/
-#if _USE_LFN
+#if FF_USE_LFN
 static
 void gen_numname (
@@ -1523,5 +1523,5 @@
 /* Calculate checksum of an SFN entry                                    */
 /*-----------------------------------------------------------------------*/
-#if _USE_LFN
+#if FF_USE_LFN
 static
 BYTE sum_sfn (
@@ -1546,10 +1546,10 @@
 static
 FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
-	DIR* dp			/* Pointer to the directory object linked to the file name */
+	FATFS_DIR* dp			/* Pointer to the directory object linked to the file name */
 )
 {
 	FRESULT res;
 	BYTE c, *dir;
-#if _USE_LFN
+#if FF_USE_LFN
 	BYTE a, ord, sum;
 #endif
@@ -1558,5 +1558,5 @@
 	if (res != FR_OK) return res;
 
-#if _USE_LFN
+#if FF_USE_LFN
 	ord = sum = 0xFF; dp->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
 #endif
@@ -1567,5 +1567,5 @@
 		c = dir[DIR_Name];
 		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
-#if _USE_LFN	/* LFN configuration */
+#if FF_USE_LFN	/* LFN configuration */
 		a = dir[DIR_Attr] & AM_MASK;
 		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
@@ -1604,8 +1604,8 @@
 /* Read an object from the directory                                     */
 /*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2
+#if FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2
 static
 FRESULT dir_read (
-	DIR* dp,		/* Pointer to the directory object */
+	FATFS_DIR* dp,		/* Pointer to the directory object */
 	int vol			/* Filtered by 0:file/directory or 1:volume label */
 )
@@ -1613,5 +1613,5 @@
 	FRESULT res;
 	BYTE a, c, *dir;
-#if _USE_LFN
+#if FF_USE_LFN
 	BYTE ord = 0xFF, sum = 0xFF;
 #endif
@@ -1625,6 +1625,6 @@
 		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
 		a = dir[DIR_Attr] & AM_MASK;
-#if _USE_LFN	/* LFN configuration */
-		if (c == DDEM || (!_FS_RPATH && c == '.') || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+#if FF_USE_LFN	/* LFN configuration */
+		if (c == DDEM || (!FF_FS_RPATH && c == '.') || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
 			ord = 0xFF;
 		} else {
@@ -1644,5 +1644,5 @@
 		}
 #else		/* Non LFN configuration */
-		if (c != DDEM && (_FS_RPATH || c != '.') && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol)	/* Is it a valid entry? */
+		if (c != DDEM && (FF_FS_RPATH || c != '.') && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol)	/* Is it a valid entry? */
 			break;
 #endif
@@ -1655,5 +1655,5 @@
 	return res;
 }
-#endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
+#endif	/* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */
 
 
@@ -1663,12 +1663,12 @@
 /* Register an object to the directory                                   */
 /*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 static
 FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
-	DIR* dp				/* Target directory with object name to be created */
+	FATFS_DIR* dp				/* Target directory with object name to be created */
 )
 {
 	FRESULT res;
-#if _USE_LFN	/* LFN configuration */
+#if FF_USE_LFN	/* LFN configuration */
 	UINT n, nent;
 	BYTE sn[12], *fn, sum;
@@ -1679,5 +1679,5 @@
 	mem_cpy(sn, fn, 12);
 
-	if (_FS_RPATH && (sn[NSFLAG] & NS_DOT))		/* Cannot create dot entry */
+	if (FF_FS_RPATH && (sn[NSFLAG] & NS_DOT))		/* Cannot create dot entry */
 		return FR_INVALID_NAME;
 
@@ -1724,5 +1724,5 @@
 			mem_set(dp->dir, 0, SZ_DIRE);	/* Clean the entry */
 			mem_cpy(dp->dir, dp->fn, 11);	/* Put SFN */
-#if _USE_LFN
+#if FF_USE_LFN
 			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
 #endif
@@ -1733,5 +1733,5 @@
 	return res;
 }
-#endif /* !_FS_READONLY */
+#endif /* !FF_FS_READONLY */
 
 
@@ -1741,12 +1741,12 @@
 /* Remove an object from the directory                                   */
 /*-----------------------------------------------------------------------*/
-#if !_FS_READONLY && !_FS_MINIMIZE
+#if !FF_FS_READONLY && !FF_FS_MINIMIZE
 static
 FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
-	DIR* dp				/* Directory object pointing the entry to be removed */
+	FATFS_DIR* dp				/* Directory object pointing the entry to be removed */
 )
 {
 	FRESULT res;
-#if _USE_LFN	/* LFN configuration */
+#if FF_USE_LFN	/* LFN configuration */
 	UINT i;
 
@@ -1780,5 +1780,5 @@
 	return res;
 }
-#endif /* !_FS_READONLY */
+#endif /* !FF_FS_READONLY */
 
 
@@ -1788,8 +1788,8 @@
 /* Get file information from directory entry                             */
 /*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2
 static
 void get_fileinfo (		/* No return code */
-	DIR* dp,			/* Pointer to the directory object */
+	FATFS_DIR* dp,			/* Pointer to the directory object */
 	FILINFO* fno	 	/* Pointer to the file information to be filled */
 )
@@ -1798,8 +1798,8 @@
 	TCHAR *p, c;
 	BYTE *dir;
-#if _USE_LFN
+#if FF_USE_LFN
 	WCHAR w, *lfn;
 #endif
-#if _CODE_PAGE == 65001
+#if FF_CODE_PAGE == 65001
 	unsigned char utf8_code[6];
 	int code_size;
@@ -1815,8 +1815,8 @@
 			if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
 			if (i == 9) *p++ = '.';				/* Insert a . if extension is exist */
-#if _USE_LFN
+#if FF_USE_LFN
 			if (IsUpper(c) && (dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY)))
 				c += 0x20;			/* To lower */
-#if _LFN_UNICODE
+#if FF_LFN_UNICODE
 			if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dir[i]))
 				c = c << 8 | dir[i++];
@@ -1834,5 +1834,5 @@
 	*p = 0;		/* Terminate SFN string by a \0 */
 
-#if _USE_LFN
+#if FF_USE_LFN
 	if (fno->lfname) {
 		i = 0; p = fno->lfname;
@@ -1840,6 +1840,6 @@
 			lfn = dp->lfn;
 			while ((w = *lfn++) != 0) {		/* Get an LFN character */
-#if !_LFN_UNICODE
-#if _CODE_PAGE == 65001
+#if !FF_LFN_UNICODE
+#if FF_CODE_PAGE == 65001
 				Utf16_to_Utf8(utf8_code, &code_size, w);
 				for (int j = 0; j < code_size - 1; j++) {
@@ -1862,5 +1862,5 @@
 #endif
 }
-#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */
 
 
@@ -1870,5 +1870,5 @@
 /* Pattern matching                                                      */
 /*-----------------------------------------------------------------------*/
-#if _USE_FIND && _FS_MINIMIZE <= 1
+#if FF_USE_FIND && FF_FS_MINIMIZE <= 1
 static
 WCHAR get_achar (		/* Get a character and advances ptr 1 or 2 */
@@ -1878,6 +1878,6 @@
 	WCHAR chr;
 
-#if !_LFN_UNICODE
-#if _CODE_PAGE == 65001
+#if !FF_LFN_UNICODE
+#if FF_CODE_PAGE == 65001
 	int code_size;
 	chr = Utf8_to_Utf16(*ptr, &code_size);
@@ -1938,5 +1938,5 @@
 	return 0;
 }
-#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */
+#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */
 
 
@@ -1949,14 +1949,14 @@
 static
 FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
-	DIR* dp,			/* Pointer to the directory object */
+	FATFS_DIR* dp,			/* Pointer to the directory object */
 	const TCHAR** path	/* Pointer to pointer to the segment in the path string */
 )
 {
-#if _USE_LFN	/* LFN configuration */
+#if FF_USE_LFN	/* LFN configuration */
 	BYTE b, cf;
 	WCHAR w, *lfn;
 	UINT i, ni, si, di;
 	const TCHAR *p;
-#if _CODE_PAGE == 65001
+#if FF_CODE_PAGE == 65001
 	unsigned char utf8_code[6];
 	int code_size;
@@ -1969,8 +1969,8 @@
 		w = p[si++];					/* Get a character */
 		if (w < ' ' || w == '/' || w == '\\') break;	/* Break on end of segment */
-		if (di >= _MAX_LFN)				/* Reject too long name */
+		if (di >= FF_MAX_LFN)				/* Reject too long name */
 			return FR_INVALID_NAME;
-#if !_LFN_UNICODE
-#if _CODE_PAGE == 65001
+#if !FF_LFN_UNICODE
+#if FF_CODE_PAGE == 65001
 		w = Utf8_to_Utf16(&p[si - 1], &code_size);
 		si += code_size - 1;
@@ -1993,5 +1993,5 @@
 	*path = &p[si];						/* Return pointer to the next segment */
 	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of path */
-#if _FS_RPATH
+#if FF_FS_RPATH
 	if ((di == 1 && lfn[di - 1] == '.') ||
 		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot entry? */
@@ -2040,5 +2040,5 @@
 			if (w) w = ExCvt[w - 0x80];	/* Convert extended character to upper (SBCS) */
 #else
-#if _CODE_PAGE == 65001
+#if FF_CODE_PAGE == 65001
 			Utf16_to_Utf8(utf8_code, &code_size, ff_wtoupper(w));
 #else
@@ -2048,10 +2048,10 @@
 			cf |= NS_LFN;				/* Force create LFN entry */
 		}
-#if _CODE_PAGE == 65001
+#if FF_CODE_PAGE == 65001
 		else
 			code_size = 1;
 #endif
 
-#if _CODE_PAGE == 65001
+#if FF_CODE_PAGE == 65001
 		if (code_size > 1) {		/* Is this DBC? (always false at SBCS cfg) */
 			if (i >= ni - 1) {
@@ -2126,5 +2126,5 @@
 	mem_set(sfn, ' ', 11);
 	si = i = b = 0; ni = 8;
-#if _FS_RPATH
+#if FF_FS_RPATH
 	if (p[si] == '.') { /* Is this a dot entry? */
 		for (;;) {
@@ -2201,5 +2201,5 @@
 static
 FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
-	DIR* dp,			/* Directory object to return last directory and found object */
+	FATFS_DIR* dp,			/* Directory object to return last directory and found object */
 	const TCHAR* path	/* Full-path string to find a file or directory */
 )
@@ -2209,5 +2209,5 @@
 
 
-#if _FS_RPATH
+#if FF_FS_RPATH
 	if (*path == '/' || *path == '\\') {	/* There is a heading separator */
 		path++;	dp->sclust = 0;				/* Strip it and start from the root directory */
@@ -2232,5 +2232,5 @@
 			if (res != FR_OK) {				/* Failed to find the object */
 				if (res == FR_NO_FILE) {	/* Object is not found */
-					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, */
+					if (FF_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, */
 						dp->sclust = 0; dp->dir = 0;	/* it is the root directory and stay there */
 						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
@@ -2269,6 +2269,6 @@
 	UINT i;
 	int vol = -1;
-#if _STR_VOLUME_ID		/* Find string drive id */
-	static const char* const str[] = {_VOLUME_STRS};
+#if FF_STR_VOLUME_ID		/* Find string drive id */
+	static const char* const str[] = {FF_VOLUME_STRS};
 	const char *sp;
 	char c;
@@ -2278,15 +2278,15 @@
 
 	if (*path) {	/* If the pointer is not a null */
-		for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the path */
+		for (tt = *path; (UINT)*tt >= (FF_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the path */
 		if (*tt == ':') {	/* If a ':' is exist in the path name */
 			tp = *path;
 			i = *tp++ - '0'; 
 			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
-				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+				if (i < FF_VOLUMES) {	/* If a drive id is found, get the value and strip it */
 					vol = (int)i;
 					*path = ++tt;
 				}
 			}
-#if _STR_VOLUME_ID
+#if FF_STR_VOLUME_ID
 			 else {	/* No numeric drive number, find string drive id */
 				i = 0; tt++;
@@ -2297,6 +2297,6 @@
 						if (IsLower(tc)) tc -= 0x20;
 					} while (c && (TCHAR)c == tc);
-				} while ((c || tp != tt) && ++i < _VOLUMES);	/* Repeat for each id until pattern match */
-				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+				} while ((c || tp != tt) && ++i < FF_VOLUMES);	/* Repeat for each id until pattern match */
+				if (i < FF_VOLUMES) {	/* If a drive id is found, get the value and strip it */
 					vol = (int)i;
 					*path = tt;
@@ -2306,5 +2306,5 @@
 			return vol;
 		}
-#if _FS_RPATH && _VOLUMES >= 2
+#if FF_FS_RPATH && FF_VOLUMES >= 2
 		vol = CurrVol;	/* Current drive */
 #else
@@ -2381,5 +2381,5 @@
 		stat = disk_status(fs->drv);
 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
-			if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check write protection if needed */
+			if (!FF_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check write protection if needed */
 				return FR_WRITE_PROTECTED;
 			return FR_OK;				/* The file system object is valid */
@@ -2395,9 +2395,9 @@
 	if (stat & STA_NOINIT)				/* Check if the initialization succeeded */
 		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
-	if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check disk write protection if needed */
+	if (!FF_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check disk write protection if needed */
 		return FR_WRITE_PROTECTED;
-#if _MAX_SS != _MIN_SS						/* Get sector size (multiple sector size cfg only) */
+#if FF_MAX_SS != FF_MIN_SS						/* Get sector size (multiple sector size cfg only) */
 	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK
-		|| SS(fs) < _MIN_SS || SS(fs) > _MAX_SS) return FR_DISK_ERR;
+		|| SS(fs) < FF_MIN_SS || SS(fs) > FF_MAX_SS) return FR_DISK_ERR;
 #endif
 	/* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */
@@ -2448,5 +2448,5 @@
 
 	/* Determine the FAT sub type */
-	sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIRE);	/* RSV + FAT + DIR */
+	sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIRE);	/* RSV + FAT + FATFS_DIR */
 	if (tsect < sysect) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
 	nclst = (tsect - sysect) / fs->csize;				/* Number of clusters */
@@ -2474,5 +2474,5 @@
 		return FR_NO_FILESYSTEM;
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 	/* Initialize cluster allocation information */
 	fs->last_clust = fs->free_clust = 0xFFFFFFFF;
@@ -2480,5 +2480,5 @@
 	/* Get fsinfo if available */
 	fs->fsi_flag = 0x80;
-#if (_FS_NOFSINFO & 3) != 3
+#if (FF_FS_NOFSINFO & 3) != 3
 	if (fmt == FS_FAT32				/* Enable FSINFO only if FAT32 and BPB_FSInfo == 1 */
 		&& LD_WORD(fs->win + BPB_FSInfo) == 1
@@ -2490,8 +2490,8 @@
 			&& LD_DWORD(fs->win + FSI_StrucSig) == 0x61417272)
 		{
-#if (_FS_NOFSINFO & 1) == 0
+#if (FF_FS_NOFSINFO & 1) == 0
 			fs->free_clust = LD_DWORD(fs->win + FSI_Free_Count);
 #endif
-#if (_FS_NOFSINFO & 2) == 0
+#if (FF_FS_NOFSINFO & 2) == 0
 			fs->last_clust = LD_DWORD(fs->win + FSI_Nxt_Free);
 #endif
@@ -2502,8 +2502,8 @@
 	fs->fs_type = fmt;	/* FAT sub-type */
 	fs->id = ++Fsid;	/* File system mount ID */
-#if _FS_RPATH
+#if FF_FS_RPATH
 	fs->cdir = 0;		/* Set current directory to root */
 #endif
-#if _FS_LOCK			/* Clear file lock semaphores */
+#if FF_FS_LOCK != 0			/* Clear file lock semaphores */
 	clear_lock(fs);
 #endif
@@ -2521,8 +2521,8 @@
 static
 FRESULT validate (	/* FR_OK(0): The object is valid, !=0: Invalid */
-	void* obj		/* Pointer to the object FIL/DIR to check validity */
-)
-{
-	FIL *fil = (FIL*)obj;	/* Assuming offset of .fs and .id in the FIL/DIR structure is identical */
+	void* obj		/* Pointer to the object FIL/FATFS_DIR to check validity */
+)
+{
+	FIL *fil = (FIL*)obj;	/* Assuming offset of .fs and .id in the FIL/FATFS_DIR structure is identical */
 
 
@@ -2567,8 +2567,8 @@
 
 	if (cfs) {
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 		clear_lock(cfs);
 #endif
-#if _FS_REENTRANT						/* Discard sync object of the current volume */
+#if FF_FS_REENTRANT						/* Discard sync object of the current volume */
 		if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
 #endif
@@ -2578,5 +2578,5 @@
 	if (fs) {
 		fs->fs_type = 0;				/* Clear new fs object */
-#if _FS_REENTRANT						/* Create sync object for the new volume */
+#if FF_FS_REENTRANT						/* Create sync object for the new volume */
 		if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
 #endif
@@ -2604,8 +2604,8 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	BYTE *dir;
 	DEFINE_NAMEBUF;
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 	DWORD dw, cl;
 #endif
@@ -2616,6 +2616,6 @@
 
 	/* Get logical drive number */
-#if !_FS_READONLY
-	mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
+#if !FF_FS_READONLY
+	mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW | FA_OPEN_APPEND;
 	res = find_volume(&dj.fs, &path, (BYTE)(mode & ~FA_READ));
 #else
@@ -2627,9 +2627,9 @@
 		res = follow_path(&dj, path);	/* Follow the file path */
 		dir = dj.dir;
-#if !_FS_READONLY	/* R/W configuration */
+#if !FF_FS_READONLY	/* R/W configuration */
 		if (res == FR_OK) {
 			if (!dir)	/* Default directory itself */
 				res = FR_INVALID_NAME;
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 			else
 				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
@@ -2640,5 +2640,5 @@
 			if (res != FR_OK) {					/* No file, create new */
 				if (res == FR_NO_FILE)			/* There is no file to open, create a new entry */
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
 #else
@@ -2649,5 +2649,5 @@
 			}
 			else {								/* Any object is already existing */
-				if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+				if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or FATFS_DIR) */
 					res = FR_DENIED;
 				} else {
@@ -2687,8 +2687,8 @@
 		if (res == FR_OK) {
 			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
-				mode |= FA__WRITTEN;
+				mode |= FA_MODIFIED;
 			fp->dir_sect = dj.fs->winsect;		/* Pointer to the directory entry */
 			fp->dir_ptr = dir;
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 			fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
 			if (!fp->lockid) res = FR_INT_ERR;
@@ -2716,5 +2716,5 @@
 			fp->fptr = 0;						/* File pointer */
 			fp->dsect = 0;
-#if _USE_FASTSEEK
+#if FF_USE_FASTSEEK
 			fp->cltbl = 0;						/* Normal seek mode */
 #endif
@@ -2766,5 +2766,5 @@
 					clst = fp->sclust;			/* Follow from the origin */
 				} else {						/* Middle or end of the file */
-#if _USE_FASTSEEK
+#if FF_USE_FASTSEEK
 					if (fp->cltbl)
 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
@@ -2786,10 +2786,10 @@
 				if (disk_read(fp->fs->drv, rbuff, sect, cc) != RES_OK)
 					ABORT(fp->fs, FR_DISK_ERR);
-#if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
-#if _FS_TINY
+#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if FF_FS_TINY
 				if (fp->fs->wflag && fp->fs->winsect - sect < cc)
 					mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
 #else
-				if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
+				if ((fp->flag & FA_DIRTY) && fp->dsect - sect < cc)
 					mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
 #endif
@@ -2798,11 +2798,11 @@
 				continue;
 			}
-#if !_FS_TINY
+#if !FF_FS_TINY
 			if (fp->dsect != sect) {			/* Load data sector if not in cache */
-#if !_FS_READONLY
-				if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
+#if !FF_FS_READONLY
+				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
 					if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
 						ABORT(fp->fs, FR_DISK_ERR);
-					fp->flag &= ~FA__DIRTY;
+					fp->flag &= ~FA_DIRTY;
 				}
 #endif
@@ -2815,5 +2815,5 @@
 		rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));	/* Get partial sector data from sector buffer */
 		if (rcnt > btr) rcnt = btr;
-#if _FS_TINY
+#if FF_FS_TINY
 		if (move_window(fp->fs, fp->dsect) != FR_OK)		/* Move sector window */
 			ABORT(fp->fs, FR_DISK_ERR);
@@ -2830,5 +2830,5 @@
 
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 /*-----------------------------------------------------------------------*/
 /* Write File                                                            */
@@ -2869,5 +2869,5 @@
 						clst = create_chain(fp->fs, 0);	/* Create a new cluster chain */
 				} else {					/* Middle or end of the file */
-#if _USE_FASTSEEK
+#if FF_USE_FASTSEEK
 					if (fp->cltbl)
 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
@@ -2882,12 +2882,12 @@
 				if (fp->sclust == 0) fp->sclust = clst;	/* Set start cluster if the first write */
 			}
-#if _FS_TINY
+#if FF_FS_TINY
 			if (fp->fs->winsect == fp->dsect && sync_window(fp->fs))	/* Write-back sector cache */
 				ABORT(fp->fs, FR_DISK_ERR);
 #else
-			if (fp->flag & FA__DIRTY) {		/* Write-back sector cache */
+			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
 				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
 					ABORT(fp->fs, FR_DISK_ERR);
-				fp->flag &= ~FA__DIRTY;
+				fp->flag &= ~FA_DIRTY;
 			}
 #endif
@@ -2901,6 +2901,6 @@
 				if (disk_write(fp->fs->drv, wbuff, sect, cc) != RES_OK)
 					ABORT(fp->fs, FR_DISK_ERR);
-#if _FS_MINIMIZE <= 2
-#if _FS_TINY
+#if FF_FS_MINIMIZE <= 2
+#if FF_FS_TINY
 				if (fp->fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
 					mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
@@ -2910,5 +2910,5 @@
 				if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
 					mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
-					fp->flag &= ~FA__DIRTY;
+					fp->flag &= ~FA_DIRTY;
 				}
 #endif
@@ -2917,5 +2917,5 @@
 				continue;
 			}
-#if _FS_TINY
+#if FF_FS_TINY
 			if (fp->fptr >= fp->fsize) {	/* Avoid silly cache filling at growing edge */
 				if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR);
@@ -2933,5 +2933,5 @@
 		wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
 		if (wcnt > btw) wcnt = btw;
-#if _FS_TINY
+#if FF_FS_TINY
 		if (move_window(fp->fs, fp->dsect) != FR_OK)	/* Move sector window */
 			ABORT(fp->fs, FR_DISK_ERR);
@@ -2940,10 +2940,10 @@
 #else
 		mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt);	/* Fit partial sector */
-		fp->flag |= FA__DIRTY;
+		fp->flag |= FA_DIRTY;
 #endif
 	}
 
 	if (fp->fptr > fp->fsize) fp->fsize = fp->fptr;	/* Update file size if needed */
-	fp->flag |= FA__WRITTEN;						/* Set file change flag */
+	fp->flag |= FA_MODIFIED;						/* Set file change flag */
 
 	LEAVE_FF(fp->fs, FR_OK);
@@ -2968,10 +2968,10 @@
 	res = validate(fp);					/* Check validity of the object */
 	if (res == FR_OK) {
-		if (fp->flag & FA__WRITTEN) {	/* Is there any change to the file? */
-#if !_FS_TINY
-			if (fp->flag & FA__DIRTY) {	/* Write-back cached data if needed */
+		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+#if !FF_FS_TINY
+			if (fp->flag & FA_DIRTY) {	/* Write-back cached data if needed */
 				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
 					LEAVE_FF(fp->fs, FR_DISK_ERR);
-				fp->flag &= ~FA__DIRTY;
+				fp->flag &= ~FA_DIRTY;
 			}
 #endif
@@ -2986,5 +2986,5 @@
 				ST_DWORD(dir + DIR_WrtTime, tm);
 				ST_WORD(dir + DIR_LstAccDate, 0);
-				fp->flag &= ~FA__WRITTEN;
+				fp->flag &= ~FA_MODIFIED;
 				fp->fs->wflag = 1;
 				res = sync_fs(fp->fs);
@@ -2996,5 +2996,5 @@
 }
 
-#endif /* !_FS_READONLY */
+#endif /* !FF_FS_READONLY */
 
 
@@ -3012,5 +3012,5 @@
 
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 	res = f_sync(fp);					/* Flush cached data */
 	if (res == FR_OK)
@@ -3019,13 +3019,13 @@
 		res = validate(fp);				/* Lock volume */
 		if (res == FR_OK) {
-#if _FS_REENTRANT
+#if FF_FS_REENTRANT
 			FATFS *fs = fp->fs;
 #endif
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 			res = dec_lock(fp->lockid);	/* Decrement file open counter */
 			if (res == FR_OK)
 #endif
 				fp->fs = 0;				/* Invalidate file object */
-#if _FS_REENTRANT
+#if FF_FS_REENTRANT
 			unlock_fs(fs, FR_OK);		/* Unlock volume */
 #endif
@@ -3042,6 +3042,6 @@
 /*-----------------------------------------------------------------------*/
 
-#if _FS_RPATH >= 1
-#if _VOLUMES >= 2
+#if FF_FS_RPATH >= 1
+#if FF_VOLUMES >= 2
 FRESULT f_chdrive (
 	const TCHAR* path		/* Drive number */
@@ -3066,5 +3066,5 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	DEFINE_NAMEBUF;
 
@@ -3093,5 +3093,5 @@
 
 
-#if _FS_RPATH >= 2
+#if FF_FS_RPATH >= 2
 FRESULT f_getcwd (
 	TCHAR* buff,	/* Pointer to the directory path */
@@ -3100,5 +3100,5 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	UINT i, n;
 	DWORD ccl;
@@ -3131,5 +3131,5 @@
 			if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
 			if (res != FR_OK) break;
-#if _USE_LFN
+#if FF_USE_LFN
 			fno.lfname = buff;
 			fno.lfsize = i;
@@ -3137,5 +3137,5 @@
 			get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
 			tp = fno.fname;
-#if _USE_LFN
+#if FF_USE_LFN
 			if (*buff) tp = buff;
 #endif
@@ -3149,5 +3149,5 @@
 		tp = buff;
 		if (res == FR_OK) {
-#if _VOLUMES >= 2
+#if FF_VOLUMES >= 2
 			*tp++ = '0' + CurrVol;			/* Put drive number */
 			*tp++ = ':';
@@ -3167,10 +3167,10 @@
 	LEAVE_FF(dj.fs, res);
 }
-#endif /* _FS_RPATH >= 2 */
-#endif /* _FS_RPATH >= 1 */
-
-
-
-#if _FS_MINIMIZE <= 2
+#endif /* FF_FS_RPATH >= 2 */
+#endif /* FF_FS_RPATH >= 1 */
+
+
+
+#if FF_FS_MINIMIZE <= 2
 /*-----------------------------------------------------------------------*/
 /* Seek File R/W Pointer                                                 */
@@ -3184,5 +3184,5 @@
 	FRESULT res;
 	DWORD clst, bcs, nsect, ifptr;
-#if _USE_FASTSEEK
+#if FF_USE_FASTSEEK
 	DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
 #endif
@@ -3194,5 +3194,5 @@
 		LEAVE_FF(fp->fs, (FRESULT)fp->err);
 
-#if _USE_FASTSEEK
+#if FF_USE_FASTSEEK
 	if (fp->cltbl) {	/* Fast seek */
 		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
@@ -3231,10 +3231,10 @@
 				dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
 				if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) {	/* Refill sector cache if needed */
-#if !_FS_TINY
-#if !_FS_READONLY
-					if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+					if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
 						if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
 							ABORT(fp->fs, FR_DISK_ERR);
-						fp->flag &= ~FA__DIRTY;
+						fp->flag &= ~FA_DIRTY;
 					}
 #endif
@@ -3252,5 +3252,5 @@
 	{
 		if (ofs > fp->fsize					/* In read-only mode, clip offset with the file size */
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 			 && !(fp->flag & FA_WRITE)
 #endif
@@ -3268,5 +3268,5 @@
 			} else {									/* When seek to back cluster, */
 				clst = fp->sclust;						/* start from the first cluster */
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 				if (clst == 0) {						/* If no cluster chain, create a new chain */
 					clst = create_chain(fp->fs, 0);
@@ -3280,5 +3280,5 @@
 			if (clst != 0) {
 				while (ofs > bcs) {						/* Cluster following loop */
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
 						clst = create_chain(fp->fs, clst);	/* Force stretch if in write mode */
@@ -3304,10 +3304,10 @@
 		}
 		if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) {	/* Fill sector cache if needed */
-#if !_FS_TINY
-#if !_FS_READONLY
-			if (fp->flag & FA__DIRTY) {			/* Write-back dirty sector cache */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+			if (fp->flag & FA_DIRTY) {			/* Write-back dirty sector cache */
 				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
 					ABORT(fp->fs, FR_DISK_ERR);
-				fp->flag &= ~FA__DIRTY;
+				fp->flag &= ~FA_DIRTY;
 			}
 #endif
@@ -3317,8 +3317,8 @@
 			fp->dsect = nsect;
 		}
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 		if (fp->fptr > fp->fsize) {			/* Set file change flag if the file size is extended */
 			fp->fsize = fp->fptr;
-			fp->flag |= FA__WRITTEN;
+			fp->flag |= FA_MODIFIED;
 		}
 #endif
@@ -3342,5 +3342,5 @@
 }
 
-#if _FS_MINIMIZE <= 1
+#if FF_FS_MINIMIZE <= 1
 /*-----------------------------------------------------------------------*/
 /* Create a Directory Object                                             */
@@ -3348,5 +3348,5 @@
 
 FRESULT f_opendir (
-	DIR* dp,			/* Pointer to directory object to create */
+	FATFS_DIR* dp,			/* Pointer to directory object to create */
 	const TCHAR* path	/* Pointer to the directory path */
 )
@@ -3376,5 +3376,5 @@
 				dp->id = fs->id;
 				res = dir_sdi(dp, 0);			/* Rewind directory */
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 				if (res == FR_OK) {
 					if (dp->sclust) {
@@ -3404,5 +3404,5 @@
 
 FRESULT f_closedir (
-	DIR *dp		/* Pointer to the directory object to be closed */
+	FATFS_DIR *dp		/* Pointer to the directory object to be closed */
 )
 {
@@ -3412,8 +3412,8 @@
 	res = validate(dp);
 	if (res == FR_OK) {
-#if _FS_REENTRANT
+#if FF_FS_REENTRANT
 		FATFS *fs = dp->fs;
 #endif
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 		if (dp->lockid)				/* Decrement sub-directory open counter */
 			res = dec_lock(dp->lockid);
@@ -3421,5 +3421,5 @@
 #endif
 			dp->fs = 0;				/* Invalidate directory object */
-#if _FS_REENTRANT
+#if FF_FS_REENTRANT
 		unlock_fs(fs, FR_OK);		/* Unlock volume */
 #endif
@@ -3436,5 +3436,5 @@
 
 FRESULT f_readdir (
-	DIR* dp,			/* Pointer to the open directory object */
+	FATFS_DIR* dp,			/* Pointer to the open directory object */
 	FILINFO* fno		/* Pointer to file information to return */
 )
@@ -3472,5 +3472,5 @@
 
 
-#if _USE_FIND
+#if FF_USE_FIND
 /*-----------------------------------------------------------------------*/
 /* Find next file                                                        */
@@ -3478,5 +3478,5 @@
 
 FRESULT f_findnext (
-	DIR* dp,		/* Pointer to the open directory object */
+	FATFS_DIR* dp,		/* Pointer to the open directory object */
 	FILINFO* fno	/* Pointer to the file information structure */
 )
@@ -3488,5 +3488,5 @@
 		res = f_readdir(dp, fno);		/* Get a directory item */
 		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
-#if _USE_LFN
+#if FF_USE_LFN
 		if (fno->lfname && pattern_matching(dp->pat, fno->lfname, 0, 0)) break;	/* Test for LFN if exist */
 #endif
@@ -3504,5 +3504,5 @@
 
 FRESULT f_findfirst (
-	DIR* dp,				/* Pointer to the blank directory object */
+	FATFS_DIR* dp,				/* Pointer to the blank directory object */
 	FILINFO* fno,			/* Pointer to the file information structure */
 	const TCHAR* path,		/* Pointer to the directory to open */
@@ -3520,9 +3520,9 @@
 }
 
-#endif	/* _USE_FIND */
-
-
-
-#if _FS_MINIMIZE == 0
+#endif	/* FF_USE_FIND */
+
+
+
+#if FF_FS_MINIMIZE == 0
 /*-----------------------------------------------------------------------*/
 /* Get File Status                                                       */
@@ -3535,5 +3535,5 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	DEFINE_NAMEBUF;
 
@@ -3559,5 +3559,5 @@
 
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 /*-----------------------------------------------------------------------*/
 /* Get Number of Free Clusters                                           */
@@ -3650,5 +3650,5 @@
 		if (fp->fsize > fp->fptr) {
 			fp->fsize = fp->fptr;	/* Set file size to current R/W point */
-			fp->flag |= FA__WRITTEN;
+			fp->flag |= FA_MODIFIED;
 			if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
 				res = remove_chain(fp->fs, fp->sclust);
@@ -3664,10 +3664,10 @@
 				}
 			}
-#if !_FS_TINY
-			if (res == FR_OK && (fp->flag & FA__DIRTY)) {
+#if !FF_FS_TINY
+			if (res == FR_OK && (fp->flag & FA_DIRTY)) {
 				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
 					res = FR_DISK_ERR;
 				else
-					fp->flag &= ~FA__DIRTY;
+					fp->flag &= ~FA_DIRTY;
 			}
 #endif
@@ -3691,5 +3691,5 @@
 {
 	FRESULT res;
-	DIR dj, sdj;
+	FATFS_DIR dj, sdj;
 	BYTE *dir;
 	DWORD dclst = 0;
@@ -3702,7 +3702,7 @@
 		INIT_BUF(dj);
 		res = follow_path(&dj, path);		/* Follow the file path */
-		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+		if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
 			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Cannot remove open object */
 #endif
@@ -3718,5 +3718,5 @@
 				dclst = ld_clust(dj.fs, dir);
 				if (dclst && (dir[DIR_Attr] & AM_DIR)) {	/* Is it a sub-directory ? */
-#if _FS_RPATH
+#if FF_FS_RPATH
 					if (dclst == dj.fs->cdir) {		 		/* Is it the current directory? */
 						res = FR_DENIED;
@@ -3724,5 +3724,5 @@
 #endif
 					{
-						mem_cpy(&sdj, &dj, sizeof (DIR));	/* Open the sub-directory */
+						mem_cpy(&sdj, &dj, sizeof (FATFS_DIR));	/* Open the sub-directory */
 						sdj.sclust = dclst;
 						res = dir_sdi(&sdj, 2);
@@ -3760,5 +3760,5 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	BYTE *dir, n;
 	DWORD dsc, dcl, pcl, tm = GET_FATTIME();
@@ -3772,5 +3772,5 @@
 		res = follow_path(&dj, path);			/* Follow the file path */
 		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
-		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT))
+		if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT))
 			res = FR_INVALID_NAME;
 		if (res == FR_NO_FILE) {				/* Can create a new directory */
@@ -3836,5 +3836,5 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	BYTE *dir;
 	DEFINE_NAMEBUF;
@@ -3846,5 +3846,5 @@
 		res = follow_path(&dj, path);		/* Follow the file path */
 		FREE_BUF();
-		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+		if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
 			res = FR_INVALID_NAME;
 		if (res == FR_OK) {
@@ -3877,5 +3877,5 @@
 {
 	FRESULT res;
-	DIR djo, djn;
+	FATFS_DIR djo, djn;
 	BYTE buf[21], *dir;
 	DWORD dw;
@@ -3890,7 +3890,7 @@
 		INIT_BUF(djo);
 		res = follow_path(&djo, path_old);		/* Check old object */
-		if (_FS_RPATH && res == FR_OK && (djo.fn[NSFLAG] & NS_DOT))
+		if (FF_FS_RPATH && res == FR_OK && (djo.fn[NSFLAG] & NS_DOT))
 			res = FR_INVALID_NAME;
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 		if (res == FR_OK) res = chk_lock(&djo, 2);
 #endif
@@ -3900,5 +3900,5 @@
 			} else {
 				mem_cpy(buf, djo.dir + DIR_Attr, 21);	/* Save information about object except name */
-				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				mem_cpy(&djn, &djo, sizeof (FATFS_DIR));		/* Duplicate the directory object */
 				if (get_ldnumber(&path_new) >= 0)		/* Snip drive number off and ignore it */
 					res = follow_path(&djn, path_new);	/* and make sure if new object name is not conflicting */
@@ -3909,6 +3909,6 @@
 					dir = djn.dir;
 					if (dir[DIR_Attr] & AM_DIR) {	/* The new object is a directory */
-						temp_new_path = (TCHAR *)ff_memalloc((_MAX_LFN + 1) * sizeof(WCHAR));
-						ntstdio_snprintf(temp_new_path, _MAX_LFN, "%s/%s", path_new, basename((char *)path_old));
+						temp_new_path = (TCHAR *)ff_memalloc((FF_MAX_LFN + 1) * sizeof(WCHAR));
+						snprintf(temp_new_path, FF_MAX_LFN, "%s/%s", path_new, basename((char *)path_old));
 						res = follow_path(&djn, temp_new_path);
 					}
@@ -3966,5 +3966,5 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	BYTE *dir;
 	DEFINE_NAMEBUF;
@@ -3977,5 +3977,5 @@
 		res = follow_path(&dj, path);	/* Follow the file path */
 		FREE_BUF();
-		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+		if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
 			res = FR_INVALID_NAME;
 		if (res == FR_OK) {
@@ -3995,13 +3995,13 @@
 }
 
-#endif /* !_FS_READONLY */
-#endif /* _FS_MINIMIZE == 0 */
-#endif /* _FS_MINIMIZE <= 1 */
-#endif /* _FS_MINIMIZE <= 2 */
-
-
-
-
-#if _USE_LABEL
+#endif /* !FF_FS_READONLY */
+#endif /* FF_FS_MINIMIZE == 0 */
+#endif /* FF_FS_MINIMIZE <= 1 */
+#endif /* FF_FS_MINIMIZE <= 2 */
+
+
+
+
+#if FF_USE_LABEL
 /*-----------------------------------------------------------------------*/
 /* Get volume label                                                      */
@@ -4015,7 +4015,7 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	UINT i, j;
-#if _USE_LFN && _LFN_UNICODE
+#if FF_USE_LFN && FF_LFN_UNICODE
 	WCHAR w;
 #endif
@@ -4032,5 +4032,5 @@
 			res = dir_read(&dj, 1);		/* Get an entry with AM_VOL */
 			if (res == FR_OK) {			/* A volume label is exist */
-#if _USE_LFN && _LFN_UNICODE
+#if FF_USE_LFN && FF_LFN_UNICODE
 				i = j = 0;
 				do {
@@ -4070,5 +4070,5 @@
 
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 /*-----------------------------------------------------------------------*/
 /* Set volume label                                                      */
@@ -4080,10 +4080,10 @@
 {
 	FRESULT res;
-	DIR dj;
+	FATFS_DIR dj;
 	BYTE vn[11];
 	UINT i, j, sl;
 	WCHAR w;
 	DWORD tm;
-#if _CODE_PAGE == 65001
+#if FF_CODE_PAGE == 65001
 	int code_size;
 	unsigned char utf8_code[6];
@@ -4101,5 +4101,5 @@
 		i = j = 0;
 		do {
-#if _CODE_PAGE == 65001
+#if FF_CODE_PAGE == 65001
 			w = ff_wtoupper(Utf8_to_Utf16(&label[i], &code_size));
 			i += code_size;
@@ -4110,5 +4110,5 @@
 				vn[j++] = utf8_code[k];
 #else
-#if _USE_LFN && _LFN_UNICODE
+#if FF_USE_LFN && FF_LFN_UNICODE
 			w = ff_convert(ff_wtoupper(label[i++]), 0);
 #else
@@ -4116,5 +4116,5 @@
 			if (IsDBCS1(w))
 				w = (j < 10 && i < sl && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
-#if _USE_LFN
+#if FF_USE_LFN
 			w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
 #else
@@ -4174,6 +4174,6 @@
 }
 
-#endif /* !_FS_READONLY */
-#endif /* _USE_LABEL */
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_LABEL */
 
 
@@ -4182,5 +4182,5 @@
 /* Forward data to the stream directly (available on only tiny cfg)      */
 /*-----------------------------------------------------------------------*/
-#if _USE_FORWARD && _FS_TINY
+#if FF_USE_FORWARD && FF_FS_TINY
 
 FRESULT f_forward (
@@ -4235,9 +4235,9 @@
 	LEAVE_FF(fp->fs, FR_OK);
 }
-#endif /* _USE_FORWARD */
-
-
-
-#if _USE_MKFS && !_FS_READONLY
+#endif /* FF_USE_FORWARD */
+
+
+
+#if FF_USE_MKFS && !FF_FS_READONLY
 /*-----------------------------------------------------------------------*/
 /* Create file system on the logical drive                               */
@@ -4263,5 +4263,5 @@
 	FATFS *fs;
 	DSTATUS stat;
-#if _USE_TRIM
+#if FF_USE_TRIM
 	DWORD eb[2];
 #endif
@@ -4282,9 +4282,9 @@
 	if (stat & STA_NOINIT) return FR_NOT_READY;
 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
-#if _MAX_SS != _MIN_SS		/* Get disk sector size */
-	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS || SS(fs) < _MIN_SS)
+#if FF_MAX_SS != FF_MIN_SS		/* Get disk sector size */
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS)
 		return FR_DISK_ERR;
 #endif
-	if (_MULTI_PARTITION && part) {
+	if (FF_MULTI_PARTITION && part) {
 		/* Get partition information from partition table in the MBR */
 		if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
@@ -4308,5 +4308,5 @@
 		au = cst[i];
 	}
-	if (au >= _MIN_SS) au /= SS(fs);	/* Number of sectors per cluster */
+	if (au >= FF_MIN_SS) au /= SS(fs);	/* Number of sectors per cluster */
 	if (!au) au = 1;
 	if (au > 128) au = 128;
@@ -4362,5 +4362,5 @@
 	}
 
-	if (_MULTI_PARTITION && part) {
+	if (FF_MULTI_PARTITION && part) {
 		/* Update system ID in the partition table */
 		tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
@@ -4465,5 +4465,5 @@
 	} while (--i);
 
-#if _USE_TRIM	/* Erase data area if needed */
+#if FF_USE_TRIM	/* Erase data area if needed */
 	{
 		eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
@@ -4488,5 +4488,5 @@
 
 
-#if _MULTI_PARTITION
+#if FF_MULTI_PARTITION
 /*-----------------------------------------------------------------------*/
 /* Create partition table on the physical drive                          */
@@ -4518,5 +4518,5 @@
 
 	/* Create partition table */
-	mem_set(buf, 0, _MAX_SS);
+	mem_set(buf, 0, FF_MAX_SS);
 	p = buf + MBR_Table; b_cyl = 0;
 	for (i = 0; i < 4; i++, p += SZ_PTE) {
@@ -4555,11 +4555,11 @@
 
 
-#endif /* _MULTI_PARTITION */
-#endif /* _USE_MKFS && !_FS_READONLY */
-
-
-
-
-#if _USE_STRFUNC
+#endif /* FF_MULTI_PARTITION */
+#endif /* FF_USE_MKFS && !FF_FS_READONLY */
+
+
+
+
+#if FF_USE_STRFUNC
 /*-----------------------------------------------------------------------*/
 /* Get a string from the file                                            */
@@ -4579,6 +4579,6 @@
 
 	while (n < len - 1) {	/* Read characters until buffer gets filled */
-#if _USE_LFN && _LFN_UNICODE
-#if _STRF_ENCODE == 3		/* Read a character in UTF-8 */
+#if FF_USE_LFN && FF_LFN_UNICODE
+#if FF_STRF_ENCODE == 3		/* Read a character in UTF-8 */
 		f_read(fp, s, 1, &rc);
 		if (rc != 1) break;
@@ -4602,9 +4602,9 @@
 			}
 		}
-#elif _STRF_ENCODE == 2		/* Read a character in UTF-16BE */
+#elif FF_STRF_ENCODE == 2		/* Read a character in UTF-16BE */
 		f_read(fp, s, 2, &rc);
 		if (rc != 2) break;
 		c = s[1] + (s[0] << 8);
-#elif _STRF_ENCODE == 1		/* Read a character in UTF-16LE */
+#elif FF_STRF_ENCODE == 1		/* Read a character in UTF-16LE */
 		f_read(fp, s, 2, &rc);
 		if (rc != 2) break;
@@ -4627,5 +4627,5 @@
 		c = s[0];
 #endif
-		if (_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
+		if (FF_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
 		*p++ = c;
 		n++;
@@ -4639,5 +4639,5 @@
 
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 /*-----------------------------------------------------------------------*/
 /* Put a character to the file                                           */
@@ -4661,5 +4661,5 @@
 
 
-	if (_USE_STRFUNC == 2 && c == '\n')	 /* LF -> CRLF conversion */
+	if (FF_USE_STRFUNC == 2 && c == '\n')	 /* LF -> CRLF conversion */
 		putc_bfd(pb, '\r');
 
@@ -4667,6 +4667,6 @@
 	if (i < 0) return;
 
-#if _USE_LFN && _LFN_UNICODE
-#if _STRF_ENCODE == 3			/* Write a character in UTF-8 */
+#if FF_USE_LFN && FF_LFN_UNICODE
+#if FF_STRF_ENCODE == 3			/* Write a character in UTF-8 */
 	if (c < 0x80) {				/* 7-bit */
 		pb->buf[i++] = (BYTE)c;
@@ -4680,8 +4680,8 @@
 		pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F));
 	}
-#elif _STRF_ENCODE == 2			/* Write a character in UTF-16BE */
+#elif FF_STRF_ENCODE == 2			/* Write a character in UTF-16BE */
 	pb->buf[i++] = (BYTE)(c >> 8);
 	pb->buf[i++] = (BYTE)c;
-#elif _STRF_ENCODE == 1			/* Write a character in UTF-16LE */
+#elif FF_STRF_ENCODE == 1			/* Write a character in UTF-16LE */
 	pb->buf[i++] = (BYTE)c;
 	pb->buf[i++] = (BYTE)(c >> 8);
@@ -4866,8 +4866,8 @@
 	ret = f_vprintf(fp, fmt, arp);
 	va_end(arp);
-
+	
 	return ret;
 }
 
-#endif /* !_FS_READONLY */
-#endif /* _USE_STRFUNC */
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_STRFUNC */
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ff.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ff.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ff.h	(revision 374)
@@ -28,5 +28,5 @@
 #include "ffconf.h"		/* FatFs configuration options */
 #include "diskio.h"
-#if _FATFS != _FFCONF
+#if _FATFS != FFCONF_DEF
 #error Wrong configuration file (ffconf.h).
 #endif
@@ -36,5 +36,5 @@
 /* Definitions of volume management */
 
-#if _MULTI_PARTITION		/* Multiple partition configuration */
+#if FF_MULTI_PARTITION		/* Multiple partition configuration */
 typedef struct {
 	BYTE pd;	/* Physical drive number */
@@ -55,7 +55,7 @@
 /* Type of path name strings on FatFs API */
 
-#if _LFN_UNICODE			/* Unicode string */
-#if !_USE_LFN
-#error _LFN_UNICODE must be 0 at non-LFN cfg.
+#if FF_LFN_UNICODE			/* Unicode string */
+#if !FF_USE_LFN
+#error FF_LFN_UNICODE must be 0 at non-LFN cfg.
 #endif
 #ifndef _INC_TCHAR
@@ -87,15 +87,15 @@
 	WORD	id;				/* File system mount ID */
 	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
-#if _MAX_SS != _MIN_SS
+#if FF_MAX_SS != FF_MIN_SS
 	WORD	ssize;			/* Bytes per sector (512, 1024, 2048 or 4096) */
 #endif
-#if _FS_REENTRANT
-	_SYNC_t	sobj;			/* Identifier of sync object */
-#endif
-#if !_FS_READONLY
+#if FF_FS_REENTRANT
+	FF_SYNC_t	sobj;			/* Identifier of sync object */
+#endif
+#if !FF_FS_READONLY
 	DWORD	last_clust;		/* Last allocated cluster */
 	DWORD	free_clust;		/* Number of free clusters */
 #endif
-#if _FS_RPATH
+#if FF_FS_RPATH
 	DWORD	cdir;			/* Current directory start cluster (0:root) */
 #endif
@@ -107,5 +107,5 @@
 	DWORD	database;		/* Data start sector */
 	DWORD	winsect;		/* Current sector appearing in the win[] */
-	BYTE	win[_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
+	BYTE	win[FF_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
 } FATFS;
 
@@ -124,16 +124,16 @@
 	DWORD	clust;			/* Current cluster of fpter (not valid when fprt is 0) */
 	DWORD	dsect;			/* Sector number appearing in buf[] (0:invalid) */
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 	DWORD	dir_sect;		/* Sector number containing the directory entry */
 	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] */
 #endif
-#if _USE_FASTSEEK
+#if FF_USE_FASTSEEK
 	DWORD*	cltbl;			/* Pointer to the cluster link map table (Nulled on file open) */
 #endif
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 	UINT	lockid;			/* File lock ID origin from 1 (index of file semaphore table Files[]) */
 #endif
-#if !_FS_TINY
-	BYTE	buf[_MAX_SS];	/* File private data read/write window */
+#if !FF_FS_TINY
+	BYTE	buf[FF_MAX_SS];	/* File private data read/write window */
 #endif
 } FIL;
@@ -141,5 +141,5 @@
 
 
-/* Directory object structure (DIR) */
+/* Directory object structure (FATFS_DIR) */
 
 typedef struct __dirstream {
@@ -152,15 +152,15 @@
 	BYTE*	dir;			/* Pointer to the current SFN entry in the win[] */
 	BYTE*	fn;				/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
-#if _FS_LOCK
+#if FF_FS_LOCK != 0
 	UINT	lockid;			/* File lock ID (index of file semaphore table Files[]) */
 #endif
-#if _USE_LFN
+#if FF_USE_LFN
 	WCHAR*	lfn;			/* Pointer to the LFN working buffer */
 	WORD	lfn_idx;		/* Last matched LFN index number (0xFFFF:No LFN) */
 #endif
-#if _USE_FIND
+#if FF_USE_FIND
 	const TCHAR*	pat;	/* Pointer to the name matching pattern */
 #endif
-} DIR;
+} FATFS_DIR;
 
 
@@ -174,5 +174,5 @@
 	BYTE	fattrib;		/* Attribute */
 	TCHAR	fname[13];		/* Short file name (8.3 format) */
-#if _USE_LFN
+#if FF_USE_LFN
 	TCHAR*	lfname;			/* Pointer to the LFN buffer */
 	UINT 	lfsize;			/* Size of LFN buffer in TCHAR */
@@ -203,5 +203,5 @@
 	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
 	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
-	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > _FS_LOCK */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > FF_FS_LOCK */
 	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
 } FRESULT;
@@ -220,9 +220,9 @@
 FRESULT f_truncate (FIL* fp);										/* Truncate file */
 FRESULT f_sync (FIL* fp);											/* Flush cached data of a writing file */
-FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
-FRESULT f_closedir (DIR* dp);										/* Close an open directory */
-FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
-FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
-FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_opendir (FATFS_DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (FATFS_DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (FATFS_DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (FATFS_DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (FATFS_DIR* dp, FILINFO* fno);							/* Find next file */
 FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
 FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
@@ -270,13 +270,13 @@
 
 /* RTC function */
-#if !_FS_READONLY && !_FS_NORTC
+#if !FF_FS_READONLY && !FF_FS_NORTC
 DWORD get_fattime (void);
 #endif
 
 /* Unicode support functions */
-#if _USE_LFN							/* Unicode - OEM code conversion */
+#if FF_USE_LFN							/* Unicode - OEM code conversion */
 WCHAR ff_convert (WCHAR chr, UINT dir);	/* OEM-Unicode bidirectional conversion */
 WCHAR ff_wtoupper (WCHAR chr);			/* Unicode upper-case conversion */
-#if _USE_LFN == 3						/* Memory functions */
+#if FF_USE_LFN == 3						/* Memory functions */
 void* ff_memalloc (UINT msize);			/* Allocate memory block */
 void ff_memfree (void* mblock);			/* Free memory block */
@@ -285,9 +285,9 @@
 
 /* Sync functions */
-#if _FS_REENTRANT
-int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj);	/* Create a sync object */
-int ff_req_grant (_SYNC_t sobj);				/* Lock sync object */
-void ff_rel_grant (_SYNC_t sobj);				/* Unlock sync object */
-int ff_del_syncobj (_SYNC_t sobj);				/* Delete a sync object */
+#if FF_FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj);	/* Create a sync object */
+int ff_req_grant (FF_SYNC_t sobj);				/* Lock sync object */
+void ff_rel_grant (FF_SYNC_t sobj);				/* Unlock sync object */
+int ff_del_syncobj (FF_SYNC_t sobj);				/* Delete a sync object */
 #endif
 
@@ -304,11 +304,12 @@
 #define	FA_OPEN_EXISTING	0x00
 
-#if !_FS_READONLY
+#if !FF_FS_READONLY
 #define	FA_WRITE			0x02
 #define	FA_CREATE_NEW		0x04
 #define	FA_CREATE_ALWAYS	0x08
 #define	FA_OPEN_ALWAYS		0x10
-#define FA__WRITTEN			0x20
-#define FA__DIRTY			0x40
+#define	FA_OPEN_APPEND		0x30
+#define FA_MODIFIED			0x20
+#define FA_DIRTY			0x40
 #endif
 
@@ -341,5 +342,5 @@
 /* Multi-byte word access macros  */
 
-#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#if FF_WORD_ACCESS == 1	/* Enable word access to the FAT structure */
 #define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
 #define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ffarch.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ffarch.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ffarch.c	(revision 374)
@@ -51,7 +51,7 @@
 #include "sdfs.h"
 #include "ff.h"
-#include "util/ntstdio.h"
-
-extern ntstdio_t ntstdio;
+#include <stdio.h>
+#include "hal/rtc_api.h"
+#include "ffarch.h"
 
 enum ffarch_state_t {
@@ -80,5 +80,5 @@
 	ret2 = get_tim(&now);
 	if (ret2 != E_OK){
-		ntstdio_printf(&ntstdio, "[ffarch] get_tim error: %s",
+		printf("[ffarch] get_tim error: %s",
 			itron_strerror(ret2));
 		return;
@@ -94,5 +94,5 @@
 		ret = tslp_tsk(timer);
 		if ((ret != E_OK) && (ret != E_TMOUT)) {
-			ntstdio_printf(&ntstdio, "[ffarch] tslp_tsk error: %s %d",
+			printf("[ffarch] tslp_tsk error: %s %d",
 				itron_strerror(ret), timer);
 			break;
@@ -101,5 +101,5 @@
 		ret2 = get_tim(&now);
 		if (ret2 != E_OK) {
-			ntstdio_printf(&ntstdio, "[ffarch] get_tim error: %s",
+			printf("[ffarch] get_tim error: %s",
 				itron_strerror(ret2));
 			break;
@@ -150,11 +150,9 @@
 
 	if (romdisk_init()) {
-		ntstdio_printf(&ntstdio, "ROM disk (0:) OK!\n");
+		printf("ROM disk (0:) OK!\n");
 	}
 	else {
-		ntstdio_printf(&ntstdio, "ROM disk (0:) NG!\n");
-	}
-
-	serial_ctl_por(SIO_PORTID, IOCTL_FCSND | IOCTL_FCRCV);
+		printf("ROM disk (0:) NG!\n");
+	}
 }
 
@@ -272,5 +270,5 @@
 {
 	DRESULT res;
-	uint32_t *dp = (uint32_t *)buff, st, ed;
+	uint32_t *dp = (uint32_t *)buff;
 	uint8_t *ptr = (uint8_t *)buff;
 
@@ -333,5 +331,5 @@
 {
 	BYTE s = 0;
-
+             
 	/* Write protected */
 	if (WP())
@@ -377,5 +375,5 @@
 	case FFS_RETRY_WAIT:
 		if (ffarch_retry_count == 0) {
-			ntstdio_printf(&ntstdio, "SD card (1:) initialize tired...\n");
+			printf("SD card (1:) initialize tired...\n");
 
 			ffarch_state = FFS_IDLE;
@@ -390,8 +388,8 @@
  		if ((sdfs._is_initialized & STA_NOINIT)
  			|| (((sdfs_prev_status & STA_NODISK) != 0) && ((sdfs_new_status & STA_NODISK) == 0))) {
-			ntstdio_printf(&ntstdio, "SD card initializing ...\n");
+			printf("SD card initializing ...\n");
 
 			if (SD_begin()) {
-				ntstdio_printf(&ntstdio, "SD card (1:) OK!\n");
+				printf("SD card (1:) OK!\n");
 
 				/* uploadディレクトリを作成しておく */
@@ -403,5 +401,5 @@
 			}
 			else {
-				ntstdio_printf(&ntstdio, "SD card (1:) NG!\n");
+				printf("SD card (1:) NG!\n");
 				ffarch_state = FFS_RETRY_WAIT;
 				ffarch_timer = 1000 * 1000;
@@ -410,5 +408,5 @@
 		/* SDカードが抜かれた場合 */
 		else if (((sdfs_prev_status & STA_NODISK) == 0) && ((sdfs_new_status & STA_NODISK) != 0)) {
-			ntstdio_printf(&ntstdio, "SD card unmount\n");
+			printf("SD card unmount\n");
 
 			f_mount(&Sd.FatFs, "1:", 0);
@@ -428,10 +426,10 @@
 }
 
-int ff_cre_syncobj(BYTE vol, _SYNC_t* sobj)
+int ff_cre_syncobj(BYTE vol, FF_SYNC_t* sobj)
 {
 	return 1;
 }
 
-int ff_req_grant(_SYNC_t sobj)
+int ff_req_grant(FF_SYNC_t sobj)
 {
 	ER ret;
@@ -440,10 +438,10 @@
 }
 
-void ff_rel_grant(_SYNC_t sobj)
+void ff_rel_grant(FF_SYNC_t sobj)
 {
 	sig_sem(SEM_FILESYSTEM);
 }
 
-int ff_del_syncobj(_SYNC_t sobj)
+int ff_del_syncobj(FF_SYNC_t sobj)
 {
 	return 1;
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ffconf.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ffconf.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/ffconf.h	(revision 374)
@@ -3,5 +3,7 @@
 /---------------------------------------------------------------------------*/
 
-#define _FFCONF 64180	/* Revision ID */
+#define FFCONF_DEF 64180	/* Revision ID */
+
+#define FFS_DBG			0
 
 /*---------------------------------------------------------------------------/
@@ -9,5 +11,5 @@
 /---------------------------------------------------------------------------*/
 
-#define _FS_READONLY	0
+#define FF_FS_READONLY	0
 /* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
 /  Read-only configuration removes writing API functions, f_write(), f_sync(),
@@ -16,5 +18,5 @@
 
 
-#define _FS_MINIMIZE	0
+#define FF_FS_MINIMIZE	0
 /* This option defines minimization level to remove some basic API functions.
 /
@@ -26,5 +28,5 @@
 
 
-#define	_USE_STRFUNC	1
+#define	FF_USE_STRFUNC	1
 /* This option switches string functions, f_gets(), f_putc(), f_puts() and
 /  f_printf().
@@ -35,25 +37,25 @@
 
 
-#define _USE_FIND		1
+#define FF_USE_FIND		1
 /* This option switches filtered directory read feature and related functions,
 /  f_findfirst() and f_findnext(). (0:Disable or 1:Enable) */
 
 
-#define	_USE_MKFS		1
+#define	FF_USE_MKFS		1
 /* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
 
 
-#define	_USE_FASTSEEK	0
+#define	FF_USE_FASTSEEK	0
 /* This option switches fast seek feature. (0:Disable or 1:Enable) */
 
 
-#define _USE_LABEL		1
+#define FF_USE_LABEL		1
 /* This option switches volume label functions, f_getlabel() and f_setlabel().
 /  (0:Disable or 1:Enable) */
 
 
-#define	_USE_FORWARD	1
+#define	FF_USE_FORWARD	1
 /* This option switches f_forward() function. (0:Disable or 1:Enable)
-/  To enable it, also _FS_TINY need to be set to 1. */
+/  To enable it, also FF_FS_TINY need to be set to 1. */
 
 
@@ -62,5 +64,5 @@
 /---------------------------------------------------------------------------*/
 
-#define _CODE_PAGE 65001
+#define FF_CODE_PAGE 65001
 /* This option specifies the OEM code page to be used on the target system.
 /  Incorrect setting of the code page can cause a file open failure.
@@ -91,9 +93,9 @@
 
 
-#define	_USE_LFN	3
-#define	_MAX_LFN	255
-/* The _USE_LFN option switches the LFN feature.
-/
-/   0: Disable LFN feature. _MAX_LFN has no effect.
+#define	FF_USE_LFN	3
+#define	FF_MAX_LFN	255
+/* The FF_USE_LFN option switches the LFN feature.
+/
+/   0: Disable LFN feature. FF_MAX_LFN has no effect.
 /   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
 /   2: Enable LFN with dynamic working buffer on the STACK.
@@ -101,5 +103,5 @@
 /
 /  When enable the LFN feature, Unicode handling functions (option/unicode.c) must
-/  be added to the project. The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes.
+/  be added to the project. The LFN working buffer occupies (FF_MAX_LFN + 1) * 2 bytes.
 /  When use stack for the working buffer, take care on stack overflow. When use heap
 /  memory for the working buffer, memory management functions, ff_memalloc() and
@@ -107,12 +109,12 @@
 
 
-#define	_LFN_UNICODE	0
+#define	FF_LFN_UNICODE	0
 /* This option switches character encoding on the API. (0:ANSI/OEM or 1:Unicode)
-/  To use Unicode string for the path name, enable LFN feature and set _LFN_UNICODE
+/  To use Unicode string for the path name, enable LFN feature and set FF_LFN_UNICODE
 /  to 1. This option also affects behavior of string I/O functions. */
 
 
-#define _STRF_ENCODE	3
-/* When _LFN_UNICODE is 1, this option selects the character encoding on the file to
+#define FF_STRF_ENCODE	3
+/* When FF_LFN_UNICODE is 1, this option selects the character encoding on the file to
 /  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
 /
@@ -122,8 +124,16 @@
 /  3: UTF-8
 /
-/  When _LFN_UNICODE is 0, this option has no effect. */
-
-
-#define _FS_RPATH	2
+/  When FF_LFN_UNICODE is 0, this option has no effect. */
+
+
+#define FF_LFN_BUF		255
+#define FF_SFN_BUF		12
+/* This set of options defines size of file name members in the FILINFO structure
+/  which is used to read out directory items. These values should be suffcient for
+/  the file names to read. The maximum possible length of the read file name depends
+/  on character encoding. When LFN is not enabled, these options have no effect. */
+
+
+#define FF_FS_RPATH	2
 /* This option configures relative path feature.
 /
@@ -139,18 +149,18 @@
 /---------------------------------------------------------------------------*/
 
-#define _VOLUMES	2
+#define FF_VOLUMES	4
 /* Number of volumes (logical drives) to be used. */
 
 
-#define _STR_VOLUME_ID	0
-#define _VOLUME_STRS	"RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
-/* _STR_VOLUME_ID option switches string volume ID feature.
-/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
-/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
-/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+#define FF_STR_VOLUME_ID	0
+#define FF_VOLUME_STRS	"RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* FF_STR_VOLUME_ID option switches string volume ID feature.
+/  When FF_STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. FF_VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to FF_VOLUMES. Valid characters for
 /  the drive ID strings are: A-Z and 0-9. */
 
 
-#define	_MULTI_PARTITION	0
+#define	FF_MULTI_PARTITION	0
 /* This option switches multi-partition feature. By default (0), each logical drive
 /  number is bound to the same physical drive number and only an FAT volume found on
@@ -160,15 +170,15 @@
 
 
-#define	_MIN_SS		512
-#define	_MAX_SS		512
+#define	FF_MIN_SS		512
+#define	FF_MAX_SS		512
 /* These options configure the range of sector size to be supported. (512, 1024,
 /  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
 /  harddisk. But a larger value may be required for on-board flash memory and some
-/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
 /  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
 /  disk_ioctl() function. */
 
 
-#define	_USE_TRIM	0
+#define	FF_USE_TRIM	0
 /* This option switches ATA-TRIM feature. (0:Disable or 1:Enable)
 /  To enable Trim feature, also CTRL_TRIM command should be implemented to the
@@ -176,5 +186,5 @@
 
 
-#define _FS_NOFSINFO	0
+#define FF_FS_NOFSINFO	0
 /* If you need to know correct free space on the FAT32 volume, set bit 0 of this
 /  option, and f_getfree() function at first time after volume mount will force
@@ -193,7 +203,7 @@
 /---------------------------------------------------------------------------*/
 
-#define	_FS_TINY	1
+#define	FF_FS_TINY	1
 /* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
-/  At the tiny configuration, size of the file object (FIL) is reduced _MAX_SS
+/  At the tiny configuration, size of the file object (FIL) is reduced FF_MAX_SS
 /  bytes. Instead of private sector buffer eliminated from the file object,
 /  common sector buffer in the file system object (FATFS) is used for the file
@@ -201,21 +211,21 @@
 
 
-#define _FS_NORTC	0
-#define _NORTC_MON	1
-#define _NORTC_MDAY	1
-#define _NORTC_YEAR	2015
-/* The _FS_NORTC option switches timestamp feature. If the system does not have
-/  an RTC function or valid timestamp is not needed, set _FS_NORTC to 1 to disable
+#define FF_FS_NORTC	0
+#define FF_NORTC_MON	1
+#define FF_NORTC_MDAY	1
+#define FF_NORTC_YEAR	2015
+/* The FF_FS_NORTC option switches timestamp feature. If the system does not have
+/  an RTC function or valid timestamp is not needed, set FF_FS_NORTC to 1 to disable
 /  the timestamp feature. All objects modified by FatFs will have a fixed timestamp
-/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR.
-/  When timestamp feature is enabled (_FS_NORTC == 0), get_fattime() function need
-/  to be added to the project to read current time form RTC. _NORTC_MON,
-/  _NORTC_MDAY and _NORTC_YEAR have no effect. 
-/  These options have no effect at read-only configuration (_FS_READONLY == 1). */
-
-
-#define	_FS_LOCK	0
-/* The _FS_LOCK option switches file lock feature to control duplicated file open
-/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR.
+/  When timestamp feature is enabled (FF_FS_NORTC == 0), get_fattime() function need
+/  to be added to the project to read current time form RTC. FF_NORTC_MON,
+/  FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. 
+/  These options have no effect at read-only configuration (FF_FS_READONLY == 1). */
+
+
+#define	FF_FS_LOCK	0
+/* The FF_FS_LOCK option switches file lock feature to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
 /  is 1.
 /
@@ -227,8 +237,8 @@
 
 
-#define _FS_REENTRANT	1
-#define _FS_TIMEOUT		1000
-#define	_SYNC_t			unsigned int
-/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs
+#define FF_FS_REENTRANT	1
+#define FF_FS_TIMEOUT		1000
+#define	FF_SYNC_t			unsigned int
+/* The FF_FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs
 /  module itself. Note that regardless of this option, file access to different
 /  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
@@ -236,5 +246,5 @@
 /  to the same volume is under control of this feature.
 /
-/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
 /   1: Enable re-entrancy. Also user provided synchronization handlers,
 /      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
@@ -242,12 +252,12 @@
 /      option/syscall.c.
 /
-/  The _FS_TIMEOUT defines timeout period in unit of time tick.
-/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  The FF_FS_TIMEOUT defines timeout period in unit of time tick.
+/  The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
 /  SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
 /  included somewhere in the scope of ff.c. */
 
 
-#define _WORD_ACCESS	1
-/* The _WORD_ACCESS option is an only platform dependent option. It defines
+#define FF_WORD_ACCESS	1
+/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
 /  which access method is used to the word data on the FAT volume.
 /
@@ -258,5 +268,5 @@
 /  * Byte order on the memory is little-endian.
 /
-/  If it is the case, _WORD_ACCESS can also be set to 1 to reduce code size.
+/  If it is the case, FF_WORD_ACCESS can also be set to 1 to reduce code size.
 /  Following table shows allowable settings of some type of processors.
 /
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.c	(revision 374)
@@ -118,9 +118,8 @@
 //#include "mbed_debug.h"
 #include "mbed_wait_api.h"
-#include "util/ntstdio.h"
-
-extern ntstdio_t ntstdio;
-#define debug(...) ntstdio_printf(&ntstdio, __VA_ARGS__)
-#define debug_if(cond, ...) if(cond){ ntstdio_printf(&ntstdio, __VA_ARGS__); }
+#include <stdio.h>
+
+#define debug(...) printf(__VA_ARGS__)
+#define debug_if(cond, ...) if(cond){ printf(__VA_ARGS__); }
 
 static int sdfs_initialise_card_v1(sdfs_t *obj);
@@ -137,5 +136,5 @@
 #define SD_DBG             0
 
-sdfs_init(sdfs_t *obj, PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name)
+void sdfs_init(sdfs_t *obj, PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name)
 {
 	obj->name = name;
Index: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.h	(revision 374)
@@ -80,5 +80,5 @@
 	* @param name The name used to access the virtual filesystem
 	*/
-sdfs_init(sdfs_t *obj, PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name);
+void sdfs_init(sdfs_t *obj, PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name);
 
 int sdfs_initialize(sdfs_t *obj);
Index: asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/usrcmd.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/usrcmd.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/usrcmd.c	(revision 374)
@@ -47,122 +47,8 @@
 #include "core/ntshell.h"
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
-
-extern ntstdio_t ntstdio;
+#include <stdio.h>
+#include <getopt.h>
+
 extern int ntshell_exit;
-
-extern int mbtowc(wchar_t *__restrict wc, const char *__restrict src, size_t n);
-
-/* musl_getopt from msul */
-char *optarg;
-int optind=1, opterr=1, optopt, optpos, optreset=0;
-extern int optind, opterr;
-
-static void ntstdio_write(ntstdio_t *handle, const char *str, int l)
-{
-	for (; *str && l >= 0; l--) {
-		ntstdio_putc(handle, *str++);
-	}
-}
-
-static void __getopt_msg(const char *a, const char *b, const char *c, size_t l)
-{
-	ntstdio_puts(&ntstdio, a);
-	ntstdio_write(&ntstdio, b, strlen(b));
-	ntstdio_write(&ntstdio, c, l);
-	ntstdio_putc(&ntstdio, '\n');
-}
-
-static int musl_getopt(int argc, char * const argv[], const char *optstring)
-{
-	int i;
-	wchar_t c, d;
-	int k, l;
-	char *optchar;
-
-	if (!optind || optreset) {
-		optreset = 0;
-		optpos = 0;
-		optind = 1;
-	}
-
-	if (optind >= argc || !argv[optind])
-		return -1;
-
-	if (argv[optind][0] != '-') {
-		if (optstring[0] == '-') {
-			optarg = argv[optind++];
-			return 1;
-		}
-		return -1;
-	}
-
-	if (!argv[optind][1])
-		return -1;
-
-	if (argv[optind][1] == '-' && !argv[optind][2])
-		return optind++, -1;
-
-	if (!optpos) optpos++;
-	if ((k = mbtowc(&c, argv[optind]+optpos, MB_LEN_MAX)) < 0) {
-		k = 1;
-		c = 0xfffd; /* replacement char */
-	}
-	optchar = argv[optind]+optpos;
-	optopt = c;
-	optpos += k;
-
-	if (!argv[optind][optpos]) {
-		optind++;
-		optpos = 0;
-	}
-
-	if (optstring[0] == '-' || optstring[0] == '+')
-		optstring++;
-
-	i = 0;
-	d = 0;
-	do {
-		l = mbtowc(&d, optstring+i, MB_LEN_MAX);
-		if (l>0) i+=l; else i++;
-	} while (l && d != c);
-
-	if (d != c) {
-		if (optstring[0] != ':' && opterr)
-			__getopt_msg(argv[0], ": unrecognized option: ", optchar, k);
-		return '?';
-	}
-	if (optstring[i] == ':') {
-		if (optstring[i+1] == ':') optarg = 0;
-		else if (optind >= argc) {
-			if (optstring[0] == ':') return ':';
-			if (opterr) __getopt_msg(argv[0],
-				": option requires an argument: ",
-				optchar, k);
-			return '?';
-		}
-		if (optstring[i+1] != ':' || optpos) {
-			optarg = argv[optind++] + optpos;
-			optpos = 0;
-		}
-	}
-	return c;
-}
-
-int shell_kill(int pid, int sig)
-{
-	DebugBreak();
-	return -1;
-}
-
-int shell_gettimeofday(struct timeval *tv, void *tzvp)
-{
-	SYSTIM time;
-	if (!tv) return 0;
-	get_tim(&time);
-	tv->tv_sec = time / 1000000;
-	tv->tv_usec = time - (tv->tv_sec * 1000000);
-	return 0;
-}
 
 void put_rc(const char *func, FRESULT rc)
@@ -178,5 +64,5 @@
 		while (*p++);
 	}
-	ntstdio_printf(&ntstdio, "%s() =>%u FR_%s\n", func, (UINT)rc, p);
+	printf("%s() =>%u FR_%s\n", func, (UINT)rc, p);
 }
 
@@ -190,5 +76,5 @@
 		while (*p++);
 	}
-	ntstdio_printf(&ntstdio, "%s() =>%u %s\n", func, (UINT)rc, p);
+	printf("%s() =>%u %s\n", func, (UINT)rc, p);
 }
 
@@ -240,5 +126,5 @@
 
 	ntlibc_strlcat(path, "\n", sizeof(path));
-	ntstdio_printf(&ntstdio, path);
+	printf(path);
 
 	return 0;
@@ -252,5 +138,5 @@
 	char *fn;
 
-#if _USE_LFN
+#if FF_USE_LFN
 	fn = *fno->lfname ? fno->lfname : fno->fname;
 #else
@@ -263,5 +149,5 @@
 
 	if (list_option & LS_LONG) {
-		ntstdio_printf(&ntstdio, "%c%c%c%c%c %04d/%02d/%02d %02d:%02d:%02d ",
+		printf("%c%c%c%c%c %04d/%02d/%02d %02d:%02d:%02d ",
 			(fno->fattrib & AM_DIR) ? 'd' : '-',
 			(fno->fattrib & AM_RDO) ? 'r' : '-',
@@ -277,20 +163,20 @@
 
 		if (fno->fattrib & AM_DIR) {                    /* It is a directory */
-			ntstdio_printf(&ntstdio, "%10S ", " ");
+			printf("%10s ", " ");
 		}
 		else {
-			ntstdio_printf(&ntstdio, "%10d ", fno->fsize);
+			printf("%10lu ", fno->fsize);
 		}
 	}
 
 	if (fno->fattrib & AM_DIR) {                    /* It is a directory */
-		ntstdio_printf(&ntstdio, "\x1B[32m%s\x1B[0m\n", fn);
+		printf("\x1B[32m%s\x1B[0m\n", fn);
 	}
 	else {
-		ntstdio_printf(&ntstdio, "%s\n", fn);
-	}
-}
-
-#define LFN_BUF_SIZE (_MAX_LFN + 1)
+		printf("%s\n", fn);
+	}
+}
+
+#define LFN_BUF_SIZE (FF_MAX_LFN + 1)
 /* lsコマンド dir内 表示 */
 void print_ls(char *path_p, char *pattern_p, BYTE list_option)
@@ -298,5 +184,5 @@
 	FRESULT res;
 	FILINFO fno;
-	DIR dir;
+	FATFS_DIR dir;
 	char *fn;   /* This function assumes non-Unicode configuration */
 
@@ -307,13 +193,13 @@
 	path_backup = ff_memalloc(LFN_BUF_SIZE);
 	if (path_backup == NULL) {
-		ntstdio_printf(&ntstdio, "ff_memalloc err.\n");
+		printf("ff_memalloc err.\n");
 		return;
 	}
 
-#if _USE_LFN
+#if FF_USE_LFN
 	char *lfn = NULL;
 	lfn = ff_memalloc(LFN_BUF_SIZE);
 	if (lfn == NULL) {
-		ntstdio_printf(&ntstdio, "ff_memalloc err.\n");
+		printf("ff_memalloc err.\n");
 		ff_memfree(path_backup);
 		return;
@@ -333,6 +219,6 @@
 
 	while ((res == FR_OK) && (fno.fname[0] != 0)) {
-		if (pattern_p != NULL && (fno.fattrib & AM_DIR) && ((fno.fname[0] == '.') ? (pattern_p[0] == '.') : 1)) {/* DIR とパターンマッチしている場合は DIR 内部を ls する */
-#if _USE_LFN
+		if (pattern_p != NULL && (fno.fattrib & AM_DIR) && ((fno.fname[0] == '.') ? (pattern_p[0] == '.') : 1)) {/* FATFS_DIR とパターンマッチしている場合は FATFS_DIR 内部を ls する */
+#if FF_USE_LFN
 			fn = *fno.lfname ? fno.lfname : fno.fname;
 #else
@@ -351,9 +237,9 @@
 			}
 
-			ntstdio_printf(&ntstdio, "\n%s/%s:\n", path_p, fn);
+			printf("\n%s/%s:\n", path_p, fn);
 
 			print_ls(fn, NULL, list_option);
 
-			ntstdio_printf(&ntstdio, "\n");
+			printf("\n");
 
 			if ((res = f_chdrive(path_backup)) != FR_OK) {
@@ -384,9 +270,9 @@
 {
 	char *pattern_p = NULL, *basename_p = NULL, *dirname_p = NULL;
-	char default_pattern[_MAX_LFN] = "";
+	char default_pattern[FF_MAX_LFN] = "";
 	int c;
 	BYTE list_option = 0;
 
-	while ((c = musl_getopt(argc, argv, "al")) != -1) {
+	while ((c = getopt(argc, argv, "al")) != -1) {
 		switch (c) {
 		case 'a':
@@ -446,9 +332,9 @@
 		return 0;
 
-#if _USE_LFN
+#if FF_USE_LFN
 	/* LFN buffer alloc */
 	lfn = ff_memalloc(LFN_BUF_SIZE);
 	if (lfn == NULL) {
-		ntstdio_printf(&ntstdio, "alloc err.\n");
+		printf("alloc err.\n");
 		goto cp_end;
 	}
@@ -460,5 +346,5 @@
 	local_buff = ff_memalloc(64);
 	if (local_buff == NULL) {
-		ntstdio_printf(&ntstdio, "alloc err.\n");
+		printf("alloc err.\n");
 		goto cp_end;
 	}
@@ -470,7 +356,7 @@
 	if (res != FR_OK) {
 		if (res == FR_NO_FILE)
-			ntstdio_printf(&ntstdio, "src no file.\n", res);
+			printf("src no file.\n");
 		else
-			ntstdio_printf(&ntstdio, "src stat err(%d).\n", res);
+			printf("src stat err(%d).\n", res);
 		goto cp_end;
 	}
@@ -481,5 +367,5 @@
 		res = f_open(&src_fp, src_str_p, (FA_OPEN_EXISTING | FA_READ));
 		if (res != FR_OK) {
-			ntstdio_printf(&ntstdio, "src open err(%d).\n", res);
+			printf("src open err(%d).\n", res);
 			goto cp_end;
 		}
@@ -496,17 +382,17 @@
 				dst_mod_str_p = ff_memalloc(LFN_BUF_SIZE);
 				if (dst_mod_str_p == NULL) {
-					ntstdio_printf(&ntstdio, "alloc err.\n");
+					printf("alloc err.\n");
 					goto cp_end;
 				}
-				ntstdio_snprintf(dst_mod_str_p, LFN_BUF_SIZE, "%s/%s\0", dst_str_p, src_basename_p);
+				snprintf(dst_mod_str_p, LFN_BUF_SIZE, "%s/%s\0", dst_str_p, src_basename_p);
 				dst_str_p = dst_mod_str_p;
 			}
 			else {
-				ntstdio_printf(&ntstdio, "dst file exists.\n");
+				printf("dst file exists.\n");
 				goto cp_end_1;
 			}
 		}
 		else {
-			ntstdio_printf(&ntstdio, "src stat err(%d).\n", res);
+			printf("src stat err(%d).\n", res);
 			goto cp_end_1;
 		}
@@ -514,5 +400,5 @@
 	res = f_open(&dst_fp, dst_str_p, (FA_CREATE_NEW | FA_WRITE));
 	if (res != FR_OK) {
-		ntstdio_printf(&ntstdio, "dst open err(%d).\n", res);
+		printf("dst open err(%d).\n", res);
 		goto cp_end_1;
 	}
@@ -525,5 +411,5 @@
 		res = f_read(&src_fp, local_buff, sizeof(local_buff), &read_size);
 		if (res != FR_OK) {
-			ntstdio_printf(&ntstdio, "src read err(%d).\n", res);
+			printf("src read err(%d).\n", res);
 			goto cp_end_2;
 		}
@@ -532,9 +418,9 @@
 		res = f_write(&dst_fp, local_buff, read_size, &write_size);
 		if (res != FR_OK) {
-			ntstdio_printf(&ntstdio, "dst write err(%d).\n", res);
+			printf("dst write err(%d).\n", res);
 			goto cp_end_2;
 		}
 		if (read_size != write_size) {
-			ntstdio_printf(&ntstdio, "dst write err(disk full).\n", res);
+			printf("dst write err(disk full).\n");
 			goto cp_end_2;
 		}
@@ -622,13 +508,13 @@
 	unsigned int op_offset = 0, op_size = 0, op_end = 0;
 
-	while ((op = musl_getopt(argc, argv, "hduos0123456789xX")) != -1) {
+	while ((op = getopt(argc, argv, "hduos0123456789xX")) != -1) {
 		switch (op) {
 		case 'h': /* help */
-			ntstdio_printf(&ntstdio, " hexdump [OPTION] file\n");
-			ntstdio_printf(&ntstdio, "  -h : help\n");
-			ntstdio_printf(&ntstdio, "  -d : print all byte with convert and color [in character area] (default)\n");
-			ntstdio_printf(&ntstdio, "  -u : try print UTF-8 code [in character area]\n");
-			ntstdio_printf(&ntstdio, "  -oOFFSET : print start offset address from top\n");
-			ntstdio_printf(&ntstdio, "  -sSIZE   : print size\n");
+			printf(" hexdump [OPTION] file\n");
+			printf("  -h : help\n");
+			printf("  -d : print all byte with convert and color [in character area] (default)\n");
+			printf("  -u : try print UTF-8 code [in character area]\n");
+			printf("  -oOFFSET : print start offset address from top\n");
+			printf("  -sSIZE   : print size\n");
 			break;
 		case 'd': /* print one byte character [in character area] (default) */
@@ -661,5 +547,5 @@
 	/* position adjusting */
 	if (op_offset >= fsrc.fsize) {
-		ntstdio_printf(&ntstdio, "error : input offset is bigger than file size(0x%X).\n", fsrc.fsize);
+		printf("error : input offset is bigger than file size(0x%lX).\n", fsrc.fsize);
 		return 0;
 	}
@@ -674,5 +560,5 @@
 		char *pos = line;
 		int rst = sizeof(line);
-		int len = ntstdio_snprintf(pos, rst, "%08X: ", i);
+		int len = snprintf(pos, rst, "%08X: ", i);
 		pos += len;
 		rst -= len;
@@ -693,7 +579,7 @@
 			char c = data[j];
 			if (j != 7)
-				len = ntstdio_snprintf(pos, rst, "%02X ", c);
+				len = snprintf(pos, rst, "%02X ", c);
 			else
-				len = ntstdio_snprintf(pos, rst, "%02X-", c);
+				len = snprintf(pos, rst, "%02X-", c);
 			pos += len;
 			rst -= len;
@@ -723,7 +609,7 @@
 								break;
 							if (j + k != 7)
-								len = ntstdio_snprintf(pos, rst, "%02X ", data[j + k]);
+								len = snprintf(pos, rst, "%02X ", data[j + k]);
 							else
-								len = ntstdio_snprintf(pos, rst, "%02X-", data[j + k]);
+								len = snprintf(pos, rst, "%02X-", data[j + k]);
 							pos += len;
 							rst -= len;
@@ -743,5 +629,5 @@
 				apos += len;
 				arst -= len;
-				len = ntstdio_snprintf(apos, arst, "\x1B[%dm%c\x1B[0m", CCOLOR_RESET, ' ');
+				len = snprintf(apos, arst, "\x1B[%dm%c\x1B[0m", CCOLOR_RESET, ' ');
 				utf8_odd_bytes--;
 			}
@@ -763,5 +649,5 @@
 					c = '?';
 				}
-				len = ntstdio_snprintf(apos, arst, "\x1B[%dm%c\x1B[0m", ccolor, c);
+				len = snprintf(apos, arst, "\x1B[%dm%c\x1B[0m", ccolor, c);
 			}
 
@@ -772,16 +658,16 @@
 		for (int j = br; j < 16; j++) {
 			if (j != 7)
-				len = ntstdio_snprintf(pos, rst, "   ");
+				len = snprintf(pos, rst, "   ");
 			else
-				len = ntstdio_snprintf(pos, rst, "  -");
+				len = snprintf(pos, rst, "  -");
 			pos += len;
 			rst -= len;
 		}
 
-		len = ntstdio_snprintf(pos, rst, ": %s\n", ascii);
+		len = snprintf(pos, rst, ": %s\n", ascii);
 		pos += len;
 		rst -= len;
 
-		ntstdio_puts(&ntstdio, line);
+		puts(line);
 	}
 
@@ -796,7 +682,7 @@
 	char buf[30];
 
-	ret = shell_clock_gettime(CLOCK_REALTIME, &tp);
+	ret = clock_gettime(CLOCK_REALTIME, &tp);
 	if (ret != 0) {
-		ntstdio_printf(&ntstdio, "clock_gettime error %d", ret);
+		printf("clock_gettime error %d", ret);
 		return 0;
 	}
@@ -804,5 +690,5 @@
 	memset(buf, 0, sizeof(buf));
 	if (ctime_r(&tp.tv_sec, buf) == NULL) {
-		ntstdio_printf(&ntstdio, "ctime_r error");
+		printf("ctime_r error");
 		return 0;
 	}
@@ -812,5 +698,5 @@
 	buf[ret - 1] = '\0';
 
-	ntstdio_printf(&ntstdio, "%s .%09u\n", buf, tp.tv_nsec);
+	printf("%s .%09ld\n", buf, tp.tv_nsec);
 	return 0;
 }
@@ -819,10 +705,10 @@
 {
 	if (argc != 2) {
-		ntstdio_printf(&ntstdio, "info sys\n");
-		ntstdio_printf(&ntstdio, "info ver\n");
+		printf("info sys\n");
+		printf("info ver\n");
 		return 0;
 	}
 	if (strcmp(argv[1], "sys") == 0) {
-		ntstdio_printf(&ntstdio, TARGET_NAME" Monitor\n");
+		printf(TARGET_NAME" Monitor\n");
 		return 0;
 	}
@@ -830,8 +716,8 @@
 		int mj, mn, bd;
 		ntshell_version(&mj, &mn, &bd);
-		ntstdio_printf(&ntstdio, "Version %d.%d.%d\n", mj, mn, bd);
-		return 0;
-	}
-	ntstdio_printf(&ntstdio, "Unknown sub command found\n");
+		printf("Version %d.%d.%d\n", mj, mn, bd);
+		return 0;
+	}
+	printf("Unknown sub command found\n");
 	return -1;
 }
Index: asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/usrcmd.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/usrcmd.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/usrcmd.h	(revision 374)
@@ -56,8 +56,4 @@
 int usrcmd_exit(int argc, char **argv);
 
-void shell_abort();
-void shell_exit(int exitcd);
-int shell_kill(int pid, int sig);
-
 #endif
 
Index: asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/util/ntstdio.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/util/ntstdio.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/ntshell/util/ntstdio.h	(revision 374)
@@ -78,4 +78,5 @@
 	int pos;
 	unsigned int option;
+	void *exinf;
 } ntstdio_t;
 
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/fdtable.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/fdtable.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/fdtable.c	(revision 374)
@@ -68,50 +68,213 @@
 #include "kernel_cfg.h"
 #include <string.h>
-
-#define IO_TYPE_FREE	0
-#define IO_TYPE_SIO		1
-#define IO_TYPE_FILE	2
-#define IO_TYPE_DIR		3
-#define IO_TYPE_TCP		4
-#define IO_TYPE_UDP	5
-
-static struct _IO_FILE fd_table[8 * sizeof(FLGPTN)] = {
-	{ 0, IO_TYPE_SIO, 0, stdio_close, stdin_read, stdio_write, sio_seek, sio_ioctl },
-	{ 1, IO_TYPE_SIO, 0, stdio_close, stdio_read, stdout_write, sio_seek, sio_ioctl },
-	{ 2, IO_TYPE_SIO, 0, stdio_close, stdio_read, stderr_write, sio_seek, sio_ioctl },
+#include "util/ntstdio.h"
+#include "hal/serial_api.h"
+
+#ifdef _DEBUG
+static const char THIS_FILE[] = __FILE__;
+#endif
+
+static int stdio_close(struct SHELL_FILE *fp);
+static size_t stdio_read(struct SHELL_FILE *fp, unsigned char *data, size_t len);
+static size_t stdio_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static size_t stdin_read(struct SHELL_FILE *fp, unsigned char *data, size_t len);
+static size_t stdout_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static size_t stderr_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static void stdio_delete(struct SHELL_FILE *fp);
+
+static int sio_close(struct SHELL_FILE *fp);
+static size_t sio_read(struct SHELL_FILE *fp, unsigned char *data, size_t len);
+static size_t sio_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static off_t sio_seek(struct SHELL_FILE *fp, off_t ofs, int org);
+static int sio_ioctl(struct SHELL_FILE *fp, int req, void *arg);
+static bool_t sio_readable(struct SHELL_FILE *fp);
+static void sio_delete(struct SHELL_FILE *fp);
+
+IO_TYPE IO_TYPE_STDIN = { stdio_close, stdin_read, stdio_write, sio_seek, sio_ioctl, sio_readable, stdio_delete };
+IO_TYPE IO_TYPE_STDOUT = { stdio_close, stdio_read, stdout_write, sio_seek, sio_ioctl, sio_readable, stdio_delete };
+IO_TYPE IO_TYPE_STDERR = { stdio_close, stdio_read, stderr_write, sio_seek, sio_ioctl, sio_readable, stdio_delete };
+IO_TYPE IO_TYPE_SIO = { sio_close, sio_read, sio_write, sio_seek, sio_ioctl, sio_readable, sio_delete };
+ntstdio_t ntstdio;
+
+static struct SHELL_FILE fd_table[8 * sizeof(FLGPTN)] = {
+	{ 0, &IO_TYPE_STDIN, 0, .exinf = &ntstdio },
+	{ 1, &IO_TYPE_STDOUT, 0, .exinf = &ntstdio },
+	{ 2, &IO_TYPE_STDERR, 0,.exinf = &ntstdio },
 };
 #define fd_table_count (sizeof(fd_table) / sizeof(fd_table[0]))
 
-static int new_fd(int type, int id)
-{
+extern ntstdio_t ntstdio;
+extern serial_t stdio_uart;
+
+unsigned char ntstdio_xi(struct ntstdio_t *handle)
+{
+	return serial_getc((serial_t *)handle->exinf);
+}
+
+void ntstdio_xo(struct ntstdio_t *handle, unsigned char c)
+{
+	serial_putc((serial_t *)handle->exinf, c);
+}
+
+void sys_init(intptr_t exinf)
+{
+	ntstdio_init(&ntstdio, NTSTDIO_OPTION_LINE_ECHO | NTSTDIO_OPTION_CANON | NTSTDIO_OPTION_LF_CRLF | NTSTDIO_OPTION_LF_CR, ntstdio_xi, ntstdio_xo);
+	ntstdio.exinf = (void *)&stdio_uart;
+}
+
+int stdio_close(struct SHELL_FILE *fp)
+{
+	return -EPERM;
+}
+
+size_t stdio_read(struct SHELL_FILE *fp, unsigned char *data, size_t len)
+{
+	return -EPERM;
+}
+
+size_t stdio_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len)
+{
+	return -EPERM;
+}
+
+size_t stdin_read(struct SHELL_FILE *fp, unsigned char *data, size_t len)
+{
+	int i = 0;
+	while (i < len) {
+		int c = ntstdio_getc((struct ntstdio_t *)fp->exinf);
+		data[i++] = c;
+		if ((c == EOF) || (c == '\n'))
+			break;
+	}
+	return i;
+}
+
+size_t stdout_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len)
+{
+	for (int i = 0; i < len; i++) {
+		ntstdio_putc((struct ntstdio_t *)fp->exinf, data[i]);
+	}
+	return len;
+}
+
+size_t stderr_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len)
+{
+	for (int i = 0; i < len; i++) {
+		ntstdio_putc((struct ntstdio_t *)fp->exinf, data[i]);
+	}
+	return len;
+}
+
+void stdio_delete(struct SHELL_FILE *fp)
+{
+}
+
+int sio_close(struct SHELL_FILE *fp)
+{
+	return -EPERM;
+}
+
+size_t sio_read(struct SHELL_FILE *fp, unsigned char *data, size_t len)
+{
+	return -EPERM;
+}
+
+size_t sio_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len)
+{
+	return -EPERM;
+}
+
+off_t sio_seek(struct SHELL_FILE *fp, off_t ofs, int org)
+{
+	return -EPERM;
+}
+
+int sio_ioctl(struct SHELL_FILE *fp, int request, void *arg)
+{
+	switch (request) {
+	case TIOCGWINSZ:
+		return 0;
+	case TCGETS:
+		return sio_tcgetattr(fp->fd, (struct termios *)arg);
+	case TCSETS + TCSANOW:
+	case TCSETS + TCSADRAIN:
+	case TCSETS + TCSAFLUSH:
+		return sio_tcsetattr(fp->fd, request - TCSETS, (const struct termios *)arg);
+	}
+
+	return -EINVAL;
+}
+
+bool_t sio_readable(struct SHELL_FILE *fp)
+{
+	return fp->readevt_w != fp->readevt_r;
+}
+
+void sio_delete(struct SHELL_FILE *fp)
+{
+	free((serial_t *)((struct ntstdio_t *)fp->exinf)->exinf);
+	((struct ntstdio_t *)fp->exinf)->exinf = NULL;
+	free((struct ntstdio_t *)fp->exinf);
+	fp->exinf = NULL;
+}
+
+struct SHELL_FILE *new_fp(IO_TYPE *type, int id, int writable)
+{
+	struct SHELL_FILE *fp = NULL;
+	ER ret;
+
+	ret = wai_sem(SEM_FILEDESC);
+	if (ret < 0) {
+		syslog(LOG_ERROR, "wai_sem => %d", ret);
+	}
+
 	for (int fd = 3; fd < fd_table_count; fd++) {
-		struct _IO_FILE *fp = &fd_table[fd];
-		if (fp->type != IO_TYPE_FREE)
+		fp = &fd_table[fd];
+		if (fp->type != NULL)
 			continue;
 
-		memset(fp, 0, sizeof(struct _IO_FILE));
+		memset(fp, 0, sizeof(struct SHELL_FILE));
 		fp->fd = fd;
 		fp->type = type;
 		fp->handle = id;
-		return fd;
-	}
-
-	return -ENOMEM;
-}
-
-static struct _IO_FILE *id_to_fd(int type, int id)
-{
+		fp->writable = writable;
+		break;
+	}
+
+	ret = sig_sem(SEM_FILEDESC);
+	if (ret < 0) {
+		syslog(LOG_ERROR, "sig_sem => %d", ret);
+	}
+
+	return fp;
+}
+
+struct SHELL_FILE *id_to_fd(IO_TYPE *type, int id)
+{
+	struct SHELL_FILE *fp = NULL;
+	ER ret;
+
+	ret = wai_sem(SEM_FILEDESC);
+	if (ret < 0) {
+		syslog(LOG_ERROR, "wai_sem => %d", ret);
+	}
+
 	for (int fd = 3; fd < fd_table_count; fd++) {
-		struct _IO_FILE *fp = &fd_table[fd];
+		fp = &fd_table[fd];
 		if ((fp->type == type) && (fp->handle == id))
-			return fp;
-	}
-
-	return NULL;
-}
-
-static int delete_fd(int type, int id)
-{
-	struct _IO_FILE *fp = id_to_fd(type, id);
+			break;
+	}
+
+	ret = sig_sem(SEM_FILEDESC);
+	if (ret < 0) {
+		syslog(LOG_ERROR, "sig_sem => %d", ret);
+	}
+
+	return fp;
+}
+
+int delete_fd_by_id(IO_TYPE *type, int id)
+{
+	struct SHELL_FILE *fp = id_to_fd(type, id);
 	if (fp == NULL)
 		return -EBADF;
@@ -120,18 +283,26 @@
 }
 
-int delete_fp(struct _IO_FILE *fp)
-{
-	free(fp->pfile);
-	fp->pfile = NULL;
-	free(fp->pdir);
-	fp->pdir = NULL;
-	free(fp->psock);
-	fp->psock = NULL;
-	memset(fp, 0, sizeof(struct _IO_FILE));
+int delete_fp(struct SHELL_FILE *fp)
+{
+	ER ret;
+
+	fp->type->delete(fp);
+
+	ret = wai_sem(SEM_FILEDESC);
+	if (ret < 0) {
+		syslog(LOG_ERROR, "wai_sem => %d", ret);
+	}
+
+	memset(fp, 0, sizeof(struct SHELL_FILE));
+
+	ret = sig_sem(SEM_FILEDESC);
+	if (ret < 0) {
+		syslog(LOG_ERROR, "sig_sem => %d", ret);
+	}
 
 	return 0;
 }
 
-struct _IO_FILE *fd_to_fp(int fd)
+struct SHELL_FILE *fd_to_fp(int fd)
 {
 	if ((fd < 0) || (fd >= fd_table_count))
@@ -140,151 +311,5 @@
 }
 
-struct _IO_FILE *new_sio_fd(int sioid)
-{
-	int fd = new_fd(IO_TYPE_SIO, sioid);
-	if ((fd < 0) || (fd >= fd_table_count))
-		return NULL;
-
-	struct _IO_FILE *fp = &fd_table[fd];
-	fp->close = sio_close;
-	fp->read = sio_read;
-	fp->write = sio_write;
-	fp->seek = sio_seek;
-	fp->ioctl = sio_ioctl;
-	fp->writable = 1;
-
-	return fp;
-}
-
-int delete_sio_fd(int sioid)
-{
-	return delete_fd(IO_TYPE_SIO, sioid);
-}
-
-struct _IO_FILE *sioid_to_fd(int sioid)
-{
-	return id_to_fd(IO_TYPE_SIO, sioid);
-}
-
-struct _IO_FILE *new_file_fd(int fileid)
-{
-	int fd = new_fd(IO_TYPE_FILE, fileid);
-	if ((fd < 0) || (fd >= fd_table_count))
-		return NULL;
-
-	struct _IO_FILE *fp = &fd_table[fd];
-	fp->close = file_close;
-	fp->read = file_read;
-	fp->write = file_write;
-	fp->seek = file_seek;
-	fp->ioctl = file_ioctl;
-	fp->writable = 1;
-	fp->pfile = malloc(sizeof(FIL));
-	memset(fp->pfile, 0, sizeof(FIL));
-
-	return fp;
-}
-
-int delete_file_fd(int fileid)
-{
-	return delete_fd(IO_TYPE_FILE, fileid);
-}
-
-struct _IO_FILE *fileid_to_fd(int fileid)
-{
-	return id_to_fd(IO_TYPE_FILE, fileid);
-}
-
-struct _IO_FILE *new_dir_fd(int fileid)
-{
-	int fd = new_fd(IO_TYPE_DIR, fileid);
-	if ((fd < 0) || (fd >= fd_table_count))
-		return NULL;
-
-	struct _IO_FILE *fp = &fd_table[fd];
-	fp->close = dir_close;
-	fp->read = dir_read;
-	fp->write = dir_write;
-	fp->seek = dir_seek;
-	fp->ioctl = dir_ioctl;
-	fp->writable = 0;
-	fp->pdir = malloc(sizeof(struct _IO_DIR));
-	memset(fp->pdir, 0, sizeof(struct _IO_DIR));
-
-	return fp;
-}
-
-int delete_dir_fd(int dirid)
-{
-	return delete_fd(IO_TYPE_DIR, dirid);
-}
-
-struct _IO_FILE *dirid_to_fd(int dirid)
-{
-	return id_to_fd(IO_TYPE_DIR, dirid);
-}
-
-#ifndef NTSHELL_NO_SOCKET
-struct _IO_FILE *new_tcp_fd(int tcpid)
-{
-	int fd = new_fd(IO_TYPE_TCP, tcpid);
-	if ((fd < 0) || (fd >= fd_table_count))
-		return NULL;
-
-	struct _IO_FILE *fp = &fd_table[fd];
-	fp->close = tcp_fd_close;
-	fp->read = tcp_fd_read;
-	fp->write = tcp_fd_write;
-	fp->seek = tcp_fd_seek;
-	fp->ioctl = tcp_fd_ioctl;
-	fp->writable = 0;
-	fp->psock = malloc(sizeof(socket_t));
-	memset(fp->psock, 0, sizeof(socket_t));
-
-	return fp;
-}
-
-int delete_tcp_fd(int tcpid)
-{
-	return delete_fd(IO_TYPE_TCP, tcpid);
-}
-
-struct _IO_FILE *tcpid_to_fd(int tcpid)
-{
-	return id_to_fd(IO_TYPE_TCP, tcpid);
-}
-
-struct _IO_FILE *new_udp_fd(int udpid)
-{
-	int fd = new_fd(IO_TYPE_UDP, udpid);
-	if ((fd < 0) || (fd >= fd_table_count))
-		return NULL;
-
-	struct _IO_FILE *fp = &fd_table[fd];
-	fp->close = udp_fd_close;
-	fp->read = udp_fd_read;
-	fp->write = udp_fd_write;
-	fp->seek = udp_fd_seek;
-	fp->ioctl = udp_fd_ioctl;
-	fp->writable = 1;
-	fp->psock = malloc(sizeof(socket_t));
-	memset(fp->psock, 0, sizeof(socket_t));
-
-	return fp;
-}
-
-int delete_udp_fd(int udpid)
-{
-	return delete_fd(IO_TYPE_UDP, udpid);
-}
-
-struct _IO_FILE *udpid_to_fd(int udpid)
-{
-	return id_to_fd(IO_TYPE_UDP, udpid);
-}
-
-#endif
-
-void memor(void *dst, void *src, size_t len)
+void memand(void *dst, void *src, size_t len)
 {
 	uint8_t *d = (uint8_t *)dst;
@@ -293,5 +318,5 @@
 
 	while (s < e) {
-		*d++ |= *s++;
+		*d++ &= *s++;
 	}
 }
@@ -336,20 +361,20 @@
 
 	ret = shell_get_evts(&evts, tmout);
-	if (rfds != NULL)
-		memset(rfds, 0, sizeof(fd_set));
-	if (wfds != NULL)
-		memset(wfds, 0, sizeof(fd_set));
-	if (efds != NULL)
-		memset(efds, 0, sizeof(fd_set));
 	if (ret == E_OK) {
 		if (rfds != NULL)
-			memor(rfds, &evts.readfds, sizeof(fd_set));
+			memand(rfds, &evts.readfds, sizeof(fd_set));
 		if (wfds != NULL)
-			memor(wfds, &evts.writefds, sizeof(fd_set));
+			memand(wfds, &evts.writefds, sizeof(fd_set));
 		if (efds != NULL)
-			memor(efds, &evts.errorfds, sizeof(fd_set));
+			memand(efds, &evts.errorfds, sizeof(fd_set));
 		return evts.count;
 	}
 	if (ret == E_TMOUT) {
+		if (rfds != NULL)
+			memset(rfds, 0, sizeof(fd_set));
+		if (wfds != NULL)
+			memset(wfds, 0, sizeof(fd_set));
+		if (efds != NULL)
+			memset(efds, 0, sizeof(fd_set));
 		return 0;
 	}
@@ -419,18 +444,13 @@
 {
 	int fd = STDIN_FILENO;
-	struct _IO_FILE *fp = &fd_table[fd];
-	T_SERIAL_RPOR rpor;
+	struct SHELL_FILE *fp = &fd_table[fd];
 	FLGPTN flgptn = 0;
 
-	ER ret = serial_ref_por(SIO_PORTID, &rpor);
-	if (ret != E_OK)
-		return;
-
-	if (rpor.reacnt != 0) {
+	if (serial_readable((serial_t *)((struct ntstdio_t *)fp->exinf)->exinf)) {
 		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
 
 		FD_SET(fd, (fd_set *)&flgptn);
 	}
-	if (rpor.wricnt != 0) {
+	if (serial_writable((serial_t *)((struct ntstdio_t *)fp->exinf)->exinf)) {
 		if (fp->writeevt_w == fp->writeevt_r) fp->writeevt_w++;
 
@@ -447,18 +467,13 @@
 {
 	int fd = STDIN_FILENO;
-	struct _IO_FILE *fp = &fd_table[fd];
-	T_SERIAL_RPOR rpor;
+	struct SHELL_FILE *fp = &fd_table[fd];
 	*flgptn = 0;
 
-	ER ret = serial_ref_por(SIO_PORTID, &rpor);
-	if (ret != E_OK)
-		return;
-
-	if (rpor.reacnt != 0) {
+	if (serial_readable((serial_t *)((struct ntstdio_t *)fp->exinf)->exinf)) {
 		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
 
 		FD_SET(fd, (fd_set *)flgptn);
 	}
-	if (rpor.wricnt != 0) {
+	if (serial_writable((serial_t *)((struct ntstdio_t *)fp->exinf)->exinf)) {
 		if (fp->writeevt_w == fp->writeevt_r) fp->writeevt_w++;
 
@@ -466,169 +481,4 @@
 	}
 }
-
-#ifndef NTSHELL_NO_SOCKET
-
-ER socket_tcp_callback(ID cepid, FN fncd, void *p_parblk)
-{
-	struct _IO_FILE *fp = tcpid_to_fd(cepid);
-	FLGPTN flgptn = 0;
-	ER ret;
-	int len;
-
-	if (fp == NULL)
-		return E_PAR;
-
-	int fd = fp->fd;
-	FD_SET(fd, (fd_set *)&flgptn);
-
-	switch (fncd) {
-	case TFN_TCP_RCV_BUF:
-		len = *(int *)p_parblk;
-		if (len <= 0)
-			return E_OK;
-
-		ret = wai_sem(SEM_FILEDESC);
-		if (ret < 0) {
-			syslog(LOG_ERROR, "wai_sem => %d", ret);
-		}
-		fp->psock->len += len;
-		ret = sig_sem(SEM_FILEDESC);
-		if (ret < 0) {
-			syslog(LOG_ERROR, "sig_sem => %d", ret);
-		}
-
-		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-
-	case TFN_TCP_RCV_DAT:
-		len = *(int *)p_parblk;
-		if (len <= 0)
-			return E_OK;
-
-		ret = wai_sem(SEM_FILEDESC);
-		if (ret < 0) {
-			syslog(LOG_ERROR, "wai_sem => %d", ret);
-		}
-		fp->psock->len += len;
-		ret = sig_sem(SEM_FILEDESC);
-		if (ret < 0) {
-			syslog(LOG_ERROR, "sig_sem => %d", ret);
-		}
-
-		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-
-	case TFN_TCP_SND_DAT:
-		if (fp->writeevt_w == fp->writeevt_r) fp->writeevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-
-	case TFN_TCP_CAN_CEP:
-		if (fp->errorevt_w == fp->errorevt_r) fp->errorevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-
-	case TFN_TCP_DEL_REP:
-		delete_tcp_rep(cepid);
-		return E_OK;
-
-	case TFN_TCP_DEL_CEP:
-		delete_tcp_fd(cepid);
-		return E_OK;
-
-	default:
-		return E_OK;
-	}
-}
-
-ER socket_udp_callback(ID cepid, FN fncd, void *p_parblk)
-{
-	struct _IO_FILE *fp = udpid_to_fd(cepid);
-	FLGPTN flgptn = 0;
-	int len;
-
-	if (fp == NULL)
-		return E_PAR;
-
-	int fd = fp->fd;
-	FD_SET(fd, (fd_set *)&flgptn);
-
-	switch (fncd) {
-	case TEV_UDP_RCV_DAT:
-	{
-		T_UDP_RCV_DAT_PARA *udppara = (T_UDP_RCV_DAT_PARA *)p_parblk;
-		len = udppara->len;
-		if (len <= 0)
-			return E_OK;
-
-		ER ret = wai_sem(SEM_FILEDESC);
-		if (ret < 0) {
-			syslog(LOG_ERROR, "wai_sem => %d", ret);
-		}
-		fp->psock->len = len;
-		if (fp->psock->input != NULL) {
-			ret = rel_net_buf(fp->psock->input);
-			if (ret < 0) {
-				syslog(LOG_ERROR, "rel_net_buf => %d", ret);
-			}
-		}
-		fp->psock->input = udppara->input;
-		fp->psock->buf = GET_UDP_SDU(udppara->input, udppara->off);
-		memset(&fp->psock->raddr4, 0, sizeof(fp->psock->raddr4));
-		fp->psock->raddr4.sin_family = AF_INET;
-		fp->psock->raddr4.sin_port = htons(udppara->rep4.portno);
-		fp->psock->raddr4.sin_addr.s_addr = htonl(udppara->rep4.ipaddr);
-		udppara->input->flags |= NB_FLG_NOREL_IFOUT;
-		ret = sig_sem(SEM_FILEDESC);
-		if (ret < 0) {
-			syslog(LOG_ERROR, "sig_sem => %d", ret);
-		}
-
-		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-	}
-	case TFN_UDP_CRE_CEP:
-		return E_OK;
-
-	case TFN_UDP_RCV_DAT:
-		len = *(int *)p_parblk;
-		if (len <= 0)
-			return E_OK;
-
-		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-
-	case TFN_UDP_SND_DAT:
-		if (fp->writeevt_w == fp->writeevt_r) fp->writeevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-
-	case TFN_UDP_CAN_CEP:
-		if (fp->errorevt_w == fp->errorevt_r) fp->errorevt_w++;
-
-		set_flg(FLG_SELECT_WAIT, flgptn);
-		return E_OK;
-
-	case TFN_UDP_DEL_CEP:
-		delete_udp_fd(cepid);
-		return E_OK;
-
-	default:
-		return E_OK;
-	}
-}
-
-#endif
 
 ER shell_get_evts(struct fd_events *evts, TMO tmout)
@@ -642,5 +492,5 @@
 		ER ret;
 		FLGPTN waitptn, flgptn, readfds = 0, writefds = 0;
-		struct _IO_FILE *fp = NULL;
+		struct SHELL_FILE *fp = NULL;
 
 		stdio_update_evts();
@@ -656,36 +506,8 @@
 #ifndef NTSHELL_NO_SOCKET
 			if (FD_ISSET(fd, &evts->readfds)) {
-				if ((fp->type == IO_TYPE_TCP) && (fp->psock->cepid != 0)) {
-					if (fp->psock->len == 0) {
-						ret = tcp_rcv_buf(fp->psock->cepid, &fp->psock->input, TMO_NBLK);
-						if ((ret != E_WBLK) && (ret != E_OBJ) && (ret < 0)) {
-							syslog(LOG_ERROR, "tcp_rcv_buf => %d", ret);
-							//return ret;
-						}
-						if (ret > 0) {
-							ret = wai_sem(SEM_FILEDESC);
-							if (ret < 0) {
-								syslog(LOG_ERROR, "wai_sem => %d", ret);
-							}
-							fp->psock->len += ret;
-							ret = sig_sem(SEM_FILEDESC);
-							if (ret < 0) {
-								syslog(LOG_ERROR, "sig_sem => %d", ret);
-							}
-						}
-					}
-					else ret = 1;
-					if (ret > 0) {
-						FD_SET(fd, (fd_set *)&readfds);
-						count++;
-						if (fp->readevt_w == fp->readevt_r) fp->readevt_r--;
-					}
-				}
-				else if ((fp->type == IO_TYPE_UDP) && (fp->psock->cepid != 0)) {
-					if (fp->psock->input != NULL) {
-						FD_SET(fd, (fd_set *)&readfds);
-						count++;
-						if (fp->readevt_w == fp->readevt_r) fp->readevt_r--;
-					}
+				if (fp->type->readable(fp)) {
+					FD_SET(fd, (fd_set *)&readfds);
+					count++;
+					if (fp->readevt_w == fp->readevt_r) fp->readevt_r--;
 				}
 				else {
@@ -786,5 +608,5 @@
 void clean_fd()
 {
-	struct _IO_FILE *fp = NULL;
+	struct SHELL_FILE *fp = NULL;
 	for (int fd = 3; fd < fd_table_count; fd++) {
 		fp = &fd_table[fd];
@@ -792,5 +614,5 @@
 			continue;
 
-		fp->close(fp);
+		fp->type->close(fp);
 
 		delete_fp(fp);
@@ -800,9 +622,9 @@
 int shell_ioctl(int fd, int request, void *arg)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
 	if (fp == NULL)
 		return -EBADF;
 
-	return fp->ioctl(fp, request, arg);
+	return fp->type->ioctl(fp, request, arg);
 }
 
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/io_stub.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/io_stub.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/io_stub.c	(revision 374)
@@ -1,7 +1,7 @@
 /*
  *  TOPPERS ECHONET Lite Communication Middleware
- * 
+ *
  *  Copyright (C) 2017 Cores Co., Ltd. Japan
- * 
+ *
  *  上記著作権者は，以下の(1)～(4)の条件を満たす場合に限り，本ソフトウェ
  *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
@@ -26,5 +26,5 @@
  *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
  *      免責すること．
- * 
+ *
  *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
  *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
@@ -32,5 +32,5 @@
  *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
  *  の責任を負わない．
- * 
+ *
  *  @(#) $Id$
  */
@@ -43,4 +43,5 @@
 #include <sil.h>
 #include <string.h>
+#include "syssvc/serial.h"
 #include "syssvc/syslog.h"
 #include "socket_stub.h"
@@ -49,4 +50,5 @@
 #include "core/ntlibc.h"
 #include "kernel_cfg.h"
+#include "target_syssvc.h"
 
 int fresult2errno(FRESULT res)
@@ -77,15 +79,37 @@
 }
 
-int shell_open(const char * path, int flags, void *arg)
-{
-	FRESULT res;
-	struct _IO_FILE *fp;
+static int file_close(struct SHELL_FILE *fp);
+static size_t file_read(struct SHELL_FILE *fp, unsigned char *data, size_t len);
+static size_t file_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static off_t file_seek(struct SHELL_FILE *fp, off_t ofs, int org);
+static int file_ioctl(struct SHELL_FILE *fp, int req, void *arg);
+static bool_t file_readable(struct SHELL_FILE *fp);
+static void file_delete(struct SHELL_FILE *fp);
+
+static int dir_close(struct SHELL_FILE *fp);
+static size_t dir_read(struct SHELL_FILE *fp, unsigned char *data, size_t len);
+static size_t dir_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static off_t dir_seek(struct SHELL_FILE *fp, off_t ofs, int org);
+static int dir_ioctl(struct SHELL_FILE *fp, int req, void *arg);
+static bool_t dir_readable(struct SHELL_FILE *fp);
+static void dir_delete(struct SHELL_FILE *fp);
+
+IO_TYPE IO_TYPE_FILE = { file_close, file_read, file_write, file_seek, file_ioctl, file_readable, file_delete };
+IO_TYPE IO_TYPE_DIR = { dir_close, dir_read, dir_write, dir_seek, dir_ioctl, dir_readable, dir_delete };
+
+int shell_open(const char *path, int flags, void *arg)
+{
+	FRESULT res;
+	struct SHELL_FILE *fp;
 
 	if (flags & O_DIRECTORY) {
-		fp = new_dir_fd(0);
+		fp = new_fp(&IO_TYPE_DIR, 0, 0);
 		if (fp == NULL)
 			return -ENOMEM;
 
-		DIR *dir = &fp->pdir->dir;
+		fp->exinf = malloc(sizeof(struct SHELL_DIR));
+		memset(fp->exinf, 0, sizeof(struct SHELL_DIR));
+
+		FATFS_DIR *dir = &((struct SHELL_DIR *)fp->exinf)->dir;
 		FRESULT res;
 		if ((res = f_opendir(dir, path)) != FR_OK) {
@@ -95,7 +119,10 @@
 	}
 
-	fp = new_file_fd(0);
+	fp = new_fp(&IO_TYPE_FILE, 0, 1);
 	if (fp == NULL)
 		return -ENOMEM;
+
+	fp->exinf = malloc(sizeof(FIL));
+	memset(fp->exinf, 0, sizeof(FIL));
 
 	BYTE fmd = 0;
@@ -133,5 +160,5 @@
 	}
 
-	if ((res = f_open(fp->pfile, path, fmd)) == FR_OK) {
+	if ((res = f_open((FIL *)fp->exinf, path, fmd)) == FR_OK) {
 		fp->handle = fp->fd;
 		return fp->fd;
@@ -141,9 +168,9 @@
 }
 
-int file_close(struct _IO_FILE *fp)
-{
-	FRESULT res;
-
-	if ((res = f_close(fp->pfile)) == FR_OK) {
+int file_close(struct SHELL_FILE *fp)
+{
+	FRESULT res;
+
+	if ((res = f_close((FIL *)fp->exinf)) == FR_OK) {
 		return 0;
 	}
@@ -152,10 +179,10 @@
 }
 
-size_t file_read(struct _IO_FILE *fp, unsigned char *data, size_t len)
+size_t file_read(struct SHELL_FILE *fp, unsigned char *data, size_t len)
 {
 	unsigned int ret = 0;
 	FRESULT res;
 
-	if ((res = f_read(fp->pfile, data, len, &ret)) != FR_OK)
+	if ((res = f_read((FIL *)fp->exinf, data, len, &ret)) != FR_OK)
 		return -EIO;
 
@@ -163,10 +190,10 @@
 }
 
-size_t file_write(struct _IO_FILE *fp, const unsigned char *data, size_t len)
+size_t file_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len)
 {
 	unsigned int ret = 0;
 	FRESULT res;
 
-	if ((res = f_write(fp->pfile, data, len, &ret)) != FR_OK)
+	if ((res = f_write((FIL *)fp->exinf, data, len, &ret)) != FR_OK)
 		return -EIO;
 
@@ -174,5 +201,5 @@
 }
 
-off_t file_seek(struct _IO_FILE *fp, off_t ptr, int dir)
+off_t file_seek(struct SHELL_FILE *fp, off_t ptr, int dir)
 {
 	switch (dir) {
@@ -191,15 +218,15 @@
 
 	FRESULT res;
-	if ((res = f_seek(fp->pfile, ptr, dir)) != FR_OK)
+	if ((res = f_seek((FIL *)fp->exinf, ptr, dir)) != FR_OK)
 		return -EIO;
 
-	return fp->pfile->fptr;
-}
-
-int file_ioctl(struct _IO_FILE *fp, int req, void *arg)
+	return ((FIL *)fp->exinf)->fptr;
+}
+
+int file_ioctl(struct SHELL_FILE *fp, int req, void *arg)
 {
 	DRESULT res;
 
-	if ((res = disk_ioctl(fp->pfile->fs->drv, req, arg) != RES_OK))
+	if ((res = disk_ioctl(((FIL *)fp->exinf)->fs->drv, req, arg) != RES_OK))
 		return -EINVAL;
 
@@ -207,11 +234,22 @@
 }
 
+bool_t file_readable(struct SHELL_FILE *fp)
+{
+	return fp->readevt_w != fp->readevt_r;
+}
+
+void file_delete(struct SHELL_FILE *fp)
+{
+	free((FIL *)fp->exinf);
+	fp->exinf = NULL;
+}
+
 int shell_close(int fd)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
-	if (fp == NULL)
-		return -EBADF;
-
-	int ret = fp->close(fp);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
+	if (fp == NULL)
+		return -EBADF;
+
+	int ret = fp->type->close(fp);
 
 	delete_fp(fp);
@@ -222,9 +260,9 @@
 ssize_t shell_read(int fd, void *data, size_t len)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
-	if (fp == NULL)
-		return -EBADF;
-
-	return fp->read(fp, (unsigned char *)data, len);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
+	if (fp == NULL)
+		return -EBADF;
+
+	return fp->type->read(fp, (unsigned char *)data, len);
 }
 
@@ -232,5 +270,5 @@
 {
 	int result = 0;
-	struct _IO_FILE *fp = fd_to_fp(fd);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
 	if (fp == NULL)
 		return -EBADF;
@@ -238,5 +276,5 @@
 	const struct iovec *end = &iov[iovcnt];
 	for (; iov < end; iov++) {
-		result += fp->read(fp, (unsigned char *)iov->iov_base, iov->iov_len);
+		result += fp->type->read(fp, (unsigned char *)iov->iov_base, iov->iov_len);
 	}
 
@@ -246,9 +284,9 @@
 ssize_t shell_write(int fd, const void *data, size_t len)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
-	if (fp == NULL)
-		return -EBADF;
-
-	return fp->write(fp, (unsigned char *)data, len);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
+	if (fp == NULL)
+		return -EBADF;
+
+	return fp->type->write(fp, (unsigned char *)data, len);
 }
 
@@ -256,5 +294,5 @@
 {
 	int result = 0;
-	struct _IO_FILE *fp = fd_to_fp(fd);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
 	if (fp == NULL)
 		return -EBADF;
@@ -262,5 +300,5 @@
 	const struct iovec *end = &iov[iovcnt];
 	for (; iov < end; iov++) {
-		result += fp->write(fp, (unsigned char *)iov->iov_base, iov->iov_len);
+		result += fp->type->write(fp, (unsigned char *)iov->iov_base, iov->iov_len);
 	}
 
@@ -270,9 +308,9 @@
 int shell_llseek(int fd, off_t ptr, off_t *result, int dir)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
-	if (fp == NULL)
-		return -EBADF;
-
-	off_t ret = fp->seek(fp, ptr, dir);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
+	if (fp == NULL)
+		return -EBADF;
+
+	off_t ret = fp->type->seek(fp, ptr, dir);
 	if (ret < 0)
 		return ret;
@@ -284,5 +322,5 @@
 int shell_fstat(int fd, struct stat * st)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
 	if (fp == NULL)
 		return -EBADF;
@@ -296,5 +334,5 @@
 int shell_fsync(int fd)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
 	if (fp == NULL)
 		return -EBADF;
@@ -304,10 +342,10 @@
 int shell_ftruncate(int fd, off_t length)
 {
-	struct _IO_FILE *fp = fd_to_fp(fd);
-	if (fp == NULL)
-		return -EBADF;
-
-	FRESULT res;
-	if ((res = f_truncate(fp->pfile)) != FR_OK)
+	struct SHELL_FILE *fp = fd_to_fp(fd);
+	if (fp == NULL)
+		return -EBADF;
+
+	FRESULT res;
+	if ((res = f_truncate((FIL *)fp->exinf)) != FR_OK)
 		return fresult2errno(res);
 
@@ -320,72 +358,80 @@
 }
 
+extern IO_TYPE IO_TYPE_SIO;
+
 int sio_tcgetattr(int fd, struct termios *termios)
 {
-	extern ntstdio_t ntstdio;
-
-	if (fd == STDIN_FILENO) {
-		memset(termios, 0, sizeof(*termios));
-
-		if (ntstdio.option & NTSTDIO_OPTION_LINE_ECHO) {
-			termios->c_lflag |= ECHO;
+	struct SHELL_FILE *fp = fd_to_fp(fd);
+	if ((fp == NULL) || (fp->type != &IO_TYPE_SIO))
+		return -EBADF;
+
+	ntstdio_t *ntstdio = (ntstdio_t *)fp->exinf;
+
+	memset(termios, 0, sizeof(*termios));
+
+	if (ntstdio->option & NTSTDIO_OPTION_LINE_ECHO) {
+		termios->c_lflag |= ECHO;
+	}
+	else {
+		termios->c_lflag &= ~ECHO;
+	}
+	if (ntstdio->option & NTSTDIO_OPTION_CANON) {
+		termios->c_lflag |= ICANON;
+	}
+	else {
+		termios->c_lflag &= ~ICANON;
+	}
+	if (ntstdio->option & NTSTDIO_OPTION_LF_CR) {
+		termios->c_iflag |= INLCR;
+	}
+	else {
+		termios->c_iflag &= ~INLCR;
+	}
+	if (ntstdio->option & NTSTDIO_OPTION_LF_CRLF) {
+		termios->c_oflag |= ONLCR;
+	}
+	else {
+		termios->c_oflag &= ~ONLCR;
+	}
+
+	return 0;
+}
+
+int sio_tcsetattr(int fd, int optional_actions, const struct termios *termios)
+{
+	struct SHELL_FILE *fp = fd_to_fp(fd);
+	if ((fp == NULL) || (fp->type != &IO_TYPE_SIO))
+		return -EBADF;
+
+	ntstdio_t *ntstdio = (ntstdio_t *)fp->exinf;
+
+	if (optional_actions == TCSANOW) {
+		if (termios->c_lflag & ECHO) {
+			ntstdio->option |= NTSTDIO_OPTION_LINE_ECHO;
 		}
 		else {
-			termios->c_lflag &= ~ECHO;
-		}
-		if (ntstdio.option & NTSTDIO_OPTION_CANON) {
-			termios->c_lflag |= ICANON;
+			ntstdio->option &= ~NTSTDIO_OPTION_LINE_ECHO;
+		}
+		if (termios->c_lflag & ICANON) {
+			ntstdio->option |= NTSTDIO_OPTION_CANON;
 		}
 		else {
-			termios->c_lflag &= ~ICANON;
-		}
-		if (ntstdio.option & NTSTDIO_OPTION_LF_CR) {
-			termios->c_iflag |= INLCR;
+			ntstdio->option &= ~NTSTDIO_OPTION_CANON;
+		}
+		if (termios->c_iflag & INLCR) {
+			ntstdio->option |= NTSTDIO_OPTION_LF_CR;
 		}
 		else {
-			termios->c_iflag &= ~INLCR;
-		}
-		if (ntstdio.option & NTSTDIO_OPTION_LF_CRLF) {
-			termios->c_oflag |= ONLCR;
+			ntstdio->option &= ~NTSTDIO_OPTION_LF_CR;
+		}
+		if (termios->c_oflag & ONLCR) {
+			ntstdio->option |= NTSTDIO_OPTION_LF_CRLF;
 		}
 		else {
-			termios->c_oflag &= ~ONLCR;
+			ntstdio->option &= ~NTSTDIO_OPTION_LF_CRLF;
 		}
 		return 0;
 	}
-	shell_abort();
-	return 0;
-}
-
-int sio_tcsetattr(int fd, int optional_actions, const struct termios *termios)
-{
-	extern ntstdio_t ntstdio;
-
-	if ((fd == STDIN_FILENO) && (optional_actions == TCSANOW)) {
-		if (termios->c_lflag & ECHO) {
-			ntstdio.option |= NTSTDIO_OPTION_LINE_ECHO;
-		}
-		else {
-			ntstdio.option &= ~NTSTDIO_OPTION_LINE_ECHO;
-		}
-		if (termios->c_lflag & ICANON) {
-			ntstdio.option |= NTSTDIO_OPTION_CANON;
-		}
-		else {
-			ntstdio.option &= ~NTSTDIO_OPTION_CANON;
-		}
-		if (termios->c_iflag & INLCR) {
-			ntstdio.option |= NTSTDIO_OPTION_LF_CR;
-		}
-		else{
-			ntstdio.option &= ~NTSTDIO_OPTION_LF_CR;
-		}
-		if (termios->c_oflag & ONLCR) {
-			ntstdio.option |= NTSTDIO_OPTION_LF_CRLF;
-		}
-		else {
-			ntstdio.option &= ~NTSTDIO_OPTION_LF_CRLF;
-		}
-		return 0;
-	}
+
 	shell_abort();
 	return 0;
@@ -396,11 +442,11 @@
 	FILINFO fi;
 	FRESULT ret;
-#if _USE_LFN
-	static char lfn[_MAX_LFN + 1];   /* Buffer to store the LFN */
+#if FF_USE_LFN
+	static char lfn[FF_MAX_LFN + 1];   /* Buffer to store the LFN */
 	fi.lfname = lfn;
 	fi.lfsize = sizeof lfn;
 #endif
 	if (strcmp(path, ".") == 0) {
-		char cwd[_MAX_LFN];
+		char cwd[FF_MAX_LFN];
 		if ((ret = f_getcwd(cwd, sizeof(cwd))) != FR_OK) {
 			return fresult2errno(ret);
@@ -426,5 +472,5 @@
 	st->st_mtim.tv_nsec = 0;
 	st->st_mtim.tv_sec = fi.fdate + fi.ftime;
-	st->st_mode  = (S_IRUSR | S_IRGRP | S_IROTH);
+	st->st_mode = (S_IRUSR | S_IRGRP | S_IROTH);
 	st->st_mode |= (fi.fattrib & AM_RDO) ? 0 : (S_IWUSR | S_IWGRP | S_IWOTH);
 	st->st_mode |= (fi.fattrib & (AM_DIR | AM_VOL)) ? S_IFDIR : S_IFREG;
@@ -485,6 +531,6 @@
 	BYTE mask = AM_RDO | AM_SYS; // AM_ARC, AM_HID
 
-	if(mode & S_IREAD) {
-		if((mode & S_IWRITE) == 0) {
+	if (mode & S_IREAD) {
+		if ((mode & S_IWRITE) == 0) {
 			attr |= AM_RDO;
 		}
@@ -494,5 +540,5 @@
 	}
 
-	if((res = f_chmod(path, attr, mask)) != FR_OK) {
+	if ((res = f_chmod(path, attr, mask)) != FR_OK) {
 		return fresult2errno(res);
 	}
@@ -507,6 +553,6 @@
 	BYTE mask = AM_RDO | AM_SYS; // AM_ARC, AM_HID
 
-	if(mode & S_IREAD) {
-		if((mode & S_IWRITE) == 0) {
+	if (mode & S_IREAD) {
+		if ((mode & S_IWRITE) == 0) {
 			attr |= AM_RDO;
 		}
@@ -516,5 +562,5 @@
 	}
 
-	if((res = f_chmod(path, attr, mask)) != FR_OK) {
+	if ((res = f_chmod(path, attr, mask)) != FR_OK) {
 		return fresult2errno(res);
 	}
@@ -526,5 +572,5 @@
 {
 	FRESULT ret;
-	if((ret = f_getcwd(buf, size)) != FR_OK) {
+	if ((ret = f_getcwd(buf, size)) != FR_OK) {
 		return NULL;
 	}
@@ -549,8 +595,8 @@
 }
 
-int dir_close(struct _IO_FILE *fp)
-{
-	FRESULT res;
-	if ((res = f_closedir(&fp->pdir->dir)) != FR_OK) {
+int dir_close(struct SHELL_FILE *fp)
+{
+	FRESULT res;
+	if ((res = f_closedir(&((struct SHELL_DIR *)fp->exinf)->dir)) != FR_OK) {
 		return fresult2errno(res);
 	}
@@ -564,21 +610,21 @@
 		return -EINVAL;
 
-	struct _IO_FILE *fp = fd_to_fp(fd);
+	struct SHELL_FILE *fp = fd_to_fp(fd);
 	if (fp == NULL)
 		return -EBADF;
 
 	FILINFO fno;
-#if _USE_LFN
-	static char lfn[_MAX_LFN + 1];   /* Buffer to store the LFN */
+#if FF_USE_LFN
+	static char lfn[FF_MAX_LFN + 1];   /* Buffer to store the LFN */
 	fno.lfname = lfn;
 	fno.lfsize = sizeof lfn;
 #endif
 	FRESULT res;
-	if ((res = f_readdir(&fp->pdir->dir, &fno)) != FR_OK || fno.fname[0] == '\0') {
+	if ((res = f_readdir(&((struct SHELL_DIR *)fp->exinf)->dir, &fno)) != FR_OK || fno.fname[0] == '\0') {
 		return fresult2errno(res);
 	}
 
 	memset(de, 0, sizeof(*de));
-#if _USE_LFN
+#if FF_USE_LFN
 	ntlibc_strlcpy(de->d_name, *fno.lfname ? fno.lfname : fno.fname, sizeof(de->d_name));
 #else
@@ -589,15 +635,15 @@
 }
 
-size_t dir_read(struct _IO_FILE *fp, unsigned char *data, size_t len)
+size_t dir_read(struct SHELL_FILE *fp, unsigned char *data, size_t len)
 {
 	return -EPERM;
 }
 
-size_t dir_write(struct _IO_FILE *fp, const unsigned char *data, size_t len)
+size_t dir_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len)
 {
 	return -EPERM;
 }
 
-off_t dir_seek(struct _IO_FILE *fp, off_t ptr, int dir)
+off_t dir_seek(struct SHELL_FILE *fp, off_t ptr, int dir)
 {
 	FRESULT res;
@@ -607,5 +653,5 @@
 
 	if (ptr == 0) {
-		if ((res = f_rewinddir(&fp->pdir->dir)) != FR_OK) {
+		if ((res = f_rewinddir(&((struct SHELL_DIR *)fp->exinf)->dir)) != FR_OK) {
 			return fresult2errno(res);
 		}
@@ -613,15 +659,15 @@
 	else {
 		FILINFO fno;
-#if _USE_LFN
-		static char lfn[_MAX_LFN + 1];   /* Buffer to store the LFN */
+#if FF_USE_LFN
+		static char lfn[FF_MAX_LFN + 1];   /* Buffer to store the LFN */
 		fno.lfname = lfn;
 		fno.lfsize = sizeof lfn;
 #endif
-		if ((res = f_rewinddir(&fp->pdir->dir)) != FR_OK) {
+		if ((res = f_rewinddir(&((struct SHELL_DIR *)fp->exinf)->dir)) != FR_OK) {
 			return fresult2errno(res);
 		}
 
 		for (int i = 0; i < ptr; i++) {
-			if ((res = f_readdir(&fp->pdir->dir, &fno)) != FR_OK || fno.fname[0] == '\0') {
+			if ((res = f_readdir(&((struct SHELL_DIR *)fp->exinf)->dir, &fno)) != FR_OK || fno.fname[0] == '\0') {
 				return fresult2errno(res);
 			}
@@ -632,7 +678,18 @@
 }
 
-int dir_ioctl(struct _IO_FILE *fp, int req, void *arg)
+int dir_ioctl(struct SHELL_FILE *fp, int req, void *arg)
 {
 	return -EINVAL;
+}
+
+bool_t dir_readable(struct SHELL_FILE *fp)
+{
+	return fp->readevt_w != fp->readevt_r;
+}
+
+void dir_delete(struct SHELL_FILE *fp)
+{
+	free((struct SHELL_DIR *)fp->exinf);
+	fp->exinf = NULL;
 }
 
@@ -687,68 +744,6 @@
 {
 	//if ((addr >= (void *)&__HeapBase) && (addr + len < (void *)&__HeapLimit)) {
-		return 0;
-	//}
-	//return -1;
-}
-
-#include "tlsf.h"
-
-static tlsf_t sys_tlsf;
-static pool_t sys_pool;
-
-void sys_init(void)
-{
-	sys_tlsf = tlsf_create(&__HeapBase);
-	if (sys_tlsf == NULL)
-		return;
-
-	sys_pool = tlsf_add_pool(sys_tlsf, ((uint8_t *)&__HeapBase) + tlsf_size(), ((intptr_t)&__HeapLimit - (intptr_t)&__HeapBase) - tlsf_size());
-}
-
-void sys_fini(void)
-{
-	tlsf_destroy(sys_tlsf);
-}
-
-void *malloc(size_t size)
-{
-	void *result;
-	wai_sem(SEM_MALLOC);
-	result = tlsf_malloc(sys_tlsf, size);
-	sig_sem(SEM_MALLOC);
-	if (result == NULL)
-		tlsf_check_pool(sys_pool);
-	return result;
-}
-
-void *calloc(size_t size, size_t count)
-{
-	void *result;
-	wai_sem(SEM_MALLOC);
-	result = tlsf_malloc(sys_tlsf, count * size);
-	sig_sem(SEM_MALLOC);
-	if (result != NULL)
-		memset(result, 0, count * size);
-	else
-		tlsf_check_pool(sys_pool);
-	return result;
-}
-
-void *realloc(void *ptr, size_t size)
-{
-	void *result;
-	wai_sem(SEM_MALLOC);
-	result = tlsf_realloc(sys_tlsf, ptr, size);
-	sig_sem(SEM_MALLOC);
-	if (result == NULL)
-		tlsf_check_pool(sys_pool);
-	return result;
-}
-
-void free(void *ptr)
-{
-	wai_sem(SEM_MALLOC);
-	tlsf_free(sys_tlsf, ptr);
-	sig_sem(SEM_MALLOC);
-}
-
+	return 0;
+//}
+//return -1;
+}
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/net_misc.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/net_misc.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/net_misc.c	(revision 374)
@@ -60,7 +60,5 @@
 #include "kernel_cfg.h"
 #include "tinet_cfg.h"
-#include "util/ntstdio.h"
-
-extern ntstdio_t ntstdio;
+#include <stdio.h>
 
 T_DHCP4_CLI_CONTEXT *dhcp4_cli_initialize(ID tskid, ID cepid);
@@ -97,5 +95,5 @@
 
 	get_tid(&nc->tskid);
-	ntstdio_printf(&ntstdio, "[NET MISC:%d,%d] started.", nc->tskid, (ID)exinf);
+	printf("[NET MISC:%d,%d] started.", nc->tskid, (ID)exinf);
 
 	/* 初期化 */
@@ -105,5 +103,5 @@
 	ret = get_tim(&time);
 	if (ret != E_OK) {
-		ntstdio_printf(&ntstdio, "[NET MISC,%d] get_tim error: %7lu,%s",
+		printf("[NET MISC,%d] get_tim error: %7lu,%s",
 			nc->cepid, time / SYSTIM_HZ, itron_strerror(ret));
 		return;
@@ -119,5 +117,5 @@
 		error = tslp_tsk(timer);
 		if ((error != E_OK) && (error != E_TMOUT)) {
-			ntstdio_printf(&ntstdio, "[NET MISC,%d] tslp_tsk error: %s %d",
+			printf("[NET MISC,%d] tslp_tsk error: %s %d",
 				nc->cepid, itron_strerror(error), timer);
 			break;
@@ -126,5 +124,5 @@
 		ret = get_tim(&time);
 		if (ret != E_OK) {
-			ntstdio_printf(&ntstdio, "[NET MISC,%d] get_tim error: %s",
+			printf("[NET MISC,%d] get_tim error: %s",
 				nc->cepid, itron_strerror(ret));
 			break;
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/netcmd.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/netcmd.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/netcmd.c	(revision 374)
@@ -59,9 +59,7 @@
 #include <netapp/resolver.h>
 #include "core/ntlibc.h"
-#include "util/ntstdio.h"
+#include <stdio.h>
 #include "ntp_cli.h"
 #include "kernel_cfg.h"
-
-extern ntstdio_t ntstdio;
 
 #if defined(SUPPORT_INET6)
@@ -280,5 +278,5 @@
 
 	if ((line = lookup_ipaddr(&addr, line, apip)) == NULL) {
-		ntstdio_printf(&ntstdio, "[PING] unknown host.\n");
+		printf("[PING] unknown host.\n");
 		return 0;
 	}
@@ -299,18 +297,18 @@
 #if defined(SUPPORT_INET4)
 	if (apip == API_PROTO_IPV6) {
-		ntstdio_printf(&ntstdio, "[PING6] size: %d, tmo: %d, host: %s\n", size, tmo, ipv62str(NULL, &addr));
+		printf("[PING6] size: %d, tmo: %d, host: %s\n", size, tmo, ipv62str(NULL, &addr));
 		ping6(&addr, (uint_t)tmo, (uint_t)size);
 	}
 	else {
 		addr4 = ntohl(addr.s6_addr32[3]);
-		ntstdio_printf(&ntstdio, "[PING4] size: %d, tmo: %d, host: %s\n", size, tmo, ip2str(NULL, &addr4));
+		printf("[PING4] size: %d, tmo: %d, host: %s\n", size, tmo, ip2str(NULL, &addr4));
 		ping4(&addr4, (uint_t)tmo, (uint_t)size);
 	}
 #else /* of #if defined(SUPPORT_INET4) */
-	ntstdio_printf(&ntstdio, "[PING6] size: %d, tmo: %d, host: %s\n", size, tmo, ipv62str(NULL, &addr));
+	printf("[PING6] size: %d, tmo: %d, host: %s\n", size, tmo, ipv62str(NULL, &addr));
 	ping6(&addr, (uint_t)tmo, (uint_t)size);
 #endif	/* of #if defined(SUPPORT_INET4) */
 #else	/* of #if defined(SUPPORT_INET6) */
-	ntstdio_printf(&ntstdio, "[PING4] size: %d, tmo: %d, host: %s\n", size, tmo, ip2str(NULL, &addr));
+	printf("[PING4] size: %d, tmo: %d, host: %s\n", size, tmo, ip2str(NULL, &addr));
 	ping4(&addr, (uint_t)tmo, (uint_t)size);
 #endif	/* of #if defined(SUPPORT_INET6) */
@@ -331,13 +329,13 @@
 		pos = str_ipv4addr(temp, sizeof(temp), &svaddr, 0);
 		temp[pos] = '\0';
-		ntstdio_printf(&ntstdio, "DHCPv4 server: %s,\n", temp);
-		ntstdio_printf(&ntstdio, "  Renew:       %u:%02u:%02u,\n",
+		printf("DHCPv4 server: %s,\n", temp);
+		printf("  Renew:       %u:%02u:%02u,\n",
 			renew / 3600, (renew / 60) % 60, renew % 60);
-		ntstdio_printf(&ntstdio, "  Rebind:      %u:%02u:%02u, Expire:   %u:%02u:%02u.\n",
+		printf("  Rebind:      %u:%02u:%02u, Expire:   %u:%02u:%02u.\n",
 			rebind / 3600, (rebind / 60) % 60, rebind % 60,
 			expire / 3600, (expire / 60) % 60, expire % 60);
 	}
 	else if (ret == E_OBJ)
-		ntstdio_printf(&ntstdio, "DHCPv4 server: not available.\n");
+		printf("DHCPv4 server: not available.\n");
 }
 
@@ -351,9 +349,9 @@
 	if (ntlibc_strcmp(argv[1], "rel") == 0) {
 		ret = dhcp4c_rel_info();
-		ntstdio_printf(&ntstdio, "dhcp4c_rel_info %d\n", ret);
+		printf("dhcp4c_rel_info %d\n", ret);
 	}
 	else if (ntlibc_strcmp(argv[1], "renew") == 0) {
 		ret = dhcp4c_renew_info();
-		ntstdio_printf(&ntstdio, "dhcp4c_renew_info %d\n", ret);
+		printf("dhcp4c_renew_info %d\n", ret);
 	}
 	else {
@@ -383,8 +381,8 @@
 		else {
 			for (c = 1; c <= *ptr; c++)
-				ntstdio_printf(&ntstdio, "%c", *(ptr + c));
+				printf("%c", *(ptr + c));
 			ptr += *ptr + 1;
 			if (*ptr)
-				ntstdio_printf(&ntstdio, ".");
+				printf(".");
 		}
 	}
@@ -406,16 +404,16 @@
 		return error;
 
-	ntstdio_printf(&ntstdio, "    mname:   ");
+	printf("    mname:   ");
 	rn_offset = s_show_dns_domain_name(msg, offset);
-	ntstdio_putc(&ntstdio, '\n');
-	ntstdio_printf(&ntstdio, "    rname:   ");
+	putchar('\n');
+	printf("    rname:   ");
 	s_show_dns_domain_name(msg, rn_offset);
-	ntstdio_putc(&ntstdio, '\n');
-
-	ntstdio_printf(&ntstdio, "    serial:  %d\n", soa.serial);
-	ntstdio_printf(&ntstdio, "    refresh: %d\n", soa.refresh);
-	ntstdio_printf(&ntstdio, "    retry:   %d\n", soa.retry);
-	ntstdio_printf(&ntstdio, "    expirel: %d\n", soa.expire);
-	ntstdio_printf(&ntstdio, "    minimum: %d\n", soa.minimum);
+	putchar('\n');
+
+	printf("    serial:  %d\n", soa.serial);
+	printf("    refresh: %d\n", soa.refresh);
+	printf("    retry:   %d\n", soa.retry);
+	printf("    expirel: %d\n", soa.expire);
+	printf("    minimum: %d\n", soa.minimum);
 
 	return E_OK;
@@ -433,5 +431,5 @@
 	int		scount;
 
-	ntstdio_printf(&ntstdio, "question   section: %d\n", rslv->dns_hdr.qdcount);
+	printf("question   section: %d\n", rslv->dns_hdr.qdcount);
 	offset = rslv->qd_offset;
 	for (scount = 1; scount <= rslv->dns_hdr.qdcount; scount++) {
@@ -439,7 +437,7 @@
 			return error;
 
-		ntstdio_printf(&ntstdio, "%2d: ", scount);
+		printf("%2d: ", scount);
 		s_show_dns_domain_name(msg, offset);
-		ntstdio_printf(&ntstdio, "\n    type: %-4s, class: %2s\n", dns_strtype(qd.type), dns_strclass(qd.class));
+		printf("\n    type: %-4s, class: %2s\n", dns_strtype(qd.type), dns_strclass(qd.class));
 		offset = error;
 	}
@@ -463,12 +461,12 @@
 	int pos;
 
-	ntstdio_printf(&ntstdio, "%10s section: %d\n", title, scount);
+	printf("%10s section: %d\n", title, scount);
 	for (count = 1; count <= scount; count++) {
 		if ((error = dns_analyze_rr(&rr, offset, msg, length)) < 0)
 			return error;
 
-		ntstdio_printf(&ntstdio, "%2d: ", count);
+		printf("%2d: ", count);
 		s_show_dns_domain_name(msg, offset);
-		ntstdio_printf(&ntstdio, "\n    type: %-4s, class: %2s, TTL: %2d, len: %3d, offset: 0x%02x\n",
+		printf("\n    type: %-4s, class: %2s, TTL: %2d, len: %3d, offset: 0x%02x\n",
 			dns_strtype(rr.type), dns_strclass(rr.class), rr.ttl, rr.rdlength, rr.rdata_offset);
 
@@ -479,15 +477,15 @@
 			pos = str_ipv4addr(temp, sizeof(temp), &in4_addr, 0);
 			temp[pos] = '\0';
-			ntstdio_printf(&ntstdio, "    IPv4 addr: %s\n", temp);
+			printf("    IPv4 addr: %s\n", temp);
 			break;
 		case DNS_TYPE_NS:
-			ntstdio_printf(&ntstdio, "    host: ");
+			printf("    host: ");
 			s_show_dns_domain_name(msg, rr.rdata_offset);
-			ntstdio_putc(&ntstdio, '\n');
+			putchar('\n');
 			break;
 		case DNS_TYPE_CNAME:
-			ntstdio_printf(&ntstdio, "    host: ");
+			printf("    host: ");
 			s_show_dns_domain_name(msg, rr.rdata_offset);
-			ntstdio_putc(&ntstdio, '\n');
+			putchar('\n');
 			break;
 		case DNS_TYPE_SOA:
@@ -495,7 +493,7 @@
 			break;
 		case DNS_TYPE_PTR:
-			ntstdio_printf(&ntstdio, "     PTR: ");
+			printf("     PTR: ");
 			s_show_dns_domain_name(msg, rr.rdata_offset);
-			ntstdio_putc(&ntstdio, '\n');
+			putchar('\n');
 			break;
 		case DNS_TYPE_AAAA:
@@ -503,17 +501,17 @@
 			pos = str_ipv6addr(temp, sizeof(temp), &in6_addr, 0);
 			temp[pos] = '\0';
-			ntstdio_printf(&ntstdio, "    IPv6 addr: %s\n", temp);
+			printf("    IPv6 addr: %s\n", temp);
 			break;
 		default:
-			ntstdio_printf(&ntstdio, "    data: ");
+			printf("    data: ");
 			col = 32;
 			for (dcount = 0; dcount < rr.rdlength; dcount++) {
-				ntstdio_printf(&ntstdio, "%02x", *(msg + rr.rdata_offset + dcount));
+				printf("%02x", *(msg + rr.rdata_offset + dcount));
 				if (--col == 0) {
-					ntstdio_printf(&ntstdio, "\n          ");
+					printf("\n          ");
 					col = 32;
 				}
 			}
-			ntstdio_putc(&ntstdio, '\n');
+			putchar('\n');
 			break;
 		}
@@ -539,9 +537,9 @@
 #if defined(SUPPORT_INET6)
 
-	ntstdio_printf(&ntstdio, "domain name:     %s\n", dns_in6_get_dname());
+	printf("domain name:     %s\n", dns_in6_get_dname());
 
 #else	/* of #if defined(SUPPORT_INET6) */
 
-	ntstdio_printf(&ntstdio, "domain name:     %s\n", dns_in4_get_dname());
+	printf("domain name:     %s\n", dns_in4_get_dname());
 
 #endif	/* of #if defined(SUPPORT_INET6) */
@@ -549,11 +547,11 @@
 #if defined(SUPPORT_INET6)
 	dns_in6_get_addr(&in6_addr);
-	ntstdio_printf(&ntstdio, "IPv6 DNS server: ");
+	printf("IPv6 DNS server: ");
 	if (IN6_IS_ADDR_UNSPECIFIED(&in6_addr))
-		ntstdio_printf(&ntstdio, "not available.\n");
+		printf("not available.\n");
 	else {
 		pos = str_ipv6addr(temp, sizeof(temp), &in6_addr, 0);
 		temp[pos] = '\0';
-		ntstdio_printf(&ntstdio, "%s.\n", temp);
+		printf("%s.\n", temp);
 	}
 #endif	/* of #if defined(SUPPORT_INET6) */
@@ -561,11 +559,11 @@
 #if defined(SUPPORT_INET4)
 	dns_in4_get_addr(&in4_addr);
-	ntstdio_printf(&ntstdio, "IPv4 DNS server: ");
+	printf("IPv4 DNS server: ");
 	if (in4_addr == IPV4_ADDRANY)
-		ntstdio_printf(&ntstdio, "not available.\n");
+		printf("not available.\n");
 	else {
 		pos = str_ipv4addr(temp, sizeof(temp), &in4_addr, 0);
 		temp[pos] = '\0';
-		ntstdio_printf(&ntstdio, "%s.\n", temp);
+		printf("%s.\n", temp);
 	}
 #endif	/* of #if defined(SUPPORT_INET4) */
@@ -604,5 +602,5 @@
 	line = skip_blanks(resolv_options(&flags, line, DEFAULT_API_PROTO));
 	if ((flags & (DNS_LUP_FLAGS_PROTO_IPV6 | DNS_LUP_FLAGS_PROTO_IPV4)) == 0) {
-		ntstdio_printf(&ntstdio, "DNS server not available.\n");
+		printf("DNS server not available.\n");
 		return 0;
 	}
@@ -620,47 +618,47 @@
 
 	if ((error = tget_mpf(MPF_RSLV_SRBUF, (void*)&msg, TMO_FEVR)) != E_OK) {
-		ntstdio_printf(&ntstdio, "get buffer error: %s.\n", itron_strerror(error));
+		printf("get buffer error: %s.\n", itron_strerror(error));
 		return 0;
 	}
 
 	if ((length = dns_lookup_host(flags | DNS_LUP_FLAGS_MSG, line, msg, DNS_UDP_MSG_LENGTH, &rslv)) < 0) {
-		//ntstdio_printf(&ntstdio, "error: %s.\n", itron_strerror(length));
+		//printf("error: %s.\n", itron_strerror(length));
 		goto err_ret;
 	}
 
 	dly_tsk(1 * 1000);
-	ntstdio_printf(&ntstdio, "DNS header: flags: ");
+	printf("DNS header: flags: ");
 	if (rslv.dns_hdr.code & (DNS_QR_RESPONSE | DNS_AUTHORITATIVE |
 		DNS_TRUN_CATION | DNS_RECURSION_DESIRED | DNS_RECURSION_AVAILABLE)) {
-		ntstdio_printf(&ntstdio, (rslv.dns_hdr.code & DNS_QR_RESPONSE) ? "QR," : "");
-		ntstdio_printf(&ntstdio, (rslv.dns_hdr.code & DNS_AUTHORITATIVE) ? "AA," : "");
-		ntstdio_printf(&ntstdio, (rslv.dns_hdr.code & DNS_TRUN_CATION) ? "TC," : "");
-		ntstdio_printf(&ntstdio, (rslv.dns_hdr.code & DNS_RECURSION_DESIRED) ? "RD," : "");
-		ntstdio_printf(&ntstdio, (rslv.dns_hdr.code & DNS_RECURSION_AVAILABLE) ? "RA," : "");
-		ntstdio_printf(&ntstdio, " ");
-	}
-	ntstdio_printf(&ntstdio, "opcode: ");
-	ntstdio_printf(&ntstdio, (rslv.dns_hdr.code & DNS_OPCODE_REVERSE) ? "RV" : "FW");
-	ntstdio_printf(&ntstdio, (rslv.dns_hdr.code & DNS_OPCODE_STATUS) ? ",ST" : "");
-	ntstdio_printf(&ntstdio, ", rcode: %s.\n",
+		printf((rslv.dns_hdr.code & DNS_QR_RESPONSE) ? "QR," : "");
+		printf((rslv.dns_hdr.code & DNS_AUTHORITATIVE) ? "AA," : "");
+		printf((rslv.dns_hdr.code & DNS_TRUN_CATION) ? "TC," : "");
+		printf((rslv.dns_hdr.code & DNS_RECURSION_DESIRED) ? "RD," : "");
+		printf((rslv.dns_hdr.code & DNS_RECURSION_AVAILABLE) ? "RA," : "");
+		printf(" ");
+	}
+	printf("opcode: ");
+	printf((rslv.dns_hdr.code & DNS_OPCODE_REVERSE) ? "RV" : "FW");
+	printf((rslv.dns_hdr.code & DNS_OPCODE_STATUS) ? ",ST" : "");
+	printf(", rcode: %s.\n",
 		(rslv.dns_hdr.code & DNS_RCODE_MASK) > DNS_RCODE_REFUSED
 		? "6" : rcode_str[rslv.dns_hdr.code & DNS_RCODE_MASK]);
 
 	if ((offset = show_dns_qdsection(msg, length, &rslv)) < 0) {
-		ntstdio_printf(&ntstdio, "msg error: %s.\n", itron_strerror(offset));
+		printf("msg error: %s.\n", itron_strerror(offset));
 	}
 	if ((offset = show_dns_section(msg, length, rslv.dns_hdr.ancount, rslv.an_offset, "answer")) < 0) {
-		ntstdio_printf(&ntstdio, "msg error: %s.\n", itron_strerror(offset));
+		printf("msg error: %s.\n", itron_strerror(offset));
 	}
 	if ((offset = show_dns_section(msg, length, rslv.dns_hdr.nscount, rslv.ns_offset, "authority")) < 0) {
-		ntstdio_printf(&ntstdio, "msg error: %s.\n", itron_strerror(offset));
+		printf("msg error: %s.\n", itron_strerror(offset));
 	}
 	if ((offset = show_dns_section(msg, length, rslv.dns_hdr.arcount, rslv.ar_offset, "additional")) < 0) {
-		ntstdio_printf(&ntstdio, "msg error: %s.\n", itron_strerror(offset));
+		printf("msg error: %s.\n", itron_strerror(offset));
 	}
 
 err_ret:
 	if ((error = rel_mpf(MPF_RSLV_SRBUF, msg)) != E_OK)
-		ntstdio_printf(&ntstdio, "release buffer error: %s.\n", itron_strerror(error));
+		printf("release buffer error: %s.\n", itron_strerror(error));
 	return 0;
 }
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/ntp_cli.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/ntp_cli.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/ntp_cli.c	(revision 374)
@@ -50,7 +50,5 @@
 #include <t_syslog.h>
 #include "kernel_cfg.h"
-#include "util/ntstdio.h"
-
-extern ntstdio_t ntstdio;
+#include <stdio.h>
 
 #endif	/* of #if defined(TARGET_KERNEL_ASP) */
@@ -279,5 +277,5 @@
 	}
 
-	ntstdio_printf(&ntstdio, "[NTP CLI,%d] recv time: %s .%09u\n",
+	printf("[NTP CLI,%d] recv time: %s .%09u\n",
 		nc->cepid, nc->buf, tp.tv_nsec);
 }
@@ -311,5 +309,5 @@
 		line = lookup_ipaddr(&nc->ipaddr6, NTP_SRV_URL, API_PROTO_IPV4);
 		if (line == NULL || !in6_is_addr_ipv4mapped(&nc->ipaddr6)) {
-			ntstdio_printf(&ntstdio, "[NTP CLI,%d] sleep %d.%03u[s], unknown host.",
+			printf("[NTP CLI,%d] sleep %d.%03u[s], unknown host.",
 				nc->cepid, SLP_ITV / SYSTIM_HZ, SLP_ITV % SYSTIM_HZ);
 			nc->timer = SLP_ITV;
@@ -319,5 +317,5 @@
 #else	/* of #if defined(SUPPORT_INET6) && defined(SUPPORT_INET4) */
 		if ((line = lookup_ipaddr(&nc->snd_rmt.ipaddr, NTP_SRV_URL, DEFAULT_API_PROTO)) == NULL) {
-			ntstdio_printf(&ntstdio, "[NTP CLI,%d] sleep %d.%03u[s], unknown host.",
+			printf("[NTP CLI,%d] sleep %d.%03u[s], unknown host.",
 				nc->cepid, SLP_ITV / SYSTIM_HZ, SLP_ITV % SYSTIM_HZ);
 			nc->timer = SLP_ITV;
@@ -423,5 +421,5 @@
 
 	if ((error = udp_snd_dat(nc->cepid, &nc->snd_rmt, ntp, len, TMO_NBLK)) != E_WBLK) {
-		ntstdio_printf(&ntstdio, "[NTP CLI,%d] udp_snd_dat error: %s",
+		printf("[NTP CLI,%d] udp_snd_dat error: %s",
 			nc->cepid, itron_strerror(error));
 		return error;
@@ -441,5 +439,5 @@
 	ret = get_tim(&time);
 	if (ret != E_OK) {
-		ntstdio_printf(&ntstdio, "[NTP CLI,%d] get_tim error: %s",
+		printf("[NTP CLI,%d] get_tim error: %s",
 			nc->cepid, itron_strerror(ret));
 		tp->tv_sec = 0;
@@ -461,5 +459,5 @@
 	ret = set_tim(time);
 	if (ret != E_OK) {
-		ntstdio_printf(&ntstdio, "[NTP CLI,%d] set_tim error: %s",
+		printf("[NTP CLI,%d] set_tim error: %s",
 			nc->cepid, itron_strerror(ret));
 	}
@@ -479,5 +477,5 @@
 	if (len < 0 && len != E_RLWAI) {
 		/* E_RLWAI 以外で、0 以下の場合は、エラーを意味している。*/
-		ntstdio_printf(&ntstdio, "[NTP CLI,%d] callback error: %s, fncd: %s", nc->cepid,
+		printf("[NTP CLI,%d] callback error: %s, fncd: %s", nc->cepid,
 			itron_strerror(len), in_strtfn(fncd));
 	}
@@ -486,5 +484,5 @@
 			if ((len = udp_rcv_dat(nc->cepid, &nc->rcv_rmt, &nc->ntp_msg, len, TMO_POL)) < 0)
 			{
-				ntstdio_printf(&ntstdio, "[NTP CLI,%d] udp_rcv_dat error: %s", nc->cepid,
+				printf("[NTP CLI,%d] udp_rcv_dat error: %s", nc->cepid,
 					itron_strerror(len));
 			}
@@ -518,5 +516,5 @@
 
 	get_tid(&nc->tskid);
-	ntstdio_printf(&ntstdio, "[NTP CLI:%d,%d] started.", nc->tskid, (ID)exinf);
+	printf("[NTP CLI:%d,%d] started.", nc->tskid, (ID)exinf);
 
 	/* 初期化 */
@@ -525,5 +523,5 @@
 	ret = get_tim(&time);
 	if (ret != E_OK) {
-		ntstdio_printf(&ntstdio, "[NTP CLI,%d] get_tim error: %7lu,%s",
+		printf("[NTP CLI,%d] get_tim error: %7lu,%s",
 			nc->cepid, time / SYSTIM_HZ, itron_strerror(ret));
 		return;
@@ -539,5 +537,5 @@
 		error = tslp_tsk(timer);
 		if ((error != E_OK) && (error != E_TMOUT)) {
-			ntstdio_printf(&ntstdio, "[NTP CLI,%d] tslp_tsk error: %s %d",
+			printf("[NTP CLI,%d] tslp_tsk error: %s %d",
 				nc->cepid, itron_strerror(error), timer);
 			break;
@@ -546,5 +544,5 @@
 		ret = get_tim(&time);
 		if (ret != E_OK) {
-			ntstdio_printf(&ntstdio, "[NTP CLI,%d] get_tim error: %s",
+			printf("[NTP CLI,%d] get_tim error: %s",
 				nc->cepid, itron_strerror(ret));
 			break;
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.c	(revision 374)
@@ -59,10 +59,6 @@
 #include "ntshell_main.h"
 #include "socket_stub.h"
-#include "usb_hbth.h"
-
-extern int bt_bnep_mode;
 
 char command[NTOPT_TEXT_MAXLEN];
-ntstdio_t ntstdio;
 
 extern uint8_t mac_addr[6];
@@ -87,33 +83,8 @@
 volatile int ntshell_state;
 jmp_buf process_exit;
-void sys_init(void);
-NTSHELL_SERIAL_READ ntshell_serial_read = 0;
-NTSHELL_SERIAL_WRITE ntshell_serial_write = 0;
-void *ntshell_serial_extobj;
-
-unsigned char ntstdio_xi(struct ntstdio_t *handle)
-{
-	unsigned char buf[1];
-	ntshell_serial_read((char *)buf, 1, ntshell_serial_extobj);
-	return buf[0];
-}
-
-void ntstdio_xo(struct ntstdio_t *handle, unsigned char c)
-{
-	char buf[1];
-	buf[0] = c;
-	ntshell_serial_write(buf, 1, ntshell_serial_extobj);
-}
-
-void ntshell_task_init(NTSHELL_SERIAL_READ func_read,
-	NTSHELL_SERIAL_WRITE func_write, void *extobj)
-{
-	ntshell_serial_read = func_read;
-	ntshell_serial_write = func_write;
-	ntshell_serial_extobj = extobj;
-
-	sys_init();
-
-	ntstdio_init(&ntstdio, NTSTDIO_OPTION_LINE_ECHO | NTSTDIO_OPTION_CANON | NTSTDIO_OPTION_LF_CRLF | NTSTDIO_OPTION_LF_CR, ntstdio_xi, ntstdio_xo);
+
+void ntshell_task_init(ID portid)
+{
+	serial_ctl_por(portid, IOCTL_CRLF | IOCTL_FCSND | IOCTL_FCRCV);
 }
 
@@ -177,8 +148,7 @@
 	const cmd_table_t *p = cmd_table_info.table;
 	for (int i = 0; i < cmd_table_info.count; i++) {
-		ntstdio_puts(&ntstdio, p->cmd);
-		ntstdio_puts(&ntstdio, "\t:");
-		ntstdio_puts(&ntstdio, p->desc);
-		ntstdio_puts(&ntstdio, "\n");
+		fwrite(p->cmd, strlen(p->cmd), 1, stdout);
+		fwrite("\t:", strlen("\t:"), 1, stdout);
+		puts(p->desc);
 		p++;
 	}
@@ -206,4 +176,5 @@
 int execute_command(int wait)
 {
+	T_RTSK rtsk;
 	ER ret;
 
@@ -228,4 +199,8 @@
 	do {
 		tslp_tsk(100000);
+
+		ret = ref_tsk(NTSHELL_TASK, &rtsk);
+		if ((ret != E_OK) || (rtsk.tskstat == TTS_DMT))
+			ntshell_state = 3;
 	} while(ntshell_state == 1);
 
@@ -237,83 +212,4 @@
 	ntlibc_strlcpy(command, text, sizeof(command));
 	return execute_command(1);
-}
-
-int stdio_close(struct _IO_FILE *fp)
-{
-	return -EPERM;
-}
-
-size_t stdio_read(struct _IO_FILE *fp, unsigned char *data, size_t len)
-{
-	return -EPERM;
-}
-
-size_t stdio_write(struct _IO_FILE *fp, const unsigned char *data, size_t len)
-{
-	return -EPERM;
-}
-
-size_t stdin_read(struct _IO_FILE *fp, unsigned char *data, size_t len)
-{
-	int i = 0;
-	while (i < len) {
-		int c = ntstdio_getc(&ntstdio);
-		data[i++] = c;
-		if ((c == EOF) || (c == '\n'))
-			break;
-	}
-	return i;
-}
-
-size_t stdout_write(struct _IO_FILE *fp, const unsigned char *data, size_t len)
-{
-	for (int i = 0; i < len; i++) {
-		ntstdio_putc(&ntstdio, data[i]);
-	}
-	return len;
-}
-
-size_t stderr_write(struct _IO_FILE *fp, const unsigned char *data, size_t len)
-{
-	for (int i = 0; i < len; i++) {
-		ntstdio_putc(&ntstdio, data[i]);
-	}
-	return len;
-}
-
-int sio_close(struct _IO_FILE *fp)
-{
-	return -EPERM;
-}
-
-size_t sio_read(struct _IO_FILE *fp, unsigned char *data, size_t len)
-{
-	return -EPERM;
-}
-
-size_t sio_write(struct _IO_FILE *fp, const unsigned char *data, size_t len)
-{
-	return -EPERM;
-}
-
-off_t sio_seek(struct _IO_FILE *fp, off_t ofs, int org)
-{
-	return -EPERM;
-}
-
-int sio_ioctl(struct _IO_FILE *fp, int request, void *arg)
-{
-	switch (request) {
-	case TIOCGWINSZ:
-		return 0;
-	case TCGETS:
-		return sio_tcgetattr(fp->fd, (struct termios *)arg);
-	case TCSETS + TCSANOW:
-	case TCSETS + TCSADRAIN:
-	case TCSETS + TCSAFLUSH:
-		return sio_tcsetattr(fp->fd, request - TCSETS, (const struct termios *)arg);
-	}
-
-	return -EINVAL;
 }
 
@@ -456,2 +352,18 @@
 }
 
+int shell_kill(int pid, int sig)
+{
+	DebugBreak();
+	return -1;
+}
+
+int shell_gettimeofday(struct timeval *tv, void *tzvp)
+{
+	SYSTIM time;
+	if (!tv) return 0;
+	get_tim(&time);
+	tv->tv_sec = time / 1000000;
+	tv->tv_usec = time - (tv->tv_sec * 1000000);
+	return 0;
+}
+
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.cfg
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.cfg	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.cfg	(revision 374)
@@ -41,6 +41,7 @@
 #include "ntshell_main.h"
 
-CRE_TSK(NTSHELL_TASK, { TA_NULL, 0, ntshell_task, NTSHELL_PRIORITY, NTSHELL_STACK_SIZE, NULL });
+ATT_INI({ TA_NULL, 0, sys_init });
+
+CRE_TSK(NTSHELL_TASK, { TA_FPU, 0, ntshell_task, NTSHELL_PRIORITY, NTSHELL_STACK_SIZE, NULL });
 CRE_FLG(FLG_SELECT_WAIT, { TA_WMUL, 0x00 });
 CRE_SEM(SEM_FILEDESC, { TA_TPRI, 1, 1 });
-CRE_SEM(SEM_MALLOC, { TA_TPRI, 1, 1 });
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/ntshell_main.h	(revision 374)
@@ -76,7 +76,9 @@
 extern PRI main_task_priority;
 
+/* ntshellの初期化 */
+void sys_init(intptr_t exinf);
+
 /* ntshellタスク初期化 */
-void ntshell_task_init(NTSHELL_SERIAL_READ func_read,
-	NTSHELL_SERIAL_WRITE func_write, void *extobj);
+void ntshell_task_init(ID portid);
 
 /* ntshellタスク */
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/shellif.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/shellif.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/shellif.h	(revision 374)
@@ -134,5 +134,5 @@
 
 // dirent.h
-typedef struct __dirstream DIR;
+typedef struct __dirstream FATFS_DIR;
 
 int shell_getdents(int, struct dirent *, size_t);
@@ -303,5 +303,4 @@
 #endif
 
-struct tm *gmtime_r(const time_t *t, struct tm *tm);
 void *malloc(size_t size);
 void *calloc(size_t size, size_t count);
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/socket_stub.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/socket_stub.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/socket_stub.c	(revision 374)
@@ -57,5 +57,8 @@
 #include <netinet/udp_var.h>
 #include <net/net_buf.h>
-//#include <netinet/tcp_var.h>
+#include <netinet/udp.h>
+#include <netinet/udp_var.h>
+#include <netinet/tcp.h>
+#include <netinet/tcp_var.h>
 #include <netapp/resolver.h>
 extern const ID tmax_tcp_cepid;
@@ -64,5 +67,28 @@
 #include "kernel_cfg.h"
 
+#ifdef _DEBUG
+static const char THIS_FILE[] = __FILE__;
+#endif
+
 #define SOCKET_TIMEOUT 2000000
+
+static int tcp_fd_close(struct SHELL_FILE *fp);
+static size_t tcp_fd_read(struct SHELL_FILE *fp, unsigned char *data, size_t len);
+static size_t tcp_fd_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static off_t tcp_fd_seek(struct SHELL_FILE *fp, off_t ofs, int org);
+static int tcp_fd_ioctl(struct SHELL_FILE *fp, int req, void *arg);
+static bool_t tcp_fd_readable(struct SHELL_FILE *fp);
+static void tcp_fd_delete(struct SHELL_FILE *fp);
+
+static int udp_fd_close(struct SHELL_FILE *fp);
+static size_t udp_fd_read(struct SHELL_FILE *fp, unsigned char *data, size_t len);
+static size_t udp_fd_write(struct SHELL_FILE *fp, const unsigned char *data, size_t len);
+static off_t udp_fd_seek(struct SHELL_FILE *fp, off_t ofs, int org);
+static int udp_fd_ioctl(struct SHELL_FILE *fp, int req, void *arg);
+static bool_t udp_fd_readable(struct SHELL_FILE *fp);
+static void udp_fd_delete(struct SHELL_FILE *fp);
+
+IO_TYPE IO_TYPE_TCP = { tcp_fd_close, tcp_fd_read, tcp_fd_write, tcp_fd_seek, tcp_fd_ioctl, tcp_fd_readable, tcp_fd_delete };
+IO_TYPE IO_TYPE_UDP = { udp_fd_close, udp_fd_read, udp_fd_write, udp_fd_seek, udp_fd_ioctl, udp_fd_readable, udp_fd_delete };
 
 typedef struct id_table_t {
@@ -116,10 +142,5 @@
 }
 
-int delete_tcp_rep(int repid)
-{
-	return delete_tcp_fd(tmax_tcp_cepid + repid);
-}
-
-typedef struct _IO_FILE SOCKET;
+typedef struct SHELL_FILE SOCKET;
 
 int shell_socket(int family, int type, int protocol)
@@ -141,8 +162,18 @@
 	switch (type) {
 	case SOCK_STREAM:
-		fp = new_tcp_fd(0);
+		fp = new_fp(&IO_TYPE_TCP, 0, 0);
+		if (fp == NULL)
+			return -ENOMEM;
+
+		fp->exinf = malloc(sizeof(socket_t));
+		memset(fp->exinf, 0, sizeof(socket_t));
 		break;
 	case SOCK_DGRAM:
-		fp = new_udp_fd(0);
+		fp = new_fp(&IO_TYPE_UDP, 0, 1);
+		if (fp == NULL)
+			return -ENOMEM;
+
+		fp->exinf = malloc(sizeof(socket_t));
+		memset(fp->exinf, 0, sizeof(socket_t));
 		break;
 	default:
@@ -150,12 +181,9 @@
 	}
 
-	if (fp == NULL) {
-		return -ENOMEM;
-	}
-
-	fp->psock->family = family;
-	fp->psock->type = type;
-	fp->psock->protocol = protocol;
-	fp->psock->flags = flags;
+	socket_t *socket = (socket_t *)fp->exinf;
+	socket->family = family;
+	socket->type = type;
+	socket->protocol = protocol;
+	socket->flags = flags;
 
 	return fp->fd;
@@ -167,5 +195,6 @@
 	if (fp == NULL)
 		return -EBADF;
-	if (fp->psock->family != addr->sa_family)
+	socket_t *socket = (socket_t *)fp->exinf;
+	if (socket->family != addr->sa_family)
 		return -EINVAL;
 
@@ -177,6 +206,6 @@
 		}
 		struct sockaddr_in *addr_in = (struct sockaddr_in *)addr;
-		memcpy(&fp->psock->laddr4, addr, len);
-		switch (fp->psock->type) {
+		memcpy(&socket->laddr4, addr, len);
+		switch (socket->type) {
 		case SOCK_STREAM: {
 			ID cepid = new_id(tcp_cepid_table, tcp_cepid_table_count);
@@ -184,10 +213,10 @@
 				return -ENOMEM;
 
-			fp->psock->buf_size = 512 + 512;
-			fp->psock->buf = malloc(fp->psock->buf_size);
+			socket->buf_size = 512 + 512;
+			socket->buf = malloc(socket->buf_size);
 #ifdef _DEBUG
-			memset(fp->psock->buf, 0, fp->psock->buf_size);
+			memset(socket->buf, 0, socket->buf_size);
 #endif
-			T_TCP_CCEP ccep = { 0, fp->psock->buf, 512, &fp->psock->buf[512], 512, (FP)socket_tcp_callback };
+			T_TCP_CCEP ccep = { 0, socket->buf, 512, &socket->buf[512], 512, (FP)socket_tcp_callback };
 			ret = tcp_cre_cep(cepid, &ccep);
 			if (ret != E_OK) {
@@ -196,5 +225,5 @@
 			}
 			fp->handle = cepid;
-			fp->psock->cepid = cepid;
+			socket->cepid = cepid;
 			break;
 		}
@@ -211,5 +240,5 @@
 			}
 			fp->handle = cepid;
-			fp->psock->cepid = cepid;
+			socket->cepid = cepid;
 			break;
 		}
@@ -223,5 +252,5 @@
 			return -EINVAL;
 		}
-		memcpy(&fp->psock->laddr4, addr, len);
+		memcpy(&socket->laddr4, addr, len);
 		break;
 	}
@@ -236,11 +265,12 @@
 	if (fp == NULL)
 		return -EBADF;
-	if (fp->psock->type != SOCK_STREAM)
+	socket_t *socket = (socket_t *)fp->exinf;
+	if (socket->type != SOCK_STREAM)
 		return -EINVAL;
 
-	fp->psock->backlog = backlog;
+	socket->backlog = backlog;
 
 	ER ret;
-	switch (fp->psock->family) {
+	switch (socket->family) {
 	case AF_INET: {
 		ID repid = new_id(tcp_repid_table, tcp_repid_table_count);
@@ -248,5 +278,5 @@
 			return -ENOMEM;
 
-		struct sockaddr_in *laddr = &fp->psock->laddr4;
+		struct sockaddr_in *laddr = &socket->laddr4;
 		T_TCP_CREP crep = { 0, {ntohl(laddr->sin_addr.s_addr), ntohs(laddr->sin_port)} };
 		ret = tcp_cre_rep(repid, &crep);
@@ -255,5 +285,5 @@
 			return -ENOMEM;
 		}
-		fp->psock->repid = repid;
+		socket->repid = repid;
 		break;
 	}
@@ -271,24 +301,25 @@
 	if (fp == NULL)
 		return -EBADF;
-	if (fp->psock->type != SOCK_STREAM)
+	socket_t *socket = (socket_t *)fp->exinf;
+	if (socket->type != SOCK_STREAM)
 		return -EINVAL;
 
 	ER ret;
-	switch (fp->psock->family) {
+	switch (socket->family) {
 	case AF_INET: {
 		if (len < 8) {
 			return -EINVAL;
 		}
-		if (fp->psock->cepid == 0) {
+		if (socket->cepid == 0) {
 			ID cepid = new_id(tcp_cepid_table, tcp_cepid_table_count);
 			if (cepid < 0)
 				return -ENOMEM;
 
-			fp->psock->buf_size = 512 + 512;
-			fp->psock->buf = malloc(fp->psock->buf_size);
+			socket->buf_size = 512 + 512;
+			socket->buf = malloc(socket->buf_size);
 #ifdef _DEBUG
-			memset(fp->psock->buf, 0, fp->psock->buf_size);
+			memset(socket->buf, 0, socket->buf_size);
 #endif
-			T_TCP_CCEP ccep = { 0, fp->psock->buf, 512, &fp->psock->buf[512], 512, (FP)socket_tcp_callback };
+			T_TCP_CCEP ccep = { 0, socket->buf, 512, &socket->buf[512], 512, (FP)socket_tcp_callback };
 			ret = tcp_cre_cep(cepid, &ccep);
 			if (ret != E_OK) {
@@ -297,13 +328,13 @@
 			}
 			fp->handle = cepid;
-			fp->psock->cepid = cepid;
-		}
-		struct sockaddr_in *laddr = &fp->psock->laddr4;
-		struct sockaddr_in *raddr = &fp->psock->raddr4;
+			socket->cepid = cepid;
+		}
+		struct sockaddr_in *laddr = &socket->laddr4;
+		struct sockaddr_in *raddr = &socket->raddr4;
 		memset(raddr, 0, sizeof(*raddr));
 		memcpy(raddr, addr, len);
 		T_IPV4EP lep = { ntohl(laddr->sin_addr.s_addr), ntohs(laddr->sin_port) };
 		T_IPV4EP rep = { ntohl(raddr->sin_addr.s_addr), ntohs(raddr->sin_port) };
-		ret = tcp_con_cep(fp->psock->cepid, &lep, &rep, SOCKET_TIMEOUT);
+		ret = tcp_con_cep(socket->cepid, &lep, &rep, SOCKET_TIMEOUT);
 		if (ret < 0) {
 			return -EHOSTUNREACH;
@@ -324,29 +355,32 @@
 	if (lfp == NULL)
 		return -EBADF;
-	if (lfp->psock->type != SOCK_STREAM)
+	if (((socket_t *)lfp->exinf)->type != SOCK_STREAM)
 		return -EINVAL;
 
-	SOCKET *fp = new_tcp_fd(0);
-	if (fp == NULL) {
+	SOCKET *fp = new_fp(&IO_TYPE_TCP, 0, 0);
+	if (fp == NULL)
 		return -ENOMEM;
-	}
-
-	memcpy(fp->psock, lfp->psock, offsetof(socket_t, buf_size));
+
+	fp->exinf = malloc(sizeof(socket_t));
+	memset(fp->exinf, 0, sizeof(socket_t));
+
+	memcpy(fp->exinf, lfp->exinf, offsetof(socket_t, buf_size));
 
 	ER ret;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
 		ID cepid;
-		if (fp->psock->cepid == 0) {
+		if (socket->cepid == 0) {
 			cepid = new_id(tcp_cepid_table, tcp_cepid_table_count);
 			if (cepid < 0)
 				return -ENOMEM;
 
-			fp->psock->buf_size = 512 + 512;
-			fp->psock->buf = malloc(fp->psock->buf_size);
+			socket->buf_size = 512 + 512;
+			socket->buf = malloc(socket->buf_size);
 #ifdef _DEBUG
-			memset(fp->psock->buf, 0, fp->psock->buf_size);
+			memset(socket->buf, 0, socket->buf_size);
 #endif
-			T_TCP_CCEP ccep = { 0, fp->psock->buf, 512, &fp->psock->buf[512], 512, (FP)socket_tcp_callback };
+			T_TCP_CCEP ccep = { 0, socket->buf, 512, &socket->buf[512], 512, (FP)socket_tcp_callback };
 			ret = tcp_cre_cep(cepid, &ccep);
 			if (ret != E_OK) {
@@ -355,20 +389,20 @@
 			}
 			fp->handle = cepid;
-			fp->psock->cepid = cepid;
+			socket->cepid = cepid;
 		}
 		else {
-			cepid = lfp->psock->cepid;
+			cepid = ((socket_t *)lfp->exinf)->cepid;
 			fp->handle = cepid;
-			lfp->handle = tmax_tcp_cepid + lfp->psock->repid;
-			lfp->psock->cepid = 0;
-			lfp->psock->buf_size = 0;
-			lfp->psock->buf = 0;
+			lfp->handle = tmax_tcp_cepid + ((socket_t *)lfp->exinf)->repid;
+			((socket_t *)lfp->exinf)->cepid = 0;
+			((socket_t *)lfp->exinf)->buf_size = 0;
+			((socket_t *)lfp->exinf)->buf = 0;
 		}
 		T_IPV4EP rep = { 0, 0 };
-		ret = tcp_acp_cep(fp->psock->cepid, fp->psock->repid, &rep, TMO_FEVR);
+		ret = tcp_acp_cep(socket->cepid, socket->repid, &rep, TMO_FEVR);
 		if (ret < 0) {
 			return -ENOMEM;
 		}
-		struct sockaddr_in *raddr = &fp->psock->raddr4;
+		struct sockaddr_in *raddr = &socket->raddr4;
 		memset(raddr, 0, sizeof(*raddr));
 		raddr->sin_family = AF_INET;
@@ -387,5 +421,5 @@
 			return -EINVAL;
 		}
-		struct sockaddr_in *raddr = &fp->psock->raddr4;
+		struct sockaddr_in *raddr = &socket->raddr4;
 		if (sz > sizeof(*raddr))
 			sz = sizeof(*raddr);
@@ -405,7 +439,8 @@
 
 	int ret = 0;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		switch (fp->psock->type) {
+		switch (socket->type) {
 		case SOCK_STREAM: {
 			if ((addr != NULL) || (alen != 0)) {
@@ -414,5 +449,5 @@
 
 			if (flags & MSG_OOB) {
-				ret = tcp_snd_oob(fp->psock->cepid, (void *)buf, len, SOCKET_TIMEOUT);
+				ret = tcp_snd_oob(socket->cepid, (void *)buf, len, SOCKET_TIMEOUT);
 				if (ret < 0) {
 					return -ECOMM;
@@ -421,5 +456,5 @@
 			else {
 				for (;;) {
-					ret = tcp_snd_dat(fp->psock->cepid, (void *)buf, len, SOCKET_TIMEOUT);
+					ret = tcp_snd_dat(socket->cepid, (void *)buf, len, SOCKET_TIMEOUT);
 					if (ret < 0) {
 						if (ret == E_TMOUT)
@@ -440,10 +475,10 @@
 				return -EINVAL;
 			}
-			struct sockaddr_in *raddr = &fp->psock->raddr4;
+			struct sockaddr_in *raddr = &socket->raddr4;
 			memset(raddr, 0, sizeof(*raddr));
 			memcpy(raddr, addr, sz);
 			T_IPV4EP rep = { ntohl(raddr->sin_addr.s_addr), ntohs(raddr->sin_port) };
-			ret = udp_snd_dat(fp->psock->cepid, &rep, (void *)buf, len,
-				(fp->psock->flags & O_NONBLOCK) ? TMO_POL : SOCKET_TIMEOUT);
+			ret = udp_snd_dat(socket->cepid, &rep, (void *)buf, len,
+				(socket->flags & O_NONBLOCK) ? TMO_POL : SOCKET_TIMEOUT);
 			if (ret < 0) {
 				return (ret == E_TMOUT) ? -ETIME : -ECOMM;
@@ -476,10 +511,11 @@
 
 	int ret = 0;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		switch (fp->psock->type) {
+		switch (socket->type) {
 		case SOCK_STREAM: {
 			if (flags & MSG_OOB) {
-				ret = tcp_rcv_oob(fp->psock->cepid, buf, len);
+				ret = tcp_rcv_oob(socket->cepid, buf, len);
 				if (ret < 0) {
 					syslog(LOG_ERROR, "tcp_rcv_oob => %d", ret);
@@ -489,15 +525,15 @@
 			else {
 				int rsz, tmp;
-				if (fp->psock->input == NULL) {
+				if (socket->input == NULL) {
 					ret = wai_sem(SEM_FILEDESC);
 					if (ret < 0) {
 						syslog(LOG_ERROR, "wai_sem => %d", ret);
 					}
-					fp->psock->len = 0;
+					socket->len = 0;
 					ret = sig_sem(SEM_FILEDESC);
 					if (ret < 0) {
 						syslog(LOG_ERROR, "sig_sem => %d", ret);
 					}
-					ret = tcp_rcv_buf(fp->psock->cepid, &fp->psock->input, TMO_FEVR);
+					ret = tcp_rcv_buf(socket->cepid, &socket->input, TMO_FEVR);
 					if (ret < 0) {
 						syslog(LOG_ERROR, "tcp_rcv_buf => %d", ret);
@@ -507,15 +543,15 @@
 				}
 				else
-					rsz = fp->psock->len;
+					rsz = socket->len;
 				tmp = rsz;
 				if (rsz > len)
 					rsz = len;
 				if (rsz >= 0) {
-					memcpy(buf, fp->psock->input, rsz);
+					memcpy(buf, socket->input, rsz);
 					ret = wai_sem(SEM_FILEDESC);
 					if (ret < 0) {
 						syslog(LOG_ERROR, "wai_sem => %d", ret);
 					}
-					fp->psock->len = tmp - rsz;
+					socket->len = tmp - rsz;
 					ret = sig_sem(SEM_FILEDESC);
 					if (ret < 0) {
@@ -523,9 +559,9 @@
 					}
 					if (tmp - rsz == 0) {
-						fp->psock->input = NULL;
+						socket->input = NULL;
 					}
 					else
-						fp->psock->input = (void *)&((uint8_t *)fp->psock->input)[rsz];
-					ret = tcp_rel_buf(fp->psock->cepid, rsz);
+						socket->input = (void *)&((uint8_t *)socket->input)[rsz];
+					ret = tcp_rel_buf(socket->cepid, rsz);
 					if ((ret != E_OBJ) && (ret < 0)) {
 						syslog(LOG_ERROR, "tcp_rel_buf => %d", ret);
@@ -538,5 +574,5 @@
 		}
 		case SOCK_DGRAM: {
-			struct sockaddr_in *raddr = &fp->psock->raddr4;
+			struct sockaddr_in *raddr = &socket->raddr4;
 			int rsz;
 			ret = wai_sem(SEM_FILEDESC);
@@ -544,5 +580,5 @@
 				syslog(LOG_ERROR, "wai_sem => %d", ret);
 			}
-			T_NET_BUF *input = fp->psock->input;
+			T_NET_BUF *input = socket->input;
 			if (input == NULL) {
 				ret = sig_sem(SEM_FILEDESC);
@@ -552,8 +588,9 @@
 
 				T_IPV4EP rep = { 0, 0 };
-				ret = udp_rcv_dat(fp->psock->cepid, &rep, buf, len,
-					(fp->psock->flags & O_NONBLOCK) ? TMO_POL : SOCKET_TIMEOUT);
+				ret = udp_rcv_dat(socket->cepid, &rep, buf, len,
+					(socket->flags & O_NONBLOCK) ? TMO_POL : SOCKET_TIMEOUT);
 				if (ret < 0) {
-					syslog(LOG_ERROR, "udp_rcv_buf => %d", ret);
+					if ((socket->flags & O_NONBLOCK) == 0)
+						syslog(LOG_ERROR, "udp_rcv_buf => %d", ret);
 					return (ret == E_TMOUT) ? -ETIME : -ECOMM;
 				}
@@ -565,10 +602,10 @@
 					}
 					int sz = *alen;
-					memset(raddr, 0, sizeof(fp->psock->raddr4));
+					memset(raddr, 0, sizeof(socket->raddr4));
 					raddr->sin_family = AF_INET;
 					raddr->sin_port = htons(rep.portno);
 					raddr->sin_addr.s_addr = htonl(rep.ipaddr);
-					if (sz > sizeof(fp->psock->raddr4))
-						sz = sizeof(fp->psock->raddr4);
+					if (sz > sizeof(socket->raddr4))
+						sz = sizeof(socket->raddr4);
 					memcpy(addr, raddr, sz);
 					*alen = sz;
@@ -580,13 +617,13 @@
 			}
 			else {
-				rsz = fp->psock->len;
-				void *pbuf = fp->psock->buf;
-				fp->psock->input = NULL;
-				fp->psock->len = 0;
-				fp->psock->buf = NULL;
+				rsz = socket->len;
+				void *pbuf = socket->buf;
+				socket->input = NULL;
+				socket->len = 0;
+				socket->buf = NULL;
 				if ((addr != NULL) && (alen != NULL)) {
 					int sz = *alen;
-					if (sz > sizeof(fp->psock->raddr4))
-						sz = sizeof(fp->psock->raddr4);
+					if (sz > sizeof(socket->raddr4))
+						sz = sizeof(socket->raddr4);
 					memcpy(addr, raddr, sz);
 					*alen = sz;
@@ -632,9 +669,10 @@
 
 	ER ret;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		switch (fp->psock->type) {
+		switch (socket->type) {
 		case SOCK_STREAM: {
-			ret = tcp_sht_cep(fp->psock->cepid);
+			ret = tcp_sht_cep(socket->cepid);
 			if (ret < 0) {
 				return -ECOMM;
@@ -661,7 +699,8 @@
 
 	ER ret;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		switch (fp->psock->type) {
+		switch (socket->type) {
 		case SOCK_STREAM: {
 			switch (level) {
@@ -669,5 +708,5 @@
 				switch (optname) {
 				case SO_REUSEADDR:
-					if (fp->psock->flags & SO_REUSEADDR) {
+					if (socket->flags & SO_REUSEADDR) {
 						*(bool *)optval = true;
 					}
@@ -677,5 +716,5 @@
 					break;
 				case SO_KEEPALIVE:
-					if (fp->psock->flags & SO_KEEPALIVE) {
+					if (socket->flags & SO_KEEPALIVE) {
 						*(bool *)optval = true;
 					}
@@ -692,5 +731,5 @@
 				break;
 			case IPPROTO_TCP:
-				ret = tcp_get_opt(fp->psock->cepid, optname, (void *)optval, *optlen);
+				ret = tcp_get_opt(socket->cepid, optname, (void *)optval, *optlen);
 				if (ret < 0) {
 					return -EINVAL;
@@ -706,5 +745,5 @@
 			switch (level) {
 			case IPPROTO_UDP:
-				ret = udp_get_opt(fp->psock->cepid, optname, (void *)optval, *optlen);
+				ret = udp_get_opt(socket->cepid, optname, (void *)optval, *optlen);
 				if (ret < 0) {
 					return -EINVAL;
@@ -736,7 +775,8 @@
 
 	ER ret;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		switch (fp->psock->type) {
+		switch (socket->type) {
 		case SOCK_STREAM: {
 			switch (level){
@@ -745,16 +785,16 @@
 				case SO_REUSEADDR:
 					if (*(bool *)optval) {
-						fp->psock->flags |= SO_REUSEADDR;
+						socket->flags |= SO_REUSEADDR;
 					}
 					else {
-						fp->psock->flags &= ~SO_REUSEADDR;
+						socket->flags &= ~SO_REUSEADDR;
 					}
 					break;
 				case SO_KEEPALIVE:
 					if (*(bool *)optval) {
-						fp->psock->flags |= SO_KEEPALIVE;
+						socket->flags |= SO_KEEPALIVE;
 					}
 					else {
-						fp->psock->flags &= ~SO_KEEPALIVE;
+						socket->flags &= ~SO_KEEPALIVE;
 					}
 					break;
@@ -764,5 +804,5 @@
 				break;
 			case IPPROTO_TCP:
-				ret = tcp_set_opt(fp->psock->cepid, optname, (void *)optval, optlen);
+				ret = tcp_set_opt(socket->cepid, optname, (void *)optval, optlen);
 				if (ret < 0) {
 					return -EINVAL;
@@ -777,5 +817,5 @@
 			switch (level){
 			case IPPROTO_UDP:
-				ret = udp_set_opt(fp->psock->cepid, optname, (void *)optval, optlen);
+				ret = udp_set_opt(socket->cepid, optname, (void *)optval, optlen);
 				if (ret < 0) {
 					return -EINVAL;
@@ -809,7 +849,8 @@
 
 	socklen_t size = *len;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		struct sockaddr_in *raddr = &fp->psock->raddr4;
+		struct sockaddr_in *raddr = &socket->raddr4;
 		*len = sizeof(struct sockaddr_in);
 		if (size > sizeof(struct sockaddr_in))
@@ -837,5 +878,6 @@
 
 	socklen_t size = *len;
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
 		const T_IN4_ADDR *laddr4 = in4_get_ifaddr(0);
@@ -843,5 +885,5 @@
 		laddr.sin_family = AF_INET;
 		laddr.sin_addr.s_addr = htonl(*laddr4);
-		laddr.sin_port = fp->psock->laddr4.sin_port;
+		laddr.sin_port = socket->laddr4.sin_port;
 		memset(&laddr.sin_zero, 0, sizeof(laddr.sin_zero));
 		*len = sizeof(struct sockaddr_in);
@@ -859,21 +901,20 @@
 }
 
-int tcp_fd_close(struct _IO_FILE *fp)
+int tcp_fd_close(struct SHELL_FILE *fp)
 {
 	ER ret, ret2;
 
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		if (fp->psock->cepid != 0) {
-			ID cepid = fp->psock->cepid;
+		if (socket->cepid != 0) {
+			ID cepid = socket->cepid;
 			ret = tcp_sht_cep(cepid);
 			if (ret < 0) {
 				//return -1;
 			}
-			ret = tcp_cls_cep(cepid, (fp->psock->repid != 0) ? 0 : SOCKET_TIMEOUT);
+			ret = tcp_cls_cep(cepid, (socket->repid != 0) ? 0 : SOCKET_TIMEOUT);
 			ret2 = tcp_del_cep(cepid);
-			free(fp->psock->buf);
-			fp->psock->buf = NULL;
-			delete_tcp_fd(cepid);
+			//delete_fd_by_id(&IO_TYPE_TCP, cepid);
 			delete_id(tcp_cepid_table, tcp_cepid_table_count, cepid);
 			if ((ret < 0) || (ret2 < 0)) {
@@ -881,10 +922,8 @@
 			}
 		}
-		else if (fp->psock->repid != 0) {
-			ID repid = fp->psock->repid;
+		else if (socket->repid != 0) {
+			ID repid = socket->repid;
 			ret = tcp_del_rep(repid);
-			free(fp->psock->buf);
-			fp->psock->buf = NULL;
-			delete_tcp_fd(tmax_tcp_cepid + repid);
+			//delete_fd_by_id(&IO_TYPE_TCP, tmax_tcp_cepid + repid);
 			delete_id(tcp_repid_table, tcp_repid_table_count, repid);
 			if (ret < 0) {
@@ -893,6 +932,4 @@
 		}
 		else {
-			free(fp->psock->buf);
-			fp->psock->buf = NULL;
 			return -EINVAL;
 		}
@@ -907,36 +944,157 @@
 }
 
-size_t tcp_fd_read(struct _IO_FILE *fp, unsigned char *dst, size_t dstsz)
+size_t tcp_fd_read(struct SHELL_FILE *fp, unsigned char *dst, size_t dstsz)
 {
 	return shell_recvfrom(fp->fd, dst, dstsz, 0, NULL, NULL);
 }
 
-size_t tcp_fd_write(struct _IO_FILE *fp, const unsigned char *src, size_t srcsz)
+size_t tcp_fd_write(struct SHELL_FILE *fp, const unsigned char *src, size_t srcsz)
 {
 	return shell_sendto(fp->fd, src, srcsz, 0, NULL, 0);
 }
 
-off_t tcp_fd_seek(struct _IO_FILE *fp, off_t ofs, int org)
+off_t tcp_fd_seek(struct SHELL_FILE *fp, off_t ofs, int org)
 {
 	return -EPERM;
 }
 
-int tcp_fd_ioctl(struct _IO_FILE *fp, int req, void *arg)
+int tcp_fd_ioctl(struct SHELL_FILE *fp, int req, void *arg)
 {
 	return -EINVAL;
 }
 
-int udp_fd_close(struct _IO_FILE *fp)
+bool_t tcp_fd_readable(struct SHELL_FILE *fp)
+{
+	ER ret;
+
+	socket_t *socket = (socket_t *)fp->exinf;
+	if (socket->cepid != 0) {
+		if (socket->len == 0) {
+			ret = tcp_rcv_buf(socket->cepid, &socket->input, TMO_NBLK);
+			if ((ret != E_WBLK) && (ret != E_OBJ) && (ret < 0)) {
+				syslog(LOG_ERROR, "tcp_rcv_buf => %d", ret);
+				//return ret;
+			}
+			if (ret > 0) {
+				ret = wai_sem(SEM_FILEDESC);
+				if (ret < 0) {
+					syslog(LOG_ERROR, "wai_sem => %d", ret);
+				}
+				socket->len += ret;
+				ret = sig_sem(SEM_FILEDESC);
+				if (ret < 0) {
+					syslog(LOG_ERROR, "sig_sem => %d", ret);
+				}
+			}
+		}
+		else ret = 1;
+		if (ret > 0) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+void tcp_fd_delete(struct SHELL_FILE *fp)
+{
+	socket_t *socket = (socket_t *)fp->exinf;
+	free(socket->buf);
+	socket->buf = NULL;
+	free(fp->exinf);
+	fp->exinf = NULL;
+}
+
+ER socket_tcp_callback(ID cepid, FN fncd, void *p_parblk)
+{
+	struct SHELL_FILE *fp = id_to_fd(&IO_TYPE_TCP, cepid);
+	FLGPTN flgptn = 0;
+	ER ret;
+	int len;
+
+	if (fp == NULL)
+		return E_PAR;
+
+	int fd = fp->fd;
+	FD_SET(fd, (fd_set *)&flgptn);
+
+	switch (fncd) {
+	case TFN_TCP_RCV_BUF:
+		len = *(int *)p_parblk;
+		if ((len <= 0) || (fp->exinf == NULL))
+			return E_OK;
+
+		ret = wai_sem(SEM_FILEDESC);
+		if (ret < 0) {
+			syslog(LOG_ERROR, "wai_sem => %d", ret);
+		}
+		socket_t *socket = (socket_t *)fp->exinf;
+		socket->len += len;
+		ret = sig_sem(SEM_FILEDESC);
+		if (ret < 0) {
+			syslog(LOG_ERROR, "sig_sem => %d", ret);
+		}
+
+		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+
+	case TFN_TCP_RCV_DAT:
+		len = *(int *)p_parblk;
+		if ((len <= 0) || (fp->exinf == NULL))
+			return E_OK;
+
+		ret = wai_sem(SEM_FILEDESC);
+		if (ret < 0) {
+			syslog(LOG_ERROR, "wai_sem => %d", ret);
+		}
+		socket->len += len;
+		ret = sig_sem(SEM_FILEDESC);
+		if (ret < 0) {
+			syslog(LOG_ERROR, "sig_sem => %d", ret);
+		}
+
+		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+
+	case TFN_TCP_SND_DAT:
+		if (fp->writeevt_w == fp->writeevt_r) fp->writeevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+
+	case TFN_TCP_CAN_CEP:
+		if (fp->errorevt_w == fp->errorevt_r) fp->errorevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+
+	case TFN_TCP_DEL_REP:
+		delete_fd_by_id(&IO_TYPE_TCP, tmax_tcp_cepid + cepid);
+		return E_OK;
+
+	case TFN_TCP_DEL_CEP:
+		delete_fd_by_id(&IO_TYPE_TCP, cepid);
+		return E_OK;
+
+	default:
+		return E_OK;
+	}
+}
+
+int udp_fd_close(struct SHELL_FILE *fp)
 {
 	ER ret;
 	ID cepid;
 
-	switch (fp->psock->family) {
+	socket_t *socket = (socket_t *)fp->exinf;
+	switch (socket->family) {
 	case AF_INET: {
-		cepid = fp->psock->cepid;
+		cepid = socket->cepid;
 		ret = udp_del_cep(cepid);
-		//free(fp->psock->buf);
-		//fp->psock->buf = NULL;
-		delete_udp_fd(cepid);
+		//delete_fd_by_id(&IO_TYPE_UDP, cepid);
 		delete_id(udp_cepid_table, udp_cepid_table_count, cepid);
 		if (ret < 0) {
@@ -953,22 +1111,126 @@
 }
 
-size_t udp_fd_read(struct _IO_FILE *fp, unsigned char *dst, size_t dstsz)
+size_t udp_fd_read(struct SHELL_FILE *fp, unsigned char *dst, size_t dstsz)
 {
 	return shell_recvfrom(fp->fd, dst, dstsz, 0, NULL, NULL);
 }
 
-size_t udp_fd_write(struct _IO_FILE *fp, const unsigned char *src, size_t srcsz)
+size_t udp_fd_write(struct SHELL_FILE *fp, const unsigned char *src, size_t srcsz)
 {
 	return shell_sendto(fp->fd, src, srcsz, 0, NULL, 0);
 }
 
-off_t udp_fd_seek(struct _IO_FILE *fp, off_t ofs, int org)
+off_t udp_fd_seek(struct SHELL_FILE *fp, off_t ofs, int org)
 {
 	return -EPERM;
 }
 
-int udp_fd_ioctl(struct _IO_FILE *fp, int req, void *arg)
+int udp_fd_ioctl(struct SHELL_FILE *fp, int req, void *arg)
 {
 	return -EINVAL;
+}
+
+bool_t udp_fd_readable(struct SHELL_FILE *fp)
+{
+	socket_t *socket = (socket_t *)fp->exinf;
+	if (socket->cepid != 0) {
+		if (socket->input != NULL) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+void udp_fd_delete(struct SHELL_FILE *fp)
+{
+	//socket_t *socket = (socket_t *)fp->exinf;
+	//free(socket->buf);
+	//socket->buf = NULL;
+	free(fp->exinf);
+	fp->exinf = NULL;
+}
+
+ER socket_udp_callback(ID cepid, FN fncd, void *p_parblk)
+{
+	struct SHELL_FILE *fp = id_to_fd(&IO_TYPE_UDP, cepid);
+	FLGPTN flgptn = 0;
+	int len;
+
+	if (fp == NULL)
+		return E_PAR;
+
+	int fd = fp->fd;
+	FD_SET(fd, (fd_set *)&flgptn);
+
+	switch (fncd) {
+	case TEV_UDP_RCV_DAT:
+	{
+		T_UDP_RCV_DAT_PARA *udppara = (T_UDP_RCV_DAT_PARA *)p_parblk;
+		len = udppara->len;
+		if ((len <= 0) || (fp->exinf == NULL))
+			return E_OK;
+
+		ER ret = wai_sem(SEM_FILEDESC);
+		if (ret < 0) {
+			syslog(LOG_ERROR, "wai_sem => %d", ret);
+		}
+		socket_t *socket = (socket_t *)fp->exinf;
+		socket->len = len;
+		if (socket->input != NULL) {
+			ret = rel_net_buf(socket->input);
+			if (ret < 0) {
+				syslog(LOG_ERROR, "rel_net_buf => %d", ret);
+			}
+		}
+		socket->input = udppara->input;
+		socket->buf = GET_UDP_SDU(udppara->input, udppara->off);
+		memset(&socket->raddr4, 0, sizeof(socket->raddr4));
+		socket->raddr4.sin_family = AF_INET;
+		socket->raddr4.sin_port = htons(udppara->rep4.portno);
+		socket->raddr4.sin_addr.s_addr = htonl(udppara->rep4.ipaddr);
+		udppara->input->flags |= NB_FLG_NOREL_IFOUT;
+		ret = sig_sem(SEM_FILEDESC);
+		if (ret < 0) {
+			syslog(LOG_ERROR, "sig_sem => %d", ret);
+		}
+
+		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+	}
+	case TFN_UDP_CRE_CEP:
+		return E_OK;
+
+	case TFN_UDP_RCV_DAT:
+		len = *(int *)p_parblk;
+		if ((len <= 0) || (fp->exinf == NULL))
+			return E_OK;
+
+		if (fp->readevt_w == fp->readevt_r) fp->readevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+
+	case TFN_UDP_SND_DAT:
+		if (fp->writeevt_w == fp->writeevt_r) fp->writeevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+
+	case TFN_UDP_CAN_CEP:
+		if (fp->errorevt_w == fp->errorevt_r) fp->errorevt_w++;
+
+		set_flg(FLG_SELECT_WAIT, flgptn);
+		return E_OK;
+
+	case TFN_UDP_DEL_CEP:
+		delete_fd_by_id(&IO_TYPE_UDP, cepid);
+		return E_OK;
+
+	default:
+		return E_OK;
+	}
 }
 
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/socket_stub.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/socket_stub.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/socket_stub.h	(revision 374)
@@ -103,18 +103,15 @@
 } socket_t;
 
-struct _IO_DIR {
-	DIR dir;
+struct SHELL_DIR {
+	FATFS_DIR dir;
 	struct dirent dirent;
 };
 
-struct _IO_FILE {
+typedef const struct io_type_s IO_TYPE;
+
+struct SHELL_FILE {
 	int fd;
-	int type;
+	IO_TYPE *type;
 	int handle;
-	int (*close)(struct _IO_FILE *);
-	size_t (*read)(struct _IO_FILE *, unsigned char *, size_t);
-	size_t (*write)(struct _IO_FILE *, const unsigned char *, size_t);
-	off_t (*seek)(struct _IO_FILE *, off_t, int);
-	int (*ioctl)(struct _IO_FILE *, int, void *);
 	int readevt_r;
 	int readevt_w;
@@ -124,9 +121,15 @@
 	int errorevt_r;
 	int errorevt_w;
-	union {
-		FIL *pfile;
-		struct _IO_DIR *pdir;
-		socket_t *psock;
-	};
+	void *exinf;
+};
+
+struct io_type_s {
+	int (*close)(struct SHELL_FILE *);
+	size_t (*read)(struct SHELL_FILE *, unsigned char *, size_t);
+	size_t (*write)(struct SHELL_FILE *, const unsigned char *, size_t);
+	off_t (*seek)(struct SHELL_FILE *, off_t, int);
+	int (*ioctl)(struct SHELL_FILE *, int, void *);
+	bool_t (*readable)(struct SHELL_FILE *);
+	void (*delete)(struct SHELL_FILE *);
 };
 
@@ -141,65 +144,10 @@
 #endif
 
-extern int stdio_close(struct _IO_FILE *fp);
-extern size_t stdio_read(struct _IO_FILE *fp, unsigned char *data, size_t len);
-extern size_t stdio_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
-extern size_t stdin_read(struct _IO_FILE *fp, unsigned char *data, size_t len);
-extern size_t stdout_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
-extern size_t stderr_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
+struct SHELL_FILE *new_fp(IO_TYPE *type, int id, int writable);
+int delete_fd_by_id(IO_TYPE *type, int id);
+struct SHELL_FILE *fd_to_fp(int fd);
+struct SHELL_FILE *id_to_fd(IO_TYPE *type, int id);
 
-extern int sio_close(struct _IO_FILE *fp);
-extern size_t sio_read(struct _IO_FILE *fp, unsigned char *data, size_t len);
-extern size_t sio_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
-extern off_t sio_seek(struct _IO_FILE *fp, off_t ofs, int org);
-extern int sio_ioctl(struct _IO_FILE *fp, int req, void *arg);
-
-extern int file_close(struct _IO_FILE *fp);
-extern size_t file_read(struct _IO_FILE *fp, unsigned char *data, size_t len);
-extern size_t file_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
-extern off_t file_seek(struct _IO_FILE *fp, off_t ofs, int org);
-extern int file_ioctl(struct _IO_FILE *fp, int req, void *arg);
-
-extern int dir_close(struct _IO_FILE *fp);
-extern size_t dir_read(struct _IO_FILE *fp, unsigned char *data, size_t len);
-extern size_t dir_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
-extern off_t dir_seek(struct _IO_FILE *fp, off_t ofs, int org);
-extern int dir_ioctl(struct _IO_FILE *fp, int req, void *arg);
-
-extern int tcp_fd_close(struct _IO_FILE *fp);
-extern size_t tcp_fd_read(struct _IO_FILE *fp, unsigned char *data, size_t len);
-extern size_t tcp_fd_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
-extern off_t tcp_fd_seek(struct _IO_FILE *fp, off_t ofs, int org);
-extern int tcp_fd_ioctl(struct _IO_FILE *fp, int req, void *arg);
-
-extern int udp_fd_close(struct _IO_FILE *fp);
-extern size_t udp_fd_read(struct _IO_FILE *fp, unsigned char *data, size_t len);
-extern size_t udp_fd_write(struct _IO_FILE *fp, const unsigned char *data, size_t len);
-extern off_t udp_fd_seek(struct _IO_FILE *fp, off_t ofs, int org);
-extern int udp_fd_ioctl(struct _IO_FILE *fp, int req, void *arg);
-
-struct _IO_FILE *fd_to_fp(int fd);
-
-struct _IO_FILE *new_sio_fd(int sioid);
-int delete_sio_fd(int sioid);
-struct _IO_FILE *sioid_to_fd(int sioid);
-
-struct _IO_FILE *new_file_fd(int fileid);
-int delete_file_fd(int fileid);
-struct _IO_FILE *fileid_to_fd(int fileid);
-
-struct _IO_FILE *new_dir_fd(int dirid);
-int delete_dir_fd(int dirid);
-struct _IO_FILE *dirid_to_fd(int dirid);
-
-struct _IO_FILE *new_tcp_fd(int tcpid);
-int delete_tcp_fd(int tcpid);
-struct _IO_FILE *tcpid_to_fd(int tcpid);
-
-struct _IO_FILE *new_udp_fd(int udpid);
-int delete_udp_fd(int udpid);
-struct _IO_FILE *udpid_to_fd(int udpid);
-
-int delete_fp(struct _IO_FILE *fp);
-int delete_tcp_rep(int repid);
+int delete_fp(struct SHELL_FILE *fp);
 void clean_fd();
 
Index: asp3_tinet_ecnl_arm/trunk/ntshell/src/syscall.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/src/syscall.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/src/syscall.c	(revision 374)
@@ -48,9 +48,9 @@
 
 	/* ==== Cleaning and invalidation of the L1 data cache ==== */
-	__v7_all_cache(2);
+	L1C_CleanInvalidateDCacheAll();
 	__DSB();
 
 	/* ==== Cleaning and invalidation of the L2 cache ==== */
-	if (PL310->AUX_CNT & (1 << 16)) {
+	if (L2C_310->AUX_CNT & (1 << 16)) {
 		assoc = 16;
 	}
@@ -58,13 +58,13 @@
 		assoc = 8;
 	}
-	PL310->INV_WAY = (1 << assoc) - 1;
-	while (PL310->INV_WAY & ((1 << assoc) - 1)); // poll invalidate
-	PL310->CACHE_SYNC = 0x0;
+	L2C_310->INV_WAY = (1 << assoc) - 1;
+	while (L2C_310->INV_WAY & ((1 << assoc) - 1)); // poll invalidate
+	L2C_310->CACHE_SYNC = 0x0;
 
 	/* ==== Invalidate all TLB entries ==== */
-	__ca9u_inv_tlb_all();
+	MMU_InvalidateTLB();
 
 	/* ==== Invalidate the L1 instruction cache ==== */
-	__v7_inv_icache_all();
+	L1C_InvalidateICacheAll();
 	__DSB();
 	__ISB();
@@ -184,5 +184,6 @@
 }
 
-long SYS_fdatasync() {
+long SYS_fdatasync(long a) {
+	//int fdatasync(int fd)
 	return no_implement("fdatasync\n");
 }
@@ -200,10 +201,11 @@
 }
 
-long SYS_futex() {
-	int futex(int *uaddr, int op, int val, const struct timespec *timeout, int *uaddr2, int val3);
+long SYS_futex(long a, long b, long c, long d, long e, long f) {
+	//int futex(int *uaddr, int op, int val, const struct timespec *timeout, int *uaddr2, int val3);
 	return no_implement("futex\n");
 }
 
-long SYS_futimesat() {
+long SYS_futimesat(long a, long b, long c) {
+	//int futimesat(int dirfd, const char *pathname, const struct timeval times[2])
 	return no_implement("futimesat\n");
 }
@@ -281,5 +283,6 @@
 }
 
-long SYS_munmap() {
+long SYS_munmap(long a, long b) {
+	//int munmap(void *start, size_t len)
 	return no_implement("munmap\n");
 }
@@ -293,9 +296,13 @@
 }
 
-long SYS_pread64() {
+long SYS_pread64(long a, long b, long c, long d) {
+	//#define pread64 pread
+	//ssize_t pread(int fd, void *buf, size_t size, off_t ofs)
 	return no_implement("pread64\n");
 }
 
-long SYS_pwrite64() {
+long SYS_pwrite64(long a, long b, long c, long d) {
+	//#define pwrite64 pwrite
+	//ssize_t pwrite(int fd, const void *buf, size_t size, off_t ofs)
 	return no_implement("pwrite64\n");
 }
@@ -337,5 +344,6 @@
 }
 
-long SYS_rt_sigqueueinfo() {
+long SYS_rt_sigqueueinfo(long a, long b, long c) {
+	//int rt_sigqueueinfo(pid_t tgid, int sig, siginfo_t *uinfo)
 	return no_implement("rt_sigqueueinfo\n");
 }
@@ -361,9 +369,11 @@
 }
 
-long SYS_sched_setscheduler() {
+long SYS_sched_setscheduler(long a, long b, long c) {
+	//int sched_setscheduler(pid_t pid, int sched, const struct sched_param *param)
 	return no_implement("sched_setscheduler\n");
 }
 
-long SYS_set_robust_list() {
+long SYS_set_robust_list(long a, long b) {
+	//long set_robust_list(struct robust_list_head *head, size_t len)
 	return no_implement("set_robust_list\n");
 }
@@ -401,9 +411,11 @@
 }
 
-long SYS_utimensat() {
+long SYS_utimensat(long a, long b, long c, long d) {
+	//int utimensat(int fd, const char *path, const struct timespec times[2], int flags)
 	return no_implement("utimensat\n");
 }
 
-long SYS_utimes() {
+long SYS_utimes(long a, long b) {
+	//int utimes(const char *path, const struct timeval times[2])
 	return no_implement("utimes\n");
 }
@@ -417,57 +429,134 @@
 }
 
-long SYS_dup()
-{
+long SYS_dup(long a) {
+	//int dup(int fd)
 	return no_implement("dup\n");
 }
 
-long SYS_dup2()
-{
+long SYS_dup2(long a, long b) {
+	//int dup2(int old, int new)
 	return no_implement("dup2\n");
 }
 
-long SYS_pipe()
-{
+long SYS_pipe(long a) {
+	//int pipe(int fd[2])
 	return no_implement("pipe\n");
 }
 
-long SYS_readlink()
-{
+long SYS_readlink(long a, long b, long c) {
+	//ssize_t readlink(const char *restrict path, char *restrict buf, size_t bufsize)
 	return no_implement("readlink\n");
 }
 
-long SYS_symlink()
-{
+long SYS_symlink(long a, long b) {
+	//int symlink(const char *existing, const char *new)
 	return no_implement("symlink\n");
 }
 
-long SYS_umask()
-{
+long SYS_umask(long a) {
+	//mode_t umask(mode_t mode)
 	return no_implement("umask\n");
 }
 
-long SYS_execve()
-{
+long SYS_execve(long a, long b, long c) {
+	//int execve(const char *path, char *const argv[], char *const envp[])
 	return no_implement("execve\n");
 }
 
-long SYS_fork()
-{
+long SYS_fork() {
+	//pid_t fork(void)
 	return no_implement("fork\n");
 }
 
-long SYS_wait4()
-{
+long SYS_wait4(long a, long b, long c, long d) {
+	//pid_t wait4(pid_t pid, int *status, int options, struct rusage *usage)
 	return no_implement("wait4\n");
 }
 
-long SYS_socketpair()
-{
+long SYS_socketpair(long a, long b, long c, long d) {
+	//int socketpair(int domain, int type, int protocol, int fd[2])
 	return no_implement("socketpair\n");
 }
 
-long SYS_flock()
-{
+long SYS_flock(long a, long b) {
+	//int flock(int fd, int op)
 	return no_implement("flock\n");
+}
+
+long SYS_fchdir()
+{
+	return no_implement("fchdir\n");
+}
+
+long SYS_getegid32()
+{
+	return no_implement("getegid32\n");
+}
+
+long SYS_geteuid32()
+{
+	return no_implement("geteuid32\n");
+}
+
+long SYS_getgid32()
+{
+	return no_implement("getgid32\n");
+}
+
+long SYS_pipe2()
+{
+	return no_implement("pipe2\n");
+}
+
+long SYS_setgid32()
+{
+	return no_implement("setgid32\n");
+}
+
+long SYS_setpgid()
+{
+	return no_implement("setpgid\n");
+}
+
+long SYS_setsid()
+{
+	return no_implement("setsid\n");
+}
+
+long SYS_setuid32()
+{
+	return no_implement("setuid32\n");
+}
+
+long SYS_tgkill()
+{
+	return no_implement("tgkill\n");
+}
+
+long SYS_nanosleep(long a, long b) {
+	//int nanosleep(const struct timespec *req, struct timespec *rem)
+	return no_implement("nanosleep\n");
+}
+
+long SYS_prlimit64(long a, long b, long c, long d) {
+	//#define prlimit64 prlimit
+	//int prlimit(pid_t pid, int resource, const struct rlimit *new_limit, struct rlimit *old_limit)
+	return no_implement("prlimit64\n");
+}
+
+long SYS_sched_getaffinity(long a, long b, long c) {
+	//int sched_getaffinity(pid_t tid, size_t size, cpu_set_t *set)
+	return no_implement("sched_getaffinity\n");
+}
+
+long SYS_sysinfo(long a) {
+	//int sysinfo(struct sysinfo *info)
+	return no_implement("sysinfo\n");
+}
+
+long SYS_ugetrlimit(long a, long b) {
+	//#define SYS_getrlimit SYS_ugetrlimit
+	//int getrlimit(int resource, struct rlimit *rlim)
+	return no_implement("ugetrlimit\n");
 }
 
Index: asp3_tinet_ecnl_arm/trunk/ntshell/tlsf/tlsf.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/ntshell/tlsf/tlsf.c	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/ntshell/tlsf/tlsf.c	(revision 374)
@@ -5,5 +5,5 @@
 #include <stdlib.h>
 #include <string.h>
-#include "util/ntstdio.h"
+#include <stdio.h>
 
 #include "tlsf.h"
@@ -16,6 +16,4 @@
 #define tlsf_decl static
 #endif
-
-extern ntstdio_t ntstdio;
 
 /*
@@ -889,5 +887,5 @@
 {
 	(void)user;
-	ntstdio_printf(&ntstdio, "\t%p %s size: %x (%p)\n", ptr, used ? "used" : "free", (unsigned int)size, block_from_ptr(ptr));
+	printf("\t%p %s size: %x (%p)\n", ptr, used ? "used" : "free", (unsigned int)size, block_from_ptr(ptr));
 }
 
@@ -978,5 +976,5 @@
 	if (((ptrdiff_t)mem % ALIGN_SIZE) != 0)
 	{
-		ntstdio_printf(&ntstdio, "tlsf_add_pool: Memory must be aligned by %u bytes.\n",
+		printf("tlsf_add_pool: Memory must be aligned by %u bytes.\n",
 			(unsigned int)ALIGN_SIZE);
 		return 0;
@@ -986,9 +984,9 @@
 	{
 #if defined (TLSF_64BIT)
-		ntstdio_printf(&ntstdio, "tlsf_add_pool: Memory size must be between 0x%x and 0x%x00 bytes.\n", 
+		printf("tlsf_add_pool: Memory size must be between 0x%x and 0x%x00 bytes.\n", 
 			(unsigned int)(pool_overhead + block_size_min),
 			(unsigned int)((pool_overhead + block_size_max) / 256));
 #else
-		ntstdio_printf(&ntstdio, "tlsf_add_pool: Memory size must be between %u and %u bytes.\n", 
+		printf("tlsf_add_pool: Memory size must be between %u and %u bytes.\n", 
 			(unsigned int)(pool_overhead + block_size_min),
 			(unsigned int)(pool_overhead + block_size_max));
@@ -1058,5 +1056,5 @@
 	if (rv)
 	{
-		ntstdio_printf(&ntstdio, "test_ffs_fls: %x ffs/fls tests failed.\n", rv);
+		printf("test_ffs_fls: %x ffs/fls tests failed.\n", rv);
 	}
 	return rv;
@@ -1075,5 +1073,5 @@
 	if (((tlsfptr_t)mem % ALIGN_SIZE) != 0)
 	{
-		ntstdio_printf(&ntstdio, "tlsf_create: Memory must be aligned to %u bytes.\n",
+		printf("tlsf_create: Memory must be aligned to %u bytes.\n",
 			(unsigned int)ALIGN_SIZE);
 		return 0;
Index: asp3_tinet_ecnl_arm/trunk/usbhost/src/usb_hbth.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/usbhost/src/usb_hbth.h	(revision 373)
+++ asp3_tinet_ecnl_arm/trunk/usbhost/src/usb_hbth.h	(revision 374)
@@ -12,6 +12,24 @@
 #define USBHOST_STACK_SIZE			2048
 
-extern void usbhost_init(ID tskid);
-extern void usbhost_main(intptr_t exinf);
+enum task_event_t {
+	TASK_EVENT_START,
+	TASK_EVENT_TERMINATE,
+	TASK_EVENT_WAKEUP,
+	TASK_EVENT_TIMEOUT,
+	TASK_EVENT_TICK = 0x80,
+};
+
+struct task_if_t {
+	void (*on_start)(struct task_if_t *task, ID tskid);
+	void (*on_end)(struct task_if_t *task);
+	int (*get_timer)(struct task_if_t *task);
+	void (*progress)(struct task_if_t *task, int elapse);
+	void (*process)(struct task_if_t *task, enum task_event_t event);
+};
+
+extern struct task_if_t bt_task;
+
+void usbhost_init(ID tskid);
+void usbhost_main(intptr_t exinf);
 
 /*
