Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c	(revision 352)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c	(revision 374)
@@ -1,522 +1,162 @@
-/**************************************************************************//**
- * @file     system_MBRZA1H.c
- * @brief    CMSIS Device System Source File for
- *           ARM Cortex-A9 Device Series
+/******************************************************************************
+ * @file     system_RZ_A1H_H.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
  * @version  V1.00
- * @date     09 January 2015
+ * @date     10 Mar 2017
  *
  * @note
  *
  ******************************************************************************/
-/* Copyright (c) 2011 - 2015 ARM LIMITED
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
 
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
+#include <RZ_A1H.h>
+#include "RZ_A1_Init.h"
+#include "irq_ctrl.h"
 
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
 
-#include <stdint.h>
-#include "MBRZA1H.h"
-#include "RZ_A1_Init.h"
+/*
+ Port 0 (P0) MD pin assignment
+ P0_0: MD_BOOT0
+ P0_1: MD_BOOT1
+ P0_2: MD_CLK
+ P0_3: MD_CLKS
+ */
 
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
 
-#if defined(__ARMCC_VERSION)
-extern void $Super$$main(void);
-__asm void FPUEnable(void);
-#else 
-void FPUEnable(void); 
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  uint32_t freq;
+  uint16_t mode;
+  uint16_t ifc;
 
-#endif
+  mode = (GPIO.PPR0 >> 2U) & 0x01U;
 
-#define FRQCR_IFC_MSK          (0x0030)
-#define FRQCR_IFC_SHFT         (8)
-#define FRQCR_IFC_1P1          (0) /* x1/1 */
-#define FRQCR_IFC_2P3          (1) /* x2/3 */
-#define FRQCR_IFC_1P3          (3) /* x1/3 */
+  if (mode == 0) {
+    /* Clock Mode 0 */
+    /* CLKIN is between 10MHz and 13.33MHz */
+    /* Divider 1 uses 1/1 ratio, PLL x30 is ON */
+    freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
+  } else {
+    /* Clock Mode 1 */
+    /* CLKIN is 48MHz */
+    /* Divider 1 uses 1/4 ratio, PLL x32 is ON */
+    freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
+  }
 
-extern uint32_t IRQNestLevel;
-unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
-uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
+  /* Get CPG.FRQCR[IFC] bits */
+  ifc = (CPG.FRQCR >> 8U) & 0x03U;
 
+  /* Determine Divider 2 output clock */
+  if (ifc == 0x03U) {
+    /* Division ratio is 1/3 */
+    freq = (freq / 3U);
+  }
+  else {
+    if (ifc == 0x01U) {
+      /* Division ratio is 2/3 */
+      freq = (freq * 2U) / 3U;
+    }
+  }
 
-/**
- * Initialize the cache.
- *
- * @param  none
- * @return none
- *
- * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
- */
-#if defined(__ARMCC_VERSION)
-#pragma push
-#pragma arm
+  SystemCoreClock = freq;
+}
 
-void InitMemorySubsystem(void) {
-
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
-     * You are not required to invalidate the main TLB, even though it is recommended for safety
-     * reasons. This ensures compatibility with future revisions of the processor. */
-
-    unsigned int l2_id;
-
-    /* Invalidate undefined data */
-    __ca9u_inv_tlb_all();
-    __v7_inv_icache_all();
-    __v7_inv_dcache_all();
-    __v7_inv_btac();
-
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
-     * invalidate in order to flush the valid data to the next level cache.
-     */
-    __enable_mmu();
-
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
-    __enable_caches();
-    __enable_btac();
-
-    /* If present, you may also need to Invalidate and Enable L2 cache here */
-    l2_id = PL310_GetID();
-    if (l2_id)
-    {
-       PL310_InvAllByWay();
-       PL310_Enable();
-    }
-}
-#pragma pop
-
-#elif defined(__GNUC__) 
-
-void InitMemorySubsystem(void) { 
- 
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
-     * You are not required to invalidate the main TLB, even though it is recommended for safety 
-     * reasons. This ensures compatibility with future revisions of the processor. */ 
- 
-    unsigned int l2_id; 
- 
-    /* Invalidate undefined data */ 
-    __ca9u_inv_tlb_all(); 
-    __v7_inv_icache_all(); 
-    __v7_inv_dcache_all(); 
-    __v7_inv_btac(); 
- 
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
-     * invalidate in order to flush the valid data to the next level cache. 
-     */ 
-    __enable_mmu(); 
- 
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
-    __enable_caches(); 
-    __enable_btac(); 
- 
-    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
-    l2_id = PL310_GetID(); 
-    if (l2_id) 
-    { 
-       PL310_InvAllByWay(); 
-       PL310_Enable(); 
-    } 
-} 
-#elif defined ( __ICCARM__ )
-
-void InitMemorySubsystem(void) { 
- 
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
-     * You are not required to invalidate the main TLB, even though it is recommended for safety 
-     * reasons. This ensures compatibility with future revisions of the processor. */ 
- 
-    unsigned int l2_id; 
- 
-    /* Invalidate undefined data */ 
-    __ca9u_inv_tlb_all(); 
-    __v7_inv_icache_all(); 
-    __v7_inv_dcache_all(); 
-    __v7_inv_btac(); 
- 
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
-     * invalidate in order to flush the valid data to the next level cache. 
-     */ 
-    __enable_mmu();
- 
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
-    __enable_caches(); 
-    __enable_btac(); 
- 
-    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
-    l2_id = PL310_GetID(); 
-    if (l2_id) 
-    { 
-       PL310_InvAllByWay(); 
-       PL310_Enable(); 
-    } 
-} 
-#else 
-
-#endif 
-
-
-extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
-
-uint32_t IRQCount = sizeof IRQTable / 4;
-
+/*----------------------------------------------------------------------------
+  IRQ Handler Register/Unregister
+ *----------------------------------------------------------------------------*/
 uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
 {
-    if (irq < IRQCount) {
-        IRQTable[irq] = handler;
-        return 0;
-    }
-    else {
-        return 1;
-    }
+    return IRQ_SetHandler(irq, handler);
 }
 
 uint32_t InterruptHandlerUnregister (IRQn_Type irq)
 {
-    if (irq < IRQCount) {
-        IRQTable[irq] = 0;
-        return 0;
-    }
-    else {
-        return 1;
-    }
+    return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
 }
 
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock.
- */
-void SystemCoreClockUpdate (void)
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
 {
-    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
+/*       do not use global variables because this function is called before
+         reaching pre-main. RW section may be overwritten afterwards.          */
+  
+  // Enable SRAM write access
+  CPG.SYSCR3 = 0x0F;
 
-    switch (frqcr_ifc) {
-        case FRQCR_IFC_1P1:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
-            break;
-        case FRQCR_IFC_2P3:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
-            break;
-        case FRQCR_IFC_1P3:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
-            break;
-        default:
-            /* do nothing */
-            break;
-    }
+  RZ_A1_InitClock();
+  RZ_A1_InitBus();
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  L2C_InvAllByWay();
+  // Enable L2C
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
 }
 
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-    IRQNestLevel = 0;
-/*       do not use global variables because this function is called before
-         reaching pre-main. RW section maybe overwritten afterwards.          */
-    RZ_A1_InitClock();
-    RZ_A1_InitBus();
-
-	//Configure GIC ICDICFR GIC_SetICDICFR()
-    GIC_Enable();
-    __enable_irq();
-
+void mbed_sdk_init(void) {
+    L1C_CleanDCacheAll();
+    L1C_InvalidateICacheAll();
 }
-
-
-//Fault Status Register (IFSR/DFSR) definitions
-#define FSR_ALIGNMENT_FAULT                  0x01   //DFSR only. Fault on first lookup
-#define FSR_INSTRUCTION_CACHE_MAINTENANCE    0x04   //DFSR only - async/external
-#define FSR_SYNC_EXT_TTB_WALK_FIRST          0x0c   //sync/external
-#define FSR_SYNC_EXT_TTB_WALK_SECOND         0x0e   //sync/external
-#define FSR_SYNC_PARITY_TTB_WALK_FIRST       0x1c   //sync/external
-#define FSR_SYNC_PARITY_TTB_WALK_SECOND      0x1e   //sync/external
-#define FSR_TRANSLATION_FAULT_FIRST          0x05   //MMU Fault - internal
-#define FSR_TRANSLATION_FAULT_SECOND         0x07   //MMU Fault - internal
-#define FSR_ACCESS_FLAG_FAULT_FIRST          0x03   //MMU Fault - internal
-#define FSR_ACCESS_FLAG_FAULT_SECOND         0x06   //MMU Fault - internal
-#define FSR_DOMAIN_FAULT_FIRST               0x09   //MMU Fault - internal
-#define FSR_DOMAIN_FAULT_SECOND              0x0b   //MMU Fault - internal
-#define FSR_PERMISION_FAULT_FIRST            0x0f   //MMU Fault - internal
-#define FSR_PERMISION_FAULT_SECOND           0x0d   //MMU Fault - internal
-#define FSR_DEBUG_EVENT                      0x02   //internal
-#define FSR_SYNC_EXT_ABORT                   0x08   //sync/external
-#define FSR_TLB_CONFLICT_ABORT               0x10   //sync/external
-#define FSR_LOCKDOWN                         0x14   //internal
-#define FSR_COPROCESSOR_ABORT                0x1a   //internal
-#define FSR_SYNC_PARITY_ERROR                0x19   //sync/external
-#define FSR_ASYNC_EXTERNAL_ABORT             0x16   //DFSR only - async/external
-#define FSR_ASYNC_PARITY_ERROR               0x18   //DFSR only - async/external
-
-void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
-    uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
-
-    switch(FS) {
-        //Synchronous parity errors - retry
-        case FSR_SYNC_PARITY_ERROR:
-        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
-        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
-            return;
-
-        //Your code here. Value in DFAR is invalid for some fault statuses.
-        case FSR_ALIGNMENT_FAULT:
-        case FSR_INSTRUCTION_CACHE_MAINTENANCE:
-        case FSR_SYNC_EXT_TTB_WALK_FIRST:
-        case FSR_SYNC_EXT_TTB_WALK_SECOND:
-        case FSR_TRANSLATION_FAULT_FIRST:
-        case FSR_TRANSLATION_FAULT_SECOND:
-        case FSR_ACCESS_FLAG_FAULT_FIRST:
-        case FSR_ACCESS_FLAG_FAULT_SECOND:
-        case FSR_DOMAIN_FAULT_FIRST:
-        case FSR_DOMAIN_FAULT_SECOND:
-        case FSR_PERMISION_FAULT_FIRST:
-        case FSR_PERMISION_FAULT_SECOND:
-        case FSR_DEBUG_EVENT:
-        case FSR_SYNC_EXT_ABORT:
-        case FSR_TLB_CONFLICT_ABORT:
-        case FSR_LOCKDOWN:
-        case FSR_COPROCESSOR_ABORT:
-        case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
-        case FSR_ASYNC_PARITY_ERROR:   //DFAR invalid
-        default:
-        	_kernel_default_exc_handler();
-    }
-}
-
-void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
-    uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
-
-    switch(FS) {
-        //Synchronous parity errors - retry
-        case FSR_SYNC_PARITY_ERROR:
-        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
-        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
-            return;
-
-        //Your code here. Value in IFAR is invalid for some fault statuses.
-        case FSR_SYNC_EXT_TTB_WALK_FIRST:
-        case FSR_SYNC_EXT_TTB_WALK_SECOND:
-        case FSR_TRANSLATION_FAULT_FIRST:
-        case FSR_TRANSLATION_FAULT_SECOND:
-        case FSR_ACCESS_FLAG_FAULT_FIRST:
-        case FSR_ACCESS_FLAG_FAULT_SECOND:
-        case FSR_DOMAIN_FAULT_FIRST:
-        case FSR_DOMAIN_FAULT_SECOND:
-        case FSR_PERMISION_FAULT_FIRST:
-        case FSR_PERMISION_FAULT_SECOND:
-        case FSR_DEBUG_EVENT: //IFAR invalid
-        case FSR_SYNC_EXT_ABORT:
-        case FSR_TLB_CONFLICT_ABORT:
-        case FSR_LOCKDOWN:
-        case FSR_COPROCESSOR_ABORT:
-        default:
-            _kernel_default_exc_handler();
-    }
-}
-
-//returns amount to decrement lr by
-//this will be 0 when we have emulated the instruction and want to execute the next instruction
-//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
-//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
-uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
-    const unsigned int THUMB = 2;
-    const unsigned int ARM = 4;
-    //Lazy VFP/NEON initialisation and switching
-
-    // (ARM ARM section A7.5) VFP data processing instruction?
-    // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
-    // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
-    // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
-    if ((state == ARM   && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
-        (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
-        if (((opcode & 0x00000E00) >> 9) == 5) {
-            FPUEnable();
-            return state;
-        }
-    }
-
-    // (ARM ARM section A7.4) NEON data processing instruction?
-    if ((state == ARM   && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
-        (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
-    // (ARM ARM section A7.7) NEON load/store instruction?
-        (state == ARM   && ((opcode >> 24) == 0xF4)) ||
-        (state == THUMB && ((opcode >> 24) == 0xF9))) {
-        FPUEnable();
-        return state;
-    }
-
-    //Add code here for other Undef cases
-    _kernel_default_exc_handler();
-    return 0;
-}
-
-#if defined(__ARMCC_VERSION)
-#pragma push
-#pragma arm
-//Critical section, called from undef handler, so systick is disabled
-__asm void FPUEnable(void) {
-        ARM
-
-        //Permit access to VFP/NEON, registers by modifying CPACR
-        MRC     p15,0,R1,c1,c0,2
-        ORR     R1,R1,#0x00F00000
-        MCR     p15,0,R1,c1,c0,2
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-        ISB
-
-        //Enable VFP/NEON
-        VMRS    R1,FPEXC
-        ORR     R1,R1,#0x40000000
-        VMSR    FPEXC,R1
-
-        //Initialise VFP/NEON registers to 0
-        MOV     R2,#0
-        //Initialise D16 registers to 0
-        VMOV    D0, R2,R2
-        VMOV    D1, R2,R2
-        VMOV    D2, R2,R2
-        VMOV    D3, R2,R2
-        VMOV    D4, R2,R2
-        VMOV    D5, R2,R2
-        VMOV    D6, R2,R2
-        VMOV    D7, R2,R2
-        VMOV    D8, R2,R2
-        VMOV    D9, R2,R2
-        VMOV    D10,R2,R2
-        VMOV    D11,R2,R2
-        VMOV    D12,R2,R2
-        VMOV    D13,R2,R2
-        VMOV    D14,R2,R2
-        VMOV    D15,R2,R2
-        //Initialise D32 registers to 0
-        VMOV    D16,R2,R2
-        VMOV    D17,R2,R2
-        VMOV    D18,R2,R2
-        VMOV    D19,R2,R2
-        VMOV    D20,R2,R2
-        VMOV    D21,R2,R2
-        VMOV    D22,R2,R2
-        VMOV    D23,R2,R2
-        VMOV    D24,R2,R2
-        VMOV    D25,R2,R2
-        VMOV    D26,R2,R2
-        VMOV    D27,R2,R2
-        VMOV    D28,R2,R2
-        VMOV    D29,R2,R2
-        VMOV    D30,R2,R2
-        VMOV    D31,R2,R2
-        //Initialise FPSCR to a known state
-        VMRS    R2,FPSCR
-        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        AND     R2,R2,R3
-        VMSR    FPSCR,R2
-
-        BX      LR
-}
-#pragma pop
-
-#elif defined(__GNUC__)
-void FPUEnable(void) {
-    __asm__ (
-        ".ARM;"
-
-        //Permit access to VFP/NEON, registers by modifying CPACR
-        "MRC     p15,0,R1,c1,c0,2;"
-        "ORR     R1,R1,#0x00F00000;"
-        "MCR     p15,0,R1,c1,c0,2;"
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-        "ISB;"
-
-        //Enable VFP/NEON
-        "VMRS    R1,FPEXC;"
-        "ORR     R1,R1,#0x40000000;"
-        "VMSR    FPEXC,R1;"
-
-        //Initialise VFP/NEON registers to 0
-        "MOV     R2,#0;"
-        //Initialise D16 registers to 0
-        "VMOV    D0, R2,R2;"
-        "VMOV    D1, R2,R2;"
-        "VMOV    D2, R2,R2;"
-        "VMOV    D3, R2,R2;"
-        "VMOV    D4, R2,R2;"
-        "VMOV    D5, R2,R2;"
-        "VMOV    D6, R2,R2;"
-        "VMOV    D7, R2,R2;"
-        "VMOV    D8, R2,R2;"
-        "VMOV    D9, R2,R2;"
-        "VMOV    D10,R2,R2;"
-        "VMOV    D11,R2,R2;"
-        "VMOV    D12,R2,R2;"
-        "VMOV    D13,R2,R2;"
-        "VMOV    D14,R2,R2;"
-        "VMOV    D15,R2,R2;"
-        //Initialise D32 registers to 0
-        "VMOV    D16,R2,R2;"
-        "VMOV    D17,R2,R2;"
-        "VMOV    D18,R2,R2;"
-        "VMOV    D19,R2,R2;"
-        "VMOV    D20,R2,R2;"
-        "VMOV    D21,R2,R2;"
-        "VMOV    D22,R2,R2;"
-        "VMOV    D23,R2,R2;"
-        "VMOV    D24,R2,R2;"
-        "VMOV    D25,R2,R2;"
-        "VMOV    D26,R2,R2;"
-        "VMOV    D27,R2,R2;"
-        "VMOV    D28,R2,R2;"
-        "VMOV    D29,R2,R2;"
-        "VMOV    D30,R2,R2;"
-        "VMOV    D31,R2,R2;"
-
-        //Initialise FPSCR to a known state
-        "VMRS    R2,FPSCR;"
-        "LDR     R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        "AND     R2,R2,R3;"
-        "VMSR    FPSCR,R2;"
-
-        //"BX      LR;"
-             :
-             :
-             :"r1", "r2", "r3");
-    return;
-}
-#else
-#endif
-
