Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/MANIFEST
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/MANIFEST	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/MANIFEST	(revision 307)
@@ -0,0 +1,20 @@
+PACKAGE asp3_arch_arm_gcc
+
+MANIFEST
+Makefile.chip
+chip_kernel.h
+chip_kernel.trb
+chip_kernel_impl.c
+chip_kernel_impl.h
+chip_rename.def
+chip_rename.h
+chip_stddef.h
+chip_sym.def
+chip_timer.c
+chip_timer.cfg
+chip_timer.h
+chip_unrename.h
+rza1.h
+scif.h
+tSCIF.c
+tSCIF.cdl
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/Makefile.chip
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/Makefile.chip	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/Makefile.chip	(revision 307)
@@ -0,0 +1,36 @@
+#
+#		Makefile ã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+#
+#  $Id: Makefile.chip 720 2016-04-01 22:16:17Z ertl-hiro $
+# 
+
+#
+#  ãããä¾å­é¨ãã£ã¬ã¯ããªåã®å®ç¾©
+#
+CHIPDIR = $(SRCDIR)/arch/$(CORE)_$(TOOL)/$(CHIP)
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+INCLUDES := $(INCLUDES) -I$(CHIPDIR)
+COPTS := $(COPTS) -mcpu=cortex-a9
+LDFLAGS := $(LDFLAGS) -mcpu=cortex-a9
+CDEFS := $(CDEFS) -D__TARGET_ARCH_ARM=7
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIRS := $(KERNEL_DIRS) $(CHIPDIR)
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS) gic_support.o
+KERNEL_COBJS := $(KERNEL_COBJS) chip_kernel_impl.o gic_kernel_impl.o \
+															chip_timer.o
+
+#
+#  ã³ã³ãã£ã®ã¥ã¬ã¼ã¿é¢ä¿ã®å¤æ°ã®å®ç¾©
+#
+CFG_TABS := $(CFG_TABS) --symval-table $(CHIPDIR)/chip_sym.def
+
+#
+#  ã³ã¢ä¾å­é¨
+#
+include $(SRCDIR)/arch/$(CORE)_$(TOOL)/common/Makefile.core
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.h	(revision 307)
@@ -0,0 +1,122 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_kernel.h 727 2016-04-03 00:47:42Z ertl-hiro $
+ */
+
+/*
+ *		kernel.hã®ã¿ã¼ã²ããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼kernel.hããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«
+ *  ããç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼ããã
+ *  åã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ããã«ä¾å­ãã¦ãããï¼
+ */
+
+#ifndef TOPPERS_CHIP_KERNEL_H
+#define TOPPERS_CHIP_KERNEL_H
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ã®ç¯å²
+ */
+#define TMIN_INTPRI		(-31)		/* å²è¾¼ã¿åªå
+åº¦ã®æå°å¤ï¼æé«å¤ï¼*/
+#define TMAX_INTPRI		(-1)		/* å²è¾¼ã¿åªå
+åº¦ã®æå¤§å¤ï¼æä½å¤ï¼*/
+
+/*
+ *  ã¿ã¼ã²ããå®ç¾©ã®å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§
+ */
+#define TA_NEGEDGE		0x04U		/* ãã¬ãã£ãã¨ãã¸ããªã¬ */
+#define TA_POSEDGE		0x08U		/* ãã¸ãã£ãã¨ãã¸ããªã¬ */
+#define TA_BOTHEDGE		0x0cU		/* ä¸¡ã¨ãã¸ããªã¬ */
+
+/*
+ *  ãµãã¼ãã§ããæ©è½ã®å®ç¾©
+ *
+ *  ena_intï¼dis_intã¨ãªã¼ãã©ã³ãã³ãã©ããµãã¼ããããã¨ãã§ããï¼
+ */
+#define TOPPERS_TARGET_SUPPORT_ENA_INT		/* ena_int */
+#define TOPPERS_TARGET_SUPPORT_DIS_INT		/* dis_int */
+#define TOPPERS_TARGET_SUPPORT_OVRHDR
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ã¿ã¤ãå¨æ
+ *
+ *  2^32 / 33.33â¦ãä¸¸ããå¤ã¨ããï¼
+ */
+#define TCYC_HRTCNT		128849019U
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ã«ã¦ã³ãå¤ã®é²ã¿å¹
+
+ */
+#define TSTEP_HRTCNT	1U
+
+/*
+ *  ãªã¼ãã©ã³ãã³ãã©ã®æ®ããã­ã»ããµæéã«æå®ã§ããæå¤§å¤
+ *
+ *  ãã®å¤ãOSã¿ã¤ãã¸ã®è¨­å®å¤ã«å¤æãã¦ã¿ã¤ãã«è¨­å®ããå¾ï¼ã¿ã¤ãã®ç¾
+ *  å¨å¤ãèª­ã¿åºãã¦Î¼ç§åä½ã«å¤æã§ããå¤ã¨ãã¦ããï¼ã¿ã¤ãã®ç¾å¨å¤ã
+ *  Î¼ç§åä½ã«å¤æããæã«34ãå ããããï¼ä»¥ä¸ã®æ¡ä»¶ãæºããæå¤§ã®å¤ã¨
+ *  ããï¼
+ *		(TMAX_OVRTIM * 33 + TMAX_OVRTIM / 3 + 1) + 34 < 2^32
+ */
+#define TMAX_OVRTIM		128849017U
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©
+ */
+#include "core_kernel.h"
+
+#endif /* TOPPERS_CHIP_KERNEL_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.trb
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.trb	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.trb	(revision 307)
@@ -0,0 +1,43 @@
+# -*- coding: utf-8 -*-
+# 
+#		ãã¹2ã®çæã¹ã¯ãªããã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+# 
+
+# 
+#  ä½¿ç¨ã§ããå²è¾¼ã¿çªå·ã¨ããã«å¯¾å¿ããå²è¾¼ã¿ãã³ãã©çªå·
+# 
+if $TOPPERS_RZA1H
+  $INTNO_VALID = [ *(0..586) ]
+else
+  $INTNO_VALID = [ *(0..537) ]
+end
+$INHNO_VALID = $INTNO_VALID
+
+#
+#  ã¿ã¼ã²ããå®ç¾©ã®å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§
+#
+$TARGET_INTATR = $TA_NEGEDGE|$TA_POSEDGE|$TA_BOTHEDGE
+
+# 
+#  çæã¹ã¯ãªããã®ã³ã¢ä¾å­é¨
+# 
+IncludeTrb("core_kernel.trb")
+
+#
+#  å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§ã«é¢ããã¿ã¼ã²ããä¾å­ã®ã¨ã©ã¼ãã§ãã¯
+#
+$cfgData[:CFG_INT].each do |key, params|
+  if $INTNO_IRQ0 <= key && key <= $INTNO_IRQ7
+    # IRQå²è¾¼ã¿ã®å ´å
+    #ï¼TA_EDGEãã»ããããã¦ããå ´åï¼
+    if (params[:intatr] & $TA_EDGE) != 0
+      error_illegal_sym("E_RSATR", params, :intatr, :intno)
+    end
+  else
+    # ãã®ä»ã®å²è¾¼ã¿ã®å ´å
+    #ï¼TA_NEGEDGEï¼TA_POSEDGEï¼TARGET_BOTHEDGEãã»ããããã¦ããå ´åï¼
+    if (params[:intatr] & $TARGET_INTATR) != 0
+      error_illegal_sym("E_RSATR", params, :intatr, :intno)
+    end
+  end
+end
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.c
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.c	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.c	(revision 307)
@@ -0,0 +1,220 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_kernel_impl.c 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		ã«ã¼ãã«ã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ */
+
+#include "kernel_impl.h"
+#include "interrupt.h"
+
+/*
+ *  ãããä¾å­ã®åæå
+ */
+void
+chip_initialize(void)
+{
+	/*
+	 *  ã­ã£ãã·ã¥ããã£ã¹ã¨ã¼ãã«
+	 */
+	arm_disable_cache();
+
+	/*
+	 *  ã³ã¢ä¾å­ã®åæå
+	 */
+	core_initialize();
+
+	/*
+	 *  ã­ã£ãã·ã¥ãã¤ãã¼ãã«
+	 */
+	arm_enable_cache();
+
+	/*
+	 *  GICã®ãã£ã¹ããªãã¥ã¼ã¿ã®åæå
+	 */
+	gicd_initialize();
+
+	/*
+	 *  GICã®CPUã¤ã³ã¿ãã§ã¼ã¹ã®åæå
+	 */
+	gicc_initialize();
+
+	/*
+	 *  åå²äºæ¸¬ã®ç¡å¹åã¨ã¤ãã¼ãã«
+	 */
+	arm_invalidate_bp();
+	arm_enable_bp();
+}
+
+/*
+ *  ãããä¾å­é¨ã®çµäºå¦ç
+ */
+void
+chip_terminate(void)
+{
+	extern void    software_term_hook(void);
+	void (*volatile fp)(void) = software_term_hook;
+
+	/*
+	 *  software_term_hookã¸ã®ãã¤ã³ã¿ãï¼ä¸æ¦volatileæå®ã®ããfpã«ä»£
+	 *  å
+¥ãã¦ããä½¿ãã®ã¯ï¼0ã¨ã®æ¯è¼ãæé©åã§åé¤ãããªãããã«ããã
+	 *  ãã§ããï¼
+	 */
+	if (fp != 0) {
+		(*fp)();
+	}
+
+	/*
+	 *  GICã®CPUã¤ã³ã¿ãã§ã¼ã¹ã®çµäºå¦ç
+	 */
+	gicc_terminate();
+
+	/*
+	 *  GICã®ãã£ã¹ããªãã¥ã¼ã¿ã®çµäºå¦ç
+	 */
+	gicd_terminate();
+
+	/*
+	 *  ã³ã¢ä¾å­ã®çµäºå¦ç
+	 */
+	core_terminate();
+}
+
+/*
+ *  å²è¾¼ã¿è¦æ±ã©ã¤ã³ã®å±æ§ã®è¨­å®
+ *
+ *  ASPã«ã¼ãã«ã§ã®å©ç¨ãæ³å®ãã¦ï¼ãã©ã¡ã¼ã¿ã¨ã©ã¼ã¯ã¢ãµã¼ã·ã§ã³ã§ãã§ã
+ *  ã¯ãã¦ããï¼
+ */
+Inline void
+config_int(INTNO intno, ATR intatr, PRI intpri)
+{
+	assert(VALID_INTNO(intno));
+	assert(TMIN_INTPRI <= intpri && intpri <= TMAX_INTPRI);
+
+	/*
+	 *  å²è¾¼ã¿ãç¦æ­¢
+	 *
+	 *  å²è¾¼ã¿ãåãä»ããã¾ã¾ï¼ã¬ãã«ããªã¬ï¼ã¨ãã¸ããªã¬ã®è¨­å®ãï¼å²
+	 *  è¾¼ã¿åªå
+åº¦ã®è¨­å®ãè¡ãã®ã¯å±éºãªããï¼å²è¾¼ã¿å±æ§ã«ãããããï¼
+	 *  ä¸æ¦ãã¹ã¯ããï¼
+	 */
+	disable_int(intno);
+
+	/*
+	 *  å²è¾¼ã¿ãã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³
+	 */
+#ifdef TOPPERS_SAFEG_SECURE
+	gicd_config_group(intno, 1U);
+#endif /* TOPPERS_SAFEG_SECURE */
+
+	if (INTNO_IRQ0 <= intno && intno <= INTNO_IRQ7) {
+		uint16_t	reg;
+
+		reg = sil_reh_mem(RZA1_ICR1);
+		reg &= ~(0x03U << ((intno - INTNO_IRQ0) * 2));
+		reg |= ((intatr >> 2) << ((intno - INTNO_IRQ0) * 2));
+		sil_wrh_mem(RZA1_ICR1, reg);
+	}
+
+	if ((intatr & TA_EDGE) != 0U) {
+#ifdef GIC_ARM11MPCORE
+		gicd_config(intno, GICD_ICFGRn_EDGE|GICD_ICFGRn_1_N);
+#else /* GIC_ARM11MPCORE */
+		gicd_config(intno, GICD_ICFGRn_EDGE);
+#endif /* GIC_ARM11MPCORE */
+		clear_int(intno);
+	}
+	else {
+#ifdef GIC_ARM11MPCORE
+		gicd_config(intno, GICD_ICFGRn_LEVEL|GICD_ICFGRn_1_N);
+#else /* GIC_ARM11MPCORE */
+		gicd_config(intno, GICD_ICFGRn_LEVEL);
+#endif /* GIC_ARM11MPCORE */
+	}
+
+	/*
+	 *  å²è¾¼ã¿åªå
+åº¦ã¨ã¿ã¼ã²ãããã­ã»ããµãè¨­å®
+	 */
+	gicd_set_priority(intno, INT_IPM(intpri));
+	gicd_set_target(intno, 1U << arm_prc_index());
+
+	/*
+	 * å²è¾¼ã¿ãè¨±å¯
+	 */
+	if ((intatr & TA_ENAINT) != 0U) {
+		enable_int(intno);
+	}
+}
+
+/*
+ *  å²è¾¼ã¿ç®¡çæ©è½ã®åæå
+ */
+void
+initialize_interrupt(void)
+{
+	uint_t			i;
+	const INTINIB	*p_intinib;
+
+	for (i = 0; i < tnum_cfg_intno; i++) {
+		p_intinib = &(intinib_table[i]);
+		config_int(p_intinib->intno, p_intinib->intatr, p_intinib->intpri);
+	}
+}
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.h	(revision 307)
@@ -0,0 +1,112 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_kernel_impl.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		kernel_impl.hã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼target_kernel_impl.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
+ *  ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CHIP_KERNEL_IMPL_H
+#define TOPPERS_CHIP_KERNEL_IMPL_H
+
+/*
+ *  RZ/A1ã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+ */
+#include "rza1.h"
+
+/*
+ *  MMUã®ä½¿ç¨ã«é¢ããè¨­å®
+ */
+#define USE_ARM_MMU
+#define USE_ARM_SSECTION
+
+/*
+ *  GICã®ãã£ã¹ããªãã¥ã¼ã¿ã®å²è¾¼ã¿ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã¬ã¸ã¹ã¿ã«è¨­å®
+ *  ããå¤ã«é¢ããå®ç¾©
+ */
+#define GIC_ARM11MPCORE
+
+/*
+ *  GICä¾å­é¨ã®å²è¾¼ã¿ç®¡çæ©è½ã®åæåã¯ä½¿ç¨ããªãï¼
+ */
+#define OMIT_GIC_INITIALIZE_INTERRUPT
+
+/*
+ *  GICã«é¢ããå®ç¾©ï¼ã³ã¢ã§å
+±éãªå®ç¾©
+ *
+ *  core_kernel_impl.hã¯ï¼gic_kernel_impl.hããã¤ã³ã¯ã«ã¼ããããï¼
+ */
+#include "gic_kernel_impl.h"
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ãããä¾å­ã®åæå
+ */
+extern void chip_initialize(void);
+
+/*
+ *  ãããä¾å­ã®çµäºå¦ç
+ */
+extern void chip_terminate(void);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CHIP_KERNEL_IMPL_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.def
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.def	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.def	(revision 307)
@@ -0,0 +1,17 @@
+# chip_kernel_impl.c
+chip_initialize
+chip_terminate
+
+# chip_timer.c
+target_hrt_initialize
+target_hrt_terminate
+target_hrt_set_event
+target_hrt_raise_event
+target_hrt_handler
+target_ovrtimer_initialize
+target_ovrtimer_terminate
+target_ovrtimer_stop
+target_ovrtimer_get_current
+target_ovrtimer_handler
+
+INCLUDE "core"
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.h	(revision 307)
@@ -0,0 +1,29 @@
+/* This file is generated from chip_rename.def by genrename. */
+
+#ifndef TOPPERS_CHIP_RENAME_H
+#define TOPPERS_CHIP_RENAME_H
+
+/*
+ *  chip_kernel_impl.c
+ */
+#define chip_initialize				_kernel_chip_initialize
+#define chip_terminate				_kernel_chip_terminate
+
+/*
+ *  chip_timer.c
+ */
+#define target_hrt_initialize		_kernel_target_hrt_initialize
+#define target_hrt_terminate		_kernel_target_hrt_terminate
+#define target_hrt_set_event		_kernel_target_hrt_set_event
+#define target_hrt_raise_event		_kernel_target_hrt_raise_event
+#define target_hrt_handler			_kernel_target_hrt_handler
+#define target_ovrtimer_initialize	_kernel_target_ovrtimer_initialize
+#define target_ovrtimer_terminate	_kernel_target_ovrtimer_terminate
+#define target_ovrtimer_stop		_kernel_target_ovrtimer_stop
+#define target_ovrtimer_get_current	_kernel_target_ovrtimer_get_current
+#define target_ovrtimer_handler		_kernel_target_ovrtimer_handler
+
+
+#include "core_rename.h"
+
+#endif /* TOPPERS_CHIP_RENAME_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.c
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.c	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.c	(revision 307)
@@ -0,0 +1,254 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: chip_serial.c 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *  ã·ãªã¢ã«I/Oããã¤ã¹ï¼SCIFï¼ãã©ã¤ãï¼RZ/A1ç¨ï¼
+ */
+
+#include <kernel.h>
+#include <t_syslog.h>
+#include "chip_serial.h"
+#include "rza1.h"
+
+static INTNO const intno_sio_bri[TNUM_SIOP] = {
+	INTNO_SCIF_BRI_1,
+	INTNO_SCIF_BRI_2,
+	INTNO_SCIF_BRI_3,
+	INTNO_SCIF_BRI_4,
+	INTNO_SCIF_BRI_5,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_BRI_6,
+	INTNO_SCIF_BRI_7,
+	INTNO_SCIF_BRI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+static INTNO const intno_sio_eri[TNUM_SIOP] = {
+	INTNO_SCIF_ERI_1,
+	INTNO_SCIF_ERI_2,
+	INTNO_SCIF_ERI_3,
+	INTNO_SCIF_ERI_4,
+	INTNO_SCIF_ERI_5,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_ERI_6,
+	INTNO_SCIF_ERI_7,
+	INTNO_SCIF_ERI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+static INTNO const intno_sio_rxi[TNUM_SIOP] = {
+	INTNO_SCIF_RXI_1,
+	INTNO_SCIF_RXI_2,
+	INTNO_SCIF_RXI_3,
+	INTNO_SCIF_RXI_4,
+	INTNO_SCIF_RXI_5,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_RXI_6,
+	INTNO_SCIF_RXI_7,
+	INTNO_SCIF_RXI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+static INTNO const intno_sio_txi[TNUM_SIOP] = {
+	INTNO_SCIF_TXI_1,
+	INTNO_SCIF_TXI_2,
+	INTNO_SCIF_TXI_3,
+	INTNO_SCIF_TXI_4,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_TXI_5,
+	INTNO_SCIF_TXI_6,
+	INTNO_SCIF_TXI_7,
+	INTNO_SCIF_TXI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãIDããå²è¾¼ã¿çªå·ãåãåºãããã®ãã¯ã­
+ */
+#define INDEX_SIOP(siopid)           ((uint_t)((siopid) - 1))
+#define get_intno_sio_bri(siopid)    (intno_sio_bri[INDEX_SIOP(siopid)])
+#define get_intno_sio_eri(siopid)    (intno_sio_eri[INDEX_SIOP(siopid)])
+#define get_intno_sio_rxi(siopid)    (intno_sio_rxi[INDEX_SIOP(siopid)])
+#define get_intno_sio_txi(siopid)    (intno_sio_txi[INDEX_SIOP(siopid)])
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+void
+sio_initialize(intptr_t exinf)
+{
+	scif_initialize();
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+SIOPCB *
+sio_opn_por(ID siopid, intptr_t exinf)
+{
+	SIOPCB    *p_siopcb;
+	ER        ercd;
+
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ããã¹ã¯ããï¼
+	 */
+	ercd = dis_int(get_intno_sio_rxi(siopid));
+	assert(ercd == E_OK);
+	ercd = dis_int(get_intno_sio_txi(siopid));
+	assert(ercd == E_OK);
+
+	/*
+	 *  ããã¤ã¹ä¾å­ã®ãªã¼ãã³å¦çï¼
+	 */
+	p_siopcb = scif_opn_por(siopid, exinf);
+
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ã®ãã¹ã¯ãè§£é¤ããï¼
+	 */
+	ercd = ena_int(get_intno_sio_rxi(siopid));
+	assert(ercd == E_OK);
+	ercd = ena_int(get_intno_sio_txi(siopid));
+	assert(ercd == E_OK);
+
+	return(p_siopcb);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+void
+sio_cls_por(SIOPCB *p_siopcb)
+{
+	ER ercd;
+	ID siopid;
+
+	/*
+	 *  ã·ãªã¢ã«I/Oãã¼ãIDã®åå¾
+	 */
+	siopid = scif_get_siopid(p_siopcb);
+
+	/*
+	 *  ããã¤ã¹ä¾å­ã®ã¯ã­ã¼ãºå¦çï¼
+	 */
+	scif_cls_por(p_siopcb);
+
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ããã¹ã¯ããï¼
+	 */
+	ercd = dis_int(intno_sio_rxi[siopid]);
+	assert(ercd == E_OK);
+	ercd = dis_int(intno_sio_txi[siopid]);
+	assert(ercd == E_OK);
+}
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©
+ */
+void sio_isr_rxi(intptr_t exinf)
+{
+    scif_rx_isr(exinf);
+}
+void sio_isr_txi(intptr_t exinf)
+{
+    scif_tx_isr(exinf);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+bool_t sio_snd_chr(SIOPCB *siopcb, char c)
+{
+	return(scif_snd_chr(siopcb, c));
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+int_t sio_rcv_chr(SIOPCB *siopcb)
+{
+	return(scif_rcv_chr(siopcb));
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+	scif_ena_cbr(siopcb, cbrtn);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+	scif_dis_cbr(siopcb, cbrtn);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+void scif_irdy_snd(intptr_t exinf)
+{
+	sio_irdy_snd(exinf);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+void scif_irdy_rcv(intptr_t exinf)
+{
+	sio_irdy_rcv(exinf);
+}
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.h	(revision 307)
@@ -0,0 +1,202 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: chip_serial.h 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *  ã·ãªã¢ã«I/Oããã¤ã¹ï¼SIOï¼ãã©ã¤ãï¼RZ/A1ç¨ï¼
+ */
+
+#ifndef TOPPERS_CHIP_SERIAL_H
+#define TOPPERS_CHIP_SERIAL_H
+
+#include "scif.h"
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©ã®ãã¯ã¿çªå·
+ */
+#define INTNO_SCIF_BRI_1        INTNO_SCIF0_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_1        INTNO_SCIF0_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_1        INTNO_SCIF0_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_1        INTNO_SCIF0_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_1
+#define INTPRI_SIO_1            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_1 */
+#define INTATR_SIO_1            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_2        INTNO_SCIF1_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_2        INTNO_SCIF1_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_2        INTNO_SCIF1_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_2        INTNO_SCIF1_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_2
+#define INTPRI_SIO_2            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_2 */
+#define INTATR_SIO_2            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_3        INTNO_SCIF2_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_3        INTNO_SCIF2_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_3        INTNO_SCIF2_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_3        INTNO_SCIF2_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_3
+#define INTPRI_SIO_3            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_3 */
+#define INTATR_SIO_3            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_4        INTNO_SCIF3_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_4        INTNO_SCIF3_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_4        INTNO_SCIF3_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_4        INTNO_SCIF3_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_4
+#define INTPRI_SIO_4            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_4 */
+#define INTATR_SIO_4            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_5        INTNO_SCIF4_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_5        INTNO_SCIF4_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_5        INTNO_SCIF4_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_5        INTNO_SCIF4_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_5
+#define INTPRI_SIO_5            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_5 */
+#define INTATR_SIO_5            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_6        INTNO_SCIF5_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_6        INTNO_SCIF5_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_6        INTNO_SCIF5_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_6        INTNO_SCIF5_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_6
+#define INTPRI_SIO_6            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_6 */
+#define INTATR_SIO_6            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_7        INTNO_SCIF6_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_7        INTNO_SCIF6_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_7        INTNO_SCIF6_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_7        INTNO_SCIF6_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_7
+#define INTPRI_SIO_7            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_7 */
+#define INTATR_SIO_7            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_8        INTNO_SCIF7_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_8        INTNO_SCIF7_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_8        INTNO_SCIF7_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_8        INTNO_SCIF7_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_8
+#define INTPRI_SIO_8            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_8 */
+#define INTATR_SIO_8            0U        /* å²è¾¼ã¿å±æ§ */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+extern void sio_initialize(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+extern SIOPCB *sio_opn_por(ID siopid, intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+extern void sio_cls_por(SIOPCB *p_siopcb);
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©
+ */
+extern void sio_isr_rxi(intptr_t exinf);
+extern void sio_isr_txi(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+extern bool_t sio_snd_chr(SIOPCB *siopcb, char c);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+extern int_t sio_rcv_chr(SIOPCB *siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+extern void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+extern void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_snd(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_rcv(intptr_t exinf);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CHIP_SERIAL_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_stddef.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_stddef.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_stddef.h	(revision 307)
@@ -0,0 +1,86 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_stddef.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		t_stddef.hã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼target_stddef.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯ã«ã¼ã
+ *  ããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ããç´æ¥ã¤
+ *  ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CHIP_STDDEF_H
+#define TOPPERS_CHIP_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_RZA1					/* ãããç¥ç§° */
+
+/*
+ *  ããããéå®ãããã¯ã­ãå®ç¾©ããã¦ãããã®ãã§ãã¯
+ */
+#if !defined(TOPPERS_RZA1H) && !defined(TOPPERS_RZA1L)
+#error Either TOPPERS_RZA1H or TOPPERS_RZA1L must be defined.
+#endif
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©
+ */
+#include "core_stddef.h"
+
+#endif /* TOPPERS_CHIP_STDDEF_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_sym.def
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_sym.def	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_sym.def	(revision 307)
@@ -0,0 +1,7 @@
+TARGET_RZA1H,true,bool,defined(TARGET_RZA1H)
+TARGET_RZA1L,true,bool,defined(TARGET_RZA1L)
+TA_NEGEDGE
+TA_POSEDGE
+TA_BOTHEDGE
+INTNO_IRQ0
+INTNO_IRQ7
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.c
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.c	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.c	(revision 307)
@@ -0,0 +1,282 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: chip_timer.c 731 2016-04-03 03:07:35Z ertl-hiro $
+ */
+
+/*
+ *		ã¿ã¤ããã©ã¤ãï¼RZ/A1 OSã¿ã¤ãç¨ï¼
+ *
+ *  RZ/A1ã¯2ãã£ã³ãã«ã®OSã¿ã¤ããæã¤ãï¼ãã®å
+ã®1ã¤ãç¨ãã¦é«åè§£è½ã¿
+ *  ã¤ããï¼ãã1ã¤ãç¨ãã¦ãªã¼ãã©ã³ã¿ã¤ããå®ç¾ããï¼
+ */
+
+#include "kernel_impl.h"
+#include "time_event.h"
+#ifdef TOPPERS_SUPPORT_OVRHDR
+#include "overrun.h"
+#endif /* TOPPERS_SUPPORT_OVRHDR */
+#include "target_timer.h"
+#include <sil.h>
+#include "rza1.h"
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
+ */
+Inline void
+target_hrt_int_clear()
+{
+	gicd_clear_pending(INTNO_OSTM0);
+}
+
+/*
+ *  ã¿ã¤ãã®èµ·åå¦ç
+ */
+void
+target_hrt_initialize(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããããªã¼ã©ã³ãã³ã°ã³ã³ãã¢ã¢ã¼ãã«è¨­å®ããï¼
+	 */
+	sil_wrb_mem(OSTM_CTL(OSTM0_BASE), OSTM_CTL_FRCMP);
+
+	/*
+	 *  OSã¿ã¤ãã®è¨­å®å¤ãæå¤§å¤ã«ãã¦ããï¼
+	 */
+	sil_wrw_mem(OSTM_CMP(OSTM0_BASE), 0xffffffff);
+
+	/*
+	 *  OSã¿ã¤ããåä½éå§ããï¼
+	 */
+	sil_wrb_mem(OSTM_TS(OSTM0_BASE), OSTM_TS_START);
+
+	/*
+	 *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_hrt_int_clear();
+}
+
+/*
+ *  ã¿ã¤ãã®åæ­¢å¦ç
+ */
+void
+target_hrt_terminate(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããåæ­¢ããï¼
+	 */
+	sil_wrb_mem(OSTM_TT(OSTM0_BASE), OSTM_TT_STOP);
+
+	/*
+	 *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_hrt_int_clear();
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã¸ã®å²è¾¼ã¿ã¿ã¤ãã³ã°ã®è¨­å®
+ */
+void
+target_hrt_set_event(HRTCNT hrtcnt)
+{
+	uint32_t	cnt = hrtcnt * 33 + hrtcnt / 3 + 1;
+	uint32_t	current;
+
+	/*
+	 *  ç¾å¨ã®ã«ã¦ã³ãå¤ãèª­ã¿ï¼hrtcntå¾ã«å²è¾¼ã¿ãçºçããããã«è¨­å®ããï¼
+	 */
+	current = sil_rew_mem(OSTM_CNT(OSTM0_BASE));
+	sil_wrw_mem(OSTM_CMP(OSTM0_BASE), current + cnt);
+
+	/*
+	 *  ä¸ã§ç¾å¨ã®ã«ã¦ã³ãå¤ãèª­ãã§ä»¥éã«ï¼cntä»¥ä¸ã«ã¦ã³ãã¢ãããã¦ã
+	 *  ãå ´åã«ã¯ï¼å²è¾¼ã¿ãçºçãããï¼
+	 */
+	if (sil_rew_mem(OSTM_CNT(OSTM0_BASE)) - current >= cnt) {
+		gicd_set_pending(INTNO_OSTM0);
+	}
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ã®è¦æ±
+ */
+void
+target_hrt_raise_event(void)
+{
+	gicd_set_pending(INTNO_OSTM0);
+}
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+void
+target_hrt_handler(void)
+{
+	/*
+	 *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_hrt_int_clear();
+
+	/*
+	 *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ãå¦çããï¼
+	 */
+	signal_time();
+}
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ããã©ã¤ã
+ */
+#ifdef TOPPERS_SUPPORT_OVRHDR
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
+ */
+Inline void
+target_ovrtimer_int_clear()
+{
+	gicd_clear_pending(INTNO_OSTM1);
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæåå¦ç
+ */
+void
+target_ovrtimer_initialize(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããã¤ã³ã¿ã¼ãã«ã¿ã¤ãã¢ã¼ãã«è¨­å®ããï¼
+	 */
+	sil_wrb_mem(OSTM_CTL(OSTM1_BASE), OSTM_CTL_INTERVAL);
+
+	/*
+	 *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_ovrtimer_int_clear();
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢å¦ç
+ */
+void
+target_ovrtimer_terminate(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããåæ­¢ããï¼
+	 */
+	sil_wrb_mem(OSTM_TT(OSTM1_BASE), OSTM_TT_STOP);
+
+	/*
+	 *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_ovrtimer_int_clear();
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢
+ */
+PRCTIM
+target_ovrtimer_stop(void)
+{
+	uint32_t	cnt;
+
+	/*
+	 *  OSã¿ã¤ããåæ­¢ããï¼
+	 */
+	sil_wrb_mem(OSTM_TT(OSTM1_BASE), OSTM_TT_STOP);
+
+	if (gicd_probe_pending(INTNO_OSTM1)) {
+		/*
+		 *  å²è¾¼ã¿è¦æ±ãçºçãã¦ããå ´å
+		 */
+		target_ovrtimer_int_clear();
+		return(0U);
+	}
+	else {
+		cnt = sil_rew_mem(OSTM_CNT(OSTM1_BASE));
+		return((PRCTIM)((cnt + 34) / 5 * 3 / 20));
+	}
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®ç¾å¨å¤ã®èª­åºã
+ */
+PRCTIM
+target_ovrtimer_get_current(void)
+{
+	uint32_t	cnt;
+
+	if (gicd_probe_pending(INTNO_OSTM1)) {
+		/*
+		 *  å²è¾¼ã¿è¦æ±ãçºçãã¦ããå ´å
+		 */
+		return(0U);
+	}
+	else {
+		cnt = sil_rew_mem(OSTM_CNT(OSTM1_BASE));
+		return((PRCTIM)((cnt + 34) / 5 * 3 / 20));
+	}
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ *
+ *  ãã®ã«ã¼ãã³ã«æ¥ãã¾ã§ã«ï¼target_ovrtimer_stopãå¼ã°ãã¦ããããï¼
+ *  OSã¿ã¤ããåæ­¢ããå¿
+è¦ã¯ãªãï¼
+ */
+void
+target_ovrtimer_handler(void)
+{
+	call_ovrhdr();					/* ãªã¼ãã©ã³ãã³ãã©ã®èµ·åå¦ç */
+}
+
+#endif /* TOPPERS_SUPPORT_OVRHDR */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.cfg
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.cfg	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.cfg	(revision 307)
@@ -0,0 +1,23 @@
+/*
+ *		ã¿ã¤ããã©ã¤ãã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ *
+ *  $Id: chip_timer.cfg 727 2016-04-03 00:47:42Z ertl-hiro $
+ */
+
+/*
+ *  é«åè§£è½ã¿ã¤ããã©ã¤ã
+ */
+ATT_INI({ TA_NULL, 0, _kernel_target_hrt_initialize });
+ATT_TER({ TA_NULL, 0, _kernel_target_hrt_terminate });
+CFG_INT(INTNO_TIMER, { TA_ENAINT|INTATR_TIMER, INTPRI_TIMER });
+DEF_INH(INHNO_TIMER, { TA_NULL, _kernel_target_hrt_handler });
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ããã©ã¤ã
+ */
+#ifdef TOPPERS_SUPPORT_OVRHDR
+ATT_INI({ TA_NULL, 0, _kernel_target_ovrtimer_initialize });
+ATT_TER({ TA_NULL, 0, _kernel_target_ovrtimer_terminate });
+CFG_INT(INTNO_OVRTIMER, { TA_ENAINT|INTATR_OVRTIMER, INTPRI_OVRTIMER });
+DEF_INH(INHNO_OVRTIMER, { TA_NULL, _kernel_target_ovrtimer_handler });
+#endif /* TOPPERS_SUPPORT_OVRHDR */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.h	(revision 307)
@@ -0,0 +1,219 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2005-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: chip_timer.h 742 2016-04-07 13:11:22Z ertl-hiro $
+ */
+
+/*
+ *		ã¿ã¤ããã©ã¤ãï¼RZ/A1 OSã¿ã¤ãç¨ï¼
+ *
+ *  RZ/A1ã¯2ãã£ã³ãã«ã®OSã¿ã¤ããæã¤ãï¼ãã®å
+ã®1ã¤ãç¨ãã¦é«åè§£è½ã¿
+ *  ã¤ããï¼ãã1ã¤ãç¨ãã¦ãªã¼ãã©ã³ã¿ã¤ããå®ç¾ããï¼
+ */
+
+#ifndef TOPPERS_CHIP_TIMER_H
+#define TOPPERS_CHIP_TIMER_H
+
+#include <sil.h>
+#include "rza1.h"
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+#define INHNO_TIMER		INTNO_OSTM0			/* å²è¾¼ã¿ãã³ãã©çªå· */
+#define INTNO_TIMER		INTNO_OSTM0			/* å²è¾¼ã¿çªå· */
+#define INTPRI_TIMER	(TMAX_INTPRI - 1)	/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_TIMER	TA_EDGE				/* å²è¾¼ã¿å±æ§ */
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+#ifdef TOPPERS_SUPPORT_OVRHDR
+#define INHNO_OVRTIMER		INTNO_OSTM1			/* å²è¾¼ã¿ãã³ãã©çªå· */
+#define INTNO_OVRTIMER		INTNO_OSTM1			/* å²è¾¼ã¿çªå· */
+#define INTPRI_OVRTIMER		TMAX_INTPRI			/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_OVRTIMER		TA_EDGE				/* å²è¾¼ã¿å±æ§ */
+#endif /* TOPPERS_SUPPORT_OVRHDR */
+
+/*
+ *  OSã¿ã¤ãã®å¨æ³¢æ°ã®æ³å®å¤ã®ãã§ãã¯
+ *
+ *  ç¾å¨ã®å®è£
+ã¯ï¼ã¯ã­ãã¯ã33.33â¦MHzã®å ´åã®ã¿ã«å¯¾å¿ãã¦ããï¼
+ */
+#if OSTM_CLK != 33333333UL
+#error Unsupported OS time clock.
+#endif /* OSTM_CLK != 33333333UL */
+
+/*
+ *  OSã¿ã¤ãã¬ã¸ã¹ã¿ã®çªå°ã®å®ç¾©
+ */
+#define OSTM_CMP(base)		((uint32_t *)(base + 0x00U))
+#define OSTM_CNT(base)		((uint32_t *)(base + 0x04U))
+#define OSTM_TE(base)		((uint8_t *)(base + 0x10U))
+#define OSTM_TS(base)		((uint8_t *)(base + 0x14U))
+#define OSTM_TT(base)		((uint8_t *)(base + 0x18U))
+#define OSTM_CTL(base)		((uint8_t *)(base + 0x20U))
+
+/*
+ *  OSã¿ã¤ã ã«ã¦ã³ãéå§ããªã¬ã¬ã¸ã¹ã¿ã®è¨­å®å¤ã®å®ç¾©
+ */
+#define OSTM_TS_START		0x01U
+
+/*
+ *  OSã¿ã¤ã ã«ã¦ã³ãåæ­¢ããªã¬ã¬ã¸ã¹ã¿ã®è¨­å®å¤ã®å®ç¾©
+ */
+#define OSTM_TT_STOP		0x01U
+
+/*
+ *  OSã¿ã¤ã å¶å¾¡ã¬ã¸ã¹ã¿ã®è¨­å®å¤ã®å®ç¾©
+ */
+#define OSTM_CTL_INTERVAL	0x00U		/* ã¤ã³ã¿ã¼ãã«ã¿ã¤ãã¢ã¼ã */
+#define OSTM_CTL_FRCMP		0x02U		/* ããªã¼ã©ã³ãã³ã°ã³ã³ãã¢ã¢ã¼ã */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®èµ·åå¦ç
+ */
+extern void	target_hrt_initialize(intptr_t exinf);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®åæ­¢å¦ç
+ */
+extern void	target_hrt_terminate(intptr_t exinf);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ç¾å¨ã®ã«ã¦ã³ãå¤ã®èª­åºã
+ */
+Inline HRTCNT
+target_hrt_get_current(void)
+{
+	uint32_t	cnt, cnt1;
+
+	cnt = sil_rew_mem(OSTM_CNT(OSTM0_BASE));
+
+	/* Î¼ç§åä½ã«å¤æï¼ã¯ã­ãã¯ã33.33â¦MHzã§ããåæï¼*/
+	cnt1 = cnt / 1000000000;
+	return((HRTCNT)((cnt - cnt1 * 999999999) * 3 / 100 + cnt1 * 30000000));
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã¸ã®å²è¾¼ã¿ã¿ã¤ãã³ã°ã®è¨­å®
+ *
+ *  é«åè§£è½ã¿ã¤ããï¼hrtcntã§æå®ããå¤ã«ã¦ã³ãã¢ãããããå²è¾¼ã¿ãçº
+ *  çãããããã«è¨­å®ããï¼
+ */
+extern void target_hrt_set_event(HRTCNT hrtcnt);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ã®è¦æ±
+ */
+extern  void target_hrt_raise_event(void);
+
+/*
+ *  å²è¾¼ã¿ã¿ã¤ãã³ã°ã«æå®ããæå¤§å¤
+ */
+#define HRTCNT_BOUND	100000002U
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+extern void	target_hrt_handler(void);
+
+#ifdef TOPPERS_SUPPORT_OVRHDR
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæåå¦ç
+ */
+extern void target_ovrtimer_initialize(intptr_t exinf);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢å¦ç
+ */
+extern void target_ovrtimer_terminate(intptr_t exinf);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åä½éå§
+ */
+Inline void
+target_ovrtimer_start(PRCTIM ovrtim)
+{
+	uint32_t	cnt = ovrtim * 33 + ovrtim / 3 + 1;
+
+	sil_wrw_mem(OSTM_CMP(OSTM1_BASE), cnt);
+	sil_wrb_mem(OSTM_TS(OSTM1_BASE), OSTM_TS_START);
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢
+ */
+extern PRCTIM target_ovrtimer_stop(void);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®ç¾å¨å¤ã®èª­åºã
+ */
+extern PRCTIM target_ovrtimer_get_current(void);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+extern void	target_ovrtimer_handler(void);
+
+#endif /* TOPPERS_SUPPORT_OVRHDR */
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CHIP_TIMER_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_unrename.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_unrename.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_unrename.h	(revision 307)
@@ -0,0 +1,30 @@
+/* This file is generated from chip_rename.def by genrename. */
+
+/* This file is included only when chip_rename.h has been included. */
+#ifdef TOPPERS_CHIP_RENAME_H
+#undef TOPPERS_CHIP_RENAME_H
+
+/*
+ *  chip_kernel_impl.c
+ */
+#undef chip_initialize
+#undef chip_terminate
+
+/*
+ *  chip_timer.c
+ */
+#undef target_hrt_initialize
+#undef target_hrt_terminate
+#undef target_hrt_set_event
+#undef target_hrt_raise_event
+#undef target_hrt_handler
+#undef target_ovrtimer_initialize
+#undef target_ovrtimer_terminate
+#undef target_ovrtimer_stop
+#undef target_ovrtimer_get_current
+#undef target_ovrtimer_handler
+
+
+#include "core_unrename.h"
+
+#endif /* TOPPERS_CHIP_RENAME_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/rza1.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/rza1.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/rza1.h	(revision 307)
@@ -0,0 +1,317 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: rza1.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		RZ/A1ã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+ */
+
+#ifndef TOPPERS_RZA1_H
+#define TOPPERS_RZA1_H
+
+#include <sil.h>
+
+/*
+ *  åã­ã£ã¹ããè¡ããã¯ã­ã®å®ç¾©
+ */
+#ifndef CAST
+#define CAST(type, val)		((type)(val))
+#endif /* CAST */
+
+/*
+ *  ã¡ã¢ãªãããã®å®ç¾©ï¼MMUã«è¨­å®ããããã«å¿
+è¦ï¼
+ */
+#define SPI_ADDR		0x18000000		/* ã·ãªã¢ã«ãã©ãã·ã¥ã¡ã¢ãª */
+#define SPI_SIZE		0x08000000		/* 128MB */
+
+#define SRAM_ADDR		0x20000000		/* å
+èµRAM */
+#ifdef TOPPERS_RZA1H
+#define SRAM_SIZE		0x00a00000		/* 10MB */
+#else /* TOPPERS_RZA1H */
+#define SRAM_SIZE		0x00300000		/* 3MB */
+#endif /* TOPPERS_RZA1H */
+
+#define IO1_ADDR		0x3fe00000		/* I/Oé åï¼äºç´é åãå«ãï¼*/
+#define IO1_SIZE		0x00200000		/* 2MB */
+#define IO2_ADDR		0xe8000000		/* I/Oé åï¼äºç´é åãå«ãï¼*/
+#define IO2_SIZE		0x18000000		/* 384MB */
+
+/*
+ *  åã¯ã­ãã¯å¨æ³¢æ°ã®å®ç¾©
+ */
+#define OSTM_CLK		RZA1_CLK_P0
+#define SCIF_CLK		RZA1_CLK_P1
+
+/*
+ *  MPCore Private Memory Regionã®å
+é ­çªå°
+ */
+#define MPCORE_PMR_BASE		0xf0000000
+
+/*
+ *  GICä¾å­é¨ãä½¿ç¨ããããã®å®ç¾©
+ */
+#ifndef GIC_TNUM_INTNO
+#ifdef TOPPERS_RZA1H
+#define GIC_TNUM_INTNO		UINT_C(587)
+#else /* TOPPERS_RZA1H */
+#define GIC_TNUM_INTNO		UINT_C(538)
+#endif /* TOPPERS_RZA1H */
+#endif /* GIC_TNUM_INT */
+
+/*
+ *  å²è¾¼ã¿ã³ã³ãã­ã¼ã©ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿ï¼RZ/A1åºæã®ãã®ï¼
+ */
+#define GICC_BASE			0xe8202000
+#define GICD_BASE			0xe8201000
+
+#define RZA1_ICR0			CAST(uint16_t *, 0xfcfef800)
+#define RZA1_ICR1			CAST(uint16_t *, 0xfcfef802)
+#define RZA1_IRQRR			CAST(uint16_t *, 0xfcfef804)
+
+/*
+ *  OSã¿ã¤ãã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define OSTM0_BASE			0xfcfec000
+#define OSTM1_BASE			0xfcfec400
+
+/*
+ *  L2ã­ã£ãã·ã¥ã³ã³ãã­ã¼ã©ï¼PL310ï¼ã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define PL310_BASE			0x3ffff000
+
+/*
+ *  ã¯ã­ãã¯ãã«ã¹ã¸ã§ãã¬ã¼ã¿ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_CPG_BASE		0xfcfe0000
+#define RZA1_FRQCR			CAST(uint16_t *, RZA1_CPG_BASE + 0x010)
+#define RZA1_FRQCR2			CAST(uint16_t *, RZA1_CPG_BASE + 0x014)
+
+/*
+ *  ãã¹ã¹ãã¼ãã³ã³ãã­ã¼ã©ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_BSC_BASE		0x3FFFC000
+#define RZA1_CMNCR			CAST(uint32_t *, RZA1_BSC_BASE)
+#define RZA1_CS0BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0004)
+#define RZA1_CS1BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0008)
+#define RZA1_CS2BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x000C)
+#define RZA1_CS3BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0010)
+#define RZA1_CS4BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0014)
+#define RZA1_CS5BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0018)
+#define RZA1_CS0WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0028)
+#define RZA1_CS1WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x002C)
+#define RZA1_CS2WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0030)
+#define RZA1_CS3WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0034)
+#define RZA1_CS4WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0038)
+#define RZA1_CS5WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x003C)
+#define RZA1_SDCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x004C)
+#define RZA1_RTCSR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0050)
+#define RZA1_RTCNT			CAST(uint32_t *, RZA1_BSC_BASE + 0x0054)
+#define RZA1_RTCOR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0058)
+
+/*
+ *  ã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define SCIF0_BASE			0xe8007000
+#define SCIF1_BASE			0xe8007800
+#define SCIF2_BASE			0xe8008000
+#define SCIF3_BASE			0xe8008800
+#define SCIF4_BASE			0xe8009000
+#ifdef TOPPERS_RZA1H
+#define SCIF5_BASE			0xe8009800
+#define SCIF6_BASE			0xe800a000
+#define SCIF7_BASE			0xe800a800
+#endif /* TOPPERS_RZA1H */
+
+/*
+ *  ãµãã¼ãããã·ãªã¢ã«ãã¼ãã®åæ°
+ */
+#ifdef TOPPERS_RZA1H
+#define TNUM_SIOP  8
+#elif defined(TOPPERS_RZ_A1L)
+#define TNUM_SIOP  5
+#endif /* TOPPERS_RZA1H */
+
+/*
+ *  ä½æ¶è²»é»åã¢ã¼ãé¢é£ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_LOWPWR_BASE	0xfcfe0000
+#define RZA1_STBCR1			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x020)
+#define RZA1_STBCR2			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x024)
+#define RZA1_STBCR3			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x420)
+#define RZA1_STBCR4			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x424)
+#define RZA1_STBCR5			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x428)
+#define RZA1_STBCR6			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x42C)
+#define RZA1_STBCR7			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x430)
+#define RZA1_STBCR8			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x434)
+#define RZA1_STBCR9			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x438)
+#define RZA1_STBCR10		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x43C)
+#define RZA1_STBCR11		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x440)
+#define RZA1_STBCR12		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x444)
+#define RZA1_STBCR13		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x470)
+#define RZA1_SYSCR1			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x400)
+#define RZA1_SYSCR2			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x404)
+#define RZA1_SYSCR3			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x408)
+#define RZA1_CPUSTS			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x018)
+
+/*
+ *  æ±ç¨å
+¥åºåãã¼ãã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_PORT_BASE		0xfcfe3000
+#define RZA1_PORT_P(n)		CAST(uint16_t *, (RZA1_PORT_BASE + 0x0000 + (n)*4))
+#define RZA1_PORT_PSR(n)	CAST(uint32_t *, (RZA1_PORT_BASE + 0x0100 + (n)*4))
+#define RZA1_PORT_PPR(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0200 + (n)*4))
+#define RZA1_PORT_PM(n)		CAST(uint16_t *, (RZA1_PORT_BASE + 0x0300 + (n)*4))
+#define RZA1_PORT_PMC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0400 + (n)*4))
+#define RZA1_PORT_PFC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0500 + (n)*4))
+#define RZA1_PORT_PFCE(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0600 + (n)*4))
+#define RZA1_PORT_PFCAE(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0a00 + (n)*4))
+#define RZA1_PORT_PIBC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x4000 + (n)*4))
+#define RZA1_PORT_PBDC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x4100 + (n)*4))
+#define RZA1_PORT_PIPC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x4200 + (n)*4))
+
+/*
+ *	å²è¾¼ã¿çªå·
+ */
+#define INTNO_IRQ0			32		/* IRQ0 */
+#define INTNO_IRQ1			33		/* IRQ1 */
+#define INTNO_IRQ2			34		/* IRQ2 */
+#define INTNO_IRQ3			35		/* IRQ3 */
+#define INTNO_IRQ4			36		/* IRQ4 */
+#define INTNO_IRQ5			37		/* IRQ5 */
+#define INTNO_IRQ6			38		/* IRQ6 */
+#define INTNO_IRQ7			39		/* IRQ7 */
+#define INTNO_OSTM0			134		/* OSã¿ã¤ã0 */
+#define INTNO_OSTM1			135		/* OSã¿ã¤ã1 */
+#define INTNO_SCIF0_BRI		221		/* SCIF0 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF0_ERI		222		/* SCIF0 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF0_RXI		223		/* SCIF0 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF0_TXI		224		/* SCIF0 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF1_BRI		225		/* SCIF1 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF1_ERI		226		/* SCIF1 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF1_RXI		227		/* SCIF1 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF1_TXI		228		/* SCIF1 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF2_BRI		229		/* SCIF2 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF2_ERI		230		/* SCIF2 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF2_RXI		231		/* SCIF2 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF2_TXI		232		/* SCIF2 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF3_BRI		233		/* SCIF3 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF3_ERI		234		/* SCIF3 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF3_RXI		235		/* SCIF3 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF3_TXI		236		/* SCIF3 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF4_BRI		237		/* SCIF4 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF4_ERI		238		/* SCIF4 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF4_RXI		239		/* SCIF4 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF4_TXI		240		/* SCIF4 éä¿¡å²è¾¼ã¿ */
+#ifdef TOPPERS_RZA1H
+#define INTNO_SCIF5_BRI		241		/* SCIF5 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF5_ERI		242		/* SCIF5 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF5_RXI		243		/* SCIF5 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF5_TXI		244		/* SCIF5 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF6_BRI		245		/* SCIF6 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF6_ERI		246		/* SCIF6 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF6_RXI		247		/* SCIF6 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF6_TXI		248		/* SCIF6 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF7_BRI		249		/* SCIF7 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF7_ERI		250		/* SCIF7 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF7_RXI		251		/* SCIF7 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF7_TXI		252		/* SCIF7 éä¿¡å²è¾¼ã¿ */
+#endif /* TOPPERS_RZA1H */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+#include "kernel.h"
+
+/*
+ *  IRQå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
+ */
+Inline void
+rza1_clear_irq(INTNO intno)
+{
+	uint16_t	reg;
+
+	reg = sil_reh_mem(RZA1_IRQRR);
+	reg &= ~(0x01U << (intno - INTNO_IRQ0));
+	sil_wrh_mem(RZA1_IRQRR, reg);
+}
+
+/*
+ *  æ±ç¨å
+¥åºåãã¼ãã®è¨­å®
+ *
+ *  æ±ç¨å
+¥åºåãã¼ãã®å¶å¾¡ã¬ã¸ã¹ã¿ã®ç¹å®ã®ããããï¼ã»ããï¼setã0ã§ãª
+ *  ãæï¼ã¾ãã¯ã¯ãªã¢ï¼setã0ã®æï¼ããï¼
+ */
+Inline void
+rza1_config_port(uint16_t *reg, uint_t bit, uint_t set)
+{
+	uint16_t	val;
+	uint16_t	mask;
+
+	mask = 0x01U << bit;
+	val = sil_reh_mem(reg);
+	if (set == 0) {
+		val &= ~mask;
+	}
+	else {
+		val |= mask;
+	}
+	sil_wrh_mem(reg, val);
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_RZA1_H */
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.c
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.c	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.c	(revision 307)
@@ -0,0 +1,628 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2001-2011 by Industrial Technology Institute,
+ *                              Miyagi Prefectural Government, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: scif.c 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *   RZ/A1ç¨ ç°¡æSIOãã©ã¤ã
+ */
+#include <sil.h>
+#include "target_syssvc.h"
+#include "rza1.h"
+#include "scif.h"
+
+/*
+ * åã¬ã¸ã¹ã¿ã®ãªãã»ãã
+ */
+#define REG_SCSMR       0x00    /* ã·ãªã¢ã«ã¢ã¼ãã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCBRR       0x04    /* ãããã¬ã¼ãã¬ã¸ã¹ã¿, 8bit */
+#define REG_SCSCR       0x08    /* ã·ãªã¢ã«ã³ã³ãã­ã¼ã«ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCFTDR      0x0C    /* éä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿, 8bit */
+#define REG_SCFSR       0x10    /* ã·ãªã¢ã«ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCFRDR      0x14    /* åä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿, 8bit */
+#define REG_SCFCR       0x18    /* FIFOã³ã³ãã­ã¼ã«ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCFDR       0x1C    /* FIFOãã¼ã¿ã«ã¦ã³ãã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCSPTR      0x20    /* ã·ãªã¢ã«ãã¼ãã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCLSR       0x24    /* ã©ã¤ã³ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCEMR       0x28    /* ã·ãªã¢ã«æ¡å¼µã¢ã¼ãã¬ã¸ã¹ã¿, 16bit */
+
+/*
+ * åã¬ã¸ã¹ã¿ã®è¨­å®å¤
+ */
+#define SCSMR_SYNC      0x0080          /* 1:ã¯ã­ãã¯åæå¼ã¢ã¼ã */
+#define SCSMR_7BIT      0x0040          /* 1:ï¼ããããã¼ã¿ */
+#define SCSMR_PARITY    0x0020          /* 1:ããªãã£ä»å  */
+#define SCSMR_ODD       0x0010          /* 1:å¥æ°ããªãã£ */
+#define SCSMR_2STOP     0x0008          /* 1:ï¼ã¹ãããããã */
+#define SCSMR_CKS1      0x0000          /* 00:P1clock / 1 */
+#define SCSMR_CKS4      0x0001          /* 01:P1clock / 4 */
+#define SCSMR_CKS16     0x0002          /* 10:P1clock / 16 */
+#define SCSMR_CKS64     0x0003          /* 11:P1clock / 64 */
+
+#define SCSCR_TIE       0x0080          /* 1:éä¿¡å²ãè¾¼ã¿è¨±å¯ */
+#define SCSCR_RIE       0x0040          /* 1:åä¿¡å²ãè¾¼ã¿,åä¿¡ã¨ã©ã¼å²ãè¾¼ã¿,ãã¬ã¼ã¯å²ãè¾¼ã¿è¨±å¯ */
+#define SCSCR_TE        0x0020          /* 1:éä¿¡è¨±å¯ */
+#define SCSCR_RE        0x0010          /* 1:åä¿¡è¨±å¯ */
+#define SCSCR_REIE      0x0008          /* 1:åä¿¡ã¨ã©ã¼å²ãè¾¼ã¿,ãã¬ã¼ã¯å²ãè¾¼ã¿è¨±å¯ */
+#define SCSCR_INTCLK    0x0000          /* 00:å
+é¨ã¯ã­ãã¯,CKSç«¯å­ã¯ç¡è¦ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+
+#define SCFSR_PER_MASK  0xF000          /* ããªãã£ã¨ã©ã¼æ°æ½åºãã¹ã¯ */
+#define SCFSR_PER_SHIFT 12              /* ããªãã£ã¨ã©ã¼æ°æ½åºå³ã·ããæ° */
+#define SCFSR_FER_MASK  0x0F00          /* ãã¬ã¼ãã³ã°ã¨ã©ã¼æ°æ½åºãã¹ã¯ */
+#define SCFSR_FER_SHIFT 8               /* ãã¬ã¼ãã³ã°ã¨ã©ã¼æ°æ½åºå³ã·ããæ° */
+#define SCFSR_ER        0x0080          /* 1:åä¿¡ã¨ã©ã¼ */
+#define SCFSR_TEND      0x0040          /* 1:éä¿¡å®äº */
+#define SCFSR_TDFE      0x0020          /* 1:éä¿¡FIFOãã¼ã¿ã¨ã³ããã£ */
+#define SCFSR_BRK       0x0010          /* 1:ãã¬ã¼ã¯æ¤åº */
+#define SCFSR_FER       0x0008          /* 1:ãã¬ã¼ãã³ã°ã¨ã©ã¼æ¤åº */
+#define SCFSR_PER       0x0004          /* 1:ããªãã£ã¨ã©ã¼æ¤åº */
+#define SCFSR_RDF       0x0002          /* 1:åä¿¡FIFOãã¼ã¿ãã« */
+#define SCFSR_DR        0x0001          /* 1:åä¿¡ãã¼ã¿ã¬ãã£ */
+
+#define SCFCR_RSTRG_15  0x0000          /* RTS#åºåã¢ã¯ãã£ãããªã¬:15 */
+#define SCFCR_RSTRG_1   0x0100          /* RTS#åºåã¢ã¯ãã£ãããªã¬:1 */
+#define SCFCR_RSTRG_4   0x0200          /* RTS#åºåã¢ã¯ãã£ãããªã¬:4 */
+#define SCFCR_RSTRG_6   0x0300          /* RTS#åºåã¢ã¯ãã£ãããªã¬:6 */
+#define SCFCR_RSTRG_8   0x0400          /* RTS#åºåã¢ã¯ãã£ãããªã¬:8 */
+#define SCFCR_RSTRG_10  0x0500          /* RTS#åºåã¢ã¯ãã£ãããªã¬:10 */
+#define SCFCR_RSTRG_12  0x0600          /* RTS#åºåã¢ã¯ãã£ãããªã¬:12 */
+#define SCFCR_RSTRG_14  0x0700          /* RTS#åºåã¢ã¯ãã£ãããªã¬:14 */
+#define SCFCR_RTRG_1    0x0000          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:1ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_RTRG_4    0x0040          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:4ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_RTRG_8    0x0080          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:8ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_RTRG_14   0x00C0          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:14ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_8    0x0000          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:8ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_4    0x0010          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:4ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_2    0x0020          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:2ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_0    0x0030          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:0ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_MCE       0x0008          /* CTS#,RTS#è¨±å¯ */
+#define SCFCR_TFRST     0x0004          /* 1:éä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿ãªã»ãã */
+#define SCFCR_RFRST     0x0002          /* 1:åä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿ãªã»ãã */
+#define SCFCR_LOOP      0x0001          /* 1:ã«ã¼ãããã¯ãã¹ã */
+
+#define SCFDR_T_MASK    0x1F00          /* æªéä¿¡ãã¼ã¿æ°æ½åºãã¹ã¯ */
+#define SCFDR_T_SHIFT   8               /* æªéä¿¡ãã¼ã¿æ°æ½åºå³ã·ããæ° */
+#define SCFDR_R_MASK    0x001F          /* åä¿¡ãã¼ã¿æ°æ½åºãã¹ã¯ */
+#define SCFDR_R_SHIFT   0               /* åä¿¡ãã¼ã¿æ°æ½åºå³ã·ããæ° */
+
+#define SCLSR_ORER      0x0001          /* 1:ãªã¼ãã¼ã©ã³ã¨ã©ã¼ */
+
+#define SCEMR_BGDM      0x0080          /* 1:ãã¼ã¬ã¼ãã¸ã§ãã¬ã¼ã¿åéã¢ã¼ã */
+#define SCEMR_ABCS16    0x0000          /* ãããã¬ã¼ãã®16åã®åºæ¬ã¯ã­ãã¯ã§åä½ */
+#define SCEMR_ABCS8     0x0001          /* ãããã¬ã¼ãã®8åã®åºæ¬ã¯ã­ãã¯ã§åä½ */
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯ã®å®ç¾©
+ */
+typedef struct sio_port_initialization_block {
+	uint16_t *port;   			/* ã·ãªã¢ã«ãã¼ãã®ãã¼ã¹ã¬ã¸ã¹ã¿ */
+	uint32_t bps_setting; 		/* ãã¼ã¬ã¼ãã®è¨­å®å¤ */
+} SIOPINIB;
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®å®ç¾©
+ */
+struct sio_port_control_block {
+	const SIOPINIB  *p_siopinib;  /* ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯ */
+	intptr_t  exinf;              /* æ¡å¼µæ
+å ± */
+	bool_t    openflag;           /* ãªã¼ãã³æ¸ã¿ãã©ã° */
+	bool_t    sendflag;           /* éä¿¡å²è¾¼ã¿ã¤ãã¼ãã«ãã©ã° */
+	bool_t    getready;           /* æå­ãåä¿¡ããç¶æ
+ */
+	bool_t    putready;           /* æå­ãéä¿¡ã§ããç¶æ
+ */
+	bool_t    is_initialized;     /* ããã¤ã¹åæåæ¸ã¿ãã©ã° */
+};
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯
+ */
+static const SIOPINIB siopinib_table[TNUM_SIOP] = {
+	{
+		(uint16_t *)(SCIF0_BASE),
+		UART1_BPS_SETTING,
+	},
+#if TNUM_SIOP > 1
+	{
+		(uint16_t *)(SCIF1_BASE),
+		UART2_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP > 1 */
+#if TNUM_SIOP > 2
+	{
+		(uint16_t *)(SCIF2_BASE),
+		UART3_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP > 2 */
+#if TNUM_SIOP > 3
+	{
+		(uint16_t *)(SCIF3_BASE),
+		UART4_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  3*/
+#if TNUM_SIOP > 4
+	{
+		(uint16_t *)(SCIF4_BASE),
+		UART5_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  4*/
+#if TNUM_SIOP > 5
+	{
+		(uint16_t *)(SCIF5_BASE),
+		UART6_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  5*/
+#if TNUM_SIOP > 6
+	{
+		(uint16_t *)(SCIF6_BASE),
+		UART7_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  6*/
+#if TNUM_SIOP > 7
+	{
+		(uint16_t *)(SCIF7_BASE),
+		UART8_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  7*/
+};
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®ã¨ãªã¢
+ */
+static SIOPCB	siopcb_table[TNUM_SIOP];
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãIDããç®¡çãã­ãã¯ãåãåºãããã®ãã¯ã­
+ */
+#define INDEX_SIOP(siopid)	 ((uint_t)((siopid) - 1))
+#define get_siopcb(siopid)	 (&(siopcb_table[INDEX_SIOP(siopid)]))
+#define get_siopinib(siopid) (&(siopinib_table[INDEX_SIOP(siopid)]))
+
+/*
+ *  ç®¡çãã­ãã¯ã¸ã®ãã¤ã³ã¿ããã·ãªã¢ã«I/Oãã¼ãIDãåãåºãããã®ãã¯ã­
+ */
+#define SIOPID(p_siopcb)    ((ID)((p_siopcb) - siopcb_table))
+
+/*
+ *  æå­ãåä¿¡ãããï¼
+ */
+Inline bool_t scif_getready(SIOPCB *p_siopcb)
+{
+	uint16_t fsrval;
+	uint16_t lsrval;
+
+	fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
+	lsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR));
+	if (fsrval & (SCFSR_ER | SCFSR_BRK)) {
+		fsrval = fsrval & ~(SCFSR_ER | SCFSR_BRK);
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
+	}
+	if (lsrval & SCLSR_ORER) {
+		lsrval = lsrval & ~SCLSR_ORER;
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR), lsrval);
+	}
+	if (fsrval & SCFSR_RDF) {
+		return true;
+	}
+	return false;
+}
+
+/*
+ *  æå­ãéä¿¡ã§ãããï¼
+ */
+Inline bool_t scif_putready(SIOPCB *p_siopcb)
+{
+	uint16_t fsrval;
+
+	fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
+	if (fsrval & SCFSR_TDFE) {
+		return true;
+	}
+	return false;
+}
+
+/*
+ *  åä¿¡ããæå­ã®ååºã
+ */
+Inline bool_t scif_getchar(SIOPCB *p_siopcb, char *rxdata)
+{
+	uint16_t fsrval;
+	uint16_t lsrval;
+	uint8_t read_data;
+
+	fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
+	lsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR));
+	if (fsrval & (SCFSR_ER | SCFSR_BRK)) {
+		fsrval = fsrval & ~(SCFSR_ER | SCFSR_BRK);
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
+	}
+	if (lsrval & SCLSR_ORER) {
+		lsrval = lsrval & ~SCLSR_ORER;
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR), lsrval);
+	}
+	if (fsrval & SCFSR_RDF) {
+		read_data = sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFRDR);
+		fsrval = fsrval & ~SCFSR_RDF;
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
+		*rxdata = (char)read_data;
+		return true;
+	}
+	return false;
+}
+
+/*
+ *  éä¿¡ããæå­ã®æ¸è¾¼ã¿
+ */
+Inline void scif_putchar(SIOPCB *p_siopcb, char c)
+{
+	sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFTDR, c);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), ~(SCFSR_TEND | SCFSR_TDFE));
+}
+
+/*
+ *  éä¿¡å²è¾¼ã¿è¨±å¯
+ */
+Inline void scif_enable_send(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval |= SCSCR_TIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+/*
+ *  éä¿¡å²è¾¼ã¿ç¦æ­¢
+ */
+Inline void scif_disable_send(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval = scrval & ~SCSCR_TIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+
+/*
+ *  åä¿¡å²è¾¼ã¿è¨±å¯
+ */
+Inline void scif_enable_rcv(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval |= SCSCR_RIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+/*
+ *  åä¿¡å²è¾¼ã¿ç¦æ­¢
+ */
+Inline void
+scif_disable_rcv(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval = scrval & ~SCSCR_RIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+void scif_initialize(void)
+{
+	SIOPCB	*p_siopcb;
+	uint_t	i;
+
+	/*
+	 *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®åæå
+	 */
+	for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
+		p_siopcb->p_siopinib = &(siopinib_table[i]);
+		p_siopcb->openflag = false;
+		p_siopcb->sendflag = false;
+	}
+}
+
+
+/*
+ * ãã¼ãã¦ã§ã¢ã®åæåå¦ç
+ */
+static int scif_init_siopinib(const SIOPINIB *p_siopinib)
+{
+	uint16_t fsrval;
+	uint8_t brrval;
+
+	fsrval = RZA1_CLK_P1 / (32 * p_siopinib->bps_setting) - 1;
+	if (fsrval > 255) return 1;
+	brrval = (uint8_t)fsrval;
+
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), 0);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFCR), SCFCR_TFRST | SCFCR_RFRST);
+	(void)sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR));
+	(void)sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCLSR));
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), 0);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCLSR), 0);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), SCSCR_INTCLK);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSMR), SCSMR_CKS1);	/* 8N1, P1clock/1 */
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCEMR), 0);
+	sil_wrb_mem((uint8_t *)p_siopinib->port + REG_SCBRR, brrval);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFCR), SCFCR_RSTRG_15 | SCFCR_RTRG_1 | SCFCR_TTRG_8);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), SCSCR_TE | SCSCR_RE | SCSCR_INTCLK);
+	while (sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR)) & SCFSR_RDF) {
+		(void)sil_reb_mem((uint8_t *)p_siopinib->port + REG_SCFRDR);
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), ~SCFSR_RDF);
+	}
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), 0);
+	return 0;
+}
+
+
+/*
+ * ã«ã¼ãã«èµ·åæã®ãã¼ãåºåç¨ã®åæå
+ */
+void
+scif_init(ID siopid)
+{
+	SIOPCB		  *p_siopcb   = get_siopcb(siopid);
+	const SIOPINIB  *p_siopinib = get_siopinib(siopid);
+	/*  ãã®æç¹ã§ã¯ãp_siopcb->p_siopinibã¯åæåããã¦ããªã  */
+
+	if (!(p_siopcb->is_initialized)) {
+		scif_init_siopinib(p_siopinib);
+		p_siopcb->is_initialized = true;
+	}
+}
+
+/*
+ *  ãã¼ãnããªã¼ãã³æ¸ã¿ãï¼ï¼ãã¼ãIDãå¼æ°ï¼
+ */
+bool_t
+scif_openflag_id(ID siopid)
+{
+	return(get_siopcb(siopid)->openflag);
+}
+
+/*
+ *  ãã¼ãnããªã¼ãã³æ¸ã¿ãï¼
+ *  ï¼ãã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ãã®å
+é ­çªå°ãå¼æ°ï¼
+ */
+bool_t
+scif_openflag_cb(SIOPCB *p_siopcb)
+{
+	return(p_siopcb->openflag);
+}
+
+/*
+ *  ãã¼ãIDã®åå¾
+ */
+ID
+scif_get_siopid(SIOPCB *p_siopcb)
+{
+	return(SIOPID(p_siopcb));
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+SIOPCB *
+scif_opn_por(ID siopid, intptr_t exinf)
+{
+	SIOPCB		  *p_siopcb;
+	const SIOPINIB  *p_siopinib;
+
+	p_siopcb = get_siopcb(siopid);
+	p_siopinib = p_siopcb->p_siopinib;
+
+	/*
+	 * ãã¼ãã¦ã§ã¢ã®åæå
+	 * ãæ¢ã«åæåãã¦ããå ´åã¯ãäºéã«åæåããªãã
+	 */
+	if (!(p_siopcb->is_initialized)) {
+		scif_init_siopinib(p_siopinib);
+		p_siopcb->is_initialized = true;
+	}
+
+	p_siopcb->exinf = exinf;
+	p_siopcb->getready = p_siopcb->putready = false;
+	p_siopcb->openflag = true;
+
+	return(p_siopcb);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+void
+scif_cls_por(SIOPCB *p_siopcb)
+{
+	sil_wrh_mem(p_siopcb->p_siopinib->port + REG_SCSCR, 0);
+}
+
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®ãã¼ãªã³ã°ã§ã®åºå
+ */
+void
+scif_pol_putc(char c, ID siopid)
+{
+	const SIOPINIB *p_siopinib;
+	uint16_t fsrval;
+	SIL_PRE_LOC;
+
+	p_siopinib = get_siopinib(siopid);
+
+	while(1) {
+		/*
+		 *  ãªã¨ã³ãã©ã³ãã«ãããããå
+¨å²è¾¼ã¿ã­ãã¯ç¶æ
+ã«ããã
+		 */
+		SIL_LOC_INT();
+
+		fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR));
+		if (fsrval & SCFSR_TDFE) {
+			sil_wrb_mem((uint8_t *)p_siopinib->port + REG_SCFTDR, c);
+			sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), ~(SCFSR_TEND | SCFSR_TDFE));
+			/*
+			 *  ãªã¿ã¼ã³ããåã«å
+¨å²è¾¼ã¿ã­ãã¯ãã©ã°ãå
+ã®ç¶æ
+ã«æ»ãã
+			 */
+			SIL_UNL_INT();
+			return;
+		} else {
+			/*
+			 *  ããã§å
+¨å²è¾¼ã¿ã­ãã¯ãè§£é¤ãã¦ãå²è¾¼ã¿ãåãä»ããã
+			 */
+			SIL_UNL_INT();
+		}
+	}
+}
+
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+bool_t
+scif_snd_chr(SIOPCB *p_siopcb, char c)
+{
+	if (scif_putready(p_siopcb)){
+		scif_putchar(p_siopcb, c);
+		return(true);
+	}
+	return(false);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+int_t
+scif_rcv_chr(SIOPCB *p_siopcb)
+{
+	char rxdata;
+	if (scif_getready(p_siopcb)) {
+		if (scif_getchar(p_siopcb, &rxdata)) {
+			return((int_t)rxdata);
+		}
+	}
+	return(-1);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+void
+scif_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+	  case SIO_RDY_SND:
+		scif_enable_send(p_siopcb);
+		break;
+	  case SIO_RDY_RCV:
+		scif_enable_rcv(p_siopcb);
+		break;
+	}
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+void
+scif_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+	  case SIO_RDY_SND:
+		scif_disable_send(p_siopcb);
+		break;
+	  case SIO_RDY_RCV:
+		scif_disable_rcv(p_siopcb);
+		break;
+	}
+}
+
+/*
+ *  SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
+ */
+void
+scif_tx_isr(ID siopid)
+{
+	SIOPCB *p_siopcb = get_siopcb(siopid);
+
+	if (scif_putready(p_siopcb)) {
+		scif_irdy_snd(p_siopcb->exinf);
+	}
+}
+
+
+/*
+ *  SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
+ */
+void
+scif_rx_isr(ID siopid)
+{
+	SIOPCB *p_siopcb = get_siopcb(siopid);
+	while (scif_getready(p_siopcb)) {
+		scif_irdy_rcv(p_siopcb->exinf);
+	}
+}
Index: asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.h
===================================================================
--- asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.h	(revision 307)
+++ asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.h	(revision 307)
@@ -0,0 +1,157 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2001-2011 by Industrial Technology Institute,
+ *                              Miyagi Prefectural Government, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: scif.h 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+
+#ifndef TOPPERS_SCIF_H
+#define TOPPERS_SCIF_H
+
+#ifndef TOPPERS_MACRO_ONLY
+
+#include <kernel.h>
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®å®ç¾©
+ */
+typedef struct sio_port_control_block	SIOPCB;
+
+/*
+ *  ã³ã¼ã«ããã¯ã«ã¼ãã³ã®è­å¥çªå·
+ */
+#define SIO_RDY_SND    1U        /* éä¿¡å¯è½ã³ã¼ã«ããã¯ */
+#define SIO_RDY_RCV    2U        /* åä¿¡éç¥ã³ã¼ã«ããã¯ */
+
+/*
+ *  SIOãã©ã¤ãã®åæåã«ã¼ãã³
+ */
+extern void scif_initialize(void);
+
+/*
+ * ã«ã¼ãã«èµ·åæã®ãã¼ãåºåç¨ã®åæå
+ */
+extern void scif_init(ID siopid);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®ãã¼ãªã³ã°ã§ã®åºå
+ */
+extern void scif_pol_putc(char c, ID siopid);
+
+/*
+ *  ãªã¼ãã³ãã¦ãããã¼ãããããï¼
+ */
+extern bool_t scif_openflag_id(ID siopid);			/*  ãã¼ãID  */
+extern bool_t scif_openflag_cb(SIOPCB *p_siopcb);	/*  ç®¡çãã­ãã¯ã®å
+é ­çªå°  */
+
+/*
+ *  ãã¼ãIDã®åå¾
+ */
+extern ID scif_get_siopid(SIOPCB *p_siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+extern SIOPCB *scif_opn_por(ID siopid, intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+extern void scif_cls_por(SIOPCB *p_siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+extern bool_t scif_snd_chr(SIOPCB *p_siopcb, char c);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+extern int_t scif_rcv_chr(SIOPCB *p_siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+extern void  scif_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+extern void scif_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn);
+
+/*
+ *  SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
+ */
+extern void scif_tx_isr(ID siopid);
+extern void scif_rx_isr(ID siopid);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+extern void scif_irdy_snd(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+extern void scif_irdy_rcv(intptr_t exinf);
+
+/*
+ *  ãã¼ãçªå·ããç®¡çãã­ãã¯ã®å
+é ­çªå°ã¸ã®å¤æ
+ */
+extern SIOPCB *scif_get_siopcb(ID siopid);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_SCIF_H */
