Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/E_PACKAGE
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/E_PACKAGE	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/E_PACKAGE	(revision 303)
@@ -0,0 +1,8 @@
+E_PACKAGE asp3_nucleo_f401re_gcc
+VERSION %date
+
+INCLUDE MANIFEST
+INCLUDE ../../MANIFEST
+INCLUDE ../../arch/arm_m_gcc/MANIFEST
+INCLUDE ../../arch/arm_m_gcc/stm32f4xx_stm32cube/MANIFEST
+INCLUDE ../../tecsgen/MANIFEST_for_asp3
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/MANIFEST
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/MANIFEST	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/MANIFEST	(revision 303)
@@ -0,0 +1,54 @@
+PACKAGE asp3_nucleo_f401re_gcc
+
+E_PACKAGE
+gdb.ini
+Makefile.target
+MANIFEST
+nucleo_f401re.h
+stm32f401re.ld
+target.cdl
+target.tf
+target_asm.inc
+target_cfg1_out.h
+target_check.trb
+target_kernel.cfg
+target_kernel.h
+target_kernel.trb
+target_kernel_impl.c
+target_kernel_impl.h
+target_rename.def
+target_rename.h
+target_sil.h
+target_stddef.h
+target_syssvc.h
+target_test.h
+target_timer.c
+target_timer.cfg
+target_timer.h
+target_unrename.h
+target_user.txt
+tPutLogTarget.c
+tPutLogTarget.cdl
+tSIOPortTarget.cdl
+tSIOPortTargetMain_inline.h
+
+stm32fcube/stm32f4xx_hal_conf.h
+stm32fcube/stm32f4xx_nucleo.c
+stm32fcube/stm32f4xx_nucleo.h
+stm32fcube/system_stm32f4xx.c
+stm32fcube/systemclock_config.c
+
+truestudio/asp/asp_debug.launch
+truestudio/asp/Makefile
+truestudio/asp/sample1.c
+truestudio/asp/sample1.cfg
+truestudio/asp/sample1.h
+truestudio/asp/.cproject
+truestudio/asp/.project
+
+truestudio/asp/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+truestudio/asp/.settings/com.atollic.truestudio.tsp.prefs
+truestudio/asp/.settings/language.settings.xml
+truestudio/asp/.settings/org.eclipse.core.resources.prefs
+
+truestudio/asp/deps/dummy.txt
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/Makefile.target
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/Makefile.target	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/Makefile.target	(revision 303)
@@ -0,0 +1,149 @@
+#
+#		Makefile ã®ã¿ã¼ã²ããä¾å­é¨ï¼NUCLEO_F401REç¨ï¼
+#
+
+#
+#  ãã¼ãå, ãããåï¼ã³ã¢åï¼éçºç°å¢åã®å®ç¾©
+#
+BOARD = nucleo_f401re
+CHIP  = stm32f4xx_stm32cube
+PRC   = arm_m
+TOOL  = gcc
+
+#
+#  FPUãä½¿ç¨ããã
+#
+FPU_USAGE = FPU_LAZYSTACKING
+
+#
+#  ä½¿ç¨ããã¿ã¤ã
+#
+#KERNEL_TIMER = SYSTICK
+KERNEL_TIMER = TIM
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+INCLUDES := $(INCLUDES) -I$(TARGETDIR) -I$(TARGETDIR)/stm32fcube
+CDEFS := $(CDEFS) -DSTM32F401xE
+COPTS := $(COPTS) 
+LDFLAGS := -nostdlib -nostartfiles $(LDFLAGS)
+
+#
+# ãã¡ã¤ã«ãµã¤ãºåæ¸ã®ããã®ãªãã·ã§ã³
+#
+COPTS   := $(COPTS) -ffunction-sections -fdata-sections
+OBJ_LDFLAGS := $(OBJ_LDFLAGS) -Wl,--gc-sections
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIRS := $(KERNEL_DIRS) $(TARGETDIR) $(TARGETDIR)/stm32fcube
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS) start.o
+KERNEL_COBJS := $(KERNEL_COBJS) target_kernel_impl.o \
+                system_stm32f4xx.o stm32f4xx_nucleo.o systemclock_config.o \
+                stm32f4xx_hal_gpio.o stm32f4xx_hal_uart.o \
+                stm32f4xx_hal_rcc.o stm32f4xx_hal_dma.o
+
+KERNEL_COBJS := $(KERNEL_COBJS) stm32f4xx_hal_tim.o
+
+#
+#  ã·ã¹ãã ãµã¼ãã¹ã«é¢ããå®ç¾©
+#
+SYSSVC_DIRS := $(SYSSVC_DIRS)
+SYSSVC_COBJS := $(SYSSVC_COBJS) usart.o
+
+#
+#  ã³ã³ãã£ã®ã¥ã¬ã¼ã¿é¢ä¿ã®å¤æ°ã®å®ç¾©
+#
+#CFG_TABS := $(CFG_TABS) --cfg1-def-table $(TARGETDIR)/target_def.csv
+#CFG1_OUT_LDFLAGS := $(LDFLAGS) -T $(TARGETDIR)/blueninja_ram_cfg1_out.ld
+
+
+#
+#  ä½¿ç¨ããã¿ã¤ã
+#
+ifeq ($(KERNEL_TIMER), SYSTICK)
+CDEFS := $(CDEFS) -DUSE_SYSTICK_AS_TIMETICK
+KERNEL_COBJS := $(KERNEL_COBJS) core_timer.o
+else
+ifeq ($(KERNEL_TIMER), TIM)
+CDEFS := $(CDEFS) -DUSE_TIM_AS_HRT
+KERNEL_COBJS := $(KERNEL_COBJS) target_timer.o
+endif
+endif
+
+#
+#  GNUéçºç°å¢ã®ã¿ã¼ã²ããã¢ã¼ã­ãã¯ãã£ã®å®ç¾©
+#
+GCC_TARGET = arm-none-eabi
+
+#
+#  ãã¬ã¼ã¹ã­ã°è¨é²ã®ãµã³ãã«ã³ã¼ãã«é¢ããå®ç¾©
+#
+ifdef ENABLE_TRACE
+	COPTS := $(COPTS) -DTOPPERS_ENABLE_TRACE
+	SYSSVC_DIRS := $(SYSSVC_DIRS) $(SRCDIR)/arch/tracelog
+endif
+
+#
+#  ä¾å­é¢ä¿ã®å®ç¾©
+#
+cfg1_out.timestamp: $(TARGETDIR)/target_timer.cfg
+
+#offset.timestamp: 
+#kernel_cfg.timestamp: $(TARGETDIR)/target_kernel.trb
+#check.timestamp: $(TARGETDIR)/target_check.trb
+
+#
+#  ãªã³ã«ã¹ã¯ãªããã®å®ç¾©
+#
+LDSCRIPT = $(TARGETDIR)/stm32f401re.ld
+
+#
+#  ãããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+include $(SRCDIR)/arch/$(PRC)_$(TOOL)/$(CHIP)/Makefile.chip
+
+#
+#  ãã©ãã·ã¥ã¸ã®æ¸ãè¾¼ã¿
+#
+UNAME_TARGET = Cygwin
+OPENOCD_PATH = /cygdrive/c/arm/OpenOCD/0.10.0-201510281129-dev/bin/openocd.exe
+OPENOCD_SCRIPT_PATH = c:/arm/OpenOCD/0.10.0-201510281129-dev/scripts
+OPENOCD_SCRIPT  = c:/arm/OpenOCD/0.10.0-201510281129-dev/scripts/board/st_nucleo_f4.cfg
+
+ifeq ($(UNAME_TARGET), Cygwin)
+	GDB = arm-gdb_m0.exe
+else
+	GDB = $(ARDUINO_BASE_DIR_WIN)\hardware\tools\gcc-arm-none-eabi-4.8.3-2014q1\bin\arm-none-eabi-gdb
+endif
+
+run: $(OBJNAME).bin
+ifeq ($(UNAME_TARGET), Cygwin)
+	"`cygpath -u "$(OPENOCD_PATH)"`" -s "$(OPENOCD_SCRIPT_PATH)" -f "$(OPENOCD_SCRIPT)" -c "program ./$(OBJNAME).bin verify 0x08000000 reset exit"
+#-c "flash probe 0; flash write_image erase ./$(OBJNAME).axf 0x08000000 reset exit"
+else
+	"$(OPENOCD_PATH)" -s "$(OPENOCD_SCRIPT_PATH)" -f "$(OPENOCD_SCRIPT)" -c "program ./$(OBJNAME).bin verify 0x4000 reset exit"
+endif
+
+ocd: $(OBJNAME).bin
+ifeq ($(UNAME_TARGET), Cygwin)
+	cygstart "$(OPENOCD_PATH)" '-s "$(OPENOCD_SCRIPT_PATH)"' '-f "$(OPENOCD_SCRIPT)"'
+else
+	start /MIN "" "$(OPENOCD_PATH)" -s "$(OPENOCD_SCRIPT_PATH)" -f "$(OPENOCD_SCRIPT)"
+endif
+
+db: $(OBJNAME).bin
+ifeq ($(UNAME_TARGET), Cygwin)
+	$(GDB) $(OBJFILE) -x $(TARGETDIR)/gdb.ini
+else
+	$(GDB) $(OBJFILE) -x $(TARGETDIR)/gdb.ini
+endif
+
+d: $(OBJNAME).bin
+ifeq ($(UNAME_TARGET), Cygwin)
+	$(GDB) $(OBJFILE) -x $(TARGETDIR)/gdb_noflash.ini
+else
+
+endif
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/gdb.ini
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/gdb.ini	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/gdb.ini	(revision 303)
@@ -0,0 +1,22 @@
+target remote localhost:3333
+set host-charset CP1252
+set target-charset CP1252
+
+# Reset to known state
+monitor reset
+
+# Load the program executable
+# load
+
+monitor program ./asp.bin verify 0x08000000
+
+
+# Reset the chip to get to a known state. Remove "monitor reset" command 
+#  if the code is not located at default address and does not run by reset. 
+monitor reset halt
+monitor reset init
+
+# Enable Debug connection in low power modes (DBGMCU->CR)
+set *0xE0042004 = (*0xE0042004) | 0x7
+
+#continue
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/nucleo_f401re.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/nucleo_f401re.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/nucleo_f401re.h	(revision 303)
@@ -0,0 +1,136 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ * 
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: nucleo_f401re.h 648 2016-02-20 00:50:56Z ertl-honda $
+ */
+
+/*
+ *		NUCLEO F401RE ãµãã¼ãã¢ã¸ã¥ã¼ã«
+ */
+
+#ifndef TOPPERS_NUCLEO_F401RE_H
+#define TOPPERS_NUCLEO_F401RE_H
+
+/*
+ *  ã³ã¢ã®ã¯ã­ãã¯å¨æ³¢æ°
+ */
+#define CPU_CLOCK_HZ	84000000
+
+/*
+ *  å²è¾¼ã¿æ°
+ */
+#define TMAX_INTNO (84 + 16)
+
+/*
+ *  å¾®å°æéå¾
+ã¡ã®ããã®å®ç¾©ï¼æ¬æ¥ã¯SILã®ã¿ã¼ã²ããä¾å­é¨ï¼
+ */
+#define SIL_DLY_TIM1    162
+#define SIL_DLY_TIM2    100
+
+#ifndef TOPPERS_MACRO_ONLY
+/*
+ *  tecsgenå®è¡æã«stm32f4xx_nucleo.hãèª­ã¿è¾¼ãã¨tecsgenãã¨ã©ã¼ã¨ãªããã
+ *  tecsgenå®è¡æã«å¿
+è¦ãªå®ç¾©ã¯ãã®ãã¡ã¤ã«ã§è¡ã
+ */
+#ifndef TECSGEN
+#include "stm32f4xx_nucleo.h"
+#else /* !TECSGEN */
+#define USART2_BASE  0x40004400U
+#define USART2_IRQn  38
+#endif /* TECSGEN */
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  USARTé¢é£ã®å®ç¾©
+ */
+#define USART_INTNO (USART2_IRQn + 16)
+#define USART_NAME  USART2
+#define USART_BASE  USART2_BASE 
+
+/*
+ *  ãã¼ã¬ã¼ã
+ */
+#define BPS_SETTING  (115200)
+
+#ifndef TOPPERS_MACRO_ONLY
+#ifndef TECSGEN
+/*
+ *  Usartã®ã¯ã­ãã¯ã¨IOã®åæå
+ */
+Inline void
+usart_low_init(void) {
+	GPIO_InitTypeDef  GPIO_InitStruct;
+
+	/* Enable Clock */
+	__HAL_RCC_GPIOA_CLK_ENABLE();
+	__HAL_RCC_USART2_CLK_ENABLE();
+  
+	/* UART TX GPIO pin configuration  */
+	GPIO_InitStruct.Pin       = GPIO_PIN_2;
+	GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+	GPIO_InitStruct.Pull      = GPIO_PULLUP;
+	GPIO_InitStruct.Speed     = GPIO_SPEED_FAST;
+	GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
+
+	HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+    
+	/* UART RX GPIO pin configuration  */
+	GPIO_InitStruct.Pin = GPIO_PIN_3;
+	GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
+    
+	HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+#endif /* TECSGEN */
+#endif /* TOPPERS_MACRO_ONLY */
+
+#endif /* TOPPERS_NUCLEO_F401RE_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32f401re.ld
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32f401re.ld	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32f401re.ld	(revision 303)
@@ -0,0 +1,61 @@
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  SRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+
+ENTRY(start)
+
+SECTIONS
+{
+	.text :
+	{
+		__text = .;
+		*(.vector)
+		*(.text)
+		*(.text.*)
+	} > FLASH
+	_etext = .;
+	PROVIDE(etext = .);
+
+	.rodata :
+	{
+		*(.rodata)
+		*(.rodata.*)
+	} > FLASH
+
+	.ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+	__exidx_start = .;
+	.ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+	__exidx_end = .;
+
+	__idata_start = .;
+	.data : AT (__idata_start)
+	{
+		__data_start = .;
+		*(.data)
+		*(.data.*)
+	} > SRAM
+	__idata_end = __idata_start + SIZEOF(.data);
+	_edata = .;
+	PROVIDE(edata = .);
+
+	. = ALIGN(4);
+
+	.bss :
+	{
+		__bss_start  = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(4);
+	} > SRAM
+	. = ALIGN(4);
+	_end = .;
+	__bss_end = .;
+	PROVIDE(end = .);
+}
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_hal_conf.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_hal_conf.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_hal_conf.h	(revision 303)
@@ -0,0 +1,405 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/GPIO_IOToggle/Inc/stm32f4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.2.2
+  * @date    09-October-2015
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED         
+#define HAL_ADC_MODULE_ENABLED
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */ 
+/* #define HAL_CRYP_MODULE_ENABLED     */ 
+/* #define HAL_DAC_MODULE_ENABLED      */ 
+/* #define HAL_DCMI_MODULE_ENABLED     */ 
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_ETH_MODULE_ENABLED      */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */  
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_LTDC_MODULE_ENABLED     */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+/* #define HAL_RNG_MODULE_ENABLED      */   
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */   
+/* #define HAL_SD_MODULE_ENABLED       */
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED*/
+/* #define HAL_WWDG_MODULE_ENABLED     */
+#define HAL_CORTEX_MODULE_ENABLED   
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)32000)    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */           
+#define  USE_RTOS                     0     
+#define  PREFETCH_ENABLE              1              
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/ 
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+ 
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+  
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+   
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_nucleo.c
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_nucleo.c	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_nucleo.c	(revision 303)
@@ -0,0 +1,854 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_nucleo.c
+  * @author  MCD Application Team
+  * @version V1.2.2
+  * @date    14-August-2015
+  * @brief   This file provides set of firmware functions to manage:
+  *          - LEDs and push-button available on STM32F4XX-Nucleo Kit 
+  *            from STMicroelectronics
+  *          - LCD, joystick and microSD available on Adafruit 1.8" TFT LCD 
+  *            shield (reference ID 802)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_nucleo.h"
+
+/** @addtogroup BSP
+  * @{
+  */ 
+
+/** @addtogroup STM32F4XX_NUCLEO
+  * @{
+  */   
+    
+/** @addtogroup STM32F4XX_NUCLEO_LOW_LEVEL 
+  * @brief This file provides set of firmware functions to manage Leds and push-button
+  *        available on STM32F4xx-Nucleo Kit from STMicroelectronics.
+  * @{
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Private_Defines
+  * @{
+  */ 
+
+/**
+  * @brief STM32F4xx NUCLEO BSP Driver version number V1.2.2
+  */
+#define __STM32F4xx_NUCLEO_BSP_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F4xx_NUCLEO_BSP_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32F4xx_NUCLEO_BSP_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_NUCLEO_BSP_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F4xx_NUCLEO_BSP_VERSION        ((__STM32F4xx_NUCLEO_BSP_VERSION_MAIN << 24)\
+                                             |(__STM32F4xx_NUCLEO_BSP_VERSION_SUB1 << 16)\
+                                             |(__STM32F4xx_NUCLEO_BSP_VERSION_SUB2 << 8 )\
+                                             |(__STM32F4xx_NUCLEO_BSP_VERSION_RC))   
+
+/**
+  * @brief LINK SD Card
+  */
+#define SD_DUMMY_BYTE            0xFF    
+#define SD_NO_RESPONSE_EXPECTED  0x80
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Private_Variables
+  * @{
+  */ 
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED2_GPIO_PORT};
+
+const uint16_t GPIO_PIN[LEDn] = {LED2_PIN};
+
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT}; 
+const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN}; 
+const uint8_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn};
+
+/**
+ * @brief BUS variables
+ */
+#if 0
+uint32_t SpixTimeout = NUCLEO_SPIx_TIMEOUT_MAX; /*<! Value of Timeout when SPI communication fails */
+static SPI_HandleTypeDef hnucleo_Spi;
+static ADC_HandleTypeDef hnucleo_Adc;
+
+/* ADC channel configuration structure declaration */
+static ADC_ChannelConfTypeDef sConfig;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Private_FunctionPrototypes
+  * @{
+  */
+static void       SPIx_Init(void);
+static void       SPIx_Write(uint8_t Value);
+static uint32_t   SPIx_Read(void);
+static void       SPIx_Error(void);
+static void       SPIx_MspInit(SPI_HandleTypeDef *hspi);
+
+static void       ADCx_Init(void);
+static void       ADCx_MspInit(ADC_HandleTypeDef *hadc);
+
+/* SD IO functions */
+void              SD_IO_Init(void);
+HAL_StatusTypeDef SD_IO_WriteCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc, uint8_t Response);
+HAL_StatusTypeDef SD_IO_WaitResponse(uint8_t Response);
+void              SD_IO_WriteDummy(void);
+void              SD_IO_WriteByte(uint8_t Data);
+uint8_t           SD_IO_ReadByte(void);
+
+/* LCD IO functions */
+void              LCD_IO_Init(void);
+void              LCD_IO_WriteData(uint8_t Data);
+void              LCD_IO_WriteMultipleData(uint8_t *pData, uint32_t Size);
+void              LCD_IO_WriteReg(uint8_t LCDReg);
+void              LCD_Delay(uint32_t delay);
+#endif
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  This method returns the STM32F4xx NUCLEO BSP Driver revision
+  * @param  None
+  * @retval version: 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t BSP_GetVersion(void)
+{
+  return __STM32F4xx_NUCLEO_BSP_VERSION;
+}
+
+/**
+  * @brief  Configures LED GPIO.
+  * @param  Led: Specifies the Led to be configured. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED2
+  * @retval None
+  */
+void BSP_LED_Init(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  GPIO_InitStruct;
+  
+  /* Enable the GPIO_LED Clock */
+  LEDx_GPIO_CLK_ENABLE(Led);
+  
+  /* Configure the GPIO_LED pin */
+  GPIO_InitStruct.Pin = GPIO_PIN[Led];
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+  
+  HAL_GPIO_Init(GPIO_PORT[Led], &GPIO_InitStruct);
+  
+  HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET); 
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: Specifies the Led to be set on. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED2
+  * @retval None
+  */
+void BSP_LED_On(Led_TypeDef Led)
+{
+  HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET); 
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED2
+  * @retval None
+  */
+void BSP_LED_Off(Led_TypeDef Led)
+{
+  HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET); 
+}
+
+/**
+  * @brief  Toggles the selected LED.
+  * @param  Led: Specifies the Led to be toggled. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED2  
+  * @retval None
+  */
+void BSP_LED_Toggle(Led_TypeDef Led)
+{
+  HAL_GPIO_TogglePin(GPIO_PORT[Led], GPIO_PIN[Led]);
+}
+
+/**
+  * @brief  Configures Button GPIO and EXTI Line.
+  * @param  Button: Specifies the Button to be configured.
+  *   This parameter should be: BUTTON_KEY
+  * @param  ButtonMode: Specifies Button mode.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
+  *                            generation capability  
+  * @retval None
+  */
+void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  
+  /* Enable the BUTTON Clock */
+  BUTTONx_GPIO_CLK_ENABLE(Button);
+  
+  if(ButtonMode == BUTTON_MODE_GPIO)
+  {
+    /* Configure Button pin as input */
+    GPIO_InitStruct.Pin = BUTTON_PIN[Button];
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);
+  }
+  
+  if(ButtonMode == BUTTON_MODE_EXTI)
+  {
+    /* Configure Button pin as input with External interrupt */
+    GPIO_InitStruct.Pin = BUTTON_PIN[Button];
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 
+    HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);
+    
+    /* Enable and set Button EXTI Interrupt to the lowest priority */
+//    HAL_NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F, 0x00);
+//    HAL_NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));
+  }
+}
+
+/**
+  * @brief  Returns the selected Button state.
+  * @param  Button: Specifies the Button to be checked.
+  *   This parameter should be: BUTTON_KEY  
+  * @retval The Button GPIO pin value.
+  */
+uint32_t BSP_PB_GetState(Button_TypeDef Button)
+{
+  return HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+}
+#if 0
+/******************************************************************************
+                            BUS OPERATIONS
+*******************************************************************************/
+/**
+  * @brief  Initializes SPI MSP.
+  * @param  None
+  * @retval None
+  */
+static void SPIx_MspInit(SPI_HandleTypeDef *hspi)
+{
+  GPIO_InitTypeDef  GPIO_InitStruct;  
+  
+  /*** Configure the GPIOs ***/  
+  /* Enable GPIO clock */
+  NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE();
+  NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE();
+  
+  /* Configure SPI SCK */
+  GPIO_InitStruct.Pin = NUCLEO_SPIx_SCK_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+  GPIO_InitStruct.Alternate = NUCLEO_SPIx_SCK_AF;
+  HAL_GPIO_Init(NUCLEO_SPIx_SCK_GPIO_PORT, &GPIO_InitStruct);
+
+  /* Configure SPI MISO and MOSI */ 
+  GPIO_InitStruct.Pin = NUCLEO_SPIx_MOSI_PIN;
+  GPIO_InitStruct.Alternate = NUCLEO_SPIx_MISO_MOSI_AF;
+  GPIO_InitStruct.Pull  = GPIO_PULLDOWN;
+  HAL_GPIO_Init(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, &GPIO_InitStruct);
+  
+  GPIO_InitStruct.Pin = NUCLEO_SPIx_MISO_PIN;
+  HAL_GPIO_Init(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, &GPIO_InitStruct);
+
+  /*** Configure the SPI peripheral ***/ 
+  /* Enable SPI clock */
+  NUCLEO_SPIx_CLK_ENABLE();
+}
+
+/**
+  * @brief  Initializes SPI HAL.
+  * @param  None
+  * @retval None
+  */
+static void SPIx_Init(void)
+{
+  if(HAL_SPI_GetState(&hnucleo_Spi) == HAL_SPI_STATE_RESET)
+  {
+    /* SPI Config */
+    hnucleo_Spi.Instance = NUCLEO_SPIx;
+      /* SPI baudrate is set to 12,5 MHz maximum (PCLK2/SPI_BaudRatePrescaler = 100/8 = 12,5 MHz) 
+       to verify these constraints:
+          - ST7735 LCD SPI interface max baudrate is 15MHz for write and 6.66MHz for read
+            Since the provided driver doesn't use read capability from LCD, only constraint 
+            on write baudrate is considered.
+          - SD card SPI interface max baudrate is 25MHz for write/read
+          - PCLK2 max frequency is 100 MHz 
+       */ 
+    hnucleo_Spi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
+    hnucleo_Spi.Init.Direction = SPI_DIRECTION_2LINES;
+    hnucleo_Spi.Init.CLKPhase = SPI_PHASE_2EDGE;
+    hnucleo_Spi.Init.CLKPolarity = SPI_POLARITY_HIGH;
+    hnucleo_Spi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+    hnucleo_Spi.Init.CRCPolynomial = 7;
+    hnucleo_Spi.Init.DataSize = SPI_DATASIZE_8BIT;
+    hnucleo_Spi.Init.FirstBit = SPI_FIRSTBIT_MSB;
+    hnucleo_Spi.Init.NSS = SPI_NSS_SOFT;
+    hnucleo_Spi.Init.TIMode = SPI_TIMODE_DISABLED;
+    hnucleo_Spi.Init.Mode = SPI_MODE_MASTER;
+
+    SPIx_MspInit(&hnucleo_Spi);
+    HAL_SPI_Init(&hnucleo_Spi);
+  }
+}
+
+/**
+  * @brief  SPI Read 4 bytes from device.
+  * @param  None
+  * @retval Read data
+*/
+static uint32_t SPIx_Read(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t readvalue = 0;
+  uint32_t writevalue = 0xFFFFFFFF;
+  
+  status = HAL_SPI_TransmitReceive(&hnucleo_Spi, (uint8_t*) &writevalue, (uint8_t*) &readvalue, 1, SpixTimeout);
+  
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* Execute user timeout callback */
+    SPIx_Error();
+  }
+
+  return readvalue;
+}
+
+/**
+  * @brief  SPI Write a byte to device.
+  * @param  Value: value to be written
+  * @retval None
+  */
+static void SPIx_Write(uint8_t Value)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  status = HAL_SPI_Transmit(&hnucleo_Spi, (uint8_t*) &Value, 1, SpixTimeout);
+    
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* Execute user timeout callback */
+    SPIx_Error();
+  }
+}
+
+/**
+  * @brief  SPI error treatment function.
+  * @param  None
+  * @retval None
+  */
+static void SPIx_Error (void)
+{
+  /* De-initialize the SPI communication BUS */
+  HAL_SPI_DeInit(&hnucleo_Spi);
+  
+  /* Re-Initiaize the SPI communication BUS */
+  SPIx_Init();
+}
+
+/******************************************************************************
+                            LINK OPERATIONS
+*******************************************************************************/
+
+/********************************* LINK SD ************************************/
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
+  *         data transfer).
+  * @param  None
+  * @retval None
+  */
+void SD_IO_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStruct;
+  uint8_t counter;
+
+  /* SD_CS_GPIO Periph clock enable */
+  SD_CS_GPIO_CLK_ENABLE();
+
+  /* Configure SD_CS_PIN pin: SD Card CS pin */
+  GPIO_InitStruct.Pin = SD_CS_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+  HAL_GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStruct);
+
+  /*------------Put SD in SPI mode--------------*/
+  /* SD SPI Config */
+  SPIx_Init();
+  
+  /* SD chip select high */
+  SD_CS_HIGH();
+  
+  /* Send dummy byte 0xFF, 10 times with CS high */
+  /* Rise CS and MOSI for 80 clocks cycles */
+  for (counter = 0; counter <= 9; counter++)
+  {
+    /* Send dummy byte 0xFF */
+    SD_IO_WriteByte(SD_DUMMY_BYTE);
+  }
+}
+
+/**
+  * @brief  Writes a byte on the SD.
+  * @param  Data: byte to send.
+  * @retval None
+  */
+void SD_IO_WriteByte(uint8_t Data)
+{
+  /* Send the byte */
+  SPIx_Write(Data);
+}
+
+/**
+  * @brief  Reads a byte from the SD.
+  * @param  None
+  * @retval The received byte.
+  */
+uint8_t SD_IO_ReadByte(void)
+{
+  uint8_t data = 0;
+  
+  /* Get the received data */
+  data = SPIx_Read();
+
+  /* Return the shifted data */
+  return data;
+}
+
+/**
+  * @brief  Sends 5 bytes command to the SD card and get response.
+  * @param  Cmd: The user expected command to send to SD card.
+  * @param  Arg: The command argument
+  * @param  Crc: The CRC
+  * @param  Response: Expected response from the SD card
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef SD_IO_WriteCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc, uint8_t Response)
+{
+  uint32_t counter = 0x00;
+  uint8_t frame[6];
+
+  /* Prepare Frame to send */
+  frame[0] = (Cmd | 0x40);         /* Construct byte 1 */
+  frame[1] = (uint8_t)(Arg >> 24); /* Construct byte 2 */
+  frame[2] = (uint8_t)(Arg >> 16); /* Construct byte 3 */
+  frame[3] = (uint8_t)(Arg >> 8);  /* Construct byte 4 */
+  frame[4] = (uint8_t)(Arg);       /* Construct byte 5 */
+  frame[5] = (Crc);                /* Construct byte 6 */
+  
+  /* SD chip select low */
+  SD_CS_LOW();
+    
+  /* Send Frame */
+  for (counter = 0; counter < 6; counter++)
+  {
+    SD_IO_WriteByte(frame[counter]); /* Send the Cmd bytes */
+  }
+
+  if(Response != SD_NO_RESPONSE_EXPECTED)
+  {
+    return SD_IO_WaitResponse(Response);
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Waits response from the SD card
+  * @param  Response: Expected response from the SD card
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef SD_IO_WaitResponse(uint8_t Response)
+{
+  uint32_t timeout = 0xFFFF;
+
+  /* Check if response is got or a timeout is happen */
+  while ((SD_IO_ReadByte() != Response) && timeout)
+  {
+    timeout--;
+  }
+
+  if (timeout == 0)
+  {
+    /* After time out */
+    return HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Right response got */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Sends dummy byte with CS High.
+  * @param  None
+  * @retval None
+  */
+void SD_IO_WriteDummy(void)
+{
+  /* SD chip select high */
+  SD_CS_HIGH();
+  
+  /* Send Dummy byte 0xFF */
+  SD_IO_WriteByte(SD_DUMMY_BYTE);
+}
+
+/********************************* LINK LCD ***********************************/
+/**
+  * @brief  Initializes the LCD.
+  * @param  None
+  * @retval None
+  */
+void LCD_IO_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStruct;
+   
+  /* LCD_CS_GPIO and LCD_DC_GPIO Periph clock enable */
+  LCD_CS_GPIO_CLK_ENABLE();
+  LCD_DC_GPIO_CLK_ENABLE();
+  
+  /* Configure LCD_CS_PIN pin: LCD Card CS pin */
+  GPIO_InitStruct.Pin = LCD_CS_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+  HAL_GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStruct);
+
+  /* Configure LCD_DC_PIN pin: LCD Card DC pin */
+  GPIO_InitStruct.Pin = LCD_DC_PIN;
+  HAL_GPIO_Init(LCD_DC_GPIO_PORT, &GPIO_InitStruct);
+  
+  /* LCD chip select high */
+  LCD_CS_HIGH();
+  
+  /* LCD SPI Config */
+  SPIx_Init();
+}
+
+/**
+  * @brief  Writes command to select the LCD register.
+  * @param  LCDReg: Address of the selected register.
+  * @retval None
+  */
+void LCD_IO_WriteReg(uint8_t LCDReg)
+{
+  /* Reset LCD control line CS */
+  LCD_CS_LOW();
+  
+  /* Set LCD data/command line DC to Low */
+  LCD_DC_LOW();
+    
+  /* Send Command */
+  SPIx_Write(LCDReg);
+  
+  /* Deselect : Chip Select high */
+  LCD_CS_HIGH();
+}
+
+/**
+  * @brief  Writes data to select the LCD register.
+  *         This function must be used after st7735_WriteReg() function
+  * @param  Data: data to write to the selected register.
+  * @retval None
+  */
+void LCD_IO_WriteData(uint8_t Data)
+{
+  /* Reset LCD control line CS */
+  LCD_CS_LOW();
+  
+  /* Set LCD data/command line DC to High */
+  LCD_DC_HIGH();
+
+  /* Send Data */
+  SPIx_Write(Data);
+  
+  /* Deselect : Chip Select high */
+  LCD_CS_HIGH();
+}
+
+/**
+  * @brief  Writes register value.
+  * @param  pData: Pointer on the register value
+  * @param  Size: Size of byte to transmit to the register
+  * @retval None
+  */
+void LCD_IO_WriteMultipleData(uint8_t *pData, uint32_t Size)
+{
+  uint32_t counter = 0;
+  
+  /* Reset LCD control line CS */
+  LCD_CS_LOW();
+  
+  /* Set LCD data/command line DC to High */
+  LCD_DC_HIGH();
+
+  if (Size == 1)
+  {
+    /* Only 1 byte to be sent to LCD - general interface can be used */
+    /* Send Data */
+    SPIx_Write(*pData);
+  }
+  else
+  {
+    /* Several data should be sent in a raw */
+    /* Direct SPI accesses for optimization */
+    for (counter = Size; counter != 0; counter--)
+    {
+      while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE)
+      {
+      }
+      /* Need to invert bytes for LCD*/
+      *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *(pData+1);
+      
+      while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE)
+      {
+      }
+      *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *pData;
+      counter--;
+      pData += 2;
+      }
+  
+    /* Wait until the bus is ready before releasing Chip select */ 
+    while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_BSY) != RESET)
+    {
+    } 
+  } 
+  
+  /* Deselect : Chip Select high */
+  LCD_CS_HIGH();
+}
+
+/**
+  * @brief  Wait for loop in ms.
+  * @param  Delay in ms.
+  * @retval None
+  */
+void LCD_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/******************************* LINK JOYSTICK ********************************/
+/**
+  * @brief  Initializes ADC MSP.
+  * @param  None
+  * @retval None
+  */
+static void ADCx_MspInit(ADC_HandleTypeDef *hadc)
+{
+  GPIO_InitTypeDef  GPIO_InitStruct;
+  
+  /*** Configure the GPIOs ***/  
+  /* Enable GPIO clock */
+  NUCLEO_ADCx_GPIO_CLK_ENABLE();
+  
+  /* Configure the selected ADC Channel as analog input */
+  GPIO_InitStruct.Pin = NUCLEO_ADCx_GPIO_PIN ;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(NUCLEO_ADCx_GPIO_PORT, &GPIO_InitStruct);
+  
+  /*** Configure the ADC peripheral ***/ 
+  /* Enable ADC clock */
+  NUCLEO_ADCx_CLK_ENABLE(); 
+}
+
+/**
+  * @brief  Initializes ADC HAL.
+  * @param  None
+  * @retval None
+  */
+static void ADCx_Init(void)
+{
+  if(HAL_ADC_GetState(&hnucleo_Adc) == HAL_ADC_STATE_RESET)
+  {
+    /* ADC Config */
+    hnucleo_Adc.Instance                   = NUCLEO_ADCx;
+    hnucleo_Adc.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV4; /* (must not exceed 36MHz) */
+    hnucleo_Adc.Init.Resolution            = ADC_RESOLUTION12b;
+    hnucleo_Adc.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+    hnucleo_Adc.Init.ContinuousConvMode    = DISABLE;
+    hnucleo_Adc.Init.DiscontinuousConvMode = DISABLE;
+    hnucleo_Adc.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+    hnucleo_Adc.Init.EOCSelection          = EOC_SINGLE_CONV;
+    hnucleo_Adc.Init.NbrOfConversion       = 1;
+    hnucleo_Adc.Init.DMAContinuousRequests = DISABLE;    
+    
+    ADCx_MspInit(&hnucleo_Adc);
+    HAL_ADC_Init(&hnucleo_Adc);
+  }
+}
+
+/**
+  * @brief  Configures joystick available on adafruit 1.8" TFT shield 
+  *         managed through ADC to detect motion.
+  * @param  None
+  * @retval Joystickstatus (0=> success, 1=> fail) 
+  */
+uint8_t BSP_JOY_Init(void)
+{
+  uint8_t status = 1;
+   
+  ADCx_Init();
+   
+  /* Select the ADC Channel to be converted */
+  sConfig.Channel = NUCLEO_ADCx_CHANNEL;
+  sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
+  sConfig.Rank = 1;
+  status = HAL_ADC_ConfigChannel(&hnucleo_Adc, &sConfig);
+  
+  /* Return Joystick initialization status */
+  return status;
+}
+
+/**
+  * @brief  Returns the Joystick key pressed.
+  * @note   To know which Joystick key is pressed we need to detect the voltage
+  *         level on each key output
+  *           - None  : 3.3 V / 4095
+  *           - SEL   : 1.055 V / 1308
+  *           - DOWN  : 0.71 V / 88
+  *           - LEFT  : 3.0 V / 3720 
+  *           - RIGHT : 0.595 V / 737
+  *           - UP    : 1.65 V / 2046
+  * @retval JOYState_TypeDef: Code of the Joystick key pressed.
+  */
+JOYState_TypeDef BSP_JOY_GetState(void)
+{
+  JOYState_TypeDef state;
+  uint16_t  keyconvertedvalue = 0;
+  
+  /* Start the conversion process */
+  HAL_ADC_Start(&hnucleo_Adc);
+  
+  /* Wait for the end of conversion */
+  HAL_ADC_PollForConversion(&hnucleo_Adc, 10);
+  
+  /* Check if the continuous conversion of regular channel is finished */
+  if(HAL_ADC_GetState(&hnucleo_Adc) == HAL_ADC_STATE_EOC_REG)
+  {
+    /* Get the converted value of regular channel */
+    keyconvertedvalue = HAL_ADC_GetValue(&hnucleo_Adc);
+  }
+  
+  if((keyconvertedvalue > 2010) && (keyconvertedvalue < 2090))
+  {
+    state = JOY_UP;
+  }
+  else if((keyconvertedvalue > 680) && (keyconvertedvalue < 780))
+  {
+    state = JOY_RIGHT;
+  }
+  else if((keyconvertedvalue > 1270) && (keyconvertedvalue < 1350))
+  {
+    state = JOY_SEL;
+  }
+  else if((keyconvertedvalue > 50) && (keyconvertedvalue < 130))
+  {
+    state = JOY_DOWN;
+  }
+  else if((keyconvertedvalue > 3680) && (keyconvertedvalue < 3760))
+  {
+    state = JOY_LEFT;
+  }
+  else
+  {
+    state = JOY_NONE;
+  }
+  
+  /* Loop while a key is pressed */
+  if(state != JOY_NONE)
+  { 
+    keyconvertedvalue = HAL_ADC_GetValue(&hnucleo_Adc);  
+  }
+  /* Return the code of the Joystick key pressed */
+  return state;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */    
+
+/**
+  * @}
+  */ 
+    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_nucleo.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_nucleo.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/stm32f4xx_nucleo.h	(revision 303)
@@ -0,0 +1,287 @@
+/** 
+  ******************************************************************************
+  * @file    stm32f4xx_nucleo.h
+  * @author  MCD Application Team
+  * @version V1.2.2
+  * @date    14-August-2015
+  * @brief   This file contains definitions for:
+  *          - LEDs and push-button available on STM32F4XX-Nucleo Kit 
+  *            from STMicroelectronics
+  *          - LCD, joystick and microSD available on Adafruit 1.8" TFT LCD 
+  *            shield (reference ID 802)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4XX_NUCLEO_H
+#define __STM32F4XX_NUCLEO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+   
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32F4XX_NUCLEO
+  * @{
+  */
+
+/** @addtogroup STM32F4XX_NUCLEO_LOW_LEVEL
+  * @{
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED2 = 0
+}Led_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_USER = 0,
+  /* Alias */
+  BUTTON_KEY  = BUTTON_USER
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+}ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE  = 0,
+  JOY_SEL   = 1,
+  JOY_DOWN  = 2,
+  JOY_LEFT  = 3,
+  JOY_RIGHT = 4,
+  JOY_UP    = 5
+}JOYState_TypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief Define for STM32F4XX_NUCLEO board  
+  */ 
+#if !defined (USE_STM32F4XX_NUCLEO)
+ #define USE_STM32F4XX_NUCLEO
+#endif
+
+/** @addtogroup STM32F4XX_NUCLEO_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                                    1
+
+#define LED2_PIN                                GPIO_PIN_5
+#define LED2_GPIO_PORT                          GPIOA
+#define LED2_GPIO_CLK_ENABLE()                  __GPIOA_CLK_ENABLE()
+#define LED2_GPIO_CLK_DISABLE()                 __GPIOA_CLK_DISABLE()  
+
+#define LEDx_GPIO_CLK_ENABLE(__INDEX__)    do{if((__INDEX__) == 0) LED2_GPIO_CLK_ENABLE(); \
+                                             }while(0)
+#define LEDx_GPIO_CLK_DISABLE(__INDEX__)    do{if((__INDEX__) == 0) LED2_GPIO_CLK_DISABLE(); \
+                                              }while(0)
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM32F4XX_NUCLEO_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                                 1  
+
+/**
+  * @brief Key push-button
+  */
+#define USER_BUTTON_PIN                         GPIO_PIN_13
+#define USER_BUTTON_GPIO_PORT                   GPIOC
+#define USER_BUTTON_GPIO_CLK_ENABLE()           __HAL_RCC_GPIOC_CLK_ENABLE()   
+#define USER_BUTTON_GPIO_CLK_DISABLE()          __HAL_RCC_GPIOC_CLK_DISABLE()  
+#define USER_BUTTON_EXTI_LINE                   GPIO_PIN_13
+#define USER_BUTTON_EXTI_IRQn                   EXTI15_10_IRQn
+/* Aliases */
+#define KEY_BUTTON_PIN                          USER_BUTTON_PIN
+#define KEY_BUTTON_GPIO_PORT                    USER_BUTTON_GPIO_PORT
+#define KEY_BUTTON_GPIO_CLK_ENABLE()            USER_BUTTON_GPIO_CLK_ENABLE()
+#define KEY_BUTTON_GPIO_CLK_DISABLE()           USER_BUTTON_GPIO_CLK_DISABLE()
+#define KEY_BUTTON_EXTI_LINE                    USER_BUTTON_EXTI_LINE
+#define KEY_BUTTON_EXTI_IRQn                    USER_BUTTON_EXTI_IRQn
+
+
+#define BUTTONx_GPIO_CLK_ENABLE(__BUTTON__)    do { if((__BUTTON__) == BUTTON_USER) { USER_BUTTON_GPIO_CLK_ENABLE(); } } while(0)
+
+#define BUTTONx_GPIO_CLK_DISABLE(__BUTTON__)   do { if((__BUTTON__) == BUTTON_USER) { USER_BUTTON_GPIO_CLK_DISABLE(); } } while(0)
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32F4XX_NUCLEO_LOW_LEVEL_BUS
+  * @{
+  */
+/*############################### SPI1 #######################################*/
+#define NUCLEO_SPIx                                     SPI1
+#define NUCLEO_SPIx_CLK_ENABLE()                        __SPI1_CLK_ENABLE()
+
+#define NUCLEO_SPIx_SCK_AF                              GPIO_AF5_SPI1
+#define NUCLEO_SPIx_SCK_GPIO_PORT                       GPIOA
+#define NUCLEO_SPIx_SCK_PIN                             GPIO_PIN_5
+#define NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE()               __GPIOA_CLK_ENABLE()
+#define NUCLEO_SPIx_SCK_GPIO_CLK_DISABLE()              __GPIOA_CLK_DISABLE()
+
+#define NUCLEO_SPIx_MISO_MOSI_AF                        GPIO_AF5_SPI1
+#define NUCLEO_SPIx_MISO_MOSI_GPIO_PORT                 GPIOA
+#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE()         __GPIOA_CLK_ENABLE()
+#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_DISABLE()        __GPIOA_CLK_DISABLE()
+#define NUCLEO_SPIx_MISO_PIN                            GPIO_PIN_6
+#define NUCLEO_SPIx_MOSI_PIN                            GPIO_PIN_7
+/* Maximum Timeout values for flags waiting loops. These timeouts are not based
+   on accurate values, they just guarantee that the application will not remain
+   stuck if the SPI communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define NUCLEO_SPIx_TIMEOUT_MAX                   1000
+
+/**
+  * @brief  SD Control Lines management
+  */
+#define SD_CS_LOW()       HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_RESET)
+#define SD_CS_HIGH()      HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_SET)
+
+/**
+  * @brief  LCD Control Lines management
+  */
+#define LCD_CS_LOW()      HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_RESET)
+#define LCD_CS_HIGH()     HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_SET)
+#define LCD_DC_LOW()      HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_RESET)
+#define LCD_DC_HIGH()     HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_SET)
+     
+/**
+  * @brief  SD Control Interface pins
+  */
+#define SD_CS_PIN                                 GPIO_PIN_5
+#define SD_CS_GPIO_PORT                           GPIOB
+#define SD_CS_GPIO_CLK_ENABLE()                 __GPIOB_CLK_ENABLE()
+#define SD_CS_GPIO_CLK_DISABLE()                __GPIOB_CLK_DISABLE()
+
+/**
+  * @brief  LCD Control Interface pins
+  */
+#define LCD_CS_PIN                                 GPIO_PIN_6
+#define LCD_CS_GPIO_PORT                           GPIOB
+#define LCD_CS_GPIO_CLK_ENABLE()                 __GPIOB_CLK_ENABLE()
+#define LCD_CS_GPIO_CLK_DISABLE()                __GPIOB_CLK_DISABLE()
+    
+/**
+  * @brief  LCD Data/Command Interface pins
+  */
+#define LCD_DC_PIN                                 GPIO_PIN_9
+#define LCD_DC_GPIO_PORT                           GPIOA
+#define LCD_DC_GPIO_CLK_ENABLE()                 __GPIOA_CLK_ENABLE()
+#define LCD_DC_GPIO_CLK_DISABLE()                __GPIOA_CLK_DISABLE()
+
+/*################################ ADC1 ######################################*/
+/**
+  * @brief  ADC Interface pins
+  *         used to detect motion of Joystick available on Adafruit 1.8" TFT shield
+  */
+#define NUCLEO_ADCx                                 ADC1
+#define NUCLEO_ADCx_CLK_ENABLE()                  __ADC1_CLK_ENABLE()
+
+#define NUCLEO_ADCx_CHANNEL                       ADC_CHANNEL_8
+   
+#define NUCLEO_ADCx_GPIO_PORT                       GPIOB
+#define NUCLEO_ADCx_GPIO_PIN                        GPIO_PIN_0
+#define NUCLEO_ADCx_GPIO_CLK_ENABLE()             __GPIOB_CLK_ENABLE()
+#define NUCLEO_ADCx_GPIO_CLK_DISABLE()            __GPIOB_CLK_DISABLE()
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Exported_Macros
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32F4XX_NUCLEO_LOW_LEVEL_Exported_Functions
+  * @{
+  */
+uint32_t         BSP_GetVersion(void);  
+void             BSP_LED_Init(Led_TypeDef Led);
+void             BSP_LED_On(Led_TypeDef Led);
+void             BSP_LED_Off(Led_TypeDef Led);
+void             BSP_LED_Toggle(Led_TypeDef Led);
+void             BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode);
+uint32_t         BSP_PB_GetState(Button_TypeDef Button);
+uint8_t          BSP_JOY_Init(void);
+JOYState_TypeDef BSP_JOY_GetState(void);
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4XX_NUCLEO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/system_stm32f4xx.c
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/system_stm32f4xx.c	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/system_stm32f4xx.c	(revision 303)
@@ -0,0 +1,278 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @version V1.2.1
+  * @date    09-October-2015
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f4xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 16000000;
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+//    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/systemclock_config.c
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/systemclock_config.c	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/stm32fcube/systemclock_config.c	(revision 303)
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    Templates/Src/main.c 
+  * @author  MCD Application Team
+  * @version V1.1.2
+  * @date    09-October-2015
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+#include "stm32f4xx_nucleo.h"
+
+extern void Error_Handler();
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow : 
+  *            System Clock source            = PLL (HSI)
+  *            SYSCLK(Hz)                     = 84000000
+  *            HCLK(Hz)                       = 84000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 2
+  *            APB2 Prescaler                 = 1
+  *            HSI Frequency(Hz)              = 16000000
+  *            PLL_M                          = 16
+  *            PLL_N                          = 336
+  *            PLL_P                          = 4
+  *            PLL_Q                          = 7
+  *            VDD(V)                         = 3.3
+  *            Main regulator output voltage  = Scale2 mode
+  *            Flash Latency(WS)              = 2 
+  * @param  None
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable Power Control clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* The voltage scaling allows optimizing the power consumption when the device is 
+     clocked below the maximum system frequency, to update the voltage scaling value 
+     regarding system frequency refer to product datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+  /* Enable HSI Oscillator and activate PLL with HSI as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = 0x10;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = 16;
+  RCC_OscInitStruct.PLL.PLLN = 336;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 
+     clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;  
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;  
+  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }  
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target.tf
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target.tf	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target.tf	(revision 303)
@@ -0,0 +1,8 @@
+$ 
+$     ãã¹2ã®ã¿ã¼ã²ããä¾å­ãã³ãã¬ã¼ãï¼NUCLEO_F401REç¨ï¼
+$ 
+
+$ 
+$  ãããä¾å­ã®ãã³ãã¬ã¼ããã¡ã¤ã«ã®ã¤ã³ã¯ã«ã¼ã
+$ 
+$INCLUDE "core.tf"$
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_asm.inc
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_asm.inc	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_asm.inc	(revision 303)
@@ -0,0 +1,1 @@
+#include "core_asm.inc"
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_cfg1_out.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_cfg1_out.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_cfg1_out.h	(revision 303)
@@ -0,0 +1,11 @@
+/*
+ *		cfg1_out.cããªã³ã¯ããããã«å¿
+è¦ãªã¹ã¿ãã®å®ç¾©
+ */
+
+void _kernel_start(void){}
+
+/*
+ *  ãããä¾å­ã®ã¹ã¿ãã®å®ç¾© 
+ */
+#include <chip_cfg1_out.h>
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_check.tf
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_check.tf	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_check.tf	(revision 303)
@@ -0,0 +1,8 @@
+$ 
+$     ãã¹3ã®ã¿ã¼ã²ããä¾å­ãã³ãã¬ã¼ãï¼NUCLEO_F401REç¨ï¼
+$ 
+
+$ 
+$  ãã¹3ã®ãããä¾å­ã®ãã³ãã¬ã¼ãã®ã¤ã³ã¯ã«ã¼ã
+$ 
+$INCLUDE "core_check.tf"$
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_check.trb
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_check.trb	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_check.trb	(revision 303)
@@ -0,0 +1,67 @@
+# ======================================================================
+# 
+#   TOPPERS/ASP Kernel
+#       Toyohashi Open Platform for Embedded Real-Time Systems/
+#       Advanced Standard Profile Kernel
+#  
+#   Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+#                               Toyohashi Univ. of Technology, JAPAN
+#   Copyright (C) 2005-2014 by Embedded and Real-Time Systems Laboratory
+#               Graduate School of Information Science, Nagoya Univ., JAPAN
+#  
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+# 
+#   @(#) $Id: target_check.trb 648 2016-02-20 00:50:56Z ertl-honda $
+#
+# =====================================================================
+
+# 
+#     ãã¹3ã®ã¿ã¼ã²ããä¾å­ãã³ãã¬ã¼ãï¼NUCLEO_F401REç¨ï¼
+# 
+
+# 
+#  ãã¹3ã®ã³ã¢ä¾å­ã®ãã³ãã¬ã¼ãã®ã¤ã³ã¯ã«ã¼ã
+# 
+IncludeTrb("core_check.trb")
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.cfg
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.cfg	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.cfg	(revision 303)
@@ -0,0 +1,7 @@
+/*
+ *		ã«ã¼ãã«å®è£
+ã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ *
+ *  $Id: target_kernel.cfg 648 2016-02-20 00:50:56Z ertl-honda $
+ */
+INCLUDE("target_timer.cfg")
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.h	(revision 303)
@@ -0,0 +1,90 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+
+/*
+ *  kernel.hã®ã¿ã¼ã²ããä¾å­é¨ï¼NUCLEO_F401REç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼kernel.hã§ã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡
+ *  ã¤ã«ããç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼ã
+ *  ããåã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ãããã«ä¾å­ãã¦ãã
+ *  ãï¼
+ */
+
+#ifndef TOPPERS_TARGET_KERNEL_H
+#define TOPPERS_TARGET_KERNEL_H
+
+#ifdef USE_TIM_AS_HRT
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ã¿ã¤ãå¨æ
+ *
+ *  ã¿ã¤ãå¨æã2^32ã®å ´åã«ã¯ï¼ãã®ãã¯ã­ãå®ç¾©ããªãï¼
+ */
+#undef TCYC_HRTCNT
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ã«ã¦ã³ãå¤ã®é²ã¿å¹
+
+ */
+#define TSTEP_HRTCNT	1U
+
+#endif /* USE_TIM_AS_HRT */
+
+/*
+ *  ãããã§å
+±éãªå®ç¾©
+ */
+#include "chip_kernel.h"
+
+#endif /* TOPPERS_TARGET_KERNEL_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.trb
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.trb	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel.trb	(revision 303)
@@ -0,0 +1,67 @@
+# ======================================================================
+# 
+#   TOPPERS/ASP Kernel
+#       Toyohashi Open Platform for Embedded Real-Time Systems/
+#       Advanced Standard Profile Kernel
+#  
+#   Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+#                               Toyohashi Univ. of Technology, JAPAN
+#   Copyright (C) 2005-2016 by Embedded and Real-Time Systems Laboratory
+#               Graduate School of Information Science, Nagoya Univ., JAPAN
+#  
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+#  
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+# 
+#   @(#) $Id: target_kernel.trb 648 2016-02-20 00:50:56Z ertl-honda $
+#
+# =====================================================================
+
+# 
+#     ãã¹2ã®ã¿ã¼ã²ããä¾å­ãã³ãã¬ã¼ãï¼NUCLEO_F401REç¨ï¼
+# 
+
+# 
+#  ã³ã¢ä¾å­ãã³ãã¬ã¼ãã®ã¤ã³ã¯ã«ã¼ã
+# 
+IncludeTrb("core_kernel.trb")
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel_impl.c
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel_impl.c	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel_impl.c	(revision 303)
@@ -0,0 +1,225 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2005-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+
+/*
+ * ã¿ã¼ã²ããä¾å­ã¢ã¸ã¥ã¼ã«ï¼NUCLEO_F401REç¨ï¼
+ */
+#include "kernel_impl.h"
+#include <sil.h>
+
+/*
+ *  èµ·åç´å¾ã®åæå(system_stm32f4xx.c)
+ */
+extern void SystemInit(void);
+
+/*
+ *  ã¯ã­ãã¯ã®åæå(systemclock_config.c)
+ */
+extern void SystemClock_Config(void);
+
+/*
+ *  ãã¼ãåºåç¨ã®UARTã®åæå
+ */
+static void usart_early_init(void);
+
+/*
+ *  ã¨ã©ã¼æã®å¦ç
+ */
+extern void Error_Handler(void);
+
+/*
+ *  èµ·åæã®ãã¼ãã¦ã§ã¢åæåå¦ç
+ */
+void
+hardware_init_hook(void) {
+	SystemInit();
+
+	/*
+	 *  -fdata-sectionsãä½¿ç¨ããã¨istkãåé¤ããï¼
+	 *  cfgã®ãã¹3ã®ãã§ãã¯ãã¨ã©ã¼ã¨ãªãããï¼
+	 *  åé¤ãããªãããã«ãã 
+	 */
+	SystemCoreClock = (uint32_t)istk;
+}
+
+/*
+ *  cfgã®pass3ã§ã¨ã©ã¼ã«ãªããªãããã«
+ */
+extern const ID _kernel_tmax_tskid;
+extern const ID _kernel_tmax_semid;
+extern const ID _kernel_tmax_flgid;
+extern const ID _kernel_tmax_dtqid;
+
+volatile ID dummy;
+
+/*
+ * ã¿ã¼ã²ããä¾å­é¨ åæåå¦ç
+ */
+void
+target_initialize(void)
+{
+	dummy = _kernel_tmax_tskid;
+	dummy = _kernel_tmax_semid;
+	dummy = _kernel_tmax_flgid;
+	dummy = _kernel_tmax_dtqid;
+
+	/*
+	 *  HALã«ããåæå
+	 *  HAL_Init() : stm32f4xx_hal.c ã®å
+å®¹ããå¿
+è¦ãªåæåã®ã¿å¼ã³åºãï¼
+	 */
+	__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+	__HAL_FLASH_DATA_CACHE_ENABLE();
+	__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+
+	/*
+	 *  ã¯ã­ãã¯ã®åæå
+	 */
+	SystemClock_Config();
+
+	/*
+	 *  ã³ã¢ä¾å­é¨ã®åæå
+	 */
+	core_initialize();
+
+	/*
+	 *  ä½¿ç¨ããããªãã§ã©ã«ã«ã¯ã­ãã¯ãä¾çµ¦
+	 */
+
+	/*
+	 *  UserLEDã®åæå
+	 */
+	BSP_LED_Init(LED2);
+
+	/*
+	 *  ãã¼ãã¼åºåç¨ã®ã·ãªã¢ã«åæå
+	 */
+	usart_early_init();
+}
+
+/*
+ * ã¿ã¼ã²ããä¾å­é¨ çµäºå¦ç
+ */
+void
+target_exit(void)
+{
+	/* ãããä¾å­é¨ã®çµäºå¦ç */
+	core_terminate();
+	while(1);
+}
+
+static UART_HandleTypeDef UartHandle;
+
+void
+usart_early_init()
+{
+	usart_low_init();
+
+	UartHandle.Instance          = USART_NAME; 
+	UartHandle.Init.BaudRate     = BPS_SETTING;
+	UartHandle.Init.WordLength   = UART_WORDLENGTH_9B;
+	UartHandle.Init.StopBits     = UART_STOPBITS_1;
+	UartHandle.Init.Parity       = UART_PARITY_ODD;
+	UartHandle.Init.HwFlowCtl    = UART_HWCONTROL_NONE;
+	UartHandle.Init.Mode         = UART_MODE_TX_RX;
+	UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+    
+	if(HAL_UART_Init(&UartHandle) != HAL_OK) {
+		Error_Handler();
+	}
+};
+
+/*
+ * ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ */
+void
+target_fput_log(char c)
+{
+	char cr = '\r';
+	if (c == '\n') {
+		HAL_UART_Transmit(&UartHandle, (uint8_t *)&cr, 1, 0xFFFF); 
+	}
+	HAL_UART_Transmit(&UartHandle, (uint8_t *)&c, 1, 0xFFFF); 
+}
+
+/*
+ * ã¨ã©ã¼çºçæã®å¦ç
+ */
+void
+Error_Handler(void){
+	volatile int loop;
+	BSP_LED_Init(LED2);
+	while(1){
+		for(loop = 0; loop < 0x100000; loop++);
+		BSP_LED_Toggle(LED2);
+	}
+}
+
+#include "time_event.h"
+
+/*
+ *  HALå®è¡ç¨ã®é¢æ°
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  return HAL_OK;
+}
+
+uint32_t HAL_GetTick(void)
+{
+  return current_hrtcnt/1000;
+}
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel_impl.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel_impl.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_kernel_impl.h	(revision 303)
@@ -0,0 +1,114 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2005-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ä¸­å±±éº»èãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+#ifndef TOPPERS_TARGET_KERNEL_IMPL_H
+#define TOPPERS_TARGET_KERNEL_IMPL_H
+
+/*
+ * ã¿ã¼ã²ããä¾å­é¨ã¢ã¸ã¥ã¼ã«ï¼NUCLEO_F401REç¨ï¼
+ *
+ * ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ï¼kernel_impl.hã®ã¿ã¼
+ * ã²ããä¾å­é¨ã®ä½ç½®ä»ãã¨ãªãï¼
+ */
+#include "nucleo_f401re.h"
+
+/*
+ *  TBITW_IPRI ã®å®ç¾©ã®ããèª­ã¿è¾¼ã¿
+ */
+#include <sil.h>
+
+/*
+ *  ããã©ã«ãã®éã¿ã¹ã¯ã³ã³ãã­ã¹ãç¨ã®ã¹ã¿ãã¯é åã®å®ç¾©
+ */
+#define DEFAULT_ISTKSZ			(0x1000)		/* 4KByte */
+
+/*
+ * IDLEå¦çã®å®ç¾©
+ *
+ * ãµã¹ãã³ãæã«OpenOCDãããã°ãã¼ã«ãä½¿ããªããªãåé¡ã®å¯¾å¿
+ * WFIç­ã§ãµã¹ãã³ããã¦ãããã­ã°ã©ã ã«å¯¾ãã¦ï¼ãã©ãã·ã¥ROM
+ * æ¸ãè¾¼ã¿ãåºæ¥ãªããªãããï¼IDELå¦çå¤æ´ï¼
+ */
+#define TOPPERS_CUSTOM_IDEL
+#define toppers_asm_custom_idle		\
+	msr		basepri, r0;			\
+	msr		basepri, r1;
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ä¾å­ã®åæå
+ */
+extern void	target_initialize(void);
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ã®çµäº
+ *
+ *  ã·ã¹ãã ãçµäºããæã«ä½¿ãï¼
+ */
+extern void	target_exit(void) NoReturn;
+
+/*
+ *  ã¨ã©ã¼çºçæã®å¦ç
+ */
+extern void Error_Handler(void);
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  ãããä¾å­ã¢ã¸ã¥ã¼ã«
+ */
+#include <chip_kernel_impl.h>
+
+#endif /* TOPPERS_TARGET_KERNEL_IMPL_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_rename.def
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_rename.def	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_rename.def	(revision 303)
@@ -0,0 +1,5 @@
+INCLUDE	"arm_m_gcc/stm32f4xx_stm32cube/chip"
+
+#target_config.c
+target_initialize
+target_exit
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_rename.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_rename.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_rename.h	(revision 303)
@@ -0,0 +1,26 @@
+/* This file is generated from target_rename.def by genrename. */
+
+#ifndef TOPPERS_TARGET_RENAME_H
+#define TOPPERS_TARGET_RENAME_H
+
+
+/*
+ * target_config.c
+ */
+#define target_initialize			_kernel_target_initialize
+#define target_exit					_kernel_target_exit
+
+#ifdef TOPPERS_LABEL_ASM
+
+
+/*
+ * target_config.c
+ */
+#define _target_initialize			__kernel_target_initialize
+#define _target_exit				__kernel_target_exit
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "chip_rename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_serial.cfg
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_serial.cfg	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_serial.cfg	(revision 303)
@@ -0,0 +1,8 @@
+/*
+ *  SIOãã©ã¤ãï¼NUCLEO_F401REç¨ï¼ã®ã³ã³ãã£ã°ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ */
+
+#include "target_serial.h"
+ATT_INI({ TA_NULL, 0, sio_initialize });
+CFG_INT(INTNO_SIO, { TA_ENAINT|INTATR_SIO, INTPRI_SIO });
+CRE_ISR(ISR_SIO, { TA_NULL, SIO_PORTID, INTNO_SIO, sio_isr, 1 });
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_serial.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_serial.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_serial.h	(revision 303)
@@ -0,0 +1,79 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2011,2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_serial.h 2612 2014-01-21 06:01:27Z ertl-honda $
+ */
+
+/*
+ * ã·ãªã¢ã«I/Oããã¤ã¹ï¼SIOï¼ãã©ã¤ã
+ */
+
+#ifndef TOPPERS_TARGET_SERIAL_H
+#define TOPPERS_TARGET_SERIAL_H
+
+/*
+ *  ã·ãªã¢ã«ãã¼ãã®åªå
+åº¦ã¨å²ãè¾¼ã¿å±æ§
+ */
+#define INTPRI_SIO		-3				/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_SIO		0				/* å²è¾¼ã¿å±æ§ */
+
+#define INHNO_SIO		(USART2_IRQn + 16)
+#define INTNO_SIO		(USART2_IRQn + 16)
+
+/*
+ *  ãããä¾å­ã¢ã¸ã¥ã¼ã«
+ */
+#include "usart.h"
+
+#endif /* TOPPERS_TARGET_SERIAL_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_sil.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_sil.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_sil.h	(revision 303)
@@ -0,0 +1,73 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ * 
+ *  Copyright (C) 2007,2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+
+/*
+ *  sil.hã®ã¿ã¼ã²ããä¾å­é¨ï¼NUCLEO_F401REç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼sil.hã®å
+é ­ã§ã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡
+ *  ã¤ã«ããã¯ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼
+ *  ãããåã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ãããã«ä¾å­ãã¦ã
+ *  ããï¼
+ */
+
+#ifndef TOPPERS_TARGET_SIL_H
+#define TOPPERS_TARGET_SIL_H
+
+/*
+ *  ãããã§å
+±éãªå®ç¾© 
+ */
+#include <chip_sil.h>
+
+#endif /* TOPPERS_TARGET_SIL_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_stddef.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_stddef.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_stddef.h	(revision 303)
@@ -0,0 +1,105 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ * 
+ *  Copyright (C) 2007,2011,2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+
+/*
+ *  t_stddef.hã®ã¿ã¼ã²ããä¾å­é¨ï¼NUCLEO_F401REç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼t_stddef.hã®å
+é ­ã§ã¤ã³ã¯ã«ã¼ããããï¼
+ *  ä»ã®ãã¡ã¤ã«ããã¯ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ä»ã®ã¤ã³ã¯ã«ã¼ã
+ *  ãã¡ã¤ã«ã«å
+ç«ã£ã¦å¦çãããããï¼ä»ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã«ä¾å­ã
+ *  ã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_TARGET_STDDEF_H
+#define TOPPERS_TARGET_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_NUCLEO_F401RE			/* ã·ã¹ãã ç¥ç§° */
+
+/*
+ *  éçºç°å¢ã§å
+±éãªå®ç¾©
+ *
+ *  éçºç°å¢ã§stdint.hãç¨æããã¦ããå ´åã«ã¯ï¼TOPPERS_STDINT_TYPE1ã®
+ *  ãã¯ã­å®ç¾©ãåé¤ãï¼stdint.hãã¤ã³ã¯ã«ã¼ãããã°ããï¼
+ */
+#ifndef TOPPERS_MACRO_ONLY
+#include <stdint.h>
+#endif /* TOPPERS_MACRO_ONLY */
+#include "tool_stddef.h"
+
+/*
+ *  ãããã§å
+±éãªå®ç¾©
+ */
+#include <chip_stddef.h>
+
+/*
+ *  ã¢ãµã¼ã·ã§ã³ã®å¤±ææã®å®è¡ä¸­æ­å¦ç
+ */
+#ifndef TOPPERS_MACRO_ONLY
+#ifndef TECSGEN
+
+Inline void
+TOPPERS_assert_abort(void)
+{
+	while (1) ;
+}
+
+#endif /* TECSGEN */
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_STDDEF_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_syssvc.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_syssvc.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_syssvc.h	(revision 303)
@@ -0,0 +1,105 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2007,2011-2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+
+/*
+ *  ã·ã¹ãã ãµã¼ãã¹ã®ã¿ã¼ã²ããä¾å­é¨ï¼NUCLEO_F401REç¨ï¼
+ *
+ *  ã·ã¹ãã ãµã¼ãã¹ã®ã¿ã¼ã²ããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ï¼ãã®ãã¡
+ *  ã¤ã«ã®å
+å®¹ã¯ï¼ã³ã³ãã¼ãã³ãè¨è¿°ãã¡ã¤ã«ã«è¨è¿°ããï¼ãã®ãã¡ã¤ã«ã¯
+ *  ç¡ããªãè¦è¾¼ã¿ï¼
+ */
+#ifndef TOPPERS_TARGET_SYSSVC_H
+#define TOPPERS_TARGET_SYSSVC_H
+
+/*
+ *  ãããå
+±æã®ãã¼ãã¦ã§ã¢è³æºã®èª­ã¿è¾¼ã¿
+ */
+#include "chip_syssvc.h"
+
+/*
+ *  èµ·åã¡ãã»ã¼ã¸ã®ã¿ã¼ã²ããã·ã¹ãã å
+ */
+#define TARGET_NAME    "NUCLEO(STM32F401RE)"
+
+/*
+ *  ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ *
+ *  ã¿ã¼ã²ããä¾å­ã®æ¹æ³ã§ï¼æå­cãè¡¨ç¤º/åºå/ä¿å­ããï¼
+ */
+extern void	target_fput_log(char c);
+
+/*
+ *  ã·ãªã¢ã«ãã¼ãæ°ã®å®ç¾©
+ */
+#define TNUM_PORT        (2)		/* ãµãã¼ãããã·ãªã¢ã«ãã¼ãã®æ° */
+#define TNUM_SIOP        (2)
+
+/*  
+ *  ãã¼ã¬ã¼ã
+ */
+#define BPS_SETTING		(115200)
+
+/*
+ *  ä½¿ç¨ããã·ãªã¢ã«ãã¼ãID
+ */
+#define SIO_PORTID		(2)
+
+/*
+ *  ã­ã°ã¿ã¹ã¯ãä½¿ç¨ãããã¼ãID
+ */
+#define LOGTASK_PORTID   SIO_PORTID
+
+#endif /* TOPPERS_TARGET_SYSSVC_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_test.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_test.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_test.h	(revision 303)
@@ -0,0 +1,71 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2007,2011,2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+
+/*
+ *		ãã¹ããã­ã°ã©ã ã®ã¿ã¼ã²ããä¾å­å®ç¾©ï¼NUCLEO_F401REç¨ï¼
+ */
+
+#ifndef TOPPERS_TARGET_TEST_H
+#define TOPPERS_TARGET_TEST_H
+
+#define STACK_SIZE			(1024)
+
+#define TASK_PORTID      2
+
+/*
+ *  ã³ã¢ä¾å­ã¢ã¸ã¥ã¼ã«ï¼ARM-Mç¨ï¼
+ */
+#include "core_test.h"
+
+#endif /* TOPPERS_TARGET_TEST_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.c
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.c	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.c	(revision 303)
@@ -0,0 +1,151 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: target_timer.c 648 2016-02-20 00:50:56Z ertl-honda $
+ */
+
+/*
+ *		ã¿ã¤ããã©ã¤ãï¼TIMç¨ï¼
+ *		 TIM2ãããªã¼ã©ã³ãã³ã°ï¼TIM5ãå²è¾¼ã¿éç¥ç¨ã«ä½¿ç¨ããï¼
+ */
+
+#include "kernel_impl.h"
+#include "time_event.h"
+#include "target_timer.h"
+#include <sil.h>
+
+/*
+ *  STM32Cubeã®TIMã®ãã³ãã«
+ */
+TIM_HandleTypeDef Tim2Handle;
+TIM_HandleTypeDef Tim5Handle;
+
+/*
+ *  ã¿ã¤ãã®èµ·åå¦ç
+ */
+void
+target_hrt_initialize(intptr_t exinf)
+{
+	/*
+	 * ããªã¼ã©ã³ãã³ã°ã¿ã¤ã
+	 */
+	/* Enable Clock. Use APB1 timer clock */
+	__HAL_RCC_TIM2_CLK_ENABLE();
+
+	Tim2Handle.Instance = TIM2;
+	Tim2Handle.Init.Period = 0xFFFFFFFF;
+	Tim2Handle.Init.Prescaler = (CPU_CLOCK_HZ/1000000);
+	Tim2Handle.Init.ClockDivision = 0;
+	Tim2Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
+
+	if(HAL_TIM_Base_Init(&Tim2Handle) != HAL_OK) {
+		/* Initialization Error */
+		Error_Handler();
+	}
+
+	if(HAL_TIM_Base_Start(&Tim2Handle) != HAL_OK) {
+		/* Initialization Error */
+		Error_Handler();
+	}
+
+	/*
+	 *  å²è¾¼ã¿éç¥ç¨ã¿ã¤ã
+	 */
+	/* Enable Clock. Use APB1 timer clock */
+	__HAL_RCC_TIM5_CLK_ENABLE();
+
+	Tim5Handle.Instance = TIM5;
+	Tim5Handle.Init.Period = 0xFF;
+	Tim5Handle.Init.Prescaler = (CPU_CLOCK_HZ/1000000);
+	Tim5Handle.Init.ClockDivision = 0;
+	Tim5Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
+
+	/* One-pulse Mode */
+	if(HAL_TIM_OnePulse_Init(&Tim5Handle,TIM_OPMODE_SINGLE) != HAL_OK) {
+		/* Initialization Error */
+		Error_Handler();
+	}
+	/* clear interrupt */
+	__HAL_TIM_CLEAR_FLAG(&Tim5Handle, TIM_SR_UIF);
+	/* enable interrupt */
+	__HAL_TIM_ENABLE_IT(&Tim5Handle, TIM_IT_UPDATE);
+}
+
+/*
+ *  ã¿ã¤ãã®åæ­¢å¦ç
+ */
+void
+target_hrt_terminate(intptr_t exinf)
+{
+	if(HAL_TIM_Base_Stop(&Tim2Handle) != HAL_OK) {
+		/* Initialization Error */
+		Error_Handler();
+	}
+	if(HAL_TIM_Base_Stop(&Tim5Handle) != HAL_OK) {
+		/* Initialization Error */
+		Error_Handler();
+	}
+}
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+void
+target_hrt_handler(void)
+{
+	/* Clear Event */
+	__HAL_TIM_CLEAR_FLAG(&Tim5Handle, TIM_SR_UIF);
+	/*
+	 *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ãå¦çããï¼
+	 */
+	signal_time();
+}
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.cfg
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.cfg	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.cfg	(revision 303)
@@ -0,0 +1,14 @@
+#include "target_timer.h"
+
+#ifdef USE_SYSTICK_AS_TIMETICK
+INCLUDE("core_timer.cfg");
+#else /* !USE_SYSTICK_AS_TIMETICK */
+#ifdef USE_TIM_AS_HRT
+ATT_INI({ TA_NULL, 0, target_hrt_initialize });
+ATT_TER({ TA_NULL, 0, target_hrt_terminate });
+CFG_INT(INTNO_TIMER, { TA_ENAINT|INTATR_TIMER, INTPRI_TIMER });
+DEF_INH(INHNO_TIMER, { TA_NULL, target_hrt_handler });
+#endif /* USE_TIM_AS_HRT */
+#endif /* USE_SYSTICK_AS_TIMETICK */
+
+
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_timer.h	(revision 303)
@@ -0,0 +1,143 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2007,2011,2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ */
+#ifndef TOPPERS_TARGET_TIMER_H
+#define TOPPERS_TARGET_TIMER_H
+
+/*
+ *  ã¿ã¤ããã©ã¤ãï¼NUCLEO_F401REç¨ï¼
+ */
+#ifdef USE_SYSTICK_AS_TIMETICK
+
+/*
+ *  ãã­ã»ããµä¾å­é¨ã§å®ç¾©ãã
+ */
+#include "core_timer.h"
+
+#else /* USE_SYSTICK_AS_TIMETICK */
+#ifdef USE_TIM_AS_HRT
+#include <sil.h>
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+#define INHNO_TIMER		(TIM5_IRQn + 16)	/* å²è¾¼ã¿ãã³ãã©çªå· */
+#define INTNO_TIMER		(TIM5_IRQn + 16)	/* å²è¾¼ã¿çªå· */
+#define INTPRI_TIMER	(TMAX_INTPRI - 1)	/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_TIMER	TA_NULL				/* å²è¾¼ã¿å±æ§ */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+#include "nucleo_f401re.h"
+
+extern TIM_HandleTypeDef Tim2Handle;
+extern TIM_HandleTypeDef Tim5Handle;
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®èµ·åå¦ç
+ */
+extern void	target_hrt_initialize(intptr_t exinf);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®åæ­¢å¦ç
+ */
+extern void	target_hrt_terminate(intptr_t exinf);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ç¾å¨ã®ã«ã¦ã³ãå¤ã®èª­åºã
+ */
+Inline HRTCNT
+target_hrt_get_current(void)
+{
+	return((HRTCNT)__HAL_TIM_GET_COUNTER(&Tim2Handle));
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã¸ã®å²è¾¼ã¿ã¿ã¤ãã³ã°ã®è¨­å®
+ *
+ *  é«åè§£è½ã¿ã¤ããï¼hrtcntã§æå®ããå¤ã«ã¦ã³ãã¢ãããããå²è¾¼ã¿ãçº
+ *  çãããããã«è¨­å®ããï¼
+ */
+Inline void
+target_hrt_set_event(HRTCNT hrtcnt)
+{
+	__HAL_TIM_SET_COUNTER(&Tim5Handle, 0);
+	__HAL_TIM_SET_AUTORELOAD(&Tim5Handle, hrtcnt);
+	HAL_TIM_Base_Start_IT(&Tim5Handle);
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ã®è¦æ±
+ *
+ */
+Inline void target_hrt_raise_event(void)
+{
+	Tim5Handle.Instance->EGR = TIM_EVENTSOURCE_UPDATE;
+}
+
+/*
+ *  å²è¾¼ã¿ã¿ã¤ãã³ã°ã«æå®ããæå¤§å¤
+ */
+#define HRTCNT_BOUND	4000000002U
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+extern void	target_hrt_handler(void);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* USE_TIM_AS_HRT */
+#endif /* USE_SYSTICK_AS_TIMETICK */
+
+#endif /* TOPPERS_TARGET_TIMER_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_unrename.h
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_unrename.h	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_unrename.h	(revision 303)
@@ -0,0 +1,27 @@
+/* This file is generated from target_rename.def by genrename. */
+
+/* This file is included only when target_rename.h has been included. */
+#ifdef TOPPERS_TARGET_RENAME_H
+#undef TOPPERS_TARGET_RENAME_H
+
+
+/*
+ * target_config.c
+ */
+#undef target_initialize
+#undef target_exit
+
+#ifdef TOPPERS_LABEL_ASM
+
+
+/*
+ * target_config.c
+ */
+#undef _target_initialize
+#undef _target_exit
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "chip_unrename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_user.txt
===================================================================
--- asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_user.txt	(revision 303)
+++ asp3_wo_tecs/trunk/target/nucleo_f401re_gcc/target_user.txt	(revision 303)
@@ -0,0 +1,212 @@
+=====================================================================
+                    NUCLEO_F401RE(GCC)ã¿ã¼ã²ããä¾å­é¨ 
+                                  Last Modified:2017 Jan 13 19:30:50
+=====================================================================
+
+(1) å¯¾å¿ãã¦ããã¿ã¼ã²ããã·ã¹ãã ã®ç¨®é¡ã»æ§æ
+
+NUCLEO_F401RE(GCC)ã¿ã¼ã²ããä¾å­é¨ã¯ï¼STM32F401RE(Cortex-M4F)ãæ­è¼ã
+ãSTãã¤ã¯ã­ç¤¾ã®NUCLEO_F401REãã¼ãããµãã¼ãããï¼ãã­ã»ããµä¾å­é¨ã¨
+ãã¦ï¼ST32F4XX_STM32CUBE(GCC)ãã­ã»ããµä¾å­é¨ããã­ã»ããµä¾å­é¨ã¨ãã¦
+ARM_Mãã­ã»ããµä¾å­é¨ãä½¿ç¨ããï¼
+
+
+(2) ä½¿ç¨ããéçºç°å¢ã¨åä½æ¤è¨¼ããæ¡ä»¶ï¼ãã¼ã¸ã§ã³ï¼ãªãã·ã§ã³ç­ï¼
+ã»ã©ã¤ãã©ãª
+
+ããã¤ã¹ãã©ã¤ã¯STM32Cubeä»å±ã®ã©ã¤ãã©ãªãä½¿ç¨ãã¦ããï¼ãããã®ãã¡
+ã¤ã«ã®ã©ã¤ã»ã³ã¹ã¯TOPPERSã©ã¤ã»ã³ã¹ã§ãªãããï¼æ³¨æãããã¨ï¼
+
+ãã¼ã¸ã§ã³ã¯æ¬¡ã®éãã§ããï¼
+
+ F4 V 1.9.0
+
+ã»ã³ã³ãã¤ã©
+
+ä»¥ä¸ã®2ç¨®é¡ã®ã³ã³ãã¤ã©ã§åä½ç¢ºèªãè¡ã£ãï¼
+
+GCC 5.4.1  (Launchpad_5.4_2016q3) 
+GCC 5.3.1  (Atollic TrueStudioä»å±)
+
+ã»ãããã°ç°å¢
+
+ãããã°ç°å¢ã¨ãã¦ã¯ï¼JTAGãããã¬ã«ST-LINKï¼ãããã¬ã¨ãã¦OpenOCD + 
+GDBãªããï¼Atollic TrueStudioãç¨ããç°å¢ã§åä½ç¢ºèªãè¡ã£ã¦ããï¼
+
+åä½ç¢ºèªãã OpenOCD ã¯ä»¥ä¸ã®ãã¼ã¸ã§ã³ã§ããï¼
+
+    2.3.6
+
+åä½ç¢ºèªãã TrueStudio ã¯ä»¥ä¸ã®ãã¼ã¸ã§ã³ã§ããï¼
+
+    V7.1.0
+
+(3) ã¿ã¼ã²ããå®ç¾©äºé 
+ã®è¦å®
+
+
+(4) ã¡ã¢ãªããã
+
+æ¨æº
+  å
+èµFlashROM
+  ã»ã¢ãã¬ã¹ : 0x08000000
+  ã»ãµã¤ãº   : 512KB
+  ã»é
+ç½®ã»ã¯ã·ã§ã³
+   ã»vectorã»ã¯ã·ã§ã³
+   ã»textã»ã¯ã·ã§ã³
+   ã»rodataã»ã¯ã·ã§ã³
+   
+  å
+èµRAM
+  ã»ã¢ãã¬ã¹ : 0x20000000
+  ã»ãµã¤ãº   : 96KB
+    ã»dataã»ã¯ã·ã§ã³
+    ã»bssã»ã¯ã·ã§ã³
+    
+(5) ã·ãªã¢ã«ã¤ã³ã¿ãã§ã¼ã¹ãã©ã¤ãã®æ
+å ±
+
+ã³ã³ã½ã¼ã«åºåã«ã¯ï¼ä»®æ³COMãã¼ãã«æ¥ç¶ããã¦ããUSARTã®ãã£ãã«2ãç¨
+ããï¼éä¿¡ãã©ã¼ãããã¯ä»¥ä¸ã®éãã§ããï¼
+
+  ã»1152200bps, Data 8bit, Parity none, Stop 1bit, Flow control none
+
+(6) ã·ã¹ãã ã­ã°æ©è½ã®æ
+å ±
+
+ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã¯ï¼UART2ãç¨ããï¼éä¿¡ãã©ã¼ãããã¯ï¼
+115200bps, 8bit, non-parity, 1topbitã§ããï¼
+
+(7) Atollic TrueStudio ã®ä½¿ç¨
+
+æ¬ããã±ã¼ã¸ã¯ Atollic TrueStudio ããµãã¼ããã¦ããï¼
+TrueStudio ã¯ï¼Freeç(ãµã¤ãºå¶éãªã)ãä»¥ä¸ãããã¦ã³ã­ã¼ãå¯è½ã§ããï¼
+
+http://timor.atollic.com/truestudio/
+
+ãã­ã¸ã§ã¯ãã®ãã«ãã¨å®è¡æ¹æ³
+
+./truestudio/asp/.cproject ãTrueStudioéãã¦ï¼./truestudioãã¯ã¼ã¯ã¹
+ãã¼ã¹ã¨ãã¦æå®ããï¼
+
+ã¡ãã¥ã¼ -> ãã­ã¸ã§ã¯ã -> ãã­ã¸ã§ã¯ãã®ãã«ã  ãé¸æããã¨ãã«ã
+ãéå§ãããï¼
+
+ã¡ãã¥ã¼ -> å®è¡ -> ãããã° ãé¸æããã¨ãããã°ãéå§ãããï¼
+   
+(8) ä»ã®NUCLEOãã¼ãã®ãµãã¼ã
+
+æ¬ããã±ã¼ã¸ã¯STM32FCUBEã«å«ã¾ãã¦ãããã¡ã¤ã«ãç¨ãã¦ï¼ããã¤ã¹ç­ã®å
+æåãè¡ã£ã¦ããããï¼ä»ã®NUCLEOãå®¹æã«ãµãã¼ãå¯è½ã§ããï¼
+
+F401REãä¾ã«æé ãã¾ã¨ããï¼
+
+./target/nucleo_f401re_gcc/stm32fcube ã«ä»¥ä¸ã®ãã¡ã¤ã«ãã³ãã¼
+
+\STM32Cube_FW_F4_V1.9.0\Projects\STM32F401RE-Nucleo\Templates\Inc\stm32f4xx_hal_conf.h
+\STM32Cube_FW_F4_V1.9.0\Projects\STM32F401RE-Nucleo\Templates\Src\system_stm32f4xx.c
+\STM32Cube_FW_F4_V1.9.0\Projects\STM32F411RE-Nucleo\Templates\Src\main.c 
+\STM32Cube_FW_F4_V1.9.0\Drivers\BSP\STM32F4xx-Nucleo\stm32f4xx_nucleo.h
+\STM32Cube_FW_F4_V1.9.0\Drivers\BSP\STM32F4xx-Nucleo\stm32f4xx_nucleo.c
+
+ããããæ¬¡ã®ããã«å¤æ´
+
+stm32f4xx_hal_conf.h
+ã»å¿
+è¦ãªHALã®ã³ã¡ã³ãã¢ã¦ããå¤ã
+system_stm32f4xx.c
+ã»SystemInitã®æåã«ããCPACRã®åæå(FPUã®åæå)ãã³ã¡ã³ãã¢ã¦ã
+main.c 
+ã»SystemClock_Config()é¢æ°ã®ã¿æ®ãã¦ï¼ãã¡ã¤ã«åãsystemclock_config.cã«
+  å¤æ´ï¼
+stm32f4xx_nucleo.c
+ã»å¿
+è¦ã§ãªãæ©è½ãã³ã¡ã³ãã¢ã¦ã
+
+./arch/arm_m_gcc/stm32f4xx_stm32cube/ ä»¥ä¸ã« 
+STM32Cube_FW_F4_V1.9.0\Drivers ä»¥ä¸ã®å¿
+è¦ãªãã¡ã¤ã«ãã³ãã¼ï¼é¢åãªå ´
+åã¯å
+¨ã¦ã³ãã¼ãã¦ãã¾ããªãï¼
+
+./target/nucleo_f401re_gcc/ ä»¥ä¸ã®ãã¡ã¤ã«ãå¤æ´
+
+Makefile.target
+22è¡ç® : ä½¿ç¨ãããããã®åçªãæå®
+CDEFS := $(CDEFS) -DSTM32F401xE
+
+stm32f401re.ld
+ã¡ã¢ãªããããä½¿ç¨ãããããã«åããã¦å¤æ´ï¼
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  SRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+target_config.h
+å²è¾¼ã¿ã®æå¤§æ°ãä½¿ç¨ãããããã«åããã¦å¤æ´(å¿
+ã+16ãããã¨)ï¼
+#define TMAX_INTNO (84 + 16)
+
+ã¯ã­ãã¯å¨æ³¢æ°ãä½¿ç¨ãããããã«åããã¦å¤æ´ï¼
+#define SYS_CLOCK		84000000
+
+target_config.c
+target_initialize() ãä½¿ç¨ãããããã«åããã¦åæåå¦çãè¿½å ï¼
+usart_early_init() ãä½¿ç¨ãããããã«åããã¦åæåå¦çãè¿½å ï¼
+
+å
+¨ãã¡ã¤ã«
+F401RE ãï¼ä½¿ç¨ãããããã®åçªã«ãªãã¬ã¼ã¹ï¼
+
+
+(9) ãã£ã¬ã¯ããªæ§æã»ãã¡ã¤ã«æ§æ
+  ./nucleo_f401re_gcc
+   ./E_PACKAGE
+   ./gdb.ini
+   ./Makefile.target
+   ./MANIFEST
+   ./nucleo_f401re.h
+   ./stm32f401re.ld
+   ./target.cdl
+   ./target.tf
+   ./target_asm.inc
+   ./target_cfg1_out.h
+   ./target_check.trb
+   ./target_kernel.cfg
+   ./target_kernel.h
+   ./target_kernel.trb
+   ./target_kernel_impl.c
+   ./target_kernel_impl.h
+   ./target_rename.def
+   ./target_rename.h
+   ./target_sil.h
+   ./target_stddef.h
+   ./target_syssvc.h
+   ./target_test.h
+   ./target_timer.c
+   ./target_timer.cfg
+   ./target_timer.h
+   ./target_unrename.h
+   ./target_user.txt
+   ./tPutLogTarget.c
+   ./tPutLogTarget.cdl
+   ./tSIOPortTarget.cdl
+   ./tSIOPortTargetMain_inline.h
+   ./stm32fcube
+     ./stm32f4xx_hal_conf.h
+     ./stm32f4xx_nucleo.c
+     ./stm32f4xx_nucleo.h
+     ./system_stm32f4xx.c
+     ./systemclock_config.c
+   ./truestudio
+     
+                        
+(10)å¤æ´å±¥æ­´
+
+2017/1/13
+ã»æ°è¦ä½æ
+
+ä»¥ä¸ï¼
