Index: uKadecot/trunk/ssp/arch/rx630_ccrx/prc_sil.h
===================================================================
--- uKadecot/trunk/ssp/arch/rx630_ccrx/prc_sil.h	(revision 108)
+++ uKadecot/trunk/ssp/arch/rx630_ccrx/prc_sil.h	(revision 154)
@@ -43,4 +43,5 @@
 #define TOPPERS_PRC_SIL_H
 
+#define TOPPERS_OMIT_SIL_ACCESS
 
 #ifndef TOPPERS_MACRO_ONLY
@@ -106,6 +107,199 @@
  *  プロセッサのエンディアン
  */
+#ifdef __LIT
 #define SIL_ENDIAN_LITTLE			/* リトルエンディアン */
-
+#endif
+#ifdef __BIG
+#define SIL_ENDIAN_BIG				/* ビッグエンディアン */
+#endif
+
+
+/*
+ *  8ビット単位の読出し／書込み
+ */
+#ifdef UINT8_MAX
+
+#pragma inline(sil_reb_mem)
+static uint8_t
+sil_reb_mem(const volatile uint8_t __evenaccess *mem)
+{
+	uint8_t	data;
+
+	data = *mem;
+	return(data);
+}
+
+#pragma inline(sil_wrb_mem)
+static void
+sil_wrb_mem(volatile uint8_t __evenaccess *mem, uint8_t data)
+{
+	*mem = data;
+}
+
+#endif /* UINT8_MAX */
+
+/*
+ *  16ビット単位の読出し／書込み
+ */
+
+#pragma inline(sil_reh_mem)
+static uint16_t
+sil_reh_mem(const volatile uint16_t __evenaccess *mem)
+{
+	uint16_t	data;
+
+	data = *mem;
+	return(data);
+}
+
+#pragma inline(sil_wrh_mem)
+static void
+sil_wrh_mem(volatile uint16_t __evenaccess *mem, uint16_t data)
+{
+	*mem = data;
+}
+
+#ifdef SIL_ENDIAN_BIG			/* ビッグエンディアンプロセッサ */
+
+#define	sil_reh_bem(mem)		sil_reh_mem(mem)
+#define	sil_wrh_bem(mem, data)	sil_wrh_mem(mem, data)
+
+#ifndef TOPPERS_OMIT_SIL_REH_LEM
+
+#pragma inline(sil_reh_lem)
+static uint16_t
+sil_reh_lem(const volatile uint16_t __evenaccess *mem)
+{
+	uint16_t	data;
+
+	data = *mem;
+	return(TOPPERS_SIL_REV_ENDIAN_UINT16(data));
+}
+
+#endif /* TOPPERS_OMIT_SIL_REH_LEM */
+#ifndef TOPPERS_OMIT_SIL_WRH_LEM
+
+#pragma inline(sil_wrh_lem)
+static void
+sil_wrh_lem(volatile uint16_t __evenaccess *mem, uint16_t data)
+{
+	*mem = TOPPERS_SIL_REV_ENDIAN_UINT16(data);
+}
+
+#endif /* TOPPERS_OMIT_SIL_WRH_LEM */
+#else /* SIL_ENDIAN_BIG */
+#ifdef SIL_ENDIAN_LITTLE		/* リトルエンディアンプロセッサ */
+
+#define	sil_reh_lem(mem)		sil_reh_mem(mem)
+#define	sil_wrh_lem(mem, data)	sil_wrh_mem(mem, data)
+
+#ifndef TOPPERS_OMIT_SIL_REH_BEM
+
+#pragma inline(sil_reh_bem)
+static uint16_t
+sil_reh_bem(const volatile uint16_t __evenaccess *mem)
+{
+	uint16_t	data;
+
+	data = *mem;
+	return(TOPPERS_SIL_REV_ENDIAN_UINT16(data));
+}
+
+#endif /* TOPPERS_OMIT_SIL_REH_BEM */
+#ifndef TOPPERS_OMIT_SIL_WRH_BEM
+
+#pragma inline(sil_wrh_bem)
+static void
+sil_wrh_bem(volatile uint16_t __evenaccess *mem, uint16_t data)
+{
+	*mem = TOPPERS_SIL_REV_ENDIAN_UINT16(data);
+}
+
+#endif /* TOPPERS_OMIT_SIL_WRH_BEM */
+#else /* SIL_ENDIAN_LITTLE */
+
+#error Neither SIL_ENDIAN_BIG nor SIL_ENDIAN_LITTLE is defined.
+
+#endif /* SIL_ENDIAN_LITTLE */
+#endif /* SIL_ENDIAN_BIG */
+
+/*
+ *  32ビット単位の読出し／書込み
+ */
+
+#pragma inline(sil_rew_mem)
+static uint32_t
+sil_rew_mem(const volatile uint32_t __evenaccess *mem)
+{
+	uint32_t	data;
+
+	data = *mem;
+	return(data);
+}
+
+#pragma inline(sil_wrw_mem)
+static void
+sil_wrw_mem(volatile uint32_t __evenaccess *mem, uint32_t data)
+{
+	*mem = data;
+}
+
+#ifdef SIL_ENDIAN_BIG			/* ビッグエンディアンプロセッサ */
+
+#define	sil_rew_bem(mem)		sil_rew_mem(mem)
+#define	sil_wrw_bem(mem, data)	sil_wrw_mem(mem, data)
+
+#ifndef TOPPERS_OMIT_SIL_REW_LEM
+
+#pragma inline(sil_rew_lem)
+static uint32_t
+sil_rew_lem(const volatile uint32_t __evenaccess *mem)
+{
+	uint32_t	data;
+
+	data = *mem;
+	return(TOPPERS_SIL_REV_ENDIAN_UINT32(data));
+}
+
+#endif /* TOPPERS_OMIT_SIL_REW_LEM */
+#ifndef TOPPERS_OMIT_SIL_WRW_LEM
+
+#pragma inline(sil_wrw_lem)
+static void
+sil_wrw_lem(volatile uint32_t __evenaccess *mem, uint32_t data)
+{
+	*mem = TOPPERS_SIL_REV_ENDIAN_UINT32(data);
+}
+
+#endif /* TOPPERS_OMIT_SIL_WRW_LEM */
+#else /* SIL_ENDIAN_BIG */		/* リトルエンディアンプロセッサ */
+
+#define	sil_rew_lem(mem)		sil_rew_mem(mem)
+#define	sil_wrw_lem(mem, data)	sil_wrw_mem(mem, data)
+
+#ifndef TOPPERS_OMIT_SIL_REW_BEM
+
+#pragma inline(sil_rew_bem)
+static uint32_t
+sil_rew_bem(const volatile uint32_t __evenaccess *mem)
+{
+	uint32_t	data;
+
+	data = *mem;
+	return(TOPPERS_SIL_REV_ENDIAN_UINT32(data));
+}
+
+#endif /* TOPPERS_OMIT_SIL_REW_BEM */
+#ifndef TOPPERS_OMIT_SIL_WRW_BEM
+
+#pragma inline(sil_wrw_bem)
+static void
+sil_wrw_bem(volatile uint32_t __evenaccess *mem, uint32_t data)
+{
+	*mem = TOPPERS_SIL_REV_ENDIAN_UINT32(data);
+}
+
+#endif /* TOPPERS_OMIT_SIL_WRW_BEM */
+#endif /* SIL_ENDIAN_BIG */
 
 #endif /* TOPPERS_PRC_SIL_H */
Index: uKadecot/trunk/ssp/arch/rx630_ccrx/rx630.h
===================================================================
--- uKadecot/trunk/ssp/arch/rx630_ccrx/rx630.h	(revision 108)
+++ uKadecot/trunk/ssp/arch/rx630_ccrx/rx630.h	(revision 154)
@@ -1475,4 +1475,40 @@
 #define PORT_PCR_B6_BIT			( 0x01U << 6U )
 #define PORT_PCR_B7_BIT			( 0x01U << 7U )
+#define PORT0_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C080 )
+#define PORT1_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C082 )
+#define PORT2_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C084 )
+#define PORT3_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C086 )
+#define PORT4_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C088 )
+#define PORT5_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C08A )
+#define PORT6_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C08C )
+#define PORT7_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C08E )
+#define PORT8_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C090 )
+#define PORT9_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C092 )
+#define PORTA_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C094 )
+#define PORTB_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C096 )
+#define PORTC_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C098 )
+#define PORTD_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C09A )
+#define PORTE_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C09C )
+#define PORTF_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C09E )
+#define PORTG_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C0A0 )
+#define PORTJ_ODR0_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C0A4 )
+#define PORT0_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C081 )
+#define PORT1_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C083 )
+#define PORT2_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C085 )
+#define PORT3_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C087 )
+#define PORT4_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C089 )
+#define PORT5_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C08B )
+#define PORT6_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C08D )
+#define PORT7_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C08F )
+#define PORT8_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C091 )
+#define PORT9_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C093 )
+#define PORTA_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C095 )
+#define PORTB_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C097 )
+#define PORTC_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C099 )
+#define PORTD_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C09B )
+#define PORTE_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C09D )
+#define PORTF_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C09F )
+#define PORTG_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C0A1 )
+#define PORTJ_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C0A5 )
 
 /*
@@ -1767,4 +1803,94 @@
 
 /*
+ * RSPI
+ */
+#define RSPI0_SPCR_ADDR		( ( volatile uint8_t __evenaccess * )0x00088380 )
+#define RSPI1_SPCR_ADDR		( ( volatile uint8_t __evenaccess * )0x000883A0 )
+#define RSPI2_SPCR_ADDR		( ( volatile uint8_t __evenaccess * )0x000883C0 )
+#define RSPI_SPCR_SPMS_BIT	( 0x01U << 0U )
+#define RSPI_SPCR_TXMD_BIT	( 0x01U << 1U )
+#define RSPI_SPCR_MODFEN_BIT	( 0x01U << 2U )
+#define RSPI_SPCR_MSTR_BIT	( 0x01U << 3U )
+#define RSPI_SPCR_SPEIE_BIT	( 0x01U << 4U )
+#define RSPI_SPCR_SPTIE_BIT	( 0x01U << 5U )
+#define RSPI_SPCR_SPE_BIT	( 0x01U << 6U )
+#define RSPI_SPCR_SPRIE_BIT	( 0x01U << 7U )
+
+#define RSPI0_SSLP_ADDR		( ( volatile uint8_t __evenaccess * )0x00088381 )
+#define RSPI1_SSLP_ADDR		( ( volatile uint8_t __evenaccess * )0x000883A1 )
+#define RSPI2_SSLP_ADDR		( ( volatile uint8_t __evenaccess * )0x000883C1 )
+
+#define RSPI0_SPPCR_ADDR	( ( volatile uint8_t __evenaccess * )0x00088382 )
+#define RSPI1_SPPCR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883A2 )
+#define RSPI2_SPPCR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883C2 )
+
+#define RSPI0_SPSR_ADDR		( ( volatile uint8_t __evenaccess * )0x00088383 )
+#define RSPI1_SPSR_ADDR		( ( volatile uint8_t __evenaccess * )0x000883A3 )
+#define RSPI2_SPSR_ADDR		( ( volatile uint8_t __evenaccess * )0x000883C3 )
+
+#define RSPI0_SPDR_ADDR		( ( volatile uint32_t __evenaccess * )0x00088384 )
+#define RSPI1_SPDR_ADDR		( ( volatile uint32_t __evenaccess * )0x000883A4 )
+#define RSPI2_SPDR_ADDR		( ( volatile uint32_t __evenaccess * )0x000883C4 )
+
+#define RSPI0_SPSCR_ADDR	( ( volatile uint8_t __evenaccess * )0x00088388 )
+#define RSPI1_SPSCR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883A8 )
+#define RSPI2_SPSCR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883C8 )
+
+#define RSPI0_SPSSR_ADDR	( ( volatile uint8_t __evenaccess * )0x00088389 )
+#define RSPI1_SPSSR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883A9 )
+#define RSPI2_SPSSR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883C9 )
+
+#define RSPI0_SPBR_ADDR		( ( volatile uint8_t __evenaccess * )0x0008838A )
+#define RSPI1_SPBR_ADDR		( ( volatile uint8_t __evenaccess * )0x000883AA )
+#define RSPI2_SPBR_ADDR		( ( volatile uint8_t __evenaccess * )0x000883CA )
+
+#define RSPI0_SPDCR_ADDR	( ( volatile uint8_t __evenaccess * )0x0008838B )
+#define RSPI1_SPDCR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883AB )
+#define RSPI2_SPDCR_ADDR	( ( volatile uint8_t __evenaccess * )0x000883CB )
+
+#define RSPI0_SPCKD_ADDR	( ( volatile uint8_t __evenaccess * )0x0008838C )
+#define RSPI1_SPCKD_ADDR	( ( volatile uint8_t __evenaccess * )0x000883AC )
+#define RSPI2_SPCKD_ADDR	( ( volatile uint8_t __evenaccess * )0x000883CC )
+
+#define RSPI0_SSLND_ADDR	( ( volatile uint8_t __evenaccess * )0x0008838D )
+#define RSPI1_SSLND_ADDR	( ( volatile uint8_t __evenaccess * )0x000883AD )
+#define RSPI2_SSLND_ADDR	( ( volatile uint8_t __evenaccess * )0x000883CD )
+
+#define RSPI0_SPND_ADDR		( ( volatile uint8_t __evenaccess * )0x0008838E )
+#define RSPI1_SPND_ADDR		( ( volatile uint8_t __evenaccess * )0x000883AE )
+#define RSPI2_SPND_ADDR		( ( volatile uint8_t __evenaccess * )0x000883CE )
+
+#define RSPI0_SPCR2_ADDR	( ( volatile uint8_t __evenaccess * )0x0008838F )
+#define RSPI1_SPCR2_ADDR	( ( volatile uint8_t __evenaccess * )0x000883AF )
+#define RSPI2_SPCR2_ADDR	( ( volatile uint8_t __evenaccess * )0x000883CF )
+
+#define RSPI0_SPCMD0_ADDR	( ( volatile uint16_t __evenaccess * )0x00088390 )
+#define RSPI0_SPCMD1_ADDR	( ( volatile uint16_t __evenaccess * )0x00088392 )
+#define RSPI0_SPCMD2_ADDR	( ( volatile uint16_t __evenaccess * )0x00088394 )
+#define RSPI0_SPCMD3_ADDR	( ( volatile uint16_t __evenaccess * )0x00088396 )
+#define RSPI0_SPCMD4_ADDR	( ( volatile uint16_t __evenaccess * )0x00088398 )
+#define RSPI0_SPCMD5_ADDR	( ( volatile uint16_t __evenaccess * )0x0008839A )
+#define RSPI0_SPCMD6_ADDR	( ( volatile uint16_t __evenaccess * )0x0008839C )
+#define RSPI0_SPCMD7_ADDR	( ( volatile uint16_t __evenaccess * )0x0008839E )
+#define RSPI1_SPCMD0_ADDR	( ( volatile uint16_t __evenaccess * )0x000883B0 )
+#define RSPI1_SPCMD1_ADDR	( ( volatile uint16_t __evenaccess * )0x000883B2 )
+#define RSPI1_SPCMD2_ADDR	( ( volatile uint16_t __evenaccess * )0x000883B4 )
+#define RSPI1_SPCMD3_ADDR	( ( volatile uint16_t __evenaccess * )0x000883B6 )
+#define RSPI1_SPCMD4_ADDR	( ( volatile uint16_t __evenaccess * )0x000883B8 )
+#define RSPI1_SPCMD5_ADDR	( ( volatile uint16_t __evenaccess * )0x000883BA )
+#define RSPI1_SPCMD6_ADDR	( ( volatile uint16_t __evenaccess * )0x000883BC )
+#define RSPI1_SPCMD7_ADDR	( ( volatile uint16_t __evenaccess * )0x000883BE )
+#define RSPI2_SPCMD0_ADDR	( ( volatile uint16_t __evenaccess * )0x000883D0 )
+#define RSPI2_SPCMD1_ADDR	( ( volatile uint16_t __evenaccess * )0x000883D2 )
+#define RSPI2_SPCMD2_ADDR	( ( volatile uint16_t __evenaccess * )0x000883D4 )
+#define RSPI2_SPCMD3_ADDR	( ( volatile uint16_t __evenaccess * )0x000883D6 )
+#define RSPI2_SPCMD4_ADDR	( ( volatile uint16_t __evenaccess * )0x000883D8 )
+#define RSPI2_SPCMD5_ADDR	( ( volatile uint16_t __evenaccess * )0x000883DA )
+#define RSPI2_SPCMD6_ADDR	( ( volatile uint16_t __evenaccess * )0x000883DC )
+#define RSPI2_SPCMD7_ADDR	( ( volatile uint16_t __evenaccess * )0x000883DE )
+#define RSPI_SPCMD_SPB_OFFSET	(8)
+#define RSPI_SPCMD_SPB_MASK (0xF << RSPI_SPCMD_SPB_OFFSET)
+
+/*
  *  UART関連の定義
  *
