Changeset 154 for uKadecot/trunk/ssp/arch/rx630_ccrx/rx630.h

Timestamp:

Feb 2, 2016, 9:54:35 PM (8 years ago)

Author:

coas-nagasima

Message:

SDカードの中身を/~/でアクセスできるよう変更

File:

• uKadecot/trunk/ssp/arch/rx630_ccrx/rx630.h (modified) (2 diffs)

uKadecot/trunk/ssp/arch/rx630_ccrx/rx630.h

@@ -1475 +1475 @@
 #define PORT_PCR_B6_BIT                 ( 0x01U << 6U )
 #define PORT_PCR_B7_BIT                 ( 0x01U << 7U )
+#define PORT0_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C080 )
+#define PORT1_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C082 )
+#define PORT2_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C084 )
+#define PORT3_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C086 )
+#define PORT4_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C088 )
+#define PORT5_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C08A )
+#define PORT6_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C08C )
+#define PORT7_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C08E )
+#define PORT8_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C090 )
+#define PORT9_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C092 )
+#define PORTA_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C094 )
+#define PORTB_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C096 )
+#define PORTC_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C098 )
+#define PORTD_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C09A )
+#define PORTE_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C09C )
+#define PORTF_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C09E )
+#define PORTG_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C0A0 )
+#define PORTJ_ODR0_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C0A4 )
+#define PORT0_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C081 )
+#define PORT1_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C083 )
+#define PORT2_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C085 )
+#define PORT3_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C087 )
+#define PORT4_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C089 )
+#define PORT5_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C08B )
+#define PORT6_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C08D )
+#define PORT7_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C08F )
+#define PORT8_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C091 )
+#define PORT9_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C093 )
+#define PORTA_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C095 )
+#define PORTB_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C097 )
+#define PORTC_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C099 )
+#define PORTD_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C09B )
+#define PORTE_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C09D )
+#define PORTF_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C09F )
+#define PORTG_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C0A1 )
+#define PORTJ_ODR1_ADDR                 ( ( volatile uint8_t __evenaccess * )0x0008C0A5 )
 
 /*
@@ -1767 +1803 @@
 
 /*
+ * RSPI
+ */
+#define RSPI0_SPCR_ADDR         ( ( volatile uint8_t __evenaccess * )0x00088380 )
+#define RSPI1_SPCR_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883A0 )
+#define RSPI2_SPCR_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883C0 )
+#define RSPI_SPCR_SPMS_BIT      ( 0x01U << 0U )
+#define RSPI_SPCR_TXMD_BIT      ( 0x01U << 1U )
+#define RSPI_SPCR_MODFEN_BIT    ( 0x01U << 2U )
+#define RSPI_SPCR_MSTR_BIT      ( 0x01U << 3U )
+#define RSPI_SPCR_SPEIE_BIT     ( 0x01U << 4U )
+#define RSPI_SPCR_SPTIE_BIT     ( 0x01U << 5U )
+#define RSPI_SPCR_SPE_BIT       ( 0x01U << 6U )
+#define RSPI_SPCR_SPRIE_BIT     ( 0x01U << 7U )
+
+#define RSPI0_SSLP_ADDR         ( ( volatile uint8_t __evenaccess * )0x00088381 )
+#define RSPI1_SSLP_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883A1 )
+#define RSPI2_SSLP_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883C1 )
+
+#define RSPI0_SPPCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x00088382 )
+#define RSPI1_SPPCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883A2 )
+#define RSPI2_SPPCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883C2 )
+
+#define RSPI0_SPSR_ADDR         ( ( volatile uint8_t __evenaccess * )0x00088383 )
+#define RSPI1_SPSR_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883A3 )
+#define RSPI2_SPSR_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883C3 )
+
+#define RSPI0_SPDR_ADDR         ( ( volatile uint32_t __evenaccess * )0x00088384 )
+#define RSPI1_SPDR_ADDR         ( ( volatile uint32_t __evenaccess * )0x000883A4 )
+#define RSPI2_SPDR_ADDR         ( ( volatile uint32_t __evenaccess * )0x000883C4 )
+
+#define RSPI0_SPSCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x00088388 )
+#define RSPI1_SPSCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883A8 )
+#define RSPI2_SPSCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883C8 )
+
+#define RSPI0_SPSSR_ADDR        ( ( volatile uint8_t __evenaccess * )0x00088389 )
+#define RSPI1_SPSSR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883A9 )
+#define RSPI2_SPSSR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883C9 )
+
+#define RSPI0_SPBR_ADDR         ( ( volatile uint8_t __evenaccess * )0x0008838A )
+#define RSPI1_SPBR_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883AA )
+#define RSPI2_SPBR_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883CA )
+
+#define RSPI0_SPDCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x0008838B )
+#define RSPI1_SPDCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883AB )
+#define RSPI2_SPDCR_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883CB )
+
+#define RSPI0_SPCKD_ADDR        ( ( volatile uint8_t __evenaccess * )0x0008838C )
+#define RSPI1_SPCKD_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883AC )
+#define RSPI2_SPCKD_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883CC )
+
+#define RSPI0_SSLND_ADDR        ( ( volatile uint8_t __evenaccess * )0x0008838D )
+#define RSPI1_SSLND_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883AD )
+#define RSPI2_SSLND_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883CD )
+
+#define RSPI0_SPND_ADDR         ( ( volatile uint8_t __evenaccess * )0x0008838E )
+#define RSPI1_SPND_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883AE )
+#define RSPI2_SPND_ADDR         ( ( volatile uint8_t __evenaccess * )0x000883CE )
+
+#define RSPI0_SPCR2_ADDR        ( ( volatile uint8_t __evenaccess * )0x0008838F )
+#define RSPI1_SPCR2_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883AF )
+#define RSPI2_SPCR2_ADDR        ( ( volatile uint8_t __evenaccess * )0x000883CF )
+
+#define RSPI0_SPCMD0_ADDR       ( ( volatile uint16_t __evenaccess * )0x00088390 )
+#define RSPI0_SPCMD1_ADDR       ( ( volatile uint16_t __evenaccess * )0x00088392 )
+#define RSPI0_SPCMD2_ADDR       ( ( volatile uint16_t __evenaccess * )0x00088394 )
+#define RSPI0_SPCMD3_ADDR       ( ( volatile uint16_t __evenaccess * )0x00088396 )
+#define RSPI0_SPCMD4_ADDR       ( ( volatile uint16_t __evenaccess * )0x00088398 )
+#define RSPI0_SPCMD5_ADDR       ( ( volatile uint16_t __evenaccess * )0x0008839A )
+#define RSPI0_SPCMD6_ADDR       ( ( volatile uint16_t __evenaccess * )0x0008839C )
+#define RSPI0_SPCMD7_ADDR       ( ( volatile uint16_t __evenaccess * )0x0008839E )
+#define RSPI1_SPCMD0_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883B0 )
+#define RSPI1_SPCMD1_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883B2 )
+#define RSPI1_SPCMD2_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883B4 )
+#define RSPI1_SPCMD3_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883B6 )
+#define RSPI1_SPCMD4_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883B8 )
+#define RSPI1_SPCMD5_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883BA )
+#define RSPI1_SPCMD6_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883BC )
+#define RSPI1_SPCMD7_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883BE )
+#define RSPI2_SPCMD0_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883D0 )
+#define RSPI2_SPCMD1_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883D2 )
+#define RSPI2_SPCMD2_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883D4 )
+#define RSPI2_SPCMD3_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883D6 )
+#define RSPI2_SPCMD4_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883D8 )
+#define RSPI2_SPCMD5_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883DA )
+#define RSPI2_SPCMD6_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883DC )
+#define RSPI2_SPCMD7_ADDR       ( ( volatile uint16_t __evenaccess * )0x000883DE )
+#define RSPI_SPCMD_SPB_OFFSET   (8)
+#define RSPI_SPCMD_SPB_MASK (0xF << RSPI_SPCMD_SPB_OFFSET)
+
+/*
  *  UART関連の定義
  *