Changeset 154 for uKadecot/trunk/ssp
- Timestamp:
- Feb 2, 2016, 9:54:35 PM (8 years ago)
- Location:
- uKadecot/trunk/ssp/arch/rx630_ccrx
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
uKadecot/trunk/ssp/arch/rx630_ccrx/prc_sil.h
r108 r154 43 43 #define TOPPERS_PRC_SIL_H 44 44 45 #define TOPPERS_OMIT_SIL_ACCESS 45 46 46 47 #ifndef TOPPERS_MACRO_ONLY … … 106 107 * プロセッサのエンディアン 107 108 */ 109 #ifdef __LIT 108 110 #define SIL_ENDIAN_LITTLE /* リトルエンディアン */ 109 111 #endif 112 #ifdef __BIG 113 #define SIL_ENDIAN_BIG /* ビッグエンディアン */ 114 #endif 115 116 117 /* 118 * 8ビット単位の読出し/書込み 119 */ 120 #ifdef UINT8_MAX 121 122 #pragma inline(sil_reb_mem) 123 static uint8_t 124 sil_reb_mem(const volatile uint8_t __evenaccess *mem) 125 { 126 uint8_t data; 127 128 data = *mem; 129 return(data); 130 } 131 132 #pragma inline(sil_wrb_mem) 133 static void 134 sil_wrb_mem(volatile uint8_t __evenaccess *mem, uint8_t data) 135 { 136 *mem = data; 137 } 138 139 #endif /* UINT8_MAX */ 140 141 /* 142 * 16ビット単位の読出し/書込み 143 */ 144 145 #pragma inline(sil_reh_mem) 146 static uint16_t 147 sil_reh_mem(const volatile uint16_t __evenaccess *mem) 148 { 149 uint16_t data; 150 151 data = *mem; 152 return(data); 153 } 154 155 #pragma inline(sil_wrh_mem) 156 static void 157 sil_wrh_mem(volatile uint16_t __evenaccess *mem, uint16_t data) 158 { 159 *mem = data; 160 } 161 162 #ifdef SIL_ENDIAN_BIG /* ビッグエンディアンプロセッサ */ 163 164 #define sil_reh_bem(mem) sil_reh_mem(mem) 165 #define sil_wrh_bem(mem, data) sil_wrh_mem(mem, data) 166 167 #ifndef TOPPERS_OMIT_SIL_REH_LEM 168 169 #pragma inline(sil_reh_lem) 170 static uint16_t 171 sil_reh_lem(const volatile uint16_t __evenaccess *mem) 172 { 173 uint16_t data; 174 175 data = *mem; 176 return(TOPPERS_SIL_REV_ENDIAN_UINT16(data)); 177 } 178 179 #endif /* TOPPERS_OMIT_SIL_REH_LEM */ 180 #ifndef TOPPERS_OMIT_SIL_WRH_LEM 181 182 #pragma inline(sil_wrh_lem) 183 static void 184 sil_wrh_lem(volatile uint16_t __evenaccess *mem, uint16_t data) 185 { 186 *mem = TOPPERS_SIL_REV_ENDIAN_UINT16(data); 187 } 188 189 #endif /* TOPPERS_OMIT_SIL_WRH_LEM */ 190 #else /* SIL_ENDIAN_BIG */ 191 #ifdef SIL_ENDIAN_LITTLE /* リトルエンディアンプロセッサ */ 192 193 #define sil_reh_lem(mem) sil_reh_mem(mem) 194 #define sil_wrh_lem(mem, data) sil_wrh_mem(mem, data) 195 196 #ifndef TOPPERS_OMIT_SIL_REH_BEM 197 198 #pragma inline(sil_reh_bem) 199 static uint16_t 200 sil_reh_bem(const volatile uint16_t __evenaccess *mem) 201 { 202 uint16_t data; 203 204 data = *mem; 205 return(TOPPERS_SIL_REV_ENDIAN_UINT16(data)); 206 } 207 208 #endif /* TOPPERS_OMIT_SIL_REH_BEM */ 209 #ifndef TOPPERS_OMIT_SIL_WRH_BEM 210 211 #pragma inline(sil_wrh_bem) 212 static void 213 sil_wrh_bem(volatile uint16_t __evenaccess *mem, uint16_t data) 214 { 215 *mem = TOPPERS_SIL_REV_ENDIAN_UINT16(data); 216 } 217 218 #endif /* TOPPERS_OMIT_SIL_WRH_BEM */ 219 #else /* SIL_ENDIAN_LITTLE */ 220 221 #error Neither SIL_ENDIAN_BIG nor SIL_ENDIAN_LITTLE is defined. 222 223 #endif /* SIL_ENDIAN_LITTLE */ 224 #endif /* SIL_ENDIAN_BIG */ 225 226 /* 227 * 32ビット単位の読出し/書込み 228 */ 229 230 #pragma inline(sil_rew_mem) 231 static uint32_t 232 sil_rew_mem(const volatile uint32_t __evenaccess *mem) 233 { 234 uint32_t data; 235 236 data = *mem; 237 return(data); 238 } 239 240 #pragma inline(sil_wrw_mem) 241 static void 242 sil_wrw_mem(volatile uint32_t __evenaccess *mem, uint32_t data) 243 { 244 *mem = data; 245 } 246 247 #ifdef SIL_ENDIAN_BIG /* ビッグエンディアンプロセッサ */ 248 249 #define sil_rew_bem(mem) sil_rew_mem(mem) 250 #define sil_wrw_bem(mem, data) sil_wrw_mem(mem, data) 251 252 #ifndef TOPPERS_OMIT_SIL_REW_LEM 253 254 #pragma inline(sil_rew_lem) 255 static uint32_t 256 sil_rew_lem(const volatile uint32_t __evenaccess *mem) 257 { 258 uint32_t data; 259 260 data = *mem; 261 return(TOPPERS_SIL_REV_ENDIAN_UINT32(data)); 262 } 263 264 #endif /* TOPPERS_OMIT_SIL_REW_LEM */ 265 #ifndef TOPPERS_OMIT_SIL_WRW_LEM 266 267 #pragma inline(sil_wrw_lem) 268 static void 269 sil_wrw_lem(volatile uint32_t __evenaccess *mem, uint32_t data) 270 { 271 *mem = TOPPERS_SIL_REV_ENDIAN_UINT32(data); 272 } 273 274 #endif /* TOPPERS_OMIT_SIL_WRW_LEM */ 275 #else /* SIL_ENDIAN_BIG */ /* リトルエンディアンプロセッサ */ 276 277 #define sil_rew_lem(mem) sil_rew_mem(mem) 278 #define sil_wrw_lem(mem, data) sil_wrw_mem(mem, data) 279 280 #ifndef TOPPERS_OMIT_SIL_REW_BEM 281 282 #pragma inline(sil_rew_bem) 283 static uint32_t 284 sil_rew_bem(const volatile uint32_t __evenaccess *mem) 285 { 286 uint32_t data; 287 288 data = *mem; 289 return(TOPPERS_SIL_REV_ENDIAN_UINT32(data)); 290 } 291 292 #endif /* TOPPERS_OMIT_SIL_REW_BEM */ 293 #ifndef TOPPERS_OMIT_SIL_WRW_BEM 294 295 #pragma inline(sil_wrw_bem) 296 static void 297 sil_wrw_bem(volatile uint32_t __evenaccess *mem, uint32_t data) 298 { 299 *mem = TOPPERS_SIL_REV_ENDIAN_UINT32(data); 300 } 301 302 #endif /* TOPPERS_OMIT_SIL_WRW_BEM */ 303 #endif /* SIL_ENDIAN_BIG */ 110 304 111 305 #endif /* TOPPERS_PRC_SIL_H */ -
uKadecot/trunk/ssp/arch/rx630_ccrx/rx630.h
r108 r154 1475 1475 #define PORT_PCR_B6_BIT ( 0x01U << 6U ) 1476 1476 #define PORT_PCR_B7_BIT ( 0x01U << 7U ) 1477 #define PORT0_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C080 ) 1478 #define PORT1_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C082 ) 1479 #define PORT2_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C084 ) 1480 #define PORT3_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C086 ) 1481 #define PORT4_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C088 ) 1482 #define PORT5_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08A ) 1483 #define PORT6_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08C ) 1484 #define PORT7_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08E ) 1485 #define PORT8_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C090 ) 1486 #define PORT9_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C092 ) 1487 #define PORTA_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C094 ) 1488 #define PORTB_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C096 ) 1489 #define PORTC_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C098 ) 1490 #define PORTD_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09A ) 1491 #define PORTE_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09C ) 1492 #define PORTF_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09E ) 1493 #define PORTG_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A0 ) 1494 #define PORTJ_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A4 ) 1495 #define PORT0_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C081 ) 1496 #define PORT1_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C083 ) 1497 #define PORT2_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C085 ) 1498 #define PORT3_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C087 ) 1499 #define PORT4_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C089 ) 1500 #define PORT5_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08B ) 1501 #define PORT6_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08D ) 1502 #define PORT7_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08F ) 1503 #define PORT8_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C091 ) 1504 #define PORT9_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C093 ) 1505 #define PORTA_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C095 ) 1506 #define PORTB_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C097 ) 1507 #define PORTC_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C099 ) 1508 #define PORTD_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09B ) 1509 #define PORTE_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09D ) 1510 #define PORTF_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09F ) 1511 #define PORTG_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A1 ) 1512 #define PORTJ_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A5 ) 1477 1513 1478 1514 /* … … 1767 1803 1768 1804 /* 1805 * RSPI 1806 */ 1807 #define RSPI0_SPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088380 ) 1808 #define RSPI1_SPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A0 ) 1809 #define RSPI2_SPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C0 ) 1810 #define RSPI_SPCR_SPMS_BIT ( 0x01U << 0U ) 1811 #define RSPI_SPCR_TXMD_BIT ( 0x01U << 1U ) 1812 #define RSPI_SPCR_MODFEN_BIT ( 0x01U << 2U ) 1813 #define RSPI_SPCR_MSTR_BIT ( 0x01U << 3U ) 1814 #define RSPI_SPCR_SPEIE_BIT ( 0x01U << 4U ) 1815 #define RSPI_SPCR_SPTIE_BIT ( 0x01U << 5U ) 1816 #define RSPI_SPCR_SPE_BIT ( 0x01U << 6U ) 1817 #define RSPI_SPCR_SPRIE_BIT ( 0x01U << 7U ) 1818 1819 #define RSPI0_SSLP_ADDR ( ( volatile uint8_t __evenaccess * )0x00088381 ) 1820 #define RSPI1_SSLP_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A1 ) 1821 #define RSPI2_SSLP_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C1 ) 1822 1823 #define RSPI0_SPPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088382 ) 1824 #define RSPI1_SPPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A2 ) 1825 #define RSPI2_SPPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C2 ) 1826 1827 #define RSPI0_SPSR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088383 ) 1828 #define RSPI1_SPSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A3 ) 1829 #define RSPI2_SPSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C3 ) 1830 1831 #define RSPI0_SPDR_ADDR ( ( volatile uint32_t __evenaccess * )0x00088384 ) 1832 #define RSPI1_SPDR_ADDR ( ( volatile uint32_t __evenaccess * )0x000883A4 ) 1833 #define RSPI2_SPDR_ADDR ( ( volatile uint32_t __evenaccess * )0x000883C4 ) 1834 1835 #define RSPI0_SPSCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088388 ) 1836 #define RSPI1_SPSCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A8 ) 1837 #define RSPI2_SPSCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C8 ) 1838 1839 #define RSPI0_SPSSR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088389 ) 1840 #define RSPI1_SPSSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A9 ) 1841 #define RSPI2_SPSSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C9 ) 1842 1843 #define RSPI0_SPBR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838A ) 1844 #define RSPI1_SPBR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AA ) 1845 #define RSPI2_SPBR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CA ) 1846 1847 #define RSPI0_SPDCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838B ) 1848 #define RSPI1_SPDCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AB ) 1849 #define RSPI2_SPDCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CB ) 1850 1851 #define RSPI0_SPCKD_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838C ) 1852 #define RSPI1_SPCKD_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AC ) 1853 #define RSPI2_SPCKD_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CC ) 1854 1855 #define RSPI0_SSLND_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838D ) 1856 #define RSPI1_SSLND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AD ) 1857 #define RSPI2_SSLND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CD ) 1858 1859 #define RSPI0_SPND_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838E ) 1860 #define RSPI1_SPND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AE ) 1861 #define RSPI2_SPND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CE ) 1862 1863 #define RSPI0_SPCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838F ) 1864 #define RSPI1_SPCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AF ) 1865 #define RSPI2_SPCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CF ) 1866 1867 #define RSPI0_SPCMD0_ADDR ( ( volatile uint16_t __evenaccess * )0x00088390 ) 1868 #define RSPI0_SPCMD1_ADDR ( ( volatile uint16_t __evenaccess * )0x00088392 ) 1869 #define RSPI0_SPCMD2_ADDR ( ( volatile uint16_t __evenaccess * )0x00088394 ) 1870 #define RSPI0_SPCMD3_ADDR ( ( volatile uint16_t __evenaccess * )0x00088396 ) 1871 #define RSPI0_SPCMD4_ADDR ( ( volatile uint16_t __evenaccess * )0x00088398 ) 1872 #define RSPI0_SPCMD5_ADDR ( ( volatile uint16_t __evenaccess * )0x0008839A ) 1873 #define RSPI0_SPCMD6_ADDR ( ( volatile uint16_t __evenaccess * )0x0008839C ) 1874 #define RSPI0_SPCMD7_ADDR ( ( volatile uint16_t __evenaccess * )0x0008839E ) 1875 #define RSPI1_SPCMD0_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B0 ) 1876 #define RSPI1_SPCMD1_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B2 ) 1877 #define RSPI1_SPCMD2_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B4 ) 1878 #define RSPI1_SPCMD3_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B6 ) 1879 #define RSPI1_SPCMD4_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B8 ) 1880 #define RSPI1_SPCMD5_ADDR ( ( volatile uint16_t __evenaccess * )0x000883BA ) 1881 #define RSPI1_SPCMD6_ADDR ( ( volatile uint16_t __evenaccess * )0x000883BC ) 1882 #define RSPI1_SPCMD7_ADDR ( ( volatile uint16_t __evenaccess * )0x000883BE ) 1883 #define RSPI2_SPCMD0_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D0 ) 1884 #define RSPI2_SPCMD1_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D2 ) 1885 #define RSPI2_SPCMD2_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D4 ) 1886 #define RSPI2_SPCMD3_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D6 ) 1887 #define RSPI2_SPCMD4_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D8 ) 1888 #define RSPI2_SPCMD5_ADDR ( ( volatile uint16_t __evenaccess * )0x000883DA ) 1889 #define RSPI2_SPCMD6_ADDR ( ( volatile uint16_t __evenaccess * )0x000883DC ) 1890 #define RSPI2_SPCMD7_ADDR ( ( volatile uint16_t __evenaccess * )0x000883DE ) 1891 #define RSPI_SPCMD_SPB_OFFSET (8) 1892 #define RSPI_SPCMD_SPB_MASK (0xF << RSPI_SPCMD_SPB_OFFSET) 1893 1894 /* 1769 1895 * UART関連の定義 1770 1896 *
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