Index: /asp_fm/asp/target/cqfrkfm3_gcc/E_PACKAGE
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/E_PACKAGE	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/E_PACKAGE	(revision 131)
@@ -0,0 +1,7 @@
+E_PACKAGE asp_cqfrkfm3_gcc
+VERSION %date
+
+INCLUDE MANIFEST
+INCLUDE ../../MANIFEST
+INCLUDE ../../arch/arm_m_gcc/MANIFEST
+../../cfg/cfg/cfg.exe
Index: /asp_fm/asp/target/cqfrkfm3_gcc/MANIFEST
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/MANIFEST	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/MANIFEST	(revision 131)
@@ -0,0 +1,28 @@
+PACKAGE asp_arch_arm_m_gcc
+
+E_PACKAGE
+cqfrkfm3.h
+cqfrkfm3_rom.ld
+Makefile.target
+MANIFEST
+target.tf
+target_asm.inc
+target_cfg1_out.h
+target_check.tf
+target_config.c
+target_config.h
+target_kernel.h
+target_offset.tf
+target_rename.def
+target_rename.h
+target_serial.c
+target_serial.cfg
+target_serial.h
+target_sil.h
+target_stddef.h
+target_syssvc.h
+target_test.h
+target_timer.cfg
+target_timer.h
+target_unrename.h
+target_user.txt
Index: /asp_fm/asp/target/cqfrkfm3_gcc/Makefile.target
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/Makefile.target	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/Makefile.target	(revision 131)
@@ -0,0 +1,91 @@
+#
+#		Makefile Ì^[QbgË¶
+#
+
+#
+#  {[h¼CvZbT¼CJ­Â«¼Ìè`
+#
+BOARD = cqfrkfm3
+PRC   = arm_m
+TOOL  = gcc
+
+#
+#  ÅK»µ½­È¢êÍtrueÉè`
+#
+#OMIT_OPTIMIZATION = true
+
+#
+#  RpCIvV
+#
+INCLUDES := $(INCLUDES) -I$(TARGETDIR)
+COPTS := $(COPTS) -mlittle-endian -mcpu=cortex-m3
+LDFLAGS := $(LDFLAGS) -mlittle-endian
+LIBS := $(LIBS)
+
+#
+#  J[lÉÖ·éè`
+#
+KERNEL_DIR := $(KERNEL_DIR) $(TARGETDIR)
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS)
+KERNEL_COBJS := $(KERNEL_COBJS) target_config.o core_timer.o
+
+#
+#  VXeT[rXÉÖ·éè`
+#
+SYSSVC_DIR := $(SYSSVC_DIR) 
+SYSSVC_COBJS := $(SYSSVC_COBJS) target_serial.o
+
+#
+#  g[XOÉÖ·éÝè
+#
+ifeq ($(ENABLE_TRACE),true)
+      COPTS := $(COPTS) -DTOPPERS_ENABLE_TRACE
+      KERNEL_DIR := $(KERNEL_DIR) $(SRCDIR)/arch/logtrace
+      KERNEL_COBJS := $(KERNEL_COBJS) trace_config.o trace_dump.o
+endif
+
+#
+#  GNUJ­Â«Ì^[QbgA[LeN`Ìè`
+#
+GCC_TARGET = arm-none-eabi
+
+#
+#  JXNvgÌè`
+#
+LDSCRIPT = $(TARGETDIR)/$(BOARD)_rom.ld
+
+#
+#  X^[gAbvW
+[ÉÖ·éè`
+#
+#  cqfrkfm3_rom.ldÉuSTARTUP(start.o)vðLqµ½½ßC
+#  X^[gAbvW
+[Ì¼OðHIDDEN_OBJSÉè`·éD
+#  Ü½CLDFLAGSÉ-nostdlibðÇÁµÄ¢éD
+#
+HIDDEN_OBJS = start.o
+
+$(HIDDEN_OBJS): %.o: %.S
+	$(CC) -c $(CFLAGS) $(KERNEL_CFLAGS) $<
+
+$(HIDDEN_OBJS:.o=.d): %.d: %.S
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) \
+		-O "$(CFLAGS) $(KERNEL_CFLAGS)" $< >> Makefile.depend
+
+LDFLAGS := -nostdlib $(LDFLAGS)
+
+#
+#  Ë¶ÖWÌè`
+#
+kernel_cfg.timestamp: $(TARGETDIR)/target.tf
+$(OBJFILE): $(TARGETDIR)/target_check.tf
+
+# 
+#  ItZbgt@C¶¬Ì½ßÌè` 
+# 
+OFFSET_TF := $(TARGETDIR)/target_offset.tf
+
+#
+#  RAË¶ÌCN[h
+#
+include $(SRCDIR)/arch/$(PRC)_$(TOOL)/common/Makefile.core
Index: /asp_fm/asp/target/cqfrkfm3_gcc/cqfrkfm3_ram.ld
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/cqfrkfm3_ram.ld	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/cqfrkfm3_ram.ld	(revision 131)
@@ -0,0 +1,90 @@
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x00000000, LENGTH = 1024K
+    RAM (rwx) : ORIGIN = 0x1fff0000, LENGTH = 128K
+}
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm","elf32-littlearm") 
+OUTPUT_ARCH(arm)
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+STARTUP(start.o)
+ENTRY(_start)
+
+SECTIONS
+{
+    .text :
+    {  
+        __text = . ; 
+        KEEP(*(.vector))
+        *(.text*)
+        *(.glue_7t)
+        *(.glue_7)
+    } > RAM
+    _etext = .	;
+    PROVIDE (etext = .)	;
+
+    .rodata : { 
+        *(.rodata*) 
+    } > RAM
+
+    . = ALIGN(4);
+    __idata_start = . ;
+    .data   :  AT(__idata_start) 
+    {
+        __data_start = . ;
+        *(vtable)
+        *(.data*)
+    } > RAM
+    __idata_end = __idata_start + SIZEOF(.data);
+    _edata  =  . ;
+    PROVIDE (edata = .);
+    . = ALIGN(4);
+
+    .bss       :
+    {
+       __bss_start = .	;
+      *(.bss*)
+      *(COMMON)
+      . = ALIGN(32 / 8);
+    } > RAM
+   . = ALIGN(32 / 8);
+     _end = .		;
+    __bss_end = .;
+    PROVIDE (end = .)	;
+
+    .comment 0 : { *(.comment) }
+
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to 
+     the beginning of the section so we begin them at 0.  */
+
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+}
Index: /asp_fm/asp/target/cqfrkfm3_gcc/cqfrkfm3_rom.ld
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/cqfrkfm3_rom.ld	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/cqfrkfm3_rom.ld	(revision 131)
@@ -0,0 +1,89 @@
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x00000000, LENGTH = 1024K
+    RAM (rwx) : ORIGIN = 0x1fff0000, LENGTH = 128K
+}
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm","elf32-littlearm") 
+OUTPUT_ARCH(arm)
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+STARTUP(start.o)
+
+SECTIONS
+{
+    .text :
+    {
+        __text = . ; 
+        *(.vector)
+        *(.text*)
+        *(.glue_7t)
+        *(.glue_7)
+    } > ROM
+    _etext = .	;
+    PROVIDE (etext = .)	;
+
+    .rodata : { 
+        *(.rodata*) 
+    } > ROM
+
+    . = ALIGN(4);
+    __idata_start = . ;
+    .data   :  AT(__idata_start) 
+    {
+        __data_start = . ;
+        *(vtable)
+        *(.data*)
+    } > RAM
+    __idata_end = __idata_start + SIZEOF(.data);
+    _edata  =  . ;
+    PROVIDE (edata = .);
+    . = ALIGN(4);
+
+    .bss       :
+    {
+       __bss_start = .	;
+      *(.bss*)
+      *(COMMON)
+      . = ALIGN(32 / 8);
+    } > RAM
+   . = ALIGN(32 / 8);
+     _end = .		;
+    __bss_end = .;
+    PROVIDE (end = .)	;
+
+    .comment 0 : { *(.comment) }
+
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to 
+     the beginning of the section so we begin them at 0.  */
+
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+}
Index: /asp_fm/asp/target/cqfrkfm3_gcc/fm3_mb9bxxx.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/fm3_mb9bxxx.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/fm3_mb9bxxx.h	(revision 131)
@@ -0,0 +1,694 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+#ifndef TOPPERS_FM3_MB9BXXX_H
+#define TOPPERS_FM3_MB9BXXX_H
+
+#include <sil.h>
+
+/*
+ *  VXeNbNÌè`i­Uqüg4MHzj
+ */
+#define SystemFrequency	144000000
+#define SysFreHCLK		144000000	/* HCLK = MasterClock / 1 */
+#define SysFrePCLK0		72000000	/* PCLK0 = HCLK / 2 */
+#define SysFrePCLK1		72000000	/* PCLK1 = HCLK / 2 */
+#define SysFrePCLK2		72000000	/* PCLK2 = HCLK / 2 */
+#define SysFreTPIU		0			/* TPIUCLK : Disable */
+
+#define SYS_CLOCK		(SystemFrequency)
+
+/*
+ *  ÝÔÌÅål
+ */
+#define TMAX_INTNO   (16 + 47)
+
+/*
+ *  ÝDæxÌrbg
+ */
+#define TBITW_IPRI     4
+
+/*
+ *  ÝDæxrbgÌTuDæxÌrbg
+ */
+#define TBITW_SUBIPRI  0
+
+/*
+ *  ÝxN^Ôè`
+ */
+#define IRQ_VECTOR_CSV			(16 + 0)
+#define IRQ_VECTOR_SWDT			(16 + 1)
+#define IRQ_VECTOR_LVD			(16 + 2)
+#define IRQ_VECTOR_WFG			(16 + 3)
+#define IRQ_VECTOR_EXINT0_7		(16 + 4)
+#define IRQ_VECTOR_EXINT8_31	(16 + 5)
+#define IRQ_VECTOR_DTIM_QDU		(16 + 6)
+#define IRQ_VECTOR_MFS0RX		(16 + 7)
+#define IRQ_VECTOR_MFS0TX		(16 + 8)
+#define IRQ_VECTOR_MFS1RX		(16 + 9)
+#define IRQ_VECTOR_MFS1TX		(16 + 10)
+#define IRQ_VECTOR_MFS2RX		(16 + 11)
+#define IRQ_VECTOR_MFS2TX		(16 + 12)
+#define IRQ_VECTOR_MFS3RX		(16 + 13)
+#define IRQ_VECTOR_MFS3TX		(16 + 14)
+#define IRQ_VECTOR_MFS4RX		(16 + 15)
+#define IRQ_VECTOR_MFS4TX		(16 + 16)
+#define IRQ_VECTOR_MFS5RX		(16 + 17)
+#define IRQ_VECTOR_MFS5TX		(16 + 18)
+#define IRQ_VECTOR_MFS6RX		(16 + 19)
+#define IRQ_VECTOR_MFS6TX		(16 + 20)
+#define IRQ_VECTOR_MFS7RX		(16 + 21)
+#define IRQ_VECTOR_MFS7TX		(16 + 22)
+#define IRQ_VECTOR_PPG			(16 + 23)
+#define IRQ_VECTOR_OSC_PLL_WC	(16 + 24)
+#define IRQ_VECTOR_ADC0	 		(16 + 25)
+#define IRQ_VECTOR_ADC1 		(16 + 26)
+#define IRQ_VECTOR_ADC2 		(16 + 27)
+#define IRQ_VECTOR_FRTIM		(16 + 28)
+#define IRQ_VECTOR_INCAP		(16 + 29)
+#define IRQ_VECTOR_OUTCOMP		(16 + 30)
+#define IRQ_VECTOR_BTIM0_7		(16 + 31)
+#define IRQ_VECTOR_CAN0_ETH0 	(16 + 32)
+#define IRQ_VECTOR_CAN1_ETH1 	(16 + 33)
+#define IRQ_VECTOR_USBF 		(16 + 34)
+#define IRQ_VECTOR_USBF_USBH	(16 + 35)
+#define IRQ_VECTOR_DMAC0		(16 + 38)
+#define IRQ_VECTOR_DMAC1		(16 + 39)
+#define IRQ_VECTOR_DMAC2		(16 + 40)
+#define IRQ_VECTOR_DMAC3		(16 + 41)
+#define IRQ_VECTOR_DMAC4		(16 + 42)
+#define IRQ_VECTOR_DMAC5		(16 + 43)
+#define IRQ_VECTOR_DMAC6		(16 + 44)
+#define IRQ_VECTOR_DMAC7		(16 + 45)
+#define IRQ_VECTOR_BTIM8_15		(16 + 46)
+
+#define FM3_PERIPH_BASE			(0x40000000UL)
+#define FM3_FLASH_IF_BASE		(FM3_PERIPH_BASE + 0x00000UL)
+#define FM3_CRG_BASE			(FM3_PERIPH_BASE + 0x10000UL)
+#define FM3_HWWDT_BASE			(FM3_PERIPH_BASE + 0x11000UL)
+#define FM3_BT_BASE				(FM3_PERIPH_BASE + 0x25000UL)
+#define FM3_ADC0_BASE			(FM3_PERIPH_BASE + 0x27000UL)
+#define FM3_ADC1_BASE			(FM3_PERIPH_BASE + 0x27100UL)
+#define FM3_ADC2_BASE			(FM3_PERIPH_BASE + 0x27200UL)
+#define FM3_CRTRIM_BASE			(FM3_PERIPH_BASE + 0x2E000UL)
+#define FM3_EXTI_BASE			(FM3_PERIPH_BASE + 0x30000UL)
+#define FM3_INTREQ_BASE			(FM3_PERIPH_BASE + 0x31000UL)
+#define FM3_GPIO_BASE			(FM3_PERIPH_BASE + 0x33000UL)
+#define FM3_MFS0_UART_BASE		(FM3_PERIPH_BASE + 0x38000UL)
+#define FM3_MFS1_UART_BASE		(FM3_PERIPH_BASE + 0x38100UL)
+#define FM3_MFS2_UART_BASE		(FM3_PERIPH_BASE + 0x38200UL)
+#define FM3_MFS3_UART_BASE		(FM3_PERIPH_BASE + 0x38300UL)
+#define FM3_MFS4_UART_BASE		(FM3_PERIPH_BASE + 0x38400UL)
+#define FM3_MFS5_UART_BASE		(FM3_PERIPH_BASE + 0x38500UL)
+#define FM3_MFS6_UART_BASE		(FM3_PERIPH_BASE + 0x38600UL)
+#define FM3_MFS7_UART_BASE		(FM3_PERIPH_BASE + 0x38700UL)
+#define FM3_EXTBUS_BASE			(FM3_PERIPH_BASE + 0x3F000UL)
+#define FM3_DMAC_BASE			(FM3_PERIPH_BASE + 0x60000UL)
+
+#define BITBAND(a, b)			((volatile uint32_t*)(0x42000000UL + (a - FM3_PERIPH_BASE) * 32 + b * 4))
+
+#define FM3_FLASH_IF_CRTRMM		(FM3_FLASH_IF_BASE + 0x100)
+
+#define FM3_CRG_SCM_CTL			(FM3_CRG_BASE + 0x00)
+#define FM3_CRG_SCM_STR			(FM3_CRG_BASE + 0x04)
+#define FM3_CRG_STB_CTL			(FM3_CRG_BASE + 0x08)
+#define FM3_CRG_RST_STR			(FM3_CRG_BASE + 0x0c)
+#define FM3_CRG_BSC_PSR			(FM3_CRG_BASE + 0x10)
+#define FM3_CRG_APBC0_PSR		(FM3_CRG_BASE + 0x14)
+#define FM3_CRG_APBC1_PSR		(FM3_CRG_BASE + 0x18)
+#define FM3_CRG_APBC2_PSR		(FM3_CRG_BASE + 0x1C)
+#define FM3_CRG_SWC_PSR			(FM3_CRG_BASE + 0x20)
+#define FM3_CRG_TTC_PSR			(FM3_CRG_BASE + 0x28)
+#define FM3_CRG_CSW_TMR			(FM3_CRG_BASE + 0x30)
+#define FM3_CRG_PSW_TMR			(FM3_CRG_BASE + 0x34)
+#define FM3_CRG_PLL_CTL1		(FM3_CRG_BASE + 0x38)
+#define FM3_CRG_PLL_CTL2		(FM3_CRG_BASE + 0x3c)
+#define FM3_CRG_CSV_CTL			(FM3_CRG_BASE + 0x40)
+#define FM3_CRG_CSV_STR			(FM3_CRG_BASE + 0x44)
+#define FM3_CRG_FCSWH_CTL		(FM3_CRG_BASE + 0x48)
+#define FM3_CRG_FCSWL_CTL		(FM3_CRG_BASE + 0x4C)
+#define FM3_CRG_FCSWD_CTL		(FM3_CRG_BASE + 0x50)
+#define FM3_CRG_DBWDT_CTL		(FM3_CRG_BASE + 0x54)
+#define FM3_CRG_INT_ENR			(FM3_CRG_BASE + 0x60)
+#define FM3_CRG_INT_STR			(FM3_CRG_BASE + 0x64)
+#define FM3_CRG_INT_CLR			(FM3_CRG_BASE + 0x68)
+
+#define SCM_CTL_MOSCE			0x02
+#define SCM_CTL_SOSCE			0x08
+#define SCM_CTL_PLLE			0x10
+#define SCM_CTL_RCS_			0xe0
+#define SCM_STR_MORDY			0x02
+#define SCM_STR_SORDY			0x08
+#define SCM_STR_PLRDY			0x10
+#define SCM_STR_RCM				0xe0
+#define APBC1_PSR_APBC1RST		0x10
+#define APBC1_PSR_APBC1EN		0x80
+#define APBC2_PSR_APBC2RST		0x10
+#define APBC2_PSR_APBC2EN		0x80
+#define SWC_PSR_TESTB			0x80
+#define PSW_TMR_PINC			0x10
+
+#define FM3_HWWDT_WDG_LDR		(FM3_HWWDT_BASE + 0x000)
+#define FM3_HWWDT_WDG_VLR		(FM3_HWWDT_BASE + 0x004)
+#define FM3_HWWDT_WDG_CTL		(FM3_HWWDT_BASE + 0x008)
+#define FM3_HWWDT_WDG_ICL		(FM3_HWWDT_BASE + 0x00C)
+#define FM3_HWWDT_WDG_RIS		(FM3_HWWDT_BASE + 0x010)
+#define FM3_HWWDT_WDG_LCK		(FM3_HWWDT_BASE + 0xC00)
+
+#define FM3_BT_CH0				(FM3_BT_BASE + 0x000)
+#define FM3_BT_CH1				(FM3_BT_BASE + 0x040)
+#define FM3_BT_CH2				(FM3_BT_BASE + 0x080)
+#define FM3_BT_CH3				(FM3_BT_BASE + 0x0C0)
+#define FM3_BT_BTSEL0123		(FM3_BT_BASE + 0x101)
+#define FM3_BT_CH4				(FM3_BT_BASE + 0x200)
+#define FM3_BT_CH5				(FM3_BT_BASE + 0x240)
+#define FM3_BT_CH6				(FM3_BT_BASE + 0x280)
+#define FM3_BT_CH7				(FM3_BT_BASE + 0x2C0)
+#define FM3_BT_BTSEL4567		(FM3_BT_BASE + 0x301)
+#define FM3_BT_CH8				(FM3_BT_BASE + 0x400)
+#define FM3_BT_CH9				(FM3_BT_BASE + 0x440)
+#define FM3_BT_CHA				(FM3_BT_BASE + 0x480)
+#define FM3_BT_CHB				(FM3_BT_BASE + 0x4C0)
+#define FM3_BT_BTSEL89AB		(FM3_BT_BASE + 0x501)
+#define FM3_BT_CHC				(FM3_BT_BASE + 0x600)
+#define FM3_BT_CHD				(FM3_BT_BASE + 0x640)
+#define FM3_BT_CHE				(FM3_BT_BASE + 0x680)
+#define FM3_BT_CHF				(FM3_BT_BASE + 0x6C0)
+#define FM3_BT_BTSELCDEF		(FM3_BT_BASE + 0x701)
+#define FM3_BT_BTSSSR			(FM3_BT_BASE + 0xFFC)
+
+#define FM3_BT0_PCSR			(FM3_BT_CH0 + 0x00)
+#define FM3_BT0_PDUT			(FM3_BT_CH0 + 0x04)
+#define FM3_BT0_TMR				(FM3_BT_CH0 + 0x08)
+#define FM3_BT0_TMCR			(FM3_BT_CH0 + 0x0C)
+#define FM3_BT0_STC				(FM3_BT_CH0 + 0x10)
+#define FM3_BT0_TMCR2			(FM3_BT_CH0 + 0x11)
+#define FM3_BT1_PCSR			(FM3_BT_CH1 + 0x00)
+#define FM3_BT1_PDUT			(FM3_BT_CH1 + 0x04)
+#define FM3_BT1_TMR				(FM3_BT_CH1 + 0x08)
+#define FM3_BT1_TMCR			(FM3_BT_CH1 + 0x0C)
+#define FM3_BT1_STC				(FM3_BT_CH1 + 0x10)
+#define FM3_BT1_TMCR2			(FM3_BT_CH1 + 0x11)
+#define FM3_BT2_PCSR			(FM3_BT_CH2 + 0x00)
+#define FM3_BT2_PDUT			(FM3_BT_CH2 + 0x04)
+#define FM3_BT2_TMR				(FM3_BT_CH2 + 0x08)
+#define FM3_BT2_TMCR			(FM3_BT_CH2 + 0x0C)
+#define FM3_BT2_STC				(FM3_BT_CH2 + 0x10)
+#define FM3_BT2_TMCR2			(FM3_BT_CH2 + 0x11)
+#define FM3_BT3_PCSR			(FM3_BT_CH3 + 0x00)
+#define FM3_BT3_PDUT			(FM3_BT_CH3 + 0x04)
+#define FM3_BT3_TMR				(FM3_BT_CH3 + 0x08)
+#define FM3_BT3_TMCR			(FM3_BT_CH3 + 0x0C)
+#define FM3_BT3_STC				(FM3_BT_CH3 + 0x10)
+#define FM3_BT3_TMCR2			(FM3_BT_CH3 + 0x11)
+#define FM3_BT4_PCSR			(FM3_BT_CH4 + 0x00)
+#define FM3_BT4_PDUT			(FM3_BT_CH4 + 0x04)
+#define FM3_BT4_TMR				(FM3_BT_CH4 + 0x08)
+#define FM3_BT4_TMCR			(FM3_BT_CH4 + 0x0C)
+#define FM3_BT4_STC				(FM3_BT_CH4 + 0x10)
+#define FM3_BT4_TMCR2			(FM3_BT_CH4 + 0x11)
+#define FM3_BT5_PCSR			(FM3_BT_CH5 + 0x00)
+#define FM3_BT5_PDUT			(FM3_BT_CH5 + 0x04)
+#define FM3_BT5_TMR				(FM3_BT_CH5 + 0x08)
+#define FM3_BT5_TMCR			(FM3_BT_CH5 + 0x0C)
+#define FM3_BT5_STC				(FM3_BT_CH5 + 0x10)
+#define FM3_BT5_TMCR2			(FM3_BT_CH5 + 0x11)
+#define FM3_BT6_PCSR			(FM3_BT_CH6 + 0x00)
+#define FM3_BT6_PDUT			(FM3_BT_CH6 + 0x04)
+#define FM3_BT6_TMR				(FM3_BT_CH6 + 0x08)
+#define FM3_BT6_TMCR			(FM3_BT_CH6 + 0x0C)
+#define FM3_BT6_STC				(FM3_BT_CH6 + 0x10)
+#define FM3_BT6_TMCR2			(FM3_BT_CH6 + 0x11)
+#define FM3_BT7_PCSR			(FM3_BT_CH7 + 0x00)
+#define FM3_BT7_PDUT			(FM3_BT_CH7 + 0x04)
+#define FM3_BT7_TMR				(FM3_BT_CH7 + 0x08)
+#define FM3_BT7_TMCR			(FM3_BT_CH7 + 0x0C)
+#define FM3_BT7_STC				(FM3_BT_CH7 + 0x10)
+#define FM3_BT7_TMCR2			(FM3_BT_CH7 + 0x11)
+#define FM3_BT8_PCSR			(FM3_BT_CH8 + 0x00)
+#define FM3_BT8_PDUT			(FM3_BT_CH8 + 0x04)
+#define FM3_BT8_TMR				(FM3_BT_CH8 + 0x08)
+#define FM3_BT8_TMCR			(FM3_BT_CH8 + 0x0C)
+#define FM3_BT8_STC				(FM3_BT_CH8 + 0x10)
+#define FM3_BT8_TMCR2			(FM3_BT_CH8 + 0x11)
+#define FM3_BT9_PCSR			(FM3_BT_CH9 + 0x00)
+#define FM3_BT9_PDUT			(FM3_BT_CH9 + 0x04)
+#define FM3_BT9_TMR				(FM3_BT_CH9 + 0x08)
+#define FM3_BT9_TMCR			(FM3_BT_CH9 + 0x0C)
+#define FM3_BT9_STC				(FM3_BT_CH9 + 0x10)
+#define FM3_BT9_TMCR2			(FM3_BT_CH9 + 0x11)
+#define FM3_BT10_PCSR			(FM3_BT_CHA + 0x00)
+#define FM3_BT10_PDUT			(FM3_BT_CHA + 0x04)
+#define FM3_BT10_TMR			(FM3_BT_CHA + 0x08)
+#define FM3_BT10_TMCR			(FM3_BT_CHA + 0x0C)
+#define FM3_BT10_STC			(FM3_BT_CHA + 0x10)
+#define FM3_BT10_TMCR2			(FM3_BT_CHA + 0x11)
+#define FM3_BT11_PCSR			(FM3_BT_CHB + 0x00)
+#define FM3_BT11_PDUT			(FM3_BT_CHB + 0x04)
+#define FM3_BT11_TMR			(FM3_BT_CHB + 0x08)
+#define FM3_BT11_TMCR			(FM3_BT_CHB + 0x0C)
+#define FM3_BT11_STC			(FM3_BT_CHB + 0x10)
+#define FM3_BT11_TMCR2			(FM3_BT_CHB + 0x11)
+#define FM3_BT12_PCSR			(FM3_BT_CHC + 0x00)
+#define FM3_BT12_PDUT			(FM3_BT_CHC + 0x04)
+#define FM3_BT12_TMR			(FM3_BT_CHC + 0x08)
+#define FM3_BT12_TMCR			(FM3_BT_CHC + 0x0C)
+#define FM3_BT12_STC			(FM3_BT_CHC + 0x10)
+#define FM3_BT12_TMCR2			(FM3_BT_CHC + 0x11)
+#define FM3_BT13_PCSR			(FM3_BT_CHD + 0x00)
+#define FM3_BT13_PDUT			(FM3_BT_CHD + 0x04)
+#define FM3_BT13_TMR			(FM3_BT_CHD + 0x08)
+#define FM3_BT13_TMCR			(FM3_BT_CHD + 0x0C)
+#define FM3_BT13_STC			(FM3_BT_CHD + 0x10)
+#define FM3_BT13_TMCR2			(FM3_BT_CHD + 0x11)
+#define FM3_BT14_PCSR			(FM3_BT_CHE + 0x00)
+#define FM3_BT14_PDUT			(FM3_BT_CHE + 0x04)
+#define FM3_BT14_TMR			(FM3_BT_CHE + 0x08)
+#define FM3_BT14_TMCR			(FM3_BT_CHE + 0x0C)
+#define FM3_BT14_STC			(FM3_BT_CHE + 0x10)
+#define FM3_BT14_TMCR2			(FM3_BT_CHE + 0x11)
+#define FM3_BT15_PCSR			(FM3_BT_CHF + 0x00)
+#define FM3_BT15_PDUT			(FM3_BT_CHF + 0x04)
+#define FM3_BT15_TMR			(FM3_BT_CHF + 0x08)
+#define FM3_BT15_TMCR			(FM3_BT_CHF + 0x0C)
+#define FM3_BT15_STC			(FM3_BT_CHF + 0x10)
+#define FM3_BT15_TMCR2			(FM3_BT_CHF + 0x11)
+
+#define FM3_ADC0_ADSR			(FM3_ADC0_BASE + 0x00)
+#define FM3_ADC0_ADCR			(FM3_ADC0_BASE + 0x01)
+#define FM3_ADC0_SFNS			(FM3_ADC0_BASE + 0x08)
+#define FM3_ADC0_SCCR			(FM3_ADC0_BASE + 0x09)
+#define FM3_ADC0_SCFD			(FM3_ADC0_BASE + 0x0c)
+#define FM3_ADC0_SCIS23			(FM3_ADC0_BASE + 0x10)
+#define FM3_ADC0_SCIS01			(FM3_ADC0_BASE + 0x14)
+#define FM3_ADC0_PFNS			(FM3_ADC0_BASE + 0x18)
+#define FM3_ADC0_PCCR			(FM3_ADC0_BASE + 0x19)
+#define FM3_ADC0_PCFD			(FM3_ADC0_BASE + 0x1c)
+#define FM3_ADC0_PCIS			(FM3_ADC0_BASE + 0x20)
+#define FM3_ADC0_CMPCR			(FM3_ADC0_BASE + 0x24)
+#define FM3_ADC0_CMPD			(FM3_ADC0_BASE + 0x26)
+#define FM3_ADC0_ADSS23			(FM3_ADC0_BASE + 0x28)
+#define FM3_ADC0_ADSS01			(FM3_ADC0_BASE + 0x2c)
+#define FM3_ADC0_ADST1			(FM3_ADC0_BASE + 0x30)
+#define FM3_ADC0_ADST0			(FM3_ADC0_BASE + 0x31)
+#define FM3_ADC0_ADCT			(FM3_ADC0_BASE + 0x34)
+#define FM3_ADC0_PRTSL			(FM3_ADC0_BASE + 0x38)
+#define FM3_ADC0_SCTSL			(FM3_ADC0_BASE + 0x39)
+#define FM3_ADC0_ADCEN			(FM3_ADC0_BASE + 0x3c)
+#define FM3_ADC1_ADSR			(FM3_ADC1_BASE + 0x00)
+#define FM3_ADC1_ADCR			(FM3_ADC1_BASE + 0x01)
+#define FM3_ADC1_SFNS			(FM3_ADC1_BASE + 0x08)
+#define FM3_ADC1_SCCR			(FM3_ADC1_BASE + 0x09)
+#define FM3_ADC1_SCFD			(FM3_ADC1_BASE + 0x0c)
+#define FM3_ADC1_SCIS23			(FM3_ADC1_BASE + 0x10)
+#define FM3_ADC1_SCIS01			(FM3_ADC1_BASE + 0x14)
+#define FM3_ADC1_PFNS			(FM3_ADC1_BASE + 0x18)
+#define FM3_ADC1_PCCR			(FM3_ADC1_BASE + 0x19)
+#define FM3_ADC1_PCFD			(FM3_ADC1_BASE + 0x1c)
+#define FM3_ADC1_PCIS			(FM3_ADC1_BASE + 0x20)
+#define FM3_ADC1_CMPCR			(FM3_ADC1_BASE + 0x24)
+#define FM3_ADC1_CMPD			(FM3_ADC1_BASE + 0x26)
+#define FM3_ADC1_ADSS23			(FM3_ADC1_BASE + 0x28)
+#define FM3_ADC1_ADSS01			(FM3_ADC1_BASE + 0x2c)
+#define FM3_ADC1_ADST1			(FM3_ADC1_BASE + 0x30)
+#define FM3_ADC1_ADST0			(FM3_ADC1_BASE + 0x31)
+#define FM3_ADC1_ADCT			(FM3_ADC1_BASE + 0x34)
+#define FM3_ADC1_PRTSL			(FM3_ADC1_BASE + 0x38)
+#define FM3_ADC1_SCTSL			(FM3_ADC1_BASE + 0x39)
+#define FM3_ADC1_ADCEN			(FM3_ADC1_BASE + 0x3c)
+#define FM3_ADC2_ADSR			(FM3_ADC2_BASE + 0x00)
+#define FM3_ADC2_ADCR			(FM3_ADC2_BASE + 0x01)
+#define FM3_ADC2_SFNS			(FM3_ADC2_BASE + 0x08)
+#define FM3_ADC2_SCCR			(FM3_ADC2_BASE + 0x09)
+#define FM3_ADC2_SCFD			(FM3_ADC2_BASE + 0x0c)
+#define FM3_ADC2_SCIS23			(FM3_ADC2_BASE + 0x10)
+#define FM3_ADC2_SCIS01			(FM3_ADC2_BASE + 0x14)
+#define FM3_ADC2_PFNS			(FM3_ADC2_BASE + 0x18)
+#define FM3_ADC2_PCCR			(FM3_ADC2_BASE + 0x19)
+#define FM3_ADC2_PCFD			(FM3_ADC2_BASE + 0x1c)
+#define FM3_ADC2_PCIS			(FM3_ADC2_BASE + 0x20)
+#define FM3_ADC2_CMPCR			(FM3_ADC2_BASE + 0x24)
+#define FM3_ADC2_CMPD			(FM3_ADC2_BASE + 0x26)
+#define FM3_ADC2_ADSS23			(FM3_ADC2_BASE + 0x28)
+#define FM3_ADC2_ADSS01			(FM3_ADC2_BASE + 0x2c)
+#define FM3_ADC2_ADST1			(FM3_ADC2_BASE + 0x30)
+#define FM3_ADC2_ADST0			(FM3_ADC2_BASE + 0x31)
+#define FM3_ADC2_ADCT			(FM3_ADC2_BASE + 0x34)
+#define FM3_ADC2_PRTSL			(FM3_ADC2_BASE + 0x38)
+#define FM3_ADC2_SCTSL			(FM3_ADC2_BASE + 0x39)
+#define FM3_ADC2_ADCEN			(FM3_ADC2_BASE + 0x3c)
+
+#define FM3_CRTRIM_MCR_PSR		(FM3_CRTRIM_BASE + 0x00)
+#define FM3_CRTRIM_MCR_FTRM		(FM3_CRTRIM_BASE + 0x04)
+#define FM3_CRTRIM_MCR_RLR		(FM3_CRTRIM_BASE + 0x0C)
+
+#define FM3_EXTI_ENIR			(FM3_EXTI_BASE + 0x00)
+#define FM3_EXTI_EIRR			(FM3_EXTI_BASE + 0x04)
+#define FM3_EXTI_EICL			(FM3_EXTI_BASE + 0x08)
+#define FM3_EXTI_ELVR			(FM3_EXTI_BASE + 0x0C)
+#define FM3_EXTI_ELVR1			(FM3_EXTI_BASE + 0x10)
+#define FM3_EXTI_NMIRR			(FM3_EXTI_BASE + 0x14)
+#define FM3_EXTI_NMICL			(FM3_EXTI_BASE + 0x18)
+
+#define FM3_INTREQ_DRQSEL		(FM3_INTREQ_BASE + 0x000)
+#define FM3_INTREQ_ODDPKS		(FM3_INTREQ_BASE + 0x00B)
+#define FM3_INTREQ_EXC02MON		(FM3_INTREQ_BASE + 0x010)
+#define FM3_INTREQ_IRQ00MON		(FM3_INTREQ_BASE + 0x014)
+#define FM3_INTREQ_IRQ01MON		(FM3_INTREQ_BASE + 0x018)
+#define FM3_INTREQ_IRQ02MON		(FM3_INTREQ_BASE + 0x01C)
+#define FM3_INTREQ_IRQ03MON		(FM3_INTREQ_BASE + 0x020)
+#define FM3_INTREQ_IRQ04MON		(FM3_INTREQ_BASE + 0x024)
+#define FM3_INTREQ_IRQ05MON		(FM3_INTREQ_BASE + 0x028)
+#define FM3_INTREQ_IRQ06MON		(FM3_INTREQ_BASE + 0x02C)
+#define FM3_INTREQ_IRQ07MON		(FM3_INTREQ_BASE + 0x030)
+#define FM3_INTREQ_IRQ08MON		(FM3_INTREQ_BASE + 0x034)
+#define FM3_INTREQ_IRQ09MON		(FM3_INTREQ_BASE + 0x038)
+#define FM3_INTREQ_IRQ10MON		(FM3_INTREQ_BASE + 0x03C)
+#define FM3_INTREQ_IRQ11MON		(FM3_INTREQ_BASE + 0x040)
+#define FM3_INTREQ_IRQ12MON		(FM3_INTREQ_BASE + 0x044)
+#define FM3_INTREQ_IRQ13MON		(FM3_INTREQ_BASE + 0x048)
+#define FM3_INTREQ_IRQ14MON		(FM3_INTREQ_BASE + 0x04C)
+#define FM3_INTREQ_IRQ15MON		(FM3_INTREQ_BASE + 0x050)
+#define FM3_INTREQ_IRQ16MON		(FM3_INTREQ_BASE + 0x054)
+#define FM3_INTREQ_IRQ17MON		(FM3_INTREQ_BASE + 0x058)
+#define FM3_INTREQ_IRQ18MON		(FM3_INTREQ_BASE + 0x05C)
+#define FM3_INTREQ_IRQ19MON		(FM3_INTREQ_BASE + 0x060)
+#define FM3_INTREQ_IRQ20MON		(FM3_INTREQ_BASE + 0x064)
+#define FM3_INTREQ_IRQ21MON		(FM3_INTREQ_BASE + 0x068)
+#define FM3_INTREQ_IRQ22MON		(FM3_INTREQ_BASE + 0x06C)
+#define FM3_INTREQ_IRQ23MON		(FM3_INTREQ_BASE + 0x070)
+#define FM3_INTREQ_IRQ24MON		(FM3_INTREQ_BASE + 0x074)
+#define FM3_INTREQ_IRQ25MON		(FM3_INTREQ_BASE + 0x078)
+#define FM3_INTREQ_IRQ26MON		(FM3_INTREQ_BASE + 0x07C)
+#define FM3_INTREQ_IRQ27MON		(FM3_INTREQ_BASE + 0x080)
+#define FM3_INTREQ_IRQ28MON		(FM3_INTREQ_BASE + 0x084)
+#define FM3_INTREQ_IRQ29MON		(FM3_INTREQ_BASE + 0x088)
+#define FM3_INTREQ_IRQ30MON		(FM3_INTREQ_BASE + 0x08C)
+#define FM3_INTREQ_IRQ31MON		(FM3_INTREQ_BASE + 0x090)
+#define FM3_INTREQ_IRQ32MON		(FM3_INTREQ_BASE + 0x094)
+#define FM3_INTREQ_IRQ33MON		(FM3_INTREQ_BASE + 0x098)
+#define FM3_INTREQ_IRQ34MON		(FM3_INTREQ_BASE + 0x09C)
+#define FM3_INTREQ_IRQ35MON		(FM3_INTREQ_BASE + 0x0A0)
+#define FM3_INTREQ_IRQ36MON		(FM3_INTREQ_BASE + 0x0A4)
+#define FM3_INTREQ_IRQ37MON		(FM3_INTREQ_BASE + 0x0A8)
+#define FM3_INTREQ_IRQ38MON		(FM3_INTREQ_BASE + 0x0AC)
+#define FM3_INTREQ_IRQ39MON		(FM3_INTREQ_BASE + 0x0B0)
+#define FM3_INTREQ_IRQ40MON		(FM3_INTREQ_BASE + 0x0B4)
+#define FM3_INTREQ_IRQ41MON		(FM3_INTREQ_BASE + 0x0B8)
+#define FM3_INTREQ_IRQ42MON		(FM3_INTREQ_BASE + 0x0BC)
+#define FM3_INTREQ_IRQ43MON		(FM3_INTREQ_BASE + 0x0C0)
+#define FM3_INTREQ_IRQ44MON		(FM3_INTREQ_BASE + 0x0C4)
+#define FM3_INTREQ_IRQ45MON		(FM3_INTREQ_BASE + 0x0C8)
+#define FM3_INTREQ_IRQ46MON		(FM3_INTREQ_BASE + 0x0CC)
+#define FM3_INTREQ_IRQ47MON		(FM3_INTREQ_BASE + 0x0D0)
+#define FM3_INTREQ_DRQSEL1		(FM3_INTREQ_BASE + 0x200)
+#define FM3_INTREQ_DQESEL		(FM3_INTREQ_BASE + 0x204)
+#define FM3_INTREQ_ODDPKS1		(FM3_INTREQ_BASE + 0x20F)
+
+#define FM3_GPIO_PFR			(FM3_GPIO_BASE + 0x000)
+#define FM3_GPIO_PFR0			(FM3_GPIO_PFR + 0x00)
+#define FM3_GPIO_PFR1			(FM3_GPIO_PFR + 0x04)
+#define FM3_GPIO_PFR2			(FM3_GPIO_PFR + 0x08)
+#define FM3_GPIO_PFR3			(FM3_GPIO_PFR + 0x0C)
+#define FM3_GPIO_PFR4			(FM3_GPIO_PFR + 0x10)
+#define FM3_GPIO_PFR5			(FM3_GPIO_PFR + 0x14)
+#define FM3_GPIO_PFR6			(FM3_GPIO_PFR + 0x18)
+#define FM3_GPIO_PFR7			(FM3_GPIO_PFR + 0x1C)
+#define FM3_GPIO_PFR8			(FM3_GPIO_PFR + 0x20)
+#define FM3_GPIO_PFR9			(FM3_GPIO_PFR + 0x24)
+#define FM3_GPIO_PFRA			(FM3_GPIO_PFR + 0x28)
+#define FM3_GPIO_PFRB			(FM3_GPIO_PFR + 0x2C)
+#define FM3_GPIO_PFRC			(FM3_GPIO_PFR + 0x30)
+#define FM3_GPIO_PFRD			(FM3_GPIO_PFR + 0x34)
+#define FM3_GPIO_PFRE			(FM3_GPIO_PFR + 0x38)
+#define FM3_GPIO_PFRF			(FM3_GPIO_PFR + 0x3C)
+#define FM3_GPIO_PCR			(FM3_GPIO_BASE + 0x100)
+#define FM3_GPIO_PCR0			(FM3_GPIO_PCR + 0x00)
+#define FM3_GPIO_PCR1			(FM3_GPIO_PCR + 0x04)
+#define FM3_GPIO_PCR2			(FM3_GPIO_PCR + 0x08)
+#define FM3_GPIO_PCR3			(FM3_GPIO_PCR + 0x0C)
+#define FM3_GPIO_PCR4			(FM3_GPIO_PCR + 0x10)
+#define FM3_GPIO_PCR5			(FM3_GPIO_PCR + 0x14)
+#define FM3_GPIO_PCR6			(FM3_GPIO_PCR + 0x18)
+#define FM3_GPIO_PCR7			(FM3_GPIO_PCR + 0x1C)
+#define FM3_GPIO_PCR8			(FM3_GPIO_PCR + 0x20)
+#define FM3_GPIO_PCR9			(FM3_GPIO_PCR + 0x24)
+#define FM3_GPIO_PCRA			(FM3_GPIO_PCR + 0x28)
+#define FM3_GPIO_PCRB			(FM3_GPIO_PCR + 0x2C)
+#define FM3_GPIO_PCRC			(FM3_GPIO_PCR + 0x30)
+#define FM3_GPIO_PCRD			(FM3_GPIO_PCR + 0x34)
+#define FM3_GPIO_PCRE			(FM3_GPIO_PCR + 0x38)
+#define FM3_GPIO_PCRF			(FM3_GPIO_PCR + 0x3C)
+#define FM3_GPIO_DDR			(FM3_GPIO_BASE + 0x200)
+#define FM3_GPIO_DDR0			(FM3_GPIO_DDR + 0x00)
+#define FM3_GPIO_DDR1			(FM3_GPIO_DDR + 0x04)
+#define FM3_GPIO_DDR2			(FM3_GPIO_DDR + 0x08)
+#define FM3_GPIO_DDR3			(FM3_GPIO_DDR + 0x0C)
+#define FM3_GPIO_DDR4			(FM3_GPIO_DDR + 0x10)
+#define FM3_GPIO_DDR5			(FM3_GPIO_DDR + 0x14)
+#define FM3_GPIO_DDR6			(FM3_GPIO_DDR + 0x18)
+#define FM3_GPIO_DDR7			(FM3_GPIO_DDR + 0x1C)
+#define FM3_GPIO_DDR8			(FM3_GPIO_DDR + 0x20)
+#define FM3_GPIO_DDR9			(FM3_GPIO_DDR + 0x24)
+#define FM3_GPIO_DDRA			(FM3_GPIO_DDR + 0x28)
+#define FM3_GPIO_DDRB			(FM3_GPIO_DDR + 0x2C)
+#define FM3_GPIO_DDRC			(FM3_GPIO_DDR + 0x30)
+#define FM3_GPIO_DDRD			(FM3_GPIO_DDR + 0x34)
+#define FM3_GPIO_DDRE			(FM3_GPIO_DDR + 0x38)
+#define FM3_GPIO_DDRF			(FM3_GPIO_DDR + 0x3C)
+#define FM3_GPIO_PDIR			(FM3_GPIO_BASE + 0x300)
+#define FM3_GPIO_PDIR0			(FM3_GPIO_PDIR + 0x00)
+#define FM3_GPIO_PDIR1			(FM3_GPIO_PDIR + 0x04)
+#define FM3_GPIO_PDIR2			(FM3_GPIO_PDIR + 0x08)
+#define FM3_GPIO_PDIR3			(FM3_GPIO_PDIR + 0x0C)
+#define FM3_GPIO_PDIR4			(FM3_GPIO_PDIR + 0x10)
+#define FM3_GPIO_PDIR5			(FM3_GPIO_PDIR + 0x14)
+#define FM3_GPIO_PDIR6			(FM3_GPIO_PDIR + 0x18)
+#define FM3_GPIO_PDIR7			(FM3_GPIO_PDIR + 0x1C)
+#define FM3_GPIO_PDIR8			(FM3_GPIO_PDIR + 0x20)
+#define FM3_GPIO_PDIR9			(FM3_GPIO_PDIR + 0x24)
+#define FM3_GPIO_PDIRA			(FM3_GPIO_PDIR + 0x28)
+#define FM3_GPIO_PDIRB			(FM3_GPIO_PDIR + 0x2C)
+#define FM3_GPIO_PDIRC			(FM3_GPIO_PDIR + 0x30)
+#define FM3_GPIO_PDIRD			(FM3_GPIO_PDIR + 0x34)
+#define FM3_GPIO_PDIRE			(FM3_GPIO_PDIR + 0x38)
+#define FM3_GPIO_PDIRF			(FM3_GPIO_PDIR + 0x3C)
+#define FM3_GPIO_PDOR			(FM3_GPIO_BASE + 0x400)
+#define FM3_GPIO_PDOR0			(FM3_GPIO_PDOR + 0x00)
+#define FM3_GPIO_PDOR1			(FM3_GPIO_PDOR + 0x04)
+#define FM3_GPIO_PDOR2			(FM3_GPIO_PDOR + 0x08)
+#define FM3_GPIO_PDOR3			(FM3_GPIO_PDOR + 0x0C)
+#define FM3_GPIO_PDOR4			(FM3_GPIO_PDOR + 0x10)
+#define FM3_GPIO_PDOR5			(FM3_GPIO_PDOR + 0x14)
+#define FM3_GPIO_PDOR6			(FM3_GPIO_PDOR + 0x18)
+#define FM3_GPIO_PDOR7			(FM3_GPIO_PDOR + 0x1C)
+#define FM3_GPIO_PDOR8			(FM3_GPIO_PDOR + 0x20)
+#define FM3_GPIO_PDOR9			(FM3_GPIO_PDOR + 0x24)
+#define FM3_GPIO_PDORA			(FM3_GPIO_PDOR + 0x28)
+#define FM3_GPIO_PDORB			(FM3_GPIO_PDOR + 0x2C)
+#define FM3_GPIO_PDORC			(FM3_GPIO_PDOR + 0x30)
+#define FM3_GPIO_PDORD			(FM3_GPIO_PDOR + 0x34)
+#define FM3_GPIO_PDORE			(FM3_GPIO_PDOR + 0x38)
+#define FM3_GPIO_PDORF			(FM3_GPIO_PDOR + 0x3C)
+#define FM3_GPIO_ADE			(FM3_GPIO_BASE + 0x500)
+#define FM3_GPIO_EPFR			(FM3_GPIO_BASE + 0x600)
+#define FM3_GPIO_EPFR00			(FM3_GPIO_EPFR + 0x00)
+#define FM3_GPIO_EPFR01			(FM3_GPIO_EPFR + 0x04)
+#define FM3_GPIO_EPFR02			(FM3_GPIO_EPFR + 0x08)
+#define FM3_GPIO_EPFR03			(FM3_GPIO_EPFR + 0x0C)
+#define FM3_GPIO_EPFR04			(FM3_GPIO_EPFR + 0x10)
+#define FM3_GPIO_EPFR05			(FM3_GPIO_EPFR + 0x14)
+#define FM3_GPIO_EPFR06			(FM3_GPIO_EPFR + 0x18)
+#define FM3_GPIO_EPFR07			(FM3_GPIO_EPFR + 0x1C)
+#define FM3_GPIO_EPFR08			(FM3_GPIO_EPFR + 0x20)
+#define FM3_GPIO_EPFR09			(FM3_GPIO_EPFR + 0x24)
+#define FM3_GPIO_EPFR10			(FM3_GPIO_EPFR + 0x28)
+#define FM3_GPIO_EPFR11			(FM3_GPIO_EPFR + 0x2C)
+#define FM3_GPIO_EPFR12			(FM3_GPIO_EPFR + 0x30)
+#define FM3_GPIO_EPFR13			(FM3_GPIO_EPFR + 0x34)
+#define FM3_GPIO_EPFR14			(FM3_GPIO_EPFR + 0x38)
+#define FM3_GPIO_EPFR15			(FM3_GPIO_EPFR + 0x3C)
+#define FM3_GPIO_PZR			(FM3_GPIO_BASE + 0x700)
+#define FM3_GPIO_PZR0			(FM3_GPIO_PZR + 0x00)
+#define FM3_GPIO_PZR1			(FM3_GPIO_PZR + 0x04)
+#define FM3_GPIO_PZR2			(FM3_GPIO_PZR + 0x08)
+#define FM3_GPIO_PZR3			(FM3_GPIO_PZR + 0x0C)
+#define FM3_GPIO_PZR4			(FM3_GPIO_PZR + 0x10)
+#define FM3_GPIO_PZR5			(FM3_GPIO_PZR + 0x14)
+#define FM3_GPIO_PZR6			(FM3_GPIO_PZR + 0x18)
+#define FM3_GPIO_PZR7			(FM3_GPIO_PZR + 0x1C)
+#define FM3_GPIO_PZR8			(FM3_GPIO_PZR + 0x20)
+#define FM3_GPIO_PZR9			(FM3_GPIO_PZR + 0x24)
+#define FM3_GPIO_PZRA			(FM3_GPIO_PZR + 0x28)
+#define FM3_GPIO_PZRB			(FM3_GPIO_PZR + 0x2C)
+#define FM3_GPIO_PZRC			(FM3_GPIO_PZR + 0x30)
+#define FM3_GPIO_PZRD			(FM3_GPIO_PZR + 0x34)
+#define FM3_GPIO_PZRE			(FM3_GPIO_PZR + 0x38)
+#define FM3_GPIO_PZRF			(FM3_GPIO_PZR + 0x3C)
+
+/*
+ *  FM3_MFSx Register Bit Definition
+ */
+#define SMR_SOE					0x01U
+#define SMR_BDS					0x04U
+#define SMR_SBL					0x08U
+#define SMR_WUCR				0x10U
+#define SMR_MD_UART				0x00U
+#define SMR_MD_UART_MP			0x20U
+#define SMR_MD_SIO				0x40U
+#define SMR_MD_LIN				0x60U
+#define SMR_MD_I2C				0x80U
+
+#define SCR_TXE					0x01U
+#define SCR_RXE					0x02U
+#define SCR_TBIE				0x04U
+#define SCR_TIE					0x08U
+#define SCR_RIE					0x10U
+#define SCR_UPCL				0x80U
+
+#define SSR_TBI					0x01U
+#define SSR_TDRE				0x02U
+#define SSR_RDRF				0x04U
+#define SSR_ORE					0x08U
+#define SSR_FRE					0x10U
+#define SSR_PE					0x20U
+#define SSR_REC					0x80U
+
+#define ESCR_P					0x08U
+#define ESCR_PEN				0x10U
+#define ESCR_INV				0x20U
+#define ESCR_ESBL				0x40U
+#define ESCR_FLWEN				0x80U
+#define ESCR_DATABITS_8			0x00U
+#define ESCR_DATABITS_5			0x01U
+#define ESCR_DATABITS_6			0x02U
+#define ESCR_DATABITS_7			0x03U
+#define ESCR_DATABITS_9			0x04U
+
+#define BGR_EXT					0x8000U
+
+#define FM3_EXBUS_MODE			(FM3_EXTBUS_BASE + 0x000)
+#define FM3_EXBUS_MODE0			(FM3_EXBUS_MODE + 0x00)
+#define FM3_EXBUS_MODE1			(FM3_EXBUS_MODE + 0x04)
+#define FM3_EXBUS_MODE2			(FM3_EXBUS_MODE + 0x08)
+#define FM3_EXBUS_MODE3			(FM3_EXBUS_MODE + 0x0C)
+#define FM3_EXBUS_MODE4			(FM3_EXBUS_MODE + 0x10)
+#define FM3_EXBUS_MODE5			(FM3_EXBUS_MODE + 0x14)
+#define FM3_EXBUS_MODE6			(FM3_EXBUS_MODE + 0x18)
+#define FM3_EXBUS_MODE7			(FM3_EXBUS_MODE + 0x1C)
+#define FM3_EXBUS_TIM			(FM3_EXTBUS_BASE + 0x020)
+#define FM3_EXBUS_TIM0			(FM3_EXBUS_TIM + 0x00)
+#define FM3_EXBUS_TIM1			(FM3_EXBUS_TIM + 0x04)
+#define FM3_EXBUS_TIM2			(FM3_EXBUS_TIM + 0x08)
+#define FM3_EXBUS_TIM3			(FM3_EXBUS_TIM + 0x0C)
+#define FM3_EXBUS_TIM4			(FM3_EXBUS_TIM + 0x10)
+#define FM3_EXBUS_TIM5			(FM3_EXBUS_TIM + 0x14)
+#define FM3_EXBUS_TIM6			(FM3_EXBUS_TIM + 0x18)
+#define FM3_EXBUS_TIM7			(FM3_EXBUS_TIM + 0x1C)
+#define FM3_EXBUS_AREA			(FM3_EXTBUS_BASE + 0x040)
+#define FM3_EXBUS_AREA0			(FM3_EXBUS_AREA + 0x00)
+#define FM3_EXBUS_AREA1			(FM3_EXBUS_AREA + 0x04)
+#define FM3_EXBUS_AREA2			(FM3_EXBUS_AREA + 0x08)
+#define FM3_EXBUS_AREA3			(FM3_EXBUS_AREA + 0x0C)
+#define FM3_EXBUS_AREA4			(FM3_EXBUS_AREA + 0x10)
+#define FM3_EXBUS_AREA5			(FM3_EXBUS_AREA + 0x14)
+#define FM3_EXBUS_AREA6			(FM3_EXBUS_AREA + 0x18)
+#define FM3_EXBUS_AREA7			(FM3_EXBUS_AREA + 0x1C)
+#define FM3_EXBUS_ATIM			(FM3_EXTBUS_BASE + 0x060)
+#define FM3_EXBUS_ATIM0			(FM3_EXBUS_ATIM + 0x00)
+#define FM3_EXBUS_ATIM1			(FM3_EXBUS_ATIM + 0x04)
+#define FM3_EXBUS_ATIM2			(FM3_EXBUS_ATIM + 0x08)
+#define FM3_EXBUS_ATIM3			(FM3_EXBUS_ATIM + 0x0C)
+#define FM3_EXBUS_ATIM4			(FM3_EXBUS_ATIM + 0x10)
+#define FM3_EXBUS_ATIM5			(FM3_EXBUS_ATIM + 0x14)
+#define FM3_EXBUS_ATIM6			(FM3_EXBUS_ATIM + 0x18)
+#define FM3_EXBUS_ATIM7			(FM3_EXBUS_ATIM + 0x1C)
+#define FM3_EXBUS_DCLKR			(FM3_EXTBUS_BASE + 0x300)
+
+#define FM3_DMAC_DMACR			(FM3_DMAC_BASE + 0x000)
+#define FM3_DMAC0_BASE			(FM3_DMAC_BASE + 0x010)
+#define FM3_DMAC_DMACA0			(FM3_DMAC0_BASE + 0x00)
+#define FM3_DMAC_DMACB0			(FM3_DMAC0_BASE + 0x04)
+#define FM3_DMAC_DMACSA0		(FM3_DMAC0_BASE + 0x08)
+#define FM3_DMAC_DMACDA0		(FM3_DMAC0_BASE + 0x0C)
+#define FM3_DMAC1_BASE			(FM3_DMAC_BASE + 0x020)
+#define FM3_DMAC_DMACA1			(FM3_DMAC1_BASE + 0x00)
+#define FM3_DMAC_DMACB1			(FM3_DMAC1_BASE + 0x04)
+#define FM3_DMAC_DMACSA1		(FM3_DMAC1_BASE + 0x08)
+#define FM3_DMAC_DMACDA1		(FM3_DMAC1_BASE + 0x0C)
+#define FM3_DMAC2_BASE			(FM3_DMAC_BASE + 0x030)
+#define FM3_DMAC_DMACA2			(FM3_DMAC2_BASE + 0x00)
+#define FM3_DMAC_DMACB2			(FM3_DMAC2_BASE + 0x04)
+#define FM3_DMAC_DMACSA2		(FM3_DMAC2_BASE + 0x08)
+#define FM3_DMAC_DMACDA2		(FM3_DMAC2_BASE + 0x0C)
+#define FM3_DMAC3_BASE			(FM3_DMAC_BASE + 0x040)
+#define FM3_DMAC_DMACA3			(FM3_DMAC3_BASE + 0x00)
+#define FM3_DMAC_DMACB3			(FM3_DMAC3_BASE + 0x04)
+#define FM3_DMAC_DMACSA3		(FM3_DMAC3_BASE + 0x08)
+#define FM3_DMAC_DMACDA3		(FM3_DMAC3_BASE + 0x0C)
+#define FM3_DMAC4_BASE			(FM3_DMAC_BASE + 0x050)
+#define FM3_DMAC_DMACA4			(FM3_DMAC4_BASE + 0x00)
+#define FM3_DMAC_DMACB4			(FM3_DMAC4_BASE + 0x04)
+#define FM3_DMAC_DMACSA4		(FM3_DMAC4_BASE + 0x08)
+#define FM3_DMAC_DMACDA4		(FM3_DMAC4_BASE + 0x0C)
+#define FM3_DMAC5_BASE			(FM3_DMAC_BASE + 0x060)
+#define FM3_DMAC_DMACA5			(FM3_DMAC5_BASE + 0x00)
+#define FM3_DMAC_DMACB5			(FM3_DMAC5_BASE + 0x04)
+#define FM3_DMAC_DMACSA5		(FM3_DMAC5_BASE + 0x08)
+#define FM3_DMAC_DMACDA5		(FM3_DMAC5_BASE + 0x0C)
+#define FM3_DMAC6_BASE			(FM3_DMAC_BASE + 0x070)
+#define FM3_DMAC_DMACA6			(FM3_DMAC6_BASE + 0x00)
+#define FM3_DMAC_DMACB6			(FM3_DMAC6_BASE + 0x04)
+#define FM3_DMAC_DMACSA6		(FM3_DMAC6_BASE + 0x08)
+#define FM3_DMAC_DMACDA6		(FM3_DMAC6_BASE + 0x0C)
+#define FM3_DMAC7_BASE			(FM3_DMAC_BASE + 0x080)
+#define FM3_DMAC_DMACA7			(FM3_DMAC7_BASE + 0x00)
+#define FM3_DMAC_DMACB7			(FM3_DMAC7_BASE + 0x04)
+#define FM3_DMAC_DMACSA7		(FM3_DMAC7_BASE + 0x08)
+#define FM3_DMAC_DMACDA7		(FM3_DMAC7_BASE + 0x0C)
+
+#ifndef TOPPERS_MACRO_ONLY
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+#endif /* TOPPERS_FM3_MB9BXXX_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target.tf
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target.tf	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target.tf	(revision 131)
@@ -0,0 +1,8 @@
+$ 
+$     pX2Ì^[QbgË¶ev[g
+$ 
+
+$ 
+$  RAË¶ev[gÌCN[h
+$ 
+$INCLUDE"arm_m_gcc/common/core.tf"$
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_asm.inc
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_asm.inc	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_asm.inc	(revision 131)
@@ -0,0 +1,1 @@
+#include "arm_m_gcc/common/core_asm.inc"
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_cfg1_out.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_cfg1_out.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_cfg1_out.h	(revision 131)
@@ -0,0 +1,10 @@
+/*
+ *		cfg1_out.cðN·é½ßÉKvÈX^uÌè`
+ */
+
+STK_T *const	_kernel_istkpt = 0x00;
+
+/*
+ *  RAË¶ÌX^uÌè` 
+ */
+#include <core_cfg1_out.h>
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_check.tf
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_check.tf	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_check.tf	(revision 131)
@@ -0,0 +1,8 @@
+$ 
+$     pX3Ì^[QbgË¶ev[g
+$ 
+
+$ 
+$  pX3ÌRAË¶Ìev[gÌCN[h
+$ 
+$INCLUDE"arm_m_gcc/common/core_check.tf"$
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_config.c
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_config.c	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_config.c	(revision 131)
@@ -0,0 +1,148 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ * ^[QbgË¶W
+[
+ */
+#include "kernel_impl.h"
+#include <sil.h>
+
+#include "fm3_mb9bxxx.h"
+#include "target_serial.h"
+
+/*
+ *  ^[QbgË¶Ìú»
+ */
+void
+target_initialize(void){
+
+	static uint32_t u32IoRegisterRead;
+
+	/*
+	 *  n[hEFAEEIb`hOE^C}Ìâ~
+	 */
+	sil_wrw_mem((uint32_t*)FM3_HWWDT_WDG_LCK, 0x1ACCE551);
+	sil_wrw_mem((uint32_t*)FM3_HWWDT_WDG_LCK, 0xE5331AAE);
+	sil_wrb_mem((uint8_t*)FM3_HWWDT_WDG_CTL, 0);
+
+	/*
+	 *  NbNÌÝè
+	 */
+	sil_wrb_mem((uint8_t*)FM3_CRG_BSC_PSR, 0);
+	sil_wrb_mem((uint8_t*)FM3_CRG_APBC0_PSR, 0);
+	sil_wrb_mem((uint8_t*)FM3_CRG_APBC1_PSR, APBC1_PSR_APBC1EN | 1);
+	sil_wrb_mem((uint8_t*)FM3_CRG_APBC2_PSR, APBC2_PSR_APBC2EN | 1);
+	sil_wrb_mem((uint8_t*)FM3_CRG_SWC_PSR, SWC_PSR_TESTB | 3);
+	sil_wrb_mem((uint8_t*)FM3_CRG_TTC_PSR, 0);
+
+	sil_wrb_mem((uint8_t*)FM3_CRG_CSW_TMR, (5 << 4) | 0x0C);
+
+	sil_wrb_mem((uint8_t*)FM3_CRG_SCM_CTL, sil_reb_mem((uint8_t*)FM3_CRG_SCM_CTL) | SCM_CTL_MOSCE);
+	while (!(sil_reb_mem((uint8_t*)FM3_CRG_SCM_STR) & SCM_CTL_MOSCE));
+
+	sil_wrb_mem((uint8_t*)FM3_CRG_PSW_TMR, 0);
+	sil_wrb_mem((uint8_t*)FM3_CRG_PLL_CTL1, ((1-1)<<4) | ((2-1)<<0));
+	sil_wrb_mem((uint8_t*)FM3_CRG_PLL_CTL2, 36-1);
+
+	sil_wrb_mem((uint8_t*)FM3_CRG_SCM_CTL, sil_reb_mem((uint8_t*)FM3_CRG_SCM_CTL) | SCM_CTL_PLLE);
+	while (!(sil_reb_mem((uint8_t*)FM3_CRG_SCM_STR) & SCM_CTL_PLLE));
+
+	sil_wrb_mem((uint8_t*)FM3_CRG_SCM_CTL, sil_reb_mem((uint8_t*)FM3_CRG_SCM_CTL) | (2 << 5));
+
+	do
+	{
+		u32IoRegisterRead = (sil_reb_mem((uint8_t*)FM3_CRG_SCM_CTL) & 0xE0); 
+	}while ((sil_reb_mem((uint8_t*)FM3_CRG_SCM_STR) & 0xE0) != u32IoRegisterRead);
+
+	/*
+	 *  ¬CRg~OÌÝè
+	 */
+	if( 0x000003FF != (sil_rew_mem((uint32_t*)FM3_FLASH_IF_CRTRMM) & 0x000003FF) )
+	{
+		sil_wrw_mem((uint32_t*)FM3_CRTRIM_MCR_RLR, 0x1ACCE554);
+		sil_wrw_mem((uint32_t*)FM3_CRTRIM_MCR_FTRM, sil_rew_mem((uint32_t*)FM3_FLASH_IF_CRTRMM));
+		sil_wrw_mem((uint32_t*)FM3_CRTRIM_MCR_RLR, 0x00000000);
+	}
+
+	/*
+	 * RAË¶Ìú»
+	 */
+	core_initialize();
+
+	/*
+	 *  oi[oÍpÌVAú»
+	 */
+	target_uart_init(SIO_PORTID);
+} 
+
+
+/*
+ *  ^[QbgË¶ÌI¹
+ */
+void
+target_exit(void)
+{
+	/*
+	 *  RAË¶ÌI¹
+	 */
+	core_terminate();
+
+	/*
+	 *  J­Â«Ë¶ÌI¹
+	 */
+	while(1);
+}
+
+
+/*
+ *  VXeOÌáxoÍÌ½ßÌ¶oÍ
+ */
+void
+target_fput_log(char c)
+{
+	if (c == '\n') {
+		sio_pol_snd_chr('\r', SIO_PORTID);
+	}
+	sio_pol_snd_chr(c, SIO_PORTID);
+}
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_config.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_config.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_config.h	(revision 131)
@@ -0,0 +1,113 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *  `bvË¶W
+[
+ *
+ *  J[lÌ^[QbgË¶ÌCN[ht@CDkernel_impl.hÌ^[
+ *  QbgË¶ÌÊut¯ÆÈéD
+ */
+
+#ifndef TOPPERS_TARGET_CONFIG_H
+#define TOPPERS_TARGET_CONFIG_H
+
+/*
+ *  ^[QbgË¶Ìn[hEFA¹Ìè`
+ */
+#include "fm3_mb9bxxx.h"
+
+/*
+ *  g[XOÉÖ·éÝè
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  RAMÀs·éêâQEMUÀsROMfobOÍMSPðú»·é
+ *  Kvª é½ß,X^[gAbv[`ÅMSPðú»·éD 
+ */
+#define INIT_MSP
+
+/*
+ *  ftHgÌñ^XNReLXgpÌX^bNÌæÌè`
+ */
+#define DEFAULT_ISTKSZ      (0x1000U)   /* 4KByte */
+
+/*
+ *  ÷­ÔÒ¿Ì½ßÌè`i{ÍSILÌ^[QbgË¶j
+ */
+#define SIL_DLY_TIM1    90
+#define SIL_DLY_TIM2    56
+
+/*
+ *  gp·éVA|[gID
+ */
+#ifndef SIO_PORTID
+#define SIO_PORTID		(1)
+#endif /* SIO_PORTID */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ^[QbgVXeË¶Ìú»
+ */
+extern void	target_initialize(void);
+
+/*
+ *  ^[QbgVXeÌI¹
+ *
+ *  VXeðI¹·éÉg¤D
+ */
+extern void	target_exit(void) NoReturn;
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  RAË¶W
+[iARM-Mpj
+ */
+#include "core_config.h"
+
+#endif /* TOPPERS_TARGET_CONFIG_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_kernel.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_kernel.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_kernel.h	(revision 131)
@@ -0,0 +1,80 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *  kernel.hÌ`bvË¶
+ *
+ *  ±ÌCN[ht@CÍCkernel.hÅCN[h³êéD¼Ìt@
+ *  C©ç¼ÚCN[h·é±ÆÍÈ¢D±Ìt@CðCN[h
+ *  ·éOÉCt_stddef.hªCN[h³êéÌÅC»êçÉË¶µÄàæ
+ *  ¢D
+ */
+
+#ifndef TOPPERS_TARGET_KERNEL_H
+#define TOPPERS_TARGET_KERNEL_H
+
+/*
+ *  J[lÇÌÝDæxÌÍÍ
+ *
+ *  TMIN_INTPRIÌè`ðÏX·é±ÆÅC±Ìxæèà¢ÝDæx
+ *  ðÂàÌðJ[lÇOÌÝÆ·é©ðÏXÅ«éD
+ */
+#define TMIN_INTPRI		(-15)		/* ÝDæxÌÅ¬liÅlj*/
+
+/*
+ *  T|[g·é@\Ìè`
+ */
+#define TOPPERS_TARGET_SUPPORT_GET_UTM	/* get_utmðT|[g·é */
+
+/*
+ *  ^CeBbNÌè`
+ */
+#define TIC_NUME   1U            /* ^CeBbNÌüúÌªq */
+#define TIC_DENO   1U            /* ^CeBbNÌüúÌªê */
+
+/*
+ *  RAË¶Å¤ÊÈè`
+ */
+#include "arm_m_gcc/common/core_kernel.h"
+
+#endif /* TOPPERS_TARGET_KERNEL_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_offset.tf
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_offset.tf	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_offset.tf	(revision 131)
@@ -0,0 +1,13 @@
+$
+$       ItZbgt@C¶¬pev[gt@C
+$
+
+$
+$  Wev[gt@CÌCN[h
+$
+$INCLUDE "kernel/genoffset.tf"$
+
+$ 
+$  RAË¶ev[gÌCN[hiARM-Mpj
+$ 
+$INCLUDE"../../arch/arm_m_gcc/common/core_offset.tf"$
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_rename.def
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_rename.def	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_rename.def	(revision 131)
@@ -0,0 +1,5 @@
+INCLUDE "arm_m_gcc/common/core"
+
+#target_config.c
+target_initialize
+target_exit
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_rename.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_rename.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_rename.h	(revision 131)
@@ -0,0 +1,26 @@
+/* This file is generated from target_rename.def by genrename. */
+
+#ifndef TOPPERS_TARGET_RENAME_H
+#define TOPPERS_TARGET_RENAME_H
+
+
+/*
+ * target_config.c
+ */
+#define target_initialize			_kernel_target_initialize
+#define target_exit					_kernel_target_exit
+
+#ifdef TOPPERS_LABEL_ASM
+
+
+/*
+ * target_config.c
+ */
+#define _target_initialize			__kernel_target_initialize
+#define _target_exit				__kernel_target_exit
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "arm_m_gcc/common/core_rename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.c	(revision 131)
@@ -0,0 +1,378 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *  VAI/OfoCXiSIOjhCo
+ */
+
+#include <kernel.h>
+#include <t_syslog.h>
+#include "target_serial.h"
+#include "target_syssvc.h"
+
+/*
+ * WX^Ýèl
+ */
+#define PORT2SIOPID(x)	((x) + 1)
+#define INDEX_PORT(x)	((x) - 1)
+#define GET_SIOPCB(x)	(&siopcb_table[INDEX_PORT(x)])
+
+/*
+ * UARTWX^è`
+ */
+#define UART_SMR(x)		(x + 0x00)
+#define UART_SCR(x)		(x + 0x01)
+#define UART_ESCR(x)	(x + 0x04)
+#define UART_SSR(x)		(x + 0x05)
+#define UART_RDR(x)		(x + 0x08)
+#define UART_TDR(x)		(x + 0x08)
+#define UART_BGR(x)		(x + 0x0c)
+#define UART_BGR0(x)	(x + 0x0c)
+#define UART_BGR1(x)	(x + 0x0d)
+#define UART_ISBA(x)	(x + 0x10)
+#define UART_ISMK(x)	(x + 0x11)
+#define UART_FCR0(x)	(x + 0x14)
+#define UART_FCR1(x)	(x + 0x15)
+#define UART_FBYTE1(x)	(x + 0x18)
+#define UART_FBYTE2(x)	(x + 0x19)
+
+/*
+ *  VAI/O|[gú»ubNÌè`
+ */
+typedef struct sio_port_initialization_block {
+	uint32_t base;
+	INTNO    intno_rx;
+	INTNO    intno_tx;
+} SIOPINIB;
+
+/*
+ *  pGPIO|[gú»ubNÌè`
+ */
+typedef struct gpio_port_initialization_block {
+	uint32_t pfr;		/* PFRxWX^AhX */
+	uint32_t pfr_set;	/* PFRxWX^ðZbg·érbg */
+	uint32_t pcr;		/* PCRxWX^AhX */
+	uint32_t pcr_set;	/* PCRxWX^ðZbg·érbg */
+	uint32_t epfr;		/* EPFRxxWX^AhX */
+	uint32_t epfr_clr;	/* EPFRxxWX^ðNA·érbg */
+	uint32_t epfr_set;	/* EPFRxxWX^ðZbg·érbg */
+	uint32_t ade;		/* ADEWX^AhX */
+	uint32_t ade_clr;	/* ADEWX^ðNA·érbg */
+} GPIOINIB;
+
+/*
+ *  VAI/O|[gÇubNÌè`
+ */
+struct sio_port_control_block {
+	const SIOPINIB  *p_siopinib;  /* VAI/O|[gú»ubN */
+	const GPIOINIB  *p_gpioinib;  /* pGPIO|[gú»ubN */
+	intptr_t        exinf;        /* g£îñ */
+	bool_t          opnflg;       /* I[vÏÝtO */
+};
+
+/*
+ * VAI/O|[gú»ubN
+ */
+const SIOPINIB siopinib_table[TNUM_SIOP] = {
+	{(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX},
+	{(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX},
+	{(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX},
+};
+
+/*
+ * pGPIO|[gú»ubN
+ */
+const GPIOINIB gpioinib_table[TNUM_SIOP] = {
+	{(uint32_t)FM3_GPIO_PFR2, (uint32_t)((1 << 1) | (1 << 2)), (uint32_t)FM3_GPIO_PCR2, (uint32_t)(1<<1), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x000000f0, (uint32_t)0x00000050, (uint32_t)FM3_GPIO_ADE, (uint32_t)(1 << 31)},
+	{(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
+	{(uint32_t)FM3_GPIO_PFR4, (uint32_t)((1 << 8) | (1 << 9)), (uint32_t)FM3_GPIO_PCR4, (uint32_t)(1<<8), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x03c00000, (uint32_t)0x03c00000, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
+};
+
+/*
+ *  VAI/O|[gÇubNÌGA
+ */
+SIOPCB	siopcb_table[TNUM_SIOP];
+
+/*
+ *  VAI/O|[gID©çÇubNðæèo·½ßÌ}N
+ */
+#define INDEX_SIOP(siopid)	((uint_t)((siopid) - 1))
+#define get_siopcb(siopid)	(&(siopcb_table[INDEX_SIOP(siopid)]))
+
+/*
+ *  SIOhCoÌú»
+ */
+void
+sio_initialize(intptr_t exinf)
+{
+	SIOPCB	*p_siopcb;
+	uint_t	i;
+
+	/*
+	 *  VAI/O|[gÇubNÌú»
+	 */
+	for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
+		p_siopcb->p_siopinib = &(siopinib_table[i]);
+		p_siopcb->p_gpioinib = &(gpioinib_table[i]);
+		p_siopcb->opnflg = false;
+	}
+}
+
+
+/*
+ *  VAI/O|[gÌI[v
+ */
+SIOPCB *
+sio_opn_por(ID siopid, intptr_t exinf)
+{
+	SIOPCB          *p_siopcb;
+	const SIOPINIB  *p_siopinib;
+	const GPIOINIB  *p_gpioinib;
+	bool_t  opnflg;
+	ER      ercd;
+
+	p_siopcb = get_siopcb(siopid);
+	p_siopinib = p_siopcb->p_siopinib;
+	p_gpioinib = p_siopcb->p_gpioinib;
+
+	/*
+	 *  I[vµ½|[gª é©ðopnflgÉÇñÅ¨­D
+	 */
+	opnflg = p_siopcb->opnflg;
+
+	p_siopcb->exinf = exinf;
+
+	/*
+	 *  n[hEFAÌú»
+	 */
+	sil_wrw_mem((uint32_t *)p_gpioinib->pfr, sil_rew_mem((uint32_t *)p_gpioinib->pfr) | p_gpioinib->pfr_set);
+	sil_wrw_mem((uint32_t *)p_gpioinib->pcr, sil_rew_mem((uint32_t *)p_gpioinib->pcr) | p_gpioinib->pcr_set);
+	sil_wrw_mem((uint32_t *)p_gpioinib->epfr, (sil_rew_mem((uint32_t *)p_gpioinib->epfr) & p_gpioinib->epfr_clr) | p_gpioinib->epfr_set);
+	sil_wrw_mem((uint32_t *)p_gpioinib->ade, sil_rew_mem((uint32_t *)p_gpioinib->ade) & ~p_gpioinib->ade_clr);
+
+	uint32_t base = p_siopinib->base;
+
+	sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
+	sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
+	sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
+	sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
+	sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_RXE | SCR_TXE);
+
+	/*
+	 *  VAI/OÝÌ}XNðð·éD
+	 */
+	if (!opnflg) {
+		ercd = ena_int(p_siopinib->intno_rx);
+		assert(ercd == E_OK);
+		ercd = ena_int(p_siopinib->intno_tx);
+		assert(ercd == E_OK);
+	}
+
+	return(p_siopcb);
+}
+
+/*
+ *  VAI/O|[gÌN[Y
+ */
+void
+sio_cls_por(SIOPCB *p_siopcb)
+{
+	/*
+	 *  VAI/OÝð}XN·éD
+	 */
+	if (!(p_siopcb->opnflg)) {
+		dis_int(p_siopcb->p_siopinib->intno_rx);
+		dis_int(p_siopcb->p_siopinib->intno_tx);
+	}
+}
+
+/*
+ *  SIOÌÝT[rX[`
+ */
+
+Inline bool_t
+sio_putready(SIOPCB* p_siopcb)
+{
+	return (sil_reb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base)) & SSR_TDRE) != 0;
+}
+
+Inline bool_t
+sio_getready(SIOPCB* p_siopcb)
+{
+	char ssr = sil_reb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base));
+
+	if ((ssr & (SSR_ORE | SSR_FRE | SSR_PE)) != 0)
+	{
+		sil_wrb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base), ssr | SSR_REC);
+		return 0;
+	}
+	if ((ssr & SSR_RDRF) != 0)
+	{
+		return 1;
+	}
+	return 0;
+}
+
+void
+sio_tx_isr(intptr_t exinf)
+{
+	SIOPCB          *p_siopcb;
+
+	p_siopcb = get_siopcb(exinf);
+
+	if (sio_putready(p_siopcb)) {
+		sio_irdy_snd(p_siopcb->exinf);
+	}
+}
+
+void
+sio_rx_isr(intptr_t exinf)
+{
+	SIOPCB          *p_siopcb;
+
+	p_siopcb = get_siopcb(exinf);
+
+	if (sio_getready(p_siopcb)) {
+		sio_irdy_rcv(p_siopcb->exinf);
+	}
+}
+
+/*
+ *  VAI/O|[gÖÌ¶M
+ */
+bool_t
+sio_snd_chr(SIOPCB *p_siopcb, char c)
+{
+	if (sio_putready(p_siopcb)) {
+		sil_wrh_mem((uint16_t *)UART_TDR(p_siopcb->p_siopinib->base), (uint16_t)c);
+
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ *  VAI/O|[g©çÌ¶óM
+ */
+int_t
+sio_rcv_chr(SIOPCB *p_siopcb)
+{
+	int_t c = -1;
+
+	if (sio_getready(p_siopcb)) {
+		c = sil_reh_mem((uint16_t *)UART_RDR(p_siopcb->p_siopinib->base)) & 0xFF;
+	}
+
+	return c;
+}
+
+/*
+ *  VAI/O|[g©çÌR[obNÌÂ
+ */
+void
+sio_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+	  case SIO_RDY_SND:
+		sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) | SCR_TIE);
+		break;
+	  case SIO_RDY_RCV:
+		sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) | SCR_RIE);
+		break;
+	}
+}
+
+/*
+ *  VAI/O|[g©çÌR[obNÌÖ~
+ */
+void
+sio_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+	  case SIO_RDY_SND:
+		sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) & ~SCR_TIE);
+		break;
+	  case SIO_RDY_RCV:
+		sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) & ~SCR_RIE);
+		break;
+	}
+}
+
+/*
+ *  1¶oÍi|[OÅÌoÍj
+ */
+void sio_pol_snd_chr(char c, ID siopid)
+{
+	uint32_t base = siopinib_table[INDEX_PORT(siopid)].base;
+
+	sil_wrh_mem((uint16_t *)UART_TDR(base), (uint16_t)c);
+	while(0 == (sil_reb_mem((uint8_t *)UART_SSR(base)) & (1 << 1)));
+
+	/*
+	 *  oÍª®SÉIíéÜÅÒÂ
+	 */
+	volatile int n = 300000000/BPS_SETTING;
+	while(n--);
+}
+
+/*
+ *  ^[QbgÌVAú»
+ */
+void target_uart_init(ID siopid)
+{
+	const GPIOINIB  *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)];
+
+	sil_wrw_mem((uint32_t *)p_gpioinib->pfr, sil_rew_mem((uint32_t *)p_gpioinib->pfr) | p_gpioinib->pfr_set);
+	sil_wrw_mem((uint32_t *)p_gpioinib->pcr, sil_rew_mem((uint32_t *)p_gpioinib->pcr) | p_gpioinib->pcr_set);
+	sil_wrw_mem((uint32_t *)p_gpioinib->epfr, (sil_rew_mem((uint32_t *)p_gpioinib->epfr) & p_gpioinib->epfr_clr) | p_gpioinib->epfr_set);
+	sil_wrw_mem((uint32_t *)p_gpioinib->ade, sil_rew_mem((uint32_t *)p_gpioinib->ade) & ~p_gpioinib->ade_clr);
+
+	uint32_t base = siopinib_table[INDEX_PORT(siopid)].base;
+
+	sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
+	sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
+	sil_wrh_mem((uint16_t *)UART_BGR(base), (uint16_t)(((SysFrePCLK2 + ((uint32_t)BPS_SETTING / 2)) / (uint32_t)BPS_SETTING) - 1));
+	sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
+	sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_TXE);
+}
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.cfg
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.cfg	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.cfg	(revision 131)
@@ -0,0 +1,11 @@
+/*
+ *  SIOhCoÌRtBM
+[Vt@C
+ */
+
+#include "target_serial.h"
+ATT_INI({ TA_NULL, 0, sio_initialize });
+ATT_ISR({ TA_NULL, SIO_PORTID, INTNO_SIO_RX, sio_rx_isr, 1 });
+ATT_ISR({ TA_NULL, SIO_PORTID, INTNO_SIO_TX, sio_tx_isr, 1 });
+CFG_INT(INTNO_SIO_RX, { TA_ENAINT|INTATR_SIO, INTPRI_SIO });
+CFG_INT(INTNO_SIO_TX, { TA_ENAINT|INTATR_SIO, INTPRI_SIO });
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_serial.h	(revision 131)
@@ -0,0 +1,154 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *    VAI/OfoCXiSIOjhCo
+ */
+
+#ifndef TOPPERS_TARGET_SERIAL_H
+#define TOPPERS_TARGET_SERIAL_H
+
+/*
+ *  SIOÌÝnhÌxN^Ô
+ */
+#if (SIO_PORTID == 1)
+#define INHNO_SIO_RX	IRQ_VECTOR_MFS0RX
+#define INHNO_SIO_TX	IRQ_VECTOR_MFS0TX
+#define INTNO_SIO_RX	IRQ_VECTOR_MFS0RX
+#define INTNO_SIO_TX	IRQ_VECTOR_MFS0TX
+#elif (SIO_PORTID == 2)
+#define INHNO_SIO_RX	IRQ_VECTOR_MFS4RX
+#define INHNO_SIO_TX	IRQ_VECTOR_MFS4TX
+#define INTNO_SIO_RX	IRQ_VECTOR_MFS4RX
+#define INTNO_SIO_TX	IRQ_VECTOR_MFS4TX
+#elif (SIO_PORTID == 3)
+#define INHNO_SIO_RX	IRQ_VECTOR_MFS3RX
+#define INHNO_SIO_TX	IRQ_VECTOR_MFS3TX
+#define INTNO_SIO_RX	IRQ_VECTOR_MFS3RX
+#define INTNO_SIO_TX	IRQ_VECTOR_MFS3TX
+#endif
+
+#define INTPRI_SIO       -3        /* ÝDæx */
+#define INTATR_SIO       0         /* Ý®« */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  VAI/O|[gÇubNÌè`
+ */
+typedef struct sio_port_control_block    SIOPCB;
+
+/*
+ *  R[obN[`Ì¯ÊÔ
+ */
+#define SIO_RDY_SND    1U        /* MÂ\R[obN */
+#define SIO_RDY_RCV    2U        /* óMÊmR[obN */
+
+/*
+ *  VAI/O|[gÌè`
+ */
+#define TNUM_SIOP       3       /* T|[g·éVAI/O|[gÌ */
+
+/*
+ *  SIOhCoÌú»
+ */
+extern void sio_initialize(intptr_t exinf);
+
+/*
+ *  VAI/O|[gÌI[v
+ */
+extern SIOPCB *sio_opn_por(ID siopid, intptr_t exinf);
+
+/*
+ *  VAI/O|[gÌN[Y
+ */
+extern void sio_cls_por(SIOPCB *p_siopcb);
+
+/*
+ *  SIOÌÝT[rX[`
+ */
+extern void sio_rx_isr(intptr_t exinf);
+extern void sio_tx_isr(intptr_t exinf);
+
+/*
+ *  VAI/O|[gÖÌ¶M
+ */
+extern bool_t sio_snd_chr(SIOPCB *p_siopcb, char c);
+
+/*
+ *  VAI/O|[g©çÌ¶óM
+ */
+extern int_t sio_rcv_chr(SIOPCB *p_siopcb);
+
+/*
+ *  VAI/O|[g©çÌR[obNÌÂ
+ */
+extern void sio_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn);
+
+/*
+ *  VAI/O|[g©çÌR[obNÌÖ~
+ */
+extern void sio_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn);
+
+/*
+ *  VAI/O|[g©çÌMÂ\R[obN
+ */
+extern void sio_irdy_snd(intptr_t exinf);
+
+/*
+ *  VAI/O|[g©çÌóMÊmR[obN
+ */
+extern void sio_irdy_rcv(intptr_t exinf);
+
+/*
+ *  1¶Mi|[OÅÌoÍj
+ */
+extern void sio_pol_snd_chr(char c, ID siopid);
+
+/*
+ *  ^[QbgÌVAú»
+ */
+extern void target_uart_init(ID siopid);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_SERIAL_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_sil.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_sil.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_sil.h	(revision 131)
@@ -0,0 +1,65 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *   sil.hÌ`bvË¶
+ *
+ *  ±ÌCN[ht@CÍCsil.hÌæªÅCN[h³êéD¼Ìt@
+ *  C©çÍ¼ÚCN[h·é±ÆÍÈ¢D±Ìt@CðCN[
+ *  h·éOÉCt_stddef.hªCN[h³êéÌÅC»êçÉË¶µÄà
+ *  æ¢D
+ */
+
+#ifndef TOPPERS_TARGET_SIL_H
+#define TOPPERS_TARGET_SIL_H
+
+/*
+ *  vZbTÌGfBA
+ */
+#define SIL_ENDIAN_LITTLE
+
+/*
+ *  RAË¶Å¤ÊÈè`
+ */
+#include "core_sil.h"
+
+#endif /* TOPPERS_TARGET_SIL_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_stddef.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_stddef.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_stddef.h	(revision 131)
@@ -0,0 +1,88 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *  t_stddef.hÌ^[QbgË¶
+ *
+ *  ±ÌCN[ht@CÍCt_stddef.hÌæªÅCN[h³êéD
+ *  ¼Ìt@C©çÍ¼ÚCN[h·é±ÆÍÈ¢D¼ÌCN[h
+ *  t@CÉæ§ÁÄ³êé½ßC¼ÌCN[ht@CÉË¶µ
+ *  ÄÍÈçÈ¢D
+ */
+
+#ifndef TOPPERS_TARGET_STDDEF_H
+#define TOPPERS_TARGET_STDDEF_H
+
+/*
+ *  ^[Qbgð¯Ê·é½ßÌ}NÌè`
+ */
+#define TOPPERS_CQ_FRK_FM3				/* VXeªÌ */
+
+/*
+ *  J­Â«Å¤ÊÈè`
+ *
+ *  J­Â«Åstdint.hªpÓ³êÄ¢éêÉÍCTOPPERS_STDINT_TYPE1Ì
+ *  }Nè`ðíµCstdint.hðCN[h·êÎæ¢D
+ */
+#define TOPPERS_STDINT_TYPE1
+#define TOPPERS_STDFLOAT_TYPE1
+#include "gcc/tool_stddef.h"
+
+/*
+ *  RAË¶Å¤ÊÈè`
+ */
+#include "arm_m_gcc/common/core_stddef.h"
+
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  AT[VÌ¸sÌÀsfiT.B.Dj
+ */
+Inline void
+TOPPERS_assert_abort(void)
+{
+    
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_STDDEF_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_syssvc.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_syssvc.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_syssvc.h	(revision 131)
@@ -0,0 +1,100 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *  VXeT[rXÌ^[QbgË¶
+ *
+ *  VXeT[rXÌ^[QbgË¶ÌCN[ht@CD±Ìt@
+ *  CÌàeÍCR|[lgLqt@CÉLq³êC±Ìt@CÍ
+ *  ³­Èé©ÝD
+ */
+
+#ifndef TOPPERS_TARGET_SYSSVC_H
+#define TOPPERS_TARGET_SYSSVC_H
+
+/*
+ *  ^[QbgVXeÌn[hEFA¹Ìè`
+ */
+#include "fm3_mb9bxxx.h"
+
+/*
+ *  g[XOÉÖ·éÝè
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  N®bZ[WÌ^[QbgVXe¼
+ */
+#define TARGET_NAME    "cqfrkfm3(ARM Cortex-M3)"
+
+/*
+ *  VXeOÌáxoÍÌ½ßÌ¶oÍ
+ *
+ *  ^[QbgË¶Ìû@ÅC¶cð\¦/oÍ/Û¶·éD
+ */
+extern void	target_fput_log(char c);
+
+/*
+ *  T|[g·éVA|[gÌ
+ */
+#define TNUM_PORT        TNUM_SIOP
+
+/*
+ *  O^XNªgp·é|[gID
+ */
+#define LOGTASK_PORTID   SIO_PORTID
+
+/*
+ *  {[[g
+ */
+#define BPS_SETTING		(115200)
+
+/*
+ *  VXeO^XNÖAÌèÌè`
+ *
+ *  ftHglÌÊèD
+ */
+
+#endif /* TOPPERS_TARGET_SYSSVC_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_test.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_test.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_test.h	(revision 131)
@@ -0,0 +1,57 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *		eXgvOÌ^[QbgË¶è`
+ */
+
+#ifndef TOPPERS_TARGET_TEST_H
+#define TOPPERS_TARGET_TEST_H
+
+/*
+ *  RAË¶W
+[iARM-Mpj
+ */
+#include "arm_m_gcc/common/core_test.h"
+
+#endif /* TOPPERS_TARGET_TEST_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_timer.cfg
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_timer.cfg	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_timer.cfg	(revision 131)
@@ -0,0 +1,6 @@
+/*
+ *    ^C}hCoÌRtBM
+[Vt@C
+ */
+#include "target_timer.h"
+INCLUDE("arm_m_gcc/common/core_timer.cfg");
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_timer.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_timer.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_timer.h	(revision 131)
@@ -0,0 +1,68 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ *  Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ *  ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ *  (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+ *       \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+ *      XR[hÉÜÜêÄ¢é±ÆD
+ *  (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+ *      Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+ *      Ì³ÛØKèðfÚ·é±ÆD
+ *  (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+ *      pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+ *      ÆD
+ *    (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+ *        ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+ *    (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+ *        ñ·é±ÆD
+ *  (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+ *      Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+ *      Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+ *      RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+ *      ÆÓ·é±ÆD
+ * 
+ *  {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ *  æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ *  ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ *  AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ *  ÌÓCðíÈ¢D
+ * 
+ */
+
+/*
+ *  ^C}hCo
+ */
+
+#ifndef TOPPERS_TARGET_TIMER_H
+#define TOPPERS_TARGET_TIMER_H
+
+/*
+ *  ^C}lÌà\»Æ~bPÊÆÌÏ·
+ */
+#define TIMER_CLOCK		(SYS_CLOCK / 1000)
+
+/*
+ *  ^C}Ýnho^Ì½ßÌè
+ */
+#define INTPRI_TIMER    (-6)          /* ÝDæx */
+#define INTATR_TIMER    0U            /* Ý®« */
+
+/*
+ *  RAË¶W
+[iARM-Mpj
+ */
+#include "arm_m_gcc/common/core_timer.h"
+
+#endif /* TOPPERS_TARGET_TIMER_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_unrename.h
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_unrename.h	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_unrename.h	(revision 131)
@@ -0,0 +1,27 @@
+/* This file is generated from target_rename.def by genrename. */
+
+/* This file is included only when target_rename.h has been included. */
+#ifdef TOPPERS_TARGET_RENAME_H
+#undef TOPPERS_TARGET_RENAME_H
+
+
+/*
+ * target_config.c
+ */
+#undef target_initialize
+#undef target_exit
+
+#ifdef TOPPERS_LABEL_ASM
+
+
+/*
+ * target_config.c
+ */
+#undef _target_initialize
+#undef _target_exit
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "arm_m_gcc/common/core_unrename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /asp_fm/asp/target/cqfrkfm3_gcc/target_user.txt
===================================================================
--- /asp_fm/asp/target/cqfrkfm3_gcc/target_user.txt	(revision 131)
+++ /asp_fm/asp/target/cqfrkfm3_gcc/target_user.txt	(revision 131)
@@ -0,0 +1,77 @@
+=====================================================================
+                          cqfrkfm3Ë¶
+=====================================================================
+
+(1) ÎµÄ¢é^[QbgVXeÌíÞE\¬
+
+cqfrkfm3Ë¶ÍCCQoÅÐÌC^[tF[X2012N6t®CQ-FRK-F
+M3ðT|[gµÄ¢éDÚµÄ¢é`bvÍMB9BF618TÅ éD
+
+(2) gp·éJ­Â«Æ®ìØµ½ðio[WCIvVj
+
+RpCÍGCCðp¢éD®ìmFÉp¢½RpCÍÈºÌÊèÅ éD
+
+  gcc version 4.5.2 (Sourcery G++ Lite 2011.03-42)
+
+fobOÂ«ÍCxmÊZ~R_N^[®ïÐÌFLASH USB Direct Prog
+rammerÆCOpenOCDÉæétbV
+ÖÌ«ÝÆfobOðmFµ
+½D
+
+(3) ^[Qbgè`ÌKè
+
+(3-1) ÝDæx
+
+CFG_INTÅgpÂ\ÈÝDæxÌÍÍÍC-16 ` -1 Å éDARM-MvZ
+bTË¶Ì}j
+A éæ¤ÉCTMIN_INTPRIÉÝèÂ\ÈlÌÅålÍ
+-15Å èCJ[lÇàÌÝÍ-15 ` -1 ÌDæxðÝèÂ\Å èC
+J[lÇOÌÝÌDæxÆµÄÍ-16ªgpÂ\Å éD
+
+(4) }bv
+
+vOÍFLASHÖf[^ÍRAMÖzu·éDzuðÏX·éÉÍC
+cqfrkfm3_rom.ld ðÏX·é±ÆD
+
+(5) VAC^tF[XhCoÌîñ
+
+VAC^tF[XhCoÅÍCUART0ðp¢éDÊMtH[}bgÍC
+115200bps, 8bit, non-parity, 1topbitÅ éD
+
+(6) VXeO@\Ìîñ
+
+VXeOÌáxoÍÍCUART0ðp¢éDÊMtH[}bgÍC
+115200bps, 8bit, non-parity, 1topbitÅ éD
+
+(7) fBNg\¬Et@C\¬
+ ./cqfrkfm3_gcc 
+   ./cqfrkfm3_rom.ld
+   ./fm3_mb9bxxx.h.h
+   ./Makefile.target
+   ./target.tf
+   ./target_asm.inc
+   ./target_cfg1_out.h
+   ./target_check.tf
+   ./target_config.c
+   ./target_config.h
+   ./target_kernel.h
+   ./target_offset.tf
+   ./target_rename.def
+   ./target_rename.h
+   ./target_serial.c
+   ./target_serial.cfg
+   ./target_serial.h
+   ./target_sil.h
+   ./target_stddef.h
+   ./target_syssvc.h
+   ./target_test.h
+   ./target_timer.cfg
+   ./target_timer.h
+   ./target_unrename.h
+   ./target_user.txt
+
+(8) o[Wð
+2012/04/23
+EÅÌ[X
+
+ÈãD
