[101] | 1 | /*
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| 2 | * TINET (TCP/IP Protocol Stack)
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| 3 | *
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| 4 | * Copyright (C) 2001-2009 by Dep. of Computer Science and Engineering
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| 5 | * Tomakomai National College of Technology, JAPAN
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| 6 | * Copyright (C) 2014 Cores Co., Ltd. Japan
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| 7 | *
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| 8 | * ãLì ÒÍCȺÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
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| 9 | * Ai{\tgEFAðüϵ½àÌðÜÞDȺ¯¶jðgpE¡»Eü
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| 10 | * ÏEÄzziȺCpÆÄÔj·é±Æð³Åø·éD
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| 11 | * (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
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| 12 | * \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
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| 13 | * XR[hÉÜÜêĢ鱯D
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| 14 | * (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
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| 15 | * pÅ«é`ÅÄzz·éêÉÍCÄzzɺ¤hL
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| 16 | gip
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| 17 | * Ò}j
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| 18 | AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
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| 19 | * Ì³ÛØKèðfÚ·é±ÆD
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| 20 | * (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
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| 21 | * pūȢ`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
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| 22 | * ÆD
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| 23 | * (a) Äzzɺ¤hL
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| 24 | gipÒ}j
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| 25 | AÈÇjÉCãLÌ
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| 26 | * ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
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| 27 | * (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
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| 28 | * ñ·é±ÆD
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| 29 | * (4) {\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶é¢©Èé¹
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| 30 | * Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
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| 31 | * ܽC{\tgEFAÌ[UܽÍGh[U©çÌ¢©Èé
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| 32 | * RÉîÿ©çàCãLì Ò¨æÑTOPPERSvWFNgð
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| 33 | * ÆÓ·é±ÆD
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| 34 | *
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| 35 | * {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
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| 36 | * æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
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| 37 | * ÉηéK«àÜßÄC¢©ÈéÛØàsíÈ¢DܽC{\tgEF
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| 38 | * AÌpÉæè¼ÚIܽÍÔÚIɶ¶½¢©Èé¹QÉÖµÄàC»
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| 39 | * ÌÓCðíÈ¢D
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| 40 | *
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| 41 | * @(#) $Id: if_rx62nreg.h 101 2015-06-02 15:37:23Z coas-nagasima $
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| 42 | */
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| 43 |
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| 44 | #ifndef RX62NRegH
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| 45 | #define RX62NRegH
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| 46 |
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| 47 | #include "t_stddef.h"
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| 48 |
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| 49 | #define EDMAC_EDMR ((uint32_t *)0x000C0000) /* EDMAC[hWX^ */
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| 50 | #define EDMAC_EDMR_SWR_BIT 0x00000001
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| 51 | #define EDMAC_EDMR_DE_BIT 0x00000040
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| 52 |
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| 53 | #define EDMAC_EDTRR ((uint32_t *)0x000C0008) /* EDMACMvWX^ */
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| 54 | #define EDMAC_EDTRR_TR 0x00000001
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| 55 |
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| 56 | #define EDMAC_EDRRR ((uint32_t *)0x000C0010) /* EDMACóMvWX^ */
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| 57 | #define EDMAC_EDRRR_RR 0x00000001
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| 58 |
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| 59 | #define EDMAC_TDLAR ((uint32_t *)0x000C0018) /* MfBXNv^XgæªAhXWX^ */
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| 60 | #define EDMAC_RDLAR ((uint32_t *)0x000C0020) /* óMfBXNv^XgæªAhXWX^ */
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| 61 |
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| 62 | #define EDMAC_EESR ((uint32_t *)0x000C0028) /* ETHERC/EDMACXe[^XWX^ */
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| 63 | #define EDMAC_EESR_FROF 0x00010000
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| 64 | #define EDMAC_EESR_RDE 0x00020000
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| 65 | #define EDMAC_EESR_FR 0x00040000
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| 66 | #define EDMAC_EESR_TC 0x00200000
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| 67 | #define EDMAC_EESR_TWB 0x40000000
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| 68 |
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| 69 | #define EDMAC_EESIPR ((uint32_t *)0x000C0030) /* ETHERC/EDMACXe[^XèÝÂWX^ */
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| 70 | #define EDMAC_EESIPR_RMAFIP 0x00000080
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| 71 | #define EDMAC_EESIPR_FROFIP 0x00010000
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| 72 | #define EDMAC_EESIPR_RDEIP 0x00020000
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| 73 | #define EDMAC_EESIPR_FRIP 0x00040000
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| 74 | #define EDMAC_EESIPR_TCIP 0x00200000
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| 75 | #define EDMAC_EESIPR_TWBIP 0x40000000
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| 76 |
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| 77 | #define EDMAC_TRSCER ((uint32_t *)0x000C0038) /* óMXe[^XRs[w¦WX^ */
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| 78 | #define EDMAC_RMFCR ((uint32_t *)0x000C0040) /* ~Xht[JE^WX^ */
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| 79 | #define EDMAC_TFTR ((uint32_t *)0x000C0048) /* MFIFOµ«¢lwèWX^ */
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| 80 | #define EDMAC_FDR ((uint32_t *)0x000C0050) /* FIFOeÊwèWX^ */
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| 81 | #define EDMAC_RMCR ((uint32_t *)0x000C0058) /* óMû®§äWX^ */
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| 82 | #define EDMAC_TFUCR ((uint32_t *)0x000C0064) /* MFIFOA_JEg */
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| 83 | #define EDMAC_RFOCR ((uint32_t *)0x000C0068) /* óMFIFOI[ot[JEg */
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| 84 | #define EDMAC_IOSR ((uint32_t *)0x000C006C) /* ÂÊoÍMÝèWX^ */
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| 85 | #define EDMAC_FCFTR ((uint32_t *)0x000C0070) /* t[§äJnFIFOµ«¢lÝèWX^ */
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| 86 | #define EDMAC_RPADIR ((uint32_t *)0x000C0078) /* óMf[^pfBO}üÝèWX^ */
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| 87 | #define EDMAC_TRIMD ((uint32_t *)0x000C007C) /* MèÝÝèWX^ */
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| 88 | #define EDMAC_RBWAR ((uint32_t *)0x000C00C8) /* óMobt@CgAhXWX^ */
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| 89 | #define EDMAC_RDFAR ((uint32_t *)0x000C00CC) /* óMfBXNv^tFb`AhXWX^ */
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| 90 | #define EDMAC_TBRAR ((uint32_t *)0x000C00D4) /* Mobt@[hAhXWX^ */
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| 91 | #define EDMAC_TDFAR ((uint32_t *)0x000C00D8) /* MfBXNv^tFb`AhXWX^ */
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| 92 |
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| 93 | #define ETHERC_ECMR ((uint32_t *)0x000C0100) /* ETHERC[hWX^ */
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| 94 | #define ETHERC_ECMR_PRM 0x00000001
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| 95 | #define ETHERC_ECMR_DM 0x00000002
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| 96 | #define ETHERC_ECMR_RTM 0x00000004
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| 97 | #define ETHERC_ECMR_TE 0x00000020
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| 98 | #define ETHERC_ECMR_RE 0x00000040
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| 99 |
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| 100 | #define ETHERC_RFLR ((uint32_t *)0x000C0108) /* óMt[·ãÀWX^ */
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| 101 | #define ETHERC_ECSR ((uint32_t *)0x000C0110) /* ETHERCXe[^XWX^ */
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| 102 | #define ETHERC_ECSR_LCHNG 0x00000004
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| 103 | #define ETHERC_ECSIPR ((uint32_t *)0x000C0118) /* ETHERCèÝÂWX^ */
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| 104 | #define ETHERC_ECSIPR_LCHNGIP 0x00000004
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| 105 | #define ETHERC_PIR ((uint32_t *)0x000C0120) /* PHYC^tF[XWX^ */
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| 106 | #define ETHERC_PIR_MDC 0x00000001
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| 107 | #define ETHERC_PIR_MMD 0x00000002
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| 108 | #define ETHERC_PIR_MDO 0x00000004
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| 109 | #define ETHERC_PIR_MDI 0x00000008
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| 110 |
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| 111 | #define ETHERC_PSR ((uint32_t *)0x000C0128) /* PHYXe[^XWX^ */
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| 112 | #define ETHERC_PSR_LMON 0x00000001
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| 113 |
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| 114 | #define ETHERC_RDMLR ((uint32_t *)0x000C0140) /* ¶¬JE^ãÀlÝèWX^ */
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| 115 | #define ETHERC_IPGR ((uint32_t *)0x000C0150) /* IPGÝèWX^ */
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| 116 | #define ETHERC_APR ((uint32_t *)0x000C0154) /* ©®PAUSEt[ÝèWX^ */
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| 117 | #define ETHERC_MPR ((uint32_t *)0x000C0158) /* è®PAUSEt[ÝèWX^ */
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| 118 | #define ETHERC_RFCF ((uint32_t *)0x000C0160) /* óMPAUSEt[JE^ */
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| 119 | #define ETHERC_TPAUSER ((uint32_t *)0x000C0164) /* ©®PAUSEt[ÄñÝèWX^ */
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| 120 | #define ETHERC_TPAUSECR ((uint32_t *)0x000C0168) /* PAUSEt[ÄñJE^ */
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| 121 | #define ETHERC_BCFRR ((uint32_t *)0x000C016C) /* Broadcastt[óMñÝèWX^ */
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| 122 | #define ETHERC_MAHR ((uint32_t *)0x000C01C0) /* MACAhXãÊÝèWX^ */
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| 123 | #define ETHERC_MALR ((uint32_t *)0x000C01C8) /* MACAhXºÊÝèWX^ */
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| 124 | #define ETHERC_TROCR ((uint32_t *)0x000C01D0) /* MgCI[oJE^WX^ */
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| 125 | #define ETHERC_CDCR ((uint32_t *)0x000C01D4) /* xÕËoJE^WX^ */
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| 126 | #define ETHERC_LCCR ((uint32_t *)0x000C01D8) /* LAÁ¸JE^WX^ */
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| 127 | #define ETHERC_CNDCR ((uint32_t *)0x000C01DC) /* LA¢oJE^WX^ */
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| 128 | #define ETHERC_CEFCR ((uint32_t *)0x000C01E4) /* CRCG[t[óMJE^WX^ */
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| 129 | #define ETHERC_FRECR ((uint32_t *)0x000C01E8) /* t[óMG[JE^WX^ */
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| 130 | #define ETHERC_TSFRCR ((uint32_t *)0x000C01EC) /* 64oCg¢t[óMJE^WX^ */
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| 131 | #define ETHERC_TLFRCR ((uint32_t *)0x000C01F0) /* wèoCg´t[óMJE^WX^ */
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| 132 | #define ETHERC_RFCR ((uint32_t *)0x000C01F4) /* [rbgt[óMJE^WX^ */
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| 133 | #define ETHERC_MAFCR ((uint32_t *)0x000C01F8) /* }`LXgAhXt[óMJE^WX^ */
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| 134 |
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| 135 | /* MfBXNv^ */
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| 136 | typedef struct t_rx62n_tx_desc {
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| 137 | uint32_t tfs : 26;
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| 138 | uint32_t twbi : 1;
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| 139 | uint32_t tfe : 1;
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| 140 | uint32_t tfp : 2;
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| 141 | uint32_t tdle : 1;
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| 142 | uint32_t tact : 1;
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| 143 | uint32_t : 16;
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| 144 | uint32_t tbl : 16;
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| 145 | uint32_t tba;
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| 146 | uint32_t binding;
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| 147 | } T_RX62N_TX_DESC;
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| 148 |
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| 149 | /* óMfBXNv^ */
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| 150 | typedef struct t_rx62n_rx_desc {
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| 151 | uint32_t rfs : 27;
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| 152 | uint32_t rfe : 1;
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| 153 | uint32_t rfp : 2;
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| 154 | uint32_t rdle : 1;
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| 155 | uint32_t ract : 1;
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| 156 | uint32_t rfl : 16;
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| 157 | uint32_t rbl : 16;
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| 158 | uint32_t rba;
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| 159 | uint32_t binding;
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| 160 | } T_RX62N_RX_DESC;
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| 161 |
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| 162 | #endif /* RX62NRegH */
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