source: uKadecot/trunk/uip/target/if_rx62n/if_rx62n.c@ 101

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1/*
2 * TOPPERS ECHONET Lite Communication Middleware
3 *
4 * Copyright (C) 2014 Cores Co., Ltd. Japan
5 *
6 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì(1)`(4)‚ÌðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒF
7 * ƒAi–{ƒ\ƒtƒgƒEƒFƒA‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü
8 * •ÏEÄ”z•ziˆÈ‰ºC—˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
9 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
10 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
11 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
12 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
13 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
14ƒƒ“ƒgi—˜—p
15 * ŽÒƒ}ƒjƒ…
16ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
17 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
18 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
19 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
20 * ‚ƁD
21 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
22ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
23ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
24 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
25 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
26 * •ñ‚·‚邱‚ƁD
27 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
28 * ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
29 * ‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚̃†[ƒU‚Ü‚½‚̓Gƒ“ƒhƒ†[ƒU‚©‚ç‚Ì‚¢‚©‚Ȃ闝
30 * —R‚ÉŠî‚­¿‹‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð
31 * –Ɛӂ·‚邱‚ƁD
32 *
33 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
34 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC“Á’è‚ÌŽg—p–Ú“I
35 * ‚ɑ΂·‚é“K‡«‚àŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒF
36 * ƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»
37 * ‚̐ӔC‚𕉂í‚È‚¢D
38 *
39 * @(#) $Id: if_rx62n.c 101 2015-06-02 15:37:23Z coas-nagasima $
40 */
41
42#define CAST(type, val) ((type)(val))
43
44#include <kernel.h>
45#include <sil.h>
46#include <t_syslog.h>
47#include <string.h>
48#include "kernel_cfg.h"
49#include "kernel/kernel_impl.h"
50#include "uip_target_config.h"
51#include "uip_arp.h"
52#include "if_rx62n.h"
53#include "ether_phy.h"
54
55extern uint8_t mac_addr[ETHER_ADDR_LEN];
56
57/*
58 * ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚Ɉˑ¶‚·‚éƒ\ƒtƒgƒEƒFƒAî•ñ
59 */
60
61typedef struct t_rx62n_softc {
62 T_RX62N_TX_DESC *tx_write;
63 T_RX62N_RX_DESC *rx_read;
64 PHY_STATE_T state;
65} T_RX62N_SOFTC;
66
67/*
68 * ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚̃\ƒtƒgƒEƒFƒAî•ñ
69 */
70
71/* ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚Ɉˑ¶‚·‚éƒ\ƒtƒgƒEƒFƒAî•ñ */
72
73static T_RX62N_SOFTC rx62n_softc;
74
75typedef struct t_rx62n_buf {
76 uint8_t rx_buff[NUM_IF_RX62N_RXBUF][32 * ((IF_RX62N_BUF_PAGE_SIZE + 31) / 32)];
77 uint8_t tx_buff[NUM_IF_RX62N_TXBUF][32 * ((IF_RX62N_BUF_PAGE_SIZE + 31) / 32)];
78 T_RX62N_RX_DESC rx_desc[NUM_IF_RX62N_RXBUF];
79 T_RX62N_TX_DESC tx_desc[NUM_IF_RX62N_TXBUF];
80} T_RX62N_BUF;
81
82#if defined(__RX)
83#pragma section ETH_MEMORY
84#endif
85T_RX62N_BUF rx62n_buf;
86#if defined(__RX)
87#pragma section
88#endif
89
90/* ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚Ɉˑ¶‚µ‚È‚¢ƒ\ƒtƒgƒEƒFƒAî•ñ */
91
92T_IF_SOFTC if_softc = {
93// {0,}, /* ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚̃AƒhƒŒƒX */
94// 0, /* ‘—Mƒ^ƒCƒ€ƒAƒEƒg */
95 &rx62n_softc, /* ƒfƒBƒoƒCƒXˆË‘¶‚̃\ƒtƒgƒEƒFƒAî•ñ */
96};
97
98/*
99 * ‹ÇŠ•Ï”
100 */
101
102static void rx62n_stop (T_RX62N_SOFTC *sc);
103static void rx62n_init_sub (T_IF_SOFTC *ic);
104static void rx62n_set_ecmr (T_IF_SOFTC *ic, PHY_MODE_T mode);
105
106/*
107 * rx62n_stop -- ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚ð’âŽ~‚·‚éB
108 *
109 * ’ˆÓ: NIC Š„‚荞‚Ý‹ÖŽ~ó‘ԂŌĂяo‚·‚±‚ƁB
110 */
111
112static void
113rx62n_stop (T_RX62N_SOFTC *sc)
114{
115 /* “®ìƒ‚[ƒhƒNƒŠƒA */
116 sil_wrw_mem(ETHERC_ECMR, 0x00000000);
117}
118
119/*
120 * rx62n_init_sub -- ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚̏‰Šú‰»
121 *
122 * ’ˆÓ: NIC Š„‚荞‚Ý‹ÖŽ~ó‘ԂŌĂяo‚·‚±‚ƁB
123 */
124
125static void
126rx62n_init_sub (T_IF_SOFTC *ic)
127{
128 int i;
129 PHY_STATE_T state = PHY_STATE_UNINIT;
130
131 /* MAC•”ƒ\ƒtƒgƒEƒGƒAEƒŠƒZƒbƒg */
132 sil_wrw_mem(EDMAC_EDMR, sil_rew_mem(EDMAC_EDMR) | EDMAC_EDMR_SWR_BIT);
133
134 /* ƒŠƒZƒbƒgŠ®—¹‘Ò‚¿ */
135 for (i = 0; i < 10000; i++) {
136 }
137
138 sil_wrw_mem(ETHERC_MAHR, ((uint32_t)mac_addr[0] << 24)
139 | ((uint32_t)mac_addr[1] << 16) | ((uint32_t)mac_addr[2] << 8 )
140 | (uint32_t)mac_addr[3]);
141 sil_wrw_mem(ETHERC_MALR, ((uint32_t)mac_addr[4] << 8 )
142 | (uint32_t)mac_addr[5]);
143
144 /* PHYƒŠƒZƒbƒg */
145 while((state = phy_reset(state, 0)) != PHY_STATE_RESET);
146 ic->sc->state = state;
147
148 /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */
149 sil_wrw_mem(ETHERC_ECSR, 0x00000037);
150
151 /* ƒŠƒ“ƒN•Ï‰»Š„‚荞‚Ý—LŒø */
152 sil_wrw_mem(ETHERC_ECSIPR, sil_rew_mem(ETHERC_ECSIPR) | ETHERC_ECSIPR_LCHNGIP);
153
154 /* Clear all ETHERC and EDMAC status bits */
155 sil_wrw_mem(EDMAC_EESR, 0x47FF0F9F);
156
157 /* ‘—ŽóMŠ„‚荞‚Ý—LŒø */
158 sil_wrw_mem(EDMAC_EESIPR, (EDMAC_EESIPR_TCIP | EDMAC_EESIPR_FRIP | EDMAC_EESIPR_RDEIP | EDMAC_EESIPR_FROFIP));
159
160 /* ŽóMƒtƒŒ[ƒ€’·ãŒÀiƒoƒbƒtƒ@ƒTƒCƒYj */
161 sil_wrw_mem(ETHERC_RFLR, IF_RX62N_BUF_PAGE_SIZE);
162
163 /* 96ƒrƒbƒgŽžŠÔi‰Šú’lj */
164 sil_wrw_mem(ETHERC_IPGR, 0x00000014);
165
166 /* Set little endian mode */
167 sil_wrw_mem(EDMAC_EDMR, sil_rew_mem(EDMAC_EDMR) | EDMAC_EDMR_DE_BIT);
168
169 /* Initialize Rx descriptor list address */
170 sil_wrw_mem(EDMAC_RDLAR, (uint32_t)rx62n_buf.rx_desc);
171 /* Initialize Tx descriptor list address */
172 sil_wrw_mem(EDMAC_TDLAR, (uint32_t)rx62n_buf.tx_desc);
173 /* Copy-back status is RFE & TFE only */
174 sil_wrw_mem(EDMAC_TRSCER, 0x00000000);
175 /* Threshold of Tx_FIFO */
176 sil_wrw_mem(EDMAC_TFTR, 0x00000000);
177 /* Transmit fifo & receive fifo is 2048 bytes */
178 sil_wrw_mem(EDMAC_FDR, 0x00000707);
179 /* RR in EDRRR is under driver control */
180 sil_wrw_mem(EDMAC_RMCR, 0x00000001);
181
182 /* PHY‚̏‰Šú‰»‚𑣂· */
183 ic->link_pre = true;
184 ic->link_now = false;
185
186 /* ƒ^[ƒQƒbƒgˆË‘¶•”‚ÌŠ„ž‚ݏ‰Šú‰» */
187 rx62n_inter_init();
188}
189
190/*
191 * rx62n_set_ecmr -- ECMRƒŒƒWƒXƒ^‚̐ݒè
192 */
193
194static void
195rx62n_set_ecmr (T_IF_SOFTC *ic, PHY_MODE_T mode)
196{
197 uint32_t ecmr;
198
199 ecmr = ETHERC_ECMR_RE | ETHERC_ECMR_TE/* | ETHERC_ECMR_PRM*/;
200
201 if ((mode & 0x01) != 0)
202 ecmr |= ETHERC_ECMR_DM;
203 if ((mode & 0x02) != 0)
204 ecmr |= ETHERC_ECMR_RTM;
205
206 /* “®ìƒ‚[ƒhÝ’è */
207 sil_wrw_mem(ETHERC_ECMR, ecmr);
208}
209
210/*
211 * rx62n_reset -- ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚ðƒŠƒZƒbƒg‚·‚éB
212 */
213
214void
215rx62n_reset (T_IF_SOFTC *ic)
216{
217 /* NIC ‚©‚ç‚ÌŠ„‚荞‚Ý‚ð‹ÖŽ~‚·‚éB*/
218 dis_int(INTNO_IF_RX62N_TRX);
219
220 rx62n_stop(ic->sc);
221 rx62n_init_sub(ic);
222
223 /* NIC ‚©‚ç‚ÌŠ„‚荞‚Ý‚ð‹–‰Â‚·‚éB*/
224 ena_int(INTNO_IF_RX62N_TRX);
225}
226
227/*
228 * get_rx62n_softc -- ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚̃\ƒtƒgƒEƒFƒAî•ñ‚ð•Ô‚·B
229 */
230
231T_IF_SOFTC *
232rx62n_get_softc (void)
233{
234 return &if_softc;
235}
236
237/*
238 * rx62n_watchdog -- ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚̃ƒbƒ`ƒhƒbƒOƒ^ƒCƒ€ƒAƒEƒg
239 */
240
241void
242rx62n_watchdog (T_IF_SOFTC *ic)
243{
244 rx62n_reset(ic);
245}
246
247/*
248 * rx62n_probe -- ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚ÌŒŸo
249 */
250
251void
252rx62n_probe (T_IF_SOFTC *ic)
253{
254 /* ƒ^[ƒQƒbƒgˆË‘¶•”‚̃oƒX‚̏‰Šú‰» */
255 rx62n_bus_init();
256
257 memcpy(uip_ethaddr.addr, mac_addr, sizeof(uip_ethaddr.addr));
258}
259
260/*
261 * rx62n_init -- ƒlƒbƒgƒ[ƒNƒCƒ“ƒ^ƒtƒF[ƒX‚̏‰Šú‰»
262 */
263
264void
265rx62n_init (T_IF_SOFTC *ic)
266{
267 T_RX62N_SOFTC *sc = ic->sc;
268 T_RX62N_TX_DESC *tdsc;
269 T_RX62N_RX_DESC *rdsc;
270 int i;
271
272 /* NIC ‚©‚ç‚ÌŠ„‚荞‚Ý‚ð‹ÖŽ~‚·‚éB*/
273 dis_int(INTNO_IF_RX62N_TRX);
274
275 tdsc = (T_RX62N_TX_DESC *)rx62n_buf.tx_desc;
276 sc->tx_write = tdsc;
277 for ( i=0 ; i < NUM_IF_RX62N_TXBUF ; i++ ) {
278 memset(tdsc, 0, sizeof(*tdsc));
279 tdsc->tbl = 0;
280 tdsc->tba = (uint32_t)&rx62n_buf.tx_buff[i];
281 tdsc++;
282 }
283 tdsc--;
284 tdsc->tdle = 1;
285
286 rdsc = (T_RX62N_RX_DESC *)rx62n_buf.rx_desc;
287 sc->rx_read = rdsc;
288 for ( i=0 ; i < NUM_IF_RX62N_RXBUF ; i++ ) {
289 memset(rdsc, 0, sizeof(*rdsc));
290 rdsc->rbl = IF_RX62N_BUF_PAGE_SIZE;
291 rdsc->rba = (uint32_t)&rx62n_buf.rx_buff[i];
292 rdsc->rfl = 0;
293 rdsc->ract = 1;
294 rdsc++;
295 }
296 rdsc--;
297 rdsc->rdle = 1;
298
299 /* rx62n_init –{‘Ì‚ðŒÄ‚яo‚·B*/
300 rx62n_init_sub(ic);
301
302 if (sil_rew_mem(EDMAC_EDRRR) == 0) {
303 sil_wrw_mem(EDMAC_EDRRR, EDMAC_EDRRR_RR);
304 }
305
306 /* NIC ‚©‚ç‚ÌŠ„‚荞‚Ý‚ð‹–‰Â‚·‚éB*/
307 ena_int(INTNO_IF_RX62N_TRX);
308}
309
310/*
311 * rx62n_link -- ƒŠƒ“ƒNó‘Ԃ̕ω»‚ɑ΂·‚鏈—
312 */
313bool_t
314rx62n_link(T_IF_SOFTC *ic)
315{
316 T_RX62N_SOFTC *sc = ic->sc;
317 PHY_MODE_T mode;
318
319 if(sc->state == PHY_STATE_NEGOTIATED){
320 ic->link_now = phy_is_link(0);
321 if(!ic->link_now)
322 sc->state = PHY_STATE_RESET;
323 return true;
324 }
325
326 /* PHY‚̏‰Šú‰» */
327 sc->state = phy_initialize(sc->state, 0, &mode);
328 if(sc->state != PHY_STATE_NEGOTIATED){
329 return false;
330 }
331
332 /* ECMRƒŒƒWƒXƒ^‚̐ݒè */
333 rx62n_set_ecmr(ic, mode);
334 return true;
335}
336
337/*
338 * rx62n_read -- ƒtƒŒ[ƒ€‚̓ǂݍž‚Ý
339 */
340
341int
342rx62n_read (T_IF_SOFTC *ic, void **input)
343{
344 T_RX62N_SOFTC *sc = ic->sc;
345 T_RX62N_RX_DESC *desc;
346 uint16_t len;
347
348 if (ic->over_flow) {
349 ic->over_flow = false;
350 }
351
352 desc = sc->rx_read;
353
354 if (desc->ract != 0) {
355 return 0;
356 }
357
358 len = desc->rfl;
359 memcpy(*input, (void *)desc->rba, len);
360
361 desc->rfp = 0;
362 desc->ract = 1;
363
364 desc++;
365 if (desc == &rx62n_buf.rx_desc[NUM_IF_RX62N_RXBUF]) {
366 desc = rx62n_buf.rx_desc;
367 }
368 sc->rx_read = desc;
369
370 if (sil_rew_mem(EDMAC_EDRRR) == 0) {
371 sil_wrw_mem(EDMAC_EDRRR, EDMAC_EDRRR_RR);
372 }
373
374 if ((ic->rxb_read == ic->rxb_write) && (desc->ract == 0))
375 ic->rxb_read--;
376
377 return len;
378}
379
380/*
381 * rx62n_start -- ‘—MƒtƒŒ[ƒ€‚ðƒoƒbƒtƒ@ƒŠƒ“ƒO‚·‚éB
382 */
383
384void
385rx62n_start (T_IF_SOFTC *ic, void *output, int size)
386{
387 T_RX62N_SOFTC *sc = ic->sc;
388 T_RX62N_TX_DESC *desc, *next;
389 uint8_t *buf = NULL;
390 int32_t len, res, pos;
391 uint32_t tfp;
392
393 for ( res = size, pos = 0; res > 0; res -= len, pos += len ) {
394 desc = sc->tx_write;
395
396 if (desc->tact != 0) {
397 break;
398 }
399
400 buf = (uint8_t *)desc->tba;
401
402 next = desc + 1;
403 if (next == &rx62n_buf.tx_desc[NUM_IF_RX62N_TXBUF]) {
404 next = rx62n_buf.tx_desc;
405 }
406 sc->tx_write = next;
407
408 len = res;
409 if ( len > IF_RX62N_BUF_PAGE_SIZE ) {
410 len = IF_RX62N_BUF_PAGE_SIZE;
411 tfp = 0x0;
412 }
413 else
414 tfp = 0x1;
415
416 if (pos == 0)
417 tfp |= 0x2;
418
419 memcpy(buf, (uint8_t *)output + pos, len);
420
421 desc->tbl = len;
422 desc->tfp = tfp;
423 desc->tact = 1;
424 }
425
426 if (sil_rew_mem(EDMAC_EDTRR) == 0) {
427 sil_wrw_mem(EDMAC_EDTRR, EDMAC_EDTRR_TR);
428 }
429}
430
431/*
432 * RX62N Ethernet Controler ‘—ŽóMŠ„‚荞‚݃nƒ“ƒhƒ‰
433 */
434
435void
436if_rx62n_trx_handler (void)
437{
438 T_IF_SOFTC *ic;
439 T_RX62N_SOFTC *sc;
440 uint32_t ecsr, eesr, psr;
441 bool_t acttsk;
442
443 i_begin_int(INTNO_IF_RX62N_TRX);
444
445 ic = &if_softc;
446 sc = ic->sc;
447
448 ecsr = sil_rew_mem(ETHERC_ECSR);
449
450 if (ecsr & ETHERC_ECSR_LCHNG) {
451 /* ETHERC•”Š„‚荞‚Ý—vˆöƒNƒŠƒA */
452 sil_wrw_mem(ETHERC_ECSR, ETHERC_ECSR_LCHNG);
453
454 psr = sil_rew_mem(ETHERC_PSR);
455 ic->link_now = (psr & ETHERC_PSR_LMON) != 0;
456
457 /* ƒŠƒ“ƒNó‘Ԃɕω»‚ ‚è */
458 if (ic->link_pre != ic->link_now) {
459 /* ŽóMŠ„‚荞‚ݏˆ— */
460 acttsk = true;
461 }
462 }
463
464 eesr = sil_rew_mem(EDMAC_EESR);
465
466 if (eesr & EDMAC_EESR_FR) {
467 /* DMA•”Š„‚荞‚Ý—vˆöƒNƒŠƒA */
468 sil_wrw_mem(EDMAC_EESR, EDMAC_EESR_FR);
469
470 /* ŽóMŠ„‚荞‚ݏˆ— */
471 acttsk = true;
472 ic->rxb_write++;
473 }
474 if (eesr & EDMAC_EESR_TC) {
475 /* DMA•”Š„‚荞‚Ý—vˆöƒNƒŠƒA */
476 sil_wrw_mem(EDMAC_EESR, EDMAC_EESR_TC);
477
478 /* ‘—MŠ„‚荞‚ݏˆ— */
479 acttsk = true;
480 }
481 if (eesr & (EDMAC_EESR_FROF | EDMAC_EESR_RDE)) {
482 /* DMA•”Š„‚荞‚Ý—vˆöƒNƒŠƒA */
483 sil_wrw_mem(EDMAC_EESR, EDMAC_EESR_FROF | EDMAC_EESR_RDE);
484
485 ic->over_flow = true;
486
487 /* ŽóMŠ„‚荞‚ݏˆ— */
488 acttsk = true;
489 ic->rxb_write++;
490 }
491
492 if(acttsk)
493 iact_tsk(UIP_TASK);
494
495 i_end_int(INTNO_IF_RX62N_TRX);
496}
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