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ether_phy.c@ 101

Last change on this file since 101 was 101, checked in by coas-nagasima, 9 years ago
TOPPERS/uKadecotのソースコードを追加
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[101]	1	/*
	2	* TINET (TCP/IP Protocol Stack)
	3	*
	4	* Copyright (C) 2001-2009 by Dep. of Computer Science and Engineering
	5	* Tomakomai National College of Technology, JAPAN
	6	* Copyright (C) 2014 Cores Co., Ltd. Japan
	7	*
	8	* ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
	9	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
	10	* ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
	11	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
	12	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
	13	* XR[hÉÜÜêÄ¢é±ÆD
	14	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
	15	* pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
	16	gip
	17	* Ò}j
	18	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
	19	* Ì³ÛØKèðfÚ·é±ÆD
	20	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
	21	* pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
	22	* ÆD
	23	* (a) ÄzzÉº¤hL
	24	gipÒ}j
	25	AÈÇjÉCãLÌ
	26	* ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
	27	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
	28	* ñ·é±ÆD
	29	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
	30	* Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
	31	* Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
	32	* RÉîÃ¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
	33	* ÆÓ·é±ÆD
	34	*
	35	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
	36	* æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
	37	* ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
	38	* AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
	39	* ÌÓCðíÈ¢D
	40	*
	41	* @(#) $Id: ether_phy.c 101 2015-06-02 15:37:23Z coas-nagasima $
	42	*/
	43
	44	#include "ether_phy.h"
	45	#include <kernel.h>
	46	#include "uip.h"
	47	#include <sil.h>
	48
	49	#define PHY_CONTROL_REGISTER 0x00
	50
	51	#define PHY_CONTROL_RESET 0x8000
	52	#define PHY_CONTROL_LOOPBACK 0x4000
	53	#define PHY_CONTROL_SPEED_SELECT 0x2000
	54	#define PHY_CONTROL_A_N_ENABLE 0x1000
	55	#define PHY_CONTROL_POWER_DOWN 0x0800
	56	#define PHY_CONTROL_ISOLATE 0x0400
	57	#define PHY_CONTROL_RESTART_A_N 0x0200
	58	#define PHY_CONTROL_DUPLEX_MODE 0x0100
	59	#define PHY_CONTROL_COLLISION_TEST 0x0080
	60
	61	#define PHY_STATUS_REGISTER 0x01
	62
	63	#define PHY_STATUS_100BASE_T4 0x8000
	64	#define PHY_STATUS_100BASE_TX_FULL_DUPLEX 0x4000
	65	#define PHY_STATUS_100BASE_TX_HALF_DUPLEX 0x2000
	66	#define PHY_STATUS_10BASE_T_FULL_DUPLEX 0x1000
	67	#define PHY_STATUS_10BASE_T_HALF_DUPLEX 0x0800
	68	#define PHY_STATUS_A_N_COMPLETE 0x0020
	69	#define PHY_STATUS_REMOTE_FAULT 0x0010
	70	#define PHY_STATUS_A_N_ABILITY 0x0008
	71	#define PHY_STATUS_LINK_STATUS 0x0004
	72	#define PHY_STATUS_JABBER_DETECT 0x0002
	73	#define PHY_STATUS_EXTENDED_CAPABILITY 0x0001
	74
	75	#define PHY_AN_ADVERTISEMENT_REGISTER 0x04
	76
	77	#define PHY_AN_AD_100BASE_T4 0x0200
	78	#define PHY_AN_AD_100BASE_TX_FULL_DUPLEX 0x0100
	79	#define PHY_AN_AD_100BASE_TX_HALF_DUPLEX 0x0080
	80	#define PHY_AN_AD_10BASE_T_FULL_DUPLEX 0x0040
	81	#define PHY_AN_AD_10BASE_T_HALF_DUPLEX 0x0020
	82	#define PHY_AN_AD_SELECTOR_FIELD 0x0001
	83
	84	#define PHY_AN_STATUS_REGISTER 0x05
	85
	86	#define PHY_AN_STATUS_100BASE_T4 0x0200
	87	#define PHY_AN_STATUS_100BASE_TX_FULL_DUPLEX 0x0100
	88	#define PHY_AN_STATUS_100BASE_TX_HALF_DUPLEX 0x0080
	89	#define PHY_AN_STATUS_10BASE_T_FULL_DUPLEX 0x0040
	90	#define PHY_AN_STATUS_10BASE_T_HALF_DUPLEX 0x0020
	91
	92	static void phy_write_bit(bool_t bit);
	93	static void phy_release_bus();
	94	static bool_t phy_read_bit();
	95	static void phy_single_rel_bus();
	96
	97	PHY_STATE_T phy_reset(PHY_STATE_T state, uint8_t phy_addr)
	98	{
	99	switch(state){
	100	case PHY_STATE_UNINIT:
	101	/* PHYÌZbg */
	102	phy_write_reg(phy_addr, PHY_CONTROL_REGISTER, PHY_CONTROL_RESET);
	103
	104	/* 500msÒÂ */
	105	/* tslp_tsk(500); svH */
	106	/* continue; */
	107	case PHY_STATE_RESETING:
	108	/* Zbg®¹ÌmF */
	109	if((phy_read_reg(phy_addr, PHY_CONTROL_REGISTER) & PHY_CONTROL_RESET) != 0)
	110	return PHY_STATE_RESETING;
	111
	112	return PHY_STATE_RESET;
	113	default:
	114	return state;
	115	}
	116	}
	117
	118	PHY_STATE_T phy_initialize(PHY_STATE_T state, uint8_t phy_addr, PHY_MODE_T *mode)
	119	{
	120	#ifndef __RX
	121	static int reset = 0;
	122	#endif
	123	uint16_t status;
	124	*mode = (PHY_MODE_T)0;
	125
	126	switch(state){
	127	case PHY_STATE_RESET:
	128	#ifndef __RX
	129	reset++;
	130	if(reset < 2){
	131	#endif
	132	/* N®¹ÌmF */
	133	if(!phy_is_link(phy_addr))
	134	return PHY_STATE_RESET;
	135	#ifndef __RX
	136	}
	137	reset = 0;
	138	#endif
	139	/* I[glSVG[VÌ¨mç¹ðLøÉÝè */
	140	phy_write_reg(phy_addr, PHY_AN_ADVERTISEMENT_REGISTER,
	141	PHY_AN_AD_100BASE_T4 \| PHY_AN_AD_100BASE_TX_FULL_DUPLEX \| PHY_AN_AD_100BASE_TX_HALF_DUPLEX
	142	\| PHY_AN_AD_10BASE_T_FULL_DUPLEX \| PHY_AN_AD_10BASE_T_HALF_DUPLEX \| PHY_AN_AD_SELECTOR_FIELD);
	143
	144	/* I[glSVG[VðLøÉÝè */
	145	phy_write_reg(phy_addr, PHY_CONTROL_REGISTER, PHY_CONTROL_SPEED_SELECT \| PHY_CONTROL_A_N_ENABLE);
	146
	147	/* continue; */
	148	case PHY_STATE_LINKED:
	149	#ifndef __RX
	150	reset++;
	151	if(reset < 2){
	152	#endif
	153	/* I[glSVG[V®¹ÌmF */
	154	if((phy_read_reg(phy_addr, PHY_STATUS_REGISTER) & PHY_STATUS_A_N_COMPLETE) == 0)
	155	return PHY_STATE_LINKED;
	156	#ifndef __RX
	157	}
	158	#endif
	159	status = phy_read_reg(phy_addr, PHY_AN_STATUS_REGISTER);
	160
	161	if ((status & (PHY_AN_STATUS_100BASE_T4 \| PHY_AN_STATUS_10BASE_T_FULL_DUPLEX \| PHY_AN_STATUS_100BASE_TX_FULL_DUPLEX)) != 0)
	162	mode = (PHY_MODE_T)(((int)mode) \| 0x01);
	163
	164	if ((status & (PHY_AN_STATUS_100BASE_T4 \| PHY_AN_STATUS_100BASE_TX_FULL_DUPLEX \| PHY_AN_STATUS_100BASE_TX_HALF_DUPLEX)) != 0)
	165	mode = (PHY_MODE_T)(((int)mode) \| 0x02);
	166
	167	return PHY_STATE_NEGOTIATED;
	168	}
	169
	170	return state;
	171	}
	172
	173	bool_t phy_is_link(uint8_t phy_addr)
	174	{
	175	#ifdef __RX
	176	/* NÌmF */
	177	return (phy_read_reg(phy_addr, PHY_STATUS_REGISTER) & PHY_STATUS_LINK_STATUS) != 0;
	178	#else
	179	return true;
	180	#endif
	181	}
	182
	183	uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr)
	184	{
	185	uint16_t result = 0, bit;
	186	int i;
	187
	188	/* PRE F32ÂÌA±µ½1b */
	189	for (i = 0; i < 32; i++)
	190	phy_write_bit(true);
	191
	192	/* ST Ft[Ìæªð¦·01bÌCg */
	193	phy_write_bit(false);
	194	phy_write_bit(true);
	195
	196	/* OP FANZXíÊð¦·R[hÌCg */
	197	phy_write_bit(true);
	198	phy_write_bit(false);
	199
	200	/* PHYAD FPHY-LSIÌAhXª1ÔÌêA00001bðCgiMSB ©çCgjB */
	201	phy_write_bit((phy_addr & 0x10) != 0);
	202	phy_write_bit((phy_addr & 0x08) != 0);
	203	phy_write_bit((phy_addr & 0x04) != 0);
	204	phy_write_bit((phy_addr & 0x02) != 0);
	205	phy_write_bit((phy_addr & 0x01) != 0);
	206
	207	/* REGAD FWX^AhXª1ÔÌêA00001bðCgiMSB©çCgjB */
	208	phy_write_bit((reg_addr & 0x10) != 0);
	209	phy_write_bit((reg_addr & 0x08) != 0);
	210	phy_write_bit((reg_addr & 0x04) != 0);
	211	phy_write_bit((reg_addr & 0x02) != 0);
	212	phy_write_bit((reg_addr & 0x01) != 0);
	213
	214	/* TA FMII/RMIIC^tF[XãÅf[^ÌM³ðØèÖ¦éÔ */
	215	/* uoXðúviZ0Æ\Ljðs¤ */
	216	phy_release_bus();
	217
	218	/* DATA F16rbgÌf[^BMSB©ç[h */
	219	for (bit = 0x8000; bit != 0; bit >>= 1) {
	220	if(phy_read_bit())
	221	result \|= bit;
	222	}
	223
	224	/* IDLE FÌMIIÇtH[}bgüÍÜÅÌÒ@Ô */
	225	/* ·ÅÉTAÉoXðúÏÝÅ è§äsv */
	226	phy_release_bus();
	227
	228	return result;
	229	}
	230
	231	void phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_data)
	232	{
	233	int i;
	234	uint16_t bit;
	235
	236	/* PRE F32ÂÌA±µ½1b */
	237	for (i = 0; i < 32; i++)
	238	phy_write_bit(true);
	239
	240	/* ST Ft[Ìæªð¦·01bÌCg */
	241	phy_write_bit(false);
	242	phy_write_bit(true);
	243
	244	/* OP FANZXíÊð¦·R[hÌCg */
	245	phy_write_bit(false);
	246	phy_write_bit(true);
	247
	248	/* PHYAD FPHY-LSIÌAhXª1ÔÌêA00001bðCgiMSB ©çCgjB */
	249	phy_write_bit((phy_addr & 0x10) != 0);
	250	phy_write_bit((phy_addr & 0x08) != 0);
	251	phy_write_bit((phy_addr & 0x04) != 0);
	252	phy_write_bit((phy_addr & 0x02) != 0);
	253	phy_write_bit((phy_addr & 0x01) != 0);
	254
	255	/* REGAD FWX^AhXª1ÔÌêA00001bðCgiMSB©çCgjB */
	256	phy_write_bit((reg_addr & 0x10) != 0);
	257	phy_write_bit((reg_addr & 0x08) != 0);
	258	phy_write_bit((reg_addr & 0x04) != 0);
	259	phy_write_bit((reg_addr & 0x02) != 0);
	260	phy_write_bit((reg_addr & 0x01) != 0);
	261
	262	/* TA FMII/RMIIC^tF[XãÅf[^ÌM³ðØèÖ¦éÔ */
	263	/* 10bðCg */
	264	phy_write_bit(true);
	265	phy_write_bit(false);
	266
	267	/* DATA F16rbgÌf[^BMSB©çCg */
	268	for (bit = 0x8000; bit != 0; bit >>= 1) {
	269	phy_write_bit((reg_data & bit) != 0);
	270	}
	271
	272	/* IDLE FÌMIIÇtH[}bgüÍÜÅÌÒ@Ô */
	273	/* uPÆoXðúviXÆ\Ljðs¤ */
	274	phy_single_rel_bus();
	275	}
	276
	277	#define ETHERC_PIR_WAIT 4
	278
	279	/*
	280	* 1 rbgf[^ÌCg
	281	*/
	282	static void phy_write_bit(bool_t bit)
	283	{
	284	int i;
	285	uint32_t data = bit ? ETHERC_PIR_MDO : 0;
	286
	287	/* PHYC^tF[XWX^ÖÌCg */
	288	sil_wrw_mem(ETHERC_PIR, data \| ETHERC_PIR_MMD \| 0/ETHERC_PIR_MDC/);
	289
	290	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	291
	292	/* PHYC^tF[XWX^ÖÌCg */
	293	sil_wrw_mem(ETHERC_PIR, data \| ETHERC_PIR_MMD \| ETHERC_PIR_MDC);
	294
	295	for(i = 2 * ETHERC_PIR_WAIT; i > 0; i--);
	296
	297	/* PHYC^tF[XWX^ÖÌCg */
	298	sil_wrw_mem(ETHERC_PIR, data \| ETHERC_PIR_MMD \| 0/ETHERC_PIR_MDC/);
	299
	300	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	301	}
	302
	303	/*
	304	* oXðú
	305	*/
	306	static void phy_release_bus()
	307	{
	308	int i;
	309
	310	/* PHYC^tF[XWX^ÖÌCg */
	311	sil_wrw_mem(ETHERC_PIR, 0/ETHERC_PIR_MMD/ \| 0/ETHERC_PIR_MDC/);
	312
	313	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	314
	315	/* PHYC^tF[XWX^ÖÌCg */
	316	sil_wrw_mem(ETHERC_PIR, 0/ETHERC_PIR_MMD/ \| ETHERC_PIR_MDC);
	317
	318	for(i = 2 * ETHERC_PIR_WAIT; i > 0; i--);
	319
	320	/* PHYC^tF[XWX^ÖÌCg */
	321	sil_wrw_mem(ETHERC_PIR, 0/ETHERC_PIR_MMD/ \| 0/ETHERC_PIR_MDC/);
	322
	323	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	324	}
	325
	326	/*
	327	* 1 rbgf[^Ì[h
	328	*/
	329	static bool_t phy_read_bit()
	330	{
	331	bool_t bit;
	332	int i;
	333
	334	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	335
	336	/* PHYC^tF[XWX^ÖÌCg */
	337	sil_wrw_mem(ETHERC_PIR, 0/ETHERC_PIR_MMD/ \| ETHERC_PIR_MDC);
	338
	339	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	340
	341	/* PHYC^tF[XWX^ÖÌCg */
	342	bit = (sil_rew_mem(ETHERC_PIR) & ETHERC_PIR_MDI) != 0;
	343
	344	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	345
	346	/* PHYC^tF[XWX^ÖÌCg */
	347	sil_wrw_mem(ETHERC_PIR, 0/ETHERC_PIR_MMD/ \| 0/ETHERC_PIR_MDC/);
	348
	349	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	350
	351	return bit;
	352	}
	353
	354	/*
	355	* PÆoXðú
	356	*/
	357	static void phy_single_rel_bus()
	358	{
	359	int i;
	360
	361	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	362
	363	/* PHYC^tF[XWX^ÖÌCg */
	364	sil_wrw_mem(ETHERC_PIR, ETHERC_PIR_MMD \| ETHERC_PIR_MDC);
	365
	366	for(i = 2 * ETHERC_PIR_WAIT; i > 0; i--);
	367
	368	/* PHYC^tF[XWX^ÖÌCg */
	369	sil_wrw_mem(ETHERC_PIR, 0/ETHERC_PIR_MMD/ \| 0/ETHERC_PIR_MDC/);
	370
	371	for(i = ETHERC_PIR_WAIT; i > 0; i--);
	372	}

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