source: uKadecot/trunk/ssp/target/grsakura_ccrx/target_support.c@ 101

Last change on this file since 101 was 101, checked in by coas-nagasima, 9 years ago

TOPPERS/uKadecotのソースコードを追加

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  • Property svn:keywords set to Id
  • Property svn:mime-type set to text/plain
File size: 2.3 KB
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1/*-----------------------------------------------------------------------------
2 * TOPPERS/SSP Windows Debug Environment
3 * Copyright (C) 2014 Cores Co., Ltd. Japan
4 *-----------------------------------------------------------------------------
5 * $Id: target_support.c 101 2015-06-02 15:37:23Z coas-nagasima $
6 */
7
8/*
9 * ƒ^[ƒQƒbƒgƒVƒXƒeƒ€ˆË‘¶ƒ‚ƒWƒ…
10[ƒ‹iAP-RX62N-0A—pj
11 */
12
13#include "kernel_impl.h"
14#include <sil.h>
15
16void hardware_init_hook()
17{
18 /*
19 * “®ìƒ‚[ƒhÝ’è
20 *
21 * “®ìƒ‚[ƒh‚̓{[ƒhã‚Ì’[Žq‚É‚æ‚Á‚ÄŒˆ’肳‚ê‚邽‚ß,
22 * ‚±‚±‚Å‚Í“Á•ÊÝ’肵‚È‚¢.
23 * ‚½‚¾‚µ, ƒŠƒgƒ‹ƒGƒ“ƒfƒBƒAƒ“/ƒVƒ“ƒOƒ‹ƒ`ƒbƒvƒ‚[ƒh
24 * ‚Å‚ ‚邱‚Æ‚ð‘O’ñ‚Æ‚·‚é.
25 *
26 * ‚Ü‚½ƒŠƒZƒbƒgŒã, “à‘ ROMF—LŒø, “à‘ RAMF—LŒø, ŠO•”ƒoƒXF–³Œø
27 * ‚Å‚ ‚é.
28 */
29
30 /*
31 * ƒNƒƒbƒNÝ’è
32 *
33 * “ü—́F12MHz
34 * PLL‰ñ˜HF12 x 8 = 96MHz
35 * ƒVƒXƒeƒ€ƒNƒƒbƒNF96MHz
36 * Žü•Óƒ‚ƒWƒ…
37[ƒ‹ƒNƒƒbƒNF48MHz
38 * ŠO•”ƒoƒXƒNƒƒbƒNF96MHz
39 * ‚Æ‚·‚é.
40 */
41 sil_wrb_mem(PORT3_PDR_ADDR,
42 sil_reb_mem(PORT3_PDR_ADDR) & ~PORT_PDR_B6_BIT);
43 sil_wrb_mem(PORT3_PDR_ADDR,
44 sil_reb_mem(PORT3_PDR_ADDR) & ~PORT_PDR_B7_BIT);
45 sil_wrb_mem(PORT3_PMR_ADDR,
46 sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PDR_B6_BIT);
47 sil_wrb_mem(PORT3_PMR_ADDR,
48 sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PDR_B7_BIT);
49
50 sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xa503);
51
52 /* ƒƒCƒ“ƒNƒƒbƒN”­UŠí‹­§”­U */
53 while((sil_reb_mem(SYSTEM_MOFCR_ADDR) & SYSTEM_MOFCR_MOFXIN) == 0)
54 sil_wrb_mem(SYSTEM_MOFCR_ADDR,
55 sil_reb_mem(SYSTEM_MOFCR_ADDR) | SYSTEM_MOFCR_MOFXIN);
56
57 /* ƒƒCƒ“ƒNƒƒbƒN”­UŠí“®ì */
58 while((sil_reb_mem(SYSTEM_MOSCCR_ADDR) & SYSTEM_MOSCCR_MOSTP) != 0)
59 sil_wrb_mem(SYSTEM_MOSCCR_ADDR,
60 sil_reb_mem(SYSTEM_MOSCCR_ADDR) & ~SYSTEM_MOSCCR_MOSTP);
61
62 sil_wrh_mem(SYSTEM_PLLCR_ADDR,
63 (sil_reh_mem(SYSTEM_PLLCR_ADDR) & ~SYSTEM_PLLCR_STC_MASK)
64 | (0x0f << SYSTEM_PLLCR_STC_OFFSET));
65
66 sil_wrb_mem(SYSTEM_PLLCR2_ADDR,
67 sil_reb_mem(SYSTEM_PLLCR2_ADDR) & ~SYSTEM_PLLCR2_PLLEN);
68
69 sil_wrw_mem(SYSTEM_SCKCR_ADDR, 0x21021211);
70
71 /* PLL‰ñ˜H‘I‘ð */
72 sil_wrh_mem(SYSTEM_SCKCR3_ADDR,
73 (sil_reh_mem(SYSTEM_SCKCR3_ADDR) & ~SYSTEM_SCKCR3_CKSEL_MASK)
74 | (4 << SYSTEM_SCKCR3_CKSEL_OFFSET));
75
76 /*
77 * ƒ‚ƒWƒ…
78[ƒ‹ƒXƒgƒbƒv
79 *
80 * ƒŠƒZƒbƒgŒã, “®ì‚µ‚Ä‚¢‚é“à‘ Žü•Óƒ‚ƒWƒ…
81[ƒ‹‚ÍDMAC, DTC,
82 * “à‘ RAM‚Ì‚Ý‚Å‚ ‚é.
83 * ‚»‚êˆÈŠO‚Ì“à‘ Žü•Óƒ‚ƒWƒ…
84[ƒ‹‚ÉŠÖ‚µ‚Ä‚ÍŽg—p‚·‚鑤‚Å
85 * Ý’è‚·‚邱‚Æ.
86 */
87 sil_wrh_mem(SYSTEM_PRCR_ADDR, 0xa500);
88}
89
90void software_init_hook()
91{
92 /*
93 * –{ƒRƒ“ƒpƒCƒ‰‚Å‚Íweak definition‚Ì‹@”\‚ª–³‚¢‚½‚ß,
94 * “Á‚É•K—v‚ȏˆ—‚Í‚È‚¢‚ª, •K‚¸ŒÄ‚яo‚·‚±‚Æ‚Æ‚·‚é.
95 */
96}
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