source: uKadecot/trunk/ssp/pdic/rx600/rx630_uart.c@ 101

Last change on this file since 101 was 101, checked in by coas-nagasima, 8 years ago

TOPPERS/uKadecotのソースコードを追加

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1/*
2 * TOPPERS/SSP Kernel
3 * Smallest Set Profile Kernel
4 *
5 * Copyright (C) 2008-2010 by Witz Corporation, JAPAN
6 * Copyright (C) 2013 by Mitsuhiro Matsuura
7 *
8 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì(1)`(4)‚ÌðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒF
9 * ƒAi–{ƒ\ƒtƒgƒEƒFƒA‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü
10 * •ÏEÄ”z•ziˆÈ‰ºC—˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
11 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
12 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
13 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
14 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
15 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
16ƒƒ“ƒgi—˜—p
17 * ŽÒƒ}ƒjƒ…
18ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
19 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
20 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
21 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
22 * ‚ƁD
23 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
24ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
25ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
26 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
27 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
28 * •ñ‚·‚邱‚ƁD
29 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
30 * ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
31 * ‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚̃†[ƒU‚Ü‚½‚̓Gƒ“ƒhƒ†[ƒU‚©‚ç‚Ì‚¢‚©‚Ȃ闝
32 * —R‚ÉŠî‚­¿‹‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð
33 * –Ɛӂ·‚邱‚ƁD
34 *
35 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
36 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC“Á’è‚ÌŽg—p–Ú“I
37 * ‚ɑ΂·‚é“K‡«‚àŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒF
38 * ƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»
39 * ‚̐ӔC‚𕉂í‚È‚¢D
40 *
41 */
42
43
44/*
45 * UART—p ŠÈˆÕSIOƒhƒ‰ƒCƒo
46 */
47
48#include <sil.h>
49#include <kernel.h>
50#include <t_syslog.h>
51#include "target_syssvc.h"
52#include "rx630_uart.h"
53
54/* ƒVƒŠƒAƒ‹ƒ‚[ƒhƒŒƒWƒXƒ^iSMR) */
55#define CKS UINT_C(0x03)
56#define STOP UINT_C(0x08)
57#define PM UINT_C(0x10)
58#define PE UINT_C(0x20)
59#define CHR UINT_C(0x40)
60#define CM UINT_C(0x80)
61#define ASYNC_7BIT UINT_C(0x00)
62#define ASYNC_8BIT UINT_C(0x40)
63
64/* ƒVƒŠƒAƒ‹ƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^iSCR) */
65#define CKE UINT_C(0x03)
66#define TEIE UINT_C(0x04)
67#define RE UINT_C(0x10)
68#define TE UINT_C(0x20)
69#define RIE UINT_C(0x40)
70#define TIE UINT_C(0x80)
71
72/* ƒVƒŠƒAƒ‹ƒXƒe[ƒ^ƒXƒŒƒWƒXƒ^iSSRj */
73#define TEND UINT_C(0x04)
74#define PER UINT_C(0x08)
75#define FER UINT_C(0x10)
76#define ORER UINT_C(0x20)
77
78/* ƒVƒŠƒAƒ‹Šg’£ƒ‚[ƒhƒŒƒWƒXƒ^iSEMR) */
79#define ACS0 UINT_C(0x01)
80#define ABCS UINT_C(0x10)
81
82#define SCI_SCR_FLG_ENABLE (RE | TE)
83#define SCI_SMR_FLG_ENABLE (STOP | PM | PE | CHR | CM)
84
85/*
86 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‰Šú‰»ƒuƒƒbƒN‚Ì’è‹`
87 */
88typedef struct sio_port_initialization_block {
89 volatile uint8_t *ctlreg; /* ƒVƒŠƒAƒ‹ƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^iSCR) */
90 volatile uint8_t *modereg; /* ƒVƒŠƒAƒ‹ƒ‚[ƒhƒŒƒWƒXƒ^iSMR) */
91 volatile uint8_t *extmodereg; /* ƒVƒŠƒAƒ‹Šg’£ƒ‚[ƒhƒŒƒWƒXƒ^iSEMR) */
92 volatile uint8_t *statusreg; /* ƒVƒŠƒAƒ‹ƒXƒe[ƒ^ƒXƒŒƒWƒXƒ^iSSRj */
93 volatile uint8_t *tdreg; /* ƒgƒ‰ƒ“ƒXƒ~ƒbƒgƒf[ƒ^ƒŒƒWƒXƒ^iTDR)*/
94 volatile uint8_t *rdreg; /* ƒŒƒV[ƒuƒf[ƒ^ƒŒƒWƒXƒ^iRDR) */
95 volatile uint8_t *bitratereg; /* ƒrƒbƒgƒŒ[ƒgƒŒƒWƒXƒ^iBRR) */
96 volatile uint32_t *mstpcrreg; /* ƒ‚ƒWƒ…
97[ƒ‹ƒXƒgƒbƒvƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^iMSTPCRj */
98 volatile uint8_t *ssrreg; /* ƒXƒe[ƒ^ƒXƒŒƒWƒXƒ^ */
99 volatile uint8_t *rxiirreg; /* RXI—pŠ„ž‚Ý—v‹ƒŒƒWƒXƒ^ */
100 uint8_t tx_intno; /* ‘—Miƒf[ƒ^ƒGƒ“ƒvƒeƒBjŠ„‚荞‚ݔԍ† */
101 uint8_t rx_intno; /* ŽóMiƒf[ƒ^ƒtƒ‹jŠ„‚荞‚ݔԍ† */
102 uint8_t te_intno; /* ‘—MiI—¹jŠ„‚荞‚ݔԍ† */
103 uint8_t sci_no; /* SCI‚̔ԍ†(SCI0`SCI6) */
104 uint32_t mstpcr_offset; /* MSTPCR‚̑Ήž‚·‚éƒrƒbƒgƒIƒtƒZƒbƒg */
105} SIOPINIB;
106
107/*
108 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒgŠÇ—ƒuƒƒbƒN‚Ì’è‹`
109 */
110struct sio_port_control_block {
111 const SIOPINIB *p_siopinib; /* ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‰Šú‰»ƒuƒƒbƒN */
112 intptr_t exinf; /* Šg’£î•ñ */
113 bool_t openflag; /* ƒI[ƒvƒ“Ï‚݃tƒ‰ƒO */
114 bool_t sendflag; /* ‘—MŠ„ž‚݃Cƒl[ƒuƒ‹ƒtƒ‰ƒO */
115 bool_t getready; /* •¶Žš‚ðŽóM‚µ‚½ó‘Ô */
116 bool_t putready; /* •¶Žš‚𑗐M‚Å‚«‚éó‘Ô */
117 bool_t is_initialized; /* ƒfƒoƒCƒX‰Šú‰»Ï‚݃tƒ‰ƒO */
118};
119
120/*
121 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒgŠÇ—ƒuƒƒbƒN‚̃GƒŠƒA
122 */
123static SIOPCB siopcb_table[TNUM_SIOP];
124
125/* ƒŒƒWƒXƒ^ƒe[ƒuƒ‹ */
126static const SIOPINIB siopinib_table[TNUM_SIOP] =
127{
128 {
129 (volatile uint8_t *)SCI0_SCR_ADDR,
130 (volatile uint8_t *)SCI0_SMR_ADDR,
131 (volatile uint8_t *)SCI0_SEMR_ADDR,
132 (volatile uint8_t *)SCI0_SSR_ADDR,
133 (volatile uint8_t *)SCI0_TDR_ADDR,
134 (volatile uint8_t *)SCI0_RDR_ADDR,
135 (volatile uint8_t *)SCI0_BRR_ADDR,
136 (volatile uint32_t *)SYSTEM_MSTPCRB_ADDR,
137 (volatile uint8_t *)SCI0_SSR_ADDR,
138 (volatile uint8_t *)ICU_IR215_ADDR,
139 INT_SCI0_TXI,
140 INT_SCI0_RXI,
141 INT_SCI0_TEI,
142 0,
143 SYSTEM_MSTPCRB_MSTPB31_BIT,
144 } , /* UART0 */
145#if TNUM_SIOP > 1
146 {
147 (volatile uint8_t *)SCI2_SCR_ADDR,
148 (volatile uint8_t *)SCI2_SMR_ADDR,
149 (volatile uint8_t *)SCI2_SEMR_ADDR,
150 (volatile uint8_t *)SCI2_SSR_ADDR,
151 (volatile uint8_t *)SCI2_TDR_ADDR,
152 (volatile uint8_t *)SCI2_RDR_ADDR,
153 (volatile uint8_t *)SCI2_BRR_ADDR,
154 (volatile uint32_t *)SYSTEM_MSTPCRB_ADDR,
155 (volatile uint8_t *)SCI2_SSR_ADDR,
156 (volatile uint8_t *)ICU_IR223_ADDR,
157 INT_SCI2_TXI,
158 INT_SCI2_RXI,
159 INT_SCI2_TEI,
160 2,
161 SYSTEM_MSTPCRB_MSTPB29_BIT,
162 } , /* UART2 */
163#endif
164};
165
166/*
167 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒgID‚©‚çŠÇ—ƒuƒƒbƒN‚ðŽæ‚èo‚·‚½‚߂̃}ƒNƒ
168 */
169#define INDEX_SIOP(siopid) ((uint_t)((siopid) - 1))
170#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
171#define get_siopinib(siopid) (&(siopinib_table[INDEX_SIOP(siopid)]))
172
173
174/*
175 * SIOƒhƒ‰ƒCƒo‚̃VƒŠƒAƒ‹ƒ‚[ƒhƒŒƒWƒXƒ^(SMR)
176 */
177static void
178rx630_uart_setmode(const SIOPINIB *p_siopinib, uint8_t bitrate, uint8_t clksrc)
179{
180 volatile uint8_t i;
181
182 /*
183 * SCIƒhƒ‰ƒCƒo‚̏‰Šú‰»ƒ‹[ƒ`ƒ“
184 */
185
186 /*
187 * Š„‚荞‚Ý—v‹æƒŒƒWƒXƒ^‚̐ݒè(ISELRi)
188 *
189 * ƒŠƒZƒbƒg’l‚Æ“¯‚¶’l‚ðÝ’è‚·‚邱‚ƂɂȂ邽‚ß,
190 * ˆ—‚͏ȗª‚·‚é.
191 */
192
193 /*
194 * ƒ‚ƒWƒ…
195[ƒ‹ƒXƒgƒbƒv‹@”\‚̐ݒè
196 */
197 sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* ‘ž‚Ý‹–‰Â */
198 sil_wrw_mem(p_siopinib->mstpcrreg,
199 sil_rew_mem(p_siopinib->mstpcrreg) & ~p_siopinib->mstpcr_offset);
200 sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* ‘ž‚Ý‹ÖŽ~ */
201
202 /* ‘—ŽóM‹ÖŽ~, SCKn’[Žq‚Í“üo—̓|[ƒg‚Æ‚µ‚ÄŽg—p */
203 sil_wrb_mem(p_siopinib->ctlreg, 0x00U);
204
205 /* ƒNƒƒbƒN‘I‘ðƒrƒbƒg(SMR.CKS[1:0]ƒrƒbƒg‚ðÝ’è) */
206 sil_wrb_mem(p_siopinib->modereg,
207 sil_reb_mem(p_siopinib->modereg) | clksrc);
208
209 /* SMR‚É‘—M^ ŽóMƒtƒH[ƒ}ƒbƒg‚ðÝ’è) */
210 sil_wrb_mem(p_siopinib->modereg,
211 sil_reb_mem(p_siopinib->modereg) & (~SCI_SMR_FLG_ENABLE));
212
213 /* ƒrƒbƒgƒŒ[ƒg‚ðÝ’è */
214 sil_wrb_mem(p_siopinib->bitratereg, bitrate);
215
216 /* ƒrƒbƒgŠúŠÔ(Šî–{ƒNƒƒbƒN16ƒTƒCƒNƒ‹‚ÌŠúŠÔ‚ª1ƒrƒbƒgŠúŠÔ‚Æ‚È‚é) */
217 for(i = 0; i < 16; i++) { }
218
219 /* ‘—ŽóM‹–‰Â */
220 sil_wrb_mem(p_siopinib->ctlreg,
221 (sil_reb_mem(p_siopinib->ctlreg) | SCI_SCR_FLG_ENABLE));
222}
223
224
225/*
226 * SIOƒhƒ‰ƒCƒo‚̏‰Šú‰»ƒ‹[ƒ`ƒ“
227 */
228void
229rx630_uart_initialize(void)
230{
231 SIOPCB *p_siopcb;
232 uint_t i;
233
234 /*
235 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒgŠÇ—ƒuƒƒbƒN‚̏‰Šú‰»
236 */
237 for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++){
238 p_siopcb->p_siopinib = &(siopinib_table[i]);
239 p_siopcb->openflag = false;
240 p_siopcb->sendflag = false;
241 }
242}
243
244/*
245 * ƒJ[ƒlƒ‹‹N“®Žž‚̃oƒi[o—Í—p‚̏‰Šú‰»
246 */
247void
248rx630_uart_init(ID siopid, uint8_t bitrate, uint8_t clksrc)
249{
250 SIOPCB *p_siopcb = get_siopcb(siopid);
251 const SIOPINIB *p_siopinib = get_siopinib(siopid);
252 /* ‚±‚ÌŽž“_‚ł́Ap_siopcb->p_siopinib‚͏‰Šú‰»‚³‚ê‚Ä‚¢‚È‚¢ */
253
254 /* “ñd‰Šú‰»‚Ì–hŽ~ */
255 p_siopcb->is_initialized = true;
256
257 /* ƒn[ƒhƒEƒFƒA‚̏‰Šú‰»ˆ—‚Æ‘—M‹–‰Â */
258 rx630_uart_setmode(p_siopinib , bitrate, clksrc);
259 sil_wrb_mem(p_siopinib->ctlreg,
260 (uint8_t)(sil_reb_mem(p_siopinib->ctlreg) | TE));
261}
262
263/*
264 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‚ւ̃|[ƒŠƒ“ƒO‚ł̏o—Í
265 */
266void
267rx630_uart_pol_putc(char c, ID siopid)
268{
269 const SIOPINIB *p_siopinib;
270
271 p_siopinib = get_siopinib(siopid);
272
273 /*
274 * ‘—MƒŒƒWƒXƒ^‚ª‹ó‚É‚È‚é‚Ü‚Å‘Ò‚Â
275 */
276 while((sil_reb_mem(p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) == 0U);
277
278 sil_wrb_mem(p_siopinib->tdreg, (uint8_t)c);
279}
280
281/*
282 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‚̃I[ƒvƒ“
283 */
284SIOPCB *
285rx630_uart_opn_por
286 (ID siopid, intptr_t exinf, uint8_t bitrate, uint8_t clksrc)
287{
288 SIOPCB *p_siopcb;
289 const SIOPINIB *p_siopinib;
290
291 p_siopcb = get_siopcb(siopid);
292 p_siopinib = p_siopcb->p_siopinib;
293
294 /*
295 * ƒn[ƒhƒEƒFƒA‚̏‰Šú‰»
296 *
297 * Šù‚ɏ‰Šú‰»‚µ‚Ä‚¢‚éê‡‚Í, “ñd‚ɏ‰Šú‰»‚µ‚È‚¢.
298 */
299 if(!(p_siopcb->is_initialized)){
300 rx630_uart_setmode(p_siopinib, bitrate, clksrc);
301 p_siopcb->is_initialized = true;
302 }
303
304 p_siopcb->exinf = exinf;
305 p_siopcb->getready = p_siopcb->putready = false;
306 p_siopcb->openflag = true;
307
308 return (p_siopcb);
309}
310
311/*
312 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‚̃Nƒ[ƒY
313 */
314void
315rx630_uart_cls_por(SIOPCB *p_siopcb)
316{
317 /*
318 * UART’âŽ~
319 */
320 sil_wrh_mem(p_siopcb->p_siopinib->ctlreg, 0x00U);
321 p_siopcb->openflag = false;
322 p_siopcb->is_initialized = false;
323}
324
325/*
326 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‚Ö‚Ì•¶Žš‘—M
327 */
328bool_t
329rx630_uart_snd_chr(SIOPCB *p_siopcb, char c)
330{
331 bool_t ercd = false;
332
333 if((sil_reb_mem(
334 (uint8_t *)p_siopcb->p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) != 0){
335 sil_wrb_mem(p_siopcb->p_siopinib->tdreg, (uint8_t)c);
336 ercd = true;
337 }
338
339 return ercd;
340}
341
342/*
343 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‚©‚ç‚Ì•¶ŽšŽóM
344 */
345int_t
346rx630_uart_rcv_chr(SIOPCB *p_siopcb)
347{
348 int_t c = -1;
349
350 /*
351 * ŽóMƒtƒ‰ƒO‚ªON‚Ì‚Æ‚«‚Ì‚ÝŽóMƒoƒbƒtƒ@‚©‚當Žš‚ðŽæ“¾‚·‚é.
352 * ‚±‚ê‚Í, ƒ|[ƒŠƒ“ƒOŽóM‚ɑΉž‚·‚邽‚ß‚Å‚ ‚é.
353 * ‚µ‚©‚µ, RX600ƒVƒŠ[ƒY‚Å‚ÍŽóMƒtƒ‰ƒO‚ª‚È‚¢‚±‚Æ, ƒVƒXƒeƒ€ƒT[ƒrƒX
354 * ‚Å‚ÍŽóMŠ„ž‚Ý‚Ì’†‚©‚炵‚©ƒf[ƒ^‚ðŽóM‚µ‚É—ˆ‚È‚¢‚±‚Æ‚©‚ç, í‚É
355 * ŽóMƒoƒbƒtƒ@‚©‚當Žš‚ðŽæ“¾‚·‚é.
356 */
357 c = (int)(sil_reb_mem(p_siopcb->p_siopinib->rdreg));
358
359 return c;
360}
361
362/*
363 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‚©‚ç‚̃R[ƒ‹ƒoƒbƒN‚Ì‹–‰Â
364 */
365void
366rx630_uart_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
367{
368 switch (cbrtn) {
369 case SIO_RDY_SND:
370 sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
371 (sil_reb_mem(p_siopcb->p_siopinib->ctlreg) | SCI_SCR_TEIE_BIT));
372 break;
373 case SIO_RDY_RCV:
374 sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
375 (sil_reb_mem(p_siopcb->p_siopinib->ctlreg) | SCI_SCR_RIE_BIT));
376 break;
377 default:
378 assert(1);
379 break;
380 }
381}
382
383/*
384 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒg‚©‚ç‚̃R[ƒ‹ƒoƒbƒN‚Ì‹ÖŽ~
385 */
386void
387rx630_uart_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
388{
389 switch (cbrtn) {
390 case SIO_RDY_SND:
391 sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
392 (sil_reb_mem(p_siopcb->p_siopinib->ctlreg) & (~SCI_SCR_TEIE_BIT)));
393 break;
394 case SIO_RDY_RCV:
395 sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
396 (sil_reb_mem(p_siopcb->p_siopinib->ctlreg) & (~SCI_SCR_RIE_BIT)));
397 break;
398 default:
399 assert(1);
400 break;
401 }
402}
403
404/*
405 * SIO‚ÌŠ„ž‚݃T[ƒrƒXƒ‹[ƒ`ƒ“
406 */
407void
408rx630_uart_tx_isr(ID siopid)
409{
410 SIOPCB *p_siopcb = get_siopcb(siopid);
411
412 if((sil_reb_mem(
413 (void *)p_siopcb->p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) != 0U){
414 /*
415 * ‘—M‰Â”\ƒR[ƒ‹ƒoƒbƒNƒ‹[ƒ`ƒ“‚ðŒÄ‚яo‚·D
416 */
417 rx630_uart_irdy_snd(p_siopcb->exinf);
418 }
419}
420
421void
422rx630_uart_rx_isr(ID siopid)
423{
424 SIOPCB *p_siopcb = get_siopcb(siopid);
425
426 /*
427 * ŽóMƒtƒ‰ƒO‚ªON‚Ì‚Æ‚«‚Ì‚ÝŽóM’Ê’mƒR[ƒ‹ƒoƒbƒNƒ‹[ƒ`ƒ“‚ðŒÄ‚яo‚·.
428 * ‚µ‚©‚µ, RX600ƒVƒŠ[ƒY‚Å‚ÍŽóMƒtƒ‰ƒO‚ª‚È‚¢‚½‚ß, í‚ÉŽóM’Ê’m
429 * ƒR[ƒ‹ƒoƒbƒNƒ‹[ƒ`ƒ“‚ðŒÄ‚яo‚·.
430 * ‚±‚±‚Å‚ÍŽóMŠ„ž‚Ý‚Ì”­¶‚ðM‚¶‚é.
431 */
432 /*
433 * ŽóM’Ê’mƒR[ƒ‹ƒoƒbƒNƒ‹[ƒ`ƒ“‚ðŒÄ‚яo‚·D
434 */
435 rx630_uart_irdy_rcv(p_siopcb->exinf);
436}
437
438
439/*
440 * ƒ|[ƒg”ԍ†‚©‚çŠÇ—ƒuƒƒbƒN‚̐擪”Ô’n‚Ö‚Ì•ÏŠ·
441 */
442SIOPCB *
443rx630_uart_get_siopcb(ID siopid) {
444 SIOPCB *p_siopcb = get_siopcb(siopid);
445 return(p_siopcb);
446}
447
448/*
449 * ŠÇ—ƒuƒƒbƒN‚̐擪”Ô’n‚©‚çŽóMŠ„ž‚ݔԍ†‚Ö‚Ì•ÏŠ·
450 */
451INTNO
452rx630_uart_intno_rx(SIOPCB *p_siopcb) {
453 INTNO intno = p_siopcb->p_siopinib->rx_intno;
454 return(intno);
455}
456
457/*
458 * ŠÇ—ƒuƒƒbƒN‚̐擪”Ô’n‚©‚ç‘—MŠ„ž‚ݔԍ†‚Ö‚Ì•ÏŠ·
459 */
460INTNO
461rx630_uart_intno_tx(SIOPCB *p_siopcb) {
462 INTNO intno = p_siopcb->p_siopinib->te_intno;
463 return(intno);
464}
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