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rx630_uart.c@ 101

Last change on this file since 101 was 101, checked in by coas-nagasima, 9 years ago
TOPPERS/uKadecotのソースコードを追加
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File size: 11.6 KB

Rev	Line
[101]	1	/*
	2	* TOPPERS/SSP Kernel
	3	* Smallest Set Profile Kernel
	4	*
	5	* Copyright (C) 2008-2010 by Witz Corporation, JAPAN
	6	* Copyright (C) 2013 by Mitsuhiro Matsuura
	7	*
	8	* ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
	9	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
	10	* ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
	11	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
	12	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
	13	* XR[hÉÜÜêÄ¢é±ÆD
	14	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
	15	* pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
	16	gip
	17	* Ò}j
	18	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
	19	* Ì³ÛØKèðfÚ·é±ÆD
	20	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
	21	* pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
	22	* ÆD
	23	* (a) ÄzzÉº¤hL
	24	gipÒ}j
	25	AÈÇjÉCãLÌ
	26	* ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
	27	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
	28	* ñ·é±ÆD
	29	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
	30	* Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
	31	* Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
	32	* RÉîÃ¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
	33	* ÆÓ·é±ÆD
	34	*
	35	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
	36	* æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
	37	* ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
	38	* AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
	39	* ÌÓCðíÈ¢D
	40	*
	41	*/
	42
	43
	44	/*
	45	* UARTp ÈÕSIOhCo
	46	*/
	47
	48	#include <sil.h>
	49	#include <kernel.h>
	50	#include <t_syslog.h>
	51	#include "target_syssvc.h"
	52	#include "rx630_uart.h"
	53
	54	/* VA[hWX^iSMR) */
	55	#define CKS UINT_C(0x03)
	56	#define STOP UINT_C(0x08)
	57	#define PM UINT_C(0x10)
	58	#define PE UINT_C(0x20)
	59	#define CHR UINT_C(0x40)
	60	#define CM UINT_C(0x80)
	61	#define ASYNC_7BIT UINT_C(0x00)
	62	#define ASYNC_8BIT UINT_C(0x40)
	63
	64	/* VARg[WX^iSCR) */
	65	#define CKE UINT_C(0x03)
	66	#define TEIE UINT_C(0x04)
	67	#define RE UINT_C(0x10)
	68	#define TE UINT_C(0x20)
	69	#define RIE UINT_C(0x40)
	70	#define TIE UINT_C(0x80)
	71
	72	/* VAXe[^XWX^iSSRj */
	73	#define TEND UINT_C(0x04)
	74	#define PER UINT_C(0x08)
	75	#define FER UINT_C(0x10)
	76	#define ORER UINT_C(0x20)
	77
	78	/* VAg£[hWX^iSEMR) */
	79	#define ACS0 UINT_C(0x01)
	80	#define ABCS UINT_C(0x10)
	81
	82	#define SCI_SCR_FLG_ENABLE (RE \| TE)
	83	#define SCI_SMR_FLG_ENABLE (STOP \| PM \| PE \| CHR \| CM)
	84
	85	/*
	86	* VAI/O\|[gú»ubNÌè`
	87	*/
	88	typedef struct sio_port_initialization_block {
	89	volatile uint8_t ctlreg; / VARg[WX^iSCR) */
	90	volatile uint8_t modereg; / VA[hWX^iSMR) */
	91	volatile uint8_t extmodereg; / VAg£[hWX^iSEMR) */
	92	volatile uint8_t statusreg; / VAXe[^XWX^iSSRj */
	93	volatile uint8_t tdreg; / gX~bgf[^WX^iTDR)*/
	94	volatile uint8_t rdreg; / V[uf[^WX^iRDR) */
	95	volatile uint8_t bitratereg; / rbg[gWX^iBRR) */
	96	volatile uint32_t mstpcrreg; / W
	97	[XgbvRg[WX^iMSTPCRj */
	98	volatile uint8_t ssrreg; / Xe[^XWX^ */
	99	volatile uint8_t rxiirreg; / RXIpÝvWX^ */
	100	uint8_t tx_intno; /* Mif[^GveBjèÝÔ */
	101	uint8_t rx_intno; /* óMif[^tjèÝÔ */
	102	uint8_t te_intno; /* MiI¹jèÝÔ */
	103	uint8_t sci_no; /* SCIÌÔ(SCI0`SCI6) */
	104	uint32_t mstpcr_offset; /* MSTPCRÌÎ·érbgItZbg */
	105	} SIOPINIB;
	106
	107	/*
	108	* VAI/O\|[gÇubNÌè`
	109	*/
	110	struct sio_port_control_block {
	111	const SIOPINIB p_siopinib; / VAI/O\|[gú»ubN */
	112	intptr_t exinf; /* g£îñ */
	113	bool_t openflag; /* I[vÏÝtO */
	114	bool_t sendflag; /* MÝCl[utO */
	115	bool_t getready; /* ¶ðóMµ½óÔ */
	116	bool_t putready; /* ¶ðMÅ«éóÔ */
	117	bool_t is_initialized; /* foCXú»ÏÝtO */
	118	};
	119
	120	/*
	121	* VAI/O\|[gÇubNÌGA
	122	*/
	123	static SIOPCB siopcb_table[TNUM_SIOP];
	124
	125	/* WX^e[u */
	126	static const SIOPINIB siopinib_table[TNUM_SIOP] =
	127	{
	128	{
	129	(volatile uint8_t *)SCI0_SCR_ADDR,
	130	(volatile uint8_t *)SCI0_SMR_ADDR,
	131	(volatile uint8_t *)SCI0_SEMR_ADDR,
	132	(volatile uint8_t *)SCI0_SSR_ADDR,
	133	(volatile uint8_t *)SCI0_TDR_ADDR,
	134	(volatile uint8_t *)SCI0_RDR_ADDR,
	135	(volatile uint8_t *)SCI0_BRR_ADDR,
	136	(volatile uint32_t *)SYSTEM_MSTPCRB_ADDR,
	137	(volatile uint8_t *)SCI0_SSR_ADDR,
	138	(volatile uint8_t *)ICU_IR215_ADDR,
	139	INT_SCI0_TXI,
	140	INT_SCI0_RXI,
	141	INT_SCI0_TEI,
	142	0,
	143	SYSTEM_MSTPCRB_MSTPB31_BIT,
	144	} , /* UART0 */
	145	#if TNUM_SIOP > 1
	146	{
	147	(volatile uint8_t *)SCI2_SCR_ADDR,
	148	(volatile uint8_t *)SCI2_SMR_ADDR,
	149	(volatile uint8_t *)SCI2_SEMR_ADDR,
	150	(volatile uint8_t *)SCI2_SSR_ADDR,
	151	(volatile uint8_t *)SCI2_TDR_ADDR,
	152	(volatile uint8_t *)SCI2_RDR_ADDR,
	153	(volatile uint8_t *)SCI2_BRR_ADDR,
	154	(volatile uint32_t *)SYSTEM_MSTPCRB_ADDR,
	155	(volatile uint8_t *)SCI2_SSR_ADDR,
	156	(volatile uint8_t *)ICU_IR223_ADDR,
	157	INT_SCI2_TXI,
	158	INT_SCI2_RXI,
	159	INT_SCI2_TEI,
	160	2,
	161	SYSTEM_MSTPCRB_MSTPB29_BIT,
	162	} , /* UART2 */
	163	#endif
	164	};
	165
	166	/*
	167	* VAI/O\|[gID©çÇubNðæèo·½ßÌ}N
	168	*/
	169	#define INDEX_SIOP(siopid) ((uint_t)((siopid) - 1))
	170	#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
	171	#define get_siopinib(siopid) (&(siopinib_table[INDEX_SIOP(siopid)]))
	172
	173
	174	/*
	175	* SIOhCoÌVA[hWX^(SMR)
	176	*/
	177	static void
	178	rx630_uart_setmode(const SIOPINIB *p_siopinib, uint8_t bitrate, uint8_t clksrc)
	179	{
	180	volatile uint8_t i;
	181
	182	/*
	183	* SCIhCoÌú»[`
	184	*/
	185
	186	/*
	187	* èÝvæWX^ÌÝè(ISELRi)
	188	*
	189	* ZbglÆ¯¶lðÝè·é±ÆÉÈé½ß,
	190	* ÍÈª·é.
	191	*/
	192
	193	/*
	194	* W
	195	[Xgbv@\ÌÝè
	196	*/
	197	sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* ÝÂ */
	198	sil_wrw_mem(p_siopinib->mstpcrreg,
	199	sil_rew_mem(p_siopinib->mstpcrreg) & ~p_siopinib->mstpcr_offset);
	200	sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* ÝÖ~ */
	201
	202	/* óMÖ~, SCKn[qÍüoÍ\|[gÆµÄgp */
	203	sil_wrb_mem(p_siopinib->ctlreg, 0x00U);
	204
	205	/* NbNIðrbg(SMR.CKS[1:0]rbgðÝè) */
	206	sil_wrb_mem(p_siopinib->modereg,
	207	sil_reb_mem(p_siopinib->modereg) \| clksrc);
	208
	209	/* SMRÉM^ óMtH[}bgðÝè) */
	210	sil_wrb_mem(p_siopinib->modereg,
	211	sil_reb_mem(p_siopinib->modereg) & (~SCI_SMR_FLG_ENABLE));
	212
	213	/* rbg[gðÝè */
	214	sil_wrb_mem(p_siopinib->bitratereg, bitrate);
	215
	216	/* rbgúÔ(î{NbN16TCNÌúÔª1rbgúÔÆÈé) */
	217	for(i = 0; i < 16; i++) { }
	218
	219	/* óMÂ */
	220	sil_wrb_mem(p_siopinib->ctlreg,
	221	(sil_reb_mem(p_siopinib->ctlreg) \| SCI_SCR_FLG_ENABLE));
	222	}
	223
	224
	225	/*
	226	* SIOhCoÌú»[`
	227	*/
	228	void
	229	rx630_uart_initialize(void)
	230	{
	231	SIOPCB *p_siopcb;
	232	uint_t i;
	233
	234	/*
	235	* VAI/O\|[gÇubNÌú»
	236	*/
	237	for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++){
	238	p_siopcb->p_siopinib = &(siopinib_table[i]);
	239	p_siopcb->openflag = false;
	240	p_siopcb->sendflag = false;
	241	}
	242	}
	243
	244	/*
	245	* J[lN®Ìoi[oÍpÌú»
	246	*/
	247	void
	248	rx630_uart_init(ID siopid, uint8_t bitrate, uint8_t clksrc)
	249	{
	250	SIOPCB *p_siopcb = get_siopcb(siopid);
	251	const SIOPINIB *p_siopinib = get_siopinib(siopid);
	252	/* ±Ì_ÅÍAp_siopcb->p_siopinibÍú»³êÄ¢È¢ */
	253
	254	/* ñdú»Ìh~ */
	255	p_siopcb->is_initialized = true;
	256
	257	/* n[hEFAÌú»ÆMÂ */
	258	rx630_uart_setmode(p_siopinib , bitrate, clksrc);
	259	sil_wrb_mem(p_siopinib->ctlreg,
	260	(uint8_t)(sil_reb_mem(p_siopinib->ctlreg) \| TE));
	261	}
	262
	263	/*
	264	* VAI/O\|[gÖÌ\|[OÅÌoÍ
	265	*/
	266	void
	267	rx630_uart_pol_putc(char c, ID siopid)
	268	{
	269	const SIOPINIB *p_siopinib;
	270
	271	p_siopinib = get_siopinib(siopid);
	272
	273	/*
	274	* MWX^ªóÉÈéÜÅÒÂ
	275	*/
	276	while((sil_reb_mem(p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) == 0U);
	277
	278	sil_wrb_mem(p_siopinib->tdreg, (uint8_t)c);
	279	}
	280
	281	/*
	282	* VAI/O\|[gÌI[v
	283	*/
	284	SIOPCB *
	285	rx630_uart_opn_por
	286	(ID siopid, intptr_t exinf, uint8_t bitrate, uint8_t clksrc)
	287	{
	288	SIOPCB *p_siopcb;
	289	const SIOPINIB *p_siopinib;
	290
	291	p_siopcb = get_siopcb(siopid);
	292	p_siopinib = p_siopcb->p_siopinib;
	293
	294	/*
	295	* n[hEFAÌú»
	296	*
	297	* ùÉú»µÄ¢éêÍ, ñdÉú»µÈ¢.
	298	*/
	299	if(!(p_siopcb->is_initialized)){
	300	rx630_uart_setmode(p_siopinib, bitrate, clksrc);
	301	p_siopcb->is_initialized = true;
	302	}
	303
	304	p_siopcb->exinf = exinf;
	305	p_siopcb->getready = p_siopcb->putready = false;
	306	p_siopcb->openflag = true;
	307
	308	return (p_siopcb);
	309	}
	310
	311	/*
	312	* VAI/O\|[gÌN[Y
	313	*/
	314	void
	315	rx630_uart_cls_por(SIOPCB *p_siopcb)
	316	{
	317	/*
	318	* UARTâ~
	319	*/
	320	sil_wrh_mem(p_siopcb->p_siopinib->ctlreg, 0x00U);
	321	p_siopcb->openflag = false;
	322	p_siopcb->is_initialized = false;
	323	}
	324
	325	/*
	326	* VAI/O\|[gÖÌ¶M
	327	*/
	328	bool_t
	329	rx630_uart_snd_chr(SIOPCB *p_siopcb, char c)
	330	{
	331	bool_t ercd = false;
	332
	333	if((sil_reb_mem(
	334	(uint8_t *)p_siopcb->p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) != 0){
	335	sil_wrb_mem(p_siopcb->p_siopinib->tdreg, (uint8_t)c);
	336	ercd = true;
	337	}
	338
	339	return ercd;
	340	}
	341
	342	/*
	343	* VAI/O\|[g©çÌ¶óM
	344	*/
	345	int_t
	346	rx630_uart_rcv_chr(SIOPCB *p_siopcb)
	347	{
	348	int_t c = -1;
	349
	350	/*
	351	* óMtOªONÌÆ«ÌÝóMobt@©ç¶ðæ¾·é.
	352	* ±êÍ, \|[OóMÉÎ·é½ßÅ é.
	353	* µ©µ, RX600V[YÅÍóMtOªÈ¢±Æ, VXeT[rX
	354	* ÅÍóMÝÌ©çµ©f[^ðóMµÉÈ¢±Æ©ç, íÉ
	355	* óMobt@©ç¶ðæ¾·é.
	356	*/
	357	c = (int)(sil_reb_mem(p_siopcb->p_siopinib->rdreg));
	358
	359	return c;
	360	}
	361
	362	/*
	363	* VAI/O\|[g©çÌR[obNÌÂ
	364	*/
	365	void
	366	rx630_uart_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
	367	{
	368	switch (cbrtn) {
	369	case SIO_RDY_SND:
	370	sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
	371	(sil_reb_mem(p_siopcb->p_siopinib->ctlreg) \| SCI_SCR_TEIE_BIT));
	372	break;
	373	case SIO_RDY_RCV:
	374	sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
	375	(sil_reb_mem(p_siopcb->p_siopinib->ctlreg) \| SCI_SCR_RIE_BIT));
	376	break;
	377	default:
	378	assert(1);
	379	break;
	380	}
	381	}
	382
	383	/*
	384	* VAI/O\|[g©çÌR[obNÌÖ~
	385	*/
	386	void
	387	rx630_uart_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
	388	{
	389	switch (cbrtn) {
	390	case SIO_RDY_SND:
	391	sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
	392	(sil_reb_mem(p_siopcb->p_siopinib->ctlreg) & (~SCI_SCR_TEIE_BIT)));
	393	break;
	394	case SIO_RDY_RCV:
	395	sil_wrb_mem(p_siopcb->p_siopinib->ctlreg,
	396	(sil_reb_mem(p_siopcb->p_siopinib->ctlreg) & (~SCI_SCR_RIE_BIT)));
	397	break;
	398	default:
	399	assert(1);
	400	break;
	401	}
	402	}
	403
	404	/*
	405	* SIOÌÝT[rX[`
	406	*/
	407	void
	408	rx630_uart_tx_isr(ID siopid)
	409	{
	410	SIOPCB *p_siopcb = get_siopcb(siopid);
	411
	412	if((sil_reb_mem(
	413	(void *)p_siopcb->p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) != 0U){
	414	/*
	415	* MÂ\R[obN[`ðÄÑo·D
	416	*/
	417	rx630_uart_irdy_snd(p_siopcb->exinf);
	418	}
	419	}
	420
	421	void
	422	rx630_uart_rx_isr(ID siopid)
	423	{
	424	SIOPCB *p_siopcb = get_siopcb(siopid);
	425
	426	/*
	427	* óMtOªONÌÆ«ÌÝóMÊmR[obN[`ðÄÑo·.
	428	* µ©µ, RX600V[YÅÍóMtOªÈ¢½ß, íÉóMÊm
	429	* R[obN[`ðÄÑo·.
	430	* ±±ÅÍóMÝÌ¶ðM¶é.
	431	*/
	432	/*
	433	* óMÊmR[obN[`ðÄÑo·D
	434	*/
	435	rx630_uart_irdy_rcv(p_siopcb->exinf);
	436	}
	437
	438
	439	/*
	440	* \|[gÔ©çÇubNÌæªÔnÖÌÏ·
	441	*/
	442	SIOPCB *
	443	rx630_uart_get_siopcb(ID siopid) {
	444	SIOPCB *p_siopcb = get_siopcb(siopid);
	445	return(p_siopcb);
	446	}
	447
	448	/*
	449	* ÇubNÌæªÔn©çóMÝÔÖÌÏ·
	450	*/
	451	INTNO
	452	rx630_uart_intno_rx(SIOPCB *p_siopcb) {
	453	INTNO intno = p_siopcb->p_siopinib->rx_intno;
	454	return(intno);
	455	}
	456
	457	/*
	458	* ÇubNÌæªÔn©çMÝÔÖÌÏ·
	459	*/
	460	INTNO
	461	rx630_uart_intno_tx(SIOPCB *p_siopcb) {
	462	INTNO intno = p_siopcb->p_siopinib->te_intno;
	463	return(intno);
	464	}

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