| 1 | /*
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| 2 | * TOPPERS/SSP Kernel
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| 3 | * Smallest Set Profile Kernel
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| 4 | *
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| 5 | * Copyright (C) 2008-2010 by Witz Corporation, JAPAN
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| 6 | * Copyright (C) 2013 by Mitsuhiro Matsuura
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| 7 | *
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| 8 | * 上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
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| 9 | * ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
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| 10 | * 変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
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| 11 | * (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
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| 12 | * 権表示，この利用条件および下記の無保証規定が，そのままの形でソー
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| 13 | * スコード中に含まれていること．
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| 14 | * (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
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| 15 | * 用できる形で再配布する場合には，再配布に伴うドキュメント（利用
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| 16 | * 者マニュアルなど）に，上記の著作権表示，この利用条件および下記
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| 17 | * の無保証規定を掲載すること．
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| 18 | * (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
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| 19 | * 用できない形で再配布する場合には，次のいずれかの条件を満たすこ
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| 20 | * と．
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| 21 | * (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
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| 22 | * 作権表示，この利用条件および下記の無保証規定を掲載すること．
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| 23 | * (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
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| 24 | * 報告すること．
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| 25 | * (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
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| 26 | * 害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
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| 27 | * また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
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| 28 | * 由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
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| 29 | * 免責すること．
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| 30 | *
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| 31 | * 本ソフトウェアは，無保証で提供されているものである．上記著作権者お
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| 32 | * よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
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| 33 | * に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
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| 34 | * アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
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| 35 | * の責任を負わない．
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| 36 | *
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| 37 | */
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| 38 |
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| 39 | /*
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| 40 | * RX630に依存する定義
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| 41 | */
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| 42 | #ifndef TOPPERS_RX630_H
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| 43 | #define TOPPERS_RX630_H
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| 44 |
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| 45 | /*
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| 46 | * CPU例外ハンドラ番号の定義(固定ベクタテーブル)
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| 47 | *
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| 48 | * 番号の範囲は0 - 31
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| 49 | */
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| 50 | #define INT_PRIVILEGED_INSTRUNCTION 20 /* 特権命令例外 */
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| 51 | #define INT_UNDEF_INSTRUNCTION 23 /* 未定義命令例外 */
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| 52 | #define INT_FLOATINGPOINT_INSTRUCTION 25 /* 浮動小数点例外 */
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| 53 | #define INT_NMI 30 /* ノンマスカブル割り込み */
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| 54 | #define INT_RESET 31 /* リセット */
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| 55 |
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| 56 | /*
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| 57 | * 割込み番号の定義(可変ベクタテーブル)
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| 58 | */
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| 59 | #define INT_BUSERR 16
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| 60 | #define INT_FCU_FCUERR 21
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| 61 | #define INT_FCU_FRDYI 23
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| 62 | #define INT_ICU_SWINT 27
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| 63 | #define INT_CMT0_CMI 28
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| 64 | #define INT_CMT1_CMI 29
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| 65 | #define INT_CMT2_CMI 30
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| 66 | #define INT_CMT3_CMI 31
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| 67 | #define INT_ETH_EINT 32
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| 68 | #define INT_USB0_D0FIFO0 33
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| 69 | #define INT_USB0_D1FIFO0 34
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| 70 | #define INT_USB0_USBI0 35
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| 71 | #define INT_USB1_D0FIFO1 36
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| 72 | #define INT_USB1_D1FIFO1 37
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| 73 | #define INT_USB1_USBI1 38
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| 74 | #define INT_RSPI0_SPRI0 39
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| 75 | #define INT_RSPI0_SPTI0 40
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| 76 | #define INT_RSPI0_SPII0 41
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| 77 | #define INT_RSPI1_SPRI1 42
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| 78 | #define INT_RSPI1_SPTI1 43
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| 79 | #define INT_RSPI1_SPII1 44
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| 80 | #define INT_RSPI2_SPRI2 45
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| 81 | #define INT_RSPI2_SPTI2 46
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| 82 | #define INT_RSPI2_SPII2 47
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| 83 | #define INT_CAN0_RXF0 48
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| 84 | #define INT_CAN0_TXF0 49
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| 85 | #define INT_CAN0_RXM0 50
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| 86 | #define INT_CAN0_TXM0 51
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| 87 | #define INT_CAN1_RXF1 52
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| 88 | #define INT_CAN1_TXF1 53
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| 89 | #define INT_CAN1_RXM1 54
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| 90 | #define INT_CAN1_TXM1 55
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| 91 | #define INT_CAN2_RXF2 56
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| 92 | #define INT_CAN2_TXF2 57
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| 93 | #define INT_CAN2_RXM2 58
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| 94 | #define INT_CAN2_TXM2 59
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| 95 | #define INT_RTC_CUP 62
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| 96 | #define INT_IRQ0 64
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| 97 | #define INT_IRQ1 65
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| 98 | #define INT_IRQ2 66
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| 99 | #define INT_IRQ3 67
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| 100 | #define INT_IRQ4 68
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| 101 | #define INT_IRQ5 69
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| 102 | #define INT_IRQ6 70
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| 103 | #define INT_IRQ7 71
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| 104 | #define INT_IRQ8 72
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| 105 | #define INT_IRQ9 73
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| 106 | #define INT_IRQ10 74
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| 107 | #define INT_IRQ11 75
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| 108 | #define INT_IRQ12 76
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| 109 | #define INT_IRQ13 77
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| 110 | #define INT_IRQ14 78
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| 111 | #define INT_IRQ15 79
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| 112 | #define INT_USB_USBR0 90
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| 113 | #define INT_USB_USBR1 91
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| 114 | #define INT_RTC_ALM 92
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| 115 | #define INT_RTC_PRD 93
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| 116 | #define INT_AD0_ADI0 98
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| 117 | #define INT_S12AD_S12ADI0 102
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| 118 | #define INT_ICU_GROUP0 106
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| 119 | #define INT_ICU_GROUP1 107
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| 120 | #define INT_ICU_GROUP2 108
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| 121 | #define INT_ICU_GROUP3 109
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| 122 | #define INT_ICU_GROUP4 110
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| 123 | #define INT_ICU_GROUP5 111
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| 124 | #define INT_ICU_GROUP6 112
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| 125 | #define INT_ICU_GROUP12 114
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| 126 | #define INT_SCI12_SCIX0 122
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| 127 | #define INT_SCI12_SCIX1 123
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| 128 | #define INT_SCI12_SCIX2 124
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| 129 | #define INT_SCI12_SCIX3 125
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| 130 | #define INT_TPU0_TGI0A 126
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| 131 | #define INT_TPU0_TGI0B 127
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| 132 | #define INT_TPU0_TGI0C 128
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| 133 | #define INT_TPU0_TGI0D 129
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| 134 | #define INT_TPU1_TGI0A 130
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| 135 | #define INT_TPU1_TGI0B 131
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| 136 | #define INT_TPU2_TGI0A 132
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| 137 | #define INT_TPU2_TGI0B 133
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| 138 | #define INT_TPU3_TGI0A 134
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| 139 | #define INT_TPU3_TGI0B 135
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| 140 | #define INT_TPU3_TGI0C 136
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| 141 | #define INT_TPU3_TGI0D 137
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| 142 | #define INT_TPU4_TGI0A 138
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| 143 | #define INT_TPU4_TGI0B 139
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| 144 | #define INT_TPU5_TGI0A 140
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| 145 | #define INT_TPU5_TGI0B 141
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| 146 | #define INT_MTU0_TGIA0 142
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| 147 | #define INT_MTU0_TGIB0 143
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| 148 | #define INT_MTU0_TGIC0 144
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| 149 | #define INT_MTU0_TGID0 145
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| 150 | #define INT_MTU0_TCIE0 146
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| 151 | #define INT_MTU0_TCIF0 147
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| 152 | #define INT_MTU1_TGIA1 148
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| 153 | #define INT_MTU1_TGIB1 149
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| 154 | #define INT_MTU2_TGIA2 150
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| 155 | #define INT_MTU2_TGIB2 151
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| 156 | #define INT_MTU3_TGIA3 152
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| 157 | #define INT_MTU3_TGIB3 153
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| 158 | #define INT_MTU3_TGIC3 154
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| 159 | #define INT_MTU3_TGID3 155
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| 160 | #define INT_MTU4_TGIA4 156
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| 161 | #define INT_MTU4_TGIB4 157
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| 162 | #define INT_MTU4_TGIC4 158
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| 163 | #define INT_MTU4_TGID4 159
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| 164 | #define INT_MTU4_TCIV4 160
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| 165 | #define INT_MTU5_TGIU5 161
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| 166 | #define INT_MTU5_TGIV5 162
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| 167 | #define INT_MTU5_TGIW5 163
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| 168 | #define INT_MTU5_TGI11A 164
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| 169 | #define INT_MTU5_TGI11B 165
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| 170 | #define INT_POE_OEI1 166
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| 171 | #define INT_POE_OEI2 167
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| 172 | #define INT_TMR0_CMI0A 170
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| 173 | #define INT_TMR0_CMI0B 171
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| 174 | #define INT_TMR0_OV0I 172
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| 175 | #define INT_TMR1_CMI1A 173
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| 176 | #define INT_TMR1_CMI1B 174
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| 177 | #define INT_TMR1_OV1I 175
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| 178 | #define INT_TMR2_CMI2A 176
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| 179 | #define INT_TMR2_CMI2B 177
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| 180 | #define INT_TMR2_OV2I 178
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| 181 | #define INT_TMR3_CMI3A 179
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| 182 | #define INT_TMR3_CMI3B 180
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| 183 | #define INT_TMR3_OV3I 181
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| 184 | #define INT_RIIC0_EEI 182
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| 185 | #define INT_RIIC0_RXI 183
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| 186 | #define INT_RIIC0_TXI 184
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| 187 | #define INT_RIIC0_TEI 185
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| 188 | #define INT_RIIC1_EEI 186
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| 189 | #define INT_RIIC1_RXI 187
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| 190 | #define INT_RIIC1_TXI 188
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| 191 | #define INT_RIIC1_TEI 189
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| 192 | #define INT_RIIC2_EEI 190
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| 193 | #define INT_RIIC2_RXI 191
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| 194 | #define INT_RIIC2_TXI 192
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| 195 | #define INT_RIIC2_TEI 193
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| 196 | #define INT_RIIC3_EEI 194
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| 197 | #define INT_RIIC3_RXI 195
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| 198 | #define INT_RIIC3_TXI 196
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| 199 | #define INT_RIIC3_TEI 197
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| 200 | #define INT_DMAC_DMAC0I 198
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| 201 | #define INT_DMAC_DMAC1I 199
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| 202 | #define INT_DMAC_DMAC2I 200
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| 203 | #define INT_DMAC_DMAC3I 201
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| 204 | #define INT_SCI0_RXI 214
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| 205 | #define INT_SCI0_TXI 215
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| 206 | #define INT_SCI0_TEI 216
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| 207 | #define INT_SCI1_RXI 217
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| 208 | #define INT_SCI1_TXI 218
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| 209 | #define INT_SCI1_TEI 219
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| 210 | #define INT_SCI2_RXI 220
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| 211 | #define INT_SCI2_TXI 221
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| 212 | #define INT_SCI2_TEI 222
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| 213 | #define INT_SCI3_RXI 223
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| 214 | #define INT_SCI3_TXI 224
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| 215 | #define INT_SCI3_TEI 225
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| 216 | #define INT_SCI4_RXI 226
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| 217 | #define INT_SCI4_TXI 227
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| 218 | #define INT_SCI4_TEI 228
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| 219 | #define INT_SCI5_RXI 229
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| 220 | #define INT_SCI5_TXI 230
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| 221 | #define INT_SCI5_TEI 231
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| 222 | #define INT_SCI6_RXI 232
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| 223 | #define INT_SCI6_TXI 233
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| 224 | #define INT_SCI6_TEI 234
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| 225 | #define INT_SCI7_RXI 235
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| 226 | #define INT_SCI7_TXI 236
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| 227 | #define INT_SCI7_TEI 237
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| 228 | #define INT_SCI8_RXI 238
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| 229 | #define INT_SCI8_TXI 239
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| 230 | #define INT_SCI8_TEI 240
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| 231 | #define INT_SCI9_RXI 241
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| 232 | #define INT_SCI9_TXI 242
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| 233 | #define INT_SCI9_TEI 243
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| 234 | #define INT_SCI10_RXI 244
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| 235 | #define INT_SCI10_TXI 245
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| 236 | #define INT_SCI10_TEI 246
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| 237 | #define INT_SCI11_RXI 247
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| 238 | #define INT_SCI11_TXI 248
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| 239 | #define INT_SCI11_TEI 249
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| 240 | #define INT_SCI12_RXI 250
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| 241 | #define INT_SCI12_TXI 251
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| 242 | #define INT_SCI12_TEI 252
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| 243 | #define INT_IEB_IEBINT 253
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| 244 |
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| 245 | /*
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| 246 | * 各モジュールのレジスタ及び設定ビット情報
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| 247 | */
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| 248 |
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| 249 | #define SYSTEM_SYSCR0_ADDR ( ( volatile uint16_t __evenaccess * )0x00080006 )
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| 250 |
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| 251 | /*
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| 252 | * モジュールストップコントロールレジスタA（MSTPCRA）
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| 253 | */
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| 254 | #define SYSTEM_MSTPCRA_ADDR ( ( volatile uint32_t __evenaccess * )0x00080010 )
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| 255 | #define SYSTEM_MSTPCRA_MSTPA0_BIT ( 1UL << 0U )
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| 256 | #define SYSTEM_MSTPCRA_MSTPA1_BIT ( 1UL << 1U )
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| 257 | #define SYSTEM_MSTPCRA_MSTPA2_BIT ( 1UL << 2U )
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| 258 | #define SYSTEM_MSTPCRA_MSTPA3_BIT ( 1UL << 3U )
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| 259 | #define SYSTEM_MSTPCRA_MSTPA4_BIT ( 1UL << 4U )
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| 260 | #define SYSTEM_MSTPCRA_MSTPA5_BIT ( 1UL << 5U )
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| 261 | #define SYSTEM_MSTPCRA_MSTPA6_BIT ( 1UL << 6U )
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| 262 | #define SYSTEM_MSTPCRA_MSTPA7_BIT ( 1UL << 7U )
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| 263 | #define SYSTEM_MSTPCRA_MSTPA8_BIT ( 1UL << 8U )
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| 264 | #define SYSTEM_MSTPCRA_MSTPA9_BIT ( 1UL << 9U )
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| 265 | #define SYSTEM_MSTPCRA_MSTPA10_BIT ( 1UL << 10U )
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| 266 | #define SYSTEM_MSTPCRA_MSTPA11_BIT ( 1UL << 11U )
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| 267 | #define SYSTEM_MSTPCRA_MSTPA12_BIT ( 1UL << 12U )
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| 268 | #define SYSTEM_MSTPCRA_MSTPA13_BIT ( 1UL << 13U )
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| 269 | #define SYSTEM_MSTPCRA_MSTPA14_BIT ( 1UL << 14U )
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| 270 | #define SYSTEM_MSTPCRA_MSTPA15_BIT ( 1UL << 15U )
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| 271 | #define SYSTEM_MSTPCRA_MSTPA16_BIT ( 1UL << 16U )
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| 272 | #define SYSTEM_MSTPCRA_MSTPA17_BIT ( 1UL << 17U )
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| 273 | #define SYSTEM_MSTPCRA_MSTPA18_BIT ( 1UL << 18U )
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| 274 | #define SYSTEM_MSTPCRA_MSTPA19_BIT ( 1UL << 19U )
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| 275 | #define SYSTEM_MSTPCRA_MSTPA20_BIT ( 1UL << 20U )
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| 276 | #define SYSTEM_MSTPCRA_MSTPA21_BIT ( 1UL << 21U )
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| 277 | #define SYSTEM_MSTPCRA_MSTPA22_BIT ( 1UL << 22U )
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| 278 | #define SYSTEM_MSTPCRA_MSTPA23_BIT ( 1UL << 23U )
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| 279 | #define SYSTEM_MSTPCRA_MSTPA24_BIT ( 1UL << 24U )
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| 280 | #define SYSTEM_MSTPCRA_MSTPA25_BIT ( 1UL << 25U )
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| 281 | #define SYSTEM_MSTPCRA_MSTPA26_BIT ( 1UL << 26U )
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| 282 | #define SYSTEM_MSTPCRA_MSTPA27_BIT ( 1UL << 27U )
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| 283 | #define SYSTEM_MSTPCRA_MSTPA28_BIT ( 1UL << 28U )
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| 284 | #define SYSTEM_MSTPCRA_MSTPA29_BIT ( 1UL << 29U )
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| 285 | #define SYSTEM_MSTPCRA_MSTPA30_BIT ( 1UL << 30U )
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| 286 | #define SYSTEM_MSTPCRA_MSTPA31_BIT ( 1UL << 31U )
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| 287 | #define SYSTEM_MSTPCRA_ACSE_BIT ( 1UL << 31U)
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| 288 |
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| 289 | /*
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| 290 | * モジュールストップコントロールレジスタB（MSTPCRB）
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| 291 | */
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| 292 | #define SYSTEM_MSTPCRB_ADDR ( ( volatile uint32_t __evenaccess * )0x00080014 )
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| 293 | #define SYSTEM_MSTPCRB_MSTPB0_BIT ( 1UL << 0U )
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| 294 | #define SYSTEM_MSTPCRB_MSTPB1_BIT ( 1UL << 1U )
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| 295 | #define SYSTEM_MSTPCRB_MSTPB2_BIT ( 1UL << 2U )
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| 296 | #define SYSTEM_MSTPCRB_MSTPB3_BIT ( 1UL << 3U )
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| 297 | #define SYSTEM_MSTPCRB_MSTPB4_BIT ( 1UL << 4U )
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| 298 | #define SYSTEM_MSTPCRB_MSTPB5_BIT ( 1UL << 5U )
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| 299 | #define SYSTEM_MSTPCRB_MSTPB6_BIT ( 1UL << 6U )
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| 300 | #define SYSTEM_MSTPCRB_MSTPB7_BIT ( 1UL << 7U )
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| 301 | #define SYSTEM_MSTPCRB_MSTPB8_BIT ( 1UL << 8U )
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| 302 | #define SYSTEM_MSTPCRB_MSTPB9_BIT ( 1UL << 9U )
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| 303 | #define SYSTEM_MSTPCRB_MSTPB10_BIT ( 1UL << 10U )
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| 304 | #define SYSTEM_MSTPCRB_MSTPB11_BIT ( 1UL << 11U )
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| 305 | #define SYSTEM_MSTPCRB_MSTPB12_BIT ( 1UL << 12U )
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| 306 | #define SYSTEM_MSTPCRB_MSTPB13_BIT ( 1UL << 13U )
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| 307 | #define SYSTEM_MSTPCRB_MSTPB14_BIT ( 1UL << 14U )
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| 308 | #define SYSTEM_MSTPCRB_MSTPB15_BIT ( 1UL << 15U )
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| 309 | #define SYSTEM_MSTPCRB_MSTPB16_BIT ( 1UL << 16U )
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| 310 | #define SYSTEM_MSTPCRB_MSTPB17_BIT ( 1UL << 17U )
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| 311 | #define SYSTEM_MSTPCRB_MSTPB18_BIT ( 1UL << 18U )
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| 312 | #define SYSTEM_MSTPCRB_MSTPB19_BIT ( 1UL << 19U )
|
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| 313 | #define SYSTEM_MSTPCRB_MSTPB20_BIT ( 1UL << 20U )
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|---|
| 314 | #define SYSTEM_MSTPCRB_MSTPB21_BIT ( 1UL << 21U )
|
|---|
| 315 | #define SYSTEM_MSTPCRB_MSTPB22_BIT ( 1UL << 22U )
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| 316 | #define SYSTEM_MSTPCRB_MSTPB23_BIT ( 1UL << 23U )
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| 317 | #define SYSTEM_MSTPCRB_MSTPB24_BIT ( 1UL << 24U )
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| 318 | #define SYSTEM_MSTPCRB_MSTPB25_BIT ( 1UL << 25U )
|
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| 319 | #define SYSTEM_MSTPCRB_MSTPB26_BIT ( 1UL << 26U )
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| 320 | #define SYSTEM_MSTPCRB_MSTPB27_BIT ( 1UL << 27U )
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| 321 | #define SYSTEM_MSTPCRB_MSTPB28_BIT ( 1UL << 28U )
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| 322 | #define SYSTEM_MSTPCRB_MSTPB29_BIT ( 1UL << 29U )
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| 323 | #define SYSTEM_MSTPCRB_MSTPB30_BIT ( 1UL << 30U )
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| 324 | #define SYSTEM_MSTPCRB_MSTPB31_BIT ( 1UL << 31U )
|
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| 325 |
|
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| 326 | /*
|
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| 327 | * モジュールストップコントロールレジスタC（MSTPCRC）
|
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| 328 | */
|
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| 329 | #define SYSTEM_MSTPCRC_ADDR ( ( volatile uint32_t __evenaccess * )0x00080018 )
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| 330 | #define SYSTEM_MSTPCRC_MSTPC0_BIT ( 1UL << 0U )
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| 331 | #define SYSTEM_MSTPCRC_MSTPC1_BIT ( 1UL << 1U )
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| 332 | #define SYSTEM_MSTPCRC_MSTPC2_BIT ( 1UL << 2U )
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| 333 | #define SYSTEM_MSTPCRC_MSTPC3_BIT ( 1UL << 3U )
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| 334 | #define SYSTEM_MSTPCRC_MSTPC4_BIT ( 1UL << 4U )
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| 335 | #define SYSTEM_MSTPCRC_MSTPC5_BIT ( 1UL << 5U )
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| 336 | #define SYSTEM_MSTPCRC_MSTPC6_BIT ( 1UL << 6U )
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| 337 | #define SYSTEM_MSTPCRC_MSTPC7_BIT ( 1UL << 7U )
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| 338 | #define SYSTEM_MSTPCRC_MSTPC8_BIT ( 1UL << 8U )
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| 339 | #define SYSTEM_MSTPCRC_MSTPC9_BIT ( 1UL << 9U )
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| 340 | #define SYSTEM_MSTPCRC_MSTPC10_BIT ( 1UL << 10U )
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| 341 | #define SYSTEM_MSTPCRC_MSTPC11_BIT ( 1UL << 11U )
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| 342 | #define SYSTEM_MSTPCRC_MSTPC12_BIT ( 1UL << 12U )
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| 343 | #define SYSTEM_MSTPCRC_MSTPC13_BIT ( 1UL << 13U )
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| 344 | #define SYSTEM_MSTPCRC_MSTPC14_BIT ( 1UL << 14U )
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| 345 | #define SYSTEM_MSTPCRC_MSTPC15_BIT ( 1UL << 15U )
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| 346 | #define SYSTEM_MSTPCRC_MSTPC16_BIT ( 1UL << 16U )
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| 347 | #define SYSTEM_MSTPCRC_MSTPC17_BIT ( 1UL << 17U )
|
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| 348 | #define SYSTEM_MSTPCRC_MSTPC18_BIT ( 1UL << 18U )
|
|---|
| 349 | #define SYSTEM_MSTPCRC_MSTPC19_BIT ( 1UL << 19U )
|
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| 350 | #define SYSTEM_MSTPCRC_MSTPC20_BIT ( 1UL << 20U )
|
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| 351 | #define SYSTEM_MSTPCRC_MSTPC21_BIT ( 1UL << 21U )
|
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| 352 | #define SYSTEM_MSTPCRC_MSTPC22_BIT ( 1UL << 22U )
|
|---|
| 353 | #define SYSTEM_MSTPCRC_MSTPC23_BIT ( 1UL << 23U )
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| 354 | #define SYSTEM_MSTPCRC_MSTPC24_BIT ( 1UL << 24U )
|
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| 355 | #define SYSTEM_MSTPCRC_MSTPC25_BIT ( 1UL << 25U )
|
|---|
| 356 | #define SYSTEM_MSTPCRC_MSTPC26_BIT ( 1UL << 26U )
|
|---|
| 357 | #define SYSTEM_MSTPCRC_MSTPC27_BIT ( 1UL << 27U )
|
|---|
| 358 | #define SYSTEM_MSTPCRC_MSTPC28_BIT ( 1UL << 28U )
|
|---|
| 359 | #define SYSTEM_MSTPCRC_MSTPC29_BIT ( 1UL << 29U )
|
|---|
| 360 | #define SYSTEM_MSTPCRC_MSTPC30_BIT ( 1UL << 30U )
|
|---|
| 361 | #define SYSTEM_MSTPCRC_MSTPC31_BIT ( 1UL << 31U )
|
|---|
| 362 |
|
|---|
| 363 | /*
|
|---|
| 364 | * クロック発生回路
|
|---|
| 365 | */
|
|---|
| 366 | #define SYSTEM_SCKCR_ADDR ( ( volatile uint32_t __evenaccess * )0x00080020 )
|
|---|
| 367 | #define SYSTEM_SCKCR2_ADDR ( ( volatile uint16_t __evenaccess * )0x00080024 )
|
|---|
| 368 | #define SYSTEM_SCKCR2_UCK_OFFSET ( 4U )
|
|---|
| 369 | #define SYSTEM_SCKCR2_UCK_MASK ( 0xFU << SYSTEM_SCKCR2_UCK_OFFSET )
|
|---|
| 370 | #define SYSTEM_SCKCR3_ADDR ( ( volatile uint16_t __evenaccess * )0x00080026 )
|
|---|
| 371 | #define SYSTEM_SCKCR3_CKSEL_OFFSET ( 8U )
|
|---|
| 372 | #define SYSTEM_SCKCR3_CKSEL_MASK ( 0x7U << SYSTEM_SCKCR3_CKSEL_OFFSET )
|
|---|
| 373 | #define SYSTEM_PLLCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00080028 )
|
|---|
| 374 | #define SYSTEM_PLLCR_STC_OFFSET ( 8U )
|
|---|
| 375 | #define SYSTEM_PLLCR_STC_MASK ( 0x3FU << SYSTEM_PLLCR_STC_OFFSET )
|
|---|
| 376 | #define SYSTEM_PLLCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x0008002A )
|
|---|
| 377 | #define SYSTEM_PLLCR2_PLLEN ( 1UL << 0U )
|
|---|
| 378 | #define SYSTEM_MOFCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C293 )
|
|---|
| 379 | #define SYSTEM_MOFCR_MOFXIN ( 1UL << 0U )
|
|---|
| 380 | #define SYSTEM_MOSCCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00080032 )
|
|---|
| 381 | #define SYSTEM_MOSCCR_MOSTP ( 1UL << 0U )
|
|---|
| 382 |
|
|---|
| 383 | /*
|
|---|
| 384 | * プロテクトレジスタ
|
|---|
| 385 | */
|
|---|
| 386 | #define SYSTEM_PRCR_ADDR ( ( volatile uint16_t __evenaccess * )0x000803FE )
|
|---|
| 387 |
|
|---|
| 388 | /*
|
|---|
| 389 | * 割り込み要求レジスタ
|
|---|
| 390 | */
|
|---|
| 391 | #define ICU_IR000_ADDR ( ( volatile uint8_t __evenaccess * )0x00087000 )
|
|---|
| 392 | #define ICU_IR001_ADDR ( ( volatile uint8_t __evenaccess * )0x00087001 )
|
|---|
| 393 | #define ICU_IR002_ADDR ( ( volatile uint8_t __evenaccess * )0x00087002 )
|
|---|
| 394 | #define ICU_IR003_ADDR ( ( volatile uint8_t __evenaccess * )0x00087003 )
|
|---|
| 395 | #define ICU_IR004_ADDR ( ( volatile uint8_t __evenaccess * )0x00087004 )
|
|---|
| 396 | #define ICU_IR005_ADDR ( ( volatile uint8_t __evenaccess * )0x00087005 )
|
|---|
| 397 | #define ICU_IR006_ADDR ( ( volatile uint8_t __evenaccess * )0x00087006 )
|
|---|
| 398 | #define ICU_IR007_ADDR ( ( volatile uint8_t __evenaccess * )0x00087007 )
|
|---|
| 399 | #define ICU_IR008_ADDR ( ( volatile uint8_t __evenaccess * )0x00087008 )
|
|---|
| 400 | #define ICU_IR009_ADDR ( ( volatile uint8_t __evenaccess * )0x00087009 )
|
|---|
| 401 | #define ICU_IR010_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700A )
|
|---|
| 402 | #define ICU_IR011_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700B )
|
|---|
| 403 | #define ICU_IR012_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700C )
|
|---|
| 404 | #define ICU_IR013_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700D )
|
|---|
| 405 | #define ICU_IR014_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700E )
|
|---|
| 406 | #define ICU_IR015_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700F )
|
|---|
| 407 | #define ICU_IR016_ADDR ( ( volatile uint8_t __evenaccess * )0x00087010 )
|
|---|
| 408 | #define ICU_IR017_ADDR ( ( volatile uint8_t __evenaccess * )0x00087011 )
|
|---|
| 409 | #define ICU_IR018_ADDR ( ( volatile uint8_t __evenaccess * )0x00087012 )
|
|---|
| 410 | #define ICU_IR019_ADDR ( ( volatile uint8_t __evenaccess * )0x00087013 )
|
|---|
| 411 | #define ICU_IR020_ADDR ( ( volatile uint8_t __evenaccess * )0x00087014 )
|
|---|
| 412 | #define ICU_IR021_ADDR ( ( volatile uint8_t __evenaccess * )0x00087015 )
|
|---|
| 413 | #define ICU_IR022_ADDR ( ( volatile uint8_t __evenaccess * )0x00087016 )
|
|---|
| 414 | #define ICU_IR023_ADDR ( ( volatile uint8_t __evenaccess * )0x00087017 )
|
|---|
| 415 | #define ICU_IR024_ADDR ( ( volatile uint8_t __evenaccess * )0x00087018 )
|
|---|
| 416 | #define ICU_IR025_ADDR ( ( volatile uint8_t __evenaccess * )0x00087019 )
|
|---|
| 417 | #define ICU_IR026_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701A )
|
|---|
| 418 | #define ICU_IR027_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701B )
|
|---|
| 419 | #define ICU_IR028_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701C )
|
|---|
| 420 | #define ICU_IR029_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701D )
|
|---|
| 421 | #define ICU_IR030_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701E )
|
|---|
| 422 | #define ICU_IR031_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701F )
|
|---|
| 423 | #define ICU_IR032_ADDR ( ( volatile uint8_t __evenaccess * )0x00087020 )
|
|---|
| 424 | #define ICU_IR033_ADDR ( ( volatile uint8_t __evenaccess * )0x00087021 )
|
|---|
| 425 | #define ICU_IR034_ADDR ( ( volatile uint8_t __evenaccess * )0x00087022 )
|
|---|
| 426 | #define ICU_IR035_ADDR ( ( volatile uint8_t __evenaccess * )0x00087023 )
|
|---|
| 427 | #define ICU_IR036_ADDR ( ( volatile uint8_t __evenaccess * )0x00087024 )
|
|---|
| 428 | #define ICU_IR037_ADDR ( ( volatile uint8_t __evenaccess * )0x00087025 )
|
|---|
| 429 | #define ICU_IR038_ADDR ( ( volatile uint8_t __evenaccess * )0x00087026 )
|
|---|
| 430 | #define ICU_IR039_ADDR ( ( volatile uint8_t __evenaccess * )0x00087027 )
|
|---|
| 431 | #define ICU_IR040_ADDR ( ( volatile uint8_t __evenaccess * )0x00087028 )
|
|---|
| 432 | #define ICU_IR041_ADDR ( ( volatile uint8_t __evenaccess * )0x00087029 )
|
|---|
| 433 | #define ICU_IR042_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702A )
|
|---|
| 434 | #define ICU_IR043_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702B )
|
|---|
| 435 | #define ICU_IR044_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702C )
|
|---|
| 436 | #define ICU_IR045_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702D )
|
|---|
| 437 | #define ICU_IR046_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702E )
|
|---|
| 438 | #define ICU_IR047_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702F )
|
|---|
| 439 | #define ICU_IR048_ADDR ( ( volatile uint8_t __evenaccess * )0x00087030 )
|
|---|
| 440 | #define ICU_IR049_ADDR ( ( volatile uint8_t __evenaccess * )0x00087031 )
|
|---|
| 441 | #define ICU_IR050_ADDR ( ( volatile uint8_t __evenaccess * )0x00087032 )
|
|---|
| 442 | #define ICU_IR051_ADDR ( ( volatile uint8_t __evenaccess * )0x00087033 )
|
|---|
| 443 | #define ICU_IR052_ADDR ( ( volatile uint8_t __evenaccess * )0x00087034 )
|
|---|
| 444 | #define ICU_IR053_ADDR ( ( volatile uint8_t __evenaccess * )0x00087035 )
|
|---|
| 445 | #define ICU_IR054_ADDR ( ( volatile uint8_t __evenaccess * )0x00087036 )
|
|---|
| 446 | #define ICU_IR055_ADDR ( ( volatile uint8_t __evenaccess * )0x00087037 )
|
|---|
| 447 | #define ICU_IR056_ADDR ( ( volatile uint8_t __evenaccess * )0x00087038 )
|
|---|
| 448 | #define ICU_IR057_ADDR ( ( volatile uint8_t __evenaccess * )0x00087039 )
|
|---|
| 449 | #define ICU_IR058_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703A )
|
|---|
| 450 | #define ICU_IR059_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703B )
|
|---|
| 451 | #define ICU_IR060_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703C )
|
|---|
| 452 | #define ICU_IR061_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703D )
|
|---|
| 453 | #define ICU_IR062_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703E )
|
|---|
| 454 | #define ICU_IR063_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703F )
|
|---|
| 455 | #define ICU_IR064_ADDR ( ( volatile uint8_t __evenaccess * )0x00087040 )
|
|---|
| 456 | #define ICU_IR065_ADDR ( ( volatile uint8_t __evenaccess * )0x00087041 )
|
|---|
| 457 | #define ICU_IR066_ADDR ( ( volatile uint8_t __evenaccess * )0x00087042 )
|
|---|
| 458 | #define ICU_IR067_ADDR ( ( volatile uint8_t __evenaccess * )0x00087043 )
|
|---|
| 459 | #define ICU_IR068_ADDR ( ( volatile uint8_t __evenaccess * )0x00087044 )
|
|---|
| 460 | #define ICU_IR069_ADDR ( ( volatile uint8_t __evenaccess * )0x00087045 )
|
|---|
| 461 | #define ICU_IR070_ADDR ( ( volatile uint8_t __evenaccess * )0x00087046 )
|
|---|
| 462 | #define ICU_IR071_ADDR ( ( volatile uint8_t __evenaccess * )0x00087047 )
|
|---|
| 463 | #define ICU_IR072_ADDR ( ( volatile uint8_t __evenaccess * )0x00087048 )
|
|---|
| 464 | #define ICU_IR073_ADDR ( ( volatile uint8_t __evenaccess * )0x00087049 )
|
|---|
| 465 | #define ICU_IR074_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704A )
|
|---|
| 466 | #define ICU_IR075_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704B )
|
|---|
| 467 | #define ICU_IR076_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704C )
|
|---|
| 468 | #define ICU_IR077_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704D )
|
|---|
| 469 | #define ICU_IR078_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704E )
|
|---|
| 470 | #define ICU_IR079_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704F )
|
|---|
| 471 | #define ICU_IR080_ADDR ( ( volatile uint8_t __evenaccess * )0x00087050 )
|
|---|
| 472 | #define ICU_IR081_ADDR ( ( volatile uint8_t __evenaccess * )0x00087051 )
|
|---|
| 473 | #define ICU_IR082_ADDR ( ( volatile uint8_t __evenaccess * )0x00087052 )
|
|---|
| 474 | #define ICU_IR083_ADDR ( ( volatile uint8_t __evenaccess * )0x00087053 )
|
|---|
| 475 | #define ICU_IR084_ADDR ( ( volatile uint8_t __evenaccess * )0x00087054 )
|
|---|
| 476 | #define ICU_IR085_ADDR ( ( volatile uint8_t __evenaccess * )0x00087055 )
|
|---|
| 477 | #define ICU_IR086_ADDR ( ( volatile uint8_t __evenaccess * )0x00087056 )
|
|---|
| 478 | #define ICU_IR087_ADDR ( ( volatile uint8_t __evenaccess * )0x00087057 )
|
|---|
| 479 | #define ICU_IR088_ADDR ( ( volatile uint8_t __evenaccess * )0x00087058 )
|
|---|
| 480 | #define ICU_IR089_ADDR ( ( volatile uint8_t __evenaccess * )0x00087059 )
|
|---|
| 481 | #define ICU_IR090_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705A )
|
|---|
| 482 | #define ICU_IR091_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705B )
|
|---|
| 483 | #define ICU_IR092_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705C )
|
|---|
| 484 | #define ICU_IR093_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705D )
|
|---|
| 485 | #define ICU_IR094_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705E )
|
|---|
| 486 | #define ICU_IR095_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705F )
|
|---|
| 487 | #define ICU_IR096_ADDR ( ( volatile uint8_t __evenaccess * )0x00087060 )
|
|---|
| 488 | #define ICU_IR097_ADDR ( ( volatile uint8_t __evenaccess * )0x00087061 )
|
|---|
| 489 | #define ICU_IR098_ADDR ( ( volatile uint8_t __evenaccess * )0x00087062 )
|
|---|
| 490 | #define ICU_IR099_ADDR ( ( volatile uint8_t __evenaccess * )0x00087063 )
|
|---|
| 491 | #define ICU_IR100_ADDR ( ( volatile uint8_t __evenaccess * )0x00087064 )
|
|---|
| 492 | #define ICU_IR101_ADDR ( ( volatile uint8_t __evenaccess * )0x00087065 )
|
|---|
| 493 | #define ICU_IR102_ADDR ( ( volatile uint8_t __evenaccess * )0x00087066 )
|
|---|
| 494 | #define ICU_IR103_ADDR ( ( volatile uint8_t __evenaccess * )0x00087067 )
|
|---|
| 495 | #define ICU_IR104_ADDR ( ( volatile uint8_t __evenaccess * )0x00087068 )
|
|---|
| 496 | #define ICU_IR105_ADDR ( ( volatile uint8_t __evenaccess * )0x00087069 )
|
|---|
| 497 | #define ICU_IR106_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706A )
|
|---|
| 498 | #define ICU_IR107_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706B )
|
|---|
| 499 | #define ICU_IR108_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706C )
|
|---|
| 500 | #define ICU_IR109_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706D )
|
|---|
| 501 | #define ICU_IR110_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706E )
|
|---|
| 502 | #define ICU_IR111_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706F )
|
|---|
| 503 | #define ICU_IR112_ADDR ( ( volatile uint8_t __evenaccess * )0x00087070 )
|
|---|
| 504 | #define ICU_IR113_ADDR ( ( volatile uint8_t __evenaccess * )0x00087071 )
|
|---|
| 505 | #define ICU_IR114_ADDR ( ( volatile uint8_t __evenaccess * )0x00087072 )
|
|---|
| 506 | #define ICU_IR115_ADDR ( ( volatile uint8_t __evenaccess * )0x00087073 )
|
|---|
| 507 | #define ICU_IR116_ADDR ( ( volatile uint8_t __evenaccess * )0x00087074 )
|
|---|
| 508 | #define ICU_IR117_ADDR ( ( volatile uint8_t __evenaccess * )0x00087075 )
|
|---|
| 509 | #define ICU_IR118_ADDR ( ( volatile uint8_t __evenaccess * )0x00087076 )
|
|---|
| 510 | #define ICU_IR119_ADDR ( ( volatile uint8_t __evenaccess * )0x00087077 )
|
|---|
| 511 | #define ICU_IR120_ADDR ( ( volatile uint8_t __evenaccess * )0x00087078 )
|
|---|
| 512 | #define ICU_IR121_ADDR ( ( volatile uint8_t __evenaccess * )0x00087079 )
|
|---|
| 513 | #define ICU_IR122_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707A )
|
|---|
| 514 | #define ICU_IR123_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707B )
|
|---|
| 515 | #define ICU_IR124_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707C )
|
|---|
| 516 | #define ICU_IR125_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707D )
|
|---|
| 517 | #define ICU_IR126_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707E )
|
|---|
| 518 | #define ICU_IR127_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707F )
|
|---|
| 519 | #define ICU_IR128_ADDR ( ( volatile uint8_t __evenaccess * )0x00087080 )
|
|---|
| 520 | #define ICU_IR129_ADDR ( ( volatile uint8_t __evenaccess * )0x00087081 )
|
|---|
| 521 | #define ICU_IR130_ADDR ( ( volatile uint8_t __evenaccess * )0x00087082 )
|
|---|
| 522 | #define ICU_IR131_ADDR ( ( volatile uint8_t __evenaccess * )0x00087083 )
|
|---|
| 523 | #define ICU_IR132_ADDR ( ( volatile uint8_t __evenaccess * )0x00087084 )
|
|---|
| 524 | #define ICU_IR133_ADDR ( ( volatile uint8_t __evenaccess * )0x00087085 )
|
|---|
| 525 | #define ICU_IR134_ADDR ( ( volatile uint8_t __evenaccess * )0x00087086 )
|
|---|
| 526 | #define ICU_IR135_ADDR ( ( volatile uint8_t __evenaccess * )0x00087087 )
|
|---|
| 527 | #define ICU_IR136_ADDR ( ( volatile uint8_t __evenaccess * )0x00087088 )
|
|---|
| 528 | #define ICU_IR137_ADDR ( ( volatile uint8_t __evenaccess * )0x00087089 )
|
|---|
| 529 | #define ICU_IR138_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708A )
|
|---|
| 530 | #define ICU_IR139_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708B )
|
|---|
| 531 | #define ICU_IR140_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708C )
|
|---|
| 532 | #define ICU_IR141_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708D )
|
|---|
| 533 | #define ICU_IR142_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708E )
|
|---|
| 534 | #define ICU_IR143_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708F )
|
|---|
| 535 | #define ICU_IR144_ADDR ( ( volatile uint8_t __evenaccess * )0x00087090 )
|
|---|
| 536 | #define ICU_IR145_ADDR ( ( volatile uint8_t __evenaccess * )0x00087091 )
|
|---|
| 537 | #define ICU_IR146_ADDR ( ( volatile uint8_t __evenaccess * )0x00087092 )
|
|---|
| 538 | #define ICU_IR147_ADDR ( ( volatile uint8_t __evenaccess * )0x00087093 )
|
|---|
| 539 | #define ICU_IR148_ADDR ( ( volatile uint8_t __evenaccess * )0x00087094 )
|
|---|
| 540 | #define ICU_IR149_ADDR ( ( volatile uint8_t __evenaccess * )0x00087095 )
|
|---|
| 541 | #define ICU_IR150_ADDR ( ( volatile uint8_t __evenaccess * )0x00087096 )
|
|---|
| 542 | #define ICU_IR151_ADDR ( ( volatile uint8_t __evenaccess * )0x00087097 )
|
|---|
| 543 | #define ICU_IR152_ADDR ( ( volatile uint8_t __evenaccess * )0x00087098 )
|
|---|
| 544 | #define ICU_IR153_ADDR ( ( volatile uint8_t __evenaccess * )0x00087099 )
|
|---|
| 545 | #define ICU_IR154_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709A )
|
|---|
| 546 | #define ICU_IR155_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709B )
|
|---|
| 547 | #define ICU_IR156_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709C )
|
|---|
| 548 | #define ICU_IR157_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709D )
|
|---|
| 549 | #define ICU_IR158_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709E )
|
|---|
| 550 | #define ICU_IR159_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709F )
|
|---|
| 551 | #define ICU_IR160_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A0 )
|
|---|
| 552 | #define ICU_IR161_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A1 )
|
|---|
| 553 | #define ICU_IR162_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A2 )
|
|---|
| 554 | #define ICU_IR163_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A3 )
|
|---|
| 555 | #define ICU_IR164_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A4 )
|
|---|
| 556 | #define ICU_IR165_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A5 )
|
|---|
| 557 | #define ICU_IR166_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A6 )
|
|---|
| 558 | #define ICU_IR167_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A7 )
|
|---|
| 559 | #define ICU_IR168_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A8 )
|
|---|
| 560 | #define ICU_IR169_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A9 )
|
|---|
| 561 | #define ICU_IR170_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AA )
|
|---|
| 562 | #define ICU_IR171_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AB )
|
|---|
| 563 | #define ICU_IR172_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AC )
|
|---|
| 564 | #define ICU_IR173_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AD )
|
|---|
| 565 | #define ICU_IR174_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AE )
|
|---|
| 566 | #define ICU_IR175_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AF )
|
|---|
| 567 | #define ICU_IR176_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B0 )
|
|---|
| 568 | #define ICU_IR177_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B1 )
|
|---|
| 569 | #define ICU_IR178_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B2 )
|
|---|
| 570 | #define ICU_IR179_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B3 )
|
|---|
| 571 | #define ICU_IR180_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B4 )
|
|---|
| 572 | #define ICU_IR181_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B5 )
|
|---|
| 573 | #define ICU_IR182_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B6 )
|
|---|
| 574 | #define ICU_IR183_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B7 )
|
|---|
| 575 | #define ICU_IR184_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B8 )
|
|---|
| 576 | #define ICU_IR185_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B9 )
|
|---|
| 577 | #define ICU_IR186_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BA )
|
|---|
| 578 | #define ICU_IR187_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BB )
|
|---|
| 579 | #define ICU_IR188_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BC )
|
|---|
| 580 | #define ICU_IR189_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BD )
|
|---|
| 581 | #define ICU_IR190_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BE )
|
|---|
| 582 | #define ICU_IR191_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BF )
|
|---|
| 583 | #define ICU_IR192_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C0 )
|
|---|
| 584 | #define ICU_IR193_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C1 )
|
|---|
| 585 | #define ICU_IR194_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C2 )
|
|---|
| 586 | #define ICU_IR195_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C3 )
|
|---|
| 587 | #define ICU_IR196_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C4 )
|
|---|
| 588 | #define ICU_IR197_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C5 )
|
|---|
| 589 | #define ICU_IR198_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C6 )
|
|---|
| 590 | #define ICU_IR199_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C7 )
|
|---|
| 591 | #define ICU_IR200_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C8 )
|
|---|
| 592 | #define ICU_IR201_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C9 )
|
|---|
| 593 | #define ICU_IR202_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CA )
|
|---|
| 594 | #define ICU_IR203_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CB )
|
|---|
| 595 | #define ICU_IR204_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CC )
|
|---|
| 596 | #define ICU_IR205_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CD )
|
|---|
| 597 | #define ICU_IR206_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CE )
|
|---|
| 598 | #define ICU_IR207_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CF )
|
|---|
| 599 | #define ICU_IR208_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D0 )
|
|---|
| 600 | #define ICU_IR209_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D1 )
|
|---|
| 601 | #define ICU_IR210_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D2 )
|
|---|
| 602 | #define ICU_IR211_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D3 )
|
|---|
| 603 | #define ICU_IR212_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D4 )
|
|---|
| 604 | #define ICU_IR213_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D5 )
|
|---|
| 605 | #define ICU_IR214_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D6 )
|
|---|
| 606 | #define ICU_IR215_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D7 )
|
|---|
| 607 | #define ICU_IR216_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D8 )
|
|---|
| 608 | #define ICU_IR217_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D9 )
|
|---|
| 609 | #define ICU_IR218_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DA )
|
|---|
| 610 | #define ICU_IR219_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DB )
|
|---|
| 611 | #define ICU_IR220_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DC )
|
|---|
| 612 | #define ICU_IR221_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DD )
|
|---|
| 613 | #define ICU_IR222_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DE )
|
|---|
| 614 | #define ICU_IR223_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DF )
|
|---|
| 615 | #define ICU_IR224_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E0 )
|
|---|
| 616 | #define ICU_IR225_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E1 )
|
|---|
| 617 | #define ICU_IR226_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E2 )
|
|---|
| 618 | #define ICU_IR227_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E3 )
|
|---|
| 619 | #define ICU_IR228_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E4 )
|
|---|
| 620 | #define ICU_IR229_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E5 )
|
|---|
| 621 | #define ICU_IR230_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E6 )
|
|---|
| 622 | #define ICU_IR231_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E7 )
|
|---|
| 623 | #define ICU_IR232_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E8 )
|
|---|
| 624 | #define ICU_IR233_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E9 )
|
|---|
| 625 | #define ICU_IR234_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EA )
|
|---|
| 626 | #define ICU_IR235_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EB )
|
|---|
| 627 | #define ICU_IR236_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EC )
|
|---|
| 628 | #define ICU_IR237_ADDR ( ( volatile uint8_t __evenaccess * )0x000870ED )
|
|---|
| 629 | #define ICU_IR238_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EE )
|
|---|
| 630 | #define ICU_IR239_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EF )
|
|---|
| 631 | #define ICU_IR240_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F0 )
|
|---|
| 632 | #define ICU_IR241_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F1 )
|
|---|
| 633 | #define ICU_IR242_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F2 )
|
|---|
| 634 | #define ICU_IR243_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F3 )
|
|---|
| 635 | #define ICU_IR244_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F4 )
|
|---|
| 636 | #define ICU_IR245_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F5 )
|
|---|
| 637 | #define ICU_IR246_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F6 )
|
|---|
| 638 | #define ICU_IR247_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F7 )
|
|---|
| 639 | #define ICU_IR248_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F8 )
|
|---|
| 640 | #define ICU_IR249_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F9 )
|
|---|
| 641 | #define ICU_IR250_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FA )
|
|---|
| 642 | #define ICU_IR251_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FB )
|
|---|
| 643 | #define ICU_IR252_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FC )
|
|---|
| 644 | #define ICU_IR253_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FD )
|
|---|
| 645 | #define ICU_IR254_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FE )
|
|---|
| 646 | #define ICU_IR255_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FF )
|
|---|
| 647 | #define ICU_IR_BIT ( 1U << 0U )
|
|---|
| 648 |
|
|---|
| 649 | /*
|
|---|
| 650 | * 割り込み要求先設定レジスタ
|
|---|
| 651 | */
|
|---|
| 652 | #define ICU_ISELR000_ADDR ( ( volatile uint8_t __evenaccess * )0x00087100 )
|
|---|
| 653 | #define ICU_ISELR001_ADDR ( ( volatile uint8_t __evenaccess * )0x00087101 )
|
|---|
| 654 | #define ICU_ISELR002_ADDR ( ( volatile uint8_t __evenaccess * )0x00087102 )
|
|---|
| 655 | #define ICU_ISELR003_ADDR ( ( volatile uint8_t __evenaccess * )0x00087103 )
|
|---|
| 656 | #define ICU_ISELR004_ADDR ( ( volatile uint8_t __evenaccess * )0x00087104 )
|
|---|
| 657 | #define ICU_ISELR005_ADDR ( ( volatile uint8_t __evenaccess * )0x00087105 )
|
|---|
| 658 | #define ICU_ISELR006_ADDR ( ( volatile uint8_t __evenaccess * )0x00087106 )
|
|---|
| 659 | #define ICU_ISELR007_ADDR ( ( volatile uint8_t __evenaccess * )0x00087107 )
|
|---|
| 660 | #define ICU_ISELR008_ADDR ( ( volatile uint8_t __evenaccess * )0x00087108 )
|
|---|
| 661 | #define ICU_ISELR009_ADDR ( ( volatile uint8_t __evenaccess * )0x00087109 )
|
|---|
| 662 | #define ICU_ISELR010_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710A )
|
|---|
| 663 | #define ICU_ISELR011_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710B )
|
|---|
| 664 | #define ICU_ISELR012_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710C )
|
|---|
| 665 | #define ICU_ISELR013_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710D )
|
|---|
| 666 | #define ICU_ISELR014_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710E )
|
|---|
| 667 | #define ICU_ISELR015_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710F )
|
|---|
| 668 | #define ICU_ISELR016_ADDR ( ( volatile uint8_t __evenaccess * )0x00087110 )
|
|---|
| 669 | #define ICU_ISELR017_ADDR ( ( volatile uint8_t __evenaccess * )0x00087111 )
|
|---|
| 670 | #define ICU_ISELR018_ADDR ( ( volatile uint8_t __evenaccess * )0x00087112 )
|
|---|
| 671 | #define ICU_ISELR019_ADDR ( ( volatile uint8_t __evenaccess * )0x00087113 )
|
|---|
| 672 | #define ICU_ISELR020_ADDR ( ( volatile uint8_t __evenaccess * )0x00087114 )
|
|---|
| 673 | #define ICU_ISELR021_ADDR ( ( volatile uint8_t __evenaccess * )0x00087115 )
|
|---|
| 674 | #define ICU_ISELR022_ADDR ( ( volatile uint8_t __evenaccess * )0x00087116 )
|
|---|
| 675 | #define ICU_ISELR023_ADDR ( ( volatile uint8_t __evenaccess * )0x00087117 )
|
|---|
| 676 | #define ICU_ISELR024_ADDR ( ( volatile uint8_t __evenaccess * )0x00087118 )
|
|---|
| 677 | #define ICU_ISELR025_ADDR ( ( volatile uint8_t __evenaccess * )0x00087119 )
|
|---|
| 678 | #define ICU_ISELR026_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711A )
|
|---|
| 679 | #define ICU_ISELR027_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711B )
|
|---|
| 680 | #define ICU_ISELR028_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711C )
|
|---|
| 681 | #define ICU_ISELR029_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711D )
|
|---|
| 682 | #define ICU_ISELR030_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711E )
|
|---|
| 683 | #define ICU_ISELR031_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711F )
|
|---|
| 684 | #define ICU_ISELR032_ADDR ( ( volatile uint8_t __evenaccess * )0x00087120 )
|
|---|
| 685 | #define ICU_ISELR033_ADDR ( ( volatile uint8_t __evenaccess * )0x00087121 )
|
|---|
| 686 | #define ICU_ISELR034_ADDR ( ( volatile uint8_t __evenaccess * )0x00087122 )
|
|---|
| 687 | #define ICU_ISELR035_ADDR ( ( volatile uint8_t __evenaccess * )0x00087123 )
|
|---|
| 688 | #define ICU_ISELR036_ADDR ( ( volatile uint8_t __evenaccess * )0x00087124 )
|
|---|
| 689 | #define ICU_ISELR037_ADDR ( ( volatile uint8_t __evenaccess * )0x00087125 )
|
|---|
| 690 | #define ICU_ISELR038_ADDR ( ( volatile uint8_t __evenaccess * )0x00087126 )
|
|---|
| 691 | #define ICU_ISELR039_ADDR ( ( volatile uint8_t __evenaccess * )0x00087127 )
|
|---|
| 692 | #define ICU_ISELR040_ADDR ( ( volatile uint8_t __evenaccess * )0x00087128 )
|
|---|
| 693 | #define ICU_ISELR041_ADDR ( ( volatile uint8_t __evenaccess * )0x00087129 )
|
|---|
| 694 | #define ICU_ISELR042_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712A )
|
|---|
| 695 | #define ICU_ISELR043_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712B )
|
|---|
| 696 | #define ICU_ISELR044_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712C )
|
|---|
| 697 | #define ICU_ISELR045_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712D )
|
|---|
| 698 | #define ICU_ISELR046_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712E )
|
|---|
| 699 | #define ICU_ISELR047_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712F )
|
|---|
| 700 | #define ICU_ISELR048_ADDR ( ( volatile uint8_t __evenaccess * )0x00087130 )
|
|---|
| 701 | #define ICU_ISELR049_ADDR ( ( volatile uint8_t __evenaccess * )0x00087131 )
|
|---|
| 702 | #define ICU_ISELR050_ADDR ( ( volatile uint8_t __evenaccess * )0x00087132 )
|
|---|
| 703 | #define ICU_ISELR051_ADDR ( ( volatile uint8_t __evenaccess * )0x00087133 )
|
|---|
| 704 | #define ICU_ISELR052_ADDR ( ( volatile uint8_t __evenaccess * )0x00087134 )
|
|---|
| 705 | #define ICU_ISELR053_ADDR ( ( volatile uint8_t __evenaccess * )0x00087135 )
|
|---|
| 706 | #define ICU_ISELR054_ADDR ( ( volatile uint8_t __evenaccess * )0x00087136 )
|
|---|
| 707 | #define ICU_ISELR055_ADDR ( ( volatile uint8_t __evenaccess * )0x00087137 )
|
|---|
| 708 | #define ICU_ISELR056_ADDR ( ( volatile uint8_t __evenaccess * )0x00087138 )
|
|---|
| 709 | #define ICU_ISELR057_ADDR ( ( volatile uint8_t __evenaccess * )0x00087139 )
|
|---|
| 710 | #define ICU_ISELR058_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713A )
|
|---|
| 711 | #define ICU_ISELR059_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713B )
|
|---|
| 712 | #define ICU_ISELR060_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713C )
|
|---|
| 713 | #define ICU_ISELR061_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713D )
|
|---|
| 714 | #define ICU_ISELR062_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713E )
|
|---|
| 715 | #define ICU_ISELR063_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713F )
|
|---|
| 716 | #define ICU_ISELR064_ADDR ( ( volatile uint8_t __evenaccess * )0x00087140 )
|
|---|
| 717 | #define ICU_ISELR065_ADDR ( ( volatile uint8_t __evenaccess * )0x00087141 )
|
|---|
| 718 | #define ICU_ISELR066_ADDR ( ( volatile uint8_t __evenaccess * )0x00087142 )
|
|---|
| 719 | #define ICU_ISELR067_ADDR ( ( volatile uint8_t __evenaccess * )0x00087143 )
|
|---|
| 720 | #define ICU_ISELR068_ADDR ( ( volatile uint8_t __evenaccess * )0x00087144 )
|
|---|
| 721 | #define ICU_ISELR069_ADDR ( ( volatile uint8_t __evenaccess * )0x00087145 )
|
|---|
| 722 | #define ICU_ISELR070_ADDR ( ( volatile uint8_t __evenaccess * )0x00087146 )
|
|---|
| 723 | #define ICU_ISELR071_ADDR ( ( volatile uint8_t __evenaccess * )0x00087147 )
|
|---|
| 724 | #define ICU_ISELR072_ADDR ( ( volatile uint8_t __evenaccess * )0x00087148 )
|
|---|
| 725 | #define ICU_ISELR073_ADDR ( ( volatile uint8_t __evenaccess * )0x00087149 )
|
|---|
| 726 | #define ICU_ISELR074_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714A )
|
|---|
| 727 | #define ICU_ISELR075_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714B )
|
|---|
| 728 | #define ICU_ISELR076_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714C )
|
|---|
| 729 | #define ICU_ISELR077_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714D )
|
|---|
| 730 | #define ICU_ISELR078_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714E )
|
|---|
| 731 | #define ICU_ISELR079_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714F )
|
|---|
| 732 | #define ICU_ISELR080_ADDR ( ( volatile uint8_t __evenaccess * )0x00087150 )
|
|---|
| 733 | #define ICU_ISELR081_ADDR ( ( volatile uint8_t __evenaccess * )0x00087151 )
|
|---|
| 734 | #define ICU_ISELR082_ADDR ( ( volatile uint8_t __evenaccess * )0x00087152 )
|
|---|
| 735 | #define ICU_ISELR083_ADDR ( ( volatile uint8_t __evenaccess * )0x00087153 )
|
|---|
| 736 | #define ICU_ISELR084_ADDR ( ( volatile uint8_t __evenaccess * )0x00087154 )
|
|---|
| 737 | #define ICU_ISELR085_ADDR ( ( volatile uint8_t __evenaccess * )0x00087155 )
|
|---|
| 738 | #define ICU_ISELR086_ADDR ( ( volatile uint8_t __evenaccess * )0x00087156 )
|
|---|
| 739 | #define ICU_ISELR087_ADDR ( ( volatile uint8_t __evenaccess * )0x00087157 )
|
|---|
| 740 | #define ICU_ISELR088_ADDR ( ( volatile uint8_t __evenaccess * )0x00087158 )
|
|---|
| 741 | #define ICU_ISELR089_ADDR ( ( volatile uint8_t __evenaccess * )0x00087159 )
|
|---|
| 742 | #define ICU_ISELR090_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715A )
|
|---|
| 743 | #define ICU_ISELR091_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715B )
|
|---|
| 744 | #define ICU_ISELR092_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715C )
|
|---|
| 745 | #define ICU_ISELR093_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715D )
|
|---|
| 746 | #define ICU_ISELR094_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715E )
|
|---|
| 747 | #define ICU_ISELR095_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715F )
|
|---|
| 748 | #define ICU_ISELR096_ADDR ( ( volatile uint8_t __evenaccess * )0x00087160 )
|
|---|
| 749 | #define ICU_ISELR097_ADDR ( ( volatile uint8_t __evenaccess * )0x00087161 )
|
|---|
| 750 | #define ICU_ISELR098_ADDR ( ( volatile uint8_t __evenaccess * )0x00087162 )
|
|---|
| 751 | #define ICU_ISELR099_ADDR ( ( volatile uint8_t __evenaccess * )0x00087163 )
|
|---|
| 752 | #define ICU_ISELR100_ADDR ( ( volatile uint8_t __evenaccess * )0x00087164 )
|
|---|
| 753 | #define ICU_ISELR101_ADDR ( ( volatile uint8_t __evenaccess * )0x00087165 )
|
|---|
| 754 | #define ICU_ISELR102_ADDR ( ( volatile uint8_t __evenaccess * )0x00087166 )
|
|---|
| 755 | #define ICU_ISELR103_ADDR ( ( volatile uint8_t __evenaccess * )0x00087167 )
|
|---|
| 756 | #define ICU_ISELR104_ADDR ( ( volatile uint8_t __evenaccess * )0x00087168 )
|
|---|
| 757 | #define ICU_ISELR105_ADDR ( ( volatile uint8_t __evenaccess * )0x00087169 )
|
|---|
| 758 | #define ICU_ISELR106_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716A )
|
|---|
| 759 | #define ICU_ISELR107_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716B )
|
|---|
| 760 | #define ICU_ISELR108_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716C )
|
|---|
| 761 | #define ICU_ISELR109_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716D )
|
|---|
| 762 | #define ICU_ISELR110_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716E )
|
|---|
| 763 | #define ICU_ISELR111_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716F )
|
|---|
| 764 | #define ICU_ISELR112_ADDR ( ( volatile uint8_t __evenaccess * )0x00087170 )
|
|---|
| 765 | #define ICU_ISELR113_ADDR ( ( volatile uint8_t __evenaccess * )0x00087171 )
|
|---|
| 766 | #define ICU_ISELR114_ADDR ( ( volatile uint8_t __evenaccess * )0x00087172 )
|
|---|
| 767 | #define ICU_ISELR115_ADDR ( ( volatile uint8_t __evenaccess * )0x00087173 )
|
|---|
| 768 | #define ICU_ISELR116_ADDR ( ( volatile uint8_t __evenaccess * )0x00087174 )
|
|---|
| 769 | #define ICU_ISELR117_ADDR ( ( volatile uint8_t __evenaccess * )0x00087175 )
|
|---|
| 770 | #define ICU_ISELR118_ADDR ( ( volatile uint8_t __evenaccess * )0x00087176 )
|
|---|
| 771 | #define ICU_ISELR119_ADDR ( ( volatile uint8_t __evenaccess * )0x00087177 )
|
|---|
| 772 | #define ICU_ISELR120_ADDR ( ( volatile uint8_t __evenaccess * )0x00087178 )
|
|---|
| 773 | #define ICU_ISELR121_ADDR ( ( volatile uint8_t __evenaccess * )0x00087179 )
|
|---|
| 774 | #define ICU_ISELR122_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717A )
|
|---|
| 775 | #define ICU_ISELR123_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717B )
|
|---|
| 776 | #define ICU_ISELR124_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717C )
|
|---|
| 777 | #define ICU_ISELR125_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717D )
|
|---|
| 778 | #define ICU_ISELR126_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717E )
|
|---|
| 779 | #define ICU_ISELR127_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717F )
|
|---|
| 780 | #define ICU_ISELR128_ADDR ( ( volatile uint8_t __evenaccess * )0x00087180 )
|
|---|
| 781 | #define ICU_ISELR129_ADDR ( ( volatile uint8_t __evenaccess * )0x00087181 )
|
|---|
| 782 | #define ICU_ISELR130_ADDR ( ( volatile uint8_t __evenaccess * )0x00087182 )
|
|---|
| 783 | #define ICU_ISELR131_ADDR ( ( volatile uint8_t __evenaccess * )0x00087183 )
|
|---|
| 784 | #define ICU_ISELR132_ADDR ( ( volatile uint8_t __evenaccess * )0x00087184 )
|
|---|
| 785 | #define ICU_ISELR133_ADDR ( ( volatile uint8_t __evenaccess * )0x00087185 )
|
|---|
| 786 | #define ICU_ISELR134_ADDR ( ( volatile uint8_t __evenaccess * )0x00087186 )
|
|---|
| 787 | #define ICU_ISELR135_ADDR ( ( volatile uint8_t __evenaccess * )0x00087187 )
|
|---|
| 788 | #define ICU_ISELR136_ADDR ( ( volatile uint8_t __evenaccess * )0x00087188 )
|
|---|
| 789 | #define ICU_ISELR137_ADDR ( ( volatile uint8_t __evenaccess * )0x00087189 )
|
|---|
| 790 | #define ICU_ISELR138_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718A )
|
|---|
| 791 | #define ICU_ISELR139_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718B )
|
|---|
| 792 | #define ICU_ISELR140_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718C )
|
|---|
| 793 | #define ICU_ISELR141_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718D )
|
|---|
| 794 | #define ICU_ISELR142_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718E )
|
|---|
| 795 | #define ICU_ISELR143_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718F )
|
|---|
| 796 | #define ICU_ISELR144_ADDR ( ( volatile uint8_t __evenaccess * )0x00087190 )
|
|---|
| 797 | #define ICU_ISELR145_ADDR ( ( volatile uint8_t __evenaccess * )0x00087191 )
|
|---|
| 798 | #define ICU_ISELR146_ADDR ( ( volatile uint8_t __evenaccess * )0x00087192 )
|
|---|
| 799 | #define ICU_ISELR147_ADDR ( ( volatile uint8_t __evenaccess * )0x00087193 )
|
|---|
| 800 | #define ICU_ISELR148_ADDR ( ( volatile uint8_t __evenaccess * )0x00087194 )
|
|---|
| 801 | #define ICU_ISELR149_ADDR ( ( volatile uint8_t __evenaccess * )0x00087195 )
|
|---|
| 802 | #define ICU_ISELR150_ADDR ( ( volatile uint8_t __evenaccess * )0x00087196 )
|
|---|
| 803 | #define ICU_ISELR151_ADDR ( ( volatile uint8_t __evenaccess * )0x00087197 )
|
|---|
| 804 | #define ICU_ISELR152_ADDR ( ( volatile uint8_t __evenaccess * )0x00087198 )
|
|---|
| 805 | #define ICU_ISELR153_ADDR ( ( volatile uint8_t __evenaccess * )0x00087199 )
|
|---|
| 806 | #define ICU_ISELR154_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719A )
|
|---|
| 807 | #define ICU_ISELR155_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719B )
|
|---|
| 808 | #define ICU_ISELR156_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719C )
|
|---|
| 809 | #define ICU_ISELR157_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719D )
|
|---|
| 810 | #define ICU_ISELR158_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719E )
|
|---|
| 811 | #define ICU_ISELR159_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719F )
|
|---|
| 812 | #define ICU_ISELR160_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A0 )
|
|---|
| 813 | #define ICU_ISELR161_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A1 )
|
|---|
| 814 | #define ICU_ISELR162_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A2 )
|
|---|
| 815 | #define ICU_ISELR163_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A3 )
|
|---|
| 816 | #define ICU_ISELR164_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A4 )
|
|---|
| 817 | #define ICU_ISELR165_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A5 )
|
|---|
| 818 | #define ICU_ISELR166_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A6 )
|
|---|
| 819 | #define ICU_ISELR167_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A7 )
|
|---|
| 820 | #define ICU_ISELR168_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A8 )
|
|---|
| 821 | #define ICU_ISELR169_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A9 )
|
|---|
| 822 | #define ICU_ISELR170_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AA )
|
|---|
| 823 | #define ICU_ISELR171_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AB )
|
|---|
| 824 | #define ICU_ISELR172_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AC )
|
|---|
| 825 | #define ICU_ISELR173_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AD )
|
|---|
| 826 | #define ICU_ISELR174_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AE )
|
|---|
| 827 | #define ICU_ISELR175_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AF )
|
|---|
| 828 | #define ICU_ISELR176_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B0 )
|
|---|
| 829 | #define ICU_ISELR177_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B1 )
|
|---|
| 830 | #define ICU_ISELR178_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B2 )
|
|---|
| 831 | #define ICU_ISELR179_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B3 )
|
|---|
| 832 | #define ICU_ISELR180_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B4 )
|
|---|
| 833 | #define ICU_ISELR181_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B5 )
|
|---|
| 834 | #define ICU_ISELR182_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B6 )
|
|---|
| 835 | #define ICU_ISELR183_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B7 )
|
|---|
| 836 | #define ICU_ISELR184_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B8 )
|
|---|
| 837 | #define ICU_ISELR185_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B9 )
|
|---|
| 838 | #define ICU_ISELR186_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BA )
|
|---|
| 839 | #define ICU_ISELR187_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BB )
|
|---|
| 840 | #define ICU_ISELR188_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BC )
|
|---|
| 841 | #define ICU_ISELR189_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BD )
|
|---|
| 842 | #define ICU_ISELR190_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BE )
|
|---|
| 843 | #define ICU_ISELR191_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BF )
|
|---|
| 844 | #define ICU_ISELR192_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C0 )
|
|---|
| 845 | #define ICU_ISELR193_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C1 )
|
|---|
| 846 | #define ICU_ISELR194_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C2 )
|
|---|
| 847 | #define ICU_ISELR195_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C3 )
|
|---|
| 848 | #define ICU_ISELR196_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C4 )
|
|---|
| 849 | #define ICU_ISELR197_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C5 )
|
|---|
| 850 | #define ICU_ISELR198_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C6 )
|
|---|
| 851 | #define ICU_ISELR199_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C7 )
|
|---|
| 852 | #define ICU_ISELR200_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C8 )
|
|---|
| 853 | #define ICU_ISELR201_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C9 )
|
|---|
| 854 | #define ICU_ISELR202_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CA )
|
|---|
| 855 | #define ICU_ISELR203_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CB )
|
|---|
| 856 | #define ICU_ISELR204_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CC )
|
|---|
| 857 | #define ICU_ISELR205_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CD )
|
|---|
| 858 | #define ICU_ISELR206_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CE )
|
|---|
| 859 | #define ICU_ISELR207_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CF )
|
|---|
| 860 | #define ICU_ISELR208_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D0 )
|
|---|
| 861 | #define ICU_ISELR209_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D1 )
|
|---|
| 862 | #define ICU_ISELR210_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D2 )
|
|---|
| 863 | #define ICU_ISELR211_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D3 )
|
|---|
| 864 | #define ICU_ISELR212_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D4 )
|
|---|
| 865 | #define ICU_ISELR213_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D5 )
|
|---|
| 866 | #define ICU_ISELR214_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D6 )
|
|---|
| 867 | #define ICU_ISELR215_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D7 )
|
|---|
| 868 | #define ICU_ISELR216_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D8 )
|
|---|
| 869 | #define ICU_ISELR217_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D9 )
|
|---|
| 870 | #define ICU_ISELR218_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DA )
|
|---|
| 871 | #define ICU_ISELR219_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DB )
|
|---|
| 872 | #define ICU_ISELR220_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DC )
|
|---|
| 873 | #define ICU_ISELR221_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DD )
|
|---|
| 874 | #define ICU_ISELR222_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DE )
|
|---|
| 875 | #define ICU_ISELR223_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DF )
|
|---|
| 876 | #define ICU_ISELR224_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E0 )
|
|---|
| 877 | #define ICU_ISELR225_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E1 )
|
|---|
| 878 | #define ICU_ISELR226_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E2 )
|
|---|
| 879 | #define ICU_ISELR227_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E3 )
|
|---|
| 880 | #define ICU_ISELR228_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E4 )
|
|---|
| 881 | #define ICU_ISELR229_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E5 )
|
|---|
| 882 | #define ICU_ISELR230_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E6 )
|
|---|
| 883 | #define ICU_ISELR231_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E7 )
|
|---|
| 884 | #define ICU_ISELR232_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E8 )
|
|---|
| 885 | #define ICU_ISELR233_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E9 )
|
|---|
| 886 | #define ICU_ISELR234_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EA )
|
|---|
| 887 | #define ICU_ISELR235_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EB )
|
|---|
| 888 | #define ICU_ISELR236_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EC )
|
|---|
| 889 | #define ICU_ISELR237_ADDR ( ( volatile uint8_t __evenaccess * )0x000871ED )
|
|---|
| 890 | #define ICU_ISELR238_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EE )
|
|---|
| 891 | #define ICU_ISELR239_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EF )
|
|---|
| 892 | #define ICU_ISELR240_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F0 )
|
|---|
| 893 | #define ICU_ISELR241_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F1 )
|
|---|
| 894 | #define ICU_ISELR242_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F2 )
|
|---|
| 895 | #define ICU_ISELR243_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F3 )
|
|---|
| 896 | #define ICU_ISELR244_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F4 )
|
|---|
| 897 | #define ICU_ISELR245_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F5 )
|
|---|
| 898 | #define ICU_ISELR246_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F6 )
|
|---|
| 899 | #define ICU_ISELR247_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F7 )
|
|---|
| 900 | #define ICU_ISELR248_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F8 )
|
|---|
| 901 | #define ICU_ISELR249_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F9 )
|
|---|
| 902 | #define ICU_ISELR250_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FA )
|
|---|
| 903 | #define ICU_ISELR251_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FB )
|
|---|
| 904 | #define ICU_ISELR252_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FC )
|
|---|
| 905 | #define ICU_ISELR253_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FD )
|
|---|
| 906 | #define ICU_ISELR254_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FE )
|
|---|
| 907 | #define ICU_ISELR255_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FF )
|
|---|
| 908 | #define ICU_ISEL_BIT ( 3U << 0U )
|
|---|
| 909 |
|
|---|
| 910 | /*
|
|---|
| 911 | * 割り込み要求許可レジスタ
|
|---|
| 912 | */
|
|---|
| 913 | #define ICU_IER02_ADDR ( ( volatile uint8_t __evenaccess * )0x00087202 )
|
|---|
| 914 | #define ICU_IER03_ADDR ( ( volatile uint8_t __evenaccess * )0x00087203 )
|
|---|
| 915 | #define ICU_IER04_ADDR ( ( volatile uint8_t __evenaccess * )0x00087204 )
|
|---|
| 916 | #define ICU_IER05_ADDR ( ( volatile uint8_t __evenaccess * )0x00087205 )
|
|---|
| 917 | #define ICU_IER06_ADDR ( ( volatile uint8_t __evenaccess * )0x00087206 )
|
|---|
| 918 | #define ICU_IER07_ADDR ( ( volatile uint8_t __evenaccess * )0x00087207 )
|
|---|
| 919 | #define ICU_IER08_ADDR ( ( volatile uint8_t __evenaccess * )0x00087208 )
|
|---|
| 920 | #define ICU_IER09_ADDR ( ( volatile uint8_t __evenaccess * )0x00087209 )
|
|---|
| 921 | #define ICU_IER0B_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720B )
|
|---|
| 922 | #define ICU_IER0C_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720C )
|
|---|
| 923 | #define ICU_IER0D_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720D )
|
|---|
| 924 | #define ICU_IER0E_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720E )
|
|---|
| 925 | #define ICU_IER0F_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720F )
|
|---|
| 926 | #define ICU_IER10_ADDR ( ( volatile uint8_t __evenaccess * )0x00087210 )
|
|---|
| 927 | #define ICU_IER11_ADDR ( ( volatile uint8_t __evenaccess * )0x00087211 )
|
|---|
| 928 | #define ICU_IER12_ADDR ( ( volatile uint8_t __evenaccess * )0x00087212 )
|
|---|
| 929 | #define ICU_IER13_ADDR ( ( volatile uint8_t __evenaccess * )0x00087213 )
|
|---|
| 930 | #define ICU_IER14_ADDR ( ( volatile uint8_t __evenaccess * )0x00087214 )
|
|---|
| 931 | #define ICU_IER15_ADDR ( ( volatile uint8_t __evenaccess * )0x00087215 )
|
|---|
| 932 | #define ICU_IER16_ADDR ( ( volatile uint8_t __evenaccess * )0x00087216 )
|
|---|
| 933 | #define ICU_IER17_ADDR ( ( volatile uint8_t __evenaccess * )0x00087217 )
|
|---|
| 934 | #define ICU_IER18_ADDR ( ( volatile uint8_t __evenaccess * )0x00087218 )
|
|---|
| 935 | #define ICU_IER19_ADDR ( ( volatile uint8_t __evenaccess * )0x00087219 )
|
|---|
| 936 | #define ICU_IER1A_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721A )
|
|---|
| 937 | #define ICU_IER1B_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721B )
|
|---|
| 938 | #define ICU_IER1C_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721C )
|
|---|
| 939 | #define ICU_IER1D_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721D )
|
|---|
| 940 | #define ICU_IER1E_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721E )
|
|---|
| 941 | #define ICU_IER1F_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721F )
|
|---|
| 942 | #define ICU_IEN0_BIT ( 1U << 0U )
|
|---|
| 943 | #define ICU_IEN1_BIT ( 1U << 1U )
|
|---|
| 944 | #define ICU_IEN2_BIT ( 1U << 2U )
|
|---|
| 945 | #define ICU_IEN3_BIT ( 1U << 3U )
|
|---|
| 946 | #define ICU_IEN4_BIT ( 1U << 4U )
|
|---|
| 947 | #define ICU_IEN5_BIT ( 1U << 5U )
|
|---|
| 948 | #define ICU_IEN6_BIT ( 1U << 6U )
|
|---|
| 949 | #define ICU_IEN7_BIT ( 1U << 7U )
|
|---|
| 950 |
|
|---|
| 951 | /*
|
|---|
| 952 | * 割り込み要因プライオリティレジスタi(i=0〜253)の設定
|
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| 953 | */
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| 954 | #define ICU_IPR000_ADDR ( ( volatile uint8_t __evenaccess * )0x00087300 )
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| 955 | #define ICU_IPR001_ADDR ( ( volatile uint8_t __evenaccess * )0x00087301 )
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| 956 | #define ICU_IPR002_ADDR ( ( volatile uint8_t __evenaccess * )0x00087302 )
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| 957 | #define ICU_IPR003_ADDR ( ( volatile uint8_t __evenaccess * )0x00087303 )
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| 958 | #define ICU_IPR004_ADDR ( ( volatile uint8_t __evenaccess * )0x00087304 )
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| 959 | #define ICU_IPR005_ADDR ( ( volatile uint8_t __evenaccess * )0x00087305 )
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| 960 | #define ICU_IPR006_ADDR ( ( volatile uint8_t __evenaccess * )0x00087306 )
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| 961 | #define ICU_IPR007_ADDR ( ( volatile uint8_t __evenaccess * )0x00087307 )
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| 962 | #define ICU_IPR008_ADDR ( ( volatile uint8_t __evenaccess * )0x00087308 )
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| 963 | #define ICU_IPR009_ADDR ( ( volatile uint8_t __evenaccess * )0x00087309 )
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| 964 | #define ICU_IPR010_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730A )
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| 965 | #define ICU_IPR011_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730B )
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| 966 | #define ICU_IPR012_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730C )
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| 967 | #define ICU_IPR013_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730D )
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| 968 | #define ICU_IPR014_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730E )
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| 969 | #define ICU_IPR015_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730F )
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| 970 | #define ICU_IPR016_ADDR ( ( volatile uint8_t __evenaccess * )0x00087310 )
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| 971 | #define ICU_IPR017_ADDR ( ( volatile uint8_t __evenaccess * )0x00087311 )
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| 972 | #define ICU_IPR018_ADDR ( ( volatile uint8_t __evenaccess * )0x00087312 )
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| 973 | #define ICU_IPR019_ADDR ( ( volatile uint8_t __evenaccess * )0x00087313 )
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| 974 | #define ICU_IPR020_ADDR ( ( volatile uint8_t __evenaccess * )0x00087314 )
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| 975 | #define ICU_IPR021_ADDR ( ( volatile uint8_t __evenaccess * )0x00087315 )
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| 976 | #define ICU_IPR022_ADDR ( ( volatile uint8_t __evenaccess * )0x00087316 )
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| 977 | #define ICU_IPR023_ADDR ( ( volatile uint8_t __evenaccess * )0x00087317 )
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| 978 | #define ICU_IPR024_ADDR ( ( volatile uint8_t __evenaccess * )0x00087318 )
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| 979 | #define ICU_IPR025_ADDR ( ( volatile uint8_t __evenaccess * )0x00087319 )
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| 980 | #define ICU_IPR026_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731A )
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| 981 | #define ICU_IPR027_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731B )
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| 982 | #define ICU_IPR028_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731C )
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| 983 | #define ICU_IPR029_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731D )
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| 984 | #define ICU_IPR030_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731E )
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| 985 | #define ICU_IPR031_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731F )
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| 986 | #define ICU_IPR032_ADDR ( ( volatile uint8_t __evenaccess * )0x00087320 )
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| 987 | #define ICU_IPR033_ADDR ( ( volatile uint8_t __evenaccess * )0x00087321 )
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| 988 | #define ICU_IPR034_ADDR ( ( volatile uint8_t __evenaccess * )0x00087322 )
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| 989 | #define ICU_IPR035_ADDR ( ( volatile uint8_t __evenaccess * )0x00087323 )
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| 990 | #define ICU_IPR036_ADDR ( ( volatile uint8_t __evenaccess * )0x00087324 )
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| 991 | #define ICU_IPR037_ADDR ( ( volatile uint8_t __evenaccess * )0x00087325 )
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| 992 | #define ICU_IPR038_ADDR ( ( volatile uint8_t __evenaccess * )0x00087326 )
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| 993 | #define ICU_IPR039_ADDR ( ( volatile uint8_t __evenaccess * )0x00087327 )
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| 994 | #define ICU_IPR040_ADDR ( ( volatile uint8_t __evenaccess * )0x00087328 )
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| 995 | #define ICU_IPR041_ADDR ( ( volatile uint8_t __evenaccess * )0x00087329 )
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| 996 | #define ICU_IPR042_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732A )
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| 997 | #define ICU_IPR043_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732B )
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| 998 | #define ICU_IPR044_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732C )
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| 999 | #define ICU_IPR045_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732D )
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| 1000 | #define ICU_IPR046_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732E )
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| 1001 | #define ICU_IPR047_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732F )
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| 1002 | #define ICU_IPR048_ADDR ( ( volatile uint8_t __evenaccess * )0x00087330 )
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| 1003 | #define ICU_IPR049_ADDR ( ( volatile uint8_t __evenaccess * )0x00087331 )
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| 1004 | #define ICU_IPR050_ADDR ( ( volatile uint8_t __evenaccess * )0x00087332 )
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| 1005 | #define ICU_IPR051_ADDR ( ( volatile uint8_t __evenaccess * )0x00087333 )
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| 1006 | #define ICU_IPR052_ADDR ( ( volatile uint8_t __evenaccess * )0x00087334 )
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| 1007 | #define ICU_IPR053_ADDR ( ( volatile uint8_t __evenaccess * )0x00087335 )
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| 1008 | #define ICU_IPR054_ADDR ( ( volatile uint8_t __evenaccess * )0x00087336 )
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| 1009 | #define ICU_IPR055_ADDR ( ( volatile uint8_t __evenaccess * )0x00087337 )
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| 1010 | #define ICU_IPR056_ADDR ( ( volatile uint8_t __evenaccess * )0x00087338 )
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| 1011 | #define ICU_IPR057_ADDR ( ( volatile uint8_t __evenaccess * )0x00087339 )
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| 1012 | #define ICU_IPR058_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733A )
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| 1013 | #define ICU_IPR059_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733B )
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| 1014 | #define ICU_IPR060_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733C )
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| 1015 | #define ICU_IPR061_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733D )
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| 1016 | #define ICU_IPR062_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733E )
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| 1017 | #define ICU_IPR063_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733F )
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| 1018 | #define ICU_IPR064_ADDR ( ( volatile uint8_t __evenaccess * )0x00087340 )
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| 1019 | #define ICU_IPR065_ADDR ( ( volatile uint8_t __evenaccess * )0x00087341 )
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| 1020 | #define ICU_IPR066_ADDR ( ( volatile uint8_t __evenaccess * )0x00087342 )
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| 1021 | #define ICU_IPR067_ADDR ( ( volatile uint8_t __evenaccess * )0x00087343 )
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| 1022 | #define ICU_IPR068_ADDR ( ( volatile uint8_t __evenaccess * )0x00087344 )
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| 1023 | #define ICU_IPR069_ADDR ( ( volatile uint8_t __evenaccess * )0x00087345 )
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| 1024 | #define ICU_IPR070_ADDR ( ( volatile uint8_t __evenaccess * )0x00087346 )
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| 1025 | #define ICU_IPR071_ADDR ( ( volatile uint8_t __evenaccess * )0x00087347 )
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| 1026 | #define ICU_IPR072_ADDR ( ( volatile uint8_t __evenaccess * )0x00087348 )
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| 1027 | #define ICU_IPR073_ADDR ( ( volatile uint8_t __evenaccess * )0x00087349 )
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| 1028 | #define ICU_IPR074_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734A )
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| 1029 | #define ICU_IPR075_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734B )
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| 1030 | #define ICU_IPR076_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734C )
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| 1031 | #define ICU_IPR077_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734D )
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| 1032 | #define ICU_IPR078_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734E )
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| 1033 | #define ICU_IPR079_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734F )
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| 1034 | #define ICU_IPR080_ADDR ( ( volatile uint8_t __evenaccess * )0x00087350 )
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| 1035 | #define ICU_IPR081_ADDR ( ( volatile uint8_t __evenaccess * )0x00087351 )
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| 1036 | #define ICU_IPR082_ADDR ( ( volatile uint8_t __evenaccess * )0x00087352 )
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| 1037 | #define ICU_IPR083_ADDR ( ( volatile uint8_t __evenaccess * )0x00087353 )
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| 1038 | #define ICU_IPR084_ADDR ( ( volatile uint8_t __evenaccess * )0x00087354 )
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| 1039 | #define ICU_IPR085_ADDR ( ( volatile uint8_t __evenaccess * )0x00087355 )
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| 1040 | #define ICU_IPR086_ADDR ( ( volatile uint8_t __evenaccess * )0x00087356 )
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| 1041 | #define ICU_IPR087_ADDR ( ( volatile uint8_t __evenaccess * )0x00087357 )
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| 1042 | #define ICU_IPR088_ADDR ( ( volatile uint8_t __evenaccess * )0x00087358 )
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| 1043 | #define ICU_IPR089_ADDR ( ( volatile uint8_t __evenaccess * )0x00087359 )
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| 1044 | #define ICU_IPR090_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735A )
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| 1045 | #define ICU_IPR091_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735B )
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| 1046 | #define ICU_IPR092_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735C )
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| 1047 | #define ICU_IPR093_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735D )
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| 1048 | #define ICU_IPR094_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735E )
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| 1049 | #define ICU_IPR095_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735F )
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| 1050 | #define ICU_IPR096_ADDR ( ( volatile uint8_t __evenaccess * )0x00087360 )
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| 1051 | #define ICU_IPR097_ADDR ( ( volatile uint8_t __evenaccess * )0x00087361 )
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| 1052 | #define ICU_IPR098_ADDR ( ( volatile uint8_t __evenaccess * )0x00087362 )
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| 1053 | #define ICU_IPR099_ADDR ( ( volatile uint8_t __evenaccess * )0x00087363 )
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| 1054 | #define ICU_IPR100_ADDR ( ( volatile uint8_t __evenaccess * )0x00087364 )
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| 1055 | #define ICU_IPR101_ADDR ( ( volatile uint8_t __evenaccess * )0x00087365 )
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| 1056 | #define ICU_IPR102_ADDR ( ( volatile uint8_t __evenaccess * )0x00087366 )
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| 1057 | #define ICU_IPR103_ADDR ( ( volatile uint8_t __evenaccess * )0x00087367 )
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| 1058 | #define ICU_IPR104_ADDR ( ( volatile uint8_t __evenaccess * )0x00087368 )
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| 1059 | #define ICU_IPR105_ADDR ( ( volatile uint8_t __evenaccess * )0x00087369 )
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| 1060 | #define ICU_IPR106_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736A )
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| 1061 | #define ICU_IPR107_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736B )
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| 1062 | #define ICU_IPR108_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736C )
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| 1063 | #define ICU_IPR109_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736D )
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| 1064 | #define ICU_IPR110_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736E )
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| 1065 | #define ICU_IPR111_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736F )
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| 1066 | #define ICU_IPR112_ADDR ( ( volatile uint8_t __evenaccess * )0x00087370 )
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| 1067 | #define ICU_IPR113_ADDR ( ( volatile uint8_t __evenaccess * )0x00087371 )
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| 1068 | #define ICU_IPR114_ADDR ( ( volatile uint8_t __evenaccess * )0x00087372 )
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| 1069 | #define ICU_IPR115_ADDR ( ( volatile uint8_t __evenaccess * )0x00087373 )
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| 1070 | #define ICU_IPR116_ADDR ( ( volatile uint8_t __evenaccess * )0x00087374 )
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| 1071 | #define ICU_IPR117_ADDR ( ( volatile uint8_t __evenaccess * )0x00087375 )
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| 1072 | #define ICU_IPR118_ADDR ( ( volatile uint8_t __evenaccess * )0x00087376 )
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| 1073 | #define ICU_IPR119_ADDR ( ( volatile uint8_t __evenaccess * )0x00087377 )
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| 1074 | #define ICU_IPR120_ADDR ( ( volatile uint8_t __evenaccess * )0x00087378 )
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| 1075 | #define ICU_IPR121_ADDR ( ( volatile uint8_t __evenaccess * )0x00087379 )
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| 1076 | #define ICU_IPR122_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737A )
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| 1077 | #define ICU_IPR123_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737B )
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| 1078 | #define ICU_IPR124_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737C )
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| 1079 | #define ICU_IPR125_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737D )
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| 1080 | #define ICU_IPR126_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737E )
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| 1081 | #define ICU_IPR127_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737F )
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| 1082 | #define ICU_IPR128_ADDR ( ( volatile uint8_t __evenaccess * )0x00087380 )
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| 1083 | #define ICU_IPR129_ADDR ( ( volatile uint8_t __evenaccess * )0x00087381 )
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| 1084 | #define ICU_IPR130_ADDR ( ( volatile uint8_t __evenaccess * )0x00087382 )
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| 1085 | #define ICU_IPR131_ADDR ( ( volatile uint8_t __evenaccess * )0x00087383 )
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| 1086 | #define ICU_IPR132_ADDR ( ( volatile uint8_t __evenaccess * )0x00087384 )
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| 1087 | #define ICU_IPR133_ADDR ( ( volatile uint8_t __evenaccess * )0x00087385 )
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| 1088 | #define ICU_IPR134_ADDR ( ( volatile uint8_t __evenaccess * )0x00087386 )
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| 1089 | #define ICU_IPR135_ADDR ( ( volatile uint8_t __evenaccess * )0x00087387 )
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| 1090 | #define ICU_IPR136_ADDR ( ( volatile uint8_t __evenaccess * )0x00087388 )
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| 1091 | #define ICU_IPR137_ADDR ( ( volatile uint8_t __evenaccess * )0x00087389 )
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| 1092 | #define ICU_IPR138_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738A )
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| 1093 | #define ICU_IPR139_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738B )
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| 1094 | #define ICU_IPR140_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738C )
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| 1095 | #define ICU_IPR141_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738D )
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| 1096 | #define ICU_IPR142_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738E )
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| 1097 | #define ICU_IPR143_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738F )
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| 1098 | #define ICU_IPR144_ADDR ( ( volatile uint8_t __evenaccess * )0x00087390 )
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| 1099 | #define ICU_IPR145_ADDR ( ( volatile uint8_t __evenaccess * )0x00087391 )
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| 1100 | #define ICU_IPR146_ADDR ( ( volatile uint8_t __evenaccess * )0x00087392 )
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| 1101 | #define ICU_IPR147_ADDR ( ( volatile uint8_t __evenaccess * )0x00087393 )
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| 1102 | #define ICU_IPR148_ADDR ( ( volatile uint8_t __evenaccess * )0x00087394 )
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| 1103 | #define ICU_IPR149_ADDR ( ( volatile uint8_t __evenaccess * )0x00087395 )
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| 1104 | #define ICU_IPR150_ADDR ( ( volatile uint8_t __evenaccess * )0x00087396 )
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| 1105 | #define ICU_IPR151_ADDR ( ( volatile uint8_t __evenaccess * )0x00087397 )
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| 1106 | #define ICU_IPR152_ADDR ( ( volatile uint8_t __evenaccess * )0x00087398 )
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| 1107 | #define ICU_IPR153_ADDR ( ( volatile uint8_t __evenaccess * )0x00087399 )
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| 1108 | #define ICU_IPR154_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739A )
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| 1109 | #define ICU_IPR155_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739B )
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| 1110 | #define ICU_IPR156_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739C )
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| 1111 | #define ICU_IPR157_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739D )
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| 1112 | #define ICU_IPR158_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739E )
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| 1113 | #define ICU_IPR159_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739F )
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| 1114 | #define ICU_IPR160_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A0 )
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| 1115 | #define ICU_IPR161_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A1 )
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| 1116 | #define ICU_IPR162_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A2 )
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| 1117 | #define ICU_IPR163_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A3 )
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| 1118 | #define ICU_IPR164_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A4 )
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| 1119 | #define ICU_IPR165_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A5 )
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| 1120 | #define ICU_IPR166_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A6 )
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| 1121 | #define ICU_IPR167_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A7 )
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| 1122 | #define ICU_IPR168_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A8 )
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| 1123 | #define ICU_IPR169_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A9 )
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| 1124 | #define ICU_IPR170_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AA )
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| 1125 | #define ICU_IPR171_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AB )
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| 1126 | #define ICU_IPR172_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AC )
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| 1127 | #define ICU_IPR173_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AD )
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| 1128 | #define ICU_IPR174_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AE )
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| 1129 | #define ICU_IPR175_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AF )
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| 1130 | #define ICU_IPR176_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B0 )
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| 1131 | #define ICU_IPR177_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B1 )
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| 1132 | #define ICU_IPR178_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B2 )
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| 1133 | #define ICU_IPR179_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B3 )
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| 1134 | #define ICU_IPR180_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B4 )
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| 1135 | #define ICU_IPR181_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B5 )
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| 1136 | #define ICU_IPR182_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B6 )
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| 1137 | #define ICU_IPR183_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B7 )
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| 1138 | #define ICU_IPR184_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B8 )
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| 1139 | #define ICU_IPR185_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B9 )
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| 1140 | #define ICU_IPR186_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BA )
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| 1141 | #define ICU_IPR187_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BB )
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| 1142 | #define ICU_IPR188_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BC )
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| 1143 | #define ICU_IPR189_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BD )
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| 1144 | #define ICU_IPR190_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BE )
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| 1145 | #define ICU_IPR191_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BF )
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| 1146 | #define ICU_IPR192_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C0 )
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| 1147 | #define ICU_IPR193_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C1 )
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| 1148 | #define ICU_IPR194_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C2 )
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| 1149 | #define ICU_IPR195_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C3 )
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| 1150 | #define ICU_IPR196_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C4 )
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| 1151 | #define ICU_IPR197_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C5 )
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| 1152 | #define ICU_IPR198_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C6 )
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| 1153 | #define ICU_IPR199_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C7 )
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| 1154 | #define ICU_IPR200_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C8 )
|
|---|
| 1155 | #define ICU_IPR201_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C9 )
|
|---|
| 1156 | #define ICU_IPR202_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CA )
|
|---|
| 1157 | #define ICU_IPR203_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CB )
|
|---|
| 1158 | #define ICU_IPR204_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CC )
|
|---|
| 1159 | #define ICU_IPR205_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CD )
|
|---|
| 1160 | #define ICU_IPR206_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CE )
|
|---|
| 1161 | #define ICU_IPR207_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CF )
|
|---|
| 1162 | #define ICU_IPR208_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D0 )
|
|---|
| 1163 | #define ICU_IPR209_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D1 )
|
|---|
| 1164 | #define ICU_IPR210_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D2 )
|
|---|
| 1165 | #define ICU_IPR211_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D3 )
|
|---|
| 1166 | #define ICU_IPR212_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D4 )
|
|---|
| 1167 | #define ICU_IPR213_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D5 )
|
|---|
| 1168 | #define ICU_IPR214_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D6 )
|
|---|
| 1169 | #define ICU_IPR215_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D7 )
|
|---|
| 1170 | #define ICU_IPR216_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D8 )
|
|---|
| 1171 | #define ICU_IPR217_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D9 )
|
|---|
| 1172 | #define ICU_IPR218_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DA )
|
|---|
| 1173 | #define ICU_IPR219_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DB )
|
|---|
| 1174 | #define ICU_IPR220_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DC )
|
|---|
| 1175 | #define ICU_IPR221_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DD )
|
|---|
| 1176 | #define ICU_IPR222_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DE )
|
|---|
| 1177 | #define ICU_IPR223_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DF )
|
|---|
| 1178 | #define ICU_IPR224_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E0 )
|
|---|
| 1179 | #define ICU_IPR225_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E1 )
|
|---|
| 1180 | #define ICU_IPR226_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E2 )
|
|---|
| 1181 | #define ICU_IPR227_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E3 )
|
|---|
| 1182 | #define ICU_IPR228_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E4 )
|
|---|
| 1183 | #define ICU_IPR229_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E5 )
|
|---|
| 1184 | #define ICU_IPR230_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E6 )
|
|---|
| 1185 | #define ICU_IPR231_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E7 )
|
|---|
| 1186 | #define ICU_IPR232_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E8 )
|
|---|
| 1187 | #define ICU_IPR233_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E9 )
|
|---|
| 1188 | #define ICU_IPR234_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EA )
|
|---|
| 1189 | #define ICU_IPR235_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EB )
|
|---|
| 1190 | #define ICU_IPR236_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EC )
|
|---|
| 1191 | #define ICU_IPR237_ADDR ( ( volatile uint8_t __evenaccess * )0x000873ED )
|
|---|
| 1192 | #define ICU_IPR238_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EE )
|
|---|
| 1193 | #define ICU_IPR239_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EF )
|
|---|
| 1194 | #define ICU_IPR240_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F0 )
|
|---|
| 1195 | #define ICU_IPR241_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F1 )
|
|---|
| 1196 | #define ICU_IPR242_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F2 )
|
|---|
| 1197 | #define ICU_IPR243_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F3 )
|
|---|
| 1198 | #define ICU_IPR244_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F4 )
|
|---|
| 1199 | #define ICU_IPR245_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F5 )
|
|---|
| 1200 | #define ICU_IPR246_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F6 )
|
|---|
| 1201 | #define ICU_IPR247_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F7 )
|
|---|
| 1202 | #define ICU_IPR248_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F8 )
|
|---|
| 1203 | #define ICU_IPR249_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F9 )
|
|---|
| 1204 | #define ICU_IPR250_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FA )
|
|---|
| 1205 | #define ICU_IPR251_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FB )
|
|---|
| 1206 | #define ICU_IPR252_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FC )
|
|---|
| 1207 | #define ICU_IPR253_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FD )
|
|---|
| 1208 | #define ICU_IPR254_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FE )
|
|---|
| 1209 | #define ICU_IPR255_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FF )
|
|---|
| 1210 | #define ICU_IPR_BIT ( 7U << 0U )
|
|---|
| 1211 |
|
|---|
| 1212 |
|
|---|
| 1213 | /*
|
|---|
| 1214 | * IRQコントロールレジスタ
|
|---|
| 1215 | */
|
|---|
| 1216 | #define ICU_IRQ0_ADDR ( ( volatile uint8_t __evenaccess * )0x00087500 )
|
|---|
| 1217 | #define ICU_IRQ1_ADDR ( ( volatile uint8_t __evenaccess * )0x00087501 )
|
|---|
| 1218 | #define ICU_IRQ2_ADDR ( ( volatile uint8_t __evenaccess * )0x00087502 )
|
|---|
| 1219 | #define ICU_IRQ3_ADDR ( ( volatile uint8_t __evenaccess * )0x00087503 )
|
|---|
| 1220 | #define ICU_IRQ4_ADDR ( ( volatile uint8_t __evenaccess * )0x00087504 )
|
|---|
| 1221 | #define ICU_IRQ5_ADDR ( ( volatile uint8_t __evenaccess * )0x00087505 )
|
|---|
| 1222 | #define ICU_IRQ6_ADDR ( ( volatile uint8_t __evenaccess * )0x00087506 )
|
|---|
| 1223 | #define ICU_IRQ7_ADDR ( ( volatile uint8_t __evenaccess * )0x00087507 )
|
|---|
| 1224 | #define ICU_IRQ8_ADDR ( ( volatile uint8_t __evenaccess * )0x00087508 )
|
|---|
| 1225 | #define ICU_IRQ9_ADDR ( ( volatile uint8_t __evenaccess * )0x00087509 )
|
|---|
| 1226 | #define ICU_IRQ10_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750A )
|
|---|
| 1227 | #define ICU_IRQ11_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750B )
|
|---|
| 1228 | #define ICU_IRQ12_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750C )
|
|---|
| 1229 | #define ICU_IRQ13_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750D )
|
|---|
| 1230 | #define ICU_IRQ14_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750E )
|
|---|
| 1231 | #define ICU_IRQ15_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750F )
|
|---|
| 1232 | #define ICU_IRQMD_BIT ( 3U << 2U )
|
|---|
| 1233 |
|
|---|
| 1234 |
|
|---|
| 1235 | /*
|
|---|
| 1236 | * 各チャンネルのレジスタ及び設定ビット情報
|
|---|
| 1237 | */
|
|---|
| 1238 | #define CMT_CMSTR0_ADDR ( ( volatile uint16_t __evenaccess * )0x00088000 )
|
|---|
| 1239 | #define CMT_CMSTR0_STR0_BIT ( 1U << 0U )
|
|---|
| 1240 | #define CMT_CMSTR0_STR1_BIT ( 1U << 1U )
|
|---|
| 1241 | #define CMT_CMSTR1_ADDR ( ( volatile uint16_t __evenaccess * )0x00088010 )
|
|---|
| 1242 | #define CMT_CMSTR1_STR2_BIT ( 1U << 0U )
|
|---|
| 1243 | #define CMT_CMSTR1_STR3_BIT ( 1U << 1U )
|
|---|
| 1244 | #define CMT0_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088002 )
|
|---|
| 1245 | #define CMT0_CMCR_CKS_BIT ( 3U )
|
|---|
| 1246 | #define CMT0_CMCR_CMIE_BIT ( 1U << 6U )
|
|---|
| 1247 | #define CMT1_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088008 )
|
|---|
| 1248 | #define CMT1_CMCR_CKS_BIT ( 3U )
|
|---|
| 1249 | #define CMT1_CMCR_CMIE_BIT ( 1U << 6U )
|
|---|
| 1250 | #define CMT2_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088012 )
|
|---|
| 1251 | #define CMT2_CMCR_CKS_BIT ( 3U)
|
|---|
| 1252 | #define CMT2_CMCR_CMIE_BIT ( 1U << 6U )
|
|---|
| 1253 | #define CMT3_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088018 )
|
|---|
| 1254 | #define CMT3_CMCR_CKS_BIT ( 3U )
|
|---|
| 1255 | #define CMT3_CMCR_CMIE_BIT ( 1U << 6U )
|
|---|
| 1256 | #define CMT0_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x00088004 )
|
|---|
| 1257 | #define CMT1_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x0008800A )
|
|---|
| 1258 | #define CMT2_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x00088014 )
|
|---|
| 1259 | #define CMT3_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x0008801A )
|
|---|
| 1260 | #define CMT0_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088006 )
|
|---|
| 1261 | #define CMT1_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x0008800C )
|
|---|
| 1262 | #define CMT2_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088016 )
|
|---|
| 1263 | #define CMT3_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x0008801C )
|
|---|
| 1264 |
|
|---|
| 1265 | #define SCI0_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A000 )
|
|---|
| 1266 | #define SCI0_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A001 )
|
|---|
| 1267 | #define SCI0_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A002 )
|
|---|
| 1268 | #define SCI0_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A003 )
|
|---|
| 1269 | #define SCI0_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A004 )
|
|---|
| 1270 | #define SCI0_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A005 )
|
|---|
| 1271 | #define SCI0_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A006 )
|
|---|
| 1272 | #define SCI0_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A007 )
|
|---|
| 1273 | #define SCI1_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A020 )
|
|---|
| 1274 | #define SCI1_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A021 )
|
|---|
| 1275 | #define SCI1_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A022 )
|
|---|
| 1276 | #define SCI1_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A023 )
|
|---|
| 1277 | #define SCI1_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A024 )
|
|---|
| 1278 | #define SCI1_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A025 )
|
|---|
| 1279 | #define SCI1_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A026 )
|
|---|
| 1280 | #define SCI1_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A027 )
|
|---|
| 1281 | #define SCI2_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A040 )
|
|---|
| 1282 | #define SCI2_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A041 )
|
|---|
| 1283 | #define SCI2_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A042 )
|
|---|
| 1284 | #define SCI2_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A043 )
|
|---|
| 1285 | #define SCI2_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A044 )
|
|---|
| 1286 | #define SCI2_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A045 )
|
|---|
| 1287 | #define SCI2_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A046 )
|
|---|
| 1288 | #define SCI2_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A047 )
|
|---|
| 1289 | #define SCI3_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A060 )
|
|---|
| 1290 | #define SCI3_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A061 )
|
|---|
| 1291 | #define SCI3_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A062 )
|
|---|
| 1292 | #define SCI3_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A063 )
|
|---|
| 1293 | #define SCI3_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A064 )
|
|---|
| 1294 | #define SCI3_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A065 )
|
|---|
| 1295 | #define SCI3_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A066 )
|
|---|
| 1296 | #define SCI3_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A067 )
|
|---|
| 1297 | #define SCI4_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A080 )
|
|---|
| 1298 | #define SCI4_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A081 )
|
|---|
| 1299 | #define SCI4_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A082 )
|
|---|
| 1300 | #define SCI4_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A083 )
|
|---|
| 1301 | #define SCI4_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A084 )
|
|---|
| 1302 | #define SCI4_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A085 )
|
|---|
| 1303 | #define SCI4_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A086 )
|
|---|
| 1304 | #define SCI4_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A087 )
|
|---|
| 1305 | #define SCI5_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A0 )
|
|---|
| 1306 | #define SCI5_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A1 )
|
|---|
| 1307 | #define SCI5_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A2 )
|
|---|
| 1308 | #define SCI5_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A3 )
|
|---|
| 1309 | #define SCI5_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A4 )
|
|---|
| 1310 | #define SCI5_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A5 )
|
|---|
| 1311 | #define SCI5_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A6 )
|
|---|
| 1312 | #define SCI5_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A7 )
|
|---|
| 1313 | #define SCI6_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C0 )
|
|---|
| 1314 | #define SCI6_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C1 )
|
|---|
| 1315 | #define SCI6_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C2 )
|
|---|
| 1316 | #define SCI6_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C3 )
|
|---|
| 1317 | #define SCI6_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C4 )
|
|---|
| 1318 | #define SCI6_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C5 )
|
|---|
| 1319 | #define SCI6_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C6 )
|
|---|
| 1320 | #define SCI6_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C7 )
|
|---|
| 1321 | #define SCI_SMR_CKS_BIT ( 3U << 0U )
|
|---|
| 1322 | #define SCI_SMR_STOP_BIT ( 1U << 3U )
|
|---|
| 1323 | #define SCI_SMR_PM_BIT ( 1U << 4U )
|
|---|
| 1324 | #define SCI_SMR_PE_BIT ( 1U << 5U )
|
|---|
| 1325 | #define SCI_SMR_CHR_BIT ( 1U << 6U )
|
|---|
| 1326 | #define SCI_SMR_CM_BIT ( 1U << 7U )
|
|---|
| 1327 | #define SCI_SCR_CKE_BIT ( 3U << 0U )
|
|---|
| 1328 | #define SCI_SCR_TEIE_BIT ( 1U << 2U )
|
|---|
| 1329 | #define SCI_SCR_RE_BIT ( 1U << 4U )
|
|---|
| 1330 | #define SCI_SCR_TE_BIT ( 1U << 5U )
|
|---|
| 1331 | #define SCI_SCR_RIE_BIT ( 1U << 6U )
|
|---|
| 1332 | #define SCI_SCR_TIE_BIT ( 1U << 7U )
|
|---|
| 1333 | #define SCI_SSR_TEND_BIT ( 1U << 2U )
|
|---|
| 1334 | #define SCI_SSR_PER_BIT ( 1U << 3U )
|
|---|
| 1335 | #define SCI_SSR_FER_BIT ( 1U << 4U )
|
|---|
| 1336 | #define SCI_SSR_ORER_BIT ( 1U << 5U )
|
|---|
| 1337 | #define SCI_SCMR_SMIF_BIT ( 1U << 0U )
|
|---|
| 1338 | #define SCI_SCMR_SINV_BIT ( 1U << 2U )
|
|---|
| 1339 | #define SCI_SCMR_SDIR_BIT ( 1U << 3U )
|
|---|
| 1340 | #define SCI_SCMR_BCP2_BIT ( 1U << 7U )
|
|---|
| 1341 | #define SCI_SEMR_ACS0_BIT ( 1U << 0U )
|
|---|
| 1342 | #define SCI_SEMR_ABCS_BIT ( 1U << 4U )
|
|---|
| 1343 |
|
|---|
| 1344 | /*
|
|---|
| 1345 | * I/Oポートのレジスタ及び設定ビット情報
|
|---|
| 1346 | */
|
|---|
| 1347 | #define PORT0_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C000 )
|
|---|
| 1348 | #define PORT1_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C001 )
|
|---|
| 1349 | #define PORT2_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C002 )
|
|---|
| 1350 | #define PORT3_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C003 )
|
|---|
| 1351 | #define PORT4_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C004 )
|
|---|
| 1352 | #define PORT5_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C005 )
|
|---|
| 1353 | #define PORT6_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C006 )
|
|---|
| 1354 | #define PORT7_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C007 )
|
|---|
| 1355 | #define PORT8_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C008 )
|
|---|
| 1356 | #define PORT9_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C009 )
|
|---|
| 1357 | #define PORTA_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00A )
|
|---|
| 1358 | #define PORTB_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00B )
|
|---|
| 1359 | #define PORTC_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00C )
|
|---|
| 1360 | #define PORTD_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00D )
|
|---|
| 1361 | #define PORTE_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00E )
|
|---|
| 1362 | #define PORTF_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00F )
|
|---|
| 1363 | #define PORTG_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C010 )
|
|---|
| 1364 | #define PORTJ_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C012 )
|
|---|
| 1365 | #define PORT_PDR_B0_BIT ( 0x01U << 0U )
|
|---|
| 1366 | #define PORT_PDR_B1_BIT ( 0x01U << 1U )
|
|---|
| 1367 | #define PORT_PDR_B2_BIT ( 0x01U << 2U )
|
|---|
| 1368 | #define PORT_PDR_B3_BIT ( 0x01U << 3U )
|
|---|
| 1369 | #define PORT_PDR_B4_BIT ( 0x01U << 4U )
|
|---|
| 1370 | #define PORT_PDR_B5_BIT ( 0x01U << 5U )
|
|---|
| 1371 | #define PORT_PDR_B6_BIT ( 0x01U << 6U )
|
|---|
| 1372 | #define PORT_PDR_B7_BIT ( 0x01U << 7U )
|
|---|
| 1373 | #define PORT0_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C020 )
|
|---|
| 1374 | #define PORT1_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C021 )
|
|---|
| 1375 | #define PORT2_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C022 )
|
|---|
| 1376 | #define PORT3_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C023 )
|
|---|
| 1377 | #define PORT4_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C024 )
|
|---|
| 1378 | #define PORT5_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C025 )
|
|---|
| 1379 | #define PORT6_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C026 )
|
|---|
| 1380 | #define PORT7_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C027 )
|
|---|
| 1381 | #define PORT8_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C028 )
|
|---|
| 1382 | #define PORT9_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C029 )
|
|---|
| 1383 | #define PORTA_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02A )
|
|---|
| 1384 | #define PORTB_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02B )
|
|---|
| 1385 | #define PORTC_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02C )
|
|---|
| 1386 | #define PORTD_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02D )
|
|---|
| 1387 | #define PORTE_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02E )
|
|---|
| 1388 | #define PORTF_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02F )
|
|---|
| 1389 | #define PORTG_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C030 )
|
|---|
| 1390 | #define PORTJ_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C032 )
|
|---|
| 1391 | #define PORT_PODR_B0_BIT ( 0x01U << 0U )
|
|---|
| 1392 | #define PORT_PODR_B1_BIT ( 0x01U << 1U )
|
|---|
| 1393 | #define PORT_PODR_B2_BIT ( 0x01U << 2U )
|
|---|
| 1394 | #define PORT_PODR_B3_BIT ( 0x01U << 3U )
|
|---|
| 1395 | #define PORT_PODR_B4_BIT ( 0x01U << 4U )
|
|---|
| 1396 | #define PORT_PODR_B5_BIT ( 0x01U << 5U )
|
|---|
| 1397 | #define PORT_PODR_B6_BIT ( 0x01U << 6U )
|
|---|
| 1398 | #define PORT_PODR_B7_BIT ( 0x01U << 7U )
|
|---|
| 1399 | #define PORT0_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C040 )
|
|---|
| 1400 | #define PORT1_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C041 )
|
|---|
| 1401 | #define PORT2_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C042 )
|
|---|
| 1402 | #define PORT3_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C043 )
|
|---|
| 1403 | #define PORT4_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C044 )
|
|---|
| 1404 | #define PORT5_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C045 )
|
|---|
| 1405 | #define PORT6_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C046 )
|
|---|
| 1406 | #define PORT7_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C047 )
|
|---|
| 1407 | #define PORT8_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C048 )
|
|---|
| 1408 | #define PORT9_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C049 )
|
|---|
| 1409 | #define PORTA_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04A )
|
|---|
| 1410 | #define PORTB_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04B )
|
|---|
| 1411 | #define PORTC_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04C )
|
|---|
| 1412 | #define PORTD_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04D )
|
|---|
| 1413 | #define PORTE_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04E )
|
|---|
| 1414 | #define PORTF_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04F )
|
|---|
| 1415 | #define PORTG_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C050 )
|
|---|
| 1416 | #define PORTJ_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C052 )
|
|---|
| 1417 | #define PORT_PIDR_B0_BIT ( 0x01U << 0U )
|
|---|
| 1418 | #define PORT_PIDR_B1_BIT ( 0x01U << 1U )
|
|---|
| 1419 | #define PORT_PIDR_B2_BIT ( 0x01U << 2U )
|
|---|
| 1420 | #define PORT_PIDR_B3_BIT ( 0x01U << 3U )
|
|---|
| 1421 | #define PORT_PIDR_B4_BIT ( 0x01U << 4U )
|
|---|
| 1422 | #define PORT_PIDR_B5_BIT ( 0x01U << 5U )
|
|---|
| 1423 | #define PORT_PIDR_B6_BIT ( 0x01U << 6U )
|
|---|
| 1424 | #define PORT_PIDR_B7_BIT ( 0x01U << 7U )
|
|---|
| 1425 | #define PORT0_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C060 )
|
|---|
| 1426 | #define PORT1_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C061 )
|
|---|
| 1427 | #define PORT2_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C062 )
|
|---|
| 1428 | #define PORT3_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C063 )
|
|---|
| 1429 | #define PORT4_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C064 )
|
|---|
| 1430 | #define PORT5_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C065 )
|
|---|
| 1431 | #define PORT6_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C066 )
|
|---|
| 1432 | #define PORT7_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C067 )
|
|---|
| 1433 | #define PORT8_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C068 )
|
|---|
| 1434 | #define PORT9_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C069 )
|
|---|
| 1435 | #define PORTA_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06A )
|
|---|
| 1436 | #define PORTB_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06B )
|
|---|
| 1437 | #define PORTC_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06C )
|
|---|
| 1438 | #define PORTD_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06D )
|
|---|
| 1439 | #define PORTE_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06E )
|
|---|
| 1440 | #define PORTF_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06F )
|
|---|
| 1441 | #define PORTG_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C070 )
|
|---|
| 1442 | #define PORTJ_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C072 )
|
|---|
| 1443 | #define PORT_PMR_B0_BIT ( 0x01U << 0U )
|
|---|
| 1444 | #define PORT_PMR_B1_BIT ( 0x01U << 1U )
|
|---|
| 1445 | #define PORT_PMR_B2_BIT ( 0x01U << 2U )
|
|---|
| 1446 | #define PORT_PMR_B3_BIT ( 0x01U << 3U )
|
|---|
| 1447 | #define PORT_PMR_B4_BIT ( 0x01U << 4U )
|
|---|
| 1448 | #define PORT_PMR_B5_BIT ( 0x01U << 5U )
|
|---|
| 1449 | #define PORT_PMR_B6_BIT ( 0x01U << 6U )
|
|---|
| 1450 | #define PORT_PMR_B7_BIT ( 0x01U << 7U )
|
|---|
| 1451 | #define PORT0_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C0 )
|
|---|
| 1452 | #define PORT1_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C1 )
|
|---|
| 1453 | #define PORT2_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C2 )
|
|---|
| 1454 | #define PORT3_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C3 )
|
|---|
| 1455 | #define PORT4_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C4 )
|
|---|
| 1456 | #define PORT5_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C5 )
|
|---|
| 1457 | #define PORT6_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C6 )
|
|---|
| 1458 | #define PORT7_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C7 )
|
|---|
| 1459 | #define PORT8_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C8 )
|
|---|
| 1460 | #define PORT9_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C9 )
|
|---|
| 1461 | #define PORTA_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CA )
|
|---|
| 1462 | #define PORTB_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CB )
|
|---|
| 1463 | #define PORTC_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CC )
|
|---|
| 1464 | #define PORTD_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CD )
|
|---|
| 1465 | #define PORTE_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CE )
|
|---|
| 1466 | #define PORTF_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CF )
|
|---|
| 1467 | #define PORTG_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0D0 )
|
|---|
| 1468 | #define PORTJ_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0D2 )
|
|---|
| 1469 | #define PORT_PCR_B0_BIT ( 0x01U << 0U )
|
|---|
| 1470 | #define PORT_PCR_B1_BIT ( 0x01U << 1U )
|
|---|
| 1471 | #define PORT_PCR_B2_BIT ( 0x01U << 2U )
|
|---|
| 1472 | #define PORT_PCR_B3_BIT ( 0x01U << 3U )
|
|---|
| 1473 | #define PORT_PCR_B4_BIT ( 0x01U << 4U )
|
|---|
| 1474 | #define PORT_PCR_B5_BIT ( 0x01U << 5U )
|
|---|
| 1475 | #define PORT_PCR_B6_BIT ( 0x01U << 6U )
|
|---|
| 1476 | #define PORT_PCR_B7_BIT ( 0x01U << 7U )
|
|---|
| 1477 |
|
|---|
| 1478 | /*
|
|---|
| 1479 | * マルチファンクションピンコントローラのレジスタ情報
|
|---|
| 1480 | */
|
|---|
| 1481 | #define MPC_PFUSB0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C114 )
|
|---|
| 1482 | #define MPC_PFUSB0_PDHZS_BIT ( 0x01U << 2U )
|
|---|
| 1483 | #define MPC_PFUSB0_PUPHZS_BIT ( 0x01U << 3U )
|
|---|
| 1484 | #define MPC_PWPR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C11F )
|
|---|
| 1485 | #define MPC_PWPR_PFSWE ( 0x01U << 6U )
|
|---|
| 1486 | #define MPC_PWPR_B0WI ( 0x01U << 7U )
|
|---|
| 1487 | #define MPC_P00PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C140 )
|
|---|
| 1488 | #define MPC_P01PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C141 )
|
|---|
| 1489 | #define MPC_P02PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C142 )
|
|---|
| 1490 | #define MPC_P03PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C143 )
|
|---|
| 1491 | #define MPC_P04PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C144 )
|
|---|
| 1492 | #define MPC_P05PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C145 )
|
|---|
| 1493 | #define MPC_P06PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C146 )
|
|---|
| 1494 | #define MPC_P07PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C147 )
|
|---|
| 1495 | #define MPC_P10PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C148 )
|
|---|
| 1496 | #define MPC_P11PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C149 )
|
|---|
| 1497 | #define MPC_P12PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14A )
|
|---|
| 1498 | #define MPC_P13PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14B )
|
|---|
| 1499 | #define MPC_P14PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14C )
|
|---|
| 1500 | #define MPC_P15PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14D )
|
|---|
| 1501 | #define MPC_P16PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14E )
|
|---|
| 1502 | #define MPC_P17PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14F )
|
|---|
| 1503 | #define MPC_P20PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C150 )
|
|---|
| 1504 | #define MPC_P21PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C151 )
|
|---|
| 1505 | #define MPC_P22PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C152 )
|
|---|
| 1506 | #define MPC_P23PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C153 )
|
|---|
| 1507 | #define MPC_P24PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C154 )
|
|---|
| 1508 | #define MPC_P25PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C155 )
|
|---|
| 1509 | #define MPC_P26PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C156 )
|
|---|
| 1510 | #define MPC_P27PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C157 )
|
|---|
| 1511 | #define MPC_P30PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C158 )
|
|---|
| 1512 | #define MPC_P31PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C159 )
|
|---|
| 1513 | #define MPC_P32PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15A )
|
|---|
| 1514 | #define MPC_P33PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15B )
|
|---|
| 1515 | #define MPC_P34PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15C )
|
|---|
| 1516 | #define MPC_P35PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15D )
|
|---|
| 1517 | #define MPC_P36PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15E )
|
|---|
| 1518 | #define MPC_P37PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15F )
|
|---|
| 1519 | #define MPC_P40PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C160 )
|
|---|
| 1520 | #define MPC_P41PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C161 )
|
|---|
| 1521 | #define MPC_P42PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C162 )
|
|---|
| 1522 | #define MPC_P43PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C163 )
|
|---|
| 1523 | #define MPC_P44PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C164 )
|
|---|
| 1524 | #define MPC_P45PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C165 )
|
|---|
| 1525 | #define MPC_P46PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C166 )
|
|---|
| 1526 | #define MPC_P47PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C167 )
|
|---|
| 1527 | #define MPC_P50PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C168 )
|
|---|
| 1528 | #define MPC_P51PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C169 )
|
|---|
| 1529 | #define MPC_P52PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16A )
|
|---|
| 1530 | #define MPC_P53PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16B )
|
|---|
| 1531 | #define MPC_P54PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16C )
|
|---|
| 1532 | #define MPC_P55PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16D )
|
|---|
| 1533 | #define MPC_P56PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16E )
|
|---|
| 1534 | #define MPC_P57PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16F )
|
|---|
| 1535 | #define MPC_P60PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C170 )
|
|---|
| 1536 | #define MPC_P61PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C171 )
|
|---|
| 1537 | #define MPC_P62PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C172 )
|
|---|
| 1538 | #define MPC_P63PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C173 )
|
|---|
| 1539 | #define MPC_P64PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C174 )
|
|---|
| 1540 | #define MPC_P65PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C175 )
|
|---|
| 1541 | #define MPC_P66PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C176 )
|
|---|
| 1542 | #define MPC_P67PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C177 )
|
|---|
| 1543 | #define MPC_P70PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C178 )
|
|---|
| 1544 | #define MPC_P71PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C179 )
|
|---|
| 1545 | #define MPC_P72PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17A )
|
|---|
| 1546 | #define MPC_P73PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17B )
|
|---|
| 1547 | #define MPC_P74PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17C )
|
|---|
| 1548 | #define MPC_P75PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17D )
|
|---|
| 1549 | #define MPC_P76PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17E )
|
|---|
| 1550 | #define MPC_P77PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17F )
|
|---|
| 1551 | #define MPC_P80PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C180 )
|
|---|
| 1552 | #define MPC_P81PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C181 )
|
|---|
| 1553 | #define MPC_P82PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C182 )
|
|---|
| 1554 | #define MPC_P83PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C183 )
|
|---|
| 1555 | #define MPC_P84PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C184 )
|
|---|
| 1556 | #define MPC_P85PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C185 )
|
|---|
| 1557 | #define MPC_P86PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C186 )
|
|---|
| 1558 | #define MPC_P87PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C187 )
|
|---|
| 1559 | #define MPC_P90PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C188 )
|
|---|
| 1560 | #define MPC_P91PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C189 )
|
|---|
| 1561 | #define MPC_P92PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18A )
|
|---|
| 1562 | #define MPC_P93PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18B )
|
|---|
| 1563 | #define MPC_P94PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18C )
|
|---|
| 1564 | #define MPC_P95PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18D )
|
|---|
| 1565 | #define MPC_P96PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18E )
|
|---|
| 1566 | #define MPC_P97PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18F )
|
|---|
| 1567 | #define MPC_PA0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C190 )
|
|---|
| 1568 | #define MPC_PA1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C191 )
|
|---|
| 1569 | #define MPC_PA2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C192 )
|
|---|
| 1570 | #define MPC_PA3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C193 )
|
|---|
| 1571 | #define MPC_PA4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C194 )
|
|---|
| 1572 | #define MPC_PA5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C195 )
|
|---|
| 1573 | #define MPC_PA6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C196 )
|
|---|
| 1574 | #define MPC_PA7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C197 )
|
|---|
| 1575 | #define MPC_PB0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C198 )
|
|---|
| 1576 | #define MPC_PB1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C199 )
|
|---|
| 1577 | #define MPC_PB2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19A )
|
|---|
| 1578 | #define MPC_PB3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19B )
|
|---|
| 1579 | #define MPC_PB4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19C )
|
|---|
| 1580 | #define MPC_PB5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19D )
|
|---|
| 1581 | #define MPC_PB6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19E )
|
|---|
| 1582 | #define MPC_PB7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19F )
|
|---|
| 1583 | #define MPC_PC0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A0 )
|
|---|
| 1584 | #define MPC_PC1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A1 )
|
|---|
| 1585 | #define MPC_PC2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A2 )
|
|---|
| 1586 | #define MPC_PC3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A3 )
|
|---|
| 1587 | #define MPC_PC4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A4 )
|
|---|
| 1588 | #define MPC_PC5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A5 )
|
|---|
| 1589 | #define MPC_PC6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A6 )
|
|---|
| 1590 | #define MPC_PC7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A7 )
|
|---|
| 1591 | #define MPC_PD0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A8 )
|
|---|
| 1592 | #define MPC_PD1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A9 )
|
|---|
| 1593 | #define MPC_PD2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AA )
|
|---|
| 1594 | #define MPC_PD3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AB )
|
|---|
| 1595 | #define MPC_PD4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AC )
|
|---|
| 1596 | #define MPC_PD5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AD )
|
|---|
| 1597 | #define MPC_PD6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AE )
|
|---|
| 1598 | #define MPC_PD7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AF )
|
|---|
| 1599 | #define MPC_PE0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B0 )
|
|---|
| 1600 | #define MPC_PE1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B1 )
|
|---|
| 1601 | #define MPC_PE2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B2 )
|
|---|
| 1602 | #define MPC_PE3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B3 )
|
|---|
| 1603 | #define MPC_PE4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B4 )
|
|---|
| 1604 | #define MPC_PE5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B5 )
|
|---|
| 1605 | #define MPC_PE6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B6 )
|
|---|
| 1606 | #define MPC_PE7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B7 )
|
|---|
| 1607 | #define MPC_PF0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B8 )
|
|---|
| 1608 | #define MPC_PF1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B9 )
|
|---|
| 1609 | #define MPC_PF2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BA )
|
|---|
| 1610 | #define MPC_PF3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BB )
|
|---|
| 1611 | #define MPC_PF4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BC )
|
|---|
| 1612 | #define MPC_PF5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BD )
|
|---|
| 1613 | #define MPC_PF6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BE )
|
|---|
| 1614 | #define MPC_PF7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BF )
|
|---|
| 1615 | #define MPC_PJ3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1D3 )
|
|---|
| 1616 |
|
|---|
| 1617 | /*
|
|---|
| 1618 | * リアルタイムクロック
|
|---|
| 1619 | */
|
|---|
| 1620 | #define RTC_R64CNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C400 )
|
|---|
| 1621 | #define RTC_RSECCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C402 )
|
|---|
| 1622 | #define RTC_RMINCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C404 )
|
|---|
| 1623 | #define RTC_RHRCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C406 )
|
|---|
| 1624 | #define RTC_RWKCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C408 )
|
|---|
| 1625 | #define RTC_RDAYCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C40A )
|
|---|
| 1626 | #define RTC_RMONCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C40C )
|
|---|
| 1627 | #define RTC_RYRCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C40E )
|
|---|
| 1628 |
|
|---|
| 1629 | /*
|
|---|
| 1630 | * 12 ビットA/D コンバータ
|
|---|
| 1631 | */
|
|---|
| 1632 | #define S12AD_ADCSR_ADDR ( ( volatile uint8_t __evenaccess * )0x00089000 )
|
|---|
| 1633 | #define S12AD_ADCSR_ADST_BIT 0x80
|
|---|
| 1634 | #define S12AD_ADANS0_ADDR ( ( volatile uint16_t __evenaccess * )0x00089004 )
|
|---|
| 1635 | #define S12AD_ADANS1_ADDR ( ( volatile uint16_t __evenaccess * )0x00089006 )
|
|---|
| 1636 | #define S12AD_ADEXICR_ADDR ( ( volatile uint16_t __evenaccess * )0x00089012 )
|
|---|
| 1637 | #define S12AD_ADDR0_ADDR ( ( volatile uint16_t __evenaccess * )0x00089020 )
|
|---|
| 1638 | #define S12AD_ADDR1_ADDR ( ( volatile uint16_t __evenaccess * )0x00089022 )
|
|---|
| 1639 | #define S12AD_ADDR2_ADDR ( ( volatile uint16_t __evenaccess * )0x00089024 )
|
|---|
| 1640 | #define S12AD_ADDR3_ADDR ( ( volatile uint16_t __evenaccess * )0x00089026 )
|
|---|
| 1641 | #define S12AD_ADDR4_ADDR ( ( volatile uint16_t __evenaccess * )0x00089028 )
|
|---|
| 1642 | #define S12AD_ADDR5_ADDR ( ( volatile uint16_t __evenaccess * )0x0008902A )
|
|---|
| 1643 | #define S12AD_ADDR6_ADDR ( ( volatile uint16_t __evenaccess * )0x0008902C )
|
|---|
| 1644 | #define S12AD_ADDR7_ADDR ( ( volatile uint16_t __evenaccess * )0x0008902E )
|
|---|
| 1645 | #define S12AD_ADDR8_ADDR ( ( volatile uint16_t __evenaccess * )0x00089030 )
|
|---|
| 1646 | #define S12AD_ADDR9_ADDR ( ( volatile uint16_t __evenaccess * )0x00089032 )
|
|---|
| 1647 | #define S12AD_ADDR10_ADDR ( ( volatile uint16_t __evenaccess * )0x00089034 )
|
|---|
| 1648 | #define S12AD_ADDR11_ADDR ( ( volatile uint16_t __evenaccess * )0x00089036 )
|
|---|
| 1649 | #define S12AD_ADDR12_ADDR ( ( volatile uint16_t __evenaccess * )0x00089038 )
|
|---|
| 1650 | #define S12AD_ADDR13_ADDR ( ( volatile uint16_t __evenaccess * )0x0008903A )
|
|---|
| 1651 | #define S12AD_ADDR14_ADDR ( ( volatile uint16_t __evenaccess * )0x0008903C )
|
|---|
| 1652 | #define S12AD_ADDR15_ADDR ( ( volatile uint16_t __evenaccess * )0x0008903E )
|
|---|
| 1653 | #define S12AD_ADDR16_ADDR ( ( volatile uint16_t __evenaccess * )0x00089040 )
|
|---|
| 1654 | #define S12AD_ADDR17_ADDR ( ( volatile uint16_t __evenaccess * )0x00089042 )
|
|---|
| 1655 | #define S12AD_ADDR18_ADDR ( ( volatile uint16_t __evenaccess * )0x00089044 )
|
|---|
| 1656 | #define S12AD_ADDR19_ADDR ( ( volatile uint16_t __evenaccess * )0x00089046 )
|
|---|
| 1657 | #define S12AD_ADDR20_ADDR ( ( volatile uint16_t __evenaccess * )0x00089048 )
|
|---|
| 1658 |
|
|---|
| 1659 | #define TPU0_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088110 )
|
|---|
| 1660 | #define TPU1_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088120 )
|
|---|
| 1661 | #define TPU2_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088130 )
|
|---|
| 1662 | #define TPU3_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088140 )
|
|---|
| 1663 | #define TPU4_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088150 )
|
|---|
| 1664 | #define TPU5_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088160 )
|
|---|
| 1665 | #define TPU6_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088180 )
|
|---|
| 1666 | #define TPU7_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088190 )
|
|---|
| 1667 | #define TPU8_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881A0 )
|
|---|
| 1668 | #define TPU9_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B0 )
|
|---|
| 1669 | #define TPU10_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C0 )
|
|---|
| 1670 | #define TPU11_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D0 )
|
|---|
| 1671 | #define TPU_TCR_TPSC_OFFSET ( 0U )
|
|---|
| 1672 | #define TPU_TCR_TPSC_MASK ( 0x7U << TPU_TCR_TPSC_OFFSET )
|
|---|
| 1673 | #define TPU_TCR_CKEG_OFFSET ( 3U )
|
|---|
| 1674 | #define TPU_TCR_CKEG_MASK ( 0x3U << TPU_TCR_CKEG_OFFSET )
|
|---|
| 1675 | #define TPU_TCR_CCLR_OFFSET ( 5U )
|
|---|
| 1676 | #define TPU_TCR_CCLR_MASK ( 0x7U << TPU_TCR_CCLR_OFFSET )
|
|---|
| 1677 |
|
|---|
| 1678 | #define TPU0_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088111 )
|
|---|
| 1679 | #define TPU1_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088121 )
|
|---|
| 1680 | #define TPU2_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088131 )
|
|---|
| 1681 | #define TPU3_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088141 )
|
|---|
| 1682 | #define TPU4_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088151 )
|
|---|
| 1683 | #define TPU5_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088161 )
|
|---|
| 1684 | #define TPU6_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088181 )
|
|---|
| 1685 | #define TPU7_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088191 )
|
|---|
| 1686 | #define TPU8_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881A1 )
|
|---|
| 1687 | #define TPU9_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B1 )
|
|---|
| 1688 | #define TPU10_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C1 )
|
|---|
| 1689 | #define TPU11_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D1 )
|
|---|
| 1690 |
|
|---|
| 1691 | #define TPU0_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C0 )
|
|---|
| 1692 | #define TPU0_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x00088112 )
|
|---|
| 1693 | #define TPU0_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x00088113 )
|
|---|
| 1694 | #define TPU1_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088122 )
|
|---|
| 1695 | #define TPU2_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088132 )
|
|---|
| 1696 | #define TPU3_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x00088142 )
|
|---|
| 1697 | #define TPU3_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x00088143 )
|
|---|
| 1698 | #define TPU4_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088152 )
|
|---|
| 1699 | #define TPU5_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088162 )
|
|---|
| 1700 | #define TPU6_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x00088182 )
|
|---|
| 1701 | #define TPU6_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x00088183 )
|
|---|
| 1702 | #define TPU7_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088192 )
|
|---|
| 1703 | #define TPU8_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881A2 )
|
|---|
| 1704 | #define TPU9_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B2 )
|
|---|
| 1705 | #define TPU9_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B3 )
|
|---|
| 1706 | #define TPU10_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C2 )
|
|---|
| 1707 | #define TPU11_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D2 )
|
|---|
| 1708 | #define TPU_TIORL_IOA_OFFSET ( 0U )
|
|---|
| 1709 | #define TPU_TIORL_IOA_MASK ( 0xFU << TPU_TIORL_IOA_OFFSET )
|
|---|
| 1710 | #define TPU_TIORL_IOB_OFFSET ( 4U )
|
|---|
| 1711 | #define TPU_TIORL_IOB_MASK ( 0xFU << TPU_TIORL_IOB_OFFSET )
|
|---|
| 1712 | #define TPU_TIORL_IOC_OFFSET ( 0U )
|
|---|
| 1713 | #define TPU_TIORL_IOC_MASK ( 0xFU << TPU_TIORL_IOC_OFFSET )
|
|---|
| 1714 | #define TPU_TIORL_IOD_OFFSET ( 4U )
|
|---|
| 1715 | #define TPU_TIORL_IOD_MASK ( 0xFU << TPU_TIORL_IOD_OFFSET )
|
|---|
| 1716 |
|
|---|
| 1717 | #define TPU0_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088118 )
|
|---|
| 1718 | #define TPU0_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008811A )
|
|---|
| 1719 | #define TPU0_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x0008811C )
|
|---|
| 1720 | #define TPU0_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x0008811E )
|
|---|
| 1721 | #define TPU1_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088128 )
|
|---|
| 1722 | #define TPU1_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008812A )
|
|---|
| 1723 | #define TPU2_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088138 )
|
|---|
| 1724 | #define TPU2_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008813A )
|
|---|
| 1725 | #define TPU3_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088148 )
|
|---|
| 1726 | #define TPU3_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008814A )
|
|---|
| 1727 | #define TPU3_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x0008814C )
|
|---|
| 1728 | #define TPU3_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x0008814E )
|
|---|
| 1729 | #define TPU4_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088158 )
|
|---|
| 1730 | #define TPU4_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008815A )
|
|---|
| 1731 | #define TPU5_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088168 )
|
|---|
| 1732 | #define TPU5_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008816A )
|
|---|
| 1733 | #define TPU6_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088188 )
|
|---|
| 1734 | #define TPU6_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008818A )
|
|---|
| 1735 | #define TPU6_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x0008818C )
|
|---|
| 1736 | #define TPU6_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x0008818E )
|
|---|
| 1737 | #define TPU7_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088198 )
|
|---|
| 1738 | #define TPU7_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008819A )
|
|---|
| 1739 | #define TPU8_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881A8 )
|
|---|
| 1740 | #define TPU8_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881AA )
|
|---|
| 1741 | #define TPU9_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881B8 )
|
|---|
| 1742 | #define TPU9_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881BA )
|
|---|
| 1743 | #define TPU9_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x000881BC )
|
|---|
| 1744 | #define TPU9_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x000881BE )
|
|---|
| 1745 | #define TPU10_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881C8 )
|
|---|
| 1746 | #define TPU10_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881CA )
|
|---|
| 1747 | #define TPU11_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881D8 )
|
|---|
| 1748 | #define TPU11_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881DA )
|
|---|
| 1749 |
|
|---|
| 1750 | #define TPUA_TSTR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088100 )
|
|---|
| 1751 | #define TPUB_TSTR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088170 )
|
|---|
| 1752 | #define TPU_TSTR_CST0_BIT ( 0x01U << 0U )
|
|---|
| 1753 | #define TPU_TSTR_CST1_BIT ( 0x01U << 1U )
|
|---|
| 1754 | #define TPU_TSTR_CST2_BIT ( 0x01U << 2U )
|
|---|
| 1755 | #define TPU_TSTR_CST3_BIT ( 0x01U << 3U )
|
|---|
| 1756 | #define TPU_TSTR_CST4_BIT ( 0x01U << 4U )
|
|---|
| 1757 | #define TPU_TSTR_CST5_BIT ( 0x01U << 5U )
|
|---|
| 1758 |
|
|---|
| 1759 | #define TPUA_TSYR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088101 )
|
|---|
| 1760 | #define TPUB_TSYR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088171 )
|
|---|
| 1761 | #define TPU_TSYR_SYNC0_BIT ( 0x01U << 0U )
|
|---|
| 1762 | #define TPU_TSYR_SYNC1_BIT ( 0x01U << 1U )
|
|---|
| 1763 | #define TPU_TSYR_SYNC2_BIT ( 0x01U << 2U )
|
|---|
| 1764 | #define TPU_TSYR_SYNC3_BIT ( 0x01U << 3U )
|
|---|
| 1765 | #define TPU_TSYR_SYNC4_BIT ( 0x01U << 4U )
|
|---|
| 1766 | #define TPU_TSYR_SYNC5_BIT ( 0x01U << 5U )
|
|---|
| 1767 |
|
|---|
| 1768 | /*
|
|---|
| 1769 | * UART関連の定義
|
|---|
| 1770 | *
|
|---|
| 1771 | * pdicのrx600/rx630_uart.cで使用する．
|
|---|
| 1772 | */
|
|---|
| 1773 | /*
|
|---|
| 1774 | * シリアルI/Oの個数
|
|---|
| 1775 | */
|
|---|
| 1776 | #define TNUM_SIOP ( 2 )
|
|---|
| 1777 |
|
|---|
| 1778 | #endif /* TOPPERS_RX630_H */
|
|---|
| 1779 |
|
|---|
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