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data_flash.c@ 101

Last change on this file since 101 was 101, checked in by coas-nagasima, 8 years ago
TOPPERS/uKadecotのソースコードを追加
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File size: 11.3 KB

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1	/*
2	* TOPPERS ECHONET Lite Communication Middleware
3	*
4	* Copyright (C) 2014 Cores Co., Ltd. Japan
5	*
6	* ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
7	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
8	* ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
9	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
10	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
11	* XR[hÉÜÜêÄ¢é±ÆD
12	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
13	* pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
14	gip
15	* Ò}j
16	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
17	* Ì³ÛØKèðfÚ·é±ÆD
18	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
19	* pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
20	* ÆD
21	* (a) ÄzzÉº¤hL
22	gipÒ}j
23	AÈÇjÉCãLÌ
24	* ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
25	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
26	* ñ·é±ÆD
27	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
28	* Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
29	* Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
30	* RÉîÃ¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
31	* ÆÓ·é±ÆD
32	*
33	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
34	* æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
35	* ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
36	* AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
37	* ÌÓCðíÈ¢D
38	*
39	* @(#) $Id: data_flash.c 101 2015-06-02 15:37:23Z coas-nagasima $
40	*/
41
42	/*
43	* TvvO(1)Ì{Ì
44	*/
45
46	#include <kernel.h>
47	#include <t_syslog.h>
48	#include <sil.h>
49	#include "data_flash.h"
50	#ifdef __RX
51	#include "rx630_ccrx/rx630.h"
52	#else
53	#include "rx630_msvc/rx630.h"
54	#endif
55	#include "grsakura.h"
56
57	#define FLASH_FWEPROR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C296 )
58
59	#define FLASH_FMODR_ADDR ( ( volatile uint8_t __evenaccess * )0x007FC402 )
60	#define FLASH_FMODR_FRDMD_BIT ( 0x01U << 4U )
61
62	#define FLASH_DFLRE0_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC440 )
63	#define FLASH_DFLRE1_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC442 )
64	#define FLASH_DFLWE0_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC450 )
65	#define FLASH_DFLWE1_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC452 )
66	#define FLASH_FCURAME_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC454 )
67
68	#define FLASH_FASTAT_ADDR ( ( volatile uint8_t __evenaccess * )0x007FC410 )
69	#define FLASH_FASTAT_DFLWPE_BIT ( 0x01U << 0 )
70	#define FLASH_FASTAT_DFLRPE_BIT ( 0x01U << 1 )
71	#define FLASH_FASTAT_DFLAE_BIT ( 0x01U << 3 )
72	#define FLASH_FASTAT_CMDLK_BIT ( 0x01U << 4 )
73	#define FLASH_FASTAT_ROMAE_BIT ( 0x01U << 7 )
74
75	#define FLASH_FENTRYR_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFB2 )
76	#define FLASH_FENTRYR_FENRTY0_BIT ( 0x0001U << 0U )
77	#define FLASH_FENTRYR_FENRTY1_BIT ( 0x0001U << 1U )
78	#define FLASH_FENTRYR_FENRTY2_BIT ( 0x0001U << 2U )
79	#define FLASH_FENTRYR_FENRTY3_BIT ( 0x0001U << 3U )
80	#define FLASH_FENTRYR_FENTRYD_BIT ( 0x0001U << 7U )
81
82	#define FLASH_FRESETR_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFB6 )
83	#define FLASH_FRESETR_FRESET_BIT ( 0x0001U << 0 )
84
85	#define FLASH_DFLBCCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFCA )
86	#define FLASH_DFLBCCNT_BCSIZE_BIT ( 0x0001U << 15U )
87	#define FLASH_DFLBCCNT_BCADR_OFFSET ( 0U )
88	#define FLASH_DFLBCCNT_BCADR_MASK ( 0x7FFU << FLASH_DFLBCCNT_BCADR_OFFSET )
89
90	#define FLASH_DFLBCSTAT_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFCE )
91	#define FLASH_DFLBCSTAT_BCST_BIT ( 0x0001U << 0U )
92
93	#define FLASH_FSTATR0_ADDR ( ( volatile uint8_t __evenaccess * )0x007FFFB0 )
94	#define FLASH_FSTATR0_PRGSPD_BIT ( 0x01U << 0 )
95	#define FLASH_FSTATR0_ERSSPD_BIT ( 0x01U << 1 )
96	#define FLASH_FSTATR0_SUSRDY_BIT ( 0x01U << 3 )
97	#define FLASH_FSTATR0_PRGERR_BIT ( 0x01U << 4 )
98	#define FLASH_FSTATR0_ERSERR_BIT ( 0x01U << 5 )
99	#define FLASH_FSTATR0_ILGLERR_BIT ( 0x01U << 6 )
100	#define FLASH_FSTATR0_FRDY_BIT ( 0x01U << 7 )
101
102	#define FLASH_PCKAR_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFE8 )
103
104	#define DATA_FLASH_BLOCK_SIZE 32
105	#ifndef _MSC_VER
106	#define DATA_FLASH_BASE_ADDR 0x00100000
107	#define FCU_FIRMWARE_ADDR 0xFEFFE000
108	#define FCU_RAM_ADDR 0x007F8000
109	#else
110	uint8_t DATA_FLASH_BASE_ADDR[DATA_FLASH_BLOCK_SIZE * 1024];
111	uint8_t FCU_FIRMWARE_ADDR[0x2000];
112	uint8_t FCU_RAM_ADDR[0x2000];
113	#endif
114
115	static void fcu_init();
116	static void fcu_copy_firm();
117	static bool_t fcu_notify_clock();
118	static void fcu_read_mode();
119	static void fcu_pe_mode();
120	static bool_t fcu_write(int blockno, void *data);
121	static bool_t fcu_erase(int blockno);
122	static bool_t fcu_check_blank(int blockno);
123	static bool_t fcu_check_valid(int blockno);
124	static bool_t fcu_check_frdy(int tWAIT);
125	static bool_t fcu_check_error();
126
127	ER data_flash_init()
128	{
129	ER ret;
130
131	/* E2f[^tbV
132	ÌÇÝÝÂ */
133	sil_wrh_mem(FLASH_DFLRE0_ADDR, 0x2DFF);
134	sil_wrh_mem(FLASH_DFLRE1_ADDR, 0xD2FF);
135	/* E2f[^tbV
136	Ì«ÝÂ */
137	sil_wrh_mem(FLASH_DFLWE0_ADDR, 0x1EFF);
138	sil_wrh_mem(FLASH_DFLWE1_ADDR, 0xE1FF);
139
140	/* tE16K = 240ms*/
141	fcu_check_frdy(240000);
142
143	/* G[mF */
144	fcu_check_error();
145
146	/* FCUt@[EFAÌRs[ */
147	fcu_copy_firm();
148
149	/* P/E[hÚs */
150	fcu_pe_mode();
151
152	/* P/E m[}[hÚs */
153	((uint8_t )DATA_FLASH_BASE_ADDR) = 0xFF;
154
155	/* G[mF */
156	fcu_check_error();
157
158	/* üÓNbNÊmR}hs */
159	ret = fcu_notify_clock();
160
161	/* [h[hÚs */
162	fcu_read_mode();
163
164	return ret ? E_OK : E_SYS;
165	}
166
167	ER data_flash_read(int blockno, void *data)
168	{
169	uint16_t wa, end;
170	uint16_t dst = (uint16_t )data;
171
172	/* P/E[hÚs */
173	fcu_pe_mode();
174
175	/* Løf[^`FbN */
176	if(!fcu_check_valid(blockno)){
177	/* [h[hÚs */
178	fcu_read_mode();
179	return E_OBJ;
180	}
181
182	/* [h[hÚs */
183	fcu_read_mode();
184
185	wa = (uint16_t )(DATA_FLASH_BLOCK_SIZE blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
186	end = &wa[DATA_FLASH_BLOCK_SIZE/sizeof(uint16_t)];
187
188	/* ÇÝoµ */
189	for(; wa < end; wa++, dst++){
190	dst = wa;
191	}
192
193	return E_OK;
194	}
195
196	ER data_flash_write(int blockno, void *data)
197	{
198	bool_t ret = true;
199
200	/* P/E[hÚs */
201	fcu_pe_mode();
202
203	/* uN`FbN */
204	if(!fcu_check_blank(blockno)){
205	/* uNÅÈ¢ÈçubNÁ */
206	ret = fcu_erase(blockno);
207	if(!ret)
208	syslog(LOG_DEBUG, "fcu_erase() result = %d", ret);
209	}
210
211	if(ret){
212	/* «Ý */
213	ret = fcu_write(blockno, data);
214	if(!ret)
215	syslog(LOG_DEBUG, "fcu_write() result = %d", ret);
216	}
217
218	/* [h[hÚs */
219	fcu_read_mode();
220
221	return ret ? E_OK : E_SYS;
222	}
223
224	static void fcu_copy_firm()
225	{
226	unsigned int src, dst, *end;
227
228	/* [h[hÚs */
229	if(sil_reh_mem(FLASH_FENTRYR_ADDR) != 0)
230	sil_wrh_mem(FLASH_FENTRYR_ADDR, 0xAA00);
231
232	/* FCU RAMANZXÂ */
233	sil_wrh_mem(FLASH_FCURAME_ADDR, 0xC401);
234
235	/* FCUt@[EFAðFCU RAMÉRs[ */
236	src = (unsigned int *)FCU_FIRMWARE_ADDR;
237	dst = (unsigned int *)FCU_RAM_ADDR;
238	end = &dst[0x2000 / sizeof(unsigned int)];
239	for(; dst < end; dst++, src++)
240	dst = src;
241	}
242
243	static bool_t fcu_notify_clock()
244	{
245	volatile uint8_t *ra;
246	volatile uint16_t *wa;
247
248	ra = (volatile uint8_t *)(DATA_FLASH_BASE_ADDR);
249	wa = (volatile uint16_t *)ra;
250
251	/* ügðÝè */
252	sil_wrh_mem(FLASH_PCKAR_ADDR, 48/FREQ_PCLK / 1000/);
253
254	/* üÓNbNÊmR}hs */
255	*ra = 0xE9;
256	*ra = 0x03;
257	*wa = 0x0F0F;
258	*wa = 0x0F0F;
259	*wa = 0x0F0F;
260	*ra = 0xD0;
261
262	/* 120Ês */
263	fcu_check_frdy(120);
264
265	/* G[mF */
266	return !fcu_check_error();
267	}
268
269	/*
270	* [h[hÚs
271	*/
272	static void fcu_read_mode()
273	{
274	int i;
275
276	for(;;){
277	for(i = 0; i < 1000; i++){
278	sil_wrh_mem(FLASH_FENTRYR_ADDR, 0xAA00);
279
280	if(sil_reh_mem(FLASH_FENTRYR_ADDR) != 0)
281	continue;
282
283	sil_wrb_mem(FLASH_FWEPROR_ADDR, 0x02);
284	return;
285	}
286
287	syslog(LOG_WARNING, "fcu_read_mode");
288	}
289	}
290
291	/*
292	* P/E[hÚs
293	*/
294	static void fcu_pe_mode()
295	{
296	sil_wrh_mem(FLASH_FENTRYR_ADDR, 0xAA80);
297	sil_wrb_mem(FLASH_FWEPROR_ADDR, 0x01);
298	}
299
300	static bool_t fcu_write(int blockno, void *data)
301	{
302	volatile uint8_t *ra;
303	volatile uint16_t wa, end;
304	uint16_t src = (uint16_t )data;
305
306	ra = (volatile uint8_t )(DATA_FLASH_BLOCK_SIZE blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
307	end = (volatile uint16_t *)(((intptr_t)ra) + DATA_FLASH_BLOCK_SIZE);
308
309	for(wa = (volatile uint16_t *)ra; wa < end; wa++, src++)
310	{
311	/* vOR}hs */
312	*ra = 0xE8;
313	*ra = 0x01;
314	wa = src;
315	*ra = 0xD0;
316
317	/* 2ms~1.1 */
318	fcu_check_frdy(2200);
319
320	/* G[mF */
321	if(fcu_check_error())
322	return false;
323	}
324
325	return true;
326	}
327
328	static bool_t fcu_erase(int blockno)
329	{
330	volatile uint8_t *ra;
331
332	ra = (volatile uint8_t )(DATA_FLASH_BLOCK_SIZE blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
333
334	/* C[XR}hs */
335	*ra = 0x20;
336	*ra = 0xD0;
337
338	/* 20ms~1.1 */
339	fcu_check_frdy(22000);
340
341	/* G[mF */
342	return !fcu_check_error();
343	}
344
345	static bool_t fcu_check_blank(int blockno)
346	{
347	volatile uint8_t *ra;
348	volatile uint16_t wa, end;
349
350	sil_wrb_mem(FLASH_FMODR_ADDR, sil_reb_mem(FLASH_FMODR_ADDR) \| FLASH_FMODR_FRDMD_BIT);
351
352	wa = (volatile uint16_t )(DATA_FLASH_BLOCK_SIZE blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
353	end = (volatile uint16_t *)(((intptr_t)wa) + DATA_FLASH_BLOCK_SIZE);
354
355	for(; wa < end; wa++)
356	{
357	sil_wrh_mem(FLASH_DFLBCCNT_ADDR, (((intptr_t)wa) & FLASH_DFLBCCNT_BCADR_MASK) << FLASH_DFLBCCNT_BCADR_OFFSET);
358
359	ra = (volatile uint8_t *)wa;
360	*ra = 0x71;
361	*ra = 0xD0;
362
363	/* 30Ês~1.1 */
364	fcu_check_frdy(33);
365
366	/* G[mF */
367	if(fcu_check_error())
368	return false;
369
370	/* uNmF */
371	if((sil_reh_mem(FLASH_DFLBCSTAT_ADDR) & FLASH_DFLBCSTAT_BCST_BIT) != 0)
372	return false;
373	}
374
375	return true;
376	}
377
378	static bool_t fcu_check_valid(int blockno)
379	{
380	volatile uint8_t *ra;
381	volatile uint16_t wa, end;
382
383	sil_wrb_mem(FLASH_FMODR_ADDR, sil_reb_mem(FLASH_FMODR_ADDR) \| FLASH_FMODR_FRDMD_BIT);
384
385	wa = (volatile uint16_t )(DATA_FLASH_BLOCK_SIZE blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
386	end = (volatile uint16_t *)(((intptr_t)wa) + DATA_FLASH_BLOCK_SIZE);
387
388	for(; wa < end; wa++)
389	{
390	sil_wrh_mem(FLASH_DFLBCCNT_ADDR, (((intptr_t)wa) & FLASH_DFLBCCNT_BCADR_MASK) << FLASH_DFLBCCNT_BCADR_OFFSET);
391
392	ra = (volatile uint8_t *)wa;
393	*ra = 0x71;
394	*ra = 0xD0;
395
396	/* 30Ês~1.1 */
397	fcu_check_frdy(33);
398
399	/* G[mF */
400	if(fcu_check_error())
401	return false;
402
403	/* uNmF */
404	if((sil_reh_mem(FLASH_DFLBCSTAT_ADDR) & FLASH_DFLBCSTAT_BCST_BIT) == 0)
405	return false;
406	}
407
408	return true;
409	}
410
411	static bool_t fcu_check_error()
412	{
413	uint8_t status;
414
415	status = sil_reb_mem(FLASH_FSTATR0_ADDR);
416
417	if((status & (FLASH_FSTATR0_ILGLERR_BIT \| FLASH_FSTATR0_ERSERR_BIT \| FLASH_FSTATR0_PRGERR_BIT)) == 0)
418	return false;
419
420	if((status & FLASH_FSTATR0_ILGLERR_BIT) != 0){
421	if(sil_reb_mem(FLASH_FASTAT_ADDR) != 0x10){
422	sil_wrb_mem(FLASH_FASTAT_ADDR, 0x10);
423	}
424
425	/* Xe[^XNAR}hs */
426	((uint8_t )DATA_FLASH_BASE_ADDR) = 0x50;
427	}
428
429	syslog(LOG_WARNING, "fcu_check_error %02x", status);
430
431	return true;
432	}
433
434	static bool_t fcu_check_frdy(int tWAIT)
435	{
436	int i, j;
437
438	for(i = 0; i < tWAIT; i++){
439	/* õ®¹ÈçI¹ */
440	if((sil_reb_mem(FLASH_FSTATR0_ADDR) & FLASH_FSTATR0_FRDY_BIT) != 0)
441	return true;
442
443	/* 1Ês? */
444	for(j = 0; j < 100; j++);
445	}
446
447	syslog(LOG_WARNING, "fcu_check_frdy timeout");
448
449	/* FCUú» */
450	fcu_init();
451
452	return false;
453	}
454
455	static void fcu_init()
456	{
457	int j;
458
459	sil_wrh_mem(FLASH_FRESETR_ADDR, 0xCC01);
460
461	// 200Ês? */
462	for(j = 0; j < 20000; j++);
463
464	sil_wrh_mem(FLASH_FRESETR_ADDR, 0xCC00);
465	}

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