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arduino.c@ 101

Last change on this file since 101 was 101, checked in by coas-nagasima, 9 years ago
TOPPERS/uKadecotのソースコードを追加
Property svn:eol-style set to `native` Property svn:keywords set to `Id` Property svn:mime-type set to `text/plain`
File size: 17.7 KB

Rev	Line
[101]	1	/*
	2	* TOPPERS ECHONET Lite Communication Middleware
	3	*
	4	* Copyright (C) 2014 Cores Co., Ltd. Japan
	5	*
	6	* ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
	7	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
	8	* ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
	9	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
	10	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
	11	* XR[hÉÜÜêÄ¢é±ÆD
	12	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
	13	* pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
	14	gip
	15	* Ò}j
	16	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
	17	* Ì³ÛØKèðfÚ·é±ÆD
	18	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
	19	* pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
	20	* ÆD
	21	* (a) ÄzzÉº¤hL
	22	gipÒ}j
	23	AÈÇjÉCãLÌ
	24	* ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
	25	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
	26	* ñ·é±ÆD
	27	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
	28	* Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
	29	* Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
	30	* RÉîÃ¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
	31	* ÆÓ·é±ÆD
	32	*
	33	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
	34	* æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
	35	* ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
	36	* AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
	37	* ÌÓCðíÈ¢D
	38	*
	39	* @(#) $Id: arduino.c 101 2015-06-02 15:37:23Z coas-nagasima $
	40	*/
	41
	42	/*
	43	* TvvO(1)Ì{Ì
	44	*/
	45
	46	#include <kernel.h>
	47	#include <t_syslog.h>
	48	#include <sil.h>
	49	#include "arduino.h"
	50	#ifdef __RX
	51	#include "rx630_ccrx/rx630.h"
	52	#else
	53	#include "rx630_msvc/rx630.h"
	54	#endif
	55
	56	/* PWMoÍ(490Hz) */
	57	#define TPU_BASE_COUNTER (48000000 / 4 / 490)
	58
	59	void arduino_init()
	60	{
	61	/*
	62	* W
	63	[Xgbv@\ÌÝè(S12AD)
	64	*/
	65	sil_wrh_mem((uint16_t )SYSTEM_PRCR_ADDR, (uint16_t)0xA502); / ÝÂ */
	66	sil_wrw_mem((uint32_t *)SYSTEM_MSTPCRA_ADDR,
	67	sil_rew_mem((uint32_t *)SYSTEM_MSTPCRA_ADDR) & ~SYSTEM_MSTPCRA_MSTPA17_BIT);
	68	sil_wrh_mem((uint16_t )SYSTEM_PRCR_ADDR, (uint16_t)0xA500); / ÝÖ~ */
	69
	70	/* 12bitADCú» */
	71	sil_wrh_mem((uint16_t )S12AD_ADEXICR_ADDR, 0x0000); / ·xZToÍAàîd³ñIð */
	72	sil_wrh_mem((uint16_t )S12AD_ADANS0_ADDR, 0x00FF); / Ï·\|[gAN000`AN007IðAAN008`AN015ñIð */
	73	sil_wrh_mem((uint16_t )S12AD_ADANS1_ADDR, 0x0000); / Ï·\|[gAN016`AN020ñIð */
	74
	75	/* PWMoÍ(490Hz) */
	76	sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* ÝÂ */
	77	sil_wrw_mem(SYSTEM_MSTPCRA_ADDR,
	78	sil_rew_mem(SYSTEM_MSTPCRA_ADDR) & ~SYSTEM_MSTPCRA_MSTPA13_BIT); /* TPU0`TPU5 */
	79	sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* ÝÖ~ */
	80
	81	/* JE^NbNÌIðAJE^NAvöÌIð */
	82	sil_wrb_mem(TPU0_TCR_ADDR, (1 << TPU_TCR_TPSC_OFFSET) \| (1 << TPU_TCR_CKEG_OFFSET)
	83	\| (1 << TPU_TCR_CCLR_OFFSET));
	84	sil_wrb_mem(TPU3_TCR_ADDR, (1 << TPU_TCR_TPSC_OFFSET) \| (1 << TPU_TCR_CKEG_OFFSET)
	85	\| (3 << TPU_TCR_CCLR_OFFSET));
	86	sil_wrb_mem(TPU4_TCR_ADDR, (1 << TPU_TCR_TPSC_OFFSET) \| (1 << TPU_TCR_CKEG_OFFSET)
	87	\| (3 << TPU_TCR_CCLR_OFFSET));
	88	/* g`oÍxÌIð */
	89	sil_wrb_mem(TPU0_TIORL_ADDR, (5 << TPU_TIORL_IOC_OFFSET) \| (5 << TPU_TIORL_IOD_OFFSET));
	90	sil_wrb_mem(TPU3_TIORH_ADDR, (5 << TPU_TIORL_IOA_OFFSET) \| (5 << TPU_TIORL_IOB_OFFSET));
	91	sil_wrb_mem(TPU3_TIORL_ADDR, (5 << TPU_TIORL_IOC_OFFSET) \| (5 << TPU_TIORL_IOD_OFFSET));
	92	sil_wrb_mem(TPU4_TIOR_ADDR, (5 << TPU_TIORL_IOA_OFFSET) \| (5 << TPU_TIORL_IOB_OFFSET));
	93	/* TGRyÌÝè */
	94	sil_wrh_mem(TPU0_TGRA_ADDR, TPU_BASE_COUNTER);
	95	sil_wrh_mem(TPU0_TGRC_ADDR, 0);
	96	sil_wrh_mem(TPU0_TGRD_ADDR, 0);
	97	sil_wrh_mem(TPU3_TGRA_ADDR, 0);
	98	sil_wrh_mem(TPU3_TGRB_ADDR, 0);
	99	sil_wrh_mem(TPU3_TGRC_ADDR, 0);
	100	sil_wrh_mem(TPU3_TGRD_ADDR, 0);
	101	sil_wrh_mem(TPU4_TGRA_ADDR, 0);
	102	sil_wrh_mem(TPU4_TGRB_ADDR, 0);
	103	/* PWM[h2ÌÝè */
	104	sil_wrb_mem(TPU0_TMDR_ADDR, 3);
	105	sil_wrb_mem(TPU3_TMDR_ADDR, 3);
	106	sil_wrb_mem(TPU4_TMDR_ADDR, 3);
	107	/* ¯ú®ìÝè */
	108	sil_wrb_mem(TPUA_TSYR_ADDR, TPU_TSYR_SYNC0_BIT \| TPU_TSYR_SYNC3_BIT \| TPU_TSYR_SYNC4_BIT);
	109	/* JEg®ìJn */
	110	sil_wrb_mem(TPUA_TSTR_ADDR, TPU_TSTR_CST0_BIT \| TPU_TSTR_CST3_BIT \| TPU_TSTR_CST4_BIT);
	111	}
	112
	113	static bool_t pin_function_table[8] = {
	114	true, true, true, true, true, true, true, true
	115	};
	116
	117	static ER change_pin_function(int pin, bool_t gpio)
	118	{
	119	ER result = E_PAR;
	120
	121	if((pin < 0) \|\| (pin >= 8))
	122	return E_PAR;
	123
	124	if(pin_function_table[pin] == gpio)
	125	return E_OK;
	126
	127	/* ÄpüoÍ\|[gÉÝè */
	128	switch(pin){
	129	case 0:
	130	/* P21 */
	131	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B1_BIT);
	132	break;
	133	case 1:
	134	/* P20 */
	135	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B0_BIT);
	136	break;
	137	case 2:
	138	/* P22 */
	139	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B2_BIT);
	140	break;
	141	case 3:
	142	/* P23 */
	143	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B3_BIT);
	144	break;
	145	case 4:
	146	/* P24 */
	147	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B4_BIT);
	148	break;
	149	case 5:
	150	/* P25 */
	151	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B5_BIT);
	152	break;
	153	case 6:
	154	/* P32 */
	155	sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PMR_B2_BIT);
	156	break;
	157	case 7:
	158	/* P33 */
	159	sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PMR_B3_BIT);
	160	break;
	161	}
	162
	163	/* «ÝveNgWX^ÌÝè PFSWErbgÖÌ«ÝðÂ */
	164	sil_wrb_mem((uint8_t *)MPC_PWPR_ADDR, 0x00);
	165	/* «ÝveNgWX^ÌÝè PxxFSWX^ÖÌ«ÝðÂ */
	166	sil_wrb_mem((uint8_t *)MPC_PWPR_ADDR, 0x40);
	167
	168	switch(pin){
	169	/* P21/TIOCA3 */
	170	case 0:
	171	if(gpio){
	172	/* P21[q@\§äWX^ P21Æ·é */
	173	sil_wrb_mem((uint8_t *)MPC_P21PFS_ADDR, 0x00);
	174	}
	175	else{
	176	/* P21[q@\§äWX^ TIOCA3Æ·é */
	177	sil_wrb_mem((uint8_t *)MPC_P21PFS_ADDR, 0x03);
	178	}
	179	result = E_OK;
	180	break;
	181	/* P20/TIOCB3 */
	182	case 1:
	183	if(gpio){
	184	/* P20[q@\§äWX^ P20Æ·é */
	185	sil_wrb_mem((uint8_t *)MPC_P20PFS_ADDR, 0x00);
	186	}
	187	else{
	188	/* P20[q@\§äWX^ TIOCB3Æ·é */
	189	sil_wrb_mem((uint8_t *)MPC_P20PFS_ADDR, 0x03);
	190	}
	191	result = E_OK;
	192	break;
	193	/* P22/TIOCC3 */
	194	case 2:
	195	if(gpio){
	196	/* P22[q@\§äWX^ P22Æ·é */
	197	sil_wrb_mem((uint8_t *)MPC_P22PFS_ADDR, 0x00);
	198	}
	199	else{
	200	/* P22[q@\§äWX^ TIOCC3Æ·é */
	201	sil_wrb_mem((uint8_t *)MPC_P22PFS_ADDR, 0x03);
	202	}
	203	result = E_OK;
	204	break;
	205	/* P23/TIOCD3 */
	206	case 3:
	207	if(gpio){
	208	/* P23[q@\§äWX^ P23Æ·é */
	209	sil_wrb_mem((uint8_t *)MPC_P23PFS_ADDR, 0x00);
	210	}
	211	else{
	212	/* P23[q@\§äWX^ TIOCD3Æ·é */
	213	sil_wrb_mem((uint8_t *)MPC_P23PFS_ADDR, 0x03);
	214	}
	215	result = E_OK;
	216	break;
	217	/* P24/TIOCB4 */
	218	case 4:
	219	if(gpio){
	220	/* P24[q@\§äWX^ P24Æ·é */
	221	sil_wrb_mem((uint8_t *)MPC_P24PFS_ADDR, 0x00);
	222	}
	223	else{
	224	/* P24[q@\§äWX^ TIOCB4Æ·é */
	225	sil_wrb_mem((uint8_t *)MPC_P24PFS_ADDR, 0x03);
	226	}
	227	result = E_OK;
	228	break;
	229	/* P25/TIOCA4 */
	230	case 5:
	231	if(gpio){
	232	/* P25[q@\§äWX^ P25Æ·é */
	233	sil_wrb_mem((uint8_t *)MPC_P25PFS_ADDR, 0x00);
	234	}
	235	else{
	236	/* P25[q@\§äWX^ TIOCA4Æ·é */
	237	sil_wrb_mem((uint8_t *)MPC_P25PFS_ADDR, 0x03);
	238	}
	239	result = E_OK;
	240	break;
	241	/* P32/TIOCC0 */
	242	case 6:
	243	if(gpio){
	244	/* P32[q@\§äWX^ P32Æ·é */
	245	sil_wrb_mem((uint8_t *)MPC_P32PFS_ADDR, 0x00);
	246	}
	247	else{
	248	/* P32[q@\§äWX^ TIOCC0Æ·é */
	249	sil_wrb_mem((uint8_t *)MPC_P32PFS_ADDR, 0x03);
	250	}
	251	result = E_OK;
	252	break;
	253	/* P33/TIOCD0 */
	254	case 7:
	255	if(gpio){
	256	/* P33[q@\§äWX^ P33Æ·é */
	257	sil_wrb_mem((uint8_t *)MPC_P33PFS_ADDR, 0x00);
	258	}
	259	else{
	260	/* P33[q@\§äWX^ TIOCD0Æ·é */
	261	sil_wrb_mem((uint8_t *)MPC_P33PFS_ADDR, 0x03);
	262	}
	263	result = E_OK;
	264	break;
	265	}
	266
	267	/* «ÝveNgWX^ÌÝè «ÝðÖ~ */
	268	sil_wrb_mem((uint8_t *)MPC_PWPR_ADDR, 0x80);
	269
	270	/* @\\|[gÉÝè */
	271	if(!gpio){
	272	switch(pin){
	273	/* P21/TIOCA3 */
	274	case 0:
	275	sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) \| PORT_PDR_B1_BIT);
	276	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) \| PORT_PMR_B1_BIT);
	277	break;
	278	/* P20/TIOCB3 */
	279	case 1:
	280	sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) \| PORT_PDR_B0_BIT);
	281	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) \| PORT_PMR_B0_BIT);
	282	break;
	283	/* P22/TIOCC3 */
	284	case 2:
	285	sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) \| PORT_PDR_B2_BIT);
	286	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) \| PORT_PMR_B2_BIT);
	287	break;
	288	/* P23/TIOCD3 */
	289	case 3:
	290	sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) \| PORT_PDR_B3_BIT);
	291	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) \| PORT_PMR_B3_BIT);
	292	break;
	293	/* P24/TIOCB4 */
	294	case 4:
	295	sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) \| PORT_PDR_B4_BIT);
	296	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) \| PORT_PMR_B4_BIT);
	297	break;
	298	/* P25/TIOCA4 */
	299	case 5:
	300	sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) \| PORT_PDR_B5_BIT);
	301	sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) \| PORT_PMR_B5_BIT);
	302	break;
	303	/* P32/TIOCC0 */
	304	case 6:
	305	sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) \| PORT_PDR_B2_BIT);
	306	sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) \| PORT_PMR_B2_BIT);
	307	break;
	308	/* P33/TIOCD0 */
	309	case 7:
	310	sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) \| PORT_PDR_B3_BIT);
	311	sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) \| PORT_PMR_B3_BIT);
	312	break;
	313	}
	314	}
	315
	316	pin_function_table[pin] = gpio;
	317
	318	return result;
	319	}
	320
	321	static ER change_pin_mode(arduino_pin_mode_t mode, volatile uint8_t *pdr, int bit)
	322	{
	323	volatile uint8_t *pcr = pdr + (PORT0_PCR_ADDR - PORT0_PDR_ADDR);
	324
	325	switch(mode){
	326	case ARDUINO_PIN_MODE_INPUT:
	327	sil_wrb_mem(pdr, sil_reb_mem(pdr) & ~bit);
	328	sil_wrb_mem(pcr, sil_reb_mem(pcr) & ~bit);
	329	return E_OK;
	330	case ARDUINO_PIN_MODE_OUTPUT:
	331	sil_wrb_mem(pdr, sil_reb_mem(pdr) \| bit);
	332	return E_OK;
	333	case ARDUINO_PIN_MODE_INPUT_PULLUP:
	334	sil_wrb_mem(pdr, sil_reb_mem(pdr) & ~bit);
	335	sil_wrb_mem(pcr, sil_reb_mem(pcr) \| bit);
	336	return E_OK;
	337	}
	338
	339	return E_PAR;
	340	}
	341
	342	ER arduino_pinMode(int pin, arduino_pin_mode_t mode)
	343	{
	344	/* ÄpüoÍ\|[gÉÝè */
	345	change_pin_function(pin, true);
	346
	347	switch(pin){
	348	case 0:
	349	/* P21 */
	350	return change_pin_mode(mode, PORT2_PDR_ADDR, PORT_PDR_B1_BIT);
	351	case 1:
	352	/* P20 */
	353	return change_pin_mode(mode, PORT2_PDR_ADDR, PORT_PDR_B0_BIT);
	354	case 2:
	355	/* P22 */
	356	return change_pin_mode(mode, PORT2_PDR_ADDR, PORT_PDR_B2_BIT);
	357	case 3:
	358	/* P23 */
	359	return change_pin_mode(mode, PORT2_PDR_ADDR, PORT_PDR_B3_BIT);
	360	case 4:
	361	/* P24 */
	362	return change_pin_mode(mode, PORT2_PDR_ADDR, PORT_PDR_B4_BIT);
	363	case 5:
	364	/* P25 */
	365	return change_pin_mode(mode, PORT2_PDR_ADDR, PORT_PDR_B5_BIT);
	366	case 6:
	367	/* P32 */
	368	return change_pin_mode(mode, PORT3_PDR_ADDR, PORT_PDR_B2_BIT);
	369	case 7:
	370	/* P33 */
	371	return change_pin_mode(mode, PORT3_PDR_ADDR, PORT_PDR_B3_BIT);
	372	case 8:
	373	/* PC2 */
	374	return change_pin_mode(mode, PORTC_PDR_ADDR, PORT_PDR_B2_BIT);
	375	case 9:
	376	/* PC3 */
	377	return change_pin_mode(mode, PORTC_PDR_ADDR, PORT_PDR_B3_BIT);
	378	case 10:
	379	/* PC4 */
	380	return change_pin_mode(mode, PORTC_PDR_ADDR, PORT_PDR_B4_BIT);
	381	case 11:
	382	/* PC6 */
	383	return change_pin_mode(mode, PORTC_PDR_ADDR, PORT_PDR_B6_BIT);
	384	case 12:
	385	/* PC7 */
	386	return change_pin_mode(mode, PORTC_PDR_ADDR, PORT_PDR_B7_BIT);
	387	case 13:
	388	/* PC5 */
	389	return change_pin_mode(mode, PORTC_PDR_ADDR, PORT_PDR_B5_BIT);
	390	}
	391
	392	return E_PAR;
	393	}
	394
	395	static ER write_gpio(arduino_digital_value_t value, volatile uint8_t *podr, int bit)
	396	{
	397	switch(value){
	398	case ARDUINO_DIGITAL_VALUE_HIGH:
	399	sil_wrb_mem(podr, sil_reb_mem(podr) \| bit);
	400	return E_OK;
	401	case ARDUINO_DIGITAL_VALUE_LOW:
	402	sil_wrb_mem(podr, sil_reb_mem(podr) & ~bit);
	403	return E_OK;
	404	}
	405
	406	return E_PAR;
	407	}
	408
	409	ER arduino_digitalWrite(int pin, arduino_digital_value_t value)
	410	{
	411	switch(pin){
	412	case 0:
	413	/* P21 */
	414	return write_gpio(value, PORT2_PODR_ADDR, PORT_PODR_B1_BIT);
	415	case 1:
	416	/* P20 */
	417	return write_gpio(value, PORT2_PODR_ADDR, PORT_PODR_B0_BIT);
	418	case 2:
	419	/* P22 */
	420	return write_gpio(value, PORT2_PODR_ADDR, PORT_PODR_B2_BIT);
	421	case 3:
	422	/* P23 */
	423	return write_gpio(value, PORT2_PODR_ADDR, PORT_PODR_B3_BIT);
	424	case 4:
	425	/* P24 */
	426	return write_gpio(value, PORT2_PODR_ADDR, PORT_PODR_B4_BIT);
	427	case 5:
	428	/* P25 */
	429	return write_gpio(value, PORT2_PODR_ADDR, PORT_PODR_B5_BIT);
	430	case 6:
	431	/* P32 */
	432	return write_gpio(value, PORT3_PODR_ADDR, PORT_PODR_B2_BIT);
	433	case 7:
	434	/* P33 */
	435	return write_gpio(value, PORT3_PODR_ADDR, PORT_PODR_B3_BIT);
	436	case 8:
	437	/* PC2 */
	438	return write_gpio(value, PORTC_PODR_ADDR, PORT_PODR_B2_BIT);
	439	case 9:
	440	/* PC3 */
	441	return write_gpio(value, PORTC_PODR_ADDR, PORT_PODR_B3_BIT);
	442	case 10:
	443	/* PC4 */
	444	return write_gpio(value, PORTC_PODR_ADDR, PORT_PODR_B4_BIT);
	445	case 11:
	446	/* PC6 */
	447	return write_gpio(value, PORTC_PODR_ADDR, PORT_PODR_B6_BIT);
	448	case 12:
	449	/* PC7 */
	450	return write_gpio(value, PORTC_PODR_ADDR, PORT_PODR_B7_BIT);
	451	case 13:
	452	/* PC5 */
	453	return write_gpio(value, PORTC_PODR_ADDR, PORT_PODR_B5_BIT);
	454	}
	455
	456	return E_PAR;
	457	}
	458
	459	static ER read_gpio(volatile uint8_t pidr, int bit, arduino_digital_value_t result)
	460	{
	461	if ((sil_reb_mem(pidr) & bit) != 0) {
	462	*result = ARDUINO_DIGITAL_VALUE_HIGH;
	463	return E_OK;
	464	}
	465	else {
	466	*result = ARDUINO_DIGITAL_VALUE_LOW;
	467	return E_OK;
	468	}
	469	}
	470
	471	ER arduino_digitalRead(int pin, arduino_digital_value_t *result)
	472	{
	473	switch(pin){
	474	case 0:
	475	/* P21 */
	476	return read_gpio(PORT2_PIDR_ADDR, PORT_PIDR_B1_BIT, result);
	477	case 1:
	478	/* P20 */
	479	return read_gpio(PORT2_PIDR_ADDR, PORT_PIDR_B0_BIT, result);
	480	case 2:
	481	/* P22 */
	482	return read_gpio(PORT2_PIDR_ADDR, PORT_PIDR_B2_BIT, result);
	483	case 3:
	484	/* P23 */
	485	return read_gpio(PORT2_PIDR_ADDR, PORT_PIDR_B3_BIT, result);
	486	case 4:
	487	/* P24 */
	488	return read_gpio(PORT2_PIDR_ADDR, PORT_PIDR_B4_BIT, result);
	489	case 5:
	490	/* P25 */
	491	return read_gpio(PORT2_PIDR_ADDR, PORT_PIDR_B5_BIT, result);
	492	case 6:
	493	/* P32 */
	494	return read_gpio(PORT3_PIDR_ADDR, PORT_PIDR_B2_BIT, result);
	495	case 7:
	496	/* P33 */
	497	return read_gpio(PORT3_PIDR_ADDR, PORT_PIDR_B3_BIT, result);
	498	case 8:
	499	/* PC2 */
	500	return read_gpio(PORTC_PIDR_ADDR, PORT_PIDR_B2_BIT, result);
	501	case 9:
	502	/* PC3 */
	503	return read_gpio(PORTC_PIDR_ADDR, PORT_PIDR_B3_BIT, result);
	504	case 10:
	505	/* PC4 */
	506	return read_gpio(PORTC_PIDR_ADDR, PORT_PIDR_B4_BIT, result);
	507	case 11:
	508	/* PC6 */
	509	return read_gpio(PORTC_PIDR_ADDR, PORT_PIDR_B6_BIT, result);
	510	case 12:
	511	/* PC7 */
	512	return read_gpio(PORTC_PIDR_ADDR, PORT_PIDR_B7_BIT, result);
	513	case 13:
	514	/* PC5 */
	515	return read_gpio(PORTC_PIDR_ADDR, PORT_PIDR_B5_BIT, result);
	516	}
	517
	518	return E_PAR;
	519	}
	520
	521	#define arduino_ad_table_count 64
	522	static uint16_t arduino_ad_table[8][arduino_ad_table_count];
	523	static int arduino_ad_pos = 0;
	524	static uint32_t arduino_ad_avelage[8];
	525
	526	ER arduino_analogRead(int pin, int *value)
	527	{
	528	switch(pin){
	529	case 14:
	530	/* value = sil_reh_mem((uint16_t )S12AD_ADDR0_ADDR); */
	531	value = 1023 - (arduino_ad_avelage[0] / (arduino_ad_table_count 4/12bit¨10bit/));
	532	return E_OK;
	533	case 15:
	534	/* value = sil_reh_mem((uint16_t )S12AD_ADDR1_ADDR); */
	535	value = 1023 - (arduino_ad_avelage[1] / (arduino_ad_table_count 4/12bit¨10bit/));
	536	return E_OK;
	537	case 16:
	538	/* value = sil_reh_mem((uint16_t )S12AD_ADDR2_ADDR); */
	539	value = 1023 - (arduino_ad_avelage[2] / (arduino_ad_table_count 4/12bit¨10bit/));
	540	return E_OK;
	541	case 17:
	542	/* value = sil_reh_mem((uint16_t )S12AD_ADDR3_ADDR); */
	543	value = 1023 - (arduino_ad_avelage[3] / (arduino_ad_table_count 4/12bit¨10bit/));
	544	return E_OK;
	545	case 18:
	546	/* value = sil_reh_mem((uint16_t )S12AD_ADDR4_ADDR); */
	547	value = 1023 - (arduino_ad_avelage[4] / (arduino_ad_table_count 4/12bit¨10bit/));
	548	return E_OK;
	549	case 19:
	550	/* value = sil_reh_mem((uint16_t )S12AD_ADDR5_ADDR); */
	551	value = 1023 - (arduino_ad_avelage[5] / (arduino_ad_table_count 4/12bit¨10bit/));
	552	return E_OK;
	553	case 20:
	554	/* value = sil_reh_mem((uint16_t )S12AD_ADDR6_ADDR); */
	555	value = 1023 - (arduino_ad_avelage[6] / (arduino_ad_table_count 4/12bit¨10bit/));
	556	return E_OK;
	557	case 21:
	558	/* value = sil_reh_mem((uint16_t )S12AD_ADDR7_ADDR); */
	559	value = 1023 - (arduino_ad_avelage[7] / (arduino_ad_table_count 4/12bit¨10bit/));
	560	return E_OK;
	561	}
	562
	563	return E_PAR;
	564	}
	565
	566	ER arduino_analogWrite(int pin, int value)
	567	{
	568	change_pin_function(pin, false);
	569
	570	value = (value * TPU_BASE_COUNTER) / 255;
	571
	572	switch(pin){
	573	case 0:
	574	/* P21/TIOCA3 */
	575	sil_wrh_mem(TPU3_TGRA_ADDR, value);
	576	return E_OK;
	577	case 1:
	578	/* P20/TIOCB3 */
	579	sil_wrh_mem(TPU3_TGRB_ADDR, value);
	580	return E_OK;
	581	case 2:
	582	/* P22/TIOCC3 */
	583	sil_wrh_mem(TPU3_TGRC_ADDR, value);
	584	return E_OK;
	585	case 3:
	586	/* P23/TIOCD3 */
	587	sil_wrh_mem(TPU3_TGRD_ADDR, value);
	588	return E_OK;
	589	case 4:
	590	/* P24/TIOCB4 */
	591	sil_wrh_mem(TPU4_TGRB_ADDR, value);
	592	return E_OK;
	593	case 5:
	594	/* P25/TIOCA4 */
	595	sil_wrh_mem(TPU4_TGRA_ADDR, value);
	596	return E_OK;
	597	case 6:
	598	/* P32/TIOCC0 */
	599	sil_wrh_mem(TPU0_TGRC_ADDR, value);
	600	return E_OK;
	601	case 7:
	602	/* P33/TIOCD0 */
	603	sil_wrh_mem(TPU0_TGRD_ADDR, value);
	604	return E_OK;
	605	}
	606
	607	return E_PAR;
	608	}
	609
	610	void arduino_tick()
	611	{
	612	static volatile uint16_t *const regs[8] = {
	613	S12AD_ADDR0_ADDR,
	614	S12AD_ADDR1_ADDR,
	615	S12AD_ADDR2_ADDR,
	616	S12AD_ADDR3_ADDR,
	617	S12AD_ADDR4_ADDR,
	618	S12AD_ADDR5_ADDR,
	619	S12AD_ADDR6_ADDR,
	620	S12AD_ADDR7_ADDR
	621	};
	622	uint16_t ad_value;
	623	int i;
	624
	625	/* ADCÌÏ·Êæ¾ */
	626	if((sil_reb_mem((uint8_t *)S12AD_ADCSR_ADDR) & S12AD_ADCSR_ADST_BIT) == 0){
	627	for (i = 0; i < 8; i++){
	628	arduino_ad_avelage[i] -= arduino_ad_table[i][arduino_ad_pos];
	629	ad_value = sil_reh_mem(regs[i]);
	630	arduino_ad_table[i][arduino_ad_pos] = ad_value;
	631	arduino_ad_avelage[i] += ad_value;
	632	}
	633
	634	arduino_ad_pos++;
	635	if(arduino_ad_pos >= arduino_ad_table_count){
	636	arduino_ad_pos = 0;
	637	}
	638
	639	/* Ï·JniVOXL[hj */
	640	sil_wrb_mem((uint8_t *)S12AD_ADCSR_ADDR, S12AD_ADCSR_ADST_BIT);
	641	}
	642	}

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