1 | /*
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2 | * TOPPERS Software
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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4 | *
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5 | * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
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6 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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7 | * Copyright (C) 2018,2019 by Naoki Saito
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8 | * Nagoya Municipal Industrial Research Institute, JAPAN
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9 | *
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10 | * ä¸è¨èä½æ¨©è
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11 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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12 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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13 | * å¤ã»åé
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14 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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15 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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16 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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17 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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18 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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19 | * ç¨ã§ããå½¢ã§åé
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20 | å¸ããå ´åã«ã¯ï¼åé
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21 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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22 | * è
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23 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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24 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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25 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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26 | * ç¨ã§ããªãå½¢ã§åé
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27 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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28 | * ã¨ï¼
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29 | * (a) åé
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30 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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31 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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32 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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33 | * (b) åé
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34 | å¸ã®å½¢æ
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35 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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36 | * å ±åãããã¨ï¼
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37 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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38 | * 害ãããï¼ä¸è¨èä½æ¨©è
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39 | ããã³TOPPERSããã¸ã§ã¯ããå
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40 | 責ãããã¨ï¼
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41 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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42 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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43 | ããã³TOPPERSããã¸ã§ã¯ãã
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44 | * å
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45 | 責ãããã¨ï¼
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46 | *
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47 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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48 | ã
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49 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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50 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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51 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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52 | * ã®è²¬ä»»ãè² ããªãï¼
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53 | *
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54 | */
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55 | /*
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56 | * ãããä¾åå¦çï¼BCM2837ç¨ï¼
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57 | */
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58 | #include <sil.h>
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59 | #include "kernel_impl.h"
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60 |
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61 | /*
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62 | * ããã»ããµã®å²è¾¼ã¿åªå
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63 | 度
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64 | */
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65 | PRI current_intpri;
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66 |
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67 | /*
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68 | * ãããã®åæå
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69 | */
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70 | void
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71 | chip_initialize(void)
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72 | {
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73 | uint32_t tmp;
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74 |
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75 | /*
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76 | * ARM64ä¾åã®åæå
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77 | */
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78 | core_initialize();
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79 |
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80 | /*
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81 | * ã¢ã©ã¤ã¡ã³ããã§ãã¯æå¹
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82 | */
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83 | tmp = (1<<3)|(1<<1);
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84 | Asm("msr sctlr_el1, %0"::"r"(tmp));
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85 |
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86 | /*
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87 | * å²è¾¼ã¿ãã¹ã¯ã®åæå
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88 | */
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89 | sil_wrw_mem((uint32_t *)(DISABLE_IRQ_B), 0xffffffff); // basic interrupt
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90 | sil_wrw_mem((uint32_t *)(DISABLE_IRQ_1), 0xffffffff); // gpu1
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91 | sil_wrw_mem((uint32_t *)(DISABLE_IRQ_2), 0xffffffff); // gpu2
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92 |
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93 | // 使ç¨ããå²è¾¼ã¿ã®è¨±å¯
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94 | chip_unmask_interrupt(0);
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95 | }
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96 |
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97 | /*
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98 | * ãããã®çµäºå¦ç
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99 | */
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100 | void
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101 | chip_terminate(void)
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102 | {
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103 | /*
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104 | * å²è¾¼ã¿ç¦æ¢
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105 | */
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106 | chip_mask_interrupt(INT_IPM(TMIN_INTPRI));
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107 |
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108 | core_terminate();
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109 | }
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110 |
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111 | /*
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112 | * å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§ã®è¨å®
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113 | */
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114 | void
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115 | x_config_int(INTNO intno, ATR intatr, PRI intpri)
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116 | {
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117 | // BCM283X ã¯ã¨ãã¸/ã¬ãã«ã®è¨å®ãå²è¾¼ã¿åªå
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118 | 度ã®è¨å®æ©è½ãæããªã
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119 | assert(VALID_INTNO(intno));
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120 | assert(TMIN_INTPRI <= intpri && intpri <= TMAX_INTPRI);
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121 | }
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122 |
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123 | /*
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124 | * çºçããå²è¾¼ã¿ã®åªå
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125 | 度ã«å¿ãã¦å²è¾¼ã¿ããã¹ã¯ãã
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126 | * å²è¾¼ã¿ã®å
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127 | ¥å£å¦çããã³åæåå¦çããå¼ã³åºããã
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128 | * priï¼å²è¾¼ã¿è¦å ã®å²è¾¼ã¿åªå
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129 | 度(å
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130 | é¨è¡¨ç¾)
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131 | */
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132 | void
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133 | chip_mask_interrupt(PRI pri)
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134 | {
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135 | uint32_t reg;
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136 | uint32_t mask_c, mask_b, mask_1, mask_2;
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137 |
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138 | current_intpri = pri;
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139 |
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140 | mask_c = _kernel_iipm_mask_table[pri * 4];
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141 | mask_b = _kernel_iipm_mask_table[pri * 4 + 1];
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142 | mask_1 = _kernel_iipm_mask_table[pri * 4 + 2];
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143 | mask_2 = _kernel_iipm_mask_table[pri * 4 + 3];
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144 |
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145 | /*
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146 | * å²è¾¼ã¿ã®ãã¹ã¯
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147 | */
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148 | // core interrupt(core timers)
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149 | reg = sil_rew_mem((uint32_t *)(0x40000040)); // Core0 Timer interrupt control
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150 | reg &= ~(mask_c & 0xf);
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151 | sil_wrw_mem((uint32_t *)(0x40000040), reg);
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152 |
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153 | // core interrupt(mailbox)
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154 | reg = sil_rew_mem((uint32_t *)(0x40000050)); // Core0 mailboxes interrupt control
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155 | reg &= ~((mask_c & 0xf0)>>4);
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156 | sil_wrw_mem((uint32_t *)(0x40000050), reg);
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157 |
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158 | // core interrupt(PMU interrupt)
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159 | if((mask_c & (1<<9)) != 0) {
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160 | sil_wrw_mem((uint32_t *)(0x40000014), 1); // PMU interrupt routing write-clear
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161 | }
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162 |
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163 | // core interrupt(AXI outstanding interrupt)
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164 | reg = sil_rew_mem((uint32_t *)(0x40000030)); // AXI outstanding interrupt
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165 | if(((mask_c & (1 << 10)) != 0) && ((reg & (1<<20)) != 0)) {
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166 | reg &= ~(1<<20);
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167 | sil_wrw_mem((uint32_t *)(0x40000030), reg);
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168 | }
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169 |
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170 | // core interrupt(local timer)
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171 | reg = sil_rew_mem((uint32_t *)(0x40000034)); // local timer control & status
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172 | if(((mask_c & (1 << 11)) != 0) && ((reg & (1<<29)) != 0)) {
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173 | reg &= ~(1<<29);
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174 | sil_wrw_mem((uint32_t *)(0x40000034), reg);
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175 | }
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176 |
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177 | // basic interrupt, GPU pending 1 and 2
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178 | sil_wrw_mem((uint32_t *)(DISABLE_IRQ_B), mask_b);
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179 | sil_wrw_mem((uint32_t *)(DISABLE_IRQ_1), mask_1);
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180 | sil_wrw_mem((uint32_t *)(DISABLE_IRQ_2), mask_2);
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181 | }
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182 |
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183 | /*
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184 | * ãã¹ã¯ããå²è¾¼ã¿ãå²è¾¼ã¿çºçåã®ç¶æ
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185 | ã«æ»ã
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186 | * ãã³ãã©å®è¡å¾ï¼åºå£å¦çã®å®è¡åã«å¼ã³åºããã
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187 | * priï¼å²è¾¼ã¿çºçåã®å²è¾¼ã¿åªå
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188 | 度
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189 | */
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190 | void
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191 | chip_unmask_interrupt(PRI pri)
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192 | {
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193 | uint32_t reg;
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194 | uint32_t mask_c, mask_b, mask_1, mask_2;
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195 |
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196 | current_intpri = pri;
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197 |
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198 | mask_c = ~(_kernel_iipm_mask_table[pri * 4]);
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199 | mask_b = ~(_kernel_iipm_mask_table[pri * 4 + 1]);
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200 | mask_1 = ~(_kernel_iipm_mask_table[pri * 4 + 2]);
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201 | mask_2 = ~(_kernel_iipm_mask_table[pri * 4 + 3]);
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202 |
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203 | /*
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204 | * ãã¹ã¯è§£é¤
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205 | */
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206 | // core interrupt(core timers)
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207 | reg = sil_rew_mem((uint32_t *)(0x40000040)); // Core0 Timer interrupt control
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208 | reg |= (mask_c & 0xf);
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209 | sil_wrw_mem((uint32_t *)(0x40000040), reg);
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210 |
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211 | // core interrupt(mailbox)
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212 | reg = sil_rew_mem((uint32_t *)(0x40000050)); // Core0 mailboxes interrupt control
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213 | reg |= (mask_c & 0xf0)>>4;
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214 | sil_wrw_mem((uint32_t *)(0x40000050), reg);
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215 |
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216 | // core interrupt(PMU interrupt)
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217 | if((mask_c & (1<<9)) != 0) {
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218 | sil_wrw_mem((uint32_t *)(0x40000010), 1); // PMU interrupt routing write-set
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219 | }
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220 |
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221 | // core interrupt(AXI outstanding interrupt)
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222 | reg = sil_rew_mem((uint32_t *)(0x40000030)); // AXI outstanding interrupt
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223 | if(((mask_c & (1 << 10)) != 0) && ((reg & (1<<20)) == 0)) {
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224 | reg |= (1<<20);
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225 | sil_wrw_mem((uint32_t *)(0x40000030), reg);
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226 | }
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227 |
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228 | // core interrupt(local timer)
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229 | reg = sil_rew_mem((uint32_t *)(0x40000034)); // local timer control & status
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230 | if(((mask_c & (1 << 11)) != 0) && ((reg & (1<<29)) == 0)) {
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231 | reg |= (1<<29);
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232 | sil_wrw_mem((uint32_t *)(0x40000034), reg);
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233 | }
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234 |
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235 | // basic interrupt, GPU pending 1 and 2
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236 | sil_wrw_mem((uint32_t *)(ENABLE_IRQ_B), mask_b);
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237 | sil_wrw_mem((uint32_t *)(ENABLE_IRQ_1), mask_1);
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238 | sil_wrw_mem((uint32_t *)(ENABLE_IRQ_2), mask_2);
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239 | }
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