source: ssp_qb_r5f100le_cs/trunk/target/qb_r5f100le_cs/target_serial.c@ 93

Last change on this file since 93 was 93, checked in by nmir-saito, 8 years ago

add Combined package of SSP kernel for QB-R5F100LE-TB(RL78 processor)

File size: 6.9 KB
Line 
1/*
2 * TOPPERS/SSP Kernel
3 * Toyohashi Open Platform for Embedded Real-Time Systems/
4 * Advanced Standard Profile Kernel
5 *
6 * Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
7 * Graduate School of Information Science, Nagoya Univ., JAPAN
8 * Copyright (C) 2010 by Meika Sugimoto
9 * Copyright (C) 2011-2015 by Naoki Saito
10 * Nagoya Municipal Industrial Research Institute, JAPAN
11 *
12 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì(1)`(4)‚ÌðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒF
13 * ƒAi–{ƒ\ƒtƒgƒEƒFƒA‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü
14 * •ÏEÄ”z•ziˆÈ‰ºC—˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
15 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
16 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
17 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
18 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
19 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
20ƒƒ“ƒgi—˜—p
21 * ŽÒƒ}ƒjƒ…
22ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
23 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
24 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
25 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
26 * ‚ƁD
27 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
28ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
29ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
30 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
31 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
32 * •ñ‚·‚邱‚ƁD
33 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
34 * ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
35 * ‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚̃†[ƒU‚Ü‚½‚̓Gƒ“ƒhƒ†[ƒU‚©‚ç‚Ì‚¢‚©‚Ȃ闝
36 * —R‚ÉŠî‚­¿‹‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð
37 * –Ɛӂ·‚邱‚ƁD
38 *
39 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
40 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC“Á’è‚ÌŽg—p–Ú“I
41 * ‚ɑ΂·‚é“K‡«‚àŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒF
42 * ƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»
43 * ‚̐ӔC‚𕉂í‚È‚¢D
44 *
45 */
46
47/*
48 * ƒVƒŠƒAƒ‹ƒhƒ‰ƒCƒoiQB-R5F100LE—pj
49 */
50#pragma sfr
51#pragma NOP
52
53#include <kernel.h>
54#include "target_serial.h"
55#include "target_syssvc.h"
56
57/*
58 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒgŠÇ—ƒuƒƒbƒNƒGƒŠƒA
59 */
60static SIOPCB siopcb_table[TNUM_SIOP];
61
62
63/*
64 * ƒŒƒWƒXƒ^Ý’è’l
65 */
66#define PORT2SIOPID(x) ((x) + 1)
67#define INDEX_PORT(x) ((x) - 1)
68#define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)])
69
70extern void x_clear_int(INTNO intno);
71
72/*
73 * ’჌ƒxƒ‹ƒVƒŠƒAƒ‹‰Šú‰»
74 */
75void target_sau_init(ID siopid)
76{
77 /* ‰Šú‰»Ï‚݂̏ꍇ‚Í‚·‚®‚ɃŠƒ^[ƒ“ */
78 if(PER0 & TBIT_PER0_SAU0EN) {
79 return;
80 }
81
82 /* ƒNƒƒbƒN‹Ÿ‹‹‹–‰Â */
83 PER0 |= TBIT_PER0_SAU0EN;
84
85 // ­‚µ‘Ò‚Â
86 NOP();
87 NOP();
88 NOP();
89
90 // CKm0 ‚ð‘I‘ðDŽü”g”‚Í fclk/8 (=2.5MHz)
91 SPS0 = UINT16_C(0x0033);
92
93 // ƒ†ƒjƒbƒg0Cƒ`ƒƒƒlƒ‹{0,1} ‚Ì“®ì’âŽ~
94 ST0 |= UINT16_C(0x0003);
95
96 // ƒ‚[ƒhÝ’è
97 // “®ìƒNƒƒbƒNFSPS0ƒŒƒWƒXƒ^‚Őݒ肵‚½“®ìƒNƒƒbƒN‚Ì‚¤‚¿CCK00 ‚Ì•û‚ðŽg‚¤
98 // “]‘—ƒNƒƒbƒNFCKS00, CKS01 ƒrƒbƒg‚ÅŽw’肵‚½“®ìƒNƒƒbƒN(‚‚܂èCK00)‚Ì•ªŽüƒNƒƒbƒN
99 // ƒXƒ^[ƒgƒgƒŠƒK—vˆöF‘—M-->ƒ\ƒtƒgƒEƒFƒAƒgƒŠƒK‚Ì‚Ý, ŽóM-->RxD0’[Žq
100 // —§‰º‚è‚ðƒXƒ^[ƒgƒrƒbƒg‚Æ‚µ‚ÄŒŸo
101 // UARTƒ‚[ƒhCŠ„‚荞‚Ý‚Í“]‘—Š®—¹Š„ž‚Ý
102 SMR00 = UINT16_C(0x0022);
103 SMR01 = UINT16_C(0x0122);
104
105 // ƒ`ƒƒƒlƒ‹0: ‘—M‚Ì‚Ý‹–‰ÂCƒ`ƒƒƒlƒ‹1: ŽóM‚Ì‚Ý‹–‰Â
106 // ƒGƒ‰[Š„ž‚ÝINTSREx‚Ì”­¶‚ð‹ÖŽ~
107 // ƒpƒŠƒeƒB‚È‚µCLSBƒtƒ@[ƒXƒgC1ƒXƒgƒbƒvƒrƒbƒgC8ƒrƒbƒgƒf[ƒ^’·
108 SCR00 = UINT16_C(0x8097);
109 SCR01 = UINT16_C(0x4097);
110
111 // [ƒrƒbƒg15:9] = 0x40 --> 64
112 // ƒVƒŠƒAƒ‹‚Ö‚Ì‹Ÿ‹‹ƒNƒƒbƒN‚Í 2.5MHz(=20/8)
113 // •ªŽü”ä‚Í (64+1)*2 = 130
114 // 2.5[MHz]/130 = 19.23[kHz]
115 SDR00 = UINT16_C(0x8000);
116 SDR01 = UINT16_C(0x8000);
117
118 // ŽóMƒ|[ƒg‚̃mƒCƒYƒtƒBƒ‹ƒ^ON
119 NFEN0 |= UINT8_C(0x01);
120
121 // ƒGƒ‰[ƒtƒ‰ƒO‚̃NƒŠƒA(ŽóM‘¤‚̃`ƒƒƒlƒ‹1‚Ì‚Ý)
122 SIR01 |= UINT16_C(0x0007);
123
124 // ƒVƒŠƒAƒ‹ƒf[ƒ^o—Í’l‚ðƒ`ƒƒƒlƒ‹0‚Ì‚Ý1‚Æ‚·‚éD
125 SO0 |= UINT16_C(0x0001);
126
127 // ’ʐMƒf[ƒ^‚Í”½“]‚¹‚¸‚»‚̂܂܏o—Í
128 SOL0 = UINT16_C(0x0000);
129
130 /*
131 * ƒVƒŠƒAƒ‹ƒ`ƒƒƒlƒ‹0ŠJŽn
132 */
133 // ƒVƒŠƒAƒ‹o—Í‹–‰Â
134 SOE0 |= UINT16_C(0x0001);
135
136 // ƒ`ƒƒƒlƒ‹{0,1}‚ÌŠJŽn
137 SS0 |= UINT16_C(0x0003);
138}
139
140/*
141 * SIO‰Šú‰»
142 */
143void sio_initialize(intptr_t exinf)
144{
145}
146
147/*
148 * ƒVƒŠƒAƒ‹ƒI[ƒvƒ“
149 */
150SIOPCB *sio_opn_por(ID siopid, intptr_t exinf)
151{
152 int_t i;
153 SIOPCB* p_siopcb;
154
155 if (siopid > TNUM_PORT) {
156 return NULL;
157 }
158
159 p_siopcb = GET_SIOPCB(siopid);
160 p_siopcb->enacb &= ~TBIT_ENACB_SND;
161 p_siopcb->enacb &= ~TBIT_ENACB_RCV;
162 p_siopcb->exinf = exinf;
163
164 // Š„ž‚݂̃}ƒXƒN
165 dis_int(INTNO_INTST0);
166 dis_int(INTNO_INTSR0);
167 // Š„ž‚Ý—v‹ƒNƒŠƒA
168 x_clear_int(INTNO_INTST0);
169 x_clear_int(INTNO_INTSR0);
170
171 // ƒn[ƒhƒEƒFƒA‚̏‰Šú‰»
172 target_sau_init(siopid);
173
174 return p_siopcb;
175}
176
177/*
178 * ƒVƒŠƒAƒ‹ƒNƒ[ƒY
179 */
180void sio_cls_por(SIOPCB *p_siopcb)
181{
182 /* ‘—ŽóM‹ÖŽ~ */
183
184 // ƒ`ƒƒƒlƒ‹{0,1}‚Ì’âŽ~
185 ST0 |= UINT16_C(0x0003);
186
187 /* ƒVƒŠƒAƒ‹ƒ‚ƒWƒ…
188[ƒ‹‚𖳌ø‚É‚·‚é */
189 PER0 &= ~TBIT_PER0_SAU0EN;
190}
191
192
193/*
194 * 1•¶Žš‘—M
195 */
196bool_t
197sio_snd_chr(SIOPCB *p_siopcb, char c)
198{
199 // ‘—Mƒoƒbƒtƒ@‚ª‹ó‚È‚ç‚΁C1•¶Žš‘—M
200 if((SSR00L & TBIT_SSRmnL_TSF) == UINT16_C(0)) {
201 SDR00 = (uint16_t)c;
202
203 return true;
204 }
205
206 return false;
207}
208
209/*
210 * 1•¶ŽšŽóM
211 */
212int_t
213sio_rcv_chr(SIOPCB *p_siopcb)
214{
215 int_t c = -1;
216
217 // ŽóMƒoƒbƒtƒ@‚Ƀf[ƒ^‚ª‚ ‚ê‚΁C1•¶ŽšŽóM
218 if((SSR01L & TBIT_SSRmnL_BFF) != 0) {
219 c = (int_t)SDR01;
220 }
221
222 return c;
223}
224
225/*
226 * ƒR[ƒ‹ƒoƒbƒN‚Ì‹–‰Â
227 */
228void
229sio_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
230{
231 switch (cbrtn) {
232 case SIO_RDY_SND:
233 p_siopcb->enacb |= TBIT_ENACB_SND;
234 x_clear_int(INTNO_INTST0);
235 ena_int(INTNO_INTST0);
236 break;
237 case SIO_RDY_RCV:
238 p_siopcb->enacb |= TBIT_ENACB_RCV;
239 x_clear_int(INTNO_INTSR0);
240 ena_int(INTNO_INTSR0);
241 break;
242 default:
243 break;
244 }
245}
246
247/*
248 * ƒR[ƒ‹ƒoƒbƒN‚Ì‹ÖŽ~
249 */
250void
251sio_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
252{
253 switch (cbrtn) {
254 case SIO_RDY_SND:
255 p_siopcb->enacb &= ~TBIT_ENACB_SND;
256 dis_int(INTNO_INTST0);
257 x_clear_int(INTNO_INTST0);
258 break;
259 case SIO_RDY_RCV:
260 p_siopcb->enacb &= ~TBIT_ENACB_RCV;
261 dis_int(INTNO_INTSR0);
262 x_clear_int(INTNO_INTSR0);
263 break;
264 default:
265 break;
266 }
267}
268
269
270/*
271 * Š„ž‚݃T[ƒrƒXƒ‹[ƒ`ƒ“
272 */
273
274/*
275 * ŽóMŠ„ž‚Ý
276 */
277void
278sio_isr_rcv(intptr_t portid)
279{
280 SIOPCB *p_siopcb = GET_SIOPCB((ID)portid);
281
282 if((p_siopcb->enacb & TBIT_ENACB_RCV) != 0) {
283 /*
284 * ŽóM’Ê’mƒR[ƒ‹ƒoƒbƒNƒ‹[ƒ`ƒ“‚ðŒÄ‚яo‚·D
285 */
286 sio_irdy_rcv(p_siopcb->exinf);
287 }
288}
289
290/*
291 * ‘—MŠ„ž‚Ý
292 */
293void
294sio_isr_snd(intptr_t portid)
295{
296 SIOPCB *p_siopcb = GET_SIOPCB((ID)portid);
297
298 if((p_siopcb->enacb & TBIT_ENACB_SND) != 0) {
299 /*
300 * ‘—M’Ê’mƒR[ƒ‹ƒoƒbƒNƒ‹[ƒ`ƒ“‚ðŒÄ‚яo‚·D
301 */
302 sio_irdy_snd(p_siopcb->exinf);
303 }
304}
305
306/*
307 * 1•¶Žšo—́iƒ|[ƒŠƒ“ƒO‚ł̏o—́j
308 */
309void
310sio_pol_snd_chr(char c, ID siopid)
311{
312 /* ‘—Mƒoƒbƒtƒ@‚ª‹ó‚É‚È‚é‚Ü‚Å‘Ò‚Â(—LŒÀŽžŠÔ“à‚ÌðŒ¬—§‚ð‰¼’è) */
313 while((SSR00L & TBIT_SSRmnL_TSF) != 0){}
314
315 // 1•¶Žš‘—M
316 SDR00 = (uint16_t)c;
317}
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