source: ssp_qb_r5f100le_cs/trunk/target/cq_frk_fm3_gcc/target_serial.c@ 93

Last change on this file since 93 was 93, checked in by nmir-saito, 8 years ago

add Combined package of SSP kernel for QB-R5F100LE-TB(RL78 processor)

File size: 8.4 KB
Line 
1/*
2 * TOPPERS/SSP Kernel
3 * Toyohashi Open Platform for Embedded Real-Time Systems/
4 * Advanced Standard Profile Kernel
5 *
6 * Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
7 * Graduate School of Information Science, Nagoya Univ., JAPAN
8 * Copyright (C) 2012 by Meika Sugimoto
9 * Copyright (C) 2015 by Naoki Saito
10 * Nagoya Municipal Industrial Research Institute, JAPAN
11 *
12 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì(1)`(4)‚ÌðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒF
13 * ƒAi–{ƒ\ƒtƒgƒEƒFƒA‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü
14 * •ÏEÄ”z•ziˆÈ‰ºC—˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
15 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
16 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
17 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
18 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
19 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
20ƒƒ“ƒgi—˜—p
21 * ŽÒƒ}ƒjƒ…
22ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
23 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
24 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
25 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
26 * ‚ƁD
27 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
28ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
29ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
30 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
31 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
32 * •ñ‚·‚邱‚ƁD
33 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
34 * ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
35 * ‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚̃†[ƒU‚Ü‚½‚̓Gƒ“ƒhƒ†[ƒU‚©‚ç‚Ì‚¢‚©‚Ȃ闝
36 * —R‚ÉŠî‚­¿‹‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð
37 * –Ɛӂ·‚邱‚ƁD
38 *
39 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
40 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC“Á’è‚ÌŽg—p–Ú“I
41 * ‚ɑ΂·‚é“K‡«‚àŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒF
42 * ƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»
43 * ‚̐ӔC‚𕉂í‚È‚¢D
44 *
45 */
46
47/*
48 * ƒVƒŠƒAƒ‹ƒhƒ‰ƒCƒoiCQ-FRM-FM3—pj
49 */
50
51#include <sil.h>
52#include "kernel_int.h"
53#include "target_serial.h"
54#include "target_syssvc.h"
55
56/*
57 * ƒŒƒWƒXƒ^Ý’è’l
58 */
59#define PORT2SIOPID(x) ((x) + 1)
60#define INDEX_PORT(x) ((x) - 1)
61#define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)])
62
63/*
64 * USARTƒŒƒWƒXƒ^’è‹`
65 * #define MFS_SMR(ch) (MFS_BASEADDR((ch)) + 0x00)
66 * #define MFS_SCR(ch) (MFS_BASEADDR((ch)) + 0x01)
67 * #define MFS_ESCR(ch) (MFS_BASEADDR((ch)) + 0x04)
68 * #define MFS_SSR(ch) (MFS_BASEADDR((ch)) + 0x05)
69 * #define MFS_RDRTDR(ch) (MFS_BASEADDR((ch)) + 0x08)
70 * #define MFS_BGR0(ch) (MFS_BASEADDR((ch)) + 0x0B)
71 * #define MFS_BGR1(ch) (MFS_BASEADDR((ch)) + 0x0C)
72 *
73 */
74
75/*
76 * ƒrƒbƒgŠ„‚è“–‚Ă̓oƒCƒgƒAƒNƒZƒX—p‚É‹Lq‚µ‚Ä‚¢‚é
77 */
78
79/* SCR */
80#define SCR_UPCL (1U << 7)
81#define SCR_RIE (1U << 4)
82#define SCR_TIE (1U << 3)
83#define SCR_TEIE (1U << 2)
84#define SCR_RXE (1U << 1)
85#define SCR_TXE (1U << 0)
86
87/* SMR */
88#define SMR_MODE_ASYNC_NORMAL (0U << 5)
89#define SMR_MODE_ASYNC_MULTI (1U << 5)
90#define SMR_MODE_CLKSYNC (2U << 5)
91#define SMR_MODE_LIN (3U << 5)
92#define SMR_MODE_I2C (4U << 5)
93
94#define SMR_WAKEUP (1U << 4)
95
96#define SMR_SBL_1OR3 (0U << 3) /* ESCR.ESBL = 0‚Å1 */
97#define SMR_SBL_2OR4 (1U << 3) /* ESCR.ESBL = 0‚Å2 */
98
99#define SMR_BDS_LSBFIRST (0U << 2)
100#define SMR_BDS_MSBFIRST (1U << 2)
101
102#define SMR_SOE_DISABLE (0U << 0)
103#define SMR_SOE_ENABLE (1U << 0)
104
105/* SSR */
106#define SSR_REC (1U << 7)
107#define SSR_PE (1U << 5)
108#define SSR_FRE (1U << 4)
109#define SSR_ORE (1U << 3)
110#define SSR_RDRF (1U << 2)
111#define SSR_TDRE (1U << 1)
112#define SSR_TBI (1U << 0)
113
114/* ESCR */
115#define ESCR_FLWEN_ENABLE (1U << 7)
116#define ESCR_FLWEN_DISABLE (0U << 7)
117#define ESCR_ESBL (1U << 6)
118#define ESCR_INV_NRZ (0U << 5)
119#define ESCR_INV_INVNRZ (1U << 5)
120#define ESCR_PEN (1U << 4)
121#define ESCR_PEN_DISABLE (0U << 4)
122#define ESCR_PEN_ENABLE (1U << 4)
123#define ESCR_P_EVEN (0U << 3)
124#define ESCR_P_ODD (1U << 3)
125#define ESCR_DATALEN_8 (0U << 0)
126#define ESCR_DATALEN_5 (1U << 0)
127#define ESCR_DATALEN_6 (2U << 0)
128#define ESCR_DATALEN_7 (3U << 0)
129#define ESCR_DATALEN_9 (4U << 0)
130
131
132/*
133 * ƒVƒŠƒAƒ‹I/Oƒ|[ƒgŠÇ—ƒuƒƒbƒNƒGƒŠƒA
134 */
135SIOPCB siopcb_table[TNUM_PORT];
136
137static const uint32_t sioreg_table[TNUM_PORT] = {
138 MFS_BASEADDR(0),
139#if (TNUM_PORT >= 2)
140 MFS_BASEADDR(4)
141#endif
142};
143
144Inline bool_t sio_putready(SIOPCB* siopcb)
145{
146 return ((sil_reb_mem((void*)MFS_SSR(siopcb->port)) & SSR_TDRE) != 0);
147}
148
149Inline bool_t sio_getready(SIOPCB* siopcb)
150{
151 return ((sil_reb_mem((void*)MFS_SSR(siopcb->port)) & SSR_RDRF) != 0);
152}
153
154/*
155 * ’჌ƒxƒ‹o—͂̏‰Šú‰»
156 */
157
158void target_low_output_init(ID siopid)
159{
160 uint32_t ch = INDEX_PORT(siopid);
161
162 /* ‰Šú‰»Ï‚݂̏ꍇ‚Í‚·‚®‚ɃŠƒ^[ƒ“ */
163 if((sil_reb_mem((void*)MFS_SCR(ch)) & (SCR_TXE | SCR_RXE)) != 0)
164 {
165 return ;
166 }
167
168 /* USART‚Ì–³Œø‰»CƒŠƒZƒbƒg */
169 sil_wrb_mem((void *)MFS_SCR(ch) , SCR_UPCL);
170 sil_wrb_mem((void *)MFS_SCR(ch) , 0x0);
171
172 /* ’ʐMƒ‚[ƒhÝ’è */
173 sil_wrb_mem((void *)MFS_SMR(ch) ,
174 (SMR_MODE_ASYNC_NORMAL | SMR_SBL_1OR3 | SMR_BDS_LSBFIRST | SMR_SOE_DISABLE));
175 sil_wrb_mem((void *)MFS_ESCR(ch) ,
176 (ESCR_FLWEN_DISABLE | ESCR_INV_NRZ | ESCR_PEN_DISABLE | ESCR_DATALEN_8));
177 /* ’ʐM‘¬“xÝ’è */
178 sil_wrh_mem((void *)MFS_BGR0(ch) , BPS_SETTING); /* ƒn[ƒtƒ[ƒhƒAƒNƒZƒX‚·‚é */
179 /* FIFO–³Œø‰» */
180 sil_wrb_mem((void *)MFS_FCR0(ch) , 0x00);
181 sil_wrb_mem((void *)MFS_FCR1(ch) , 0x00);
182
183 /* USART‚Ì—LŒø‰» */
184 sil_orb((void *)MFS_SMR(ch) , SMR_SOE_ENABLE);
185 sil_orb((void*)MFS_SCR(ch) , (SCR_TXE | SCR_RXE));
186}
187
188/*
189 * ƒ^[ƒQƒbƒg‚̃VƒŠƒAƒ‹‰Šú‰»
190 */
191void target_usart_init(ID siopid)
192{
193 target_low_output_init(siopid);
194
195 /* Š„ž‚Ý‹–‰Â */
196 x_clear_int(INTNO_SIO_TX);
197 x_clear_int(INTNO_SIO_RX);
198 /* Š„ž‚Ý‹ÖŽ~ */
199 (void)ena_int(INTNO_SIO_TX);
200 (void)ena_int(INTNO_SIO_RX);
201}
202
203/*
204 * ƒ^[ƒQƒbƒg‚̃VƒŠƒAƒ‹I—¹
205 */
206void target_usart_term(ID siopid)
207{
208 /* Š„ž‚Ý‹ÖŽ~ */
209 (void)dis_int(INTNO_SIO_TX);
210 (void)dis_int(INTNO_SIO_RX);
211
212 /* USART‚Ì–³Œø‰» */
213 sil_andb((void*)MFS_SCR(INDEX_PORT(siopid)) , (SCR_TXE | SCR_RIE));
214}
215
216/*
217 * SIO‰Šú‰»
218 */
219void sio_initialize(intptr_t exinf)
220{
221 int i;
222
223 for (i = 0; i < TNUM_PORT; i++) {
224 siopcb_table[i].port = i;
225 siopcb_table[i].reg = sioreg_table[i];
226 siopcb_table[i].exinf = 0;
227 }
228}
229
230/*
231 * ƒVƒŠƒAƒ‹ƒI[ƒvƒ“
232 */
233SIOPCB *sio_opn_por(ID siopid, intptr_t exinf)
234{
235 SIOPCB* siopcb;
236
237 if (siopid > TNUM_PORT) {
238 return NULL;
239 }
240
241 siopcb = GET_SIOPCB(siopid);
242 siopcb->exinf = exinf;
243
244 target_usart_init(siopid);
245
246 return siopcb;
247}
248
249/*
250 * ƒVƒŠƒAƒ‹ƒNƒ[ƒY
251 */
252void sio_cls_por(SIOPCB *p_siopcb)
253{
254 target_usart_term(p_siopcb->port);
255}
256
257/*
258 * Š„ž‚݃nƒ“ƒhƒ‰
259 */
260void sio_isr_tx(intptr_t exinf)
261{
262 SIOPCB* siopcb = GET_SIOPCB(exinf);
263
264 if (sio_putready(siopcb)) {
265 sio_irdy_snd(siopcb->exinf);
266 }
267}
268
269void sio_isr_rx(intptr_t exinf)
270{
271 SIOPCB* siopcb = GET_SIOPCB(exinf);
272
273 if (sio_getready(siopcb)) {
274 sio_irdy_rcv(siopcb->exinf);
275 }
276}
277
278/*
279 * 1•¶Žš‘—M
280 */
281bool_t sio_snd_chr(SIOPCB *siopcb, char c)
282{
283 bool_t ret = false;
284
285 if (sio_putready(siopcb)) {
286 sil_wrb_mem((void*)MFS_RDRTDR(siopcb->port), c);
287
288 ret = true;
289 }
290
291 return ret;
292}
293
294/*
295 * 1•¶ŽšŽóM
296 */
297int_t sio_rcv_chr(SIOPCB *siopcb)
298{
299 int_t c = -1;
300
301 if (sio_getready(siopcb)) {
302 c = (int)sil_reb_mem((void*)MFS_RDRTDR(siopcb->port));
303 }
304
305 return c;
306}
307
308/*
309 * ƒR[ƒ‹ƒoƒbƒN‚Ì‹–‰Â
310 */
311void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn)
312{
313 switch (cbrtn) {
314 case SIO_RDY_SND:
315 sil_orb((void*)MFS_SCR(siopcb->port), SCR_TIE);
316 break;
317 case SIO_RDY_RCV:
318 sil_orb((void*)MFS_SCR(siopcb->port), SCR_RIE);
319 break;
320 default:
321 break;
322 }
323}
324
325/*
326 * ƒR[ƒ‹ƒoƒbƒN‚Ì‹ÖŽ~
327 */
328void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn)
329{
330 switch (cbrtn) {
331 case SIO_RDY_SND:
332 sil_andb((void*)MFS_SCR(siopcb->port), ~SCR_TIE);
333 break;
334 case SIO_RDY_RCV:
335 sil_andb((void*)MFS_SCR(siopcb->port), ~SCR_RIE);
336 break;
337 default:
338 break;
339 }
340}
341
342/*
343 * 1•¶Žšo—́iƒ|[ƒŠƒ“ƒO‚ł̏o—́j
344 */
345void sio_pol_snd_chr(char c, ID siopid)
346{
347 sil_wrb_mem((void*)MFS_RDRTDR(INDEX_PORT(siopid)), (int)c);
348
349 while ((sil_reb_mem((void*)MFS_SSR(INDEX_PORT(siopid))) & SSR_TDRE) == 0U)
350 ;
351}
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