source: ssp_qb_r5f100le_cs/trunk/target/cq_frk_fm3_gcc/MB9BF618T.h@ 93

Last change on this file since 93 was 93, checked in by nmir-saito, 8 years ago

add Combined package of SSP kernel for QB-R5F100LE-TB(RL78 processor)

File size: 13.5 KB
Line 
1/*
2 * TOPPERS/SSP Kernel
3 * Smallest Set Profile Kernel
4 *
5 * Copyright (C) 2012 Meika Sugimoto
6 *
7 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì(1)`(4)‚ÌðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒF
8 * ƒAi–{ƒ\ƒtƒgƒEƒFƒA‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü
9 * •ÏEÄ”z•ziˆÈ‰ºC—˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
10 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
11 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
12 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
13 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
14 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
15ƒƒ“ƒgi—˜—p
16 * ŽÒƒ}ƒjƒ…
17ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
18 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
19 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
20 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
21 * ‚ƁD
22 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
23ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
24ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
25 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
26 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
27 * •ñ‚·‚邱‚ƁD
28 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
29* ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
30 * ‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚̃†[ƒU‚Ü‚½‚̓Gƒ“ƒhƒ†[ƒU‚©‚ç‚Ì‚¢‚©‚Ȃ闝
31 * —R‚ÉŠî‚­¿‹‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð
32 * –Ɛӂ·‚邱‚ƁD
33 *
34 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
35 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC“Á’è‚ÌŽg—p–Ú“I
36 * ‚ɑ΂·‚é“K‡«‚àŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒF
37 * ƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»
38 * ‚̐ӔC‚𕉂í‚È‚¢D
39 *
40 */
41
42#ifndef TOPPERS_MB9BF618T_H
43#define TOPPERS_MB9BF618T_H
44
45/*
46 * CORTEX-M3 CPU‚̈ˑ¶•”‚̃Cƒ“ƒNƒ‹[ƒh
47 */
48#include "arm_m_gcc/arm_m.h"
49
50/*
51 * ƒvƒƒZƒbƒT‚̃Gƒ“ƒfƒBƒAƒ“’è‹`
52 * MB9BF618T‚̓Šƒgƒ‹ƒGƒ“ƒfƒBƒAƒ“
53 */
54#define SIL_ENDIAN_LITTLE
55
56
57/*
58 * Š„ž‚ݔԍ†‚̍őå’l
59 */
60#define TMAX_INTNO (16 + 48)
61
62/*
63 * Š„ž‚Ý—Dæ“x‚̃rƒbƒg•
64 */
65#define TBITW_IPRI (4)
66
67
68/*
69 * Š„ž‚݃xƒNƒ^”ԍ†’è‹`
70 */
71#define INT_FCS (16)
72#define INT_LVD (17)
73#define INT_SW_WDT (18)
74#define INT_MFT (19)
75#define INT_EXTI0TO7 (20)
76#define INT_EXT_8TO31 (21)
77#define INT_DUALTMR_QPRC (22)
78#define INT_MFS0_RX (23)
79#define INT_MFS0_TX (24)
80#define INT_MFS1_RX (25)
81#define INT_MFS1_TX (26)
82#define INT_MFS2_RX (27)
83#define INT_MFS2_TX (28)
84#define INT_MFS3_RX (29)
85#define INT_MFS3_TX (30)
86#define INT_MFS4_RX (31)
87#define INT_MFS4_TX (32)
88#define INT_MFS5_RX (33)
89#define INT_MFS5_TX (34)
90#define INT_MFS6_RX (35)
91#define INT_MFS6_TX (36)
92#define INT_MFS7_RX (37)
93#define INT_MFS7_TX (38)
94#define INT_PPG (39)
95#define INT_CLK_CNT (40)
96#define INT_AD0 (41)
97#define INT_AD1 (42)
98#define INT_AD2 (43)
99#define INT_BASETMR_0TO7 (44)
100#define INT_MFT_FREERUN (45)
101#define INT_MFT_INCAPTURE (46)
102#define INT_OUTCOMPARE (47)
103#define INT_CAN0_ETH0 (48)
104#define INT_CAN1_ETH1 (49)
105#define INT_USB0_FNC (50)
106#define INT_USB0_FNCHOST (51)
107#define INT_USB1_FNC (52)
108#define INT_USB1_FNCHOST (53)
109#define INT_DMA0 (54)
110#define INT_DMA1 (55)
111#define INT_DMA2 (56)
112#define INT_DMA3 (57)
113#define INT_DMA4 (58)
114#define INT_DMA5 (59)
115#define INT_DMA6 (60)
116#define INT_DMA7 (61)
117#define INT_BASETMR_8TO15 (62)
118#define INT_RESERVE (63)
119
120
121/*
122 * Š„ž‚Ý—Dæ“xƒrƒbƒg•’†‚̃Tƒu—Dæ“x‚̃rƒbƒg•
123 */
124#define TBITW_SUBIPRI 0
125
126
127/* MB9BF618T‚̃yƒŠƒtƒFƒ‰ƒ‹ƒŒƒWƒXƒ^’è‹` */
128
129/* BUS:AHB */
130#define AHBPERIPH_BASE (0x40000000)
131
132#define FLASHIF_BASE (AHBPERIPH_BASE + 0x0000)
133
134/* BUS:APB0 */
135#define APB0PERIPH_BASE (0x40010000)
136
137#define CLOCKRESET_BASE (APB0PERIPH_BASE + 0x0000)
138#define HW_WDT_BASE (APB0PERIPH_BASE + 0x1000)
139#define SW_WDT_BASE (APB0PERIPH_BASE + 0x2000)
140#define DUALTMR_BASE (APB0PERIPH_BASE + 0x5000)
141
142/* BUS:APB1 */
143#define APB1PERIPH_BASE (0x40020000)
144#define MFT0_BASE (APB1PERIPH_BASE + 0x0000)
145#define MFT1_BASE (APB1PERIPH_BASE + 0x1000)
146#define PPG_BASE (APB1PERIPH_BASE + 0x4000)
147#define BASETMR_BASE (APB1PERIPH_BASE + 0x5000)
148#define QUADCNT_BASE (APB1PERIPH_BASE + 0x5000)
149#define ADCONV_BASE (APB1PERIPH_BASE + 0x7000)
150#define HSPDCR_TRIM_BASE (APB1PERIPH_BASE + 0xE000)
151
152/* BUS:APB2 */
153#define APB2PERIPH_BASE (0x40030000)
154#define EXTI_BASE (APB2PERIPH_BASE + 0x0000)
155#define INTREQ_BASE (APB2PERIPH_BASE + 0x1000)
156#define GPIO_BASE (APB2PERIPH_BASE + 0x3000)
157#define LVD_BASE (APB2PERIPH_BASE + 0x5000)
158#define DSTBY_MODE_BASE (APB2PERIPH_BASE + 0x5800)
159#define USBCLK_BASE (APB2PERIPH_BASE + 0x6000)
160#define CAN_PRESCL_BASE (APB2PERIPH_BASE + 0x7000)
161#define MFS_BASE (APB2PERIPH_BASE + 0x8000)
162#define CRC_BASE (APB2PERIPH_BASE + 0x9000)
163#define WATCHCNT_BASE (APB2PERIPH_BASE + 0xA000)
164#define RTC_BASE (APB2PERIPH_BASE + 0xB000)
165#define EXTBUS_BASE (APB2PERIPH_BASE + 0xF000)
166
167/* BUS:AHB */
168#define USB_CH0_BASE (AHBPERIPH_BASE + 0x40000)
169#define USB_CH1_BASE (AHBPERIPH_BASE + 0x50000)
170#define DMAC_BASE (AHBPERIPH_BASE + 0x60000)
171#define CAN_CH0_BASE (AHBPERIPH_BASE + 0x62000)
172#define CAN_CH1_BASE (AHBPERIPH_BASE + 0x63000)
173#define ETH0_BASE (AHBPERIPH_BASE + 0x64000)
174#define ETHSYS_BASE (AHBPERIPH_BASE + 0x66000)
175#define ETH1_BASE (AHBPERIPH_BASE + 0x67000)
176
177#define FLASHIF_WORK_BASE (0x200E0000)
178
179/* ƒNƒƒbƒN/ƒŠƒZƒbƒgŠÖ˜A‚̃ŒƒWƒXƒ^ */
180#define SCM_CTL (CLOCKRESET_BASE + 0x0000)
181#define SCM_STR (CLOCKRESET_BASE + 0x0004)
182#define STB_CTL (CLOCKRESET_BASE + 0x0008) /* 4byte access */
183#define RST_STR (CLOCKRESET_BASE + 0x000C) /* 2byte access */
184#define BSC_PSR (CLOCKRESET_BASE + 0x0010)
185#define APBC0_PSR (CLOCKRESET_BASE + 0x0014)
186#define APBC1_PSR (CLOCKRESET_BASE + 0x0018)
187#define APBC2_PSR (CLOCKRESET_BASE + 0x001C)
188#define TTC_PSR (CLOCKRESET_BASE + 0x0028)
189#define CSW_PSR (CLOCKRESET_BASE + 0x0030)
190#define PSW_TMR (CLOCKRESET_BASE + 0x0034)
191#define PLL_CTL1 (CLOCKRESET_BASE + 0x0038)
192#define PLL_CTL2 (CLOCKRESET_BASE + 0x003C)
193#define INT_ENR (CLOCKRESET_BASE + 0x0060)
194#define INT_STR (CLOCKRESET_BASE + 0x0064)
195#define INT_CLR (CLOCKRESET_BASE + 0x0068)
196
197/* SCM_CTL , SCM_STR‚̃rƒbƒgŠ„“–‚Ä */
198#define SCM_CTL_RCS_HIGHCR (0 << 5)
199#define SCM_CTL_RCS_MAINCLK (1 << 5)
200#define SCM_CTL_RCS_PLLCLK (2 << 5)
201#define SCM_CTL_RCS_LOWCR (4 << 5)
202#define SCM_CTL_RCS_SUBCLK (5 << 5)
203#define SCM_CTL_RCS_MASK (7 << 5)
204
205#define SCM_CTL_MOSCE (1 << 1)
206#define SCM_CTL_SOSCE (1 << 3)
207#define SCM_CTL_PLLE (1 << 4)
208#define SCM_STR_MORDY (1 << 1)
209#define SCM_STR_SOSCE (1 << 3)
210#define SCM_STR_PLRDY (1 << 4)
211
212/* ƒNƒƒbƒN•ªŽü”äÝ’è’l */
213#define BSC_CLK_DIV_1 (0)
214#define BSC_CLK_DIV_2 (1)
215#define BSC_CLK_DIV_3 (2)
216#define BSC_CLK_DIV_4 (3)
217#define BSC_CLK_DIV_6 (4)
218#define BSC_CLK_DIV_8 (5)
219#define BSC_CLK_DIV_16 (6)
220
221/* APBƒNƒƒbƒN§ŒäÝ’è’l */
222#define APBC_EN (1 << 7)
223#define APBC_RESET (1 << 4)
224
225/* ƒNƒƒbƒN•ªŽü”äÝ’è’l */
226#define APB_CLK_DIV_1 (0)
227#define APB_CLK_DIV_2 (1)
228#define APB_CLK_DIV_4 (2)
229#define APB_CLK_DIV_8 (3)
230
231
232/* ƒNƒƒbƒNŠÖ˜AŠ„ž‚݂̃rƒbƒgŠ„“–‚Ä */
233#define INT_CLL_MCS (1 << 0)
234#define INT_CLL_SCS (1 << 1)
235#define INT_CLL_PCS (1 << 2)
236#define INT_CLL_FCS (1 << 5)
237
238/* CSW_TMR‚̃rƒbƒgŠ„“–‚Ä */
239#define PSW_TMR_MOWT_CONF0 (0 << 0) /* 2^1 / FCRH */
240#define PSW_TMR_MOWT_CONF1 (1 << 0) /* 2^5 / FCRH */
241#define PSW_TMR_MOWT_CONF2 (2 << 0) /* 2^6 / FCRH */
242#define PSW_TMR_MOWT_CONF3 (3 << 0) /* 2^7 / FCRH */
243#define PSW_TMR_MOWT_CONF4 (4 << 0) /* 2^8 / FCRH */
244#define PSW_TMR_MOWT_CONF5 (5 << 0) /* 2^9 / FCRH */
245#define PSW_TMR_MOWT_CONF6 (6 << 0) /* 2^10 / FCRH */
246#define PSW_TMR_MOWT_CONF7 (7 << 0) /* 2^11 / FCRH */
247#define PSW_TMR_MOWT_CONF8 (8 << 0) /* 2^12 / FCRH */
248#define PSW_TMR_MOWT_CONF9 (9 << 0) /* 2^13 / FCRH */
249#define PSW_TMR_MOWT_CONF10 (10 << 0) /* 2^14 / FCRH */
250#define PSW_TMR_MOWT_CONF11 (11 << 0) /* 2^16 / FCRH */
251#define PSW_TMR_MOWT_CONF12 (12 << 0) /* 2^17 / FCRH */
252#define PSW_TMR_MOWT_CONF13 (13 << 0) /* 2^19 / FCRH */
253#define PSW_TMR_MOWT_CONF14 (14 << 0) /* 2^21 / FCRH */
254#define PSW_TMR_MOWT_CONF15 (15 << 0) /* 2^23 / FCRH */
255
256/* PSW_TMR‚̃rƒbƒgŠ„“–‚Ä */
257#define PSW_TMR_PINC_MO (0 << 4)
258#define PSW_TMR_PINC_CR (1 << 4)
259#define PSW_TMR_POWT_CONF0 (0 << 0) /* 2^9 / FCRH */
260#define PSW_TMR_POWT_CONF1 (1 << 0) /* 2^10 / FCRH */
261#define PSW_TMR_POWT_CONF2 (2 << 0) /* 2^11 / FCRH */
262#define PSW_TMR_POWT_CONF3 (3 << 0) /* 2^12 / FCRH */
263#define PSW_TMR_POWT_CONF4 (4 << 0) /* 2^13 / FCRH */
264#define PSW_TMR_POWT_CONF5 (5 << 0) /* 2^14 / FCRH */
265#define PSW_TMR_POWT_CONF6 (6 << 0) /* 2^15 / FCRH */
266#define PSW_TMR_POWT_CONF7 (7 << 0) /* 2^16 / FCRH */
267
268/* PLL_CTL1 , PLL_CTL2‚̃rƒbƒgŠ„“–‚Ä */
269#define PLL_CTL1_PLLK(n) (((n) - 1) << 4)
270#define PLL_CTL1_PLLM(n) (((n) - 1) << 0)
271#define PLL_CTL2_PLLN(n) (((n) - 1) << 0)
272
273/* WDT */
274#define WDG_CTL (HW_WDT_BASE + 0x0008)
275#define WDG_LCK (HW_WDT_BASE + 0x0C00)
276
277#define WDG_RESDIS (0 << 1)
278#define WDG_RESENA (1 << 1)
279#define WDG_RESINTDIS (0 << 0)
280#define WDG_RESINTENA (1 << 0)
281
282#define WDG_UNLOCK_VAL (0x1ACCE551)
283
284/* MFS(Multi Functional Serial */
285#define MFS_BASEADDR(ch) (MFS_BASE + ((ch) * 0x0100))
286
287#define MFS_SMR(ch) (MFS_BASEADDR((ch)) + 0x00)
288#define MFS_SCR(ch) (MFS_BASEADDR((ch)) + 0x01)
289#define MFS_ESCR(ch) (MFS_BASEADDR((ch)) + 0x04)
290#define MFS_SSR(ch) (MFS_BASEADDR((ch)) + 0x05)
291#define MFS_RDRTDR(ch) (MFS_BASEADDR((ch)) + 0x08) /* 2byte access */
292#define MFS_BGR0(ch) (MFS_BASEADDR((ch)) + 0x0C)
293#define MFS_BGR1(ch) (MFS_BASEADDR((ch)) + 0x0D)
294#define MFS_FCR0(ch) (MFS_BASEADDR((ch)) + 0x14)
295#define MFS_FCR1(ch) (MFS_BASEADDR((ch)) + 0x15)
296
297/* GPIO */
298#define BITMAP_0 (1 << 0)
299#define BITMAP_1 (1 << 1)
300#define BITMAP_2 (1 << 2)
301#define BITMAP_3 (1 << 3)
302#define BITMAP_4 (1 << 4)
303#define BITMAP_5 (1 << 5)
304#define BITMAP_6 (1 << 6)
305#define BITMAP_7 (1 << 7)
306
307/* #define GPIO_BASE (APB2PERIPH_BASE + 0x3000) */
308#define PFR0 (GPIO_BASE + 0x0000)
309#define PFR1 (GPIO_BASE + 0x0004)
310#define PFR2 (GPIO_BASE + 0x0008)
311#define PFR3 (GPIO_BASE + 0x000C)
312#define PFR4 (GPIO_BASE + 0x0010)
313#define PFR5 (GPIO_BASE + 0x0014)
314#define PFR6 (GPIO_BASE + 0x0018)
315#define PFR7 (GPIO_BASE + 0x001C)
316#define PFR8 (GPIO_BASE + 0x0020)
317#define PFR9 (GPIO_BASE + 0x0024)
318#define PFRA (GPIO_BASE + 0x0028)
319#define PFRB (GPIO_BASE + 0x002C)
320#define PFRC (GPIO_BASE + 0x0030)
321#define PFRD (GPIO_BASE + 0x0034)
322#define PFRE (GPIO_BASE + 0x0038)
323#define PFRF (GPIO_BASE + 0x003C)
324
325#define PDDR0 (GPIO_BASE + 0x0200)
326#define PDDR1 (GPIO_BASE + 0x0204)
327#define PDDR2 (GPIO_BASE + 0x0208)
328#define PDDR3 (GPIO_BASE + 0x020C)
329#define PDDR4 (GPIO_BASE + 0x0210)
330#define PDDR5 (GPIO_BASE + 0x0214)
331#define PDDR6 (GPIO_BASE + 0x0218)
332#define PDDR7 (GPIO_BASE + 0x021C)
333#define PDDR8 (GPIO_BASE + 0x0220)
334#define PDDR9 (GPIO_BASE + 0x0224)
335#define PDDRA (GPIO_BASE + 0x0228)
336#define PDDRB (GPIO_BASE + 0x022C)
337#define PDDRC (GPIO_BASE + 0x0230)
338#define PDDRD (GPIO_BASE + 0x0234)
339#define PDDRE (GPIO_BASE + 0x0238)
340#define PDDRF (GPIO_BASE + 0x023C)
341
342#define PDIR0 (GPIO_BASE + 0x0300)
343#define PDIR1 (GPIO_BASE + 0x0304)
344#define PDIR2 (GPIO_BASE + 0x0308)
345#define PDIR3 (GPIO_BASE + 0x030C)
346#define PDIR4 (GPIO_BASE + 0x0310)
347#define PDIR5 (GPIO_BASE + 0x0314)
348#define PDIR6 (GPIO_BASE + 0x0318)
349#define PDIR7 (GPIO_BASE + 0x031C)
350#define PDIR8 (GPIO_BASE + 0x0320)
351#define PDIR9 (GPIO_BASE + 0x0324)
352#define PDIRA (GPIO_BASE + 0x0328)
353#define PDIRB (GPIO_BASE + 0x032C)
354#define PDIRC (GPIO_BASE + 0x0330)
355#define PDIRD (GPIO_BASE + 0x0334)
356#define PDIRE (GPIO_BASE + 0x0338)
357#define PDIRF (GPIO_BASE + 0x033C)
358
359#define PDOR0 (GPIO_BASE + 0x0400)
360#define PDOR1 (GPIO_BASE + 0x0404)
361#define PDOR2 (GPIO_BASE + 0x0408)
362#define PDOR3 (GPIO_BASE + 0x040C)
363#define PDOR4 (GPIO_BASE + 0x0410)
364#define PDOR5 (GPIO_BASE + 0x0414)
365#define PDOR6 (GPIO_BASE + 0x0418)
366#define PDOR7 (GPIO_BASE + 0x041C)
367#define PDOR8 (GPIO_BASE + 0x0420)
368#define PDOR9 (GPIO_BASE + 0x0424)
369#define PDORA (GPIO_BASE + 0x0428)
370#define PDORB (GPIO_BASE + 0x042C)
371#define PDORC (GPIO_BASE + 0x0430)
372#define PDORD (GPIO_BASE + 0x0434)
373#define PDORE (GPIO_BASE + 0x0438)
374#define PDORF (GPIO_BASE + 0x043C)
375
376#define EPFR0 (GPIO_BASE + 0x0600)
377#define EPFR1 (GPIO_BASE + 0x0604)
378#define EPFR2 (GPIO_BASE + 0x0608)
379#define EPFR3 (GPIO_BASE + 0x060C)
380#define EPFR4 (GPIO_BASE + 0x0610)
381#define EPFR5 (GPIO_BASE + 0x0614)
382#define EPFR6 (GPIO_BASE + 0x0618)
383#define EPFR7 (GPIO_BASE + 0x061C)
384#define EPFR8 (GPIO_BASE + 0x0620)
385#define EPFR9 (GPIO_BASE + 0x0624)
386#define EPFRA (GPIO_BASE + 0x0628)
387#define EPFRB (GPIO_BASE + 0x062C)
388#define EPFRC (GPIO_BASE + 0x0630)
389#define EPFRD (GPIO_BASE + 0x0634)
390#define EPFRE (GPIO_BASE + 0x0638)
391#define EPFRF (GPIO_BASE + 0x063C)
392
393#define PCR0 (GPIO_BASE + 0x0100)
394#define PCR1 (GPIO_BASE + 0x0104)
395
396
397#define ADE (GPIO_BASE + 0x0500)
398
399#endif /* TOPPERS_MB9BF618T_H */
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