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source: ssp_qb_r5f100le_cs/trunk/arch/rl78_ca78k0r/prc_config.c@ 93

Last change on this file since 93 was 93, checked in by nmir-saito, 9 years ago
add Combined package of SSP kernel for QB-R5F100LE-TB(RL78 processor)
File size: 9.5 KB

Line
1	/*
2	* TOPPERS/SSP Kernel
3	* Smallest Set Profile Kernel
4	*
5	* Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
6	* Toyohashi Univ. of Technology, JAPAN
7	* Copyright (C) 2005,2006 by Embedded and Real-Time Systems Laboratory
8	* Graduate School of Information Science, Nagoya Univ., JAPAN
9	* Copyright (C) 2008 by Witz Corporation, JAPAN
10	* Copyright (C) 2010-2014 by Naoki Saito
11	* Nagoya Municipal Industrial Research Institute, JAPAN
12	*
13	* ãLì ÒÍCÈºÌ (1)`(4) Ìðð½·êÉÀèC{\tgEF
14	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»EüÏE
15	* ÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
16	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
17	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[X
18	* R[hÉÜÜêÄ¢é±ÆD
19	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉgp
20	* Å«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
21	gipÒ}
22	* j
23	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºLÌ³Û
24	* ØKèðfÚ·é±ÆD
25	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉgp
26	* Å«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±ÆD
27	* (a) ÄzzÉº¤hL
28	gipÒ}j
29	AÈÇjÉCãLÌì
30	* \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
31	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉñ
32	* ·é±ÆD
33	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹Q
34	* ©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆDÜ½C
35	* {\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©ÈéRÉîÃ
36	* ¿©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
37	*
38	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨æ
39	* ÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚIÉÎ·
40	* éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEFAÌp
41	* Éæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»ÌÓCð
42	* íÈ¢D
43	*
44	*/
45
46	/*
47	* vZbTË¶W
48	[iRL78j
49	*/
50	#pragma EI
51	#pragma DI
52	#include <kernel_impl.h>
53
54	/*
55	* Ý¶ñðÛ¶·éÏ
56	*/
57	uint8_t intnest;
58
59
60	/*
61	* (1) ReLXgÉÖ·éè`
62	*/
63
64
65	/*
66	* ReLXgÌQÆ
67	*/
68	bool_t
69	sense_context(void)
70	{
71	/* lXgJE^0æèåÈçñ^XNReLXg */
72	return (intnest > 0);
73	}
74
75
76	/*
77	* (2) VXeóÔÉÖ·éè`
78	*/
79
80	/*
81	* CPUbNtOÀ»Ì½ßÌÏ
82	*/
83	bool_t lock_flag; /* CPUbNtOÌlðÛ·éÏ */
84	#if TMIN_INTPRI != -4
85	uint8_t saved_psw; /* ÝDæxxðÛ¶·éÏ */
86	#endif
87
88	/*
89	* CPU bNóÔÖÌÚs
90	* ±ÌÖÍCCPU bNóÔÌÆ«ÉÄÑ¾³êÈ¢±ÆðOñÆ·éD
91	*/
92	void
93	t_lock_cpu(void)
94	{
95	#if TMIN_INTPRI == -4
96	DI();
97	#else
98	/* ^XNÅÍÝDæx}XNÌlÍ 0 ÌÍ¸ÈÌÅÛ¶·éKvªÈ¢ */
99	set_psw(PSW_SET_ISP(get_psw(), ISP_LOCK));
100	#endif
101	lock_flag = true;
102	}
103
104	void
105	i_lock_cpu(void)
106	{
107	#if TMIN_INTPRI == -4
108	DI();
109	#else
110	uint8_t psw;
111
112	/*
113	* get_psw() ÌÔèlð¼Ú saved_isp ÉÛ¶¹¸CêÏ
114	* psw ÖÛ¶·éÌÍCget_psw() ÌÄÑ¾µ¼ãÉÝª¶µC
115	* N®³ê½ÝÅ saved_isp ªÏX³êéÂ\«ª é½ßD
116	*/
117	psw = get_psw();
118	if (TIPM_LOCK < ISP2IPM(PSW2ISP(psw))) {
119	set_psw(PSW_SET_ISP(psw, ISP_LOCK));
120	}
121	saved_psw = psw;
122	#endif
123	lock_flag = true;
124	}
125
126	/*
127	* CPUbNóÔÌð
128	* ±ÌÖÍCCPU bNóÔÌÆ«ÉÌÝÄÑ¾³êé±ÆðOñÆ·éD
129	*/
130	void
131	t_unlock_cpu(void)
132	{
133	lock_flag = false;
134	#if TMIN_INTPRI == -4
135	EI();
136	#else
137	/* ^XNÀsÍÝ}XNSðóÔÌÍ¸ÈÌÅCSðÉµÄ¨ */
138	set_psw(PSW_SET_ISP(get_psw(), ISP_ENAALL));
139	#endif
140	}
141
142	void
143	i_unlock_cpu(void)
144	{
145	lock_flag = false;
146	#if TMIN_INTPRI == -4
147	EI();
148	#else
149	set_psw(PSW_SET_ISP(get_psw(), PSW2ISP(saved_psw)));
150	#endif
151	}
152
153	/*
154	* CPUbNóÔÌQÆ
155	*/
156	bool_t
157	x_sense_lock(void)
158	{
159	return lock_flag;
160	}
161
162	/*
163	* ÝDæx}XN(IPM) ÌÝè
164	* wèµ½ÝDæx(-1, -2, ..., TMIN_INTPRI) ð³É
165	* vZbTÌÝDæxx (IPL) ðÝè·éD
166	*/
167	void
168	x_set_ipm(PRI intpri)
169	{
170	set_psw(PSW_SET_ISP(get_psw(), IPM2ISP(intpri)));
171	}
172
173	PRI
174	x_get_ipm(void)
175	{
176	return (ISP2IPM(PSW2ISP(get_psw())));
177	}
178
179
180
181	/*
182	* (7) dispacher ÅÌÝÒ¿
183	*/
184	void
185	idle_loop(void)
186	{
187	t_unlock_cpu();
188	t_lock_cpu();
189	}
190
191
192	/*
193	* vZbTË¶Ìú»
194	*/
195	void
196	prc_initialize(void)
197	{
198	}
199
200	/*
201	* vZbTË¶ÌI¹
202	*/
203	void
204	prc_terminate(void)
205	{
206	/* ÁÉKvÈÍÈ¢ */
207	}
208
209	/*
210	* ÝvÖ~tOÌZbg
211	*/
212	bool_t
213	x_disable_int(INTNO intno)
214	{
215	volatile uint8_t *reg_addr;
216
217	/* xè`ª0Å éêÍCFG_INT³êÄ¢È¢ */
218	if(intpri_table[intno] == 0U)
219	{
220	return (false);
221	}
222	// Ý}XNEtOEWX^ÌYrbgð1ÉZbg
223	if(intno < 32) {
224	reg_addr = (volatile uint8_t *)TADR_MK0L;
225	reg_addr += (intno/8);
226	}
227	else {
228	reg_addr = (volatile uint8_t *)TADR_MK2L;
229	reg_addr += ((intno-32) / 8);
230	}
231	*reg_addr \|= (uint8_t)(1 << (intno % 8));
232
233	return(true);
234	}
235
236	/*
237	* ÝvÖ~tOÌNA
238	*/
239	bool_t
240	x_enable_int(INTNO intno)
241	{
242	volatile uint8_t *reg_addr;
243
244	/* xè`ª0Å éêÍCFG_INT³êÄ¢È¢ */
245	if(intpri_table[intno] == 0u)
246	{
247	return (false);
248	}
249	// Ý}XNEtOEWX^ÌYrbgð0ÉZbg
250	if(intno < 32) {
251	reg_addr = (volatile uint8_t *)TADR_MK0L;
252	reg_addr += (intno/8);
253	}
254	else {
255	reg_addr = (volatile uint8_t *)TADR_MK2L;
256	reg_addr += ((intno-32) / 8);
257	}
258	*reg_addr &= (uint8_t)~(1 << (intno % 8));
259
260	return(true);
261	}
262
263	/*
264	* ÝvÌNA
265	*/
266	void
267	x_clear_int(INTNO intno)
268	{
269	volatile uint8_t *reg_addr;
270
271	// ÝvtOEWX^ÌYrbgð0ÉZbg
272	if(intno < 32) {
273	reg_addr = (volatile uint8_t *)TADR_IF0L;
274	reg_addr += (intno/8);
275	}
276	else {
277	reg_addr = (volatile uint8_t *)TADR_IF2L;
278	reg_addr += ((intno-32) / 8);
279	}
280	*reg_addr &= (uint8_t)~(1 << (intno % 8));
281	}
282
283	/*
284	* ÝvÌ`FbN
285	*/
286	bool_t
287	x_probe_int(INTNO intno)
288	{
289	volatile uint8_t *reg_addr;
290
291	// ÝvtOEWX^ÌYrbgª 1 Èç true
292	if(intno < 32) {
293	reg_addr = (volatile uint8_t *)TADR_IF0L;
294	reg_addr += (intno/8);
295	}
296	else {
297	reg_addr = (volatile uint8_t *)TADR_IF2L;
298	reg_addr += ((intno-32) / 8);
299	}
300
301	return((*reg_addr & (uint8_t)(1 << (intno % 8))) != 0);
302	}
303
304	/*
305	* ÝvCÌ®«ÌÝè
306	*/
307	void
308	x_config_int(INTNO intno, ATR intatr, PRI intpri)
309	{
310	volatile uint8_t *reg_addr;
311	uint8_t portno;
312
313	assert(VALID_INTNO_CFGINT(intno));
314	assert(TMIN_INTPRI <= intpri && intpri <= TMAX_INTPRI);
315
316	/*
317	* ÝÌ}XN
318	*
319	* Ýðó¯t¯½ÜÜCxgK^GbWgKÌÝèâC
320	* ÝDæxÌÝèðs¤ÌÍë¯È½ßCÝ®«É©©íç¸C
321	* êU}XN·éD
322	*/
323	(void) x_disable_int(intno);
324
325	/*
326	* DæxÌÝè
327	*/
328	// DæÊwètOEWX^ÌYrbgÉlðZbg
329	if(intno < 32) {
330	reg_addr = (volatile uint8_t *)TADR_PR00L;
331	reg_addr += (intno/8);
332	}
333	else {
334	reg_addr = (volatile uint8_t *)TADR_PR02L;
335	reg_addr += ((intno-32) / 8);
336	}
337	// DæÊxÌÝè(áÊrbg)
338	if((IPM2ILVL(intpri) & 0x01) != 0) {
339	*reg_addr \|= (uint8_t)(1 << (intno % 8));
340	}
341	else {
342	*reg_addr &= (uint8_t)~(1 << (intno % 8));
343	}
344	// DæÊxÌÝè(Êrbg)
345	if((IPM2ILVL(intpri) & 0x02) != 0) {
346	*(reg_addr+4) \|= (uint8_t)(1 << (intno % 8));
347	}
348	else {
349	*(reg_addr+4) &= (uint8_t)~(1 << (intno % 8));
350	}
351
352	/*
353	* gKÌÝè
354	*/
355	if(intno <= 7) {
356	reg_addr = (volatile uint8_t *)TADR_EGP0; // EGP0
357	portno = (uint8_t)(intno - 2);
358	}
359	else {
360	reg_addr = (volatile uint8_t *)TADR_EGP1; // EGP1
361	portno = (uint8_t)(intno - 29);
362	}
363
364	/* INT[qÌêÍÝmû@ðÝè·é */
365	if((intatr & TA_POSEDGE) != 0U)
366	{
367	// OÝ§¿ãªèGbWÂWX^ÌYrbgð1ÉZbg
368	*reg_addr \|= (uint8_t)(1 << (portno % 8));
369	// OÝ§¿ºªèGbWÂWX^ÌYrbgð0ÉZbg
370	*(reg_addr+1) &= (uint8_t)~(1 << (portno % 8));
371	}
372	else if((intatr & TA_NEGEDGE) != 0U)
373	{
374	// OÝ§¿ãªèGbWÂWX^ÌYrbgð0ÉZbg
375	*reg_addr &= (uint8_t)~(1 << (portno % 8));
376	// OÝ§¿ºªèGbWÂWX^ÌYrbgð1ÉZbg
377	*(reg_addr+1) \|= (uint8_t)(1 << (portno % 8));
378	}
379	else if((intatr & TA_BOTHEDGE) != 0U)
380	{
381	// OÝ§¿ãªèGbWÂWX^ÌYrbgð1ÉZbg
382	*reg_addr \|= (uint8_t)(1 << (portno % 8));
383	// OÝ§¿ºªèGbWÂWX^ÌYrbgð1ÉZbg
384	*(reg_addr+1) \|= (uint8_t)(1 << (portno % 8));
385	}
386	else { // Ç¿çÅàÈ¢êÍGbWoðÖ~
387	// OÝ§¿ãªèGbWÂWX^ÌYrbgð0ÉZbg
388	*reg_addr &= (uint8_t)~(1 << (portno % 8));
389	// OÝ§¿ºªèGbWÂWX^ÌYrbgð0ÉZbg
390	*(reg_addr+1) &= (uint8_t)~(1 << (portno % 8));
391	}
392
393	/*
394	* ÝÌ}XNð(DæxÝè)
395	*/
396	if ((intatr & TA_ENAINT) != 0U) {
397	(void) x_enable_int(intno);
398	}
399	}
400
401	/*
402	* NMIð·×ÄÌÝÌÖ~
403	*/
404	uint8_t
405	TOPPERS_disint(void)
406	{
407	volatile uint8_t TOPPERS_psw;
408
409	TOPPERS_psw = get_psw();
410	DI();
411	return(TOPPERS_psw);
412	}
413
414	/*
415	* ÝDæx}XNià\»jÌ»ÝlÌÝè
416	*/
417	void
418	TOPPERS_enaint(uint8_t TOPPERS_psw)
419	{
420	if(TOPPERS_psw & PSW_IE_MASK)
421	{
422	EI();
423	}
424	}
425
426

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