source: ssp_qb_r5f100le_cs/trunk/arch/arm_m_gcc/arm_m.h@ 93

Last change on this file since 93 was 93, checked in by nmir-saito, 8 years ago

add Combined package of SSP kernel for QB-R5F100LE-TB(RL78 processor)

File size: 4.7 KB
Line 
1/*
2 * TOPPERS/SSP Kernel
3 * Smallest Set Profile Kernel
4 *
5 * Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
6 * Graduate School of Information Science, Nagoya Univ., JAPAN
7 *
8 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì(1)`(4)‚ÌðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒF
9 * ƒAi–{ƒ\ƒtƒgƒEƒFƒA‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü
10 * •ÏEÄ”z•ziˆÈ‰ºC—˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
11 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
12 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
13 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
14 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
15 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
16ƒƒ“ƒgi—˜—p
17 * ŽÒƒ}ƒjƒ…
18ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
19 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
20 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
21 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
22 * ‚ƁD
23 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
24ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
25ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
26 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
27 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
28 * •ñ‚·‚邱‚ƁD
29 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
30 * ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
31 * ‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚̃†[ƒU‚Ü‚½‚̓Gƒ“ƒhƒ†[ƒU‚©‚ç‚Ì‚¢‚©‚Ȃ闝
32 * —R‚ÉŠî‚­¿‹‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð
33 * –Ɛӂ·‚邱‚ƁD
34 *
35 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
36 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC“Á’è‚ÌŽg—p–Ú“I
37 * ‚ɑ΂·‚é“K‡«‚àŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒF
38 * ƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»
39 * ‚̐ӔC‚𕉂í‚È‚¢D
40 *
41 * @(#) $Id: arm_m.h 1304 2008-08-27 07:28:36Z ertl-honda $
42 */
43
44/*
45 * ARMVx-M‚̃n[ƒhƒEƒFƒAŽ‘Œ¹‚Ì’è‹`
46 */
47
48#ifndef ARM_M_H
49#define ARM_M_H
50
51
52/*
53 * EPSR‚ÌTƒrƒbƒg
54 */
55#define EPSR_T 0x01000000
56
57/*
58 * IPSR‚Ì ISR NUMBER
59 */
60#define IPSR_ISR_NUMBER 0x1ff
61
62/*
63 * —áŠOEŠ„ž‚Ý”­¶Žž‚ɃXƒ^ƒbƒNã‚ɐς܂ê‚é•Û‘¶—̈æ‚̃TƒCƒY
64 * –{ƒJ[ƒlƒ‹‚Å‚Í—áŠOƒtƒŒ[ƒ€‚ƌĂÔ
65 */
66#define EXC_FRAME_SIZE (8*4)
67
68/*
69 * —áŠOEŠ„ž‚Ý”­¶Žž‚ÉLR‚ɐݒ肳‚ê‚éEXC_RETURN‚Ì’l
70 */
71#define EXC_RETURN_HANDLER 0x0
72#define EXC_RETURN_THREAD 0x8
73#define EXC_RETURN_MSP 0x0
74#define EXC_RETURN_PSP 0x4
75
76/*
77 * CONTROLƒŒƒWƒXƒ^
78 */
79#define CONTROL_PSP 0x02
80#define CONTROL_MSP 0x00
81
82/*
83 * —áŠO”ԍ†
84 */
85#define EXCNO_NMI 2
86#define EXCNO_HARD 3
87#define EXCNO_MPU 4
88#define EXCNO_BUS 5
89#define EXCNO_USAGE 6
90#define EXCNO_SVCALL 11
91#define EXCNO_DEBUG 12
92#define EXCNO_PENDSV 14
93
94/*
95 * —áŠO”ԍ†‚̍ŏ¬’l‚ƍőå’l
96 */
97#define TMIN_EXCNO 2
98#define TMAX_EXCNO 14
99
100/*
101 * Š„ž‚ݔԍ†
102 */
103#define IRQNO_SYSTICK 15
104
105/*
106 * Š„ž‚ݔԍ†‚̍ŏ¬’l
107 */
108#define TMIN_INTNO 15
109
110/*
111 * —áŠOƒtƒŒ[ƒ€‚̃IƒtƒZƒbƒg
112 */
113#define P_EXCINF_OFFSET_EXC_RETURN 0x00
114#define P_EXCINF_OFFSET_BASEPRI 0x01
115#define P_EXCINF_OFFSET_XPSR 0x09
116#define P_EXCINF_OFFSET_PC 0x08
117
118/*
119 * NVICŠÖ˜A
120 */
121
122/*
123 * ƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^
124 */
125#define NVIC_INT_CTRL 0xe000ed04
126
127#define NVIC_PENDSVSET 0x10000000
128
129/*
130 * ƒVƒXƒeƒ€ƒnƒ“ƒhƒ‰[ƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^
131 */
132#define NVIC_SYS_HND_CTRL 0xE000ED24
133
134/*
135 * Še—áŠO‚Ì‹–‰Âƒrƒbƒg
136 */
137#define NVIC_SYS_HND_CTRL_USAGE 0x00040000
138#define NVIC_SYS_HND_CTRL_BUS 0x00020000
139#define NVIC_SYS_HND_CTRL_MEM 0x00010000
140
141/*
142 * —Dæ“xÝ’背ƒWƒXƒ^
143 */
144#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
145#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
146#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
147#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
148
149/*
150 * Š„ž‚Ý‹–‰ÂƒŒƒWƒXƒ^
151 */
152#define NVIC_SETENA0 0xE000E100 // IRQ 0 to 31 Set Enable Register
153
154/*
155 * Š„ž‚Ý‹ÖŽ~ƒŒƒWƒXƒ^
156 */
157#define NVIC_CLRENA0 0xE000E180 // IRQ 0 to 31 Set Disable Register
158
159/*
160 * ƒxƒNƒ^ƒe[ƒuƒ‹ƒIƒtƒZƒbƒgƒŒƒWƒXƒ^
161 */
162#define NVIC_VECTTBL 0xE000ED08
163
164
165/*
166 * SYSTICŠÖ˜AƒŒƒWƒXƒ^
167 */
168#define SYSTIC_CONTROL_STATUS 0xE000E010
169#define SYSTIC_RELOAD_VALUE 0xE000E014
170#define SYSTIC_CURRENT_VALUE 0xE000E018
171#define SYSTIC_CALIBRATION 0xE000E01C
172
173#define SYSTIC_ENABLE 0x01
174#define SYSTIC_TICINT 0x02
175#define SYSTIC_CLKSOURCE 0x04
176#define SYSTIC_COUNTFLAG 0x10000
177
178#define SYSTIC_SKEW 0x40000000
179#define SYSTIC_NOREF 0x80000000
180#define SYSTIC_TENMS 0x00ffffff
181
182#endif /* ARM_M_H */
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