| 1 | /*
|
|---|
| 2 | * TOPPERS/SSP Kernel
|
|---|
| 3 | * Smallest Set Profile Kernel
|
|---|
| 4 | *
|
|---|
| 5 | * Copyright (C) 2013,2014 by Naoki Saito
|
|---|
| 6 | * Nagoya Municipal Industrial Research Institute, JAPAN
|
|---|
| 7 | *
|
|---|
| 8 | * 上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
|
|---|
| 9 | * ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
|
|---|
| 10 | * 変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
|
|---|
| 11 | * (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
|
|---|
| 12 | * 権表示，この利用条件および下記の無保証規定が，そのままの形でソー
|
|---|
| 13 | * スコード中に含まれていること．
|
|---|
| 14 | * (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
|
|---|
| 15 | * 用できる形で再配布する場合には，再配布に伴うドキュメント（利用
|
|---|
| 16 | * 者マニュアルなど）に，上記の著作権表示，この利用条件および下記
|
|---|
| 17 | * の無保証規定を掲載すること．
|
|---|
| 18 | * (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
|
|---|
| 19 | * 用できない形で再配布する場合には，次のいずれかの条件を満たすこ
|
|---|
| 20 | * と．
|
|---|
| 21 | * (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
|
|---|
| 22 | * 作権表示，この利用条件および下記の無保証規定を掲載すること．
|
|---|
| 23 | * (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
|
|---|
| 24 | * 報告すること．
|
|---|
| 25 | * (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
|
|---|
| 26 | * 害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
|
|---|
| 27 | * また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
|
|---|
| 28 | * 由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
|
|---|
| 29 | * 免責すること．
|
|---|
| 30 | *
|
|---|
| 31 | * 本ソフトウェアは，無保証で提供されているものである．上記著作権者お
|
|---|
| 32 | * よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
|
|---|
| 33 | * に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
|
|---|
| 34 | * アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
|
|---|
| 35 | * の責任を負わない．
|
|---|
| 36 | *
|
|---|
| 37 | */
|
|---|
| 38 |
|
|---|
| 39 | #ifndef TOPPERS_LPC812M101FDH20_H
|
|---|
| 40 | #define TOPPERS_LPC812M101FDH20_H
|
|---|
| 41 |
|
|---|
| 42 | /*
|
|---|
| 43 | * CORTEX-M CPUの依存部のインクルード
|
|---|
| 44 | */
|
|---|
| 45 | #include "armv6_m_gcc/arm_m.h"
|
|---|
| 46 |
|
|---|
| 47 | /*
|
|---|
| 48 | * プロセッサのエンディアン定義
|
|---|
| 49 | * LPC812 はリトルエンディアン
|
|---|
| 50 | */
|
|---|
| 51 | #define SIL_ENDIAN_LITTLE
|
|---|
| 52 |
|
|---|
| 53 | /*
|
|---|
| 54 | * 割込み番号の最大値
|
|---|
| 55 | */
|
|---|
| 56 | #define TMAX_INTNO (47)
|
|---|
| 57 |
|
|---|
| 58 | /*
|
|---|
| 59 | * 割込み優先度のビット幅
|
|---|
| 60 | */
|
|---|
| 61 | #define TBITW_IPRI (2)
|
|---|
| 62 |
|
|---|
| 63 | /*
|
|---|
| 64 | * 割込みベクタ番号定義
|
|---|
| 65 | */
|
|---|
| 66 | #define INT_SPI0 (16)
|
|---|
| 67 | #define INT_SPI1 (17)
|
|---|
| 68 |
|
|---|
| 69 | #define INT_UART0 (19)
|
|---|
| 70 | #define INT_UART1 (20)
|
|---|
| 71 | #define INT_UART2 (21)
|
|---|
| 72 |
|
|---|
| 73 | #define INT_I2C0 (24)
|
|---|
| 74 | #define INT_SCT (25)
|
|---|
| 75 | #define INT_MRT (26)
|
|---|
| 76 | #define INT_CMP (27)
|
|---|
| 77 | #define INT_WDT (28)
|
|---|
| 78 | #define INT_BOD (29)
|
|---|
| 79 |
|
|---|
| 80 | #define INT_WKT (31)
|
|---|
| 81 |
|
|---|
| 82 | #define INT_PININT0 (40)
|
|---|
| 83 | #define INT_PININT1 (41)
|
|---|
| 84 | #define INT_PININT2 (42)
|
|---|
| 85 | #define INT_PININT3 (43)
|
|---|
| 86 | #define INT_PININT4 (44)
|
|---|
| 87 | #define INT_PININT5 (45)
|
|---|
| 88 | #define INT_PININT6 (46)
|
|---|
| 89 | #define INT_PININT7 (47)
|
|---|
| 90 |
|
|---|
| 91 |
|
|---|
| 92 | /*
|
|---|
| 93 | * 割込み優先度ビット幅中のサブ優先度のビット幅
|
|---|
| 94 | */
|
|---|
| 95 | #define TBITW_SUBIPRI 0
|
|---|
| 96 |
|
|---|
| 97 |
|
|---|
| 98 | /*
|
|---|
| 99 | * LPC812のレジスタ定義
|
|---|
| 100 | */
|
|---|
| 101 | /* SYSCON */
|
|---|
| 102 | #define TADR_SYSCON_BASE (0x40048000)
|
|---|
| 103 |
|
|---|
| 104 | #define TOFFSET_SYSCON_SYSMEMREMAP (0x000)
|
|---|
| 105 | #define TOFFSET_SYSCON_PRESETCTRL (0x004)
|
|---|
| 106 | #define TOFFSET_SYSCON_SYSPLLCTRL (0x008)
|
|---|
| 107 | #define TOFFSET_SYSCON_SYSPLLSTAT (0x00C)
|
|---|
| 108 | #define TOFFSET_SYSCON_SYSOSCCTRL (0x020)
|
|---|
| 109 | #define TOFFSET_SYSCON_WDTOSCCTRL (0x024)
|
|---|
| 110 | #define TOFFSET_SYSCON_SYSRSTSTAT (0x030)
|
|---|
| 111 | #define TOFFSET_SYSCON_SYSPLLCLKSEL (0x040)
|
|---|
| 112 | #define TOFFSET_SYSCON_SYSPLLCLKUEN (0x044)
|
|---|
| 113 | #define TOFFSET_SYSCON_MAINCLKSEL (0x070)
|
|---|
| 114 | #define TOFFSET_SYSCON_MAINCLKUEN (0x074)
|
|---|
| 115 | #define TOFFSET_SYSCON_SYSAHBCLKDIV (0x078)
|
|---|
| 116 | #define TOFFSET_SYSCON_SYSAHBCLKCTRL (0x080)
|
|---|
| 117 | #define TOFFSET_SYSCON_UARTCLKDIV (0x094)
|
|---|
| 118 | #define TOFFSET_SYSCON_CLKOUTSEL (0x0E0)
|
|---|
| 119 | #define TOFFSET_SYSCON_CLKOUTUEN (0x0E4)
|
|---|
| 120 | #define TOFFSET_SYSCON_CLKOUTDIV (0x0E8)
|
|---|
| 121 | #define TOFFSET_SYSCON_UARTFRGDIV (0x0F0)
|
|---|
| 122 | #define TOFFSET_SYSCON_UARTFRGMULT (0x0F4)
|
|---|
| 123 | #define TOFFSET_SYSCON_EXTTRACECMD (0x0FC)
|
|---|
| 124 | #define TOFFSET_SYSCON_PIOPORCAP0 (0x100)
|
|---|
| 125 | #define TOFFSET_SYSCON_IOCONCLKDIV6 (0x134)
|
|---|
| 126 | #define TOFFSET_SYSCON_IOCONCLKDIV5 (0x138)
|
|---|
| 127 | #define TOFFSET_SYSCON_IOCONCLKDIV4 (0x13C)
|
|---|
| 128 | #define TOFFSET_SYSCON_IOCONCLKDIV3 (0x140)
|
|---|
| 129 | #define TOFFSET_SYSCON_IOCONCLKDIV2 (0x144)
|
|---|
| 130 | #define TOFFSET_SYSCON_IOCONCLKDIV1 (0x148)
|
|---|
| 131 | #define TOFFSET_SYSCON_IOCONCLKDIV0 (0x14C)
|
|---|
| 132 | #define TOFFSET_SYSCON_BODCTRL (0x150)
|
|---|
| 133 | #define TOFFSET_SYSCON_SYSTCKCAL (0x154)
|
|---|
| 134 | #define TOFFSET_SYSCON_IRQLATENCY (0x170)
|
|---|
| 135 | #define TOFFSET_SYSCON_NMISRC (0x174)
|
|---|
| 136 | #define TOFFSET_SYSCON_PINTSEL0 (0x178)
|
|---|
| 137 | #define TOFFSET_SYSCON_PINTSEL1 (0x17C)
|
|---|
| 138 | #define TOFFSET_SYSCON_PINTSEL2 (0x180)
|
|---|
| 139 | #define TOFFSET_SYSCON_PINTSEL3 (0x184)
|
|---|
| 140 | #define TOFFSET_SYSCON_PINTSEL4 (0x188)
|
|---|
| 141 | #define TOFFSET_SYSCON_PINTSEL5 (0x18C)
|
|---|
| 142 | #define TOFFSET_SYSCON_PINTSEL6 (0x190)
|
|---|
| 143 | #define TOFFSET_SYSCON_PINTSEL7 (0x194)
|
|---|
| 144 | #define TOFFSET_SYSCON_STARTERP0 (0x204)
|
|---|
| 145 | #define TOFFSET_SYSCON_STARTERP1 (0x214)
|
|---|
| 146 | #define TOFFSET_SYSCON_PDSLEEPCFG (0x230)
|
|---|
| 147 | #define TOFFSET_SYSCON_PDAWAKECFG (0x234)
|
|---|
| 148 | #define TOFFSET_SYSCON_PDRUNCFG (0x238)
|
|---|
| 149 | #define TOFFSET_SYSCON_DEVICE_ID (0x3F8)
|
|---|
| 150 |
|
|---|
| 151 | #define TADR_SYSCON_SYSMEMREMAP (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSMEMREMAP )
|
|---|
| 152 | #define TADR_SYSCON_PRESETCTRL (TADR_SYSCON_BASE + TOFFSET_SYSCON_PRESETCTRL )
|
|---|
| 153 | #define TADR_SYSCON_SYSPLLCTRL (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSPLLCTRL )
|
|---|
| 154 | #define TADR_SYSCON_SYSPLLSTAT (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSPLLSTAT )
|
|---|
| 155 | #define TADR_SYSCON_SYSOSCCTRL (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSOSCCTRL )
|
|---|
| 156 | #define TADR_SYSCON_WDTOSCCTRL (TADR_SYSCON_BASE + TOFFSET_SYSCON_WDTOSCCTRL )
|
|---|
| 157 | #define TADR_SYSCON_SYSRSTSTAT (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSRSTSTAT )
|
|---|
| 158 | #define TADR_SYSCON_SYSPLLCLKSEL (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSPLLCLKSEL)
|
|---|
| 159 | #define TADR_SYSCON_SYSPLLCLKUEN (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSPLLCLKUEN)
|
|---|
| 160 | #define TADR_SYSCON_MAINCLKSEL (TADR_SYSCON_BASE + TOFFSET_SYSCON_MAINCLKSEL )
|
|---|
| 161 | #define TADR_SYSCON_MAINCLKUEN (TADR_SYSCON_BASE + TOFFSET_SYSCON_MAINCLKUEN )
|
|---|
| 162 | #define TADR_SYSCON_SYSAHBCLKDIV (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSAHBCLKDIV)
|
|---|
| 163 | #define TADR_SYSCON_SYSAHBCLKCTRL (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSAHBCLKCTRL)
|
|---|
| 164 | #define TADR_SYSCON_UARTCLKDIV (TADR_SYSCON_BASE + TOFFSET_SYSCON_UARTCLKDIV )
|
|---|
| 165 | #define TADR_SYSCON_CLKOUTSEL (TADR_SYSCON_BASE + TOFFSET_SYSCON_CLKOUTSEL )
|
|---|
| 166 | #define TADR_SYSCON_CLKOUTUEN (TADR_SYSCON_BASE + TOFFSET_SYSCON_CLKOUTUEN )
|
|---|
| 167 | #define TADR_SYSCON_CLKOUTDIV (TADR_SYSCON_BASE + TOFFSET_SYSCON_CLKOUTDIV )
|
|---|
| 168 | #define TADR_SYSCON_UARTFRGDIV (TADR_SYSCON_BASE + TOFFSET_SYSCON_UARTFRGDIV )
|
|---|
| 169 | #define TADR_SYSCON_UARTFRGMULT (TADR_SYSCON_BASE + TOFFSET_SYSCON_UARTFRGMULT )
|
|---|
| 170 | #define TADR_SYSCON_EXTTRACECMD (TADR_SYSCON_BASE + TOFFSET_SYSCON_EXTTRACECMD )
|
|---|
| 171 | #define TADR_SYSCON_PIOPORCAP0 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PIOPORCAP0 )
|
|---|
| 172 | #define TADR_SYSCON_IOCONCLKDIV6 (TADR_SYSCON_BASE + TOFFSET_SYSCON_IOCONCLKDIV6)
|
|---|
| 173 | #define TADR_SYSCON_IOCONCLKDIV5 (TADR_SYSCON_BASE + TOFFSET_SYSCON_IOCONCLKDIV5)
|
|---|
| 174 | #define TADR_SYSCON_IOCONCLKDIV4 (TADR_SYSCON_BASE + TOFFSET_SYSCON_IOCONCLKDIV4)
|
|---|
| 175 | #define TADR_SYSCON_IOCONCLKDIV3 (TADR_SYSCON_BASE + TOFFSET_SYSCON_IOCONCLKDIV3)
|
|---|
| 176 | #define TADR_SYSCON_IOCONCLKDIV2 (TADR_SYSCON_BASE + TOFFSET_SYSCON_IOCONCLKDIV2)
|
|---|
| 177 | #define TADR_SYSCON_IOCONCLKDIV1 (TADR_SYSCON_BASE + TOFFSET_SYSCON_IOCONCLKDIV1)
|
|---|
| 178 | #define TADR_SYSCON_IOCONCLKDIV0 (TADR_SYSCON_BASE + TOFFSET_SYSCON_IOCONCLKDIV0)
|
|---|
| 179 | #define TADR_SYSCON_BODCTRL (TADR_SYSCON_BASE + TOFFSET_SYSCON_BODCTRL )
|
|---|
| 180 | #define TADR_SYSCON_SYSTCKCAL (TADR_SYSCON_BASE + TOFFSET_SYSCON_SYSTCKCAL )
|
|---|
| 181 | #define TADR_SYSCON_IRQLATENCY (TADR_SYSCON_BASE + TOFFSET_SYSCON_IRQLATENCY )
|
|---|
| 182 | #define TADR_SYSCON_NMISRC (TADR_SYSCON_BASE + TOFFSET_SYSCON_NMISRC )
|
|---|
| 183 | #define TADR_SYSCON_PINTSEL0 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL0 )
|
|---|
| 184 | #define TADR_SYSCON_PINTSEL1 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL1 )
|
|---|
| 185 | #define TADR_SYSCON_PINTSEL2 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL2 )
|
|---|
| 186 | #define TADR_SYSCON_PINTSEL3 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL3 )
|
|---|
| 187 | #define TADR_SYSCON_PINTSEL4 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL4 )
|
|---|
| 188 | #define TADR_SYSCON_PINTSEL5 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL5 )
|
|---|
| 189 | #define TADR_SYSCON_PINTSEL6 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL6 )
|
|---|
| 190 | #define TADR_SYSCON_PINTSEL7 (TADR_SYSCON_BASE + TOFFSET_SYSCON_PINTSEL7 )
|
|---|
| 191 | #define TADR_SYSCON_STARTERP0 (TADR_SYSCON_BASE + TOFFSET_SYSCON_STARTERP0 )
|
|---|
| 192 | #define TADR_SYSCON_STARTERP1 (TADR_SYSCON_BASE + TOFFSET_SYSCON_STARTERP1 )
|
|---|
| 193 | #define TADR_SYSCON_PDSLEEPCFG (TADR_SYSCON_BASE + TOFFSET_SYSCON_PDSLEEPCFG )
|
|---|
| 194 | #define TADR_SYSCON_PDAWAKECFG (TADR_SYSCON_BASE + TOFFSET_SYSCON_PDAWAKECFG )
|
|---|
| 195 | #define TADR_SYSCON_PDRUNCFG (TADR_SYSCON_BASE + TOFFSET_SYSCON_PDRUNCFG )
|
|---|
| 196 | #define TADR_SYSCON_DEVICE_ID (TADR_SYSCON_BASE + TOFFSET_SYSCON_DEVICE_ID )
|
|---|
| 197 |
|
|---|
| 198 |
|
|---|
| 199 | // PRESETCTRL
|
|---|
| 200 | #define TBITPTN_SYSCON_PRESETCTRL_SPI0_RST_N (1 << 0)
|
|---|
| 201 | #define TBITPTN_SYSCON_PRESETCTRL_SPI1_RST_N (1 << 1)
|
|---|
| 202 | #define TBITPTN_SYSCON_PRESETCTRL_UARTFRG_RST_N (1 << 2)
|
|---|
| 203 | #define TBITPTN_SYSCON_PRESETCTRL_USART0_RST_N (1 << 3)
|
|---|
| 204 | #define TBITPTN_SYSCON_PRESETCTRL_UART1_RST_N (1 << 4)
|
|---|
| 205 | #define TBITPTN_SYSCON_PRESETCTRL_UART2_RST_N (1 << 5)
|
|---|
| 206 | #define TBITPTN_SYSCON_PRESETCTRL_I2C_RST_N (1 << 6)
|
|---|
| 207 | #define TBITPTN_SYSCON_PRESETCTRL_MRT_RST_N (1 << 7)
|
|---|
| 208 | #define TBITPTN_SYSCON_PRESETCTRL_SCT_RST_N (1 << 8)
|
|---|
| 209 | #define TBITPTN_SYSCON_PRESETCTRL_WKT_RST_N (1 << 9)
|
|---|
| 210 | #define TBITPTN_SYSCON_PRESETCTRL_GPIO_RST_N (1 << 10)
|
|---|
| 211 | #define TBITPTN_SYSCON_PRESETCTRL_FLASH_RST_N (1 << 11)
|
|---|
| 212 | #define TBITPTN_SYSCON_PRESETCTRL_ACMP_RST_N (1 << 12)
|
|---|
| 213 |
|
|---|
| 214 | // SYSPLLCTRL
|
|---|
| 215 | #define TBITPTN_SYSCON_SYSPLLCTRL_MSEL (0x1F)
|
|---|
| 216 | #define TBITPTN_SYSCON_SYSPLLCTRL_PSEL (0x11 << 5)
|
|---|
| 217 | #define TBITPTN_SYSCON_SYSPLLCTRL_PSEL_P1 (0x00 << 5)
|
|---|
| 218 | #define TBITPTN_SYSCON_SYSPLLCTRL_PSEL_P2 (0x01 << 5)
|
|---|
| 219 | #define TBITPTN_SYSCON_SYSPLLCTRL_PSEL_P4 (0x02 << 5)
|
|---|
| 220 | #define TBITPTN_SYSCON_SYSPLLCTRL_PSEL_P8 (0x03 << 5)
|
|---|
| 221 |
|
|---|
| 222 | // SYSPLLSTAT
|
|---|
| 223 | #define TBITPTN_SYSCON_SYSPLLSTAT_LOCK (1 << 0)
|
|---|
| 224 |
|
|---|
| 225 | // SYSOSCCTRL
|
|---|
| 226 | #define TBITPTN_SYSCON_SYSOSCCTRL_BYPASS (1 << 0)
|
|---|
| 227 | #define TBITPTN_SYSCON_SYSOSCCTRL_FREQRANGE (1 << 1)
|
|---|
| 228 |
|
|---|
| 229 | // SYSPLLCLKSEL
|
|---|
| 230 | #define TBITPTN_SYSCON_SYSPLLCLKSEL_SEL (3 << 0)
|
|---|
| 231 | #define TBITPTN_SYSCON_SYSPLLCLKSEL_SEL_IRC (0 << 0)
|
|---|
| 232 | #define TBITPTN_SYSCON_SYSPLLCLKSEL_SEL_SYSOSC (1 << 0)
|
|---|
| 233 | #define TBITPTN_SYSCON_SYSPLLCLKSEL_SEL_CLKIN (3 << 0)
|
|---|
| 234 |
|
|---|
| 235 | // SYSPLLCLKUEN
|
|---|
| 236 | #define TBITPTN_SYSCON_SYSPLLCLKUEN_ENA (1 << 0)
|
|---|
| 237 |
|
|---|
| 238 | // MAINCLKSEL
|
|---|
| 239 | #define TBITPTN_SYSCON_MAINCLKSEL_SEL (0x11 << 0)
|
|---|
| 240 | #define TBITPTN_SYSCON_MAINCLKSEL_SEL_IRC (0x00 << 0)
|
|---|
| 241 | #define TBITPTN_SYSCON_MAINCLKSEL_SEL_PLLIN (0x01 << 0)
|
|---|
| 242 | #define TBITPTN_SYSCON_MAINCLKSEL_SEL_WDTOSC (0x02 << 0)
|
|---|
| 243 | #define TBITPTN_SYSCON_MAINCLKSEL_SEL_PLLOUT (0x03 << 0)
|
|---|
| 244 |
|
|---|
| 245 | // MAINCLKUEN
|
|---|
| 246 | #define TBITPTN_SYSCON_MAINCLKUEN_ENA (1 << 0)
|
|---|
| 247 |
|
|---|
| 248 | // SYSAHBCLKDIV
|
|---|
| 249 | #define TBITPTN_SYSCON_SYSAHBCLKDIV_DIV (0xff << 0)
|
|---|
| 250 |
|
|---|
| 251 | // SYSAHBCLKCTRL
|
|---|
| 252 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_SYS (1 << 0)
|
|---|
| 253 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_ROM (1 << 1)
|
|---|
| 254 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_RAM (1 << 2)
|
|---|
| 255 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_FLASHREG (1 << 3)
|
|---|
| 256 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_FLASH (1 << 4)
|
|---|
| 257 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_I2C (1 << 5)
|
|---|
| 258 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_GPIO (1 << 6)
|
|---|
| 259 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_SWM (1 << 7)
|
|---|
| 260 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_SCT (1 << 8)
|
|---|
| 261 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_WKT (1 << 9)
|
|---|
| 262 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_MRT (1 << 10)
|
|---|
| 263 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_SPI0 (1 << 11)
|
|---|
| 264 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_SPI1 (1 << 12)
|
|---|
| 265 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_CRC (1 << 13)
|
|---|
| 266 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_UART0 (1 << 14)
|
|---|
| 267 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_UART1 (1 << 15)
|
|---|
| 268 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_UART2 (1 << 16)
|
|---|
| 269 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_WWDT (1 << 17)
|
|---|
| 270 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_IOCON (1 << 18)
|
|---|
| 271 | #define TBITPTN_SYSCON_SYSAHBCLKCTRL_ACMP (1 << 19)
|
|---|
| 272 |
|
|---|
| 273 | // PDRUNCFG
|
|---|
| 274 | #define TBITPTN_SYSCON_PDRUNCFG_IRCOUTPD (1 << 0)
|
|---|
| 275 | #define TBITPTN_SYSCON_PDRUNCFG_IRCPD (1 << 1)
|
|---|
| 276 | #define TBITPTN_SYSCON_PDRUNCFG_FLASHPD (1 << 2)
|
|---|
| 277 | #define TBITPTN_SYSCON_PDRUNCFG_BODPD (1 << 3)
|
|---|
| 278 | #define TBITPTN_SYSCON_PDRUNCFG_SYSOSCPD (1 << 5)
|
|---|
| 279 | #define TBITPTN_SYSCON_PDRUNCFG_WDTOSCPD (1 << 6)
|
|---|
| 280 | #define TBITPTN_SYSCON_PDRUNCFG_SYSPLLPD (1 << 7)
|
|---|
| 281 | #define TBITPTN_SYSCON_PDRUNCFG_ACMP (1 << 15)
|
|---|
| 282 |
|
|---|
| 283 |
|
|---|
| 284 |
|
|---|
| 285 | /* IOCON */
|
|---|
| 286 | #define TADR_IOCON_BASE (0x40044000)
|
|---|
| 287 |
|
|---|
| 288 | #define TOFFSET_IOCON_PIO0_17 (0x00)
|
|---|
| 289 | #define TOFFSET_IOCON_PIO0_13 (0x04)
|
|---|
| 290 | #define TOFFSET_IOCON_PIO0_12 (0x08)
|
|---|
| 291 | #define TOFFSET_IOCON_PIO0_5 (0x0C)
|
|---|
| 292 | #define TOFFSET_IOCON_PIO0_4 (0x10)
|
|---|
| 293 | #define TOFFSET_IOCON_PIO0_3 (0x14)
|
|---|
| 294 | #define TOFFSET_IOCON_PIO0_2 (0x18)
|
|---|
| 295 | #define TOFFSET_IOCON_PIO0_11 (0x1C)
|
|---|
| 296 | #define TOFFSET_IOCON_PIO0_10 (0x20)
|
|---|
| 297 | #define TOFFSET_IOCON_PIO0_16 (0x24)
|
|---|
| 298 | #define TOFFSET_IOCON_PIO0_15 (0x28)
|
|---|
| 299 | #define TOFFSET_IOCON_PIO0_1 (0x2C)
|
|---|
| 300 | #define TOFFSET_IOCON_PIO0_9 (0x34)
|
|---|
| 301 | #define TOFFSET_IOCON_PIO0_8 (0x38)
|
|---|
| 302 | #define TOFFSET_IOCON_PIO0_7 (0x3C)
|
|---|
| 303 | #define TOFFSET_IOCON_PIO0_6 (0x40)
|
|---|
| 304 | #define TOFFSET_IOCON_PIO0_0 (0x44)
|
|---|
| 305 | #define TOFFSET_IOCON_PIO0_14 (0x48)
|
|---|
| 306 |
|
|---|
| 307 | #define TADR_IOCON_PIO0_17 (TADR_IOCON_BASE + TOFFSET_PIO0_17)
|
|---|
| 308 | #define TADR_IOCON_PIO0_13 (TADR_IOCON_BASE + TOFFSET_PIO0_13)
|
|---|
| 309 | #define TADR_IOCON_PIO0_12 (TADR_IOCON_BASE + TOFFSET_PIO0_12)
|
|---|
| 310 | #define TADR_IOCON_PIO0_5 (TADR_IOCON_BASE + TOFFSET_PIO0_5 )
|
|---|
| 311 | #define TADR_IOCON_PIO0_4 (TADR_IOCON_BASE + TOFFSET_PIO0_4 )
|
|---|
| 312 | #define TADR_IOCON_PIO0_3 (TADR_IOCON_BASE + TOFFSET_PIO0_3 )
|
|---|
| 313 | #define TADR_IOCON_PIO0_2 (TADR_IOCON_BASE + TOFFSET_PIO0_2 )
|
|---|
| 314 | #define TADR_IOCON_PIO0_11 (TADR_IOCON_BASE + TOFFSET_PIO0_11)
|
|---|
| 315 | #define TADR_IOCON_PIO0_10 (TADR_IOCON_BASE + TOFFSET_PIO0_10)
|
|---|
| 316 | #define TADR_IOCON_PIO0_16 (TADR_IOCON_BASE + TOFFSET_PIO0_16)
|
|---|
| 317 | #define TADR_IOCON_PIO0_15 (TADR_IOCON_BASE + TOFFSET_PIO0_15)
|
|---|
| 318 | #define TADR_IOCON_PIO0_1 (TADR_IOCON_BASE + TOFFSET_PIO0_1 )
|
|---|
| 319 | #define TADR_IOCON_PIO0_9 (TADR_IOCON_BASE + TOFFSET_PIO0_9 )
|
|---|
| 320 | #define TADR_IOCON_PIO0_8 (TADR_IOCON_BASE + TOFFSET_PIO0_8 )
|
|---|
| 321 | #define TADR_IOCON_PIO0_7 (TADR_IOCON_BASE + TOFFSET_PIO0_7 )
|
|---|
| 322 | #define TADR_IOCON_PIO0_6 (TADR_IOCON_BASE + TOFFSET_PIO0_6 )
|
|---|
| 323 | #define TADR_IOCON_PIO0_0 (TADR_IOCON_BASE + TOFFSET_PIO0_0 )
|
|---|
| 324 | #define TADR_IOCON_PIO0_14 (TADR_IOCON_BASE + TOFFSET_PIO0_14)
|
|---|
| 325 |
|
|---|
| 326 |
|
|---|
| 327 | // ビット定義
|
|---|
| 328 | #define TBITPTN_IOCON_PIOx_MODE (3 << 3)
|
|---|
| 329 | #define TBITPTN_IOCON_PIOx_MODE_INACTIVE (0 << 3)
|
|---|
| 330 | #define TBITPTN_IOCON_PIOx_MODE_PULLDOWN (1 << 3)
|
|---|
| 331 | #define TBITPTN_IOCON_PIOx_MODE_PULLUP (2 << 3)
|
|---|
| 332 | #define TBITPTN_IOCON_PIOx_MODE_REPEATER (3 << 3)
|
|---|
| 333 |
|
|---|
| 334 | #define TBITPTN_IOCON_PIOx_HYS (1 << 5)
|
|---|
| 335 | #define TBITPTN_IOCON_PIOx_INV (1 << 6)
|
|---|
| 336 | #define TBITPTN_IOCON_PIOx_OD (1 << 10)
|
|---|
| 337 |
|
|---|
| 338 | #define TBITPTN_IOCON_PIOx_SMODE (3 << 11)
|
|---|
| 339 | #define TBITPTN_IOCON_PIOx_SMODE_BYPASS (0 << 11)
|
|---|
| 340 | #define TBITPTN_IOCON_PIOx_SMODE_1CLK (1 << 11)
|
|---|
| 341 | #define TBITPTN_IOCON_PIOx_SMODE_2CLK (2 << 11)
|
|---|
| 342 | #define TBITPTN_IOCON_PIOx_SMODE_3CLK (3 << 11)
|
|---|
| 343 |
|
|---|
| 344 | #define TBITPTN_IOCON_PIOx_CLKDIV (7 << 13)
|
|---|
| 345 | #define TBITPTN_IOCON_PIOx_CLKDIV_CLKDIV0 (0 << 13)
|
|---|
| 346 | #define TBITPTN_IOCON_PIOx_CLKDIV_CLKDIV1 (1 << 13)
|
|---|
| 347 | #define TBITPTN_IOCON_PIOx_CLKDIV_CLKDIV2 (2 << 13)
|
|---|
| 348 | #define TBITPTN_IOCON_PIOx_CLKDIV_CLKDIV3 (3 << 13)
|
|---|
| 349 | #define TBITPTN_IOCON_PIOx_CLKDIV_CLKDIV4 (4 << 13)
|
|---|
| 350 | #define TBITPTN_IOCON_PIOx_CLKDIV_CLKDIV5 (5 << 13)
|
|---|
| 351 | #define TBITPTN_IOCON_PIOx_CLKDIV_CLKDIV6 (6 << 13)
|
|---|
| 352 |
|
|---|
| 353 |
|
|---|
| 354 | /* SWM */
|
|---|
| 355 | #define TADR_SWM_BASE 0x4000C000
|
|---|
| 356 |
|
|---|
| 357 | #define TOFFSET_SWM_PINASSIGN0 (0x000)
|
|---|
| 358 | #define TOFFSET_SWM_PINASSIGN1 (0x004)
|
|---|
| 359 | #define TOFFSET_SWM_PINASSIGN2 (0x008)
|
|---|
| 360 | #define TOFFSET_SWM_PINASSIGN3 (0x00C)
|
|---|
| 361 | #define TOFFSET_SWM_PINASSIGN4 (0x010)
|
|---|
| 362 | #define TOFFSET_SWM_PINASSIGN5 (0x014)
|
|---|
| 363 | #define TOFFSET_SWM_PINASSIGN6 (0x018)
|
|---|
| 364 | #define TOFFSET_SWM_PINASSIGN7 (0x01C)
|
|---|
| 365 | #define TOFFSET_SWM_PINASSIGN8 (0x020)
|
|---|
| 366 | #define TOFFSET_SWM_PINENABLE0 (0x1C0)
|
|---|
| 367 |
|
|---|
| 368 | #define TADR_SWM_PINASSIGN0 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN0)
|
|---|
| 369 | #define TADR_SWM_PINASSIGN1 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN1)
|
|---|
| 370 | #define TADR_SWM_PINASSIGN2 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN2)
|
|---|
| 371 | #define TADR_SWM_PINASSIGN3 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN3)
|
|---|
| 372 | #define TADR_SWM_PINASSIGN4 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN4)
|
|---|
| 373 | #define TADR_SWM_PINASSIGN5 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN5)
|
|---|
| 374 | #define TADR_SWM_PINASSIGN6 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN6)
|
|---|
| 375 | #define TADR_SWM_PINASSIGN7 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN7)
|
|---|
| 376 | #define TADR_SWM_PINASSIGN8 (TADR_SWM_BASE + TOFFSET_SWM_PINASSIGN8)
|
|---|
| 377 | #define TADR_SWM_PINENABLE0 (TADR_SWM_BASE + TOFFSET_SWM_PINENABLE0)
|
|---|
| 378 |
|
|---|
| 379 | #define TBITPTN_SWM_PINENABLE0_ACMPI1EN (1 << 0)
|
|---|
| 380 | #define TBITPTN_SWM_PINENABLE0_ACMPI2EN (1 << 0)
|
|---|
| 381 | #define TBITPTN_SWM_PINENABLE0_SWCLKEN (1 << 2)
|
|---|
| 382 | #define TBITPTN_SWM_PINENABLE0_SWDIOEN (1 << 3)
|
|---|
| 383 | #define TBITPTN_SWM_PINENABLE0_XTALINEN (1 << 4)
|
|---|
| 384 | #define TBITPTN_SWM_PINENABLE0_XTALOUTEN (1 << 5)
|
|---|
| 385 | #define TBITPTN_SWM_PINENABLE0_RESETEN (1 << 6)
|
|---|
| 386 | #define TBITPTN_SWM_PINENABLE0_CLKIN (1 << 7)
|
|---|
| 387 | #define TBITPTN_SWM_PINENABLE0_VDDCMP (1 << 8)
|
|---|
| 388 |
|
|---|
| 389 |
|
|---|
| 390 | /* USART */
|
|---|
| 391 | #define TADR_USART_BASE(index) (0x40064000 + (0x4000) * index)
|
|---|
| 392 | #define TADR_USART0_BASE TADR_USART_BASE(0)
|
|---|
| 393 | #define TADR_USART1_BASE TADR_USART_BASE(1)
|
|---|
| 394 | #define TADR_USART2_BASE TADR_USART_BASE(2)
|
|---|
| 395 |
|
|---|
| 396 | #define TOFFSET_USART_CFG (0x00)
|
|---|
| 397 | #define TOFFSET_USART_CTRL (0x04)
|
|---|
| 398 | #define TOFFSET_USART_STAT (0x08)
|
|---|
| 399 | #define TOFFSET_USART_INTENSET (0x0C)
|
|---|
| 400 | #define TOFFSET_USART_INTENCLR (0x10)
|
|---|
| 401 | #define TOFFSET_USART_RXDATA (0x14)
|
|---|
| 402 | #define TOFFSET_USART_RXDATASTAT (0x18)
|
|---|
| 403 | #define TOFFSET_USART_TXDATA (0x1C)
|
|---|
| 404 | #define TOFFSET_USART_BRG (0x20)
|
|---|
| 405 | #define TOFFSET_USART_INTSTAT (0x24)
|
|---|
| 406 |
|
|---|
| 407 | #define TADR_USART_CFG(base) (base + TOFFSET_USART_CFG )
|
|---|
| 408 | #define TADR_USART_CTRL(base) (base + TOFFSET_USART_CTRL )
|
|---|
| 409 | #define TADR_USART_STAT(base) (base + TOFFSET_USART_STAT )
|
|---|
| 410 | #define TADR_USART_INTENSET(base) (base + TOFFSET_USART_INTENSET )
|
|---|
| 411 | #define TADR_USART_INTENCLR(base) (base + TOFFSET_USART_INTENCLR )
|
|---|
| 412 | #define TADR_USART_RXDATA(base) (base + TOFFSET_USART_RXDATA )
|
|---|
| 413 | #define TADR_USART_RXDATASTAT(base) (base + TOFFSET_USART_RXDATASTAT)
|
|---|
| 414 | #define TADR_USART_TXDATA(base) (base + TOFFSET_USART_TXDATA )
|
|---|
| 415 | #define TADR_USART_BRG(base) (base + TOFFSET_USART_BRG )
|
|---|
| 416 | #define TADR_USART_INTSTAT(base) (base + TOFFSET_USART_INTSTAT )
|
|---|
| 417 |
|
|---|
| 418 | // CFG
|
|---|
| 419 | #define TBITPTN_USART_CFG_ENABLE (1 << 0)
|
|---|
| 420 | #define TBITPTN_USART_CFG_DATALEN (3 << 2)
|
|---|
| 421 | #define TBITPTN_USART_CFG_DATALEN_7BIT (0 << 2)
|
|---|
| 422 | #define TBITPTN_USART_CFG_DATALEN_8BIT (1 << 2)
|
|---|
| 423 | #define TBITPTN_USART_CFG_DATALEN_9BIT (2 << 2)
|
|---|
| 424 | #define TBITPTN_USART_CFG_PARITYSEL (3 << 4)
|
|---|
| 425 | #define TBITPTN_USART_CFG_PARITYSEL_NOPARITY (0 << 4)
|
|---|
| 426 | #define TBITPTN_USART_CFG_PARITYSEL_EVEN (2 << 4)
|
|---|
| 427 | #define TBITPTN_USART_CFG_PARITYSEL_ODD (3 << 4)
|
|---|
| 428 | #define TBITPTN_USART_CFG_STOPLEN (1 << 6)
|
|---|
| 429 | #define TBITPTN_USART_CFG_STOPLEN_1BIT (0 << 6)
|
|---|
| 430 | #define TBITPTN_USART_CFG_STOPLEN_2BIT (1 << 6)
|
|---|
| 431 | #define TBITPTN_USART_CFG_CTSEN (1 << 9)
|
|---|
| 432 | #define TBITPTN_USART_CFG_SYNCEN (1 << 11)
|
|---|
| 433 | #define TBITPTN_USART_CFG_CLKPOL (1 << 12)
|
|---|
| 434 | #define TBITPTN_USART_CFG_SYNCMST (1 << 14)
|
|---|
| 435 | #define TBITPTN_USART_CFG_LOOP (1 << 15)
|
|---|
| 436 |
|
|---|
| 437 | // STAT
|
|---|
| 438 | #define TBITPTN_USART_STAT_RXRDY (1 << 0)
|
|---|
| 439 | #define TBITPTN_USART_STAT_RXIDLE (1 << 1)
|
|---|
| 440 | #define TBITPTN_USART_STAT_TXRDY (1 << 2)
|
|---|
| 441 | #define TBITPTN_USART_STAT_TXIDLE (1 << 3)
|
|---|
| 442 | #define TBITPTN_USART_STAT_CTS (1 << 4)
|
|---|
| 443 | #define TBITPTN_USART_STAT_DELTACTS (1 << 5)
|
|---|
| 444 | #define TBITPTN_USART_STAT_TXDISINT (1 << 6)
|
|---|
| 445 | #define TBITPTN_USART_STAT_OVERRUNINT (1 << 8)
|
|---|
| 446 | #define TBITPTN_USART_STAT_RXBRK (1 << 10)
|
|---|
| 447 | #define TBITPTN_USART_STAT_DELTARXBRK (1 << 11)
|
|---|
| 448 | #define TBITPTN_USART_STAT_START (1 << 12)
|
|---|
| 449 | #define TBITPTN_USART_STAT_FRAMERRINT (1 << 13)
|
|---|
| 450 | #define TBITPTN_USART_STAT_PARITYERRINT (1 << 14)
|
|---|
| 451 | #define TBITPTN_USART_STAT_RXNOISEINT (1 << 15)
|
|---|
| 452 |
|
|---|
| 453 | // INTENSET
|
|---|
| 454 | #define TBITPTN_USART_INTENSET_RXRDYEN (1 << 0)
|
|---|
| 455 | #define TBITPTN_USART_INTENSET_TXRDYEN (1 << 2)
|
|---|
| 456 | #define TBITPTN_USART_INTENSET_DELTACTSEN (1 << 5)
|
|---|
| 457 | #define TBITPTN_USART_INTENSET_TXDISINTEN (1 << 6)
|
|---|
| 458 | #define TBITPTN_USART_INTENSET_OVERRUNEN (1 << 8)
|
|---|
| 459 | #define TBITPTN_USART_INTENSET_DELTARXBRKEN (1 << 11)
|
|---|
| 460 | #define TBITPTN_USART_INTENSET_STARTEN (1 << 12)
|
|---|
| 461 | #define TBITPTN_USART_INTENSET_FRAMERREN (1 << 13)
|
|---|
| 462 | #define TBITPTN_USART_INTENSET_PARITYERREN (1 << 14)
|
|---|
| 463 | #define TBITPTN_USART_INTENSET_RXNOISEEN (1 << 15)
|
|---|
| 464 |
|
|---|
| 465 | // INTENCLR
|
|---|
| 466 | #define TBITPTN_USART_INTENCLR_RXRDYCLR (1 << 0)
|
|---|
| 467 | #define TBITPTN_USART_INTENCLR_TXRDYCLR (1 << 2)
|
|---|
| 468 | #define TBITPTN_USART_INTENCLR_DELTACTSCLR (1 << 5)
|
|---|
| 469 | #define TBITPTN_USART_INTENCLR_TXDISINTCLR (1 << 6)
|
|---|
| 470 | #define TBITPTN_USART_INTENCLR_OVERRUNCLR (1 << 8)
|
|---|
| 471 | #define TBITPTN_USART_INTENCLR_DELTARXBRKCLR (1 << 11)
|
|---|
| 472 | #define TBITPTN_USART_INTENCLR_STARTCLR (1 << 12)
|
|---|
| 473 | #define TBITPTN_USART_INTENCLR_FRAMERRCLR (1 << 13)
|
|---|
| 474 | #define TBITPTN_USART_INTENCLR_PARITYERRCLR (1 << 14)
|
|---|
| 475 | #define TBITPTN_USART_INTENCLR_RXNOISECLR (1 << 15)
|
|---|
| 476 |
|
|---|
| 477 |
|
|---|
| 478 | #endif /* TOPPERS_LPC812M101FDH20_H */
|
|---|
![(please configure the [header_logo] section in trac.ini)](/trac_user/contrib/chrome/site/your_project_logo.png){kind=logo}
