[136] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | * Copyright (C) 2015 by 3rd Designing Center
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| 9 | * Imageing System Development Division RICOH COMPANY, LTD.
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 13 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 14 | * å¤ã»åé
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| 15 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 16 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 17 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 18 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 19 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 20 | * ç¨ã§ããå½¢ã§åé
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| 21 | å¸ããå ´åã«ã¯ï¼åé
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| 22 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 23 | * è
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| 24 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 25 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 26 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 27 | * ç¨ã§ããªãå½¢ã§åé
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| 28 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 29 | * ã¨ï¼
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| 30 | * (a) åé
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| 31 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 32 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 33 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 34 | * (b) åé
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| 35 | å¸ã®å½¢æ
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| 36 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 37 | * å ±åãããã¨ï¼
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| 38 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 39 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 40 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 41 | 責ãããã¨ï¼
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| 42 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 43 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 44 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 45 | * å
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| 46 | 責ãããã¨ï¼
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| 47 | *
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| 48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 49 | ã
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| 50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 51 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 52 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 53 | * ã®è²¬ä»»ãè² ããªãï¼
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| 54 | *
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| 55 | * @(#) $Id: chip_serial.c 698 2015-07-27 22:47:16Z roi $
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| 56 | */
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| 57 |
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| 58 | /*
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| 59 | * ã·ãªã¢ã«I/Oããã¤ã¹ï¼SIOï¼ãã©ã¤ãï¼stm32f4xxç¨ï¼
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| 60 | */
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| 61 |
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| 62 | #include <kernel.h>
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| 63 | #include <t_syslog.h>
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| 64 | #include "target_stddef.h"
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| 65 | #include "target_serial.h"
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| 66 | #include "target_syssvc.h"
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| 67 |
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| 68 | /*
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| 69 | * ã¬ã¸ã¹ã¿è¨å®å¤
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| 70 | */
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| 71 | #define PORT2SIOPID(x) ((x) + 1)
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| 72 | #define INDEX_PORT(x) ((x) - 1)
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| 73 | #define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)])
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| 74 |
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| 75 | /*
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| 76 | * GPIO Configuration Mode enumeration
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| 77 | */
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| 78 | #define GPIO_Mode_IN 0x0 /* GPIO Input Mode */
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| 79 | #define GPIO_Mode_OUT GPIO_MODER_MODER0 /* GPIO Output Mode */
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| 80 | #define GPIO_Mode_AF GPIO_MODER_MODER1 /* GPIO Alternate function Mode */
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| 81 | #define GPIO_Mode_AN GPIO_MODER_MODER2 /* GPIO Analog Mode */
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| 82 |
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| 83 | /*
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| 84 | * GPIO Output Maximum frequency enumeration
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| 85 | */
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| 86 | #define GPIO_Speed_2MHz 0x0 /* Low speed */
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| 87 | #define GPIO_Speed_25MHz GPIO_OSPEEDER_OSPEEDR0 /* Medium speed */
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| 88 | #define GPIO_Speed_50MHz GPIO_OSPEEDER_OSPEEDR1 /* Fast speed */
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| 89 | #define GPIO_Speed_100MHz GPIO_OSPEEDER_OSPEEDR2 /* High speed on 30 pF (80 MHz Output max speed on 15 pF) */
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| 90 |
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| 91 | /*
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| 92 | * GPIO Output type enumeration
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| 93 | */
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| 94 | #define GPIO_OType_PP 0x0
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| 95 | #define GPIO_OType_OD 0x1
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| 96 |
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| 97 | /*
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| 98 | * GPIO Configuration PullUp PullDown enumeration
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| 99 | */
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| 100 | #define GPIO_PuPd_NOPULL 0x0
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| 101 | #define GPIO_PuPd_UP GPIO_PUPDR_PUPDR0
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| 102 | #define GPIO_PuPd_DOWN GPIO_PUPDR_PUPDR1
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| 103 |
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| 104 | /*
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| 105 | * AF 7 selection
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| 106 | */
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| 107 | #define GPIO_AF7 0x07 /* AF7 value */
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| 108 |
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| 109 | /*
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| 110 | * USART Word Length
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| 111 | */
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| 112 | #define USART_WordLength_8b 0x0000
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| 113 | #define USART_WordLength_9b USART_CR1_M
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| 114 |
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| 115 | /*
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| 116 | * USART Stop Bits
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| 117 | */
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| 118 | #define USART_StopBits_1 0x0000
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| 119 | #define USART_StopBits_0_5 USART_CR2_STOP_0
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| 120 | #define USART_StopBits_2 USART_CR2_STOP_1
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| 121 | #define USART_StopBits_1_5 USART_CR2_STOP
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| 122 |
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| 123 | /*
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| 124 | * USART Parity
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| 125 | */
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| 126 | #define USART_Parity_No 0x0000
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| 127 | #define USART_Parity_Even USART_CR1_PCE
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| 128 | #define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
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| 129 |
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| 130 | /*
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| 131 | * USART MODE
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| 132 | */
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| 133 | #define USART_Mode_Rx USART_CR1_RE
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| 134 | #define USART_Mode_Tx USART_CR1_TE
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| 135 |
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| 136 | /** @defgroup USART_Hardware_Flow_Control
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| 137 | * @{
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| 138 | */
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| 139 | #define USART_HardwareFlowControl_None 0x0000
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| 140 | #define USART_HardwareFlowControl_RTS USART_CR3_RTSE
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| 141 | #define USART_HardwareFlowControl_CTS USART_CR3_CTSE
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| 142 | #define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
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| 143 |
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| 144 | #define CR1_CLEAR_MASK (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)
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| 145 | #define CR3_CLEAR_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
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| 146 |
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| 147 |
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| 148 | /*
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| 149 | * ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯ã®å®ç¾©
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| 150 | */
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| 151 | typedef struct sio_port_initialization_block {
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| 152 | uint32_t base;
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| 153 | INTNO intno_usart;
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| 154 | } SIOPINIB;
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| 155 |
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| 156 | /*
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| 157 | * å
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| 158 | ¼ç¨GPIOãã¼ãåæåãããã¯ã®å®ç¾©
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| 159 | */
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| 160 | typedef struct gpio_port_initialization_block {
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| 161 | uint32_t clockbase/* pfr*/; /* PFRxã¬ã¸ã¹ã¿ã¢ãã¬ã¹ */
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| 162 | uint32_t clock_set;
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| 163 | uint32_t portbase;
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| 164 | uint32_t port_set;
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| 165 |
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| 166 | uint32_t txportbase;
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| 167 | uint32_t txpinport;
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| 168 | uint32_t txmode_msk;
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| 169 | uint32_t txmode_set;
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| 170 | uint32_t txspeed_msk;
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| 171 | uint32_t txspeed_set;
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| 172 | uint32_t txtype_msk;
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| 173 | uint32_t txtype_set;
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| 174 | uint32_t txpupd_msk;
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| 175 | uint32_t txpupd_set;
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| 176 |
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| 177 | uint32_t rxportbase;
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| 178 | uint32_t rxpinport;
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| 179 | uint32_t rxmode_msk;
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| 180 | uint32_t rxmode_set;
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| 181 | uint32_t rxspeed_msk;
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| 182 | uint32_t rxspeed_set;
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| 183 | uint32_t rxtype_msk;
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| 184 | uint32_t rxtype_set;
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| 185 | uint32_t rxpupd_msk;
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| 186 | uint32_t rxpupd_set;
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| 187 | } GPIOINIB;
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| 188 |
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| 189 | /*
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| 190 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®å®ç¾©
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| 191 | */
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| 192 | struct sio_port_control_block {
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| 193 | const SIOPINIB *p_siopinib; /* ã·ãªã¢ã«I/Oãã¼ãåæåããã㯠*/
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| 194 | const GPIOINIB *p_gpioinib; /* å
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| 195 | ¼ç¨GPIOãã¼ãåæåããã㯠*/
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| 196 | intptr_t exinf; /* æ¡å¼µæ
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| 197 | å ± */
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| 198 | bool_t opnflg; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
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| 199 | };
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| 200 |
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| 201 | /*
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| 202 | * ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯
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| 203 | */
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| 204 | const SIOPINIB siopinib_table[TNUM_SIOP] = {
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| 205 | {(uint32_t)USART1_BASE, (INTNO)INTNO_SIO1},
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| 206 | #if TNUM_SIOP >= 2
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| 207 | {(uint32_t)USART2_BASE, (INTNO)INTNO_SIO2},
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| 208 | #endif
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| 209 | };
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| 210 |
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| 211 | /*
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| 212 | * å
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| 213 | ¼ç¨GPIOãã¼ãåæåãããã¯
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| 214 | */
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| 215 | const GPIOINIB gpioinib_table[TNUM_SIOP] = {
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| 216 | {(uint32_t)(TADR_RCC_BASE+TOFF_U1_APBNER), (uint32_t)ENABLE_U1_PORT,
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| 217 | (uint32_t)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR), (uint32_t)ENABLE_U1_GPIO,
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| 218 | (uint32_t)TADR_U1_GPIO_BASE, (uint32_t)TX1_PINPOS,
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| 219 | (uint32_t)~(GPIO_MODER_MODER2 << (TX1_PINPOS*2)), (uint32_t)(GPIO_Mode_AF << (TX1_PINPOS*2)),
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| 220 | (uint32_t)~(GPIO_OSPEEDER_OSPEEDR2 << (TX1_PINPOS*2)), (uint32_t)(GPIO_Speed_50MHz << (TX1_PINPOS*2)),
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| 221 | (uint32_t)~(GPIO_OTYPER_OT << TX1_PINPOS), (uint32_t)(GPIO_OType_PP << TX1_PINPOS),
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| 222 | (uint32_t)~(GPIO_PUPDR_PUPDR2 << (TX1_PINPOS*2)), (uint32_t)(GPIO_PuPd_UP << (TX1_PINPOS*2)),
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| 223 | (uint32_t)TADR_U1_GPIO_BASE, (uint32_t)RX1_PINPOS,
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| 224 | (uint32_t)~(GPIO_MODER_MODER2 << (RX1_PINPOS*2)), (uint32_t)(GPIO_Mode_AF << (RX1_PINPOS*2)),
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| 225 | (uint32_t)~(GPIO_OSPEEDER_OSPEEDR2 << (RX1_PINPOS*2)), (uint32_t)(GPIO_Speed_50MHz << (RX1_PINPOS*2)),
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| 226 | (uint32_t)~(GPIO_OTYPER_OT << RX1_PINPOS), (uint32_t)(GPIO_OType_PP << RX1_PINPOS),
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| 227 | (uint32_t)~(GPIO_PUPDR_PUPDR2 << (RX1_PINPOS*2)), (uint32_t)(GPIO_PuPd_UP << (RX1_PINPOS*2))
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| 228 | #if TNUM_SIOP >= 2
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| 229 | },
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| 230 | {(uint32_t)(TADR_RCC_BASE+TOFF_U2_APBNER), (uint32_t)ENABLE_U2_PORT,
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| 231 | (uint32_t)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR), (uint32_t)ENABLE_U2_GPIO,
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| 232 | (uint32_t)TADR_U2_GPIO_BASE, (uint32_t)TX2_PINPOS,
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| 233 | (uint32_t)~(GPIO_MODER_MODER2 << (TX2_PINPOS*2)), (uint32_t)(GPIO_Mode_AF << (TX2_PINPOS*2)),
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| 234 | (uint32_t)~(GPIO_OSPEEDER_OSPEEDR2 << (TX2_PINPOS*2)), (uint32_t)(GPIO_Speed_50MHz << (TX2_PINPOS*2)),
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| 235 | (uint32_t)~(GPIO_OTYPER_OT << TX2_PINPOS), (uint32_t)(GPIO_OType_PP << TX2_PINPOS),
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| 236 | (uint32_t)~(GPIO_PUPDR_PUPDR2 << (TX2_PINPOS*2)), (uint32_t)(GPIO_PuPd_UP << (TX2_PINPOS*2)),
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| 237 | (uint32_t)TADR_U2_GPIO_BASE, (uint32_t)RX2_PINPOS,
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| 238 | (uint32_t)~(GPIO_MODER_MODER2 << (RX2_PINPOS*2)), (uint32_t)(GPIO_Mode_AF << (RX2_PINPOS*2)),
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| 239 | (uint32_t)~(GPIO_OSPEEDER_OSPEEDR2 << (RX2_PINPOS*2)), (uint32_t)(GPIO_Speed_50MHz << (RX2_PINPOS*2)),
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| 240 | (uint32_t)~(GPIO_OTYPER_OT << RX2_PINPOS), (uint32_t)(GPIO_OType_PP << RX2_PINPOS),
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| 241 | (uint32_t)~(GPIO_PUPDR_PUPDR2 << (RX2_PINPOS*2)), (uint32_t)(GPIO_PuPd_UP << (RX2_PINPOS*2)),
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| 242 | #endif
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| 243 | }
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| 244 | };
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| 245 |
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| 246 | /*
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| 247 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®ã¨ãªã¢
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| 248 | */
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| 249 | SIOPCB siopcb_table[TNUM_SIOP];
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| 250 |
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| 251 | /*
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| 252 | * ã·ãªã¢ã«I/Oãã¼ãIDãã管çãããã¯ãåãåºãããã®ãã¯ã
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| 253 | */
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| 254 | #define INDEX_SIOP(siopid) ((uint_t)((siopid) - 1))
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| 255 | #define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
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| 256 |
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| 257 | static void setup_gpio_source(uint32_t base, uint8_t source, uint8_t select)
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| 258 | {
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| 259 | uint32_t tmpreg, regoff;
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| 260 | regoff = TOFF_GPIO_AFR0+((source>>1) & 0x4);
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| 261 | tmpreg = (sil_rew_mem((uint32_t *)(base+regoff)) & ~(0xF << ((source & 0x07) * 4)))
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| 262 | | (select << ((source & 0x07) * 4));
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| 263 | sil_wrw_mem((uint32_t *)(base+regoff), tmpreg);
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| 264 | }
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| 265 |
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| 266 | void put_hex(char a, int val)
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| 267 | {
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| 268 | int i, j;
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| 269 | target_fput_log(a);
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| 270 | target_fput_log(' ');
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| 271 | for(i = 28 ; i >= 0 ; i-= 4){
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| 272 | j = (val >> i) & 0xf;;
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| 273 | if(j > 9)
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| 274 | j += ('A'-10);
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| 275 | else
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| 276 | j += '0';
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| 277 | target_fput_log(j);
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| 278 | }
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| 279 | target_fput_log('\n');
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| 280 | }
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| 281 |
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| 282 | /*
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| 283 | * SIOãã©ã¤ãã®åæå
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| 284 | */
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| 285 | void
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| 286 | sio_initialize(intptr_t exinf)
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| 287 | {
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| 288 | SIOPCB *p_siopcb;
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| 289 | uint_t i;
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| 290 |
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| 291 | /*
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| 292 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®åæå
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| 293 | */
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| 294 | for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
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| 295 | p_siopcb->p_siopinib = &(siopinib_table[i]);
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| 296 | p_siopcb->p_gpioinib = &(gpioinib_table[i]);
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| 297 | p_siopcb->opnflg = false;
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| 298 | }
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| 299 | }
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| 300 |
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| 301 |
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| 302 | /*
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| 303 | * ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
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| 304 | */
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| 305 | SIOPCB *
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| 306 | sio_opn_por(ID siopid, intptr_t exinf)
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| 307 | {
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| 308 | SIOPCB *p_siopcb;
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| 309 | const SIOPINIB *p_siopinib;
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| 310 | const GPIOINIB *p_gpioinib;
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| 311 | bool_t opnflg;
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| 312 | ER ercd;
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| 313 | uint32_t base, txbase, rxbase;
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| 314 | uint32_t apbclock, integerdivider, fractionaldivider, tmp;
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| 315 |
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| 316 | p_siopcb = get_siopcb(siopid);
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| 317 | p_siopinib = p_siopcb->p_siopinib;
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| 318 | p_gpioinib = p_siopcb->p_gpioinib;
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| 319 |
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| 320 | /*
|
---|
| 321 | * ãªã¼ãã³ãããã¼ããããããopnflgã«èªãã§ããï¼
|
---|
| 322 | */
|
---|
| 323 | opnflg = p_siopcb->opnflg;
|
---|
| 324 |
|
---|
| 325 | p_siopcb->exinf = exinf;
|
---|
| 326 | txbase = p_gpioinib->txportbase;
|
---|
| 327 | rxbase = p_gpioinib->rxportbase;
|
---|
| 328 |
|
---|
| 329 | if(txbase == 0 || rxbase == 0) /* no usart port */
|
---|
| 330 | goto sio_opn_exit;
|
---|
| 331 |
|
---|
| 332 | /*
|
---|
| 333 | * ãã¼ãã¦ã§ã¢ã®åæå
|
---|
| 334 | */
|
---|
| 335 | sil_wrw_mem((uint32_t *)p_gpioinib->clockbase, sil_rew_mem((uint32_t *)p_gpioinib->clockbase) | p_gpioinib->clock_set);
|
---|
| 336 | sil_wrw_mem((uint32_t *)p_gpioinib->portbase, sil_rew_mem((uint32_t *)p_gpioinib->portbase) | p_gpioinib->port_set);
|
---|
| 337 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_MODER), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_MODER)) & p_gpioinib->txmode_msk) | p_gpioinib->txmode_set);
|
---|
| 338 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_OSPEEDR), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_OSPEEDR)) & p_gpioinib->txspeed_msk) | p_gpioinib->txspeed_set);
|
---|
| 339 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_OTYPER), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_OTYPER)) & p_gpioinib->txtype_msk) | p_gpioinib->txtype_set);
|
---|
| 340 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR)) & p_gpioinib->txpupd_msk) | p_gpioinib->txpupd_set);
|
---|
| 341 | sil_wrw_mem((uint32_t *)(rxbase+TOFF_GPIO_MODER), (sil_rew_mem((uint32_t *)(rxbase+TOFF_GPIO_MODER)) & p_gpioinib->rxmode_msk) | p_gpioinib->rxmode_set);
|
---|
| 342 | sil_wrw_mem((uint32_t *)(rxbase+TOFF_GPIO_OSPEEDR), (sil_rew_mem((uint32_t *)(rxbase+TOFF_GPIO_OSPEEDR)) & p_gpioinib->rxspeed_msk) | p_gpioinib->rxspeed_set);
|
---|
| 343 | sil_wrw_mem((uint32_t *)(rxbase+TOFF_GPIO_OTYPER), (sil_rew_mem((uint32_t *)(rxbase+TOFF_GPIO_OTYPER)) & p_gpioinib->rxtype_msk) | p_gpioinib->rxtype_set);
|
---|
| 344 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR)) & p_gpioinib->rxpupd_msk) | p_gpioinib->rxpupd_set);
|
---|
| 345 | setup_gpio_source(txbase, p_gpioinib->txpinport, GPIO_AF7);
|
---|
| 346 | setup_gpio_source(rxbase, p_gpioinib->rxpinport, GPIO_AF7);
|
---|
| 347 |
|
---|
| 348 | base = p_siopinib->base;
|
---|
| 349 |
|
---|
| 350 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) & ~USART_CR1_UE);
|
---|
| 351 | tmp = sil_reh_mem((uint16_t *)(base+TOFF_USART_CR2)) & ~USART_CR2_STOP;
|
---|
| 352 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR2), tmp | USART_StopBits_1);
|
---|
| 353 | tmp = sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) & ~CR1_CLEAR_MASK;
|
---|
| 354 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR1), tmp | USART_WordLength_8b | USART_Parity_No | USART_Mode_Rx | USART_Mode_Tx);
|
---|
| 355 | tmp = sil_reh_mem((uint16_t *)(base+TOFF_USART_CR3)) & ~CR3_CLEAR_MASK;
|
---|
| 356 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR3), tmp | USART_HardwareFlowControl_None);
|
---|
| 357 |
|
---|
| 358 | if ((base == TADR_USART1_BASE) || (base == TADR_USART6_BASE))
|
---|
| 359 | apbclock = SysFrePCLK2;
|
---|
| 360 | else
|
---|
| 361 | apbclock = SysFrePCLK1;
|
---|
| 362 |
|
---|
| 363 | if ((sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) & USART_CR1_OVER8) != 0){
|
---|
| 364 | integerdivider = ((25 * apbclock) / (2 * BPS_SETTING)); /* 8 Samples */
|
---|
| 365 | tmp = (integerdivider / 100) << 4;
|
---|
| 366 | fractionaldivider = integerdivider - (100 * (tmp >> 4));
|
---|
| 367 | tmp |= ((((fractionaldivider * 8) + 50) / 100)) & 0x07;
|
---|
| 368 | }
|
---|
| 369 | else{ /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
|
---|
| 370 | integerdivider = ((25 * apbclock) / (4 * BPS_SETTING)); /* 16 Samples */
|
---|
| 371 | tmp = (integerdivider / 100) << 4;
|
---|
| 372 | fractionaldivider = integerdivider - (100 * (tmp >> 4));
|
---|
| 373 | tmp |= ((((fractionaldivider * 16) + 50) / 100)) & 0x0F;
|
---|
| 374 | }
|
---|
| 375 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_BRR), tmp);
|
---|
| 376 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) | USART_CR1_RXNEIE);
|
---|
| 377 | p_siopcb->opnflg = true;
|
---|
| 378 |
|
---|
| 379 | /*
|
---|
| 380 | * ã·ãªã¢ã«I/Oå²è¾¼ã¿ã®ãã¹ã¯ã解é¤ããï¼
|
---|
| 381 | */
|
---|
| 382 | if (!opnflg) {
|
---|
| 383 | ercd = ena_int(p_siopinib->intno_usart);
|
---|
| 384 | assert(ercd == E_OK);
|
---|
| 385 | }
|
---|
| 386 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) | USART_CR1_UE);
|
---|
| 387 |
|
---|
| 388 | sio_opn_exit:;
|
---|
| 389 | return(p_siopcb);
|
---|
| 390 | }
|
---|
| 391 |
|
---|
| 392 | /*
|
---|
| 393 | * ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
|
---|
| 394 | */
|
---|
| 395 | void
|
---|
| 396 | sio_cls_por(SIOPCB *p_siopcb)
|
---|
| 397 | {
|
---|
| 398 | /*
|
---|
| 399 | * ã·ãªã¢ã«I/Oå²è¾¼ã¿ããã¹ã¯ããï¼
|
---|
| 400 | */
|
---|
| 401 | if ((p_siopcb->opnflg)) {
|
---|
| 402 | dis_int(p_siopcb->p_siopinib->intno_usart);
|
---|
| 403 | }
|
---|
| 404 | p_siopcb->opnflg = false;
|
---|
| 405 | }
|
---|
| 406 |
|
---|
| 407 | /*
|
---|
| 408 | * SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
|
---|
| 409 | */
|
---|
| 410 |
|
---|
| 411 | Inline bool_t
|
---|
| 412 | sio_putready(SIOPCB* p_siopcb)
|
---|
| 413 | {
|
---|
| 414 | uint16_t cr1 = sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1));
|
---|
| 415 | uint16_t ssr = sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_SR));
|
---|
| 416 |
|
---|
| 417 | if ((cr1 & USART_CR1_TXEIE) != 0 && (ssr & USART_SR_TC) != 0)
|
---|
| 418 | {
|
---|
| 419 | return 1;
|
---|
| 420 | }
|
---|
| 421 | return 0;
|
---|
| 422 | }
|
---|
| 423 |
|
---|
| 424 | Inline bool_t
|
---|
| 425 | sio_getready(SIOPCB* p_siopcb)
|
---|
| 426 | {
|
---|
| 427 | uint16_t cr1 = sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1));
|
---|
| 428 | uint16_t ssr = sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_SR));
|
---|
| 429 |
|
---|
| 430 | if ((ssr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) != 0)
|
---|
| 431 | {
|
---|
| 432 | return 0;
|
---|
| 433 | }
|
---|
| 434 | if ((cr1 & USART_CR1_RXNEIE) != 0 && (ssr & USART_SR_RXNE) != 0)
|
---|
| 435 | {
|
---|
| 436 | return 1;
|
---|
| 437 | }
|
---|
| 438 | return 0;
|
---|
| 439 | }
|
---|
| 440 |
|
---|
| 441 | void
|
---|
| 442 | sio_usart_isr(intptr_t exinf)
|
---|
| 443 | {
|
---|
| 444 | SIOPCB *p_siopcb;
|
---|
| 445 |
|
---|
| 446 | p_siopcb = get_siopcb(exinf);
|
---|
| 447 |
|
---|
| 448 | if (sio_getready(p_siopcb)) {
|
---|
| 449 | sio_irdy_rcv(p_siopcb->exinf);
|
---|
| 450 | }
|
---|
| 451 | if (sio_putready(p_siopcb)) {
|
---|
| 452 | sio_irdy_snd(p_siopcb->exinf);
|
---|
| 453 | }
|
---|
| 454 | }
|
---|
| 455 |
|
---|
| 456 | /*
|
---|
| 457 | * ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
|
---|
| 458 | */
|
---|
| 459 | bool_t
|
---|
| 460 | sio_snd_chr(SIOPCB *p_siopcb, char c)
|
---|
| 461 | {
|
---|
| 462 | if (sio_putready(p_siopcb)) {
|
---|
| 463 | sil_wrh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_DR), (uint16_t)c);
|
---|
| 464 | return true;
|
---|
| 465 | }
|
---|
| 466 | return false;
|
---|
| 467 | }
|
---|
| 468 |
|
---|
| 469 | /*
|
---|
| 470 | * ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
|
---|
| 471 | */
|
---|
| 472 | int_t
|
---|
| 473 | sio_rcv_chr(SIOPCB *p_siopcb)
|
---|
| 474 | {
|
---|
| 475 | int_t c = -1;
|
---|
| 476 |
|
---|
| 477 | if (sio_getready(p_siopcb)) {
|
---|
| 478 | c = sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_DR)) & 0xFF;
|
---|
| 479 | }
|
---|
| 480 | return c;
|
---|
| 481 | }
|
---|
| 482 |
|
---|
| 483 | /*
|
---|
| 484 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
|
---|
| 485 | */
|
---|
| 486 | void
|
---|
| 487 | sio_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
|
---|
| 488 | {
|
---|
| 489 | switch (cbrtn) {
|
---|
| 490 | case SIO_RDY_SND:
|
---|
| 491 | sil_wrh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1)) | USART_CR1_TXEIE);
|
---|
| 492 | break;
|
---|
| 493 | case SIO_RDY_RCV:
|
---|
| 494 | sil_wrh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1)) | USART_CR1_RXNEIE);
|
---|
| 495 | break;
|
---|
| 496 | }
|
---|
| 497 | }
|
---|
| 498 |
|
---|
| 499 | /*
|
---|
| 500 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
|
---|
| 501 | */
|
---|
| 502 | void
|
---|
| 503 | sio_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
|
---|
| 504 | {
|
---|
| 505 | switch (cbrtn) {
|
---|
| 506 | case SIO_RDY_SND:
|
---|
| 507 | sil_wrh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1)) & ~USART_CR1_TXEIE);
|
---|
| 508 | break;
|
---|
| 509 | case SIO_RDY_RCV:
|
---|
| 510 | sil_wrh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(p_siopcb->p_siopinib->base+TOFF_USART_CR1)) & ~USART_CR1_RXNEIE);
|
---|
| 511 | break;
|
---|
| 512 | }
|
---|
| 513 | }
|
---|
| 514 |
|
---|
| 515 | /*
|
---|
| 516 | * 1æååºåï¼ãã¼ãªã³ã°ã§ã®åºåï¼
|
---|
| 517 | */
|
---|
| 518 | void sio_pol_snd_chr(int8_t c, ID siopid)
|
---|
| 519 | {
|
---|
| 520 | uint32_t base = siopinib_table[INDEX_PORT(siopid)].base;
|
---|
| 521 |
|
---|
| 522 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_DR), (uint16_t)c);
|
---|
| 523 | while(0 == (sil_reh_mem((uint16_t *)(base+TOFF_USART_SR)) & USART_SR_TC));
|
---|
| 524 |
|
---|
| 525 | /*
|
---|
| 526 | * åºåãå®å
|
---|
| 527 | ¨ã«çµããã¾ã§å¾
|
---|
| 528 | ã¤
|
---|
| 529 | */
|
---|
| 530 | volatile int n = 300000000/BPS_SETTING;
|
---|
| 531 | while(n--);
|
---|
| 532 | }
|
---|
| 533 |
|
---|
| 534 | /*
|
---|
| 535 | * ã¿ã¼ã²ããã®ã·ãªã¢ã«åæå
|
---|
| 536 | */
|
---|
| 537 | void chip_uart_init(ID siopid)
|
---|
| 538 | {
|
---|
| 539 | const GPIOINIB *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)];
|
---|
| 540 | const SIOPINIB *p_siopinib = &siopinib_table[INDEX_PORT(siopid)];
|
---|
| 541 | uint32_t base, txbase, rxbase;
|
---|
| 542 | uint32_t apbclock, integerdivider, fractionaldivider, tmp;
|
---|
| 543 |
|
---|
| 544 | txbase = p_gpioinib->txportbase;
|
---|
| 545 | rxbase = p_gpioinib->rxportbase;
|
---|
| 546 |
|
---|
| 547 | sil_wrw_mem((uint32_t *)p_gpioinib->clockbase, sil_rew_mem((uint32_t *)p_gpioinib->clockbase) | p_gpioinib->clock_set);
|
---|
| 548 | sil_wrw_mem((uint32_t *)p_gpioinib->portbase, sil_rew_mem((uint32_t *)p_gpioinib->portbase) | p_gpioinib->port_set);
|
---|
| 549 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_MODER), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_MODER)) & p_gpioinib->txmode_msk) | p_gpioinib->txmode_set);
|
---|
| 550 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_OSPEEDR), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_OSPEEDR)) & p_gpioinib->txspeed_msk) | p_gpioinib->txspeed_set);
|
---|
| 551 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_OTYPER), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_OTYPER)) & p_gpioinib->txtype_msk) | p_gpioinib->txtype_set);
|
---|
| 552 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR)) & p_gpioinib->txpupd_msk) | p_gpioinib->txpupd_set);
|
---|
| 553 | sil_wrw_mem((uint32_t *)(rxbase+TOFF_GPIO_MODER), (sil_rew_mem((uint32_t *)(rxbase+TOFF_GPIO_MODER)) & p_gpioinib->rxmode_msk) | p_gpioinib->rxmode_set);
|
---|
| 554 | sil_wrw_mem((uint32_t *)(rxbase+TOFF_GPIO_OSPEEDR), (sil_rew_mem((uint32_t *)(rxbase+TOFF_GPIO_OSPEEDR)) & p_gpioinib->rxspeed_msk) | p_gpioinib->rxspeed_set);
|
---|
| 555 | sil_wrw_mem((uint32_t *)(rxbase+TOFF_GPIO_OTYPER), (sil_rew_mem((uint32_t *)(rxbase+TOFF_GPIO_OTYPER)) & p_gpioinib->rxtype_msk) | p_gpioinib->rxtype_set);
|
---|
| 556 | sil_wrw_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR), (sil_rew_mem((uint32_t *)(txbase+TOFF_GPIO_PUPDR)) & p_gpioinib->rxpupd_msk) | p_gpioinib->rxpupd_set);
|
---|
| 557 | setup_gpio_source(txbase, p_gpioinib->txpinport, GPIO_AF7);
|
---|
| 558 | setup_gpio_source(rxbase, p_gpioinib->rxpinport, GPIO_AF7);
|
---|
| 559 |
|
---|
| 560 | base = p_siopinib->base;
|
---|
| 561 |
|
---|
| 562 | tmp = sil_reh_mem((uint16_t *)(base+TOFF_USART_CR2)) & ~USART_CR2_STOP;
|
---|
| 563 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR2), tmp | USART_StopBits_1);
|
---|
| 564 | tmp = sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) & ~CR1_CLEAR_MASK;
|
---|
| 565 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR1), tmp | USART_WordLength_8b | USART_Parity_No | USART_Mode_Rx | USART_Mode_Tx);
|
---|
| 566 | tmp = sil_reh_mem((uint16_t *)(base+TOFF_USART_CR3)) & ~CR3_CLEAR_MASK;
|
---|
| 567 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR3), tmp | USART_HardwareFlowControl_None);
|
---|
| 568 |
|
---|
| 569 | if ((base == TADR_USART1_BASE) || (base == TADR_USART6_BASE))
|
---|
| 570 | apbclock = SysFrePCLK2;
|
---|
| 571 | else
|
---|
| 572 | apbclock = SysFrePCLK1;
|
---|
| 573 |
|
---|
| 574 | if ((sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) & USART_CR1_OVER8) != 0){
|
---|
| 575 | integerdivider = ((25 * apbclock) / (2 * BPS_SETTING)); /* 8 Samples */
|
---|
| 576 | tmp = (integerdivider / 100) << 4;
|
---|
| 577 | fractionaldivider = integerdivider - (100 * (tmp >> 4));
|
---|
| 578 | tmp |= ((((fractionaldivider * 8) + 50) / 100)) & 0x07;
|
---|
| 579 | }
|
---|
| 580 | else{ /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
|
---|
| 581 | integerdivider = ((25 * apbclock) / (4 * BPS_SETTING)); /* 16 Samples */
|
---|
| 582 | tmp = (integerdivider / 100) << 4;
|
---|
| 583 | fractionaldivider = integerdivider - (100 * (tmp >> 4));
|
---|
| 584 | tmp |= ((((fractionaldivider * 16) + 50) / 100)) & 0x0F;
|
---|
| 585 | }
|
---|
| 586 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_BRR), tmp);
|
---|
| 587 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) & ~(USART_CR1_TXEIE | USART_CR1_RXNEIE));
|
---|
| 588 | sil_wrh_mem((uint16_t *)(base+TOFF_USART_CR1), sil_reh_mem((uint16_t *)(base+TOFF_USART_CR1)) | USART_CR1_UE);
|
---|
| 589 | }
|
---|