[136] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2005-2011 by Embedded and Real-Time Systems Laboratory
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| 9 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼Free Software Foundation ã«ãã£ã¦å
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| 13 | ¬è¡¨ããã¦ãã
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| 14 | * GNU General Public License ã® Version 2 ã«è¨è¿°ããã¦ããæ¡ä»¶ãï¼ä»¥
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| 15 | * ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§
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| 16 | * ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãåå©ç¨å¯è½ãªãã¤ããªã³ã¼ãï¼ãªãã±ã¼ã¿ãã«ãªã
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| 23 | * ã¸ã§ã¯ããã¡ã¤ã«ãã©ã¤ãã©ãªãªã©ï¼ã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼å©ç¨
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| 24 | * ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 25 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼
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| 26 | * ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 27 | * (3) æ¬ã½ããã¦ã§ã¢ãåå©ç¨ä¸å¯è½ãªãã¤ããªã³ã¼ãã®å½¢ã¾ãã¯æ©å¨ã«çµ
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| 28 | * ã¿è¾¼ãã å½¢ã§å©ç¨ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºãããã¨ï¼
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| 29 | * (a) å©ç¨ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½
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| 31 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (b) å©ç¨ã®å½¢æ
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| 33 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼ä¸è¨èä½æ¨©è
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| 34 | ã«å ±åãã
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| 35 | * ãã¨ï¼
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| 36 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 37 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 38 | ãå
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| 39 | 責ãããã¨ï¼
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| 40 | *
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| 41 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 42 | ã¯ï¼
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| 43 | * æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ã
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| 44 | * ãªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çããã
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| 45 | * ããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 46 | *
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| 47 | */
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| 48 | #ifndef TOPPERS_ST32F_H
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| 49 | #define TOPPERS_ST32F_H
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| 50 |
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| 51 | #include <sil.h>
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| 52 |
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| 53 | /*
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| 54 | * ARM-Mä¾åé¨ã®ã¤ã³ã¯ã«ã¼ã
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| 55 | */
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| 56 | #include "arm_m_gcc/common/arm_m.h"
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| 57 |
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| 58 | /*
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| 59 | * å²è¾¼ã¿çªå·ã®æ大å¤
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| 60 | */
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| 61 | #define TMAX_INTNO (16 + 42)
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| 62 |
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| 63 | /*
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| 64 | * å²è¾¼ã¿åªå
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| 65 | 度ãããå¹
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| 66 | ä¸ã®ãµãåªå
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| 67 | 度ã®ãããå¹
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| 68 |
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| 69 | */
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| 70 | #define TBITW_SUBIPRI 0
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| 71 |
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| 72 | /*
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| 73 | * å²è¾¼ã¿ãã¯ã¿çªå·å®ç¾©
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| 74 | */
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| 75 | #define IRQ_VECTOR_USART1 (16 + 37)
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| 76 | #define IRQ_VECTOR_USART2 (16 + 38)
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| 77 |
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| 78 |
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| 79 | /*
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| 80 | * ããªãã§ã©ã«ã¬ã¸ã¹ã¿å®ç¾©
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| 81 | */
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| 82 | #define PERIPH_REG_BASE (0x40000000UL)
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| 83 | #define SRAM_BASE (0x20000000UL)
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| 84 |
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| 85 | #define APB1_PERIPH (PERIPH_REG_BASE)
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| 86 | #define APB2_PERIPH (PERIPH_REG_BASE + 0x10000)
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| 87 | #define AHB_PERIPH (PERIPH_REG_BASE + 0x20000)
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| 88 |
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| 89 | /* BUS:APB1 */
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| 90 | #define TIM2_BASE (APB1_PERIPH)
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| 91 | #define TIM3_BASE (APB1_PERIPH + 0x400)
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| 92 | #define TIM4_BASE (APB1_PERIPH + 0x800)
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| 93 | #define RTC_BASE (APB1_PERIPH + 0x2800)
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| 94 | #define WWDG_BASE (APB1_PERIPH + 0x2C00)
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| 95 | #define IWDG_BASE (APB1_PERIPH + 0x3000)
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| 96 | #define SPI2_BASE (APB1_PERIPH + 0x3800)
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| 97 | #define USART2_BASE (APB1_PERIPH + 0x4400)
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| 98 | #define USART3_BASE (APB1_PERIPH + 0x4800)
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| 99 | #define I2C1_BASE (APB1_PERIPH + 0x5400)
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| 100 | #define I2C2_BASE (APB1_PERIPH + 0x5800)
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| 101 | #define USB_BASE (APB1_PERIPH + 0x5C00)
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| 102 | #define CAN_BASE (APB1_PERIPH + 0x6400)
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| 103 | #define BKP_BASE (APB1_PERIPH + 0x6C00)
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| 104 | #define PWR_BASE (APB1_PERIPH + 0x7000)
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| 105 |
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| 106 | /* BUS:APB2 */
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| 107 | #define AFIO_BASE (APB2_PERIPH)
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| 108 | #define EXTI_BASE (APB2_PERIPH + 0x400)
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| 109 | #define GPIOA_BASE (APB2_PERIPH + 0x800)
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| 110 | #define GPIOB_BASE (APB2_PERIPH + 0xC00)
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| 111 | #define GPIOC_BASE (APB2_PERIPH + 0x1000)
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| 112 | #define GPIOD_BASE (APB2_PERIPH + 0x1400)
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| 113 | #define GPIOE_BASE (APB2_PERIPH + 0x1800)
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| 114 | #define ADC1_BASE (APB2_PERIPH + 0x2400)
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| 115 | #define ADC2_BASE (APB2_PERIPH + 0x2800)
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| 116 | #define TIM1_BASE (APB2_PERIPH + 0x2C00)
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| 117 | #define SPI1_BASE (APB2_PERIPH + 0x3000)
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| 118 | #define USART1_BASE (APB2_PERIPH + 0x3800)
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| 119 |
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| 120 | /* BUS:AHB */
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| 121 | #define DMA_BASE (AHB_PERIPH)
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| 122 | #define RCC_BASE (AHB_PERIPH + 0x1000)
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| 123 | #define FLASH_BASE (AHB_PERIPH + 0x2000)
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| 124 |
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| 125 | /* System Control space */
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| 126 | #define SCS_BASE (0xE000E000)
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| 127 | #define SYSTM_BASE (SCS_BASE + 0x0010)
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| 128 | #define NVIC_BASE (SCS_BASE + 0x0100)
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| 129 | #define SYSCB_BASE (SCS_BASE + 0x0D00)
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| 130 |
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| 131 | /* RCC */
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| 132 | #define RCC_CR (RCC_BASE)
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| 133 | #define RCC_CFGR (RCC_BASE + 0x04)
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| 134 | #define RCC_CIR (RCC_BASE + 0x08)
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| 135 | #define RCC_APB2RSTR (RCC_BASE + 0x0C)
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| 136 | #define RCC_APB1RSTR (RCC_BASE + 0x10)
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| 137 | #define RCC_AHBENR (RCC_BASE + 0x14)
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| 138 | #define RCC_APB2ENR (RCC_BASE + 0x18)
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| 139 | #define RCC_APB1ENR (RCC_BASE + 0x1C)
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| 140 | #define RCC_BDCR (RCC_BASE + 0x20)
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| 141 | #define RCC_CSR (RCC_BASE + 0x24)
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| 142 |
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| 143 |
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| 144 | /* NVIC */
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| 145 | #define NVIC_ENAVLE_REG(ch) (NVIC_BASE + ((ch) >> 5))
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| 146 | #define NVIC_DISABLE_REG(ch) (NVIC_BASE + 0x80 + ((ch) >> 5))
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| 147 | #define NVIC_SET_PEND_REG(ch) (NVIC_BASE + 0x100 + ((ch) >> 5))
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| 148 | #define NVIC_CLEAR_PEND_REG(ch) (NVIC_BASE + 0x180 + ((ch) >> 5))
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| 149 | #define NVIC_ACTIVE_REG(ch) (NVIC_BASE + 0x200 + ((ch) >> 5))
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| 150 | #define NVIC_PRIO_REG(ch) (NVIC_BASE + 0x300 + ((ch) >> 2))
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| 151 |
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| 152 | /* GPIOx */
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| 153 | #define GPIO_CRL(x) (x)
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| 154 | #define GPIO_CRH(x) ((x) + 0x04)
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| 155 | #define GPIO_IDR(x) ((x) + 0x08)
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| 156 | #define GPIO_ODR(x) ((x) + 0x0C)
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| 157 | #define GPIO_BSRR(x) ((x) + 0x10)
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| 158 | #define GPIO_BRR(x) ((x) + 0x14)
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| 159 | #define GPIO_LCKR(x) ((x) + 0x18)
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| 160 |
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| 161 | /* AFIO */
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| 162 | #define AFIO_EVCR (AFIO_BASE)
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| 163 | #define AFIO_MAPR (AFIO_BASE + 0x04)
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| 164 | #define AFIO_EXTICR1 (AFIO_BASE + 0x08)
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| 165 | #define AFIO_EXTICR2 (AFIO_BASE + 0x0C)
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| 166 | #define AFIO_EXTICR3 (AFIO_BASE + 0x10)
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| 167 | #define AFIO_EXTICR4 (AFIO_BASE + 0x14)
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| 168 |
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| 169 | /* FLASH */
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| 170 | #define FLASH_ACR (FLASH_BASE)
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| 171 |
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| 172 | /* RCCã¬ã¸ã¹ã¿å®ç¾© */
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| 173 | #define CR_PLL_RDY (0x02000000)
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| 174 | #define CR_PLL_ON (0x01000000)
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| 175 | #define CR_HSE_RDY (0x00020000)
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| 176 | #define CR_HSE_ON (0x00010000)
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| 177 | #define CR_HSI_RDY (0x00000002)
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| 178 | #define CR_HSI_ON (0x00000001)
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| 179 | #define CFGR_PLLMUL_MASK (0x003C0000)
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| 180 | #define CFGR_PLL_XTPRE (0x00020000)
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| 181 | #define CFGR_PLL_SRC (0x00010000)
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| 182 | #define CFGR_HPRE_MASK (0x000000F0)
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| 183 | #define CFGR_PPRE2_MASK (0x00003800)
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| 184 | #define CFGR_PPRE1_MASK (0x00000700)
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| 185 | #define CFGR_SWS_MASK (0x0000000C)
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| 186 | #define CFGR_SW_MASK (0x00000003)
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| 187 | #define CFGR_SW_PLL (0x02)
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| 188 | #define APB1ENR_USART2_EN (0x00020000)
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| 189 | #define APB2ENR_ADC3_EN (0x8000)
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| 190 | #define APB2ENR_USART1_EN (0x4000)
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| 191 | #define APB2ENR_TIM8_EN (0x2000)
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| 192 | #define APB2ENR_SPI1_EN (0x1000)
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| 193 | #define APB2ENR_TIM1_EN (0x0800)
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| 194 | #define APB2ENR_ADC2_EN (0x0400)
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| 195 | #define APB2ENR_ADC1_EN (0x0200)
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| 196 | #define APB2ENR_IOPG_EN (0x0100)
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| 197 | #define APB2ENR_IOPF_EN (0x0080)
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| 198 | #define APB2ENR_IOPE_EN (0x0040)
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| 199 | #define APB2ENR_IOPD_EN (0x0020)
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| 200 | #define APB2ENR_IOPC_EN (0x0010)
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| 201 | #define APB2ENR_IOPB_EN (0x0008)
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| 202 | #define APB2ENR_IOPA_EN (0x0004)
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| 203 | #define APB2ENR_AFIO_EN (0x0001)
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| 204 | #define AHBENR_SDIO_EN (0x0400)
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| 205 | #define AHBENR_FSMC_EN (0x0100)
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| 206 | #define AHBENR_CRCE_EN (0x0040)
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| 207 | #define AHBENR_FLITF_EN (0x0010)
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| 208 | #define AHBENR_SRAM_EN (0x0004)
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| 209 | #define AHBENR_DMA_EN (0x0001)
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| 210 |
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| 211 | /* FLASHã¬ã¸ã¹ã¿å®ç¾© */
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| 212 | #define ACR_PRFTBE (0x10)
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| 213 | #define ACR_LATENCY_MASK (0x07)
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| 214 | #define ACR_LATENCY_ZERO (0x00)
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| 215 | #define ACR_LATENCY_ONE (0x01)
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| 216 | #define ACR_LATENCY_TWO (0x02)
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| 217 |
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| 218 | /* GPIOxã¬ã¸ã¹ã¿å®ç¾© */
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| 219 | #define CNF_IN_ANALOG (0x00)
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| 220 | #define CNF_IN_FLOATING (0x01)
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| 221 | #define CNF_IN_PULL (0x02)
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| 222 | #define CNF_OUT_GP_PP (0x00)
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| 223 | #define CNF_OUT_GP_OD (0x01)
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| 224 | #define CNF_OUT_AF_PP (0x02)
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| 225 | #define CNF_OUT_AF_OD (0x03)
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| 226 | #define MODE_INPUT (0x00)
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| 227 | #define MODE_OUTPUT_10MHZ (0x01)
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| 228 | #define MODE_OUTPUT_2MHZ (0x02)
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| 229 | #define MODE_OUTPUT_50MHZ (0x03)
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| 230 |
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| 231 | #define CR_MODE_MASK(x) (0x03 << ((x) << 2))
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| 232 | #define CR_CNF_MASK(x) (0x0C << ((x) << 2))
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| 233 | #define CR_MODE(x,v) (((v) & 0x03) << ((x) << 2))
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| 234 | #define CR_CNF(x,v) ((((v) << 2) & 0x0C) << ((x) << 2))
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| 235 |
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| 236 | /* AFIOã¬ã¸ã¹ã¿å®ç¾© */
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| 237 | #define MAPR_USART2_REMAP (0x0008)
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| 238 |
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| 239 | #ifndef TOPPERS_MACRO_ONLY
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| 240 | /*
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| 241 | * GPIOã¬ã¸ã¹ã¿æä½é¢æ°
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| 242 | */
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| 243 | Inline void
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| 244 | set_cr_mode(uint32_t reg, uint_t p, int_t v)
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| 245 | {
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| 246 | if (p < 8) {
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| 247 | sil_andw((void*)GPIO_CRL(reg), ~CR_MODE_MASK(p));
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| 248 | sil_orw((void*)GPIO_CRL(reg), CR_MODE(p, v));
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| 249 | } else if (8 <= p && p < 16) {
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| 250 | sil_andw((void*)GPIO_CRH(reg), ~CR_MODE_MASK(p - 8));
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| 251 | sil_orw((void*)GPIO_CRH(reg), CR_MODE(p - 8, v));
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| 252 | }
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| 253 | }
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| 254 |
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| 255 | Inline void
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| 256 | set_cr_cnf(uint32_t reg, uint_t p, int_t v)
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| 257 | {
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| 258 | if (p < 8) {
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| 259 | sil_andw((void*)GPIO_CRL(reg), ~CR_CNF_MASK(p));
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| 260 | sil_orw((void*)GPIO_CRL(reg), CR_CNF(p, v));
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| 261 | } else if (8 <= p && p < 16) {
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| 262 | sil_andw((void*)GPIO_CRH(reg), ~CR_CNF_MASK(p - 8));
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| 263 | sil_orw((void*)GPIO_CRH(reg), CR_CNF(p - 8, v));
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| 264 | }
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| 265 | }
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| 266 |
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| 267 | Inline void
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| 268 | set_port_pull(uint32_t reg, uint_t p, bool_t up)
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| 269 | {
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| 270 | if (up) {
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| 271 | sil_wrw_mem((void*)GPIO_BSRR(reg), 0x01 << p);
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| 272 | } else {
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| 273 | sil_wrw_mem((void*)GPIO_BRR(reg), 0x01 << p);
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| 274 | }
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| 275 | }
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| 276 |
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| 277 | #endif /* TOPPERS_MACRO_ONLY */
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| 278 | #endif /* TOPPERS_ST32F_H */
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