[136] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 11 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 12 | * å¤ã»åé
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| 13 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 14 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 15 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 16 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 17 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 18 | * ç¨ã§ããå½¢ã§åé
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| 19 | å¸ããå ´åã«ã¯ï¼åé
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| 20 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 21 | * è
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| 22 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 23 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 24 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããªãå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 27 | * ã¨ï¼
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| 28 | * (a) åé
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| 29 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 31 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (b) åé
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| 33 | å¸ã®å½¢æ
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| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 35 | * å ±åãããã¨ï¼
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| 36 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 37 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 38 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 39 | 責ãããã¨ï¼
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| 40 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 41 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 43 | * å
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 49 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 50 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 51 | * ã®è²¬ä»»ãè² ããªãï¼
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| 52 | *
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| 53 | * @(#) $Id: core_config_v6m.h 2695 2015-11-05 07:28:01Z ertl-honda $
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| 54 | */
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| 55 |
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| 56 | /*
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| 57 | * å²è¾¼ã¿å¦çã¢ãã«ï¼ARMv6-Mç¨ï¼
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| 58 | *
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| 59 | * ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼core_config.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
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| 60 | * ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
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| 61 | * ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
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| 62 | */
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| 63 |
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| 64 | #ifndef TOPPERS_CORE_INTMODEL_V6M_H
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| 65 | #define TOPPERS_CORE_INTMODEL_V6M_H
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| 66 |
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| 67 | /*
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| 68 | * ã¿ã¼ã²ããä¾åã®ãªãã¸ã§ã¯ãå±æ§
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| 69 | */
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| 70 | #define TARGET_INHATR TA_NONKERNEL /* ã¿ã¼ã²ããå®ç¾©ã®å²è¾¼ã¿ãã³ãã©å±æ§ */
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| 71 |
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| 72 | /*
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| 73 | * å²è¾¼ã¿åªå
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| 74 | 度ãã¹ã¯ã®å¤é¨è¡¨ç¾ã¨å
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| 75 | é¨è¡¨ç¾ã®å¤æ
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| 76 | *
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| 77 | * ã¢ã»ã³ããªè¨èªã®ã½ã¼ã¹ãã¡ã¤ã«ããã¤ã³ã¯ã«ã¼ãããå ´åã®ããã«ï¼
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| 78 | * CASTã使ç¨
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| 79 | * å¤é¨è¡¨ç¾ : TMIN_INTPRI ï½ 0
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| 80 | * å
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| 81 | é¨è¡¨ç¾ : 0 ï½ -TMIN_INTPRI
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| 82 | */
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| 83 | #define EXT_IPM(iipm) (CAST(PRI,iipm + TMIN_INTPRI)) /* å
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| 84 | é¨è¡¨ç¾ãå¤é¨è¡¨ç¾ã« */
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| 85 | #define INT_IPM(ipm) (CAST(uint8_t, ipm - TMIN_INTPRI)) /* å¤é¨è¡¨ç¾ãå
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| 86 | é¨è¡¨ç¾ã« */
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| 87 |
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| 88 | /*
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| 89 | * å²è¾¼ã¿åªå
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| 90 | 度ãã¹ã¯ãNVICã®åªå
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| 91 | 度ã«å¤æ
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| 92 | */
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| 93 | #define INT_NVIC_PRI(ipm) (((1 << TBITW_IPRI) - CAST(uint8_t, -(ipm))) << (8 - TBITW_IPRI))
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| 94 |
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| 95 | /*
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| 96 | * TIPM_ENAALLï¼å²è¾¼ã¿åªå
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| 97 | 度ãã¹ã¯å
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| 98 | ¨è§£é¤ï¼ã®å
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| 99 | é¨è¡¨ç¾
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| 100 | *
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| 101 | */
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| 102 | #define IIPM_ENAALL (-TMIN_INTPRI)
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| 103 |
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| 104 | #ifndef TOPPERS_MACRO_ONLY
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| 105 |
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| 106 | /*
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| 107 | * å²è¾¼ã¿è¦æ±ç¦æ¢ãã©ã°ã®å®ç¾ã®ããã®å¤æ°
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| 108 | */
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| 109 | extern uint32_t ief; /* IRQã®å²è¾¼ã¿è¦æ±è¨±å¯ãã©ã°ã®ç¶æ
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| 110 | */
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| 111 | extern uint8_t ief_systick; /* SysTickã®å²è¾¼ã¿è¦æ±è¨±å¯ãã©ã°ã®ç¶æ
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| 112 | */
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| 113 |
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| 114 | /*
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| 115 | * å²è¾¼ã¿åªå
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| 116 | 度ãã¹ã¯å®ç¾ã®ããã®å¤æ°
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| 117 | */
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| 118 | extern uint8_t iipm; /* ç¾å¨ã®å²è¾¼ã¿åªå
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| 119 | 度ãã¹ã¯ã®å¤ */
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| 120 |
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| 121 | /*
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| 122 | * å²è¾¼ã¿åªå
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| 123 | 度ãã¹ã¯å®ç¾ã®ããã®å¤æ°ï¼kernel_cfg.cï¼
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| 124 | */
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| 125 | extern const uint32_t iipm_enable_irq_tbl[];
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| 126 | extern const uint8_t iipm_enable_systic_tbl[];
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| 127 |
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| 128 | /*
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| 129 | * CPUããã¯ç¶æ
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| 130 | ã¸ã®ç§»è¡
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| 131 | *
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| 132 | */
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| 133 | Inline void
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| 134 | x_lock_cpu(void)
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| 135 | {
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| 136 | set_primask();
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| 137 | /* ã¯ãªãã£ã«ã«ã»ã¯ã·ã§ã³ã®åå¾ã§ã¡ã¢ãªãæ¸ãæããå¯è½æ§ããã */
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| 138 | ARM_MEMORY_CHANGED;
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| 139 | }
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| 140 |
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| 141 | #define t_lock_cpu() x_lock_cpu()
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| 142 | #define i_lock_cpu() x_lock_cpu()
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| 143 |
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| 144 | /*
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| 145 | * CPUããã¯ç¶æ
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| 146 | ã®è§£é¤
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| 147 | *
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| 148 | */
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| 149 | Inline void
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| 150 | x_unlock_cpu(void)
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| 151 | {
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| 152 | /* ã¯ãªãã£ã«ã«ã»ã¯ã·ã§ã³ã®åå¾ã§ã¡ã¢ãªãæ¸ãæããå¯è½æ§ããã */
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| 153 | ARM_MEMORY_CHANGED;
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| 154 | clear_primask();
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| 155 | }
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| 156 |
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| 157 | #define t_unlock_cpu() x_unlock_cpu()
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| 158 | #define i_unlock_cpu() x_unlock_cpu()
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| 159 |
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| 160 | /*
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| 161 | * CPUããã¯ç¶æ
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| 162 | ã®åç
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| 163 | §
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| 164 | */
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| 165 | Inline bool_t
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| 166 | x_sense_lock(void)
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| 167 | {
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| 168 | return(read_primask() == 0x1u);
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| 169 | }
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| 170 |
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| 171 | #define t_sense_lock() x_sense_lock()
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| 172 | #define i_sense_lock() x_sense_lock()
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| 173 |
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| 174 | /*
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| 175 | * chg_ipmã§æå¹ãªå²è¾¼ã¿åªå
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| 176 | 度ã®ç¯å²ã®å¤å®
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| 177 | *
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| 178 | * TMIN_INTPRIã®å¤ã«ãããï¼chg_ipmã§ã¯ï¼-(1 << TBITW_IPRI)ï½TIPM_ENAALLï¼ï¼0ï¼
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| 179 | * ã®ç¯å²ã«è¨å®ã§ãããã¨ã¨ããï¼ã¿ã¼ã²ããå®ç¾©ã®æ¡å¼µï¼ï¼
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| 180 | * å²è¾¼ã¿åªå
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| 181 | 度ã®ãããå¹
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| 182 | (TBITW_IPRI)ã 2 ã®å ´åã¯ï¼-4 ï½ 0 ãæå®å¯è½ã§ããï¼
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| 183 | *
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| 184 | */
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| 185 | #define VALID_INTPRI_CHGIPM(intpri) \
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| 186 | ((-((1 << TBITW_IPRI) - 1) <= (intpri) && (intpri) <= TIPM_ENAALL))
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| 187 |
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| 188 | /*
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| 189 | * ï¼ã¢ãã«ä¸ã®ï¼å²è¾¼ã¿åªå
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| 190 | 度ãã¹ã¯ã®è¨å®
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| 191 | *
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| 192 | */
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| 193 | Inline void
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| 194 | x_set_ipm(PRI intpri)
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| 195 | {
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| 196 | uint32_t tmp;
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| 197 | iipm = INT_IPM(intpri);
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| 198 |
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| 199 | tmp = sil_rew_mem((void *)SYSTIC_CONTROL_STATUS);
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| 200 | if ((iipm_enable_systic_tbl[iipm] & ief_systick) == 0x01) {
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| 201 | tmp |= SYSTIC_TICINT;
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| 202 | }else{
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| 203 | tmp &= ~SYSTIC_TICINT;
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| 204 | }
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| 205 | sil_wrw_mem((void *)SYSTIC_CONTROL_STATUS, tmp);
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| 206 |
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| 207 | /* ä¸æ¦å
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| 208 | ¨å²è¾¼ã¿ç¦æ¢ */
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| 209 | sil_wrw_mem((void *)NVIC_CLRENA0, 0xffffffff);
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| 210 | sil_wrw_mem((void *)NVIC_SETENA0, (iipm_enable_systic_tbl[iipm] & ief));
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| 211 | }
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| 212 |
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| 213 | #define t_set_ipm(intpri) x_set_ipm(intpri)
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| 214 | #define i_set_ipm(intpri) x_set_ipm(intpri)
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| 215 |
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| 216 | /*
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| 217 | * ï¼ã¢ãã«ä¸ã®ï¼å²è¾¼ã¿åªå
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| 218 | 度ãã¹ã¯ã®åç
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| 219 | §
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| 220 | *
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| 221 | */
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| 222 | Inline PRI
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| 223 | x_get_ipm(void)
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| 224 | {
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| 225 | return EXT_IPM(iipm);
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| 226 | }
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| 227 |
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| 228 | #define t_get_ipm() x_get_ipm()
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| 229 | #define i_get_ipm() x_get_ipm()
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| 230 |
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| 231 | /*
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| 232 | * å²è¾¼ã¿è¦æ±ç¦æ¢ãã©ã°
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| 233 | */
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| 234 |
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| 235 | /*
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| 236 | * å²è¾¼ã¿å±æ§ãè¨å®ããã¦ããããå¤å¥ããããã®å¤æ°ï¼kernel_cfg.cï¼
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| 237 | */
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| 238 | extern const uint32_t bitpat_cfgint[];
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| 239 |
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| 240 | /*
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| 241 | * å²è¾¼ã¿è¦æ±ç¦æ¢ãã©ã°ã®ã»ãã
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| 242 | *
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| 243 | * å²è¾¼ã¿å±æ§ãè¨å®ããã¦ããªãå²è¾¼ã¿è¦æ±ã©ã¤ã³ã«å¯¾ãã¦å²è¾¼ã¿è¦æ±ç¦æ¢
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| 244 | * ãã©ã°ãã¯ãªã¢ãããã¨ããå ´åã«ã¯ï¼falseãè¿ãï¼
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| 245 | */
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| 246 | Inline bool_t
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| 247 | x_disable_int(INTNO intno)
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| 248 | {
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| 249 | uint32_t tmp;
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| 250 |
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| 251 | /*
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| 252 | * å²è¾¼ã¿å±æ§ãè¨å®ããã¦ããªãå ´å
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| 253 | */
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| 254 | if ((bitpat_cfgint[intno >> 5] & (1 << (intno & 0x1f))) == 0x00) {
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| 255 | return(false);
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| 256 | }
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| 257 |
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| 258 | if (intno == IRQNO_SYSTICK) {
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| 259 | tmp = sil_rew_mem((void *)SYSTIC_CONTROL_STATUS);
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| 260 | tmp &= ~SYSTIC_TICINT;
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| 261 | sil_wrw_mem((void *)SYSTIC_CONTROL_STATUS, tmp);
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| 262 | ief_systick &= ~0x01;
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| 263 | }else {
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| 264 | tmp = intno - 16;
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| 265 | sil_wrw_mem((void *)(NVIC_CLRENA0), (1 << (tmp & 0x1f)));
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| 266 | ief &= ~(1 << (tmp & 0x1f));
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| 267 | }
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| 268 |
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| 269 | return(true);
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| 270 | }
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| 271 |
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| 272 | #define t_disable_int(intno) x_disable_int(intno)
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| 273 | #define i_disable_int(intno) x_disable_int(intno)
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| 274 |
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| 275 | /*
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| 276 | * å²è¾¼ã¿è¦æ±ç¦æ¢ãã©ã°ã®è§£é¤
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| 277 | *
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| 278 | * å²è¾¼ã¿å±æ§ãè¨å®ããã¦ããªãå²è¾¼ã¿è¦æ±ã©ã¤ã³ã«å¯¾ãã¦å²è¾¼ã¿è¦æ±ç¦æ¢
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| 279 | * ãã©ã°ãã¯ãªã¢ãããã¨ããå ´åã«ã¯ï¼falseãè¿ãï¼
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| 280 | */
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| 281 | Inline bool_t
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| 282 | x_enable_int(INTNO intno)
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| 283 | {
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| 284 | uint32_t tmp;
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| 285 |
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| 286 | /*
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| 287 | * å²è¾¼ã¿å±æ§ãè¨å®ããã¦ããªãå ´å
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| 288 | */
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| 289 | if ((bitpat_cfgint[intno >> 5] & (1 << (intno & 0x1f))) == 0x00) {
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| 290 | return(false);
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| 291 | }
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| 292 |
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| 293 | if (intno == IRQNO_SYSTICK) {
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| 294 | ief_systick |= 0x01;
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| 295 | if ((iipm_enable_systic_tbl[iipm] & ief_systick) == 0x01) {
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| 296 | tmp = sil_rew_mem((void *)SYSTIC_CONTROL_STATUS);
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| 297 | tmp |= SYSTIC_TICINT;;
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| 298 | sil_wrw_mem((void *)SYSTIC_CONTROL_STATUS, tmp);
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| 299 | }
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| 300 | }else {
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| 301 | tmp = intno - 16;
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| 302 | ief |= (1 << (tmp & 0x1f));
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| 303 | if ((iipm_enable_irq_tbl[iipm] & (1 << (tmp & 0x1f))) != 0) {
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| 304 | sil_wrw_mem((void *)(NVIC_SETENA0), (1 << (tmp & 0x1f)));
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| 305 | }
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| 306 | }
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| 307 |
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| 308 | return(true);
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| 309 | }
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| 310 |
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| 311 | #define t_enable_int(intno) x_enable_int(intno)
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| 312 | #define i_enable_int(intno) x_enable_int(intno)
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| 313 |
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| 314 | /*
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| 315 | * PendSVCãã³ãã©ï¼core_support.Sï¼
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| 316 | */
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| 317 | extern void pendsvc_handler(void);
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| 318 |
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| 319 | #endif /* TOPPERS_MACRO_ONLY */
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| 320 | #endif /* TOPPERS_CORE_INTMODEL_V6M_H */
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