[136] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2008-2015 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 11 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 12 | * å¤ã»åé
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| 13 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 14 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 15 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 16 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 17 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 18 | * ç¨ã§ããå½¢ã§åé
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| 19 | å¸ããå ´åã«ã¯ï¼åé
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| 20 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 21 | * è
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| 22 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 23 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 24 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããªãå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 27 | * ã¨ï¼
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| 28 | * (a) åé
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| 29 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 31 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (b) åé
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| 33 | å¸ã®å½¢æ
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| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 35 | * å ±åãããã¨ï¼
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| 36 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 37 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 38 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 39 | 責ãããã¨ï¼
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| 40 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 41 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 43 | * å
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 49 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 50 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 51 | * ã®è²¬ä»»ãè² ããªãï¼
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| 52 | *
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| 53 | * @(#) $Id: arm_m.h 2711 2015-11-23 01:07:27Z ertl-honda $
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| 54 | */
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| 55 |
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| 56 | /*
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| 57 | * ARMVx-Mã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
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| 58 | */
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| 59 |
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| 60 | #ifndef ARM_M_H
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| 61 | #define ARM_M_H
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| 62 |
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| 63 | #if !((__TARGET_ARCH_THUMB == 4) || (__TARGET_ARCH_THUMB == 3))
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| 64 | #error __TARGET_ARCH_THUMB is not defined or other than 4(ARMv7)/3(ARMv6)
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| 65 | #endif /* __TARGET_ARCH_THUMB == 4 */
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| 66 |
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| 67 | /*
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| 68 | * EPSRã®Tããã
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| 69 | */
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| 70 | #define EPSR_T 0x01000000
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| 71 |
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| 72 | /*
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| 73 | * IPSRã® ISR NUMBER
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| 74 | */
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| 75 | #define IPSR_ISR_NUMBER 0x1ff
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| 76 |
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| 77 | /*
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| 78 | * ä¾å¤ã»å²è¾¼ã¿çºçæã«ã¹ã¿ãã¯ä¸ã«ç©ã¾ããä¿åé åã®ãµã¤ãº
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| 79 | * æ¬ã«ã¼ãã«ã§ã¯ä¾å¤ãã¬ã¼ã ã¨å¼ã¶
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| 80 | */
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| 81 | #define EXC_FRAME_SIZE (8*4)
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| 82 |
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| 83 | /*
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| 84 | * ä¾å¤ã»å²è¾¼ã¿çºçæã«LRã«è¨å®ãããEXC_RETURNã®å¤
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| 85 | */
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| 86 | #define EXC_RETURN_PSP 0x04
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| 87 | #define EXC_RETURN_HANDLER_MSP 0x00
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| 88 | #define EXC_RETURN_TREAD_MSP 0x09
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| 89 | #define EXC_RETURN_TREAD_PSP 0x0d
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| 90 | #define EXC_RETURN_FP 0x10
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| 91 | #define EXC_RETURN_FP_USED 0x00
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| 92 | #define EXC_RETURN_FP_NONUSED 0x10
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| 93 | #define EXC_RETURN_OTHER 0xFFFFFFE0
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| 94 |
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| 95 | /*
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| 96 | * CONTROLã¬ã¸ã¹ã¿
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| 97 | */
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| 98 | #define CONTROL_PSP 0x02
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| 99 | #define CONTROL_MSP 0x00
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| 100 | #define CONTROL_FPCA 0x04
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| 101 |
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| 102 | /*
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| 103 | * ä¾å¤çªå·
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| 104 | */
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| 105 | #define EXCNO_NMI 2
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| 106 | #define EXCNO_HARD 3
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| 107 | #define EXCNO_MPU 4
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| 108 | #define EXCNO_BUS 5
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| 109 | #define EXCNO_USAGE 6
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| 110 | #define EXCNO_SVCALL 11
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| 111 | #define EXCNO_DEBUG 12
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| 112 | #define EXCNO_PENDSV 14
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| 113 |
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| 114 | /*
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| 115 | * ä¾å¤çªå·ã®æå°å¤ã¨æ大å¤
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| 116 | */
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| 117 | #define TMIN_EXCNO 2
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| 118 | #define TMAX_EXCNO 14
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| 119 |
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| 120 | /*
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| 121 | * å²è¾¼ã¿çªå·
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| 122 | */
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| 123 | #define IRQNO_SYSTICK 15
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| 124 |
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| 125 | /*
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| 126 | * å²è¾¼ã¿çªå·ã®æå°å¤
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| 127 | */
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| 128 | #define TMIN_INTNO 15
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| 129 |
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| 130 | /*
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| 131 | * ä¾å¤ãã¬ã¼ã ã®ãªãã»ãã
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| 132 | */
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| 133 | #define P_EXCINF_OFFSET_EXC_RETURN 0x01
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| 134 | #define P_EXCINF_OFFSET_IIPM 0x00
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| 135 | #define P_EXCINF_OFFSET_XPSR 0x09
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| 136 | #define P_EXCINF_OFFSET_PC 0x08
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| 137 |
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| 138 | /*
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| 139 | * NVICé¢é£
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| 140 | */
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| 141 |
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| 142 | /*
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| 143 | * ã·ã¹ãã ãã³ãã©ã¼ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿
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| 144 | */
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| 145 | #define NVIC_SYS_HND_CTRL 0xE000ED24
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| 146 |
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| 147 | /*
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| 148 | * åä¾å¤ã®è¨±å¯ããã
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| 149 | */
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| 150 | #define NVIC_SYS_HND_CTRL_USAGE 0x00040000
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| 151 | #define NVIC_SYS_HND_CTRL_BUS 0x00020000
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| 152 | #define NVIC_SYS_HND_CTRL_MEM 0x00010000
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| 153 |
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| 154 | /*
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| 155 | * åªå
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| 156 | 度è¨å®ã¬ã¸ã¹ã¿
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| 157 | */
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| 158 | #define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
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| 159 | #define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
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| 160 | #define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
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| 161 | #define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
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| 162 |
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| 163 | /*
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| 164 | * å²è¾¼ã¿è¨±å¯ã¬ã¸ã¹ã¿
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| 165 | */
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| 166 | #define NVIC_SETENA0 0xE000E100 // IRQ 0 to 31 Set Enable Register
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| 167 |
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| 168 | /*
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| 169 | * å²è¾¼ã¿ç¦æ¢ã¬ã¸ã¹ã¿
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| 170 | */
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| 171 | #define NVIC_CLRENA0 0xE000E180 // IRQ 0 to 31 Set Disable Register
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| 172 |
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| 173 | /*
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| 174 | * å²è¾¼ã¿ã»ãããã³ãã£ã³ã°ã¬ã¸ã¹ã¿
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| 175 | */
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| 176 | #define NVIC_ISER0 0xE000E200 // IRQ 0 to 31 Set-Pending Register
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| 177 |
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| 178 | /*
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| 179 | * å²è¾¼ã¿ã¯ãªã¢ãã³ãã£ã³ã°ã¬ã¸ã¹ã¿
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| 180 | */
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| 181 | #define NVIC_ICER0 0xE000E280 // IRQ 0 to 31 Clear-Pending Register
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| 182 |
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| 183 | /*
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| 184 | * ãã¯ã¿ãã¼ãã«ãªãã»ããã¬ã¸ã¹ã¿
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| 185 | */
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| 186 | #define NVIC_VECTTBL 0xE000ED08
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| 187 |
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| 188 | /*
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| 189 | * å²ãè¾¼ã¿å¶å¾¡ã¨ç¶æ
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| 190 | ã¬ã¸ã¹ã¿
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| 191 | */
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| 192 | #define NVIC_ICSR 0xE000ED04
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| 193 | #define NVIC_PENDSVSET (1 << 28) /* PenvSVCä¾å¤ */
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| 194 | #define NVIC_PENDSTSET (1 << 26) /* SYSTickä¾å¤ */
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| 195 |
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| 196 |
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| 197 | /*
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| 198 | * SYSTICé¢é£ã¬ã¸ã¹ã¿
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| 199 | */
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| 200 | #define SYSTIC_CONTROL_STATUS 0xE000E010
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| 201 | #define SYSTIC_RELOAD_VALUE 0xE000E014
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| 202 | #define SYSTIC_CURRENT_VALUE 0xE000E018
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| 203 | #define SYSTIC_CALIBRATION 0xE000E01C
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| 204 |
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| 205 | #define SYSTIC_ENABLE 0x01
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| 206 | #define SYSTIC_TICINT 0x02
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| 207 | #define SYSTIC_CLKSOURCE 0x04
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| 208 | #define SYSTIC_COUNTFLAG 0x10000
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| 209 |
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| 210 | #define SYSTIC_SKEW 0x40000000
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| 211 | #define SYSTIC_NOREF 0x80000000
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| 212 | #define SYSTIC_TENMS 0x00ffffff
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| 213 |
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| 214 | /*
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| 215 | * FPUé¢é£ã¬ã¸ã¹ã¿
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| 216 | */
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| 217 | #if __TARGET_ARCH_THUMB == 4
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| 218 |
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| 219 | #define CPACR 0xE000ED88
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| 220 | #define FPCCR 0xE000EF34
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| 221 |
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| 222 | #define CPACR_FPU_ENABLE 0x00f00000
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| 223 | #define FPCCR_NO_PRESERV 0x00000000
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| 224 | #define FPCCR_NO_LAZYSTACKING 0x80000000
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| 225 | #define FPCCR_LAZYSTACKING 0xC0000000
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| 226 |
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| 227 | #endif /* __TARGET_ARCH_THUMB == 4 */
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| 228 |
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| 229 |
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| 230 | #if defined(TOPPERS_CORTEX_M0) || defined(TOPPERS_CORTEX_M0PLUS)
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| 231 | /*
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| 232 | * M0/M0+åºæã®å
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| 233 | 容
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| 234 | */
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| 235 |
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| 236 | /*
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| 237 | * å²è¾¼ã¿åªå
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| 238 | 度ã®ç¯å²
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| 239 | */
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| 240 | #define TMIN_INTPRI (-4) /* å²è¾¼ã¿åªå
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| 241 | 度ã®æå°å¤ï¼æé«å¤ï¼*/
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| 242 | #define TMAX_INTPRI (-1) /* å²è¾¼ã¿åªå
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| 243 | 度ã®æ大å¤ï¼æä½å¤ï¼*/
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| 244 |
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| 245 | /*
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| 246 | * å²è¾¼ã¿åªå
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| 247 | 度ã®ãããå¹
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| 248 |
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| 249 | */
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| 250 | #define TBITW_IPRI 2
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| 251 |
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| 252 | #endif /* defined(TOPPERS_CORTEX_M0) || defined(TOPPERS_CORTEX_M0PLUS) */
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| 253 |
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| 254 | #endif /* ARM_M_H */
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