1 | /*
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2 | * TOPPERS/ASP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Just Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2015 by 3rd Designing Center
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7 | * Imageing System Development Division RICOH COMPANY, LTD.
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8 | *
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9 | * ä¸è¨èä½æ¨©è
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10 | ã¯ï¼ä»¥ä¸ã® (1)ï½(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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11 | * ã«ãã£ã¦å
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12 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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13 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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14 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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15 | å¸ï¼ä»¥ä¸ï¼
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17 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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19 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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24 | * è
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27 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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28 | * ç¨ã§ããªãå½¢ã§åé
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29 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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30 | * ã¨ï¼
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31 | * (a) åé
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32 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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33 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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34 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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35 | * (b) åé
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36 | å¸ã®å½¢æ
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37 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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38 | * å ±åãããã¨ï¼
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39 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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40 | * 害ãããï¼ä¸è¨èä½æ¨©è
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41 | ããã³TOPPERSããã¸ã§ã¯ããå
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42 | 責ãããã¨ï¼
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43 | *
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44 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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45 | ã
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46 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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47 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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48 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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49 | *
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50 | * @(#) $Id: stm32f4xx.h,v 1.1 2015/07/18 21:48:24 roi Exp $
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51 | */
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52 |
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53 | #ifndef _STM32F4XX_H_
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54 | #define _STM32F4XX_H_
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55 |
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56 | #include <sil.h>
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57 | #include "cmsis_f4.h"
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58 |
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59 | /*
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60 | * å²è¾¼ã¿çªå·ã®æ大å¤
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61 | */
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62 | #define TMAX_INTNO (16 + 82)
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63 |
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64 | /*
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65 | * å²è¾¼ã¿åªå
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66 | 度ã®ãããå¹
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67 |
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68 | */
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69 | #define TBITW_IPRI 4
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70 |
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71 | /*
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72 | * INTERRUPT NUMBER
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73 | */
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74 | #define IRQ_VECTOR_WWDG (16 + 0) /* Window WatchDog Interrupt */
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75 | #define IRQ_VECTOR_PVD (16 + 1) /* PVD through EXTI Line detection Interrupt */
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76 | #define IRQ_VECTOR_TAMP_STAMP (16 + 2) /* Tamper and TimeStamp interrupts through the EXTI line */
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77 | #define IRQ_VECTOR_RTC_WKUP (16 + 3) /* RTC Wakeup interrupt through the EXTI line */
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78 | #define IRQ_VECTOR_FLASH (16 + 4) /* FLASH global Interrupt */
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79 | #define IRQ_VECTOR_RCC (16 + 5) /* RCC global Interrupt */
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80 | #define IRQ_VECTOR_EXTI0 (16 + 6) /* EXTI Line0 Interrupt */
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81 | #define IRQ_VECTOR_EXTI1 (16 + 7) /* EXTI Line1 Interrupt */
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82 | #define IRQ_VECTOR_EXTI2 (16 + 8) /* EXTI Line2 Interrupt */
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83 | #define IRQ_VECTOR_EXTI3 (16 + 9) /* EXTI Line3 Interrupt */
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84 | #define IRQ_VECTOR_EXTI4 (16 + 10) /* EXTI Line4 Interrupt */
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85 | #define IRQ_VECTOR_DMA1_STREAM0 (16 + 11) /* DMA1 Stream 0 global Interrupt */
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86 | #define IRQ_VECTOR_DMA1_STREAM1 (16 + 12) /* DMA1 Stream 1 global Interrupt */
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87 | #define IRQ_VECTOR_DMA1_STREAM2 (16 + 13) /* DMA1 Stream 2 global Interrupt */
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88 | #define IRQ_VECTOR_DMA1_STREAM3 (16 + 14) /* DMA1 Stream 3 global Interrupt */
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89 | #define IRQ_VECTOR_DMA1_STREAM4 (16 + 15) /* DMA1 Stream 4 global Interrupt */
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90 | #define IRQ_VECTOR_DMA1_STREAM5 (16 + 16) /* DMA1 Stream 5 global Interrupt */
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91 | #define IRQ_VECTOR_DMA1_STREAM6 (16 + 17) /* DMA1 Stream 6 global Interrupt */
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92 | #define IRQ_VECTOR_ADC (16 + 18) /* ADC1, ADC2 and ADC3 global Interrupts */
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93 | #define IRQ_VECTOR_CAN1_TX (16 + 19) /* CAN1 TX Interrupt */
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94 | #define IRQ_VECTOR_CAN1_RX0 (16 + 20) /* CAN1 RX0 Interrupt */
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95 | #define IRQ_VECTOR_CAN1_RX1 (16 + 21) /* CAN1 RX1 Interrupt */
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96 | #define IRQ_VECTOR_CAN1_SCE (16 + 22) /* CAN1 SCE Interrupt */
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97 | #define IRQ_VECTOR_EXTI9_5 (16 + 23) /* External Line[9:5] Interrupts */
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98 | #define IRQ_VECTOR_TIM1_BRK_TIM9 (16 + 24) /* TIM1 Break interrupt and TIM9 global interrupt */
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99 | #define IRQ_VECTOR_TIM1_UP_TIM10 (16 + 25) /* TIM1 Update Interrupt and TIM10 global interrupt */
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100 | #define IRQ_VECTOR_TIM1_TRG_COM_TIM11 (16+26) /* TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
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101 | #define IRQ_VECTOR_TIM1_CC (16 + 27) /* TIM1 Capture Compare Interrupt */
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102 | #define IRQ_VECTOR_TIM2 (16 + 28) /* TIM2 global Interrupt */
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103 | #define IRQ_VECTOR_TIM3 (16 + 29) /* TIM3 global Interrupt */
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104 | #define IRQ_VECTOR_TIM4 (16 + 30) /* TIM4 global Interrupt */
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105 | #define IRQ_VECTOR_I2C1_EV (16 + 31) /* I2C1 Event Interrupt */
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106 | #define IRQ_VECTOR_I2C1_ER (16 + 32) /* I2C1 Error Interrupt */
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107 | #define IRQ_VECTOR_I2C2_EV (16 + 33) /* I2C2 Event Interrupt */
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108 | #define IRQ_VECTOR_I2C2_ER (16 + 34) /* I2C2 Error Interrupt */
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109 | #define IRQ_VECTOR_SPI1 (16 + 35) /* SPI1 global Interrupt */
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110 | #define IRQ_VECTOR_SPI2 (16 + 36) /* SPI2 global Interrupt */
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111 | #define IRQ_VECTOR_USART1 (16 + 37) /* USART1 global Interrupt */
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112 | #define IRQ_VECTOR_USART2 (16 + 38) /* USART2 global Interrupt */
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113 | #define IRQ_VECTOR_USART3 (16 + 39) /* USART3 global Interrupt */
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114 | #define IRQ_VECTOR_EXTI15_10 (16 + 40) /* External Line[15:10] Interrupts */
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115 | #define IRQ_VECTOR_RTC_ALARM (16 + 41) /* RTC Alarm (A and B) through EXTI Line Interrupt */
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116 | #define IRQ_VECTOR_OTG_FS_WKUP (16 + 42) /* USB OTG FS Wakeup through EXTI line interrupt */
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117 | #define IRQ_VECTOR_TIM8_BRK_TIM12 (16 + 43) /* TIM8 Break Interrupt and TIM12 global interrupt */
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118 | #define IRQ_VECTOR_TIM8_UP_TIM13 (16 + 44) /* TIM8 Update Interrupt and TIM13 global interrupt */
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119 | #define IRQ_VECTOR_TIM8_TRG_COM_TIM14 (16+45) /* TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
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120 | #define IRQ_VECTOR_TIM8_CC (16 + 46) /* TIM8 Capture Compare Interrupt */
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121 | #define IRQ_VECTOR_DMA1_STREAM7 (16 + 47) /* DMA1 Stream7 Interrupt */
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122 | #define IRQ_VECTOR_FSMC (16 + 48) /* FSMC global Interrupt */
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123 | #define IRQ_VECTOR_SDIO (16 + 49) /* SDIO global Interrupt */
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124 | #define IRQ_VECTOR_TIM5 (16 + 50) /* TIM5 global Interrupt */
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125 | #define IRQ_VECTOR_SPI3 (16 + 51) /* SPI3 global Interrupt */
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126 | #define IRQ_VECTOR_UART4 (16 + 52) /* UART4 global Interrupt */
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127 | #define IRQ_VECTOR_UART5 (16 + 53) /* UART5 global Interrupt */
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128 | #define IRQ_VECTOR_TIM6_DAC (16 + 54) /* TIM6 global and DAC1&2 underrun error interrupts */
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129 | #define IRQ_VECTOR_TIM7 (16 + 55) /* TIM7 global interrupt */
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130 | #define IRQ_VECTOR_DMA2_STREAM0 (16 + 56) /* DMA2 Stream 0 global Interrupt */
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131 | #define IRQ_VECTOR_DMA2_STREAM1 (16 + 57) /* DMA2 Stream 1 global Interrupt */
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132 | #define IRQ_VECTOR_DMA2_STREAM2 (16 + 58) /* DMA2 Stream 2 global Interrupt */
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133 | #define IRQ_VECTOR_DMA2_STREAM3 (16 + 59) /* DMA2 Stream 3 global Interrupt */
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134 | #define IRQ_VECTOR_DMA2_STREAM4 (16 + 60) /* DMA2 Stream 4 global Interrupt */
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135 | #define IRQ_VECTOR_ETH (16 + 61) /* Ethernet global Interrupt */
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136 | #define IRQ_VECTOR_ETH_WKUP (16 + 62) /* Ethernet Wakeup through EXTI line Interrupt */
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137 | #define IRQ_VECTOR_CAN2_TX (16 + 63) /* CAN2 TX Interrupt */
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138 | #define IRQ_VECTOR_CAN2_RX0 (16 + 64) /* CAN2 RX0 Interrupt */
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139 | #define IRQ_VECTOR_CAN2_RX1 (16 + 65) /* CAN2 RX1 Interrupt */
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140 | #define IRQ_VECTOR_CAN2_SCE (16 + 66) /* CAN2 SCE Interrupt */
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141 | #define IRQ_VECTOR_OTG_FS (16 + 67) /* USB OTG FS global Interrupt */
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142 | #define IRQ_VECTOR_DMA2_STREAM5 (16 + 68) /* DMA2 Stream 5 global interrupt */
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143 | #define IRQ_VECTOR_DMA2_STREAM6 (16 + 69) /* DMA2 Stream 6 global interrupt */
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144 | #define IRQ_VECTOR_DMA2_STREAM7 (16 + 70) /* DMA2 Stream 7 global interrupt */
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145 | #define IRQ_VECTOR_USART6 (16 + 71) /* USART6 global interrupt */
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146 | #define IRQ_VECTOR_I2C3_EV (16 + 72) /* I2C3 event interrupt */
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147 | #define IRQ_VECTOR_I2C3_ER (16 + 73) /* I2C3 error interrupt */
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148 | #define IRQ_VECTOR_OTG_HS_EP1_OUT (16 + 74) /* USB OTG HS End Point 1 Out global interrupt */
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149 | #define IRQ_VECTOR_OTG_HS_EP1_IN (16 + 75) /* USB OTG HS End Point 1 In global interrupt */
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150 | #define IRQ_VECTOR_OTG_HS_WKUP (16 + 76) /* USB OTG HS Wakeup through EXTI interrupt */
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151 | #define IRQ_VECTOR_OTG_HS (16 + 77) /* USB OTG HS global interrupt */
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152 | #define IRQ_VECTOR_DCMI (16 + 78) /* DCMI global interrupt */
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153 | #define IRQ_VECTOR_CRYP (16 + 79) /* CRYP crypto global interrupt */
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154 | #define IRQ_VECTOR_HASH_RNG (16 + 80) /* Hash and Rng global interrupt */
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155 | #define IRQ_VECTOR_FPU (16 + 81) /* FPU global interrupt */
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156 |
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157 | /*
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158 | * PERIPHERAL MEMORY MAP
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159 | */
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160 | #define FLASH_BASE 0x08000000 /*!< FLASH(up to 1 MB) base address in the alias region */
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161 | #define CCMDATARAM_BASE 0x10000000 /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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162 | #define SRAM1_BASE 0x20000000 /*!< SRAM1(112 KB) base address in the alias region */
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163 | #define SRAM2_BASE 0x2001C000 /*!< SRAM2(16 KB) base address in the alias region */
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164 | #define PERIPH_BASE 0x40000000 /*!< Peripheral base address in the alias region */
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165 | #define BKPSRAM_BASE 0x40024000 /*!< Backup SRAM(4 KB) base address in the alias region */
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166 | #define FSMC_R_BASE 0xA0000000 /*!< FSMC registers base address */
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167 |
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168 | #define CCMDATARAM_BB_BASE 0x12000000 /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
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169 | #define SRAM1_BB_BASE 0x22000000 /*!< SRAM1(112 KB) base address in the bit-band region */
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170 | #define SRAM2_BB_BASE 0x2201C000 /*!< SRAM2(16 KB) base address in the bit-band region */
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171 | #define PERIPH_BB_BASE 0x42000000 /*!< Peripheral base address in the bit-band region */
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172 | #define BKPSRAM_BB_BASE 0x42024000 /*!< Backup SRAM(4 KB) base address in the bit-band region */
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173 |
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174 | /*!< Peripheral memory map */
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175 | #define APB1PERIPH_BASE PERIPH_BASE
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176 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
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177 | #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
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178 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
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179 |
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180 | /*
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181 | * TIM
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182 | */
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183 | #define TADR_TIM2_BASE (APB1PERIPH_BASE + 0x0000)
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184 | #define TADR_TIM3_BASE (APB1PERIPH_BASE + 0x0400)
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185 | #define TADR_TIM4_BASE (APB1PERIPH_BASE + 0x0800)
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186 | #define TADR_TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
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187 | #define TADR_TIM6_BASE (APB1PERIPH_BASE + 0x1000)
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188 | #define TADR_TIM7_BASE (APB1PERIPH_BASE + 0x1400)
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189 | #define TADR_TIM12_BASE (APB1PERIPH_BASE + 0x1800)
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190 | #define TADR_TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
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191 | #define TADR_TIM14_BASE (APB1PERIPH_BASE + 0x2000)
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192 | #define TADR_TIM1_BASE (APB2PERIPH_BASE + 0x0000)
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193 | #define TADR_TIM8_BASE (APB2PERIPH_BASE + 0x0400)
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194 | #define TADR_TIM9_BASE (APB2PERIPH_BASE + 0x4000)
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195 | #define TADR_TIM10_BASE (APB2PERIPH_BASE + 0x4400)
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196 | #define TADR_TIM11_BASE (APB2PERIPH_BASE + 0x4800)
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197 | #define TOFF_TIM_CR1 0x0000 /* (RW-16) TIM control register 1 */
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198 | #define TIM_CR1_CEN 0x0001 /* Counter enable */
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199 | #define TIM_CR1_UDIS 0x0002 /* Update disable */
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200 | #define TIM_CR1_URS 0x0004 /* Update request source */
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201 | #define TIM_CR1_OPM 0x0008 /* One pulse mode */
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202 | #define TIM_CR1_DIR 0x0010 /* Direction */
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203 | #define TIM_CR1_CMS_0 0x0020 /* CMS[1:0] bit 0 */
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204 | #define TIM_CR1_CMS_1 0x0040 /* CMS[1:0] bit 1 */
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205 | #define TIM_CR1_ARPE 0x0080 /* Auto-reload preload enable */
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206 | #define TIM_CR1_CKD_0 0x0100 /* CKD[1:0] bit 0 */
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207 | #define TIM_CR1_CKD_1 0x0200 /* CKD[1:0] bit 1 */
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208 | #define TOFF_TIM_CR2 0x0004 /* (RW-16) TIM control register 2 */
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209 | #define TOFF_TIM_SMCR 0x0008 /* (RW-16) TIM slave mode control register */
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210 | #define TOFF_TIM_DIER 0x000C /* (RW-16) TIM DMA/interrupt enable register */
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211 | #define TIM_DIER_UIE 0x0001 /* Update interrupt enable */
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212 | #define TIM_DIER_CC1IE 0x0002 /* Capture/Compare 1 interrupt enable */
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213 | #define TIM_DIER_CC2IE 0x0004 /* Capture/Compare 2 interrupt enable */
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214 | #define TIM_DIER_CC3IE 0x0008 /* Capture/Compare 3 interrupt enable */
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215 | #define TIM_DIER_CC4IE 0x0010 /* Capture/Compare 4 interrupt enable */
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216 | #define TIM_DIER_COMIE 0x0020 /* COM interrupt enable */
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217 | #define TIM_DIER_TIE 0x0040 /* Trigger interrupt enable */
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218 | #define TIM_DIER_BIE 0x0080 /* Break interrupt enable */
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219 | #define TIM_DIER_UDE 0x0100 /* Update DMA request enable */
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220 | #define TIM_DIER_CC1DE 0x0200 /* Capture/Compare 1 DMA request enable */
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221 | #define TIM_DIER_CC2DE 0x0400 /* Capture/Compare 2 DMA request enable */
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222 | #define TIM_DIER_CC3DE 0x0800 /* Capture/Compare 3 DMA request enable */
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223 | #define TIM_DIER_CC4DE 0x1000 /* Capture/Compare 4 DMA request enable */
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224 | #define TIM_DIER_COMDE 0x2000 /* COM DMA request enable */
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225 | #define TIM_DIER_TDE 0x4000 /* Trigger DMA request enable */
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226 | #define TOFF_TIM_SR 0x0010 /* (RW-16) TIM status register */
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227 | #define TIM_SR_UIF 0x0001 /* Update interrupt Flag */
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228 | #define TIM_SR_CC1IF 0x0002 /* Capture/Compare 1 interrupt Flag */
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229 | #define TIM_SR_CC2IF 0x0004 /* Capture/Compare 2 interrupt Flag */
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230 | #define TIM_SR_CC3IF 0x0008 /* Capture/Compare 3 interrupt Flag */
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231 | #define TIM_SR_CC4IF 0x0010 /* Capture/Compare 4 interrupt Flag */
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232 | #define TIM_SR_COMIF 0x0020 /* COM interrupt Flag */
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233 | #define TIM_SR_TIF 0x0040 /* Trigger interrupt Flag */
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234 | #define TIM_SR_BIF 0x0080 /* Break interrupt Flag */
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235 | #define TIM_SR_CC1OF 0x0200 /* Capture/Compare 1 Overcapture Flag */
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236 | #define TIM_SR_CC2OF 0x0400 /* Capture/Compare 2 Overcapture Flag */
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237 | #define TIM_SR_CC3OF 0x0800 /* Capture/Compare 3 Overcapture Flag */
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238 | #define TIM_SR_CC4OF 0x1000 /* Capture/Compare 4 Overcapture Flag */
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239 | #define TOFF_TIM_EGR 0x0014 /* (RW-16) TIM event generation register */
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240 | #define TOFF_TIM_CCMR1 0x0018 /* (RW-16) TIM capture/compare mode register 1 */
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241 | #define TOFF_TIM_CCMR2 0x001C /* (RW-16) TIM capture/compare mode register 2 */
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242 | #define TOFF_TIM_CCER 0x0020 /* (RW-16) TIM capture/compare enable register */
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243 | #define TOFF_TIM_CNT 0x0024 /* (RW) TIM counter register */
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244 | #define TOFF_TIM_PSC 0x0028 /* (RW-16) TIM prescaler */
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245 | #define TOFF_TIM_ARR 0x002C /* (RW) TIM auto-reload register */
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246 | #define TOFF_TIM_RCR 0x0030 /* (RW-16) TIM repetition counter register */
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247 | #define TOFF_TIM_CCR1 0x0034 /* (RW) TIM capture/compare register 1 */
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248 | #define TOFF_TIM_CCR2 0x0038 /* (RW) TIM capture/compare register 2 */
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249 | #define TOFF_TIM_CCR3 0x003C /* (RW) TIM capture/compare register 3 */
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250 | #define TOFF_TIM_CCR4 0x0040 /* (RW) TIM capture/compare register 4 */
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251 | #define TOFF_TIM_BDTR 0x0044 /* (RW-16) TIM break and dead-time register */
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252 | #define TOFF_TIM_DCR 0x0048 /* (RW-16) TIM DMA control register */
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253 | #define TOFF_TIM_DMAR 0x004C /* (RW-16) TIM DMA address for full transfer */
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254 | #define TOFF_TIM_OR 0x0050 /* (RW-16) TIM option register */
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255 |
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256 | /*
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257 | * REAL-TIME CLOCK
|
---|
258 | */
|
---|
259 | #define TADR_RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
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260 | #define TOFF_RTC_TR 0x0000 /* (RW) RTC time register */
|
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261 | #define TOFF_RTC_DR 0x0004 /* (RW) RTC date register */
|
---|
262 | #define TOFF_RTC_CR 0x0008 /* (RW) RTC control register */
|
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263 | #define TOFF_RTC_ISR 0x000C /* (RW) RTC initialization and status register */
|
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264 | #define TOFF_RTC_PRER 0x0010 /* (RW) RTC prescaler register */
|
---|
265 | #define TOFF_RTC_WUTR 0x0014 /* (RW) RTC wakeup timer register */
|
---|
266 | #define TOFF_RTC_CALIBR 0x0018 /* (RW) RTC calibration register */
|
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267 | #define TOFF_RTC_ALRMAR 0x001C /* (RW) RTC alarm A register */
|
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268 | #define TOFF_RTC_ALRMBR 0x0020 /* (RW) RTC alarm B register */
|
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269 | #define TOFF_RTC_WPR 0x0024 /* (RW) RTC write protection register */
|
---|
270 | #define TOFF_RTC_SSR 0x0028 /* (RW) RTC sub second register */
|
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271 | #define TOFF_RTC_SHIFTR 0x002C /* (RW) RTC shift control register */
|
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272 | #define TOFF_RTC_TSTR 0x0030 /* (RW) RTC time stamp time register */
|
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273 | #define TOFF_RTC_TSDR 0x0034 /* (RW) RTC time stamp date register */
|
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274 | #define TOFF_RTC_TSSSR 0x0038 /* (RW) RTC time-stamp sub second register */
|
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275 | #define TOFF_RTC_CALR 0x003C /* (RW) RTC calibration register */
|
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276 | #define TOFF_RTC_TAFCR 0x0040 /* (RW) RTC tamper and alternate function configuration register */
|
---|
277 | #define TOFF_RTC_ALRMASSR 0x0044 /* (RW) RTC alarm A sub second register */
|
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278 | #define TOFF_RTC_ALRMBSSR 0x0048 /* (RW) RTC alarm B sub second register */
|
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279 | #define TOFF_RTC_BKP0R 0x0050 /* (RW) RTC backup register 0 */
|
---|
280 | #define TOFF_RTC_BKP1R 0x0054 /* (RW) RTC backup register 1 */
|
---|
281 | #define TOFF_RTC_BKP2R 0x0058 /* (RW) RTC backup register 2 */
|
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282 | #define TOFF_RTC_BKP3R 0x005C /* (RW) RTC backup register 3 */
|
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283 | #define TOFF_RTC_BKP4R 0x0060 /* (RW) RTC backup register 4 */
|
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284 | #define TOFF_RTC_BKP5R 0x0064 /* (RW) RTC backup register 5 */
|
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285 | #define TOFF_RTC_BKP6R 0x0068 /* (RW) RTC backup register 6 */
|
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286 | #define TOFF_RTC_BKP7R 0x006C /* (RW) RTC backup register 7 */
|
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287 | #define TOFF_RTC_BKP8R 0x0070 /* (RW) RTC backup register 8 */
|
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288 | #define TOFF_RTC_BKP9R 0x0074 /* (RW) RTC backup register 9 */
|
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289 | #define TOFF_RTC_BKP10R 0x0078 /* (RW) RTC backup register 10 */
|
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290 | #define TOFF_RTC_BKP11R 0x007C /* (RW) RTC backup register 11 */
|
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291 | #define TOFF_RTC_BKP12R 0x0080 /* (RW) RTC backup register 12 */
|
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292 | #define TOFF_RTC_BKP13R 0x0084 /* (RW) RTC backup register 13 */
|
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293 | #define TOFF_RTC_BKP14R 0x0088 /* (RW) RTC backup register 14 */
|
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294 | #define TOFF_RTC_BKP15R 0x008C /* (RW) RTC backup register 15 */
|
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295 | #define TOFF_RTC_BKP16R 0x0090 /* (RW) RTC backup register 16 */
|
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296 | #define TOFF_RTC_BKP17R 0x0094 /* (RW) RTC backup register 17 */
|
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297 | #define TOFF_RTC_BKP18R 0x0098 /* (RW) RTC backup register 18 */
|
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298 | #define TOFF_RTC_BKP19R 0x009C /* (RW) RTC backup register 19 */
|
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299 |
|
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300 | /*
|
---|
301 | * WINDOW WATCHDOG
|
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302 | */
|
---|
303 | #define TADR_WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
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304 | #define TOFF_WWDG_CR 0x0000 /* (RW) WWDG Control register */
|
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305 | #define TOFF_WWDG_CFR 0x0004 /* (RW) WWDG Configuration register */
|
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306 | #define TOFF_WWDG_SR 0x0008 /* (R) WWDG Status register */
|
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307 |
|
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308 | /*
|
---|
309 | * INDEPENDENT WATCHDOG
|
---|
310 | */
|
---|
311 | #define TADR_IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
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312 | #define TOFF_IWDG_KR 0x0000 /* (RW) IWDG Key register */
|
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313 | #define TOFF_IWDG_PR 0x0004 /* (RW) IWDG Prescaler register */
|
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314 | #define TOFF_IWDG_RLR 0x0008 /* (RW) IWDG Reload register */
|
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315 | #define TOFF_IWDG_SR 0x000C /* (RW) IWDG Status register */
|
---|
316 |
|
---|
317 | /*
|
---|
318 | * SERIAL PERIPHERAL IINTERFACE
|
---|
319 | */
|
---|
320 | #define TADR_I2S2EXTt_BASE (APB1PERIPH_BASE + 0x3400)
|
---|
321 | #define TADR_SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
---|
322 | #define TADR_SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
|
---|
323 | #define TADR_I2S3EXT_BASE (APB1PERIPH_BASE + 0x4000)
|
---|
324 | #define TADR_SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
---|
325 | #define TOFF_SPI_CR1 0x0000 /* (RW-16) SPI control register 1 (not used in I2S mode) */
|
---|
326 | #define TOFF_SPI_CR2 0x0004 /* (RW-16) SPI control register 2 */
|
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327 | #define TOFF_SPI_SR 0x0008 /* (RW-16) SPI status register */
|
---|
328 | #define TOFF_SPI_DR 0x000C /* (RW-16) SPI data register */
|
---|
329 | #define TOFF_SPI_CRCPR 0x0010 /* (RW-16) SPI CRC polynomial register (not used in I2S mode) */
|
---|
330 | #define TOFF_SPI_RXCRCR 0x0014 /* (RW-16) SPI RX CRC register (not used in I2S mode) */
|
---|
331 | #define TOFF_SPI_TXCRCR 0x0018 /* (RW-16) SPI TX CRC register (not used in I2S mode) */
|
---|
332 | #define TOFF_SPI_I2SCFGR 0x001C /* (RW-16) SPI_I2S configuration register */
|
---|
333 | #define TOFF_SPI_I2SPR 0x0020 /* (RW-16) SPI_I2S prescaler register */
|
---|
334 |
|
---|
335 | /*
|
---|
336 | * UNIVERSAL SYNCHRONOUS ASYNCHORONOUS RECEIVER TRANSMITTER
|
---|
337 | */
|
---|
338 | #define TADR_USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
---|
339 | #define TADR_USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
---|
340 | #define TADR_UART4_BASE (APB1PERIPH_BASE + 0x4C00)
|
---|
341 | #define TADR_UART5_BASE (APB1PERIPH_BASE + 0x5000)
|
---|
342 | #define TADR_USART1_BASE (APB2PERIPH_BASE + 0x1000)
|
---|
343 | #define TADR_USART6_BASE (APB2PERIPH_BASE + 0x1400)
|
---|
344 | #define TOFF_USART_SR 0x0000 /* (RW-16) USART Status register */
|
---|
345 | #define USART_SR_PE 0x0001 /* Parity Error */
|
---|
346 | #define USART_SR_FE 0x0002 /* Framing Error */
|
---|
347 | #define USART_SR_NE 0x0004 /* Noise Error Flag */
|
---|
348 | #define USART_SR_ORE 0x0008 /* OverRun Error */
|
---|
349 | #define USART_SR_IDLE 0x0010 /* IDLE line detected */
|
---|
350 | #define USART_SR_RXNE 0x0020 /* Read Data Register Not Empty */
|
---|
351 | #define USART_SR_TC 0x0040 /* Transmission Complete */
|
---|
352 | #define USART_SR_TXE 0x0080 /* Transmit Data Register Empty */
|
---|
353 | #define USART_SR_LBD 0x0100 /* LIN Break Detection Flag */
|
---|
354 | #define USART_SR_CTS 0x0200 /* CTS Flag */
|
---|
355 | #define TOFF_USART_DR 0x0004 /* (RW-16) USART Data register */
|
---|
356 | #define TOFF_USART_BRR 0x0008 /* (RW-16) USART Baud rate register */
|
---|
357 | #define TOFF_USART_CR1 0x000C /* (RW-16) USART Control register 1 */
|
---|
358 | #define USART_CR1_SBK 0x0001 /* Send Break */
|
---|
359 | #define USART_CR1_RWU 0x0002 /* Receiver wakeup */
|
---|
360 | #define USART_CR1_RE 0x0004 /* Receiver Enable */
|
---|
361 | #define USART_CR1_TE 0x0008 /* Transmitter Enable */
|
---|
362 | #define USART_CR1_IDLEIE 0x0010 /* IDLE Interrupt Enable */
|
---|
363 | #define USART_CR1_RXNEIE 0x0020 /* RXNE Interrupt Enable */
|
---|
364 | #define USART_CR1_TCIE 0x0040 /* Transmission Complete Interrupt Enable */
|
---|
365 | #define USART_CR1_TXEIE 0x0080 /* PE Interrupt Enable */
|
---|
366 | #define USART_CR1_PEIE 0x0100 /* PE Interrupt Enable */
|
---|
367 | #define USART_CR1_PS 0x0200 /* Parity Selection */
|
---|
368 | #define USART_CR1_PCE 0x0400 /* Parity Control Enable */
|
---|
369 | #define USART_CR1_WAKE 0x0800 /* Wakeup method */
|
---|
370 | #define USART_CR1_M 0x1000 /* Word length */
|
---|
371 | #define USART_CR1_UE 0x2000 /* USART Enable */
|
---|
372 | #define USART_CR1_OVER8 0x8000 /* USART Oversampling by 8 enable */
|
---|
373 | #define TOFF_USART_CR2 0x0010 /* (RW-16) USART Control register 2 */
|
---|
374 | #define USART_CR2_ADD 0x000F /* Address of the USART node */
|
---|
375 | #define USART_CR2_LBDL 0x0020 /* LIN Break Detection Length */
|
---|
376 | #define USART_CR2_LBDIE 0x0040 /* LIN Break Detection Interrupt Enable */
|
---|
377 | #define USART_CR2_LBCL 0x0100 /* Last Bit Clock pulse */
|
---|
378 | #define USART_CR2_CPHA 0x0200 /* Clock Phase */
|
---|
379 | #define USART_CR2_CPOL 0x0400 /* Clock Polarity */
|
---|
380 | #define USART_CR2_CLKEN 0x0800 /* Clock Enable */
|
---|
381 | #define USART_CR2_STOP 0x3000 /* STOP[1:0] bits (STOP bits) */
|
---|
382 | #define USART_CR2_STOP_0 0x1000 /* Bit 0 */
|
---|
383 | #define USART_CR2_STOP_1 0x2000 /* Bit 1 */
|
---|
384 | #define USART_CR2_LINEN 0x4000 /* LIN mode enable */
|
---|
385 | #define TOFF_USART_CR3 0x0014 /* (RW-16) USART Control register 3 */
|
---|
386 | #define USART_CR3_EIE 0x0001 /* Error Interrupt Enable */
|
---|
387 | #define USART_CR3_IREN 0x0002 /* IrDA mode Enable */
|
---|
388 | #define USART_CR3_IRLP 0x0004 /* IrDA Low-Power */
|
---|
389 | #define USART_CR3_HDSEL 0x0008 /* Half-Duplex Selection */
|
---|
390 | #define USART_CR3_NACK 0x0010 /* Smartcard NACK enable */
|
---|
391 | #define USART_CR3_SCEN 0x0020 /* Smartcard mode enable */
|
---|
392 | #define USART_CR3_DMAR 0x0040 /* DMA Enable Receiver */
|
---|
393 | #define USART_CR3_DMAT 0x0080 /* DMA Enable Transmitter */
|
---|
394 | #define USART_CR3_RTSE 0x0100 /* RTS Enable */
|
---|
395 | #define USART_CR3_CTSE 0x0200 /* CTS Enable */
|
---|
396 | #define USART_CR3_CTSIE 0x0400 /* CTS Interrupt Enable */
|
---|
397 | #define USART_CR3_ONEBIT 0x0800 /* USART One bit method enable */
|
---|
398 | #define TOFF_USART_GTPR 0x0018 /* (RW-16) USART Guard time and prescaler register */
|
---|
399 | #define USART_GTPR_PSC 0x00FF /* PSC[7:0] bits (Prescaler value) */
|
---|
400 | #define USART_GTPR_PSC_0 0x0001 /* Bit 0 */
|
---|
401 | #define USART_GTPR_PSC_1 0x0002 /* Bit 1 */
|
---|
402 | #define USART_GTPR_PSC_2 0x0004 /* Bit 2 */
|
---|
403 | #define USART_GTPR_PSC_3 0x0008 /* Bit 3 */
|
---|
404 | #define USART_GTPR_PSC_4 0x0010 /* Bit 4 */
|
---|
405 | #define USART_GTPR_PSC_5 0x0020 /* Bit 5 */
|
---|
406 | #define USART_GTPR_PSC_6 0x0040 /* Bit 6 */
|
---|
407 | #define USART_GTPR_PSC_7 0x0080 /* Bit 7 */
|
---|
408 | #define USART_GTPR_GT 0xFF00 /* Guard time value */
|
---|
409 |
|
---|
410 | /*
|
---|
411 | * INTER-INTERATED CIRCUIT IINTERFACE(16)
|
---|
412 | */
|
---|
413 | #define TADR_I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
---|
414 | #define TADR_I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
---|
415 | #define TADR_I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
|
---|
416 | #define TOFF_I2C_CR1 0x0000 /* (RW-16) I2C Control register 1 */
|
---|
417 | #define TOFF_I2C_CR2 0x0004 /* (RW-16) I2C Control register 2 */
|
---|
418 | #define TOFF_I2C_OAR1 0x0008 /* (RW-16) I2C Own address register 1 */
|
---|
419 | #define TOFF_I2C_OAR2 0x000C /* (RW-16) I2C Own address register 2 */
|
---|
420 | #define TOFF_I2C_DR 0x0010 /* (RW-16) I2C Data register */
|
---|
421 | #define TOFF_I2C_SR1 0x0014 /* (R-16) I2C Status register 1 */
|
---|
422 | #define TOFF_I2C_SR2 0x0018 /* (R-16) I2C Status register 2 */
|
---|
423 | #define TOFF_I2C_CCR 0x001C /* (RW-16) I2C Clock control register */
|
---|
424 | #define TOFF_I2C_TRISE 0x0020 /* (RW-16) I2C TRISE register */
|
---|
425 |
|
---|
426 | /*
|
---|
427 | * CONTROLLER AREA NETWORK
|
---|
428 | */
|
---|
429 | #define TADR_CAN1_BASE (APB1PERIPH_BASE + 0x6400)
|
---|
430 | #define TADR_CAN2_BASE (APB1PERIPH_BASE + 0x6800)
|
---|
431 | #define TOFF_CAN_MCR 0x0000 /* (RW) CAN master control register */
|
---|
432 | #define TOFF_CAN_MSR 0x0004 /* (R) CAN master status register */
|
---|
433 | #define TOFF_CAN_TSR 0x0008 /* (R) CAN transmit status register */
|
---|
434 | #define TOFF_CAN_RF0R 0x000C /* (RW) CAN receive FIFO 0 register */
|
---|
435 | #define TOFF_CAN_RF1R 0x0010 /* (RW) CAN receive FIFO 1 register */
|
---|
436 | #define TOFF_CAN_IER 0x0014 /* (RW) CAN interrupt enable register */
|
---|
437 | #define TOFF_CAN_ESR 0x0018 /* (RW) CAN error status register */
|
---|
438 | #define TOFF_CAN_BTR 0x001C /* (RW) CAN bit timing register */
|
---|
439 | /* CAN TX MailBox */
|
---|
440 | #define TOFF_CAN_TIR1 0x0180 /* (RW) CAN(1) TX mailbox identifier register */
|
---|
441 | #define TOFF_CAN_TDTR1 0x0184 /* (RW) CAN(1) mailbox data length control and time stamp register */
|
---|
442 | #define TOFF_CAN_TDLR1 0x0188 /* (RW) CAN(1) mailbox data low register */
|
---|
443 | #define TOFF_CAN_TDHR1 0x018C /* (RW) CAN(1) mailbox data high register */
|
---|
444 | #define TOFF_CAN_TIR2 0x0190 /* (RW) CAN(2) TX mailbox identifier register */
|
---|
445 | #define TOFF_CAN_TDTR2 0x0194 /* (RW) CAN(2) mailbox data length control and time stamp register */
|
---|
446 | #define TOFF_CAN_TDLR2 0x0198 /* (RW) CAN(2) mailbox data low register */
|
---|
447 | #define TOFF_CAN_TDHR2 0x019C /* (RW) CAN(2) mailbox data high register */
|
---|
448 | #define TOFF_CAN_TIR3 0x01A0 /* (RW) CAN(3) TX mailbox identifier register */
|
---|
449 | #define TOFF_CAN_TDTR3 0x01A4 /* (RW) CAN(3) mailbox data length control and time stamp register */
|
---|
450 | #define TOFF_CAN_TDLR3 0x01A8 /* (RW) CAN(3) mailbox data low register */
|
---|
451 | #define TOFF_CAN_TDHR3 0x01AC /* (RW) CAN(3) mailbox data high register */
|
---|
452 | /* CAN FIFO MailBox */
|
---|
453 | #define TOFF_CAN_RIR1 0x01B0 /* (RW) CAN(1) receive FIFO mailbox identifier register */
|
---|
454 | #define TOFF_CAN_RDTR1 0x01B4 /* (RW) CAN(1) receive FIFO mailbox data length control and time stamp register */
|
---|
455 | #define TOFF_CAN_RDLR1 0x01B8 /* (RW) CAN(1) receive FIFO mailbox data low register */
|
---|
456 | #define TOFF_CAN_RDHR1 0x01BC /* (RW) CAN(1) receive FIFO mailbox data high register */
|
---|
457 | #define TOFF_CAN_RIR2 0x01C0 /* (RW) CAN(2) receive FIFO mailbox identifier register */
|
---|
458 | #define TOFF_CAN_RDTR2 0x01C4 /* (RW) CAN(2) receive FIFO mailbox data length control and time stamp register */
|
---|
459 | #define TOFF_CAN_RDLR2 0x01C8 /* (RW) CAN(2) receive FIFO mailbox data low register */
|
---|
460 | #define TOFF_CAN_RDHR2 0x01CC /* (RW) CAN(2) receive FIFO mailbox data high register */
|
---|
461 | #define TOFF_CAN_FMR 0x0200 /* (RW) CAN filter master register */
|
---|
462 | #define TOFF_CAN_FM1R 0x0204 /* (RW) CAN filter mode register */
|
---|
463 | #define TOFF_CAN_FS1R 0x020C /* (RW) CAN filter scale register */
|
---|
464 | #define TOFF_CAN_FFA1R 0x0214 /* (RW) CAN filter FIFO assignment register */
|
---|
465 | #define TOFF_CAN_FA1R 0x0218 /* (RW) CAN filter activation register */
|
---|
466 | #define TOFF_CAN_FR_BASE 0x0240
|
---|
467 | #define TOFF_CAN_FR1 0x0240 /* (RW) CAN Filter bank register 1 */
|
---|
468 | #define TOFF_CAN_FR2 0x0244 /* (RW) CAN Filter bank register 1 */
|
---|
469 |
|
---|
470 | /*
|
---|
471 | * POWER CONTROL
|
---|
472 | */
|
---|
473 | #define TADR_PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
---|
474 | #define TOFF_PWR_CR 0x0000 /* (RW) PWR power control register */
|
---|
475 | #define PWR_CR_LPDS 0x00000001 /* Low-Power Deepsleep */
|
---|
476 | #define PWR_CR_PDDS 0x00000002 /* Power Down Deepsleep */
|
---|
477 | #define PWR_CR_CWUF 0x00000004 /* Clear Wakeup Flag */
|
---|
478 | #define PWR_CR_CSBF 0x00000008 /* Clear Standby Flag */
|
---|
479 | #define PWR_CR_PVDE 0x00000010 /* Power Voltage Detector Enable */
|
---|
480 | #define PWR_CR_PLS_0 0x00000020 /* Bit 0 */
|
---|
481 | #define PWR_CR_PLS_1 0x00000040 /* Bit 1 */
|
---|
482 | #define PWR_CR_PLS_2 0x00000080 /* Bit 2 */
|
---|
483 | #define PWR_CR_DBP 0x00000100 /* Disable Backup Domain write protection */
|
---|
484 | #define PWR_CR_FPDS 0x00000200 /* Flash power down in Stop mode */
|
---|
485 | #define PWR_CR_VOS 0x00004000 /* Regulator voltage scaling output selection */
|
---|
486 | #define PWR_CR_ODEN 0x00010000 /* Over Drive enable */
|
---|
487 | #define PWR_CR_ODSWEN 0x00020000 /* Over Drive switch enabled */
|
---|
488 | #define PWR_CR_UDEN_0 0x00040000 /* Under Drive enable in stop mode Bit 0 */
|
---|
489 | #define PWR_CR_UDEN_1 0x00080000 /* Under Drive enable in stop mode Bit 1 */
|
---|
490 | /* Legacy define */
|
---|
491 | #define PWR_CR_PMODE PWR_CR_VOS
|
---|
492 | #define TOFF_PWR_CSR 0x0004 /* (RW) PWR power control/status register */
|
---|
493 | #define PWR_CSR_WUF 0x00000001 /* Wakeup Flag */
|
---|
494 | #define PWR_CSR_SBF 0x00000002 /* Standby Flag */
|
---|
495 | #define PWR_CSR_PVDO 0x00000004 /* PVD Output */
|
---|
496 | #define PWR_CSR_BRR 0x00000008 /* Backup regulator ready */
|
---|
497 | #define PWR_CSR_EWUP 0x00000100 /* Enable WKUP pin */
|
---|
498 | #define PWR_CSR_BRE 0x00000200 /* Backup regulator enable */
|
---|
499 | #define PWR_CSR_VOSRDY 0x00004000 /* Regulator voltage scaling output selection ready */
|
---|
500 | #define PWR_CSR_ODRDY 0x00010000 /* Over Drive generator ready */
|
---|
501 | #define PWR_CSR_ODSWRDY 0x00020000 /* Over Drive Switch ready */
|
---|
502 | #define PWR_CSR_UDSWRDY 0x000C0000 /* Under Drive ready */
|
---|
503 | /* Legacy define */
|
---|
504 | #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
|
---|
505 |
|
---|
506 | /*
|
---|
507 | * DIGITAL TO ANALOG CONVTER
|
---|
508 | */
|
---|
509 | #define TADR_DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
---|
510 | #define TOFF_DAC_CR 0x0000 /* (RW) DAC control register */
|
---|
511 | #define TOFF_DAC_SWTRIGR 0x0004 /* (RW) DAC software trigger register */
|
---|
512 | #define TOFF_DAC_DHR12R1 0x0008 /* (RW) DAC channel1 12-bit right-aligned data holding register */
|
---|
513 | #define TOFF_DAC_DHR12L1 0x000C /* (RW) DAC channel1 12-bit left aligned data holding register */
|
---|
514 | #define TOFF_DAC_DHR8R1 0x0010 /* (RW) DAC channel1 8-bit right aligned data holding register */
|
---|
515 | #define TOFF_DAC_DHR12R2 0x0014 /* (RW) DAC channel2 12-bit right aligned data holding register */
|
---|
516 | #define TOFF_DAC_DHR12L2 0x0018 /* (RW) DAC channel2 12-bit left aligned data holding register */
|
---|
517 | #define TOFF_DAC_DHR8R2 0x001C /* (RW) DAC channel2 8-bit right-aligned data holding register */
|
---|
518 | #define TOFF_DAC_DHR12RD 0x0020 /* (RW) Dual DAC 12-bit right-aligned data holding register */
|
---|
519 | #define TOFF_DAC_DHR12LD 0x0024 /* (RW) DUAL DAC 12-bit left aligned data holding register */
|
---|
520 | #define TOFF_DAC_DHR8RD 0x0028 /* (RW) DUAL DAC 8-bit right aligned data holding register */
|
---|
521 | #define TOFF_DAC_DOR1 0x002C /* (RW) DAC channel1 data output register */
|
---|
522 | #define TOFF_DAC_DOR2 0x0030 /* (RW) DAC channel2 data output register */
|
---|
523 | #define TOFF_DAC_SR 0x0034 /* (RW) DAC status register */
|
---|
524 |
|
---|
525 |
|
---|
526 | /*
|
---|
527 | * ANALOG TO DIGITAL CONVERTER
|
---|
528 | */
|
---|
529 | #define TADR_ADC1_BASE (APB2PERIPH_BASE + 0x2000)
|
---|
530 | #define TADR_ADC2_BASE (APB2PERIPH_BASE + 0x2100)
|
---|
531 | #define TADR_ADC3_BASE (APB2PERIPH_BASE + 0x2200)
|
---|
532 | #define TOFF_ADC_SR 0x0000 /* (RW) ADC status register */
|
---|
533 | #define TOFF_ADC_CR1 0x0004 /* (RW) ADC control register 1 */
|
---|
534 | #define TOFF_ADC_CR2 0x0008 /* (RW) ADC control register 2 */
|
---|
535 | #define TOFF_ADC_SMPR1 0x000C /* (RW) ADC sample time register 1 */
|
---|
536 | #define TOFF_ADC_SMPR2 0x0010 /* (RW) ADC sample time register 2 */
|
---|
537 | #define TOFF_ADC_JOFR1 0x0014 /* (RW) ADC injected channel data offset register 1 */
|
---|
538 | #define TOFF_ADC_JOFR2 0x0018 /* (RW) ADC injected channel data offset register 2 */
|
---|
539 | #define TOFF_ADC_JOFR3 0x001C /* (RW) ADC injected channel data offset register 3 */
|
---|
540 | #define TOFF_ADC_JOFR4 0x0020 /* (RW) ADC injected channel data offset register 4 */
|
---|
541 | #define TOFF_ADC_HTR 0x0024 /* (RW) ADC watchdog higher threshold register */
|
---|
542 | #define TOFF_ADC_LTR 0x0028 /* (RW) ADC watchdog lower threshold register */
|
---|
543 | #define TOFF_ADC_SQR1 0x002C /* (RW) ADC regular sequence register 1 */
|
---|
544 | #define TOFF_ADC_SQR2 0x0030 /* (RW) ADC regular sequence register 2 */
|
---|
545 | #define TOFF_ADC_SQR3 0x0034 /* (RW) ADC regular sequence register 3 */
|
---|
546 | #define TOFF_ADC_JSQR 0x0038 /* (RW) ADC injected sequence register */
|
---|
547 | #define TOFF_ADC_JDR1 0x003C /* (RW) ADC injected data register 1 */
|
---|
548 | #define TOFF_ADC_JDR2 0x0040 /* (RW) ADC injected data register 2 */
|
---|
549 | #define TOFF_ADC_JDR3 0x0044 /* (RW) ADC injected data register 3 */
|
---|
550 | #define TOFF_ADC_JDR4 0x0048 /* (RW) ADC injected data register 4 */
|
---|
551 | #define TOFF_ADC_DR 0x004C /* (RW) ADC regular data register */
|
---|
552 |
|
---|
553 | #define TADR_ADC_BASE (APB2PERIPH_BASE + 0x2300)
|
---|
554 | #define TOFF_ADC_CSR 0x0000 /* (RW) ADC Common status register */
|
---|
555 | #define TOFF_ADC_CCR 0x0004 /* (RW) ADC common control register */
|
---|
556 | #define TOFF_ADC_CDR 0x0008 /* (RW) ADC common regular data register for dual AND triple modes */
|
---|
557 |
|
---|
558 | /*
|
---|
559 | * SD HOST INTERFACE
|
---|
560 | */
|
---|
561 | #define TADR_SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
|
---|
562 | #define TOFF_SDIO_POWER 0x0000 /* (RW) SDIO power control register */
|
---|
563 | #define TOFF_SDIO_CLKCR 0x0004 /* (RW) SDI clock control register */
|
---|
564 | #define TOFF_SDIO_ARG 0x0008 /* (RW) SDIO argument register */
|
---|
565 | #define TOFF_SDIO_CMD 0x000C /* (RW) SDIO command register */
|
---|
566 | #define TOFF_SDIO_RESPCMD 0x0018 /* (R) SDIO command response register */
|
---|
567 | #define TOFF_SDIO_RESP 0x0014 /* (R) SDIO response 1 register */
|
---|
568 | #define TOFF_SDIO_RESP2 0x0018 /* (R) SDIO response 2 register */
|
---|
569 | #define TOFF_SDIO_RESP3 0x001C /* (R) SDIO response 3 register */
|
---|
570 | #define TOFF_SDIO_RESP4 0x0020 /* (R) SDIO response 4 register */
|
---|
571 | #define TOFF_SDIO_DTIMER 0x0024 /* (RW) SDIO data timer register */
|
---|
572 | #define TOFF_SDIO_DLEN 0x0028 /* (RW) SDIO data length register */
|
---|
573 | #define TOFF_SDIO_DCTRL 0x002C /* (RW) SDIO data control register */
|
---|
574 | #define TOFF_SDIO_DCOUNT 0x0030 /* (R) SDIO data counter register */
|
---|
575 | #define TOFF_SDIO_STA 0x0034 /* (R) SDIO status register */
|
---|
576 | #define TOFF_SDIO_ICR 0x0038 /* (RW) SDIO interrupt clear register */
|
---|
577 | #define TOFF_SDIO_MASK 0x003C /* (RW) SDIO mask register */
|
---|
578 | #define TOFF_SDIO_FIFOCNT 0x0048 /* (R) SDIO FIFO counter register */
|
---|
579 | #define TOFF_SDIO_FIFO 0x0080 /* (RW) SDIO data FIFO register */
|
---|
580 |
|
---|
581 | /*
|
---|
582 | * SYSTEM CONFIGURATION CONTROLLER
|
---|
583 | */
|
---|
584 | #define TADR_SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
|
---|
585 | #define TOFF_SYSCFG_MEMRMP 0x0000 /* (RW) SYSCFG memory remap register */
|
---|
586 | #define TOFF_SYSCFG_PMC 0x0004 /* (RW) SYSCFG peripheral mode configuration register */
|
---|
587 | #define TOFF_SYSCFG_EXTICR0 0x0008 /* (RW) SYSCFG external interrupt configuration registers 0 */
|
---|
588 | #define TOFF_SYSCFG_EXTICR1 0x000C /* (RW) SYSCFG external interrupt configuration registers 1 */
|
---|
589 | #define TOFF_SYSCFG_EXTICR2 0x0010 /* (RW) SYSCFG external interrupt configuration registers 2 */
|
---|
590 | #define TOFF_SYSCFG_EXTICR3 0x0014 /* (RW) SYSCFG external interrupt configuration registers 3 */
|
---|
591 | #define TOFF_SYSCFG_CMPCR 0x0020 /* (RW) SYSCFG Compensation cell control register */
|
---|
592 |
|
---|
593 | /*
|
---|
594 | * EXTERNAL INTERRUPT/EVENT CONTROLLER
|
---|
595 | */
|
---|
596 | #define TADR_EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
|
---|
597 | #define TOFF_EXTI_IMR 0x0000 /* (RW) EXTI Interrupt mask register */
|
---|
598 | #define TOFF_EXTI_EMR 0x0004 /* (RW) EXTI Event mask register */
|
---|
599 | #define TOFF_EXTI_RTSR 0x0008 /* (RW) EXTI Rising trigger selection register */
|
---|
600 | #define TOFF_EXTI_FTSR 0x000C /* (RW) EXTI Falling trigger selection register */
|
---|
601 | #define TOFF_EXTI_SWIER 0x0010 /* (RW) EXTI Software interrupt event register */
|
---|
602 | #define TOFF_EXTI_PR 0x0014 /* (RW) EXTI Pending register */
|
---|
603 |
|
---|
604 | /*
|
---|
605 | * GENERAL PURPOSE I/O
|
---|
606 | */
|
---|
607 | #define TADR_GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
|
---|
608 | #define TADR_GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
|
---|
609 | #define TADR_GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
|
---|
610 | #define TADR_GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
|
---|
611 | #define TADR_GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
|
---|
612 | #define TADR_GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
|
---|
613 | #define TADR_GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
|
---|
614 | #define TADR_GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
|
---|
615 | #define TADR_GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
|
---|
616 | #define TOFF_GPIO_MODER 0x0000 /* (RW) GPIO port mode register */
|
---|
617 | #define GPIO_MODER_MODER0 0x1
|
---|
618 | #define GPIO_MODER_MODER1 0x2
|
---|
619 | #define GPIO_MODER_MODER2 0x3
|
---|
620 | #define TOFF_GPIO_OTYPER 0x0004 /* (RW) GPIO port output type register */
|
---|
621 | #define GPIO_OTYPER_OT 0x1
|
---|
622 | #define TOFF_GPIO_OSPEEDR 0x0008 /* (RW) GPIO port output speed register */
|
---|
623 | #define GPIO_OSPEEDER_OSPEEDR0 0x1
|
---|
624 | #define GPIO_OSPEEDER_OSPEEDR1 0x2
|
---|
625 | #define GPIO_OSPEEDER_OSPEEDR2 0x3
|
---|
626 | #define TOFF_GPIO_PUPDR 0x000C /* (RW) GPIO port pull-up/pull-down register */
|
---|
627 | #define GPIO_PUPDR_PUPDR0 0x1
|
---|
628 | #define GPIO_PUPDR_PUPDR1 0x2
|
---|
629 | #define GPIO_PUPDR_PUPDR2 0x3
|
---|
630 | #define TOFF_GPIO_IDR 0x0010 /* (R) GPIO port input data register */
|
---|
631 | #define TOFF_GPIO_ODR 0x0014 /* (RW) GPIO port output data register */
|
---|
632 | #define TOFF_GPIO_BSRRL 0x0018 /* (RW-16) GPIO port bit set/reset low register */
|
---|
633 | #define TOFF_GPIO_BSRRH 0x001A /* (RW-16) GPIO port bit set/reset high register */
|
---|
634 | #define TOFF_GPIO_LCKR 0x001C /* (RW) GPIO port configuration lock register */
|
---|
635 | #define TOFF_GPIO_AFR0 0x0020 /* (RW) GPIO alternate function registers */
|
---|
636 | #define TOFF_GPIO_AFR1 0x0024 /* (RW) GPIO alternate function registers */
|
---|
637 |
|
---|
638 | /*
|
---|
639 | * CRC CALCULATION UNIT
|
---|
640 | */
|
---|
641 | #define TADR_CRC_BASE (AHB1PERIPH_BASE + 0x3000)
|
---|
642 | #define TOFF_CRC_DR 0x0000 /* (RW) CRC Data register */
|
---|
643 | #define TOFF_CRC_IDR 0x0004 /* (RW-8) CRC Independent data register */
|
---|
644 | #define TOFF_CRC_CR 0x0008 /* (RW) CRC Control register */
|
---|
645 |
|
---|
646 | /*
|
---|
647 | * RESET AND CLOCK CONTROL
|
---|
648 | */
|
---|
649 | #define TADR_RCC_BASE (AHB1PERIPH_BASE + 0x3800)
|
---|
650 | #define TOFF_RCC_CR 0x0000 /* (RW) RCC clock control register */
|
---|
651 | #define RCC_CR_HSION 0x00000001
|
---|
652 | #define RCC_CR_HSIRDY 0x00000002
|
---|
653 | #define RCC_CR_HSITRIM_0 0x00000008 /* Bit 0 */
|
---|
654 | #define RCC_CR_HSITRIM_1 0x00000010 /* Bit 1 */
|
---|
655 | #define RCC_CR_HSITRIM_2 0x00000020 /* Bit 2 */
|
---|
656 | #define RCC_CR_HSITRIM_3 0x00000040 /* Bit 3 */
|
---|
657 | #define RCC_CR_HSITRIM_4 0x00000080 /* Bit 4 */
|
---|
658 | #define RCC_CR_HSICAL_0 0x00000100 /* Bit 0 */
|
---|
659 | #define RCC_CR_HSICAL_1 0x00000200 /* Bit 1 */
|
---|
660 | #define RCC_CR_HSICAL_2 0x00000400 /* Bit 2 */
|
---|
661 | #define RCC_CR_HSICAL_3 0x00000800 /* Bit 3 */
|
---|
662 | #define RCC_CR_HSICAL_4 0x00001000 /* Bit 4 */
|
---|
663 | #define RCC_CR_HSICAL_5 0x00002000 /* Bit 5 */
|
---|
664 | #define RCC_CR_HSICAL_6 0x00004000 /* Bit 6 */
|
---|
665 | #define RCC_CR_HSICAL_7 0x00008000 /* Bit 7 */
|
---|
666 | #define RCC_CR_HSEON 0x00010000
|
---|
667 | #define RCC_CR_HSERDY 0x00020000
|
---|
668 | #define RCC_CR_HSEBYP 0x00040000
|
---|
669 | #define RCC_CR_CSSON 0x00080000
|
---|
670 | #define RCC_CR_PLLON 0x01000000
|
---|
671 | #define RCC_CR_PLLRDY 0x02000000
|
---|
672 | #define RCC_CR_PLLI2SON 0x04000000
|
---|
673 | #define RCC_CR_PLLI2SRDY 0x08000000
|
---|
674 | #define TOFF_RCC_PLLCFGR 0x0004 /* (RW) RCC PLL configuration register */
|
---|
675 | #define RCC_PLLCFGR_PLLM_0 0x00000001
|
---|
676 | #define RCC_PLLCFGR_PLLM_1 0x00000002
|
---|
677 | #define RCC_PLLCFGR_PLLM_2 0x00000004
|
---|
678 | #define RCC_PLLCFGR_PLLM_3 0x00000008
|
---|
679 | #define RCC_PLLCFGR_PLLM_4 0x00000010
|
---|
680 | #define RCC_PLLCFGR_PLLM_5 0x00000020
|
---|
681 | #define RCC_PLLCFGR_PLLN_0 0x00000040
|
---|
682 | #define RCC_PLLCFGR_PLLN_1 0x00000080
|
---|
683 | #define RCC_PLLCFGR_PLLN_2 0x00000100
|
---|
684 | #define RCC_PLLCFGR_PLLN_3 0x00000200
|
---|
685 | #define RCC_PLLCFGR_PLLN_4 0x00000400
|
---|
686 | #define RCC_PLLCFGR_PLLN_5 0x00000800
|
---|
687 | #define RCC_PLLCFGR_PLLN_6 0x00001000
|
---|
688 | #define RCC_PLLCFGR_PLLN_7 0x00002000
|
---|
689 | #define RCC_PLLCFGR_PLLN_8 0x00004000
|
---|
690 | #define RCC_PLLCFGR_PLLP_0 0x00010000
|
---|
691 | #define RCC_PLLCFGR_PLLP_1 0x00020000
|
---|
692 | #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000
|
---|
693 | #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000
|
---|
694 | #define RCC_PLLCFGR_PLLQ_0 0x01000000
|
---|
695 | #define RCC_PLLCFGR_PLLQ_1 0x02000000
|
---|
696 | #define RCC_PLLCFGR_PLLQ_2 0x04000000
|
---|
697 | #define RCC_PLLCFGR_PLLQ_3 0x08000000
|
---|
698 | #define TOFF_RCC_CFGR 0x0008 /* (RW) RCC clock configuration register */
|
---|
699 | #define RCC_CFGR_SW_0 0x00000001 /* Bit 0 */
|
---|
700 | #define RCC_CFGR_SW_1 0x00000002 /* Bit 1 */
|
---|
701 | #define RCC_CFGR_SW_HSI 0x00000000 /* HSI selected as system clock */
|
---|
702 | #define RCC_CFGR_SW_HSE 0x00000001 /* HSE selected as system clock */
|
---|
703 | #define RCC_CFGR_SW_PLL 0x00000002 /* PLL selected as system clock */
|
---|
704 | #define RCC_CFGR_SWS_0 0x00000004 /* Bit 0 */
|
---|
705 | #define RCC_CFGR_SWS_1 0x00000008 /* Bit 1 */
|
---|
706 | #define RCC_CFGR_SWS_HSI 0x00000000 /* HSI oscillator used as system clock */
|
---|
707 | #define RCC_CFGR_SWS_HSE 0x00000004 /* HSE oscillator used as system clock */
|
---|
708 | #define RCC_CFGR_SWS_PLL 0x00000008 /* PLL used as system clock */
|
---|
709 | #define RCC_CFGR_HPRE_0 0x00000010 /* Bit 0 */
|
---|
710 | #define RCC_CFGR_HPRE_1 0x00000020 /* Bit 1 */
|
---|
711 | #define RCC_CFGR_HPRE_2 0x00000040 /* Bit 2 */
|
---|
712 | #define RCC_CFGR_HPRE_3 0x00000080 /* Bit 3 */
|
---|
713 | #define RCC_CFGR_HPRE_DIV1 0x00000000 /* SYSCLK not divided */
|
---|
714 | #define RCC_CFGR_HPRE_DIV2 0x00000080 /* SYSCLK divided by 2 */
|
---|
715 | #define RCC_CFGR_HPRE_DIV4 0x00000090 /* SYSCLK divided by 4 */
|
---|
716 | #define RCC_CFGR_HPRE_DIV8 0x000000A0 /* SYSCLK divided by 8 */
|
---|
717 | #define RCC_CFGR_HPRE_DIV16 0x000000B0 /* SYSCLK divided by 16 */
|
---|
718 | #define RCC_CFGR_HPRE_DIV64 0x000000C0 /* SYSCLK divided by 64 */
|
---|
719 | #define RCC_CFGR_HPRE_DIV128 0x000000D0 /* SYSCLK divided by 128 */
|
---|
720 | #define RCC_CFGR_HPRE_DIV256 0x000000E0 /* SYSCLK divided by 256 */
|
---|
721 | #define RCC_CFGR_HPRE_DIV512 0x000000F0 /* SYSCLK divided by 512 */
|
---|
722 | #define RCC_CFGR_PPRE1_0 0x00000400 /* Bit 0 */
|
---|
723 | #define RCC_CFGR_PPRE1_1 0x00000800 /* Bit 1 */
|
---|
724 | #define RCC_CFGR_PPRE1_2 0x00001000 /* Bit 2 */
|
---|
725 | #define RCC_CFGR_PPRE1_DIV1 0x00000000 /* HCLK not divided */
|
---|
726 | #define RCC_CFGR_PPRE1_DIV2 0x00001000 /* HCLK divided by 2 */
|
---|
727 | #define RCC_CFGR_PPRE1_DIV4 0x00001400 /* HCLK divided by 4 */
|
---|
728 | #define RCC_CFGR_PPRE1_DIV8 0x00001800 /* HCLK divided by 8 */
|
---|
729 | #define RCC_CFGR_PPRE1_DIV16 0x00001C00 /* HCLK divided by 16 */
|
---|
730 | #define RCC_CFGR_PPRE2_0 0x00002000 /* Bit 0 */
|
---|
731 | #define RCC_CFGR_PPRE2_1 0x00004000 /* Bit 1 */
|
---|
732 | #define RCC_CFGR_PPRE2_2 0x00008000 /* Bit 2 */
|
---|
733 | #define RCC_CFGR_PPRE2_DIV1 0x00000000 /* HCLK not divided */
|
---|
734 | #define RCC_CFGR_PPRE2_DIV2 0x00008000 /* HCLK divided by 2 */
|
---|
735 | #define RCC_CFGR_PPRE2_DIV4 0x0000A000 /* HCLK divided by 4 */
|
---|
736 | #define RCC_CFGR_PPRE2_DIV8 0x0000C000 /* HCLK divided by 8 */
|
---|
737 | #define RCC_CFGR_PPRE2_DIV16 0x0000E000 /* HCLK divided by 16 */
|
---|
738 | #define RCC_CFGR_RTCPRE_0 0x00010000
|
---|
739 | #define RCC_CFGR_RTCPRE_1 0x00020000
|
---|
740 | #define RCC_CFGR_RTCPRE_2 0x00040000
|
---|
741 | #define RCC_CFGR_RTCPRE_3 0x00080000
|
---|
742 | #define RCC_CFGR_RTCPRE_4 0x00100000
|
---|
743 | #define RCC_CFGR_MCO1_0 0x00200000
|
---|
744 | #define RCC_CFGR_MCO1_1 0x00400000
|
---|
745 | #define RCC_CFGR_I2SSRC 0x00800000
|
---|
746 | #define RCC_CFGR_MCO1PRE_0 0x01000000
|
---|
747 | #define RCC_CFGR_MCO1PRE_1 0x02000000
|
---|
748 | #define RCC_CFGR_MCO1PRE_2 0x04000000
|
---|
749 | #define RCC_CFGR_MCO2PRE_0 0x08000000
|
---|
750 | #define RCC_CFGR_MCO2PRE_1 0x10000000
|
---|
751 | #define RCC_CFGR_MCO2PRE_2 0x20000000
|
---|
752 | #define RCC_CFGR_MCO2_0 0x40000000
|
---|
753 | #define RCC_CFGR_MCO2_1 0x80000000
|
---|
754 | #define TOFF_RCC_CIR 0x000C /* (RW) RCC clock interrupt register */
|
---|
755 | #define RCC_CIR_LSIRDYF 0x00000001
|
---|
756 | #define RCC_CIR_LSERDYF 0x00000002
|
---|
757 | #define RCC_CIR_HSIRDYF 0x00000004
|
---|
758 | #define RCC_CIR_HSERDYF 0x00000008
|
---|
759 | #define RCC_CIR_PLLRDYF 0x00000010
|
---|
760 | #define RCC_CIR_PLLI2SRDYF 0x00000020
|
---|
761 | #define RCC_CIR_CSSF 0x00000080
|
---|
762 | #define RCC_CIR_LSIRDYIE 0x00000100
|
---|
763 | #define RCC_CIR_LSERDYIE 0x00000200
|
---|
764 | #define RCC_CIR_HSIRDYIE 0x00000400
|
---|
765 | #define RCC_CIR_HSERDYIE 0x00000800
|
---|
766 | #define RCC_CIR_PLLRDYIE 0x00001000
|
---|
767 | #define RCC_CIR_PLLI2SRDYIE 0x00002000
|
---|
768 | #define RCC_CIR_LSIRDYC 0x00010000
|
---|
769 | #define RCC_CIR_LSERDYC 0x00020000
|
---|
770 | #define RCC_CIR_HSIRDYC 0x00040000
|
---|
771 | #define RCC_CIR_HSERDYC 0x00080000
|
---|
772 | #define RCC_CIR_PLLRDYC 0x00100000
|
---|
773 | #define RCC_CIR_PLLI2SRDYC 0x00200000
|
---|
774 | #define RCC_CIR_CSSC 0x00800000
|
---|
775 | #define TOFF_RCC_AHB1RSTR 0x0010 /* (RW) RCC AHB1 peripheral reset register */
|
---|
776 | #define RCC_AHB1RSTR_GPIOARST 0x00000001
|
---|
777 | #define RCC_AHB1RSTR_GPIOBRST 0x00000002
|
---|
778 | #define RCC_AHB1RSTR_GPIOCRST 0x00000004
|
---|
779 | #define RCC_AHB1RSTR_GPIODRST 0x00000008
|
---|
780 | #define RCC_AHB1RSTR_GPIOERST 0x00000010
|
---|
781 | #define RCC_AHB1RSTR_GPIOFRST 0x00000020
|
---|
782 | #define RCC_AHB1RSTR_GPIOGRST 0x00000040
|
---|
783 | #define RCC_AHB1RSTR_GPIOHRST 0x00000080
|
---|
784 | #define RCC_AHB1RSTR_GPIOIRST 0x00000100
|
---|
785 | #define RCC_AHB1RSTR_CRCRST 0x00001000
|
---|
786 | #define RCC_AHB1RSTR_DMA1RST 0x00200000
|
---|
787 | #define RCC_AHB1RSTR_DMA2RST 0x00400000
|
---|
788 | #define RCC_AHB1RSTR_ETHMACRST 0x02000000
|
---|
789 | #define RCC_AHB1RSTR_OTGHRST 0x10000000
|
---|
790 | #define TOFF_RCC_AHB2RSTR 0x0014 /* (RW) RCC AHB2 peripheral reset register */
|
---|
791 | #define RCC_AHB2RSTR_DCMIRST 0x00000001
|
---|
792 | #define RCC_AHB2RSTR_CRYPRST 0x00000010
|
---|
793 | #define RCC_AHB2RSTR_HSAHRST 0x00000020
|
---|
794 | #define RCC_AHB2RSTR_RNGRST 0x00000040
|
---|
795 | #define RCC_AHB2RSTR_OTGFSRST 0x00000080
|
---|
796 | #define TOFF_RCC_AHB3RSTR 0x0018 /* (RW) RCC AHB3 peripheral reset register */
|
---|
797 | #define RCC_AHB3RSTR_FSMCRST 0x00000001
|
---|
798 | #define TOFF_RCC_APB1RSTR 0x0020 /* (RW) RCC APB1 peripheral reset register */
|
---|
799 | #define RCC_APB1RSTR_TIM2RST 0x00000001
|
---|
800 | #define RCC_APB1RSTR_TIM3RST 0x00000002
|
---|
801 | #define RCC_APB1RSTR_TIM4RST 0x00000004
|
---|
802 | #define RCC_APB1RSTR_TIM5RST 0x00000008
|
---|
803 | #define RCC_APB1RSTR_TIM6RST 0x00000010
|
---|
804 | #define RCC_APB1RSTR_TIM7RST 0x00000020
|
---|
805 | #define RCC_APB1RSTR_TIM12RST 0x00000040
|
---|
806 | #define RCC_APB1RSTR_TIM13RST 0x00000080
|
---|
807 | #define RCC_APB1RSTR_TIM14RST 0x00000100
|
---|
808 | #define RCC_APB1RSTR_WWDGEN 0x00000800
|
---|
809 | #define RCC_APB1RSTR_SPI2RST 0x00008000
|
---|
810 | #define RCC_APB1RSTR_SPI3RST 0x00010000
|
---|
811 | #define RCC_APB1RSTR_USART2RST 0x00020000
|
---|
812 | #define RCC_APB1RSTR_USART3RST 0x00040000
|
---|
813 | #define RCC_APB1RSTR_UART4RST 0x00080000
|
---|
814 | #define RCC_APB1RSTR_UART5RST 0x00100000
|
---|
815 | #define RCC_APB1RSTR_I2C1RST 0x00200000
|
---|
816 | #define RCC_APB1RSTR_I2C2RST 0x00400000
|
---|
817 | #define RCC_APB1RSTR_I2C3RST 0x00800000
|
---|
818 | #define RCC_APB1RSTR_CAN1RST 0x02000000
|
---|
819 | #define RCC_APB1RSTR_CAN2RST 0x04000000
|
---|
820 | #define RCC_APB1RSTR_PWRRST 0x10000000
|
---|
821 | #define RCC_APB1RSTR_DACRST 0x20000000
|
---|
822 | #define TOFF_RCC_APB2RSTR 0x0024 /* (RW) RCC APB2 peripheral reset register */
|
---|
823 | #define RCC_APB2RSTR_TIM1RST 0x00000001
|
---|
824 | #define RCC_APB2RSTR_TIM8RST 0x00000002
|
---|
825 | #define RCC_APB2RSTR_USART1RST 0x00000010
|
---|
826 | #define RCC_APB2RSTR_USART6RST 0x00000020
|
---|
827 | #define RCC_APB2RSTR_ADCRST 0x00000100
|
---|
828 | #define RCC_APB2RSTR_SDIORST 0x00000800
|
---|
829 | #define RCC_APB2RSTR_SPI1RST 0x00001000
|
---|
830 | #define RCC_APB2RSTR_SYSCFGRST 0x00004000
|
---|
831 | #define RCC_APB2RSTR_TIM9RST 0x00010000
|
---|
832 | #define RCC_APB2RSTR_TIM10RST 0x00020000
|
---|
833 | #define RCC_APB2RSTR_TIM11RST 0x00040000
|
---|
834 | /* Old SPI1RST bit definition, maintained for legacy purpose */
|
---|
835 | #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
|
---|
836 | #define TOFF_RCC_AHB1ENR 0x0030 /* (RW) RCC AHB1 peripheral clock register */
|
---|
837 | #define RCC_AHB1ENR_GPIOAEN 0x00000001
|
---|
838 | #define RCC_AHB1ENR_GPIOBEN 0x00000002
|
---|
839 | #define RCC_AHB1ENR_GPIOCEN 0x00000004
|
---|
840 | #define RCC_AHB1ENR_GPIODEN 0x00000008
|
---|
841 | #define RCC_AHB1ENR_GPIOEEN 0x00000010
|
---|
842 | #define RCC_AHB1ENR_GPIOFEN 0x00000020
|
---|
843 | #define RCC_AHB1ENR_GPIOGEN 0x00000040
|
---|
844 | #define RCC_AHB1ENR_GPIOHEN 0x00000080
|
---|
845 | #define RCC_AHB1ENR_GPIOIEN 0x00000100
|
---|
846 | #define RCC_AHB1ENR_CRCEN 0x00001000
|
---|
847 | #define RCC_AHB1ENR_BKPSRAMEN 0x00040000
|
---|
848 | #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000
|
---|
849 | #define RCC_AHB1ENR_DMA1EN 0x00200000
|
---|
850 | #define RCC_AHB1ENR_DMA2EN 0x00400000
|
---|
851 | #define RCC_AHB1ENR_ETHMACEN 0x02000000
|
---|
852 | #define RCC_AHB1ENR_ETHMACTXEN 0x04000000
|
---|
853 | #define RCC_AHB1ENR_ETHMACRXEN 0x08000000
|
---|
854 | #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000
|
---|
855 | #define RCC_AHB1ENR_OTGHSEN 0x20000000
|
---|
856 | #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000
|
---|
857 | #define TOFF_RCC_AHB2ENR 0x0034 /* (RW) RCC AHB2 peripheral clock register */
|
---|
858 | #define RCC_AHB2ENR_DCMIEN 0x00000001
|
---|
859 | #define RCC_AHB2ENR_CRYPEN 0x00000010
|
---|
860 | #define RCC_AHB2ENR_HASHEN 0x00000020
|
---|
861 | #define RCC_AHB2ENR_RNGEN 0x00000040
|
---|
862 | #define RCC_AHB2ENR_OTGFSEN 0x00000080
|
---|
863 | #define TOFF_RCC_AHB3ENR 0x0038 /* (RW) RCC AHB3 peripheral clock register */
|
---|
864 | #define RCC_AHB3ENR_FSMCEN 0x00000001
|
---|
865 | #define TOFF_RCC_APB1ENR 0x0040 /* (RW) RCC APB1 peripheral clock enable register */
|
---|
866 | #define RCC_APB1ENR_TIM2EN 0x00000001
|
---|
867 | #define RCC_APB1ENR_TIM3EN 0x00000002
|
---|
868 | #define RCC_APB1ENR_TIM4EN 0x00000004
|
---|
869 | #define RCC_APB1ENR_TIM5EN 0x00000008
|
---|
870 | #define RCC_APB1ENR_TIM6EN 0x00000010
|
---|
871 | #define RCC_APB1ENR_TIM7EN 0x00000020
|
---|
872 | #define RCC_APB1ENR_TIM12EN 0x00000040
|
---|
873 | #define RCC_APB1ENR_TIM13EN 0x00000080
|
---|
874 | #define RCC_APB1ENR_TIM14EN 0x00000100
|
---|
875 | #define RCC_APB1ENR_WWDGEN 0x00000800
|
---|
876 | #define RCC_APB1ENR_SPI2EN 0x00004000
|
---|
877 | #define RCC_APB1ENR_SPI3EN 0x00008000
|
---|
878 | #define RCC_APB1ENR_USART2EN 0x00020000
|
---|
879 | #define RCC_APB1ENR_USART3EN 0x00040000
|
---|
880 | #define RCC_APB1ENR_UART4EN 0x00080000
|
---|
881 | #define RCC_APB1ENR_UART5EN 0x00100000
|
---|
882 | #define RCC_APB1ENR_I2C1EN 0x00200000
|
---|
883 | #define RCC_APB1ENR_I2C2EN 0x00400000
|
---|
884 | #define RCC_APB1ENR_I2C3EN 0x00800000
|
---|
885 | #define RCC_APB1ENR_CAN1EN 0x02000000
|
---|
886 | #define RCC_APB1ENR_CAN2EN 0x04000000
|
---|
887 | #define RCC_APB1ENR_PWREN 0x10000000
|
---|
888 | #define RCC_APB1ENR_DACEN 0x20000000
|
---|
889 | #define TOFF_RCC_APB2ENR 0x0044 /* (RW) RCC APB2 peripheral clock enable register */
|
---|
890 | #define RCC_APB2ENR_TIM1EN 0x00000001
|
---|
891 | #define RCC_APB2ENR_TIM8EN 0x00000002
|
---|
892 | #define RCC_APB2ENR_USART1EN 0x00000010
|
---|
893 | #define RCC_APB2ENR_USART6EN 0x00000020
|
---|
894 | #define RCC_APB2ENR_ADC1EN 0x00000100
|
---|
895 | #define RCC_APB2ENR_ADC2EN 0x00000200
|
---|
896 | #define RCC_APB2ENR_ADC3EN 0x00000400
|
---|
897 | #define RCC_APB2ENR_SDIOEN 0x00000800
|
---|
898 | #define RCC_APB2ENR_SPI1EN 0x00001000
|
---|
899 | #define RCC_APB2ENR_SYSCFGEN 0x00004000
|
---|
900 | #define RCC_APB2ENR_TIM11EN 0x00040000
|
---|
901 | #define RCC_APB2ENR_TIM10EN 0x00020000
|
---|
902 | #define RCC_APB2ENR_TIM9EN 0x00010000
|
---|
903 | #define TOFF_RCC_AHB1LPENR 0x0050 /* (RW) RCC AHB1 peripheral clock enable in low power mode register */
|
---|
904 | #define RCC_AHB1LPENR_GPIOALPEN 0x00000001
|
---|
905 | #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002
|
---|
906 | #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004
|
---|
907 | #define RCC_AHB1LPENR_GPIODLPEN 0x00000008
|
---|
908 | #define RCC_AHB1LPENR_GPIOELPEN 0x00000010
|
---|
909 | #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020
|
---|
910 | #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040
|
---|
911 | #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080
|
---|
912 | #define RCC_AHB1LPENR_GPIOILPEN 0x00000100
|
---|
913 | #define RCC_AHB1LPENR_CRCLPEN 0x00001000
|
---|
914 | #define RCC_AHB1LPENR_FLITFLPEN 0x00008000
|
---|
915 | #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000
|
---|
916 | #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000
|
---|
917 | #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000
|
---|
918 | #define RCC_AHB1LPENR_DMA1LPEN 0x00200000
|
---|
919 | #define RCC_AHB1LPENR_DMA2LPEN 0x00400000
|
---|
920 | #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000
|
---|
921 | #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000
|
---|
922 | #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000
|
---|
923 | #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000
|
---|
924 | #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000
|
---|
925 | #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000
|
---|
926 | #define TOFF_RCC_AHB2LPENR 0x0054 /* (RW) RCC AHB2 peripheral clock enable in low power mode register */
|
---|
927 | #define RCC_AHB2LPENR_DCMILPEN 0x00000001
|
---|
928 | #define RCC_AHB2LPENR_CRYPLPEN 0x00000010
|
---|
929 | #define RCC_AHB2LPENR_HASHLPEN 0x00000020
|
---|
930 | #define RCC_AHB2LPENR_RNGLPEN 0x00000040
|
---|
931 | #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080
|
---|
932 | #define TOFF_RCC_AHB3LPENR 0x0058 /* (RW) RCC AHB3 peripheral clock enable in low power mode register */
|
---|
933 | #define RCC_AHB3LPENR_FSMCLPEN 0x00000001
|
---|
934 | #define TOFF_RCC_APB1LPENR 0x0060 /* (RW) RCC APB1 peripheral clock enable in low power mode register */
|
---|
935 | #define RCC_APB1LPENR_TIM2LPEN 0x00000001
|
---|
936 | #define RCC_APB1LPENR_TIM3LPEN 0x00000002
|
---|
937 | #define RCC_APB1LPENR_TIM4LPEN 0x00000004
|
---|
938 | #define RCC_APB1LPENR_TIM5LPEN 0x00000008
|
---|
939 | #define RCC_APB1LPENR_TIM6LPEN 0x00000010
|
---|
940 | #define RCC_APB1LPENR_TIM7LPEN 0x00000020
|
---|
941 | #define RCC_APB1LPENR_TIM12LPEN 0x00000040
|
---|
942 | #define RCC_APB1LPENR_TIM13LPEN 0x00000080
|
---|
943 | #define RCC_APB1LPENR_TIM14LPEN 0x00000100
|
---|
944 | #define RCC_APB1LPENR_WWDGLPEN 0x00000800
|
---|
945 | #define RCC_APB1LPENR_SPI2LPEN 0x00004000
|
---|
946 | #define RCC_APB1LPENR_SPI3LPEN 0x00008000
|
---|
947 | #define RCC_APB1LPENR_USART2LPEN 0x00020000
|
---|
948 | #define RCC_APB1LPENR_USART3LPEN 0x00040000
|
---|
949 | #define RCC_APB1LPENR_UART4LPEN 0x00080000
|
---|
950 | #define RCC_APB1LPENR_UART5LPEN 0x00100000
|
---|
951 | #define RCC_APB1LPENR_I2C1LPEN 0x00200000
|
---|
952 | #define RCC_APB1LPENR_I2C2LPEN 0x00400000
|
---|
953 | #define RCC_APB1LPENR_I2C3LPEN 0x00800000
|
---|
954 | #define RCC_APB1LPENR_CAN1LPEN 0x02000000
|
---|
955 | #define RCC_APB1LPENR_CAN2LPEN 0x04000000
|
---|
956 | #define RCC_APB1LPENR_PWRLPEN 0x10000000
|
---|
957 | #define RCC_APB1LPENR_DACLPEN 0x20000000
|
---|
958 | #define TOFF_RCC_APB2LPENR 0x0064 /* (RW) RCC APB2 peripheral clock enable in low power mode register */
|
---|
959 | #define RCC_APB2LPENR_TIM1LPEN 0x00000001
|
---|
960 | #define RCC_APB2LPENR_TIM8LPEN 0x00000002
|
---|
961 | #define RCC_APB2LPENR_USART1LPEN 0x00000010
|
---|
962 | #define RCC_APB2LPENR_USART6LPEN 0x00000020
|
---|
963 | #define RCC_APB2LPENR_ADC1LPEN 0x00000100
|
---|
964 | #define RCC_APB2LPENR_ADC2PEN 0x00000200
|
---|
965 | #define RCC_APB2LPENR_ADC3LPEN 0x00000400
|
---|
966 | #define RCC_APB2LPENR_SDIOLPEN 0x00000800
|
---|
967 | #define RCC_APB2LPENR_SPI1LPEN 0x00001000
|
---|
968 | #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000
|
---|
969 | #define RCC_APB2LPENR_TIM9LPEN 0x00010000
|
---|
970 | #define RCC_APB2LPENR_TIM10LPEN 0x00020000
|
---|
971 | #define RCC_APB2LPENR_TIM11LPEN 0x00040000
|
---|
972 | #define TOFF_RCC_BDCR 0x0070 /* (RW) RCC Backup domain control register */
|
---|
973 | #define RCC_BDCR_LSEON 0x00000001
|
---|
974 | #define RCC_BDCR_LSERDY 0x00000002
|
---|
975 | #define RCC_BDCR_LSEBYP 0x00000004
|
---|
976 | #define RCC_BDCR_RTCSEL 0x00000300
|
---|
977 | #define RCC_BDCR_RTCSEL_0 0x00000100
|
---|
978 | #define RCC_BDCR_RTCSEL_1 0x00000200
|
---|
979 | #define RCC_BDCR_RTCEN 0x00008000
|
---|
980 | #define RCC_BDCR_BDRST 0x00010000
|
---|
981 | #define TOFF_RCC_CSR 0x0074 /* (RW) RCC clock control & status register */
|
---|
982 | #define RCC_CSR_LSION 0x00000001
|
---|
983 | #define RCC_CSR_LSIRDY 0x00000002
|
---|
984 | #define RCC_CSR_RMVF 0x01000000
|
---|
985 | #define RCC_CSR_BORRSTF 0x02000000
|
---|
986 | #define RCC_CSR_PADRSTF 0x04000000
|
---|
987 | #define RCC_CSR_PORRSTF 0x08000000
|
---|
988 | #define RCC_CSR_SFTRSTF 0x10000000
|
---|
989 | #define RCC_CSR_WDGRSTF 0x20000000
|
---|
990 | #define RCC_CSR_WWDGRSTF 0x40000000
|
---|
991 | #define RCC_CSR_LPWRRSTF 0x80000000
|
---|
992 | #define TOFF_RCC_SSCGR 0x0080 /* (RW) RCC spread spectrum clock generation register */
|
---|
993 | #define RCC_SSCGR_MODPER 0x00001FFF
|
---|
994 | #define RCC_SSCGR_INCSTEP 0x0FFFE000
|
---|
995 | #define RCC_SSCGR_SPREADSEL 0x40000000
|
---|
996 | #define RCC_SSCGR_SSCGEN 0x80000000
|
---|
997 | #define TOFF_RCC_PLLI2SCFGR 0x0084 /* (RW) RCC PLLI2S configuration register */
|
---|
998 | #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0
|
---|
999 | #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000
|
---|
1000 |
|
---|
1001 | /*
|
---|
1002 | * FLASH REGISTERS
|
---|
1003 | */
|
---|
1004 | #define TADR_FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
|
---|
1005 | #define TOFF_FLASH_ACR 0x0000 /* (RW) FLASH access control register */
|
---|
1006 | #define FLASH_ACR_LATENCY_0WS 0x00000000
|
---|
1007 | #define FLASH_ACR_LATENCY_1WS 0x00000001
|
---|
1008 | #define FLASH_ACR_LATENCY_2WS 0x00000002
|
---|
1009 | #define FLASH_ACR_LATENCY_3WS 0x00000003
|
---|
1010 | #define FLASH_ACR_LATENCY_4WS 0x00000004
|
---|
1011 | #define FLASH_ACR_LATENCY_5WS 0x00000005
|
---|
1012 | #define FLASH_ACR_LATENCY_6WS 0x00000006
|
---|
1013 | #define FLASH_ACR_LATENCY_7WS 0x00000007
|
---|
1014 | #define FLASH_ACR_PRFTEN 0x00000100
|
---|
1015 | #define FLASH_ACR_ICEN 0x00000200
|
---|
1016 | #define FLASH_ACR_DCEN 0x00000400
|
---|
1017 | #define FLASH_ACR_ICRST 0x00000800
|
---|
1018 | #define FLASH_ACR_DCRST 0x00001000
|
---|
1019 | #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00
|
---|
1020 | #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03
|
---|
1021 | #define TOFF_FLASH_KEYR 0x0004 /* (RW) FLASH key register */
|
---|
1022 | #define TOFF_FLASH_OPTKEYR 0x0008 /* (RW) FLASH option key register */
|
---|
1023 | #define TOFF_FLASH_SR 0x000C /* (RW) FLASH status register */
|
---|
1024 | #define FLASH_SR_EOP 0x00000001
|
---|
1025 | #define FLASH_SR_SOP 0x00000002
|
---|
1026 | #define FLASH_SR_WRPERR 0x00000010
|
---|
1027 | #define FLASH_SR_PGAERR 0x00000020
|
---|
1028 | #define FLASH_SR_PGPERR 0x00000040
|
---|
1029 | #define FLASH_SR_PGSERR 0x00000080
|
---|
1030 | #define FLASH_SR_BSY 0x00010000
|
---|
1031 | #define TOFF_FLASH_CR 0x0010 /* (RW) FLASH control register */
|
---|
1032 | #define FLASH_CR_PG 0x00000001
|
---|
1033 | #define FLASH_CR_SER 0x00000002
|
---|
1034 | #define FLASH_CR_MER 0x00000004
|
---|
1035 | #define FLASH_CR_SNB_0 0x00000008
|
---|
1036 | #define FLASH_CR_SNB_1 0x00000010
|
---|
1037 | #define FLASH_CR_SNB_2 0x00000020
|
---|
1038 | #define FLASH_CR_SNB_3 0x00000040
|
---|
1039 | #define FLASH_CR_PSIZE_0 0x00000100
|
---|
1040 | #define FLASH_CR_PSIZE_1 0x00000200
|
---|
1041 | #define FLASH_CR_STRT 0x00010000
|
---|
1042 | #define FLASH_CR_EOPIE 0x01000000
|
---|
1043 | #define FLASH_CR_LOCK 0x80000000
|
---|
1044 | #define TOFF_FLASH_OPTCR 0x0014 /* (RW) FLASH option control register */
|
---|
1045 | #define FLASH_OPTCR_OPTLOCK 0x00000001
|
---|
1046 | #define FLASH_OPTCR_OPTSTRT 0x00000002
|
---|
1047 | #define FLASH_OPTCR_BOR_LEV_0 0x00000004
|
---|
1048 | #define FLASH_OPTCR_BOR_LEV_1 0x00000008
|
---|
1049 | #define FLASH_OPTCR_BOR_LEV 0x0000000C
|
---|
1050 | #define FLASH_OPTCR_WDG_SW 0x00000020
|
---|
1051 | #define FLASH_OPTCR_nRST_STOP 0x00000040
|
---|
1052 | #define FLASH_OPTCR_nRST_STDBY 0x00000080
|
---|
1053 | #define FLASH_OPTCR_RDP_0 0x00000100
|
---|
1054 | #define FLASH_OPTCR_RDP_1 0x00000200
|
---|
1055 | #define FLASH_OPTCR_RDP_2 0x00000400
|
---|
1056 | #define FLASH_OPTCR_RDP_3 0x00000800
|
---|
1057 | #define FLASH_OPTCR_RDP_4 0x00001000
|
---|
1058 | #define FLASH_OPTCR_RDP_5 0x00002000
|
---|
1059 | #define FLASH_OPTCR_RDP_6 0x00004000
|
---|
1060 | #define FLASH_OPTCR_RDP_7 0x00008000
|
---|
1061 | #define FLASH_OPTCR_nWRP_0 0x00010000
|
---|
1062 | #define FLASH_OPTCR_nWRP_1 0x00020000
|
---|
1063 | #define FLASH_OPTCR_nWRP_2 0x00040000
|
---|
1064 | #define FLASH_OPTCR_nWRP_3 0x00080000
|
---|
1065 | #define FLASH_OPTCR_nWRP_4 0x00100000
|
---|
1066 | #define FLASH_OPTCR_nWRP_5 0x00200000
|
---|
1067 | #define FLASH_OPTCR_nWRP_6 0x00400000
|
---|
1068 | #define FLASH_OPTCR_nWRP_7 0x00800000
|
---|
1069 | #define FLASH_OPTCR_nWRP_8 0x01000000
|
---|
1070 | #define FLASH_OPTCR_nWRP_9 0x02000000
|
---|
1071 | #define FLASH_OPTCR_nWRP_10 0x04000000
|
---|
1072 | #define FLASH_OPTCR_nWRP_11 0x08000000
|
---|
1073 |
|
---|
1074 | /*
|
---|
1075 | * DMA CONTROLLER
|
---|
1076 | */
|
---|
1077 | #define TADR_DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
|
---|
1078 | #define TADR_DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
|
---|
1079 | #define TOFF_DMAI_LISR 0x0000 /* (RW) DMA low interrupt status register */
|
---|
1080 | #define TOFF_DMAI_HISR 0x0004 /* (RW) DMA high interrupt status register */
|
---|
1081 | #define TOFF_DMAI_LIFCR 0x0008 /* (RW) DMA low interrupt flag clear register */
|
---|
1082 | #define TOFF_DMAI_HIFCR 0x000C /* (RW) DMA high interrupt flag clear register */
|
---|
1083 |
|
---|
1084 | #define TADR_DMA1_STM0_BASE (DMA1_BASE + 0x010)
|
---|
1085 | #define TADR_DMA1_STM1_BASE (DMA1_BASE + 0x028)
|
---|
1086 | #define TADR_DMA1_STM2_BASE (DMA1_BASE + 0x040)
|
---|
1087 | #define TADR_DMA1_STM3_BASE (DMA1_BASE + 0x058)
|
---|
1088 | #define TADR_DMA1_STM4_BASE (DMA1_BASE + 0x070)
|
---|
1089 | #define TADR_DMA1_STM5_BASE (DMA1_BASE + 0x088)
|
---|
1090 | #define TADR_DMA1_STM6_BASE (DMA1_BASE + 0x0A0)
|
---|
1091 | #define TADR_DMA1_STM7_BASE (DMA1_BASE + 0x0B8)
|
---|
1092 | #define TADR_DMA2_STM0_BASE (DMA2_BASE + 0x010)
|
---|
1093 | #define TADR_DMA2_STM1_BASE (DMA2_BASE + 0x028)
|
---|
1094 | #define TADR_DMA2_STM2_BASE (DMA2_BASE + 0x040)
|
---|
1095 | #define TADR_DMA2_STM3_BASE (DMA2_BASE + 0x058)
|
---|
1096 | #define TADR_DMA2_STM4_BASE (DMA2_BASE + 0x070)
|
---|
1097 | #define TADR_DMA2_STM5_BASE (DMA2_BASE + 0x088)
|
---|
1098 | #define TADR_DMA2_STM6_BASE (DMA2_BASE + 0x0A0)
|
---|
1099 | #define TADR_DMA2_STM7_BASE (DMA2_BASE + 0x0B8)
|
---|
1100 | #define TOFF_DMAS_CR 0x0000 /* (RW) DMA stream x configuration register */
|
---|
1101 | #define TOFF_DMAS_NDTR 0x0004 /* (RW) DMA stream x number of data register */
|
---|
1102 | #define TOFF_DMAS_PAR 0x0008 /* (RW) DMA stream x peripheral address register */
|
---|
1103 | #define TOFF_DMAS_M0AR 0x000C /* (RW) DMA stream x memory 0 address register */
|
---|
1104 | #define TOFF_DMAS_M1AR 0x0010 /* (RW) DMA stream x memory 1 address register */
|
---|
1105 | #define TOFF_DMAS_FCR 0x0014 /* (RW) DMA stream x FIFO control register */
|
---|
1106 |
|
---|
1107 |
|
---|
1108 |
|
---|
1109 |
|
---|
1110 | #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
|
---|
1111 | #define ETH_MAC_BASE (ETH_BASE)
|
---|
1112 | #define ETH_MMC_BASE (ETH_BASE + 0x0100)
|
---|
1113 | #define ETH_PTP_BASE (ETH_BASE + 0x0700)
|
---|
1114 | #define ETH_DMA_BASE (ETH_BASE + 0x1000)
|
---|
1115 |
|
---|
1116 |
|
---|
1117 |
|
---|
1118 | /*
|
---|
1119 | * DCMI
|
---|
1120 | */
|
---|
1121 | #define TADR_DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
|
---|
1122 | #define TOFF_DCMI_CR 0x0000 /* (RW) DCMI control register 1 */
|
---|
1123 | #define TOFF_DCMI_SR 0x0004 /* (R) DCMI status register */
|
---|
1124 | #define TOFF_DCMI_RISR 0x0008 /* (R) DCMI raw interrupt status register */
|
---|
1125 | #define TOFF_DCMI_IER 0x000C /* (RW) DCMI interrupt enable register */
|
---|
1126 | #define TOFF_DCMI_MISR 0x0010 /* (RW) DCMI masked interrupt status register */
|
---|
1127 | #define TOFF_DCMI_ICR 0x0014 /* (RW) DCMI interrupt clear register */
|
---|
1128 | #define TOFF_DCMI_ESCR 0x0018 /* (RW) DCMI embedded synchronization code register */
|
---|
1129 | #define TOFF_DCMI_ESUR 0x001C /* (RW) DCMI embedded synchronization unmask register */
|
---|
1130 | #define TOFF_DCMI_CWSTRTR 0x0020 /* (RW) DCMI crop window start */
|
---|
1131 | #define TOFF_DCMI_CWSIZER 0x0024 /* (RW) DCMI crop window size */
|
---|
1132 | #define TOFF_DCMI_DR 0x0028 /* (RW) DCMI data register */
|
---|
1133 |
|
---|
1134 | /*
|
---|
1135 | * CRYPTO PROCESSER
|
---|
1136 | */
|
---|
1137 | #define TADR_CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
|
---|
1138 | #define TOFF_CRYP_CR 0x0000 /* (RW) CRYP control register */
|
---|
1139 | #define TOFF_CRYP_SR 0x0004 /* (R) CRYP status register */
|
---|
1140 | #define TOFF_CRYP_DR 0x0008 /* (RW) CRYP data input register */
|
---|
1141 | #define TOFF_CRYP_DOUT 0x000C /* (RW) CRYP data output register */
|
---|
1142 | #define TOFF_CRYP_DMACR 0x0010 /* (RW) CRYP DMA control register */
|
---|
1143 | #define TOFF_CRYP_IMSCR 0x0014 /* (RW) CRYP interrupt mask set/clear register */
|
---|
1144 | #define TOFF_CRYP_RISR 0x0018 /* (RW) CRYP raw interrupt status register */
|
---|
1145 | #define TOFF_CRYP_MISR 0x001C /* (RW) CRYP masked interrupt status register */
|
---|
1146 | #define TOFF_CRYP_K0LR 0x0020 /* (RW) CRYP key left register 0 */
|
---|
1147 | #define TOFF_CRYP_K0RR 0x0024 /* (RW) CRYP key right register 0 */
|
---|
1148 | #define TOFF_CRYP_K1LR 0x0028 /* (RW) CRYP key left register 1 */
|
---|
1149 | #define TOFF_CRYP_K1RR 0x002C /* (RW) CRYP key right register 1 */
|
---|
1150 | #define TOFF_CRYP_K2LR 0x0030 /* (RW) CRYP key left register 2 */
|
---|
1151 | #define TOFF_CRYP_K2RR 0x0034 /* (RW) CRYP key right register 2 */
|
---|
1152 | #define TOFF_CRYP_K3LR 0x0038 /* (RW) CRYP key left register 3 */
|
---|
1153 | #define TOFF_CRYP_K3RR 0x003C /* (RW) CRYP key right register 3 */
|
---|
1154 | #define TOFF_CRYP_IV0LR 0x0040 /* (RW) CRYP initialization vector left-word register 0 */
|
---|
1155 | #define TOFF_CRYP_IV0RR 0x0044 /* (RW) CRYP initialization vector right-word register 0 */
|
---|
1156 | #define TOFF_CRYP_IV1LR 0x0048 /* (RW) CRYP initialization vector left-word register 1 */
|
---|
1157 | #define TOFF_CRYP_IV1RR 0x004C /* (RW) CRYP initialization vector right-word register 1 */
|
---|
1158 |
|
---|
1159 | /*
|
---|
1160 | * HASH
|
---|
1161 | */
|
---|
1162 | #define TADR_HASH_BASE (AHB2PERIPH_BASE + 0x60400)
|
---|
1163 | #define TOFF_HASH_CR 0x0000 /* (RW) HASH control register */
|
---|
1164 | #define TOFF_HASH_DIN 0x0004 /* (RW) HASH data input register */
|
---|
1165 | #define TOFF_HASH_STR 0x0008 /* (RW) HASH start register */
|
---|
1166 | #define TOFF_HASH_HR0 0x000C /* (RW) HASH digest registers 0 */
|
---|
1167 | #define TOFF_HASH_HR1 0x0010 /* (RW) HASH digest registers 1 */
|
---|
1168 | #define TOFF_HASH_HR2 0x0014 /* (RW) HASH digest registers 2 */
|
---|
1169 | #define TOFF_HASH_HR3 0x0018 /* (RW) HASH digest registers 3 */
|
---|
1170 | #define TOFF_HASH_HR4 0x001C /* (RW) HASH digest registers 4 */
|
---|
1171 | #define TOFF_HASH_IMR 0x0020 /* (RW) HASH interrupt enable register */
|
---|
1172 | #define TOFF_HASH_SR 0x0024 /* (R) HASH status register */
|
---|
1173 | #define TOFF_HASH_CSR0 0x00F8 /* (RW) HASH context swap registers 0 */
|
---|
1174 | #define TOFF_HASH_CSR1 0x00FC /* (RW) HASH context swap registers 1 */
|
---|
1175 | #define TOFF_HASH_CSR2 0x0100 /* (RW) HASH context swap registers 2 */
|
---|
1176 | #define TOFF_HASH_CSR3 0x0104 /* (RW) HASH context swap registers 3 */
|
---|
1177 | #define TOFF_HASH_CSR4 0x0108 /* (RW) HASH context swap registers 4 */
|
---|
1178 | #define TOFF_HASH_CSR5 0x010C /* (RW) HASH context swap registers 5 */
|
---|
1179 | #define TOFF_HASH_CSR6 0x0110 /* (RW) HASH context swap registers 6 */
|
---|
1180 | #define TOFF_HASH_CSR7 0x0114 /* (RW) HASH context swap registers 7 */
|
---|
1181 | #define TOFF_HASH_CSR8 0x0118 /* (RW) HASH context swap registers 8 */
|
---|
1182 | #define TOFF_HASH_CSR9 0x011C /* (RW) HASH context swap registers 9 */
|
---|
1183 | #define TOFF_HASH_CSR10 0x0120 /* (RW) HASH context swap registers 10 */
|
---|
1184 | #define TOFF_HASH_CSR11 0x0124 /* (RW) HASH context swap registers 11 */
|
---|
1185 | #define TOFF_HASH_CSR12 0x0128 /* (RW) HASH context swap registers 12 */
|
---|
1186 | #define TOFF_HASH_CSR13 0x012C /* (RW) HASH context swap registers 13 */
|
---|
1187 | #define TOFF_HASH_CSR14 0x0130 /* (RW) HASH context swap registers 14 */
|
---|
1188 | #define TOFF_HASH_CSR15 0x0134 /* (RW) HASH context swap registers 15 */
|
---|
1189 | #define TOFF_HASH_CSR16 0x0138 /* (RW) HASH context swap registers 16 */
|
---|
1190 | #define TOFF_HASH_CSR17 0x013C /* (RW) HASH context swap registers 17 */
|
---|
1191 | #define TOFF_HASH_CSR18 0x0140 /* (RW) HASH context swap registers 18 */
|
---|
1192 | #define TOFF_HASH_CSR19 0x0144 /* (RW) HASH context swap registers 19 */
|
---|
1193 | #define TOFF_HASH_CSR20 0x0148 /* (RW) HASH context swap registers 20 */
|
---|
1194 | #define TOFF_HASH_CSR21 0x014C /* (RW) HASH context swap registers 21 */
|
---|
1195 | #define TOFF_HASH_CSR22 0x0150 /* (RW) HASH context swap registers 22 */
|
---|
1196 | #define TOFF_HASH_CSR23 0x0154 /* (RW) HASH context swap registers 23 */
|
---|
1197 | #define TOFF_HASH_CSR24 0x0158 /* (RW) HASH context swap registers 24 */
|
---|
1198 | #define TOFF_HASH_CSR25 0x015C /* (RW) HASH context swap registers 25 */
|
---|
1199 | #define TOFF_HASH_CSR26 0x0160 /* (RW) HASH context swap registers 26 */
|
---|
1200 | #define TOFF_HASH_CSR27 0x0164 /* (RW) HASH context swap registers 27 */
|
---|
1201 | #define TOFF_HASH_CSR28 0x0168 /* (RW) HASH context swap registers 28 */
|
---|
1202 | #define TOFF_HASH_CSR29 0x016C /* (RW) HASH context swap registers 29 */
|
---|
1203 | #define TOFF_HASH_CSR30 0x0170 /* (RW) HASH context swap registers 30 */
|
---|
1204 | #define TOFF_HASH_CSR31 0x0174 /* (RW) HASH context swap registers 31 */
|
---|
1205 | #define TOFF_HASH_CSR32 0x0178 /* (RW) HASH context swap registers 32 */
|
---|
1206 | #define TOFF_HASH_CSR33 0x017C /* (RW) HASH context swap registers 33 */
|
---|
1207 | #define TOFF_HASH_CSR34 0x0180 /* (RW) HASH context swap registers 34 */
|
---|
1208 | #define TOFF_HASH_CSR35 0x0184 /* (RW) HASH context swap registers 35 */
|
---|
1209 | #define TOFF_HASH_CSR36 0x0188 /* (RW) HASH context swap registers 36 */
|
---|
1210 | #define TOFF_HASH_CSR37 0x018C /* (RW) HASH context swap registers 37 */
|
---|
1211 | #define TOFF_HASH_CSR38 0x0190 /* (RW) HASH context swap registers 38 */
|
---|
1212 | #define TOFF_HASH_CSR39 0x0194 /* (RW) HASH context swap registers 39 */
|
---|
1213 | #define TOFF_HASH_CSR40 0x0198 /* (RW) HASH context swap registers 40 */
|
---|
1214 | #define TOFF_HASH_CSR41 0x019C /* (RW) HASH context swap registers 41 */
|
---|
1215 | #define TOFF_HASH_CSR42 0x01A0 /* (RW) HASH context swap registers 42 */
|
---|
1216 | #define TOFF_HASH_CSR43 0x01A4 /* (RW) HASH context swap registers 43 */
|
---|
1217 | #define TOFF_HASH_CSR44 0x01A8 /* (RW) HASH context swap registers 44 */
|
---|
1218 | #define TOFF_HASH_CSR45 0x01AC /* (RW) HASH context swap registers 45 */
|
---|
1219 | #define TOFF_HASH_CSR46 0x01B0 /* (RW) HASH context swap registers 46 */
|
---|
1220 | #define TOFF_HASH_CSR47 0x01B4 /* (RW) HASH context swap registers 47 */
|
---|
1221 | #define TOFF_HASH_CSR48 0x01B8 /* (RW) HASH context swap registers 48 */
|
---|
1222 | #define TOFF_HASH_CSR49 0x01BC /* (RW) HASH context swap registers 49 */
|
---|
1223 | #define TOFF_HASH_CSR50 0x01C0 /* (RW) HASH context swap registers 50 */
|
---|
1224 |
|
---|
1225 | /*
|
---|
1226 | * RNG
|
---|
1227 | */
|
---|
1228 | #define TADR_RNG_BASE (AHB2PERIPH_BASE + 0x60800)
|
---|
1229 | #define TOFF_RNG_CR 0x0000 /* (RW) RNG control register */
|
---|
1230 | #define TOFF_RNG_SR 0x0004 /* (RW) RNG status register */
|
---|
1231 | #define TOFF_RNG_DR 0x0008 /* (RW) RNG data register */
|
---|
1232 |
|
---|
1233 | /*
|
---|
1234 | * FLEXIBLE STATIC MEMORY
|
---|
1235 | */
|
---|
1236 | #define TADR_FSMC_R_BASE (FSMC_R_BASE + 0x0000)
|
---|
1237 |
|
---|
1238 | /*
|
---|
1239 | * FLEXIBLE STATIC MEMORY CONTROLLER
|
---|
1240 | */
|
---|
1241 | #define TOFF_FSMC_R_BTCR0 0x0000 /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 0 */
|
---|
1242 | #define TOFF_FSMC_R_BTCR1 0x0004 /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 1 */
|
---|
1243 | #define TOFF_FSMC_R_BTCR2 0x0008 /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 2 */
|
---|
1244 | #define TOFF_FSMC_R_BTCR3 0x000C /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 3 */
|
---|
1245 | #define TOFF_FSMC_R_BTCR4 0x0010 /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 4 */
|
---|
1246 | #define TOFF_FSMC_R_BTCR5 0x0014 /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 5 */
|
---|
1247 | #define TOFF_FSMC_R_BTCR6 0x0018 /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 6 */
|
---|
1248 | #define TOFF_FSMC_R_BTCR7 0x001C /* (RW) NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR) 7 */
|
---|
1249 |
|
---|
1250 | /*
|
---|
1251 | * FLEXIBLE STATIC MEMORY CONTROLLER BANK1E
|
---|
1252 | */
|
---|
1253 | #define TOFF_FSMC_R_BWTR0 0x0104 /* (RW) NOR/PSRAM write timing registers 0 */
|
---|
1254 | #define TOFF_FSMC_R_BWTR1 0x0108 /* (RW) NOR/PSRAM write timing registers 1 */
|
---|
1255 | #define TOFF_FSMC_R_BWTR2 0x010C /* (RW) NOR/PSRAM write timing registers 2 */
|
---|
1256 | #define TOFF_FSMC_R_BWTR3 0x0110 /* (RW) NOR/PSRAM write timing registers 3 */
|
---|
1257 | #define TOFF_FSMC_R_BWTR4 0x0114 /* (RW) NOR/PSRAM write timing registers 4 */
|
---|
1258 | #define TOFF_FSMC_R_BWTR5 0x0118 /* (RW) NOR/PSRAM write timing registers 5 */
|
---|
1259 | #define TOFF_FSMC_R_BWTR6 0x011C /* (RW) NOR/PSRAM write timing registers 6 */
|
---|
1260 |
|
---|
1261 | /*
|
---|
1262 | * FLEXIBLE STATIC MEMORY CONTROLLER BANK2
|
---|
1263 | */
|
---|
1264 | #define TOFF_FSMC_R_PCR2 0x0060 /* (RW) NAND Flash control register 2 */
|
---|
1265 | #define TOFF_FSMC_R_SR2 0x0064 /* (RW) NAND Flash FIFO status and interrupt register 2 */
|
---|
1266 | #define TOFF_FSMC_R_PMEM2 0x0068 /* (RW) NAND Flash Common memory space timing register 2 */
|
---|
1267 | #define TOFF_FSMC_R_PATT2 0x006C /* (RW) NAND Flash Attribute memory space timing register 2 */
|
---|
1268 | #define TOFF_FSMC_R_ECCR2 0x0074 /* (RW) NAND Flash ECC result registers 2 */
|
---|
1269 |
|
---|
1270 | /*
|
---|
1271 | * FLEXIBLE STATIC MEMORY CONTROLLER BANK3
|
---|
1272 | */
|
---|
1273 | #define TOFF_FSMC_R_PCR3 0x0080 /* (RW) NAND Flash control register 3 */
|
---|
1274 | #define TOFF_FSMC_R_SR3 0x0084 /* (RW) NAND Flash FIFO status and interrupt register 3 */
|
---|
1275 | #define TOFF_FSMC_R_PMEM3 0x0088 /* (RW) NAND Flash Common memory space timing register 3 */
|
---|
1276 | #define TOFF_FSMC_R_PATT3 0x008C /* (RW) NAND Flash Attribute memory space timing register 3 */
|
---|
1277 | #define TOFF_FSMC_R_ECCR3 0x0094 /* (RW) NAND Flash ECC result registers 3 */
|
---|
1278 |
|
---|
1279 | /*
|
---|
1280 | * FLEXIBLE STATIC MEMORY CONTROLLER BANK4
|
---|
1281 | */
|
---|
1282 | #define TOFF_FSMC_R_PCR4 0x00A0 /* (RW) PC Card control register 4 */
|
---|
1283 | #define TOFF_FSMC_R_SR4 0x00A4 /* (RW) PC Card FIFO status and interrupt register 4 */
|
---|
1284 | #define TOFF_FSMC_R_PMEM4 0x00A8 /* (RW) PC Card Common memory space timing register 4 */
|
---|
1285 | #define TOFF_FSMC_R_PATT4 0x00AC /* (RW) PC Card Attribute memory space timing register 4 */
|
---|
1286 | #define TOFF_FSMC_R_PIO4 0x00B0 /* (RW) PC Card I/O space timing register 4 */
|
---|
1287 |
|
---|
1288 | /*
|
---|
1289 | * DEBUG MCU
|
---|
1290 | */
|
---|
1291 | #define TADR_DBGMCU_BASE 0xE0042000
|
---|
1292 | #define TOFF_DBGMCU_IDCODE 0x0000 /* (RW) MCU device ID code */
|
---|
1293 | #define TOFF_DBGMCU_CR 0x0004 /* (RW) Debug MCU configuration register */
|
---|
1294 | #define TOFF_DBGMCU_APB1FZ 0x0008 /* (RW) Debug MCU APB1 freeze register */
|
---|
1295 | #define TOFF_DBGMCU_APB2FZ 0x000C /* (RW) Debug MCU APB2 freeze register */
|
---|
1296 |
|
---|
1297 |
|
---|
1298 | #endif /* _STM32F4XX_H_ */
|
---|
1299 |
|
---|