1 | /*
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2 | * TOPPERS/ASP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Just Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2015 by 3rd Designing Center
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7 | * Imageing System Development Division RICOH COMPANY, LTD.
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8 | *
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9 | * ä¸è¨èä½æ¨©è
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10 | ã¯ï¼ä»¥ä¸ã® (1)ï½(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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11 | * ã«ãã£ã¦å
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12 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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13 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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14 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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15 | å¸ï¼ä»¥ä¸ï¼
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16 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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17 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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18 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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19 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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20 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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21 | * ç¨ã§ããå½¢ã§åé
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22 | å¸ããå ´åã«ã¯ï¼åé
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23 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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24 | * è
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25 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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26 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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27 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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28 | * ç¨ã§ããªãå½¢ã§åé
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29 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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30 | * ã¨ï¼
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31 | * (a) åé
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32 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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33 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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34 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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35 | * (b) åé
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36 | å¸ã®å½¢æ
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37 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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38 | * å ±åãããã¨ï¼
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39 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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40 | * 害ãããï¼ä¸è¨èä½æ¨©è
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41 | ããã³TOPPERSããã¸ã§ã¯ããå
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42 | 責ãããã¨ï¼
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43 | *
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44 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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45 | ã
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46 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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47 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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48 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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49 | *
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50 | * @(#) $Id: cmsis.h,v 1.1 2015/07/27 22:56:07 roi Exp $
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51 | */
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52 |
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53 | #ifndef _CMSIS_F4_H_
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54 | #define _CMSIS_F4_H_
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55 |
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56 | #define __NVIC_PRIO_BITS 4 /* STM32F4XX uses 4 Bits for the Priority Levels */
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57 |
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58 | /* Memory mapping of Cortex-M4 Hardware */
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59 | #define TADR_ITM_BASE (0xE0000000UL) /* ITM Base Address */
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60 | #define TOFF_ITM_PORT 0x0000 /* (W) ITM Stimulus Port Registers */
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61 | #define TOFF_ITM_TER 0x0E00 /* (RW) ITM Trace Enable Register */
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62 | #define TOFF_ITM_TPR 0x0E40 /* (RW) ITM Trace Privilege Register */
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63 | #define TOFF_ITM_TCR 0x0E80 /* (RW) ITM Trace Control Register */
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64 | #define TADR_SCS_BASE (0xE000E000UL) /* System Control Space Base Address */
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65 | #define TOFF_SCS_ICTR 0x0004 /* (R) Interrupt Controller Type Register */
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66 | #define TOFF_SCS_ACTLR 0x0008 /* (RW) Auxiliary Control Register */
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67 | #define TADR_COREDEBUG_BASE (0xE000EDF0UL) /* Core Debug Base Address */
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68 | #define TADR_SYSTICK_BASE (TADR_SCS_BASE+0x0010UL) /* SysTick Base Address */
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69 | #define TOFF_SYSTICK_CTRL 0x0000 /* (RW) SysTick Control and Status Register */
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70 | #define TOFF_SYSTICK_LOAD 0x0004 /* (RW) SysTick Reload Value Register */
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71 | #define TOFF_SYSTICK_VAL 0x0008 /* (RW) SysTick Current Value Register */
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72 | #define TOFF_SYSTICK_CALIB 0x000C /* (R) SysTick Calibration Register */
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73 | #define TADR_NVIC_BASE (TADR_SCS_BASE+0x0100UL) /* NVIC Base Address */
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74 | #define TOFF_NVIC_ISER 0x0000 /* (RW) Interrupt Set Enable Register */
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75 | #define TOFF_NVIC_ICER 0x0080 /* (RW) Interrupt Clear Enable Register */
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76 | #define TOFF_NVIC_ISPR 0x0100 /* (RW) Interrupt Set Pending Register */
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77 | #define TOFF_NVIC_ICPR 0x0180 /* (RW) Interrupt Clear Pending Register */
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78 | #define TOFF_NVIC_IABR 0x0200 /* (RW) Interrupt Active bit Register */
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79 | #define TOFF_NVIC_IP 0x0300 /* (RW) Interrupt Priority Register (8Bit wide) */
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80 | #define TOFF_NVIC_STIR 0x0E00 /* (W) Software Trigger Interrupt Register */
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81 | #define TADR_SCB_BASE (TADR_SCS_BASE+0x0D00UL) /* System Control Block Base Address */
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82 | #define TOFF_SCB_CPUID 0x0000 /* (R) CPUID Base Register */
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83 | #define TOFF_SCB_ICSR 0x0004 /* (RW) Interrupt Control and State Register */
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84 | #define TOFF_SCB_VTOR 0x0008 /* (RW) Vector Table Offset Register */
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85 | #define TOFF_SCB_AIRCR 0x000C /* (RW) Application Interrupt and Reset Control Register */
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86 | #define TOFF_SCB_SCR 0x0010 /* (RW) System Control Register */
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87 | #define TOFF_SCB_CCR 0x0014 /* (RW) Configuration Control Register */
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88 | #define TOFF_SCB_SHP4 0x0018 /* (RW-8) System Handlers Priority Registers 4 */
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89 | #define TOFF_SCB_SHP5 0x0019 /* (RW-8) System Handlers Priority Registers 5 */
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90 | #define TOFF_SCB_SHP6 0x001A /* (RW-8) System Handlers Priority Registers 6 */
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91 | #define TOFF_SCB_SHP7 0x001B /* (RW-8) System Handlers Priority Registers 7 */
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92 | #define TOFF_SCB_SHP8 0x001C /* (RW-8) System Handlers Priority Registers 8 */
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93 | #define TOFF_SCB_SHP9 0x001D /* (RW-8) System Handlers Priority Registers 9 */
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94 | #define TOFF_SCB_SHP10 0x001E /* (RW-8) System Handlers Priority Registers 10 */
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95 | #define TOFF_SCB_SHP11 0x001F /* (RW-8) System Handlers Priority Registers 11 */
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96 | #define TOFF_SCB_SHP12 0x0020 /* (RW-8) System Handlers Priority Registers 12 */
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97 | #define TOFF_SCB_SHP13 0x0021 /* (RW-8) System Handlers Priority Registers 13 */
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98 | #define TOFF_SCB_SHP14 0x0022 /* (RW-8) System Handlers Priority Registers 14 */
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99 | #define TOFF_SCB_SHP15 0x0023 /* (RW-8) System Handlers Priority Registers 15 */
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100 | #define TOFF_SCB_SHCSR 0x0024 /* (RW) System Handler Control and State Register */
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101 | #define TOFF_SCB_CFSR 0x0028 /* (RW) Configurable Fault Status Register */
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102 | #define TOFF_SCB_HFSR 0x002C /* (RW) HardFault Status Register */
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103 | #define TOFF_SCB_DFSR 0x0030 /* (RW) Debug Fault Status Register */
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104 | #define TOFF_SCB_MMFAR 0x0034 /* (RW) MemManage Fault Address Register */
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105 | #define TOFF_SCB_BFAR 0x0038 /* (RW) BusFault Address Register */
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106 | #define TOFF_SCB_AFSR 0x003C /* (RW) Auxiliary Fault Status Register */
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107 | #define TOFF_SCB_PFR0 0x0040 /* (R) Processor Feature Register 0 */
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108 | #define TOFF_SCB_PFR1 0x0044 /* (R) Processor Feature Register 1 */
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109 | #define TOFF_SCB_DFR 0x0048 /* (R) Debug Feature Register */
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110 | #define TOFF_SCB_ADR 0x004C /* (R) Auxiliary Feature Register */
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111 | #define TOFF_SCB_MMFR0 0x0050 /* (R) Memory Model Feature Register 0 */
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112 | #define TOFF_SCB_MMFR1 0x0054 /* (R) Memory Model Feature Register 1 */
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113 | #define TOFF_SCB_MMFR2 0x0058 /* (R) Memory Model Feature Register 2 */
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114 | #define TOFF_SCB_MMFR3 0x005C /* (R) Memory Model Feature Register 3 */
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115 | #define TOFF_SCB_ISAR0 0x0060 /* (R) Instruction Set Attributes Register 0 */
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116 | #define TOFF_SCB_ISAR1 0x0064 /* (R) Instruction Set Attributes Register 1 */
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117 | #define TOFF_SCB_ISAR2 0x0068 /* (R) Instruction Set Attributes Register 2 */
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118 | #define TOFF_SCB_ISAR3 0x006C /* (R) Instruction Set Attributes Register 3 */
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119 | #define TOFF_SCB_ISAR4 0x0070 /* (R) Instruction Set Attributes Register 4 */
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120 | #define TOFF_SCB_CPACR 0x0088 /* (RW) Coprocessor Access Control Register */
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121 |
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122 | #endif /* _CMSIS_F4_H_ */
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123 |
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